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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for AMBA serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright 1999 ARM Limited | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 8 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
1da177e4 LT |
24 | * This is a generic driver for ARM AMBA-type serial ports. They |
25 | * have a lot of 16550-like features, but are not register compatible. | |
26 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
27 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
28 | * required, these have to be supplied via some other means (eg, GPIO) | |
29 | * and hooked into this driver. | |
30 | */ | |
1da177e4 | 31 | |
cb06ff10 | 32 | |
1da177e4 LT |
33 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
34 | #define SUPPORT_SYSRQ | |
35 | #endif | |
36 | ||
37 | #include <linux/module.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/console.h> | |
41 | #include <linux/sysrq.h> | |
42 | #include <linux/device.h> | |
43 | #include <linux/tty.h> | |
44 | #include <linux/tty_flip.h> | |
45 | #include <linux/serial_core.h> | |
46 | #include <linux/serial.h> | |
a62c80e5 RK |
47 | #include <linux/amba/bus.h> |
48 | #include <linux/amba/serial.h> | |
f8ce2547 | 49 | #include <linux/clk.h> |
5a0e3ad6 | 50 | #include <linux/slab.h> |
68b65f73 RK |
51 | #include <linux/dmaengine.h> |
52 | #include <linux/dma-mapping.h> | |
53 | #include <linux/scatterlist.h> | |
c16d51a3 | 54 | #include <linux/delay.h> |
258aea76 | 55 | #include <linux/types.h> |
32614aad ML |
56 | #include <linux/of.h> |
57 | #include <linux/of_device.h> | |
258e0551 | 58 | #include <linux/pinctrl/consumer.h> |
cb70706c | 59 | #include <linux/sizes.h> |
de609582 | 60 | #include <linux/io.h> |
1da177e4 LT |
61 | |
62 | #define UART_NR 14 | |
63 | ||
64 | #define SERIAL_AMBA_MAJOR 204 | |
65 | #define SERIAL_AMBA_MINOR 64 | |
66 | #define SERIAL_AMBA_NR UART_NR | |
67 | ||
68 | #define AMBA_ISR_PASS_LIMIT 256 | |
69 | ||
b63d4f0f RK |
70 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
71 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 72 | |
5926a295 AR |
73 | /* There is by now at least one vendor with differing details, so handle it */ |
74 | struct vendor_data { | |
75 | unsigned int ifls; | |
ec489aa8 LW |
76 | unsigned int lcrh_tx; |
77 | unsigned int lcrh_rx; | |
ac3e3fb4 | 78 | bool oversampling; |
38d62436 | 79 | bool dma_threshold; |
4fd0690b | 80 | bool cts_event_workaround; |
78506f22 | 81 | |
ea33640a | 82 | unsigned int (*get_fifosize)(struct amba_device *dev); |
5926a295 AR |
83 | }; |
84 | ||
ea33640a | 85 | static unsigned int get_fifosize_arm(struct amba_device *dev) |
78506f22 | 86 | { |
ea33640a | 87 | return amba_rev(dev) < 3 ? 16 : 32; |
78506f22 JK |
88 | } |
89 | ||
5926a295 AR |
90 | static struct vendor_data vendor_arm = { |
91 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
ec489aa8 LW |
92 | .lcrh_tx = UART011_LCRH, |
93 | .lcrh_rx = UART011_LCRH, | |
ac3e3fb4 | 94 | .oversampling = false, |
38d62436 | 95 | .dma_threshold = false, |
4fd0690b | 96 | .cts_event_workaround = false, |
78506f22 | 97 | .get_fifosize = get_fifosize_arm, |
5926a295 AR |
98 | }; |
99 | ||
ea33640a | 100 | static unsigned int get_fifosize_st(struct amba_device *dev) |
78506f22 JK |
101 | { |
102 | return 64; | |
103 | } | |
104 | ||
5926a295 AR |
105 | static struct vendor_data vendor_st = { |
106 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, | |
ec489aa8 LW |
107 | .lcrh_tx = ST_UART011_LCRH_TX, |
108 | .lcrh_rx = ST_UART011_LCRH_RX, | |
ac3e3fb4 | 109 | .oversampling = true, |
38d62436 | 110 | .dma_threshold = true, |
4fd0690b | 111 | .cts_event_workaround = true, |
78506f22 | 112 | .get_fifosize = get_fifosize_st, |
1da177e4 LT |
113 | }; |
114 | ||
68b65f73 | 115 | /* Deals with DMA transactions */ |
ead76f32 LW |
116 | |
117 | struct pl011_sgbuf { | |
118 | struct scatterlist sg; | |
119 | char *buf; | |
120 | }; | |
121 | ||
122 | struct pl011_dmarx_data { | |
123 | struct dma_chan *chan; | |
124 | struct completion complete; | |
125 | bool use_buf_b; | |
126 | struct pl011_sgbuf sgbuf_a; | |
127 | struct pl011_sgbuf sgbuf_b; | |
128 | dma_cookie_t cookie; | |
129 | bool running; | |
cb06ff10 CM |
130 | struct timer_list timer; |
131 | unsigned int last_residue; | |
132 | unsigned long last_jiffies; | |
133 | bool auto_poll_rate; | |
134 | unsigned int poll_rate; | |
135 | unsigned int poll_timeout; | |
ead76f32 LW |
136 | }; |
137 | ||
68b65f73 RK |
138 | struct pl011_dmatx_data { |
139 | struct dma_chan *chan; | |
140 | struct scatterlist sg; | |
141 | char *buf; | |
142 | bool queued; | |
143 | }; | |
144 | ||
c19f12b5 RK |
145 | /* |
146 | * We wrap our port structure around the generic uart_port. | |
147 | */ | |
148 | struct uart_amba_port { | |
149 | struct uart_port port; | |
150 | struct clk *clk; | |
151 | const struct vendor_data *vendor; | |
68b65f73 | 152 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
153 | unsigned int im; /* interrupt mask */ |
154 | unsigned int old_status; | |
ffca2b11 | 155 | unsigned int fifosize; /* vendor-specific */ |
c19f12b5 RK |
156 | unsigned int lcrh_tx; /* vendor-specific */ |
157 | unsigned int lcrh_rx; /* vendor-specific */ | |
d8d8ffa4 | 158 | unsigned int old_cr; /* state during shutdown */ |
c19f12b5 RK |
159 | bool autorts; |
160 | char type[12]; | |
68b65f73 RK |
161 | #ifdef CONFIG_DMA_ENGINE |
162 | /* DMA stuff */ | |
ead76f32 LW |
163 | bool using_tx_dma; |
164 | bool using_rx_dma; | |
165 | struct pl011_dmarx_data dmarx; | |
68b65f73 RK |
166 | struct pl011_dmatx_data dmatx; |
167 | #endif | |
168 | }; | |
169 | ||
29772c4e LW |
170 | /* |
171 | * Reads up to 256 characters from the FIFO or until it's empty and | |
172 | * inserts them into the TTY layer. Returns the number of characters | |
173 | * read from the FIFO. | |
174 | */ | |
175 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) | |
176 | { | |
177 | u16 status, ch; | |
178 | unsigned int flag, max_count = 256; | |
179 | int fifotaken = 0; | |
180 | ||
181 | while (max_count--) { | |
182 | status = readw(uap->port.membase + UART01x_FR); | |
183 | if (status & UART01x_FR_RXFE) | |
184 | break; | |
185 | ||
186 | /* Take chars from the FIFO and update status */ | |
187 | ch = readw(uap->port.membase + UART01x_DR) | | |
188 | UART_DUMMY_DR_RX; | |
189 | flag = TTY_NORMAL; | |
190 | uap->port.icount.rx++; | |
191 | fifotaken++; | |
192 | ||
193 | if (unlikely(ch & UART_DR_ERROR)) { | |
194 | if (ch & UART011_DR_BE) { | |
195 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
196 | uap->port.icount.brk++; | |
197 | if (uart_handle_break(&uap->port)) | |
198 | continue; | |
199 | } else if (ch & UART011_DR_PE) | |
200 | uap->port.icount.parity++; | |
201 | else if (ch & UART011_DR_FE) | |
202 | uap->port.icount.frame++; | |
203 | if (ch & UART011_DR_OE) | |
204 | uap->port.icount.overrun++; | |
205 | ||
206 | ch &= uap->port.read_status_mask; | |
207 | ||
208 | if (ch & UART011_DR_BE) | |
209 | flag = TTY_BREAK; | |
210 | else if (ch & UART011_DR_PE) | |
211 | flag = TTY_PARITY; | |
212 | else if (ch & UART011_DR_FE) | |
213 | flag = TTY_FRAME; | |
214 | } | |
215 | ||
216 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) | |
217 | continue; | |
218 | ||
219 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
220 | } | |
221 | ||
222 | return fifotaken; | |
223 | } | |
224 | ||
225 | ||
68b65f73 RK |
226 | /* |
227 | * All the DMA operation mode stuff goes inside this ifdef. | |
228 | * This assumes that you have a generic DMA device interface, | |
229 | * no custom DMA interfaces are supported. | |
230 | */ | |
231 | #ifdef CONFIG_DMA_ENGINE | |
232 | ||
233 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
234 | ||
ead76f32 LW |
235 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
236 | enum dma_data_direction dir) | |
237 | { | |
cb06ff10 CM |
238 | dma_addr_t dma_addr; |
239 | ||
240 | sg->buf = dma_alloc_coherent(chan->device->dev, | |
241 | PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); | |
ead76f32 LW |
242 | if (!sg->buf) |
243 | return -ENOMEM; | |
244 | ||
cb06ff10 CM |
245 | sg_init_table(&sg->sg, 1); |
246 | sg_set_page(&sg->sg, phys_to_page(dma_addr), | |
247 | PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); | |
248 | sg_dma_address(&sg->sg) = dma_addr; | |
c64be923 | 249 | sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; |
ead76f32 | 250 | |
ead76f32 LW |
251 | return 0; |
252 | } | |
253 | ||
254 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |
255 | enum dma_data_direction dir) | |
256 | { | |
257 | if (sg->buf) { | |
cb06ff10 CM |
258 | dma_free_coherent(chan->device->dev, |
259 | PL011_DMA_BUFFER_SIZE, sg->buf, | |
260 | sg_dma_address(&sg->sg)); | |
ead76f32 LW |
261 | } |
262 | } | |
263 | ||
787b0c1f | 264 | static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *uap) |
68b65f73 RK |
265 | { |
266 | /* DMA is the sole user of the platform data right now */ | |
574de559 | 267 | struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); |
68b65f73 RK |
268 | struct dma_slave_config tx_conf = { |
269 | .dst_addr = uap->port.mapbase + UART01x_DR, | |
270 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 271 | .direction = DMA_MEM_TO_DEV, |
68b65f73 | 272 | .dst_maxburst = uap->fifosize >> 1, |
258aea76 | 273 | .device_fc = false, |
68b65f73 RK |
274 | }; |
275 | struct dma_chan *chan; | |
276 | dma_cap_mask_t mask; | |
277 | ||
787b0c1f | 278 | chan = dma_request_slave_channel(dev, "tx"); |
68b65f73 | 279 | |
68b65f73 | 280 | if (!chan) { |
787b0c1f AB |
281 | /* We need platform data */ |
282 | if (!plat || !plat->dma_filter) { | |
283 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
284 | return; | |
285 | } | |
286 | ||
287 | /* Try to acquire a generic DMA engine slave TX channel */ | |
288 | dma_cap_zero(mask); | |
289 | dma_cap_set(DMA_SLAVE, mask); | |
290 | ||
291 | chan = dma_request_channel(mask, plat->dma_filter, | |
292 | plat->dma_tx_param); | |
293 | if (!chan) { | |
294 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
295 | return; | |
296 | } | |
68b65f73 RK |
297 | } |
298 | ||
299 | dmaengine_slave_config(chan, &tx_conf); | |
300 | uap->dmatx.chan = chan; | |
301 | ||
302 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
303 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
304 | |
305 | /* Optionally make use of an RX channel as well */ | |
787b0c1f | 306 | chan = dma_request_slave_channel(dev, "rx"); |
0d3c673e | 307 | |
787b0c1f AB |
308 | if (!chan && plat->dma_rx_param) { |
309 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); | |
310 | ||
311 | if (!chan) { | |
312 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
313 | return; | |
314 | } | |
315 | } | |
316 | ||
317 | if (chan) { | |
ead76f32 LW |
318 | struct dma_slave_config rx_conf = { |
319 | .src_addr = uap->port.mapbase + UART01x_DR, | |
320 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 321 | .direction = DMA_DEV_TO_MEM, |
b2aeb775 | 322 | .src_maxburst = uap->fifosize >> 2, |
258aea76 | 323 | .device_fc = false, |
ead76f32 | 324 | }; |
2d3b7d6e AJ |
325 | struct dma_slave_caps caps; |
326 | ||
327 | /* | |
328 | * Some DMA controllers provide information on their capabilities. | |
329 | * If the controller does, check for suitable residue processing | |
330 | * otherwise assime all is well. | |
331 | */ | |
332 | if (0 == dma_get_slave_caps(chan, &caps)) { | |
333 | if (caps.residue_granularity == | |
334 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { | |
335 | dma_release_channel(chan); | |
336 | dev_info(uap->port.dev, | |
337 | "RX DMA disabled - no residue processing\n"); | |
338 | return; | |
339 | } | |
340 | } | |
ead76f32 LW |
341 | dmaengine_slave_config(chan, &rx_conf); |
342 | uap->dmarx.chan = chan; | |
343 | ||
8f898bfd | 344 | if (plat && plat->dma_rx_poll_enable) { |
cb06ff10 CM |
345 | /* Set poll rate if specified. */ |
346 | if (plat->dma_rx_poll_rate) { | |
347 | uap->dmarx.auto_poll_rate = false; | |
348 | uap->dmarx.poll_rate = plat->dma_rx_poll_rate; | |
349 | } else { | |
350 | /* | |
351 | * 100 ms defaults to poll rate if not | |
352 | * specified. This will be adjusted with | |
353 | * the baud rate at set_termios. | |
354 | */ | |
355 | uap->dmarx.auto_poll_rate = true; | |
356 | uap->dmarx.poll_rate = 100; | |
357 | } | |
358 | /* 3 secs defaults poll_timeout if not specified. */ | |
359 | if (plat->dma_rx_poll_timeout) | |
360 | uap->dmarx.poll_timeout = | |
361 | plat->dma_rx_poll_timeout; | |
362 | else | |
363 | uap->dmarx.poll_timeout = 3000; | |
364 | } else | |
365 | uap->dmarx.auto_poll_rate = false; | |
366 | ||
ead76f32 LW |
367 | dev_info(uap->port.dev, "DMA channel RX %s\n", |
368 | dma_chan_name(uap->dmarx.chan)); | |
369 | } | |
68b65f73 RK |
370 | } |
371 | ||
372 | #ifndef MODULE | |
373 | /* | |
374 | * Stack up the UARTs and let the above initcall be done at device | |
375 | * initcall time, because the serial driver is called as an arch | |
376 | * initcall, and at this time the DMA subsystem is not yet registered. | |
377 | * At this point the driver will switch over to using DMA where desired. | |
378 | */ | |
379 | struct dma_uap { | |
380 | struct list_head node; | |
381 | struct uart_amba_port *uap; | |
787b0c1f | 382 | struct device *dev; |
c19f12b5 RK |
383 | }; |
384 | ||
68b65f73 RK |
385 | static LIST_HEAD(pl011_dma_uarts); |
386 | ||
387 | static int __init pl011_dma_initcall(void) | |
388 | { | |
389 | struct list_head *node, *tmp; | |
390 | ||
391 | list_for_each_safe(node, tmp, &pl011_dma_uarts) { | |
392 | struct dma_uap *dmau = list_entry(node, struct dma_uap, node); | |
787b0c1f | 393 | pl011_dma_probe_initcall(dmau->dev, dmau->uap); |
68b65f73 RK |
394 | list_del(node); |
395 | kfree(dmau); | |
396 | } | |
397 | return 0; | |
398 | } | |
399 | ||
400 | device_initcall(pl011_dma_initcall); | |
401 | ||
787b0c1f | 402 | static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) |
68b65f73 RK |
403 | { |
404 | struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL); | |
405 | if (dmau) { | |
406 | dmau->uap = uap; | |
787b0c1f | 407 | dmau->dev = dev; |
68b65f73 RK |
408 | list_add_tail(&dmau->node, &pl011_dma_uarts); |
409 | } | |
410 | } | |
411 | #else | |
787b0c1f | 412 | static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) |
68b65f73 | 413 | { |
787b0c1f | 414 | pl011_dma_probe_initcall(dev, uap); |
68b65f73 RK |
415 | } |
416 | #endif | |
417 | ||
418 | static void pl011_dma_remove(struct uart_amba_port *uap) | |
419 | { | |
420 | /* TODO: remove the initcall if it has not yet executed */ | |
421 | if (uap->dmatx.chan) | |
422 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
423 | if (uap->dmarx.chan) |
424 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
425 | } |
426 | ||
68b65f73 RK |
427 | /* Forward declare this for the refill routine */ |
428 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); | |
429 | ||
430 | /* | |
431 | * The current DMA TX buffer has been sent. | |
432 | * Try to queue up another DMA buffer. | |
433 | */ | |
434 | static void pl011_dma_tx_callback(void *data) | |
435 | { | |
436 | struct uart_amba_port *uap = data; | |
437 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
438 | unsigned long flags; | |
439 | u16 dmacr; | |
440 | ||
441 | spin_lock_irqsave(&uap->port.lock, flags); | |
442 | if (uap->dmatx.queued) | |
443 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
444 | DMA_TO_DEVICE); | |
445 | ||
446 | dmacr = uap->dmacr; | |
447 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
448 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
449 | ||
450 | /* | |
451 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
452 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
453 | * | |
454 | * Note: we need to be careful here of a potential race between DMA | |
455 | * and the rest of the driver - if the driver disables TX DMA while | |
456 | * a TX buffer completing, we must update the tx queued status to | |
457 | * get further refills (hence we check dmacr). | |
458 | */ | |
459 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
460 | uart_circ_empty(&uap->port.state->xmit)) { | |
461 | uap->dmatx.queued = false; | |
462 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
463 | return; | |
464 | } | |
465 | ||
466 | if (pl011_dma_tx_refill(uap) <= 0) { | |
467 | /* | |
468 | * We didn't queue a DMA buffer for some reason, but we | |
469 | * have data pending to be sent. Re-enable the TX IRQ. | |
470 | */ | |
471 | uap->im |= UART011_TXIM; | |
472 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
473 | } | |
474 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
475 | } | |
476 | ||
477 | /* | |
478 | * Try to refill the TX DMA buffer. | |
479 | * Locking: called with port lock held and IRQs disabled. | |
480 | * Returns: | |
481 | * 1 if we queued up a TX DMA buffer. | |
482 | * 0 if we didn't want to handle this by DMA | |
483 | * <0 on error | |
484 | */ | |
485 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
486 | { | |
487 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
488 | struct dma_chan *chan = dmatx->chan; | |
489 | struct dma_device *dma_dev = chan->device; | |
490 | struct dma_async_tx_descriptor *desc; | |
491 | struct circ_buf *xmit = &uap->port.state->xmit; | |
492 | unsigned int count; | |
493 | ||
494 | /* | |
495 | * Try to avoid the overhead involved in using DMA if the | |
496 | * transaction fits in the first half of the FIFO, by using | |
497 | * the standard interrupt handling. This ensures that we | |
498 | * issue a uart_write_wakeup() at the appropriate time. | |
499 | */ | |
500 | count = uart_circ_chars_pending(xmit); | |
501 | if (count < (uap->fifosize >> 1)) { | |
502 | uap->dmatx.queued = false; | |
503 | return 0; | |
504 | } | |
505 | ||
506 | /* | |
507 | * Bodge: don't send the last character by DMA, as this | |
508 | * will prevent XON from notifying us to restart DMA. | |
509 | */ | |
510 | count -= 1; | |
511 | ||
512 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
513 | if (count > PL011_DMA_BUFFER_SIZE) | |
514 | count = PL011_DMA_BUFFER_SIZE; | |
515 | ||
516 | if (xmit->tail < xmit->head) | |
517 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
518 | else { | |
519 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
e2a545a6 AJ |
520 | size_t second; |
521 | ||
522 | if (first > count) | |
523 | first = count; | |
524 | second = count - first; | |
68b65f73 RK |
525 | |
526 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
527 | if (second) | |
528 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
529 | } | |
530 | ||
531 | dmatx->sg.length = count; | |
532 | ||
533 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
534 | uap->dmatx.queued = false; | |
535 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
536 | return -EBUSY; | |
537 | } | |
538 | ||
16052827 | 539 | desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, |
68b65f73 RK |
540 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
541 | if (!desc) { | |
542 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
543 | uap->dmatx.queued = false; | |
544 | /* | |
545 | * If DMA cannot be used right now, we complete this | |
546 | * transaction via IRQ and let the TTY layer retry. | |
547 | */ | |
548 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
549 | return -EBUSY; | |
550 | } | |
551 | ||
552 | /* Some data to go along to the callback */ | |
553 | desc->callback = pl011_dma_tx_callback; | |
554 | desc->callback_param = uap; | |
555 | ||
556 | /* All errors should happen at prepare time */ | |
557 | dmaengine_submit(desc); | |
558 | ||
559 | /* Fire the DMA transaction */ | |
560 | dma_dev->device_issue_pending(chan); | |
561 | ||
562 | uap->dmacr |= UART011_TXDMAE; | |
563 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
564 | uap->dmatx.queued = true; | |
565 | ||
566 | /* | |
567 | * Now we know that DMA will fire, so advance the ring buffer | |
568 | * with the stuff we just dispatched. | |
569 | */ | |
570 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
571 | uap->port.icount.tx += count; | |
572 | ||
573 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
574 | uart_write_wakeup(&uap->port); | |
575 | ||
576 | return 1; | |
577 | } | |
578 | ||
579 | /* | |
580 | * We received a transmit interrupt without a pending X-char but with | |
581 | * pending characters. | |
582 | * Locking: called with port lock held and IRQs disabled. | |
583 | * Returns: | |
584 | * false if we want to use PIO to transmit | |
585 | * true if we queued a DMA buffer | |
586 | */ | |
587 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
588 | { | |
ead76f32 | 589 | if (!uap->using_tx_dma) |
68b65f73 RK |
590 | return false; |
591 | ||
592 | /* | |
593 | * If we already have a TX buffer queued, but received a | |
594 | * TX interrupt, it will be because we've just sent an X-char. | |
595 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
596 | */ | |
597 | if (uap->dmatx.queued) { | |
598 | uap->dmacr |= UART011_TXDMAE; | |
599 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
600 | uap->im &= ~UART011_TXIM; | |
601 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
602 | return true; | |
603 | } | |
604 | ||
605 | /* | |
606 | * We don't have a TX buffer queued, so try to queue one. | |
25985edc | 607 | * If we successfully queued a buffer, mask the TX IRQ. |
68b65f73 RK |
608 | */ |
609 | if (pl011_dma_tx_refill(uap) > 0) { | |
610 | uap->im &= ~UART011_TXIM; | |
611 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
612 | return true; | |
613 | } | |
614 | return false; | |
615 | } | |
616 | ||
617 | /* | |
618 | * Stop the DMA transmit (eg, due to received XOFF). | |
619 | * Locking: called with port lock held and IRQs disabled. | |
620 | */ | |
621 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
622 | { | |
623 | if (uap->dmatx.queued) { | |
624 | uap->dmacr &= ~UART011_TXDMAE; | |
625 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
626 | } | |
627 | } | |
628 | ||
629 | /* | |
630 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
631 | * character queued for send, try to get that character out ASAP. | |
632 | * Locking: called with port lock held and IRQs disabled. | |
633 | * Returns: | |
634 | * false if we want the TX IRQ to be enabled | |
635 | * true if we have a buffer queued | |
636 | */ | |
637 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
638 | { | |
639 | u16 dmacr; | |
640 | ||
ead76f32 | 641 | if (!uap->using_tx_dma) |
68b65f73 RK |
642 | return false; |
643 | ||
644 | if (!uap->port.x_char) { | |
645 | /* no X-char, try to push chars out in DMA mode */ | |
646 | bool ret = true; | |
647 | ||
648 | if (!uap->dmatx.queued) { | |
649 | if (pl011_dma_tx_refill(uap) > 0) { | |
650 | uap->im &= ~UART011_TXIM; | |
651 | ret = true; | |
652 | } else { | |
653 | uap->im |= UART011_TXIM; | |
654 | ret = false; | |
655 | } | |
656 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
657 | } else if (!(uap->dmacr & UART011_TXDMAE)) { | |
658 | uap->dmacr |= UART011_TXDMAE; | |
659 | writew(uap->dmacr, | |
660 | uap->port.membase + UART011_DMACR); | |
661 | } | |
662 | return ret; | |
663 | } | |
664 | ||
665 | /* | |
666 | * We have an X-char to send. Disable DMA to prevent it loading | |
667 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
668 | */ | |
669 | dmacr = uap->dmacr; | |
670 | uap->dmacr &= ~UART011_TXDMAE; | |
671 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
672 | ||
673 | if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { | |
674 | /* | |
675 | * No space in the FIFO, so enable the transmit interrupt | |
676 | * so we know when there is space. Note that once we've | |
677 | * loaded the character, we should just re-enable DMA. | |
678 | */ | |
679 | return false; | |
680 | } | |
681 | ||
682 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
683 | uap->port.icount.tx++; | |
684 | uap->port.x_char = 0; | |
685 | ||
686 | /* Success - restore the DMA state */ | |
687 | uap->dmacr = dmacr; | |
688 | writew(dmacr, uap->port.membase + UART011_DMACR); | |
689 | ||
690 | return true; | |
691 | } | |
692 | ||
693 | /* | |
694 | * Flush the transmit buffer. | |
695 | * Locking: called with port lock held and IRQs disabled. | |
696 | */ | |
697 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
b83286bf FE |
698 | __releases(&uap->port.lock) |
699 | __acquires(&uap->port.lock) | |
68b65f73 | 700 | { |
a5820c24 DT |
701 | struct uart_amba_port *uap = |
702 | container_of(port, struct uart_amba_port, port); | |
68b65f73 | 703 | |
ead76f32 | 704 | if (!uap->using_tx_dma) |
68b65f73 RK |
705 | return; |
706 | ||
707 | /* Avoid deadlock with the DMA engine callback */ | |
708 | spin_unlock(&uap->port.lock); | |
709 | dmaengine_terminate_all(uap->dmatx.chan); | |
710 | spin_lock(&uap->port.lock); | |
711 | if (uap->dmatx.queued) { | |
712 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
713 | DMA_TO_DEVICE); | |
714 | uap->dmatx.queued = false; | |
715 | uap->dmacr &= ~UART011_TXDMAE; | |
716 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
717 | } | |
718 | } | |
719 | ||
ead76f32 LW |
720 | static void pl011_dma_rx_callback(void *data); |
721 | ||
722 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
723 | { | |
724 | struct dma_chan *rxchan = uap->dmarx.chan; | |
ead76f32 LW |
725 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
726 | struct dma_async_tx_descriptor *desc; | |
727 | struct pl011_sgbuf *sgbuf; | |
728 | ||
729 | if (!rxchan) | |
730 | return -EIO; | |
731 | ||
732 | /* Start the RX DMA job */ | |
733 | sgbuf = uap->dmarx.use_buf_b ? | |
734 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
16052827 | 735 | desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, |
a485df4b | 736 | DMA_DEV_TO_MEM, |
ead76f32 LW |
737 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
738 | /* | |
739 | * If the DMA engine is busy and cannot prepare a | |
740 | * channel, no big deal, the driver will fall back | |
741 | * to interrupt mode as a result of this error code. | |
742 | */ | |
743 | if (!desc) { | |
744 | uap->dmarx.running = false; | |
745 | dmaengine_terminate_all(rxchan); | |
746 | return -EBUSY; | |
747 | } | |
748 | ||
749 | /* Some data to go along to the callback */ | |
750 | desc->callback = pl011_dma_rx_callback; | |
751 | desc->callback_param = uap; | |
752 | dmarx->cookie = dmaengine_submit(desc); | |
753 | dma_async_issue_pending(rxchan); | |
754 | ||
755 | uap->dmacr |= UART011_RXDMAE; | |
756 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
757 | uap->dmarx.running = true; | |
758 | ||
759 | uap->im &= ~UART011_RXIM; | |
760 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | /* | |
766 | * This is called when either the DMA job is complete, or | |
767 | * the FIFO timeout interrupt occurred. This must be called | |
768 | * with the port spinlock uap->port.lock held. | |
769 | */ | |
770 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
771 | u32 pending, bool use_buf_b, | |
772 | bool readfifo) | |
773 | { | |
05c7cd39 | 774 | struct tty_port *port = &uap->port.state->port; |
ead76f32 LW |
775 | struct pl011_sgbuf *sgbuf = use_buf_b ? |
776 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
ead76f32 LW |
777 | int dma_count = 0; |
778 | u32 fifotaken = 0; /* only used for vdbg() */ | |
779 | ||
cb06ff10 CM |
780 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
781 | int dmataken = 0; | |
782 | ||
783 | if (uap->dmarx.poll_rate) { | |
784 | /* The data can be taken by polling */ | |
785 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
786 | /* Recalculate the pending size */ | |
787 | if (pending >= dmataken) | |
788 | pending -= dmataken; | |
789 | } | |
790 | ||
791 | /* Pick the remain data from the DMA */ | |
ead76f32 | 792 | if (pending) { |
ead76f32 LW |
793 | |
794 | /* | |
795 | * First take all chars in the DMA pipe, then look in the FIFO. | |
796 | * Note that tty_insert_flip_buf() tries to take as many chars | |
797 | * as it can. | |
798 | */ | |
cb06ff10 CM |
799 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, |
800 | pending); | |
ead76f32 LW |
801 | |
802 | uap->port.icount.rx += dma_count; | |
803 | if (dma_count < pending) | |
804 | dev_warn(uap->port.dev, | |
805 | "couldn't insert all characters (TTY is full?)\n"); | |
806 | } | |
807 | ||
cb06ff10 CM |
808 | /* Reset the last_residue for Rx DMA poll */ |
809 | if (uap->dmarx.poll_rate) | |
810 | dmarx->last_residue = sgbuf->sg.length; | |
811 | ||
ead76f32 LW |
812 | /* |
813 | * Only continue with trying to read the FIFO if all DMA chars have | |
814 | * been taken first. | |
815 | */ | |
816 | if (dma_count == pending && readfifo) { | |
817 | /* Clear any error flags */ | |
818 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
819 | uap->port.membase + UART011_ICR); | |
820 | ||
821 | /* | |
822 | * If we read all the DMA'd characters, and we had an | |
29772c4e LW |
823 | * incomplete buffer, that could be due to an rx error, or |
824 | * maybe we just timed out. Read any pending chars and check | |
825 | * the error status. | |
826 | * | |
827 | * Error conditions will only occur in the FIFO, these will | |
828 | * trigger an immediate interrupt and stop the DMA job, so we | |
829 | * will always find the error in the FIFO, never in the DMA | |
830 | * buffer. | |
ead76f32 | 831 | */ |
29772c4e | 832 | fifotaken = pl011_fifo_to_tty(uap); |
ead76f32 LW |
833 | } |
834 | ||
835 | spin_unlock(&uap->port.lock); | |
836 | dev_vdbg(uap->port.dev, | |
837 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
838 | dma_count, fifotaken); | |
2e124b4a | 839 | tty_flip_buffer_push(port); |
ead76f32 LW |
840 | spin_lock(&uap->port.lock); |
841 | } | |
842 | ||
843 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
844 | { | |
845 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
846 | struct dma_chan *rxchan = dmarx->chan; | |
847 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? | |
848 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
849 | size_t pending; | |
850 | struct dma_tx_state state; | |
851 | enum dma_status dmastat; | |
852 | ||
853 | /* | |
854 | * Pause the transfer so we can trust the current counter, | |
855 | * do this before we pause the PL011 block, else we may | |
856 | * overflow the FIFO. | |
857 | */ | |
858 | if (dmaengine_pause(rxchan)) | |
859 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
860 | dmastat = rxchan->device->device_tx_status(rxchan, | |
861 | dmarx->cookie, &state); | |
862 | if (dmastat != DMA_PAUSED) | |
863 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
864 | ||
865 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
866 | uap->dmacr &= ~UART011_RXDMAE; | |
867 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
868 | uap->dmarx.running = false; | |
869 | ||
870 | pending = sgbuf->sg.length - state.residue; | |
871 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
872 | /* Then we terminate the transfer - we now know our residue */ | |
873 | dmaengine_terminate_all(rxchan); | |
874 | ||
875 | /* | |
876 | * This will take the chars we have so far and insert | |
877 | * into the framework. | |
878 | */ | |
879 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
880 | ||
881 | /* Switch buffer & re-trigger DMA job */ | |
882 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
883 | if (pl011_dma_rx_trigger_dma(uap)) { | |
884 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
885 | "fall back to interrupt mode\n"); | |
886 | uap->im |= UART011_RXIM; | |
887 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
888 | } | |
889 | } | |
890 | ||
891 | static void pl011_dma_rx_callback(void *data) | |
892 | { | |
893 | struct uart_amba_port *uap = data; | |
894 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
6dc01aa6 | 895 | struct dma_chan *rxchan = dmarx->chan; |
ead76f32 | 896 | bool lastbuf = dmarx->use_buf_b; |
6dc01aa6 CM |
897 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? |
898 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
899 | size_t pending; | |
900 | struct dma_tx_state state; | |
ead76f32 LW |
901 | int ret; |
902 | ||
903 | /* | |
904 | * This completion interrupt occurs typically when the | |
905 | * RX buffer is totally stuffed but no timeout has yet | |
906 | * occurred. When that happens, we just want the RX | |
907 | * routine to flush out the secondary DMA buffer while | |
908 | * we immediately trigger the next DMA job. | |
909 | */ | |
910 | spin_lock_irq(&uap->port.lock); | |
6dc01aa6 CM |
911 | /* |
912 | * Rx data can be taken by the UART interrupts during | |
913 | * the DMA irq handler. So we check the residue here. | |
914 | */ | |
915 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
916 | pending = sgbuf->sg.length - state.residue; | |
917 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
918 | /* Then we terminate the transfer - we now know our residue */ | |
919 | dmaengine_terminate_all(rxchan); | |
920 | ||
ead76f32 LW |
921 | uap->dmarx.running = false; |
922 | dmarx->use_buf_b = !lastbuf; | |
923 | ret = pl011_dma_rx_trigger_dma(uap); | |
924 | ||
6dc01aa6 | 925 | pl011_dma_rx_chars(uap, pending, lastbuf, false); |
ead76f32 LW |
926 | spin_unlock_irq(&uap->port.lock); |
927 | /* | |
928 | * Do this check after we picked the DMA chars so we don't | |
929 | * get some IRQ immediately from RX. | |
930 | */ | |
931 | if (ret) { | |
932 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
933 | "fall back to interrupt mode\n"); | |
934 | uap->im |= UART011_RXIM; | |
935 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
936 | } | |
937 | } | |
938 | ||
939 | /* | |
940 | * Stop accepting received characters, when we're shutting down or | |
941 | * suspending this port. | |
942 | * Locking: called with port lock held and IRQs disabled. | |
943 | */ | |
944 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
945 | { | |
946 | /* FIXME. Just disable the DMA enable */ | |
947 | uap->dmacr &= ~UART011_RXDMAE; | |
948 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
949 | } | |
68b65f73 | 950 | |
cb06ff10 CM |
951 | /* |
952 | * Timer handler for Rx DMA polling. | |
953 | * Every polling, It checks the residue in the dma buffer and transfer | |
954 | * data to the tty. Also, last_residue is updated for the next polling. | |
955 | */ | |
956 | static void pl011_dma_rx_poll(unsigned long args) | |
957 | { | |
958 | struct uart_amba_port *uap = (struct uart_amba_port *)args; | |
959 | struct tty_port *port = &uap->port.state->port; | |
960 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
961 | struct dma_chan *rxchan = uap->dmarx.chan; | |
962 | unsigned long flags = 0; | |
963 | unsigned int dmataken = 0; | |
964 | unsigned int size = 0; | |
965 | struct pl011_sgbuf *sgbuf; | |
966 | int dma_count; | |
967 | struct dma_tx_state state; | |
968 | ||
969 | sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
970 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
971 | if (likely(state.residue < dmarx->last_residue)) { | |
972 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
973 | size = dmarx->last_residue - state.residue; | |
974 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, | |
975 | size); | |
976 | if (dma_count == size) | |
977 | dmarx->last_residue = state.residue; | |
978 | dmarx->last_jiffies = jiffies; | |
979 | } | |
980 | tty_flip_buffer_push(port); | |
981 | ||
982 | /* | |
983 | * If no data is received in poll_timeout, the driver will fall back | |
984 | * to interrupt mode. We will retrigger DMA at the first interrupt. | |
985 | */ | |
986 | if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) | |
987 | > uap->dmarx.poll_timeout) { | |
988 | ||
989 | spin_lock_irqsave(&uap->port.lock, flags); | |
990 | pl011_dma_rx_stop(uap); | |
c25a1ad7 GL |
991 | uap->im |= UART011_RXIM; |
992 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
cb06ff10 CM |
993 | spin_unlock_irqrestore(&uap->port.lock, flags); |
994 | ||
995 | uap->dmarx.running = false; | |
996 | dmaengine_terminate_all(rxchan); | |
997 | del_timer(&uap->dmarx.timer); | |
998 | } else { | |
999 | mod_timer(&uap->dmarx.timer, | |
1000 | jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1001 | } | |
1002 | } | |
1003 | ||
68b65f73 RK |
1004 | static void pl011_dma_startup(struct uart_amba_port *uap) |
1005 | { | |
ead76f32 LW |
1006 | int ret; |
1007 | ||
68b65f73 RK |
1008 | if (!uap->dmatx.chan) |
1009 | return; | |
1010 | ||
4c0be45b | 1011 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); |
68b65f73 RK |
1012 | if (!uap->dmatx.buf) { |
1013 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
1014 | uap->port.fifosize = uap->fifosize; | |
1015 | return; | |
1016 | } | |
1017 | ||
1018 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
1019 | ||
1020 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
1021 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
1022 | uap->using_tx_dma = true; |
1023 | ||
1024 | if (!uap->dmarx.chan) | |
1025 | goto skip_rx; | |
1026 | ||
1027 | /* Allocate and map DMA RX buffers */ | |
1028 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1029 | DMA_FROM_DEVICE); | |
1030 | if (ret) { | |
1031 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1032 | "RX buffer A", ret); | |
1033 | goto skip_rx; | |
1034 | } | |
68b65f73 | 1035 | |
ead76f32 LW |
1036 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
1037 | DMA_FROM_DEVICE); | |
1038 | if (ret) { | |
1039 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1040 | "RX buffer B", ret); | |
1041 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1042 | DMA_FROM_DEVICE); | |
1043 | goto skip_rx; | |
1044 | } | |
1045 | ||
1046 | uap->using_rx_dma = true; | |
68b65f73 | 1047 | |
ead76f32 | 1048 | skip_rx: |
68b65f73 RK |
1049 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
1050 | uap->dmacr |= UART011_DMAONERR; | |
1051 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
38d62436 RK |
1052 | |
1053 | /* | |
1054 | * ST Micro variants has some specific dma burst threshold | |
1055 | * compensation. Set this to 16 bytes, so burst will only | |
1056 | * be issued above/below 16 bytes. | |
1057 | */ | |
1058 | if (uap->vendor->dma_threshold) | |
1059 | writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, | |
1060 | uap->port.membase + ST_UART011_DMAWM); | |
ead76f32 LW |
1061 | |
1062 | if (uap->using_rx_dma) { | |
1063 | if (pl011_dma_rx_trigger_dma(uap)) | |
1064 | dev_dbg(uap->port.dev, "could not trigger initial " | |
1065 | "RX DMA job, fall back to interrupt mode\n"); | |
cb06ff10 CM |
1066 | if (uap->dmarx.poll_rate) { |
1067 | init_timer(&(uap->dmarx.timer)); | |
1068 | uap->dmarx.timer.function = pl011_dma_rx_poll; | |
1069 | uap->dmarx.timer.data = (unsigned long)uap; | |
1070 | mod_timer(&uap->dmarx.timer, | |
1071 | jiffies + | |
1072 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1073 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1074 | uap->dmarx.last_jiffies = jiffies; | |
1075 | } | |
ead76f32 | 1076 | } |
68b65f73 RK |
1077 | } |
1078 | ||
1079 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1080 | { | |
ead76f32 | 1081 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
1082 | return; |
1083 | ||
1084 | /* Disable RX and TX DMA */ | |
1085 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
1086 | barrier(); | |
1087 | ||
1088 | spin_lock_irq(&uap->port.lock); | |
1089 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
1090 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
1091 | spin_unlock_irq(&uap->port.lock); | |
1092 | ||
ead76f32 LW |
1093 | if (uap->using_tx_dma) { |
1094 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
1095 | dmaengine_terminate_all(uap->dmatx.chan); | |
1096 | if (uap->dmatx.queued) { | |
1097 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
1098 | DMA_TO_DEVICE); | |
1099 | uap->dmatx.queued = false; | |
1100 | } | |
1101 | ||
1102 | kfree(uap->dmatx.buf); | |
1103 | uap->using_tx_dma = false; | |
68b65f73 RK |
1104 | } |
1105 | ||
ead76f32 LW |
1106 | if (uap->using_rx_dma) { |
1107 | dmaengine_terminate_all(uap->dmarx.chan); | |
1108 | /* Clean up the RX DMA */ | |
1109 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); | |
1110 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); | |
cb06ff10 CM |
1111 | if (uap->dmarx.poll_rate) |
1112 | del_timer_sync(&uap->dmarx.timer); | |
ead76f32 LW |
1113 | uap->using_rx_dma = false; |
1114 | } | |
1115 | } | |
68b65f73 | 1116 | |
ead76f32 LW |
1117 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
1118 | { | |
1119 | return uap->using_rx_dma; | |
68b65f73 RK |
1120 | } |
1121 | ||
ead76f32 LW |
1122 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
1123 | { | |
1124 | return uap->using_rx_dma && uap->dmarx.running; | |
1125 | } | |
1126 | ||
68b65f73 RK |
1127 | #else |
1128 | /* Blank functions if the DMA engine is not available */ | |
aabdd290 | 1129 | static inline void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) |
68b65f73 RK |
1130 | { |
1131 | } | |
1132 | ||
1133 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
1134 | { | |
1135 | } | |
1136 | ||
1137 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
1138 | { | |
1139 | } | |
1140 | ||
1141 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1142 | { | |
1143 | } | |
1144 | ||
1145 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
1146 | { | |
1147 | return false; | |
1148 | } | |
1149 | ||
1150 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
1151 | { | |
1152 | } | |
1153 | ||
1154 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
1155 | { | |
1156 | return false; | |
1157 | } | |
1158 | ||
ead76f32 LW |
1159 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
1160 | { | |
1161 | } | |
1162 | ||
1163 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1164 | { | |
1165 | } | |
1166 | ||
1167 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
1168 | { | |
1169 | return -EIO; | |
1170 | } | |
1171 | ||
1172 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
1173 | { | |
1174 | return false; | |
1175 | } | |
1176 | ||
1177 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
1178 | { | |
1179 | return false; | |
1180 | } | |
1181 | ||
68b65f73 RK |
1182 | #define pl011_dma_flush_buffer NULL |
1183 | #endif | |
1184 | ||
b129a8cc | 1185 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 | 1186 | { |
a5820c24 DT |
1187 | struct uart_amba_port *uap = |
1188 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1189 | |
1190 | uap->im &= ~UART011_TXIM; | |
1191 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
68b65f73 | 1192 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
1193 | } |
1194 | ||
b129a8cc | 1195 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 | 1196 | { |
a5820c24 DT |
1197 | struct uart_amba_port *uap = |
1198 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1199 | |
68b65f73 RK |
1200 | if (!pl011_dma_tx_start(uap)) { |
1201 | uap->im |= UART011_TXIM; | |
1202 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1203 | } | |
1da177e4 LT |
1204 | } |
1205 | ||
1206 | static void pl011_stop_rx(struct uart_port *port) | |
1207 | { | |
a5820c24 DT |
1208 | struct uart_amba_port *uap = |
1209 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1210 | |
1211 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
1212 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
1213 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
ead76f32 LW |
1214 | |
1215 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1216 | } |
1217 | ||
1218 | static void pl011_enable_ms(struct uart_port *port) | |
1219 | { | |
a5820c24 DT |
1220 | struct uart_amba_port *uap = |
1221 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1222 | |
1223 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
1224 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1225 | } | |
1226 | ||
7d12e780 | 1227 | static void pl011_rx_chars(struct uart_amba_port *uap) |
b83286bf FE |
1228 | __releases(&uap->port.lock) |
1229 | __acquires(&uap->port.lock) | |
1da177e4 | 1230 | { |
29772c4e | 1231 | pl011_fifo_to_tty(uap); |
1da177e4 | 1232 | |
2389b272 | 1233 | spin_unlock(&uap->port.lock); |
2e124b4a | 1234 | tty_flip_buffer_push(&uap->port.state->port); |
ead76f32 LW |
1235 | /* |
1236 | * If we were temporarily out of DMA mode for a while, | |
1237 | * attempt to switch back to DMA mode again. | |
1238 | */ | |
1239 | if (pl011_dma_rx_available(uap)) { | |
1240 | if (pl011_dma_rx_trigger_dma(uap)) { | |
1241 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " | |
1242 | "fall back to interrupt mode again\n"); | |
1243 | uap->im |= UART011_RXIM; | |
30ae5859 | 1244 | writew(uap->im, uap->port.membase + UART011_IMSC); |
cb06ff10 | 1245 | } else { |
89fa28db | 1246 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1247 | /* Start Rx DMA poll */ |
1248 | if (uap->dmarx.poll_rate) { | |
1249 | uap->dmarx.last_jiffies = jiffies; | |
1250 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1251 | mod_timer(&uap->dmarx.timer, | |
1252 | jiffies + | |
1253 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1254 | } | |
89fa28db | 1255 | #endif |
cb06ff10 | 1256 | } |
ead76f32 | 1257 | } |
2389b272 | 1258 | spin_lock(&uap->port.lock); |
1da177e4 LT |
1259 | } |
1260 | ||
1261 | static void pl011_tx_chars(struct uart_amba_port *uap) | |
1262 | { | |
ebd2c8f6 | 1263 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
1264 | int count; |
1265 | ||
1266 | if (uap->port.x_char) { | |
1267 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
1268 | uap->port.icount.tx++; | |
1269 | uap->port.x_char = 0; | |
1270 | return; | |
1271 | } | |
1272 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1273 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1274 | return; |
1275 | } | |
1276 | ||
68b65f73 RK |
1277 | /* If we are using DMA mode, try to send some characters. */ |
1278 | if (pl011_dma_tx_irq(uap)) | |
1279 | return; | |
1280 | ||
ffca2b11 | 1281 | count = uap->fifosize >> 1; |
1da177e4 LT |
1282 | do { |
1283 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); | |
1284 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1285 | uap->port.icount.tx++; | |
1286 | if (uart_circ_empty(xmit)) | |
1287 | break; | |
1288 | } while (--count > 0); | |
1289 | ||
1290 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1291 | uart_write_wakeup(&uap->port); | |
1292 | ||
1293 | if (uart_circ_empty(xmit)) | |
b129a8cc | 1294 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1295 | } |
1296 | ||
1297 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1298 | { | |
1299 | unsigned int status, delta; | |
1300 | ||
1301 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1302 | ||
1303 | delta = status ^ uap->old_status; | |
1304 | uap->old_status = status; | |
1305 | ||
1306 | if (!delta) | |
1307 | return; | |
1308 | ||
1309 | if (delta & UART01x_FR_DCD) | |
1310 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1311 | ||
1312 | if (delta & UART01x_FR_DSR) | |
1313 | uap->port.icount.dsr++; | |
1314 | ||
1315 | if (delta & UART01x_FR_CTS) | |
1316 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
1317 | ||
bdc04e31 | 1318 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1319 | } |
1320 | ||
7d12e780 | 1321 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1322 | { |
1323 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1324 | unsigned long flags; |
1da177e4 LT |
1325 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
1326 | int handled = 0; | |
4fd0690b | 1327 | unsigned int dummy_read; |
1da177e4 | 1328 | |
963cc981 | 1329 | spin_lock_irqsave(&uap->port.lock, flags); |
1da177e4 LT |
1330 | status = readw(uap->port.membase + UART011_MIS); |
1331 | if (status) { | |
1332 | do { | |
4fd0690b R |
1333 | if (uap->vendor->cts_event_workaround) { |
1334 | /* workaround to make sure that all bits are unlocked.. */ | |
1335 | writew(0x00, uap->port.membase + UART011_ICR); | |
1336 | ||
1337 | /* | |
1338 | * WA: introduce 26ns(1 uart clk) delay before W1C; | |
1339 | * single apb access will incur 2 pclk(133.12Mhz) delay, | |
1340 | * so add 2 dummy reads | |
1341 | */ | |
1342 | dummy_read = readw(uap->port.membase + UART011_ICR); | |
1343 | dummy_read = readw(uap->port.membase + UART011_ICR); | |
1344 | } | |
1345 | ||
1da177e4 LT |
1346 | writew(status & ~(UART011_TXIS|UART011_RTIS| |
1347 | UART011_RXIS), | |
1348 | uap->port.membase + UART011_ICR); | |
1349 | ||
ead76f32 LW |
1350 | if (status & (UART011_RTIS|UART011_RXIS)) { |
1351 | if (pl011_dma_rx_running(uap)) | |
1352 | pl011_dma_rx_irq(uap); | |
1353 | else | |
1354 | pl011_rx_chars(uap); | |
1355 | } | |
1da177e4 LT |
1356 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1357 | UART011_CTSMIS|UART011_RIMIS)) | |
1358 | pl011_modem_status(uap); | |
1359 | if (status & UART011_TXIS) | |
1360 | pl011_tx_chars(uap); | |
1361 | ||
4fd0690b | 1362 | if (pass_counter-- == 0) |
1da177e4 LT |
1363 | break; |
1364 | ||
1365 | status = readw(uap->port.membase + UART011_MIS); | |
1366 | } while (status != 0); | |
1367 | handled = 1; | |
1368 | } | |
1369 | ||
963cc981 | 1370 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
1371 | |
1372 | return IRQ_RETVAL(handled); | |
1373 | } | |
1374 | ||
e643f87f | 1375 | static unsigned int pl011_tx_empty(struct uart_port *port) |
1da177e4 | 1376 | { |
a5820c24 DT |
1377 | struct uart_amba_port *uap = |
1378 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1379 | unsigned int status = readw(uap->port.membase + UART01x_FR); |
1380 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
1381 | } | |
1382 | ||
e643f87f | 1383 | static unsigned int pl011_get_mctrl(struct uart_port *port) |
1da177e4 | 1384 | { |
a5820c24 DT |
1385 | struct uart_amba_port *uap = |
1386 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1387 | unsigned int result = 0; |
1388 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1389 | ||
5159f407 | 1390 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
1391 | if (status & uartbit) \ |
1392 | result |= tiocmbit | |
1393 | ||
5159f407 JS |
1394 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
1395 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); | |
1396 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
1397 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
1398 | #undef TIOCMBIT | |
1da177e4 LT |
1399 | return result; |
1400 | } | |
1401 | ||
1402 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1403 | { | |
a5820c24 DT |
1404 | struct uart_amba_port *uap = |
1405 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1406 | unsigned int cr; |
1407 | ||
1408 | cr = readw(uap->port.membase + UART011_CR); | |
1409 | ||
5159f407 | 1410 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
1411 | if (mctrl & tiocmbit) \ |
1412 | cr |= uartbit; \ | |
1413 | else \ | |
1414 | cr &= ~uartbit | |
1415 | ||
5159f407 JS |
1416 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
1417 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
1418 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
1419 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
1420 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
1421 | |
1422 | if (uap->autorts) { | |
1423 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
1424 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
1425 | } | |
5159f407 | 1426 | #undef TIOCMBIT |
1da177e4 LT |
1427 | |
1428 | writew(cr, uap->port.membase + UART011_CR); | |
1429 | } | |
1430 | ||
1431 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1432 | { | |
a5820c24 DT |
1433 | struct uart_amba_port *uap = |
1434 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1435 | unsigned long flags; |
1436 | unsigned int lcr_h; | |
1437 | ||
1438 | spin_lock_irqsave(&uap->port.lock, flags); | |
ec489aa8 | 1439 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1440 | if (break_state == -1) |
1441 | lcr_h |= UART01x_LCRH_BRK; | |
1442 | else | |
1443 | lcr_h &= ~UART01x_LCRH_BRK; | |
ec489aa8 | 1444 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1445 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1446 | } | |
1447 | ||
84b5ae15 | 1448 | #ifdef CONFIG_CONSOLE_POLL |
5c8124a0 AV |
1449 | |
1450 | static void pl011_quiesce_irqs(struct uart_port *port) | |
1451 | { | |
a5820c24 DT |
1452 | struct uart_amba_port *uap = |
1453 | container_of(port, struct uart_amba_port, port); | |
5c8124a0 AV |
1454 | unsigned char __iomem *regs = uap->port.membase; |
1455 | ||
1456 | writew(readw(regs + UART011_MIS), regs + UART011_ICR); | |
1457 | /* | |
1458 | * There is no way to clear TXIM as this is "ready to transmit IRQ", so | |
1459 | * we simply mask it. start_tx() will unmask it. | |
1460 | * | |
1461 | * Note we can race with start_tx(), and if the race happens, the | |
1462 | * polling user might get another interrupt just after we clear it. | |
1463 | * But it should be OK and can happen even w/o the race, e.g. | |
1464 | * controller immediately got some new data and raised the IRQ. | |
1465 | * | |
1466 | * And whoever uses polling routines assumes that it manages the device | |
1467 | * (including tx queue), so we're also fine with start_tx()'s caller | |
1468 | * side. | |
1469 | */ | |
1470 | writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC); | |
1471 | } | |
1472 | ||
e643f87f | 1473 | static int pl011_get_poll_char(struct uart_port *port) |
84b5ae15 | 1474 | { |
a5820c24 DT |
1475 | struct uart_amba_port *uap = |
1476 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 JW |
1477 | unsigned int status; |
1478 | ||
5c8124a0 AV |
1479 | /* |
1480 | * The caller might need IRQs lowered, e.g. if used with KDB NMI | |
1481 | * debugger. | |
1482 | */ | |
1483 | pl011_quiesce_irqs(port); | |
1484 | ||
f5316b4a JW |
1485 | status = readw(uap->port.membase + UART01x_FR); |
1486 | if (status & UART01x_FR_RXFE) | |
1487 | return NO_POLL_CHAR; | |
84b5ae15 JW |
1488 | |
1489 | return readw(uap->port.membase + UART01x_DR); | |
1490 | } | |
1491 | ||
e643f87f | 1492 | static void pl011_put_poll_char(struct uart_port *port, |
84b5ae15 JW |
1493 | unsigned char ch) |
1494 | { | |
a5820c24 DT |
1495 | struct uart_amba_port *uap = |
1496 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 JW |
1497 | |
1498 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) | |
1499 | barrier(); | |
1500 | ||
1501 | writew(ch, uap->port.membase + UART01x_DR); | |
1502 | } | |
1503 | ||
1504 | #endif /* CONFIG_CONSOLE_POLL */ | |
1505 | ||
b3564c2c | 1506 | static int pl011_hwinit(struct uart_port *port) |
1da177e4 | 1507 | { |
a5820c24 DT |
1508 | struct uart_amba_port *uap = |
1509 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1510 | int retval; |
1511 | ||
78d80c5a | 1512 | /* Optionaly enable pins to be muxed in and configured */ |
2b996fc5 | 1513 | pinctrl_pm_select_default_state(port->dev); |
78d80c5a | 1514 | |
1da177e4 LT |
1515 | /* |
1516 | * Try to enable the clock producer. | |
1517 | */ | |
1c4c4394 | 1518 | retval = clk_prepare_enable(uap->clk); |
1da177e4 | 1519 | if (retval) |
7f6d942a | 1520 | return retval; |
1da177e4 LT |
1521 | |
1522 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1523 | ||
9b96fbac LW |
1524 | /* Clear pending error and receive interrupts */ |
1525 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS | | |
1526 | UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR); | |
1527 | ||
b3564c2c AV |
1528 | /* |
1529 | * Save interrupts enable mask, and enable RX interrupts in case if | |
1530 | * the interrupt is used for NMI entry. | |
1531 | */ | |
1532 | uap->im = readw(uap->port.membase + UART011_IMSC); | |
1533 | writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC); | |
1534 | ||
574de559 | 1535 | if (dev_get_platdata(uap->port.dev)) { |
b3564c2c AV |
1536 | struct amba_pl011_data *plat; |
1537 | ||
574de559 | 1538 | plat = dev_get_platdata(uap->port.dev); |
b3564c2c AV |
1539 | if (plat->init) |
1540 | plat->init(); | |
1541 | } | |
1542 | return 0; | |
b3564c2c AV |
1543 | } |
1544 | ||
b60f2f66 JM |
1545 | static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) |
1546 | { | |
1547 | writew(lcr_h, uap->port.membase + uap->lcrh_rx); | |
1548 | if (uap->lcrh_rx != uap->lcrh_tx) { | |
1549 | int i; | |
1550 | /* | |
1551 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1552 | * to get this delay write read only register 10 times | |
1553 | */ | |
1554 | for (i = 0; i < 10; ++i) | |
1555 | writew(0xff, uap->port.membase + UART011_MIS); | |
1556 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); | |
1557 | } | |
1558 | } | |
1559 | ||
b3564c2c AV |
1560 | static int pl011_startup(struct uart_port *port) |
1561 | { | |
a5820c24 DT |
1562 | struct uart_amba_port *uap = |
1563 | container_of(port, struct uart_amba_port, port); | |
570d2910 | 1564 | unsigned int cr, lcr_h, fbrd, ibrd; |
b3564c2c AV |
1565 | int retval; |
1566 | ||
1567 | retval = pl011_hwinit(port); | |
1568 | if (retval) | |
1569 | goto clk_dis; | |
1570 | ||
1571 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1572 | ||
1da177e4 LT |
1573 | /* |
1574 | * Allocate the IRQ | |
1575 | */ | |
1576 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
1577 | if (retval) | |
1578 | goto clk_dis; | |
1579 | ||
c19f12b5 | 1580 | writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); |
1da177e4 LT |
1581 | |
1582 | /* | |
570d2910 JM |
1583 | * Provoke TX FIFO interrupt into asserting. Taking care to preserve |
1584 | * baud rate and data format specified by FBRD, IBRD and LCRH as the | |
1585 | * UART may already be in use as a console. | |
1da177e4 | 1586 | */ |
fe433907 JM |
1587 | spin_lock_irq(&uap->port.lock); |
1588 | ||
570d2910 JM |
1589 | fbrd = readw(uap->port.membase + UART011_FBRD); |
1590 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
1591 | lcr_h = readw(uap->port.membase + uap->lcrh_rx); | |
1592 | ||
1da177e4 LT |
1593 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; |
1594 | writew(cr, uap->port.membase + UART011_CR); | |
1595 | writew(0, uap->port.membase + UART011_FBRD); | |
1596 | writew(1, uap->port.membase + UART011_IBRD); | |
b60f2f66 | 1597 | pl011_write_lcr_h(uap, 0); |
1da177e4 LT |
1598 | writew(0, uap->port.membase + UART01x_DR); |
1599 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
1600 | barrier(); | |
1601 | ||
570d2910 JM |
1602 | writew(fbrd, uap->port.membase + UART011_FBRD); |
1603 | writew(ibrd, uap->port.membase + UART011_IBRD); | |
1604 | pl011_write_lcr_h(uap, lcr_h); | |
1605 | ||
d8d8ffa4 SKS |
1606 | /* restore RTS and DTR */ |
1607 | cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); | |
1608 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
1da177e4 LT |
1609 | writew(cr, uap->port.membase + UART011_CR); |
1610 | ||
fe433907 JM |
1611 | spin_unlock_irq(&uap->port.lock); |
1612 | ||
1da177e4 LT |
1613 | /* |
1614 | * initialise the old status of the modem signals | |
1615 | */ | |
1616 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1617 | ||
68b65f73 RK |
1618 | /* Startup DMA */ |
1619 | pl011_dma_startup(uap); | |
1620 | ||
1da177e4 | 1621 | /* |
ead76f32 LW |
1622 | * Finally, enable interrupts, only timeouts when using DMA |
1623 | * if initial RX DMA job failed, start in interrupt mode | |
1624 | * as well. | |
1da177e4 LT |
1625 | */ |
1626 | spin_lock_irq(&uap->port.lock); | |
9b96fbac LW |
1627 | /* Clear out any spuriously appearing RX interrupts */ |
1628 | writew(UART011_RTIS | UART011_RXIS, | |
1629 | uap->port.membase + UART011_ICR); | |
ead76f32 LW |
1630 | uap->im = UART011_RTIM; |
1631 | if (!pl011_dma_rx_running(uap)) | |
1632 | uap->im |= UART011_RXIM; | |
1da177e4 LT |
1633 | writew(uap->im, uap->port.membase + UART011_IMSC); |
1634 | spin_unlock_irq(&uap->port.lock); | |
1635 | ||
1636 | return 0; | |
1637 | ||
1638 | clk_dis: | |
1c4c4394 | 1639 | clk_disable_unprepare(uap->clk); |
1da177e4 LT |
1640 | return retval; |
1641 | } | |
1642 | ||
ec489aa8 LW |
1643 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
1644 | unsigned int lcrh) | |
1645 | { | |
1646 | unsigned long val; | |
1647 | ||
1648 | val = readw(uap->port.membase + lcrh); | |
1649 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
1650 | writew(val, uap->port.membase + lcrh); | |
1651 | } | |
1652 | ||
1da177e4 LT |
1653 | static void pl011_shutdown(struct uart_port *port) |
1654 | { | |
a5820c24 DT |
1655 | struct uart_amba_port *uap = |
1656 | container_of(port, struct uart_amba_port, port); | |
d8d8ffa4 | 1657 | unsigned int cr; |
1da177e4 LT |
1658 | |
1659 | /* | |
1660 | * disable all interrupts | |
1661 | */ | |
1662 | spin_lock_irq(&uap->port.lock); | |
1663 | uap->im = 0; | |
1664 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1665 | writew(0xffff, uap->port.membase + UART011_ICR); | |
1666 | spin_unlock_irq(&uap->port.lock); | |
1667 | ||
68b65f73 RK |
1668 | pl011_dma_shutdown(uap); |
1669 | ||
1da177e4 LT |
1670 | /* |
1671 | * Free the interrupt | |
1672 | */ | |
1673 | free_irq(uap->port.irq, uap); | |
1674 | ||
1675 | /* | |
1676 | * disable the port | |
d8d8ffa4 SKS |
1677 | * disable the port. It should not disable RTS and DTR. |
1678 | * Also RTS and DTR state should be preserved to restore | |
1679 | * it during startup(). | |
1da177e4 | 1680 | */ |
3b43816f | 1681 | uap->autorts = false; |
fe433907 | 1682 | spin_lock_irq(&uap->port.lock); |
d8d8ffa4 SKS |
1683 | cr = readw(uap->port.membase + UART011_CR); |
1684 | uap->old_cr = cr; | |
1685 | cr &= UART011_CR_RTS | UART011_CR_DTR; | |
1686 | cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1687 | writew(cr, uap->port.membase + UART011_CR); | |
fe433907 | 1688 | spin_unlock_irq(&uap->port.lock); |
1da177e4 LT |
1689 | |
1690 | /* | |
1691 | * disable break condition and fifos | |
1692 | */ | |
ec489aa8 LW |
1693 | pl011_shutdown_channel(uap, uap->lcrh_rx); |
1694 | if (uap->lcrh_rx != uap->lcrh_tx) | |
1695 | pl011_shutdown_channel(uap, uap->lcrh_tx); | |
1da177e4 LT |
1696 | |
1697 | /* | |
1698 | * Shut down the clock producer | |
1699 | */ | |
1c4c4394 | 1700 | clk_disable_unprepare(uap->clk); |
78d80c5a | 1701 | /* Optionally let pins go into sleep states */ |
2b996fc5 | 1702 | pinctrl_pm_select_sleep_state(port->dev); |
c16d51a3 | 1703 | |
574de559 | 1704 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
1705 | struct amba_pl011_data *plat; |
1706 | ||
574de559 | 1707 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
1708 | if (plat->exit) |
1709 | plat->exit(); | |
1710 | } | |
1711 | ||
36f339d1 PH |
1712 | if (uap->port.ops->flush_buffer) |
1713 | uap->port.ops->flush_buffer(port); | |
1da177e4 LT |
1714 | } |
1715 | ||
1716 | static void | |
606d099c AC |
1717 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1718 | struct ktermios *old) | |
1da177e4 | 1719 | { |
a5820c24 DT |
1720 | struct uart_amba_port *uap = |
1721 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1722 | unsigned int lcr_h, old_cr; |
1723 | unsigned long flags; | |
c19f12b5 RK |
1724 | unsigned int baud, quot, clkdiv; |
1725 | ||
1726 | if (uap->vendor->oversampling) | |
1727 | clkdiv = 8; | |
1728 | else | |
1729 | clkdiv = 16; | |
1da177e4 LT |
1730 | |
1731 | /* | |
1732 | * Ask the core to calculate the divisor for us. | |
1733 | */ | |
ac3e3fb4 | 1734 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1735 | port->uartclk / clkdiv); |
89fa28db | 1736 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1737 | /* |
1738 | * Adjust RX DMA polling rate with baud rate if not specified. | |
1739 | */ | |
1740 | if (uap->dmarx.auto_poll_rate) | |
1741 | uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); | |
89fa28db | 1742 | #endif |
ac3e3fb4 LW |
1743 | |
1744 | if (baud > port->uartclk/16) | |
1745 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1746 | else | |
1747 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1748 | |
1749 | switch (termios->c_cflag & CSIZE) { | |
1750 | case CS5: | |
1751 | lcr_h = UART01x_LCRH_WLEN_5; | |
1752 | break; | |
1753 | case CS6: | |
1754 | lcr_h = UART01x_LCRH_WLEN_6; | |
1755 | break; | |
1756 | case CS7: | |
1757 | lcr_h = UART01x_LCRH_WLEN_7; | |
1758 | break; | |
1759 | default: // CS8 | |
1760 | lcr_h = UART01x_LCRH_WLEN_8; | |
1761 | break; | |
1762 | } | |
1763 | if (termios->c_cflag & CSTOPB) | |
1764 | lcr_h |= UART01x_LCRH_STP2; | |
1765 | if (termios->c_cflag & PARENB) { | |
1766 | lcr_h |= UART01x_LCRH_PEN; | |
1767 | if (!(termios->c_cflag & PARODD)) | |
1768 | lcr_h |= UART01x_LCRH_EPS; | |
1769 | } | |
ffca2b11 | 1770 | if (uap->fifosize > 1) |
1da177e4 LT |
1771 | lcr_h |= UART01x_LCRH_FEN; |
1772 | ||
1773 | spin_lock_irqsave(&port->lock, flags); | |
1774 | ||
1775 | /* | |
1776 | * Update the per-port timeout. | |
1777 | */ | |
1778 | uart_update_timeout(port, termios->c_cflag, baud); | |
1779 | ||
b63d4f0f | 1780 | port->read_status_mask = UART011_DR_OE | 255; |
1da177e4 | 1781 | if (termios->c_iflag & INPCK) |
b63d4f0f | 1782 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
ef8b9ddc | 1783 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
b63d4f0f | 1784 | port->read_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1785 | |
1786 | /* | |
1787 | * Characters to ignore | |
1788 | */ | |
1789 | port->ignore_status_mask = 0; | |
1790 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1791 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1792 | if (termios->c_iflag & IGNBRK) { |
b63d4f0f | 1793 | port->ignore_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1794 | /* |
1795 | * If we're ignoring parity and break indicators, | |
1796 | * ignore overruns too (for real raw support). | |
1797 | */ | |
1798 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1799 | port->ignore_status_mask |= UART011_DR_OE; |
1da177e4 LT |
1800 | } |
1801 | ||
1802 | /* | |
1803 | * Ignore all characters if CREAD is not set. | |
1804 | */ | |
1805 | if ((termios->c_cflag & CREAD) == 0) | |
b63d4f0f | 1806 | port->ignore_status_mask |= UART_DUMMY_DR_RX; |
1da177e4 LT |
1807 | |
1808 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1809 | pl011_enable_ms(port); | |
1810 | ||
1811 | /* first, disable everything */ | |
1812 | old_cr = readw(port->membase + UART011_CR); | |
1813 | writew(0, port->membase + UART011_CR); | |
1814 | ||
3b43816f RV |
1815 | if (termios->c_cflag & CRTSCTS) { |
1816 | if (old_cr & UART011_CR_RTS) | |
1817 | old_cr |= UART011_CR_RTSEN; | |
1818 | ||
1819 | old_cr |= UART011_CR_CTSEN; | |
1820 | uap->autorts = true; | |
1821 | } else { | |
1822 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1823 | uap->autorts = false; | |
1824 | } | |
1825 | ||
c19f12b5 RK |
1826 | if (uap->vendor->oversampling) { |
1827 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1828 | old_cr |= ST_UART011_CR_OVSFACT; |
1829 | else | |
1830 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1831 | } | |
1832 | ||
c5dd553b LW |
1833 | /* |
1834 | * Workaround for the ST Micro oversampling variants to | |
1835 | * increase the bitrate slightly, by lowering the divisor, | |
1836 | * to avoid delayed sampling of start bit at high speeds, | |
1837 | * else we see data corruption. | |
1838 | */ | |
1839 | if (uap->vendor->oversampling) { | |
1840 | if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) | |
1841 | quot -= 1; | |
1842 | else if ((baud > 3250000) && (quot > 2)) | |
1843 | quot -= 2; | |
1844 | } | |
1da177e4 LT |
1845 | /* Set baud rate */ |
1846 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
1847 | writew(quot >> 6, port->membase + UART011_IBRD); | |
1848 | ||
1849 | /* | |
1850 | * ----------v----------v----------v----------v----- | |
c5dd553b LW |
1851 | * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER |
1852 | * UART011_FBRD & UART011_IBRD. | |
1da177e4 LT |
1853 | * ----------^----------^----------^----------^----- |
1854 | */ | |
b60f2f66 | 1855 | pl011_write_lcr_h(uap, lcr_h); |
1da177e4 LT |
1856 | writew(old_cr, port->membase + UART011_CR); |
1857 | ||
1858 | spin_unlock_irqrestore(&port->lock, flags); | |
1859 | } | |
1860 | ||
1861 | static const char *pl011_type(struct uart_port *port) | |
1862 | { | |
a5820c24 DT |
1863 | struct uart_amba_port *uap = |
1864 | container_of(port, struct uart_amba_port, port); | |
e8a7ba86 | 1865 | return uap->port.type == PORT_AMBA ? uap->type : NULL; |
1da177e4 LT |
1866 | } |
1867 | ||
1868 | /* | |
1869 | * Release the memory region(s) being used by 'port' | |
1870 | */ | |
e643f87f | 1871 | static void pl011_release_port(struct uart_port *port) |
1da177e4 LT |
1872 | { |
1873 | release_mem_region(port->mapbase, SZ_4K); | |
1874 | } | |
1875 | ||
1876 | /* | |
1877 | * Request the memory region(s) being used by 'port' | |
1878 | */ | |
e643f87f | 1879 | static int pl011_request_port(struct uart_port *port) |
1da177e4 LT |
1880 | { |
1881 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
1882 | != NULL ? 0 : -EBUSY; | |
1883 | } | |
1884 | ||
1885 | /* | |
1886 | * Configure/autoconfigure the port. | |
1887 | */ | |
e643f87f | 1888 | static void pl011_config_port(struct uart_port *port, int flags) |
1da177e4 LT |
1889 | { |
1890 | if (flags & UART_CONFIG_TYPE) { | |
1891 | port->type = PORT_AMBA; | |
e643f87f | 1892 | pl011_request_port(port); |
1da177e4 LT |
1893 | } |
1894 | } | |
1895 | ||
1896 | /* | |
1897 | * verify the new serial_struct (for TIOCSSERIAL). | |
1898 | */ | |
e643f87f | 1899 | static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) |
1da177e4 LT |
1900 | { |
1901 | int ret = 0; | |
1902 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
1903 | ret = -EINVAL; | |
a62c4133 | 1904 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
1905 | ret = -EINVAL; |
1906 | if (ser->baud_base < 9600) | |
1907 | ret = -EINVAL; | |
1908 | return ret; | |
1909 | } | |
1910 | ||
1911 | static struct uart_ops amba_pl011_pops = { | |
e643f87f | 1912 | .tx_empty = pl011_tx_empty, |
1da177e4 | 1913 | .set_mctrl = pl011_set_mctrl, |
e643f87f | 1914 | .get_mctrl = pl011_get_mctrl, |
1da177e4 LT |
1915 | .stop_tx = pl011_stop_tx, |
1916 | .start_tx = pl011_start_tx, | |
1917 | .stop_rx = pl011_stop_rx, | |
1918 | .enable_ms = pl011_enable_ms, | |
1919 | .break_ctl = pl011_break_ctl, | |
1920 | .startup = pl011_startup, | |
1921 | .shutdown = pl011_shutdown, | |
68b65f73 | 1922 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
1923 | .set_termios = pl011_set_termios, |
1924 | .type = pl011_type, | |
e643f87f LW |
1925 | .release_port = pl011_release_port, |
1926 | .request_port = pl011_request_port, | |
1927 | .config_port = pl011_config_port, | |
1928 | .verify_port = pl011_verify_port, | |
84b5ae15 | 1929 | #ifdef CONFIG_CONSOLE_POLL |
b3564c2c | 1930 | .poll_init = pl011_hwinit, |
e643f87f LW |
1931 | .poll_get_char = pl011_get_poll_char, |
1932 | .poll_put_char = pl011_put_poll_char, | |
84b5ae15 | 1933 | #endif |
1da177e4 LT |
1934 | }; |
1935 | ||
1936 | static struct uart_amba_port *amba_ports[UART_NR]; | |
1937 | ||
1938 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
1939 | ||
d358788f | 1940 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 1941 | { |
a5820c24 DT |
1942 | struct uart_amba_port *uap = |
1943 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1944 | |
d358788f RK |
1945 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
1946 | barrier(); | |
1da177e4 LT |
1947 | writew(ch, uap->port.membase + UART01x_DR); |
1948 | } | |
1949 | ||
1950 | static void | |
1951 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
1952 | { | |
1953 | struct uart_amba_port *uap = amba_ports[co->index]; | |
1954 | unsigned int status, old_cr, new_cr; | |
ef605fdb RV |
1955 | unsigned long flags; |
1956 | int locked = 1; | |
1da177e4 LT |
1957 | |
1958 | clk_enable(uap->clk); | |
1959 | ||
ef605fdb RV |
1960 | local_irq_save(flags); |
1961 | if (uap->port.sysrq) | |
1962 | locked = 0; | |
1963 | else if (oops_in_progress) | |
1964 | locked = spin_trylock(&uap->port.lock); | |
1965 | else | |
1966 | spin_lock(&uap->port.lock); | |
1967 | ||
1da177e4 LT |
1968 | /* |
1969 | * First save the CR then disable the interrupts | |
1970 | */ | |
1971 | old_cr = readw(uap->port.membase + UART011_CR); | |
1972 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
1973 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1974 | writew(new_cr, uap->port.membase + UART011_CR); | |
1975 | ||
d358788f | 1976 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
1977 | |
1978 | /* | |
1979 | * Finally, wait for transmitter to become empty | |
1980 | * and restore the TCR | |
1981 | */ | |
1982 | do { | |
1983 | status = readw(uap->port.membase + UART01x_FR); | |
1984 | } while (status & UART01x_FR_BUSY); | |
1985 | writew(old_cr, uap->port.membase + UART011_CR); | |
1986 | ||
ef605fdb RV |
1987 | if (locked) |
1988 | spin_unlock(&uap->port.lock); | |
1989 | local_irq_restore(flags); | |
1990 | ||
1da177e4 LT |
1991 | clk_disable(uap->clk); |
1992 | } | |
1993 | ||
1994 | static void __init | |
1995 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
1996 | int *parity, int *bits) | |
1997 | { | |
1998 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
1999 | unsigned int lcr_h, ibrd, fbrd; | |
2000 | ||
ec489aa8 | 2001 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
2002 | |
2003 | *parity = 'n'; | |
2004 | if (lcr_h & UART01x_LCRH_PEN) { | |
2005 | if (lcr_h & UART01x_LCRH_EPS) | |
2006 | *parity = 'e'; | |
2007 | else | |
2008 | *parity = 'o'; | |
2009 | } | |
2010 | ||
2011 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
2012 | *bits = 7; | |
2013 | else | |
2014 | *bits = 8; | |
2015 | ||
2016 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
2017 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
2018 | ||
2019 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 2020 | |
c19f12b5 | 2021 | if (uap->vendor->oversampling) { |
ac3e3fb4 LW |
2022 | if (readw(uap->port.membase + UART011_CR) |
2023 | & ST_UART011_CR_OVSFACT) | |
2024 | *baud *= 2; | |
2025 | } | |
1da177e4 LT |
2026 | } |
2027 | } | |
2028 | ||
2029 | static int __init pl011_console_setup(struct console *co, char *options) | |
2030 | { | |
2031 | struct uart_amba_port *uap; | |
2032 | int baud = 38400; | |
2033 | int bits = 8; | |
2034 | int parity = 'n'; | |
2035 | int flow = 'n'; | |
4b4851c6 | 2036 | int ret; |
1da177e4 LT |
2037 | |
2038 | /* | |
2039 | * Check whether an invalid uart number has been specified, and | |
2040 | * if so, search for the first available port that does have | |
2041 | * console support. | |
2042 | */ | |
2043 | if (co->index >= UART_NR) | |
2044 | co->index = 0; | |
2045 | uap = amba_ports[co->index]; | |
d28122a5 RK |
2046 | if (!uap) |
2047 | return -ENODEV; | |
1da177e4 | 2048 | |
78d80c5a | 2049 | /* Allow pins to be muxed in and configured */ |
2b996fc5 | 2050 | pinctrl_pm_select_default_state(uap->port.dev); |
78d80c5a | 2051 | |
4b4851c6 RK |
2052 | ret = clk_prepare(uap->clk); |
2053 | if (ret) | |
2054 | return ret; | |
2055 | ||
574de559 | 2056 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
2057 | struct amba_pl011_data *plat; |
2058 | ||
574de559 | 2059 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
2060 | if (plat->init) |
2061 | plat->init(); | |
2062 | } | |
2063 | ||
1da177e4 LT |
2064 | uap->port.uartclk = clk_get_rate(uap->clk); |
2065 | ||
2066 | if (options) | |
2067 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2068 | else | |
2069 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
2070 | ||
2071 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
2072 | } | |
2073 | ||
2d93486c | 2074 | static struct uart_driver amba_reg; |
1da177e4 LT |
2075 | static struct console amba_console = { |
2076 | .name = "ttyAMA", | |
2077 | .write = pl011_console_write, | |
2078 | .device = uart_console_device, | |
2079 | .setup = pl011_console_setup, | |
2080 | .flags = CON_PRINTBUFFER, | |
2081 | .index = -1, | |
2082 | .data = &amba_reg, | |
2083 | }; | |
2084 | ||
2085 | #define AMBA_CONSOLE (&amba_console) | |
0d3c673e RH |
2086 | |
2087 | static void pl011_putc(struct uart_port *port, int c) | |
2088 | { | |
2089 | while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) | |
2090 | ; | |
2091 | writeb(c, port->membase + UART01x_DR); | |
2092 | while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) | |
2093 | ; | |
2094 | } | |
2095 | ||
2096 | static void pl011_early_write(struct console *con, const char *s, unsigned n) | |
2097 | { | |
2098 | struct earlycon_device *dev = con->data; | |
2099 | ||
2100 | uart_console_write(&dev->port, s, n, pl011_putc); | |
2101 | } | |
2102 | ||
2103 | static int __init pl011_early_console_setup(struct earlycon_device *device, | |
2104 | const char *opt) | |
2105 | { | |
2106 | if (!device->port.membase) | |
2107 | return -ENODEV; | |
2108 | ||
2109 | device->con->write = pl011_early_write; | |
2110 | return 0; | |
2111 | } | |
2112 | EARLYCON_DECLARE(pl011, pl011_early_console_setup); | |
45e0f0f5 | 2113 | OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); |
0d3c673e | 2114 | |
1da177e4 LT |
2115 | #else |
2116 | #define AMBA_CONSOLE NULL | |
2117 | #endif | |
2118 | ||
2119 | static struct uart_driver amba_reg = { | |
2120 | .owner = THIS_MODULE, | |
2121 | .driver_name = "ttyAMA", | |
2122 | .dev_name = "ttyAMA", | |
2123 | .major = SERIAL_AMBA_MAJOR, | |
2124 | .minor = SERIAL_AMBA_MINOR, | |
2125 | .nr = UART_NR, | |
2126 | .cons = AMBA_CONSOLE, | |
2127 | }; | |
2128 | ||
32614aad ML |
2129 | static int pl011_probe_dt_alias(int index, struct device *dev) |
2130 | { | |
2131 | struct device_node *np; | |
2132 | static bool seen_dev_with_alias = false; | |
2133 | static bool seen_dev_without_alias = false; | |
2134 | int ret = index; | |
2135 | ||
2136 | if (!IS_ENABLED(CONFIG_OF)) | |
2137 | return ret; | |
2138 | ||
2139 | np = dev->of_node; | |
2140 | if (!np) | |
2141 | return ret; | |
2142 | ||
2143 | ret = of_alias_get_id(np, "serial"); | |
2144 | if (IS_ERR_VALUE(ret)) { | |
2145 | seen_dev_without_alias = true; | |
2146 | ret = index; | |
2147 | } else { | |
2148 | seen_dev_with_alias = true; | |
2149 | if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { | |
2150 | dev_warn(dev, "requested serial port %d not available.\n", ret); | |
2151 | ret = index; | |
2152 | } | |
2153 | } | |
2154 | ||
2155 | if (seen_dev_with_alias && seen_dev_without_alias) | |
2156 | dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); | |
2157 | ||
2158 | return ret; | |
2159 | } | |
2160 | ||
aa25afad | 2161 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
1da177e4 LT |
2162 | { |
2163 | struct uart_amba_port *uap; | |
5926a295 | 2164 | struct vendor_data *vendor = id->data; |
1da177e4 LT |
2165 | void __iomem *base; |
2166 | int i, ret; | |
2167 | ||
2168 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
2169 | if (amba_ports[i] == NULL) | |
2170 | break; | |
2171 | ||
7f6d942a TB |
2172 | if (i == ARRAY_SIZE(amba_ports)) |
2173 | return -EBUSY; | |
1da177e4 | 2174 | |
de609582 LW |
2175 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), |
2176 | GFP_KERNEL); | |
7f6d942a TB |
2177 | if (uap == NULL) |
2178 | return -ENOMEM; | |
1da177e4 | 2179 | |
32614aad ML |
2180 | i = pl011_probe_dt_alias(i, &dev->dev); |
2181 | ||
de609582 LW |
2182 | base = devm_ioremap(&dev->dev, dev->res.start, |
2183 | resource_size(&dev->res)); | |
7f6d942a TB |
2184 | if (!base) |
2185 | return -ENOMEM; | |
1da177e4 | 2186 | |
de609582 | 2187 | uap->clk = devm_clk_get(&dev->dev, NULL); |
7f6d942a TB |
2188 | if (IS_ERR(uap->clk)) |
2189 | return PTR_ERR(uap->clk); | |
1da177e4 | 2190 | |
c19f12b5 | 2191 | uap->vendor = vendor; |
ec489aa8 LW |
2192 | uap->lcrh_rx = vendor->lcrh_rx; |
2193 | uap->lcrh_tx = vendor->lcrh_tx; | |
d8d8ffa4 | 2194 | uap->old_cr = 0; |
ea33640a | 2195 | uap->fifosize = vendor->get_fifosize(dev); |
1da177e4 LT |
2196 | uap->port.dev = &dev->dev; |
2197 | uap->port.mapbase = dev->res.start; | |
2198 | uap->port.membase = base; | |
2199 | uap->port.iotype = UPIO_MEM; | |
2200 | uap->port.irq = dev->irq[0]; | |
ffca2b11 | 2201 | uap->port.fifosize = uap->fifosize; |
1da177e4 LT |
2202 | uap->port.ops = &amba_pl011_pops; |
2203 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
2204 | uap->port.line = i; | |
787b0c1f | 2205 | pl011_dma_probe(&dev->dev, uap); |
1da177e4 | 2206 | |
c3d8b76f LW |
2207 | /* Ensure interrupts from this UART are masked and cleared */ |
2208 | writew(0, uap->port.membase + UART011_IMSC); | |
2209 | writew(0xffff, uap->port.membase + UART011_ICR); | |
2210 | ||
e8a7ba86 RK |
2211 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); |
2212 | ||
1da177e4 LT |
2213 | amba_ports[i] = uap; |
2214 | ||
2215 | amba_set_drvdata(dev, uap); | |
ef2889f7 TB |
2216 | |
2217 | if (!amba_reg.state) { | |
2218 | ret = uart_register_driver(&amba_reg); | |
2219 | if (ret < 0) { | |
2220 | pr_err("Failed to register AMBA-PL011 driver\n"); | |
2221 | return ret; | |
2222 | } | |
2223 | } | |
2224 | ||
1da177e4 LT |
2225 | ret = uart_add_one_port(&amba_reg, &uap->port); |
2226 | if (ret) { | |
1da177e4 | 2227 | amba_ports[i] = NULL; |
ef2889f7 | 2228 | uart_unregister_driver(&amba_reg); |
68b65f73 | 2229 | pl011_dma_remove(uap); |
1da177e4 | 2230 | } |
7f6d942a | 2231 | |
1da177e4 LT |
2232 | return ret; |
2233 | } | |
2234 | ||
2235 | static int pl011_remove(struct amba_device *dev) | |
2236 | { | |
2237 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1e7da053 | 2238 | bool busy = false; |
1da177e4 LT |
2239 | int i; |
2240 | ||
1da177e4 LT |
2241 | uart_remove_one_port(&amba_reg, &uap->port); |
2242 | ||
2243 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
2244 | if (amba_ports[i] == uap) | |
2245 | amba_ports[i] = NULL; | |
1e7da053 GL |
2246 | else if (amba_ports[i]) |
2247 | busy = true; | |
1da177e4 | 2248 | |
68b65f73 | 2249 | pl011_dma_remove(uap); |
1e7da053 GL |
2250 | if (!busy) |
2251 | uart_unregister_driver(&amba_reg); | |
1da177e4 LT |
2252 | return 0; |
2253 | } | |
2254 | ||
d0ce850d UH |
2255 | #ifdef CONFIG_PM_SLEEP |
2256 | static int pl011_suspend(struct device *dev) | |
b736b89f | 2257 | { |
d0ce850d | 2258 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2259 | |
2260 | if (!uap) | |
2261 | return -EINVAL; | |
2262 | ||
2263 | return uart_suspend_port(&amba_reg, &uap->port); | |
2264 | } | |
2265 | ||
d0ce850d | 2266 | static int pl011_resume(struct device *dev) |
b736b89f | 2267 | { |
d0ce850d | 2268 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2269 | |
2270 | if (!uap) | |
2271 | return -EINVAL; | |
2272 | ||
2273 | return uart_resume_port(&amba_reg, &uap->port); | |
2274 | } | |
2275 | #endif | |
2276 | ||
d0ce850d UH |
2277 | static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); |
2278 | ||
2c39c9e1 | 2279 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
2280 | { |
2281 | .id = 0x00041011, | |
2282 | .mask = 0x000fffff, | |
5926a295 AR |
2283 | .data = &vendor_arm, |
2284 | }, | |
2285 | { | |
2286 | .id = 0x00380802, | |
2287 | .mask = 0x00ffffff, | |
2288 | .data = &vendor_st, | |
1da177e4 LT |
2289 | }, |
2290 | { 0, 0 }, | |
2291 | }; | |
2292 | ||
60f7a33b DM |
2293 | MODULE_DEVICE_TABLE(amba, pl011_ids); |
2294 | ||
1da177e4 LT |
2295 | static struct amba_driver pl011_driver = { |
2296 | .drv = { | |
2297 | .name = "uart-pl011", | |
d0ce850d | 2298 | .pm = &pl011_dev_pm_ops, |
1da177e4 LT |
2299 | }, |
2300 | .id_table = pl011_ids, | |
2301 | .probe = pl011_probe, | |
2302 | .remove = pl011_remove, | |
2303 | }; | |
2304 | ||
2305 | static int __init pl011_init(void) | |
2306 | { | |
1da177e4 LT |
2307 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); |
2308 | ||
ef2889f7 | 2309 | return amba_driver_register(&pl011_driver); |
1da177e4 LT |
2310 | } |
2311 | ||
2312 | static void __exit pl011_exit(void) | |
2313 | { | |
2314 | amba_driver_unregister(&pl011_driver); | |
1da177e4 LT |
2315 | } |
2316 | ||
4dd9e742 AR |
2317 | /* |
2318 | * While this can be a module, if builtin it's most likely the console | |
2319 | * So let's leave module_exit but move module_init to an earlier place | |
2320 | */ | |
2321 | arch_initcall(pl011_init); | |
1da177e4 LT |
2322 | module_exit(pl011_exit); |
2323 | ||
2324 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
2325 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
2326 | MODULE_LICENSE("GPL"); |