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serial: pl011: Fix DMA ->flush_buffer()
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / amba-pl011.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1da177e4 2/*
1da177e4
LT		 3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
68b65f73 9 * Copyright (C) 2010 ST-Ericsson SA
1da177e4 10 *
1da177e4
LT		 11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
17 */
1da177e4 18
cb06ff10 19
1da177e4
LT		 20#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
23
24#include <linux/module.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
29#include <linux/device.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
a62c80e5
RK		 34#include <linux/amba/bus.h>
35#include <linux/amba/serial.h>
f8ce2547 36#include <linux/clk.h>
5a0e3ad6 37#include <linux/slab.h>
68b65f73
RK		 38#include <linux/dmaengine.h>
39#include <linux/dma-mapping.h>
40#include <linux/scatterlist.h>
c16d51a3 41#include <linux/delay.h>
258aea76 42#include <linux/types.h>
32614aad
ML		 43#include <linux/of.h>
44#include <linux/of_device.h>
258e0551 45#include <linux/pinctrl/consumer.h>
cb70706c 46#include <linux/sizes.h>
de609582 47#include <linux/io.h>
3db9ab0b 48#include <linux/acpi.h>
1da177e4 49
9f25bc51
RK		 50#include "amba-pl011.h"
51
1da177e4
LT		 52#define UART_NR 14
53
54#define SERIAL_AMBA_MAJOR 204
55#define SERIAL_AMBA_MINOR 64
56#define SERIAL_AMBA_NR UART_NR
57
58#define AMBA_ISR_PASS_LIMIT 256
59
b63d4f0f
RK		 60#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
61#define UART_DUMMY_DR_RX (1 << 16)
1da177e4 62
debb7f64
RK		 63static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
64 [REG_DR] = UART01x_DR,
debb7f64 65 [REG_FR] = UART01x_FR,
e4df9a80
RK		 66 [REG_LCRH_RX] = UART011_LCRH,
67 [REG_LCRH_TX] = UART011_LCRH,
debb7f64
RK		 68 [REG_IBRD] = UART011_IBRD,
69 [REG_FBRD] = UART011_FBRD,
debb7f64
RK		 70 [REG_CR] = UART011_CR,
71 [REG_IFLS] = UART011_IFLS,
72 [REG_IMSC] = UART011_IMSC,
73 [REG_RIS] = UART011_RIS,
74 [REG_MIS] = UART011_MIS,
75 [REG_ICR] = UART011_ICR,
76 [REG_DMACR] = UART011_DMACR,
debb7f64
RK		 77};
78
5926a295
AR		 79/* There is by now at least one vendor with differing details, so handle it */
80struct vendor_data {
439403bd 81 const u16 *reg_offset;
5926a295 82 unsigned int ifls;
0e125a5f
SG		 83 unsigned int fr_busy;
84 unsigned int fr_dsr;
85 unsigned int fr_cts;
86 unsigned int fr_ri;
d8a4995b 87 unsigned int inv_fr;
84c3e03b 88 bool access_32b;
ac3e3fb4 89 bool oversampling;
38d62436 90 bool dma_threshold;
4fd0690b 91 bool cts_event_workaround;
71eec483 92 bool always_enabled;
cefc2d1d 93 bool fixed_options;
78506f22 94
ea33640a 95 unsigned int (*get_fifosize)(struct amba_device *dev);
5926a295
AR		 96};
97
ea33640a 98static unsigned int get_fifosize_arm(struct amba_device *dev)
78506f22 99{
ea33640a 100 return amba_rev(dev) < 3 ? 16 : 32;
78506f22
JK		 101}
102
5926a295 103static struct vendor_data vendor_arm = {
439403bd 104 .reg_offset = pl011_std_offsets,
5926a295 105 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
0e125a5f
SG		 106 .fr_busy = UART01x_FR_BUSY,
107 .fr_dsr = UART01x_FR_DSR,
108 .fr_cts = UART01x_FR_CTS,
109 .fr_ri = UART011_FR_RI,
ac3e3fb4 110 .oversampling = false,
38d62436 111 .dma_threshold = false,
4fd0690b 112 .cts_event_workaround = false,
71eec483 113 .always_enabled = false,
cefc2d1d 114 .fixed_options = false,
78506f22 115 .get_fifosize = get_fifosize_arm,
5926a295
AR		 116};
117
d054b3ac 118static const struct vendor_data vendor_sbsa = {
439403bd 119 .reg_offset = pl011_std_offsets,
0e125a5f
SG		 120 .fr_busy = UART01x_FR_BUSY,
121 .fr_dsr = UART01x_FR_DSR,
122 .fr_cts = UART01x_FR_CTS,
123 .fr_ri = UART011_FR_RI,
1aabf523 124 .access_32b = true,
0dd1e247
AP		 125 .oversampling = false,
126 .dma_threshold = false,
127 .cts_event_workaround = false,
128 .always_enabled = true,
129 .fixed_options = true,
130};
131
37ef38f3 132#ifdef CONFIG_ACPI_SPCR_TABLE
d054b3ac 133static const struct vendor_data vendor_qdt_qdf2400_e44 = {
d8a4995b
CC		 134 .reg_offset = pl011_std_offsets,
135 .fr_busy = UART011_FR_TXFE,
136 .fr_dsr = UART01x_FR_DSR,
137 .fr_cts = UART01x_FR_CTS,
138 .fr_ri = UART011_FR_RI,
139 .inv_fr = UART011_FR_TXFE,
140 .access_32b = true,
141 .oversampling = false,
142 .dma_threshold = false,
143 .cts_event_workaround = false,
144 .always_enabled = true,
145 .fixed_options = true,
146};
37ef38f3 147#endif
d8a4995b 148
bf69ff8a
RK		 149static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
150 [REG_DR] = UART01x_DR,
151 [REG_ST_DMAWM] = ST_UART011_DMAWM,
152 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
153 [REG_FR] = UART01x_FR,
e4df9a80
RK		 154 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
155 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
bf69ff8a
RK		 156 [REG_IBRD] = UART011_IBRD,
157 [REG_FBRD] = UART011_FBRD,
bf69ff8a
RK		 158 [REG_CR] = UART011_CR,
159 [REG_IFLS] = UART011_IFLS,
160 [REG_IMSC] = UART011_IMSC,
161 [REG_RIS] = UART011_RIS,
162 [REG_MIS] = UART011_MIS,
163 [REG_ICR] = UART011_ICR,
164 [REG_DMACR] = UART011_DMACR,
165 [REG_ST_XFCR] = ST_UART011_XFCR,
166 [REG_ST_XON1] = ST_UART011_XON1,
167 [REG_ST_XON2] = ST_UART011_XON2,
168 [REG_ST_XOFF1] = ST_UART011_XOFF1,
169 [REG_ST_XOFF2] = ST_UART011_XOFF2,
170 [REG_ST_ITCR] = ST_UART011_ITCR,
171 [REG_ST_ITIP] = ST_UART011_ITIP,
172 [REG_ST_ABCR] = ST_UART011_ABCR,
173 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
174};
175
ea33640a 176static unsigned int get_fifosize_st(struct amba_device *dev)
78506f22
JK		 177{
178 return 64;
179}
180
5926a295 181static struct vendor_data vendor_st = {
bf69ff8a 182 .reg_offset = pl011_st_offsets,
5926a295 183 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
0e125a5f
SG		 184 .fr_busy = UART01x_FR_BUSY,
185 .fr_dsr = UART01x_FR_DSR,
186 .fr_cts = UART01x_FR_CTS,
187 .fr_ri = UART011_FR_RI,
ac3e3fb4 188 .oversampling = true,
38d62436 189 .dma_threshold = true,
4fd0690b 190 .cts_event_workaround = true,
71eec483 191 .always_enabled = false,
cefc2d1d 192 .fixed_options = false,
78506f22 193 .get_fifosize = get_fifosize_st,
1da177e4
LT		 194};
195
7ec75871
RK		 196static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
197 [REG_DR] = ZX_UART011_DR,
198 [REG_FR] = ZX_UART011_FR,
199 [REG_LCRH_RX] = ZX_UART011_LCRH,
200 [REG_LCRH_TX] = ZX_UART011_LCRH,
201 [REG_IBRD] = ZX_UART011_IBRD,
202 [REG_FBRD] = ZX_UART011_FBRD,
203 [REG_CR] = ZX_UART011_CR,
204 [REG_IFLS] = ZX_UART011_IFLS,
205 [REG_IMSC] = ZX_UART011_IMSC,
206 [REG_RIS] = ZX_UART011_RIS,
207 [REG_MIS] = ZX_UART011_MIS,
208 [REG_ICR] = ZX_UART011_ICR,
209 [REG_DMACR] = ZX_UART011_DMACR,
210};
211
9c267ddb
SG		 212static unsigned int get_fifosize_zte(struct amba_device *dev)
213{
214 return 16;
215}
216
2426fbc7 217static struct vendor_data vendor_zte = {
7ec75871
RK		 218 .reg_offset = pl011_zte_offsets,
219 .access_32b = true,
220 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
0e125a5f
SG		 221 .fr_busy = ZX_UART01x_FR_BUSY,
222 .fr_dsr = ZX_UART01x_FR_DSR,
223 .fr_cts = ZX_UART01x_FR_CTS,
224 .fr_ri = ZX_UART011_FR_RI,
9c267ddb 225 .get_fifosize = get_fifosize_zte,
7ec75871
RK		 226};
227
68b65f73 228/* Deals with DMA transactions */
ead76f32
LW		 229
230struct pl011_sgbuf {
231 struct scatterlist sg;
232 char *buf;
233};
234
235struct pl011_dmarx_data {
236 struct dma_chan *chan;
237 struct completion complete;
238 bool use_buf_b;
239 struct pl011_sgbuf sgbuf_a;
240 struct pl011_sgbuf sgbuf_b;
241 dma_cookie_t cookie;
242 bool running;
cb06ff10
CM		 243 struct timer_list timer;
244 unsigned int last_residue;
245 unsigned long last_jiffies;
246 bool auto_poll_rate;
247 unsigned int poll_rate;
248 unsigned int poll_timeout;
ead76f32
LW		 249};
250
68b65f73
RK		 251struct pl011_dmatx_data {
252 struct dma_chan *chan;
253 struct scatterlist sg;
254 char *buf;
255 bool queued;
256};
257
c19f12b5
RK		 258/*
259 * We wrap our port structure around the generic uart_port.
260 */
261struct uart_amba_port {
262 struct uart_port port;
debb7f64 263 const u16 *reg_offset;
c19f12b5
RK		 264 struct clk *clk;
265 const struct vendor_data *vendor;
68b65f73 266 unsigned int dmacr; /* dma control reg */
c19f12b5
RK		 267 unsigned int im; /* interrupt mask */
268 unsigned int old_status;
ffca2b11 269 unsigned int fifosize; /* vendor-specific */
d8d8ffa4 270 unsigned int old_cr; /* state during shutdown */
cefc2d1d 271 unsigned int fixed_baud; /* vendor-set fixed baud rate */
c19f12b5 272 char type[12];
68b65f73
RK		 273#ifdef CONFIG_DMA_ENGINE
274 /* DMA stuff */
ead76f32
LW		 275 bool using_tx_dma;
276 bool using_rx_dma;
277 struct pl011_dmarx_data dmarx;
68b65f73 278 struct pl011_dmatx_data dmatx;
1c9be310 279 bool dma_probed;
68b65f73
RK		 280#endif
281};
282
9f25bc51
RK		 283static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
284 unsigned int reg)
285{
debb7f64 286 return uap->reg_offset[reg];
9f25bc51
RK		 287}
288
b2a4e24c
RK		 289static unsigned int pl011_read(const struct uart_amba_port *uap,
290 unsigned int reg)
75836339 291{
84c3e03b
RK		 292 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
293
3b78fae7
TT		 294 return (uap->port.iotype == UPIO_MEM32) ?
295 readl_relaxed(addr) : readw_relaxed(addr);
75836339
RK		 296}
297
b2a4e24c
RK		 298static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
299 unsigned int reg)
75836339 300{
84c3e03b
RK		 301 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
302
3b78fae7 303 if (uap->port.iotype == UPIO_MEM32)
f5ce6edd 304 writel_relaxed(val, addr);
84c3e03b 305 else
f5ce6edd 306 writew_relaxed(val, addr);
75836339
RK		 307}
308
29772c4e
LW		 309/*
310 * Reads up to 256 characters from the FIFO or until it's empty and
311 * inserts them into the TTY layer. Returns the number of characters
312 * read from the FIFO.
313 */
314static int pl011_fifo_to_tty(struct uart_amba_port *uap)
315{
71a5cd8a
TT		 316 u16 status;
317 unsigned int ch, flag, max_count = 256;
29772c4e
LW		 318 int fifotaken = 0;
319
320 while (max_count--) {
9f25bc51 321 status = pl011_read(uap, REG_FR);
29772c4e
LW		 322 if (status & UART01x_FR_RXFE)
323 break;
324
325 /* Take chars from the FIFO and update status */
9f25bc51 326 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
29772c4e
LW		 327 flag = TTY_NORMAL;
328 uap->port.icount.rx++;
329 fifotaken++;
330
331 if (unlikely(ch & UART_DR_ERROR)) {
332 if (ch & UART011_DR_BE) {
333 ch &= ~(UART011_DR_FE | UART011_DR_PE);
334 uap->port.icount.brk++;
335 if (uart_handle_break(&uap->port))
336 continue;
337 } else if (ch & UART011_DR_PE)
338 uap->port.icount.parity++;
339 else if (ch & UART011_DR_FE)
340 uap->port.icount.frame++;
341 if (ch & UART011_DR_OE)
342 uap->port.icount.overrun++;
343
344 ch &= uap->port.read_status_mask;
345
346 if (ch & UART011_DR_BE)
347 flag = TTY_BREAK;
348 else if (ch & UART011_DR_PE)
349 flag = TTY_PARITY;
350 else if (ch & UART011_DR_FE)
351 flag = TTY_FRAME;
352 }
353
354 if (uart_handle_sysrq_char(&uap->port, ch & 255))
355 continue;
356
357 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
358 }
359
360 return fifotaken;
361}
362
363
68b65f73
RK		 364/*
365 * All the DMA operation mode stuff goes inside this ifdef.
366 * This assumes that you have a generic DMA device interface,
367 * no custom DMA interfaces are supported.
368 */
369#ifdef CONFIG_DMA_ENGINE
370
371#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
372
ead76f32
LW		 373static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
374 enum dma_data_direction dir)
375{
cb06ff10
CM		 376 dma_addr_t dma_addr;
377
378 sg->buf = dma_alloc_coherent(chan->device->dev,
379 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
ead76f32
LW		 380 if (!sg->buf)
381 return -ENOMEM;
382
cb06ff10
CM		 383 sg_init_table(&sg->sg, 1);
384 sg_set_page(&sg->sg, phys_to_page(dma_addr),
385 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
386 sg_dma_address(&sg->sg) = dma_addr;
c64be923 387 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
ead76f32 388
ead76f32
LW		 389 return 0;
390}
391
392static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
393 enum dma_data_direction dir)
394{
395 if (sg->buf) {
cb06ff10
CM		 396 dma_free_coherent(chan->device->dev,
397 PL011_DMA_BUFFER_SIZE, sg->buf,
398 sg_dma_address(&sg->sg));
ead76f32
LW		 399 }
400}
401
1c9be310 402static void pl011_dma_probe(struct uart_amba_port *uap)
68b65f73
RK		 403{
404 /* DMA is the sole user of the platform data right now */
574de559 405 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
1c9be310 406 struct device *dev = uap->port.dev;
68b65f73 407 struct dma_slave_config tx_conf = {
9f25bc51
RK		 408 .dst_addr = uap->port.mapbase +
409 pl011_reg_to_offset(uap, REG_DR),
68b65f73 410 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 411 .direction = DMA_MEM_TO_DEV,
68b65f73 412 .dst_maxburst = uap->fifosize >> 1,
258aea76 413 .device_fc = false,
68b65f73
RK		 414 };
415 struct dma_chan *chan;
416 dma_cap_mask_t mask;
417
1c9be310
JRO		 418 uap->dma_probed = true;
419 chan = dma_request_slave_channel_reason(dev, "tx");
420 if (IS_ERR(chan)) {
421 if (PTR_ERR(chan) == -EPROBE_DEFER) {
1c9be310
JRO		 422 uap->dma_probed = false;
423 return;
424 }
68b65f73 425
787b0c1f
AB		 426 /* We need platform data */
427 if (!plat || !plat->dma_filter) {
428 dev_info(uap->port.dev, "no DMA platform data\n");
429 return;
430 }
431
432 /* Try to acquire a generic DMA engine slave TX channel */
433 dma_cap_zero(mask);
434 dma_cap_set(DMA_SLAVE, mask);
435
436 chan = dma_request_channel(mask, plat->dma_filter,
437 plat->dma_tx_param);
438 if (!chan) {
439 dev_err(uap->port.dev, "no TX DMA channel!\n");
440 return;
441 }
68b65f73
RK		 442 }
443
444 dmaengine_slave_config(chan, &tx_conf);
445 uap->dmatx.chan = chan;
446
447 dev_info(uap->port.dev, "DMA channel TX %s\n",
448 dma_chan_name(uap->dmatx.chan));
ead76f32
LW		 449
450 /* Optionally make use of an RX channel as well */
787b0c1f 451 chan = dma_request_slave_channel(dev, "rx");
0d3c673e 452
d9e105ca 453 if (!chan && plat && plat->dma_rx_param) {
787b0c1f
AB		 454 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
455
456 if (!chan) {
457 dev_err(uap->port.dev, "no RX DMA channel!\n");
458 return;
459 }
460 }
461
462 if (chan) {
ead76f32 463 struct dma_slave_config rx_conf = {
9f25bc51
RK		 464 .src_addr = uap->port.mapbase +
465 pl011_reg_to_offset(uap, REG_DR),
ead76f32 466 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 467 .direction = DMA_DEV_TO_MEM,
b2aeb775 468 .src_maxburst = uap->fifosize >> 2,
258aea76 469 .device_fc = false,
ead76f32 470 };
2d3b7d6e
AJ		 471 struct dma_slave_caps caps;
472
473 /*
474 * Some DMA controllers provide information on their capabilities.
475 * If the controller does, check for suitable residue processing
476 * otherwise assime all is well.
477 */
478 if (0 == dma_get_slave_caps(chan, &caps)) {
479 if (caps.residue_granularity ==
480 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
481 dma_release_channel(chan);
482 dev_info(uap->port.dev,
483 "RX DMA disabled - no residue processing\n");
484 return;
485 }
486 }
ead76f32
LW		 487 dmaengine_slave_config(chan, &rx_conf);
488 uap->dmarx.chan = chan;
489
98267d33 490 uap->dmarx.auto_poll_rate = false;
8f898bfd 491 if (plat && plat->dma_rx_poll_enable) {
cb06ff10
CM		 492 /* Set poll rate if specified. */
493 if (plat->dma_rx_poll_rate) {
494 uap->dmarx.auto_poll_rate = false;
495 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
496 } else {
497 /*
498 * 100 ms defaults to poll rate if not
499 * specified. This will be adjusted with
500 * the baud rate at set_termios.
501 */
502 uap->dmarx.auto_poll_rate = true;
503 uap->dmarx.poll_rate = 100;
504 }
505 /* 3 secs defaults poll_timeout if not specified. */
506 if (plat->dma_rx_poll_timeout)
507 uap->dmarx.poll_timeout =
508 plat->dma_rx_poll_timeout;
509 else
510 uap->dmarx.poll_timeout = 3000;
98267d33
AJ		 511 } else if (!plat && dev->of_node) {
512 uap->dmarx.auto_poll_rate = of_property_read_bool(
513 dev->of_node, "auto-poll");
514 if (uap->dmarx.auto_poll_rate) {
515 u32 x;
516
517 if (0 == of_property_read_u32(dev->of_node,
518 "poll-rate-ms", &x))
519 uap->dmarx.poll_rate = x;
520 else
521 uap->dmarx.poll_rate = 100;
522 if (0 == of_property_read_u32(dev->of_node,
523 "poll-timeout-ms", &x))
524 uap->dmarx.poll_timeout = x;
525 else
526 uap->dmarx.poll_timeout = 3000;
527 }
528 }
ead76f32
LW		 529 dev_info(uap->port.dev, "DMA channel RX %s\n",
530 dma_chan_name(uap->dmarx.chan));
531 }
68b65f73
RK		 532}
533
68b65f73
RK		 534static void pl011_dma_remove(struct uart_amba_port *uap)
535{
68b65f73
RK		 536 if (uap->dmatx.chan)
537 dma_release_channel(uap->dmatx.chan);
ead76f32
LW		 538 if (uap->dmarx.chan)
539 dma_release_channel(uap->dmarx.chan);
68b65f73
RK		 540}
541
734745ca 542/* Forward declare these for the refill routine */
68b65f73 543static int pl011_dma_tx_refill(struct uart_amba_port *uap);
734745ca 544static void pl011_start_tx_pio(struct uart_amba_port *uap);
68b65f73
RK		 545
546/*
547 * The current DMA TX buffer has been sent.
548 * Try to queue up another DMA buffer.
549 */
550static void pl011_dma_tx_callback(void *data)
551{
552 struct uart_amba_port *uap = data;
553 struct pl011_dmatx_data *dmatx = &uap->dmatx;
554 unsigned long flags;
555 u16 dmacr;
556
557 spin_lock_irqsave(&uap->port.lock, flags);
558 if (uap->dmatx.queued)
559 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
560 DMA_TO_DEVICE);
561
562 dmacr = uap->dmacr;
563 uap->dmacr = dmacr & ~UART011_TXDMAE;
9f25bc51 564 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 565
566 /*
567 * If TX DMA was disabled, it means that we've stopped the DMA for
568 * some reason (eg, XOFF received, or we want to send an X-char.)
569 *
570 * Note: we need to be careful here of a potential race between DMA
571 * and the rest of the driver - if the driver disables TX DMA while
572 * a TX buffer completing, we must update the tx queued status to
573 * get further refills (hence we check dmacr).
574 */
575 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
576 uart_circ_empty(&uap->port.state->xmit)) {
577 uap->dmatx.queued = false;
578 spin_unlock_irqrestore(&uap->port.lock, flags);
579 return;
580 }
581
734745ca 582 if (pl011_dma_tx_refill(uap) <= 0)
68b65f73
RK		 583 /*
584 * We didn't queue a DMA buffer for some reason, but we
585 * have data pending to be sent. Re-enable the TX IRQ.
586 */
734745ca
DM		 587 pl011_start_tx_pio(uap);
588
68b65f73
RK		 589 spin_unlock_irqrestore(&uap->port.lock, flags);
590}
591
592/*
593 * Try to refill the TX DMA buffer.
594 * Locking: called with port lock held and IRQs disabled.
595 * Returns:
596 * 1 if we queued up a TX DMA buffer.
597 * 0 if we didn't want to handle this by DMA
598 * <0 on error
599 */
600static int pl011_dma_tx_refill(struct uart_amba_port *uap)
601{
602 struct pl011_dmatx_data *dmatx = &uap->dmatx;
603 struct dma_chan *chan = dmatx->chan;
604 struct dma_device *dma_dev = chan->device;
605 struct dma_async_tx_descriptor *desc;
606 struct circ_buf *xmit = &uap->port.state->xmit;
607 unsigned int count;
608
609 /*
610 * Try to avoid the overhead involved in using DMA if the
611 * transaction fits in the first half of the FIFO, by using
612 * the standard interrupt handling. This ensures that we
613 * issue a uart_write_wakeup() at the appropriate time.
614 */
615 count = uart_circ_chars_pending(xmit);
616 if (count < (uap->fifosize >> 1)) {
617 uap->dmatx.queued = false;
618 return 0;
619 }
620
621 /*
622 * Bodge: don't send the last character by DMA, as this
623 * will prevent XON from notifying us to restart DMA.
624 */
625 count -= 1;
626
627 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
628 if (count > PL011_DMA_BUFFER_SIZE)
629 count = PL011_DMA_BUFFER_SIZE;
630
631 if (xmit->tail < xmit->head)
632 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
633 else {
634 size_t first = UART_XMIT_SIZE - xmit->tail;
e2a545a6
AJ		 635 size_t second;
636
637 if (first > count)
638 first = count;
639 second = count - first;
68b65f73
RK		 640
641 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
642 if (second)
643 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
644 }
645
646 dmatx->sg.length = count;
647
648 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
649 uap->dmatx.queued = false;
650 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
651 return -EBUSY;
652 }
653
16052827 654 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
68b65f73
RK		 655 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
656 if (!desc) {
657 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
658 uap->dmatx.queued = false;
659 /*
660 * If DMA cannot be used right now, we complete this
661 * transaction via IRQ and let the TTY layer retry.
662 */
663 dev_dbg(uap->port.dev, "TX DMA busy\n");
664 return -EBUSY;
665 }
666
667 /* Some data to go along to the callback */
668 desc->callback = pl011_dma_tx_callback;
669 desc->callback_param = uap;
670
671 /* All errors should happen at prepare time */
672 dmaengine_submit(desc);
673
674 /* Fire the DMA transaction */
675 dma_dev->device_issue_pending(chan);
676
677 uap->dmacr |= UART011_TXDMAE;
9f25bc51 678 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 679 uap->dmatx.queued = true;
680
681 /*
682 * Now we know that DMA will fire, so advance the ring buffer
683 * with the stuff we just dispatched.
684 */
685 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
686 uap->port.icount.tx += count;
687
688 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
689 uart_write_wakeup(&uap->port);
690
691 return 1;
692}
693
694/*
695 * We received a transmit interrupt without a pending X-char but with
696 * pending characters.
697 * Locking: called with port lock held and IRQs disabled.
698 * Returns:
699 * false if we want to use PIO to transmit
700 * true if we queued a DMA buffer
701 */
702static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
703{
ead76f32 704 if (!uap->using_tx_dma)
68b65f73
RK		 705 return false;
706
707 /*
708 * If we already have a TX buffer queued, but received a
709 * TX interrupt, it will be because we've just sent an X-char.
710 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
711 */
712 if (uap->dmatx.queued) {
713 uap->dmacr |= UART011_TXDMAE;
9f25bc51 714 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73 715 uap->im &= ~UART011_TXIM;
9f25bc51 716 pl011_write(uap->im, uap, REG_IMSC);
68b65f73
RK		 717 return true;
718 }
719
720 /*
721 * We don't have a TX buffer queued, so try to queue one.
25985edc 722 * If we successfully queued a buffer, mask the TX IRQ.
68b65f73
RK		 723 */
724 if (pl011_dma_tx_refill(uap) > 0) {
725 uap->im &= ~UART011_TXIM;
9f25bc51 726 pl011_write(uap->im, uap, REG_IMSC);
68b65f73
RK		 727 return true;
728 }
729 return false;
730}
731
732/*
733 * Stop the DMA transmit (eg, due to received XOFF).
734 * Locking: called with port lock held and IRQs disabled.
735 */
736static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
737{
738 if (uap->dmatx.queued) {
739 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 740 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 741 }
742}
743
744/*
745 * Try to start a DMA transmit, or in the case of an XON/OFF
746 * character queued for send, try to get that character out ASAP.
747 * Locking: called with port lock held and IRQs disabled.
748 * Returns:
749 * false if we want the TX IRQ to be enabled
750 * true if we have a buffer queued
751 */
752static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
753{
754 u16 dmacr;
755
ead76f32 756 if (!uap->using_tx_dma)
68b65f73
RK		 757 return false;
758
759 if (!uap->port.x_char) {
760 /* no X-char, try to push chars out in DMA mode */
761 bool ret = true;
762
763 if (!uap->dmatx.queued) {
764 if (pl011_dma_tx_refill(uap) > 0) {
765 uap->im &= ~UART011_TXIM;
9f25bc51 766 pl011_write(uap->im, uap, REG_IMSC);
734745ca 767 } else
68b65f73 768 ret = false;
68b65f73
RK		 769 } else if (!(uap->dmacr & UART011_TXDMAE)) {
770 uap->dmacr |= UART011_TXDMAE;
9f25bc51 771 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 772 }
773 return ret;
774 }
775
776 /*
777 * We have an X-char to send. Disable DMA to prevent it loading
778 * the TX fifo, and then see if we can stuff it into the FIFO.
779 */
780 dmacr = uap->dmacr;
781 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 782 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73 783
9f25bc51 784 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
68b65f73
RK		 785 /*
786 * No space in the FIFO, so enable the transmit interrupt
787 * so we know when there is space. Note that once we've
788 * loaded the character, we should just re-enable DMA.
789 */
790 return false;
791 }
792
9f25bc51 793 pl011_write(uap->port.x_char, uap, REG_DR);
68b65f73
RK		 794 uap->port.icount.tx++;
795 uap->port.x_char = 0;
796
797 /* Success - restore the DMA state */
798 uap->dmacr = dmacr;
9f25bc51 799 pl011_write(dmacr, uap, REG_DMACR);
68b65f73
RK		 800
801 return true;
802}
803
804/*
805 * Flush the transmit buffer.
806 * Locking: called with port lock held and IRQs disabled.
807 */
808static void pl011_dma_flush_buffer(struct uart_port *port)
b83286bf
FE		 809__releases(&uap->port.lock)
810__acquires(&uap->port.lock)
68b65f73 811{
a5820c24
DT		 812 struct uart_amba_port *uap =
813 container_of(port, struct uart_amba_port, port);
68b65f73 814
ead76f32 815 if (!uap->using_tx_dma)
68b65f73
RK		 816 return;
817
417bce42
VW		 818 dmaengine_terminate_async(uap->dmatx.chan);
819
68b65f73
RK		 820 if (uap->dmatx.queued) {
821 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
822 DMA_TO_DEVICE);
823 uap->dmatx.queued = false;
824 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 825 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 826 }
827}
828
ead76f32
LW		 829static void pl011_dma_rx_callback(void *data);
830
831static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
832{
833 struct dma_chan *rxchan = uap->dmarx.chan;
ead76f32
LW		 834 struct pl011_dmarx_data *dmarx = &uap->dmarx;
835 struct dma_async_tx_descriptor *desc;
836 struct pl011_sgbuf *sgbuf;
837
838 if (!rxchan)
839 return -EIO;
840
841 /* Start the RX DMA job */
842 sgbuf = uap->dmarx.use_buf_b ?
843 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
16052827 844 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
a485df4b 845 DMA_DEV_TO_MEM,
ead76f32
LW		 846 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
847 /*
848 * If the DMA engine is busy and cannot prepare a
849 * channel, no big deal, the driver will fall back
850 * to interrupt mode as a result of this error code.
851 */
852 if (!desc) {
853 uap->dmarx.running = false;
854 dmaengine_terminate_all(rxchan);
855 return -EBUSY;
856 }
857
858 /* Some data to go along to the callback */
859 desc->callback = pl011_dma_rx_callback;
860 desc->callback_param = uap;
861 dmarx->cookie = dmaengine_submit(desc);
862 dma_async_issue_pending(rxchan);
863
864 uap->dmacr |= UART011_RXDMAE;
9f25bc51 865 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32
LW		 866 uap->dmarx.running = true;
867
868 uap->im &= ~UART011_RXIM;
9f25bc51 869 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 870
871 return 0;
872}
873
874/*
875 * This is called when either the DMA job is complete, or
876 * the FIFO timeout interrupt occurred. This must be called
877 * with the port spinlock uap->port.lock held.
878 */
879static void pl011_dma_rx_chars(struct uart_amba_port *uap,
880 u32 pending, bool use_buf_b,
881 bool readfifo)
882{
05c7cd39 883 struct tty_port *port = &uap->port.state->port;
ead76f32
LW		 884 struct pl011_sgbuf *sgbuf = use_buf_b ?
885 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
ead76f32
LW		 886 int dma_count = 0;
887 u32 fifotaken = 0; /* only used for vdbg() */
888
cb06ff10
CM		 889 struct pl011_dmarx_data *dmarx = &uap->dmarx;
890 int dmataken = 0;
891
892 if (uap->dmarx.poll_rate) {
893 /* The data can be taken by polling */
894 dmataken = sgbuf->sg.length - dmarx->last_residue;
895 /* Recalculate the pending size */
896 if (pending >= dmataken)
897 pending -= dmataken;
898 }
899
900 /* Pick the remain data from the DMA */
ead76f32 901 if (pending) {
ead76f32
LW		 902
903 /*
904 * First take all chars in the DMA pipe, then look in the FIFO.
905 * Note that tty_insert_flip_buf() tries to take as many chars
906 * as it can.
907 */
cb06ff10
CM		 908 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
909 pending);
ead76f32
LW		 910
911 uap->port.icount.rx += dma_count;
912 if (dma_count < pending)
913 dev_warn(uap->port.dev,
914 "couldn't insert all characters (TTY is full?)\n");
915 }
916
cb06ff10
CM		 917 /* Reset the last_residue for Rx DMA poll */
918 if (uap->dmarx.poll_rate)
919 dmarx->last_residue = sgbuf->sg.length;
920
ead76f32
LW		 921 /*
922 * Only continue with trying to read the FIFO if all DMA chars have
923 * been taken first.
924 */
925 if (dma_count == pending && readfifo) {
926 /* Clear any error flags */
75836339 927 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
9f25bc51 928 UART011_FEIS, uap, REG_ICR);
ead76f32
LW		 929
930 /*
931 * If we read all the DMA'd characters, and we had an
29772c4e
LW		 932 * incomplete buffer, that could be due to an rx error, or
933 * maybe we just timed out. Read any pending chars and check
934 * the error status.
935 *
936 * Error conditions will only occur in the FIFO, these will
937 * trigger an immediate interrupt and stop the DMA job, so we
938 * will always find the error in the FIFO, never in the DMA
939 * buffer.
ead76f32 940 */
29772c4e 941 fifotaken = pl011_fifo_to_tty(uap);
ead76f32
LW		 942 }
943
944 spin_unlock(&uap->port.lock);
945 dev_vdbg(uap->port.dev,
946 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
947 dma_count, fifotaken);
2e124b4a 948 tty_flip_buffer_push(port);
ead76f32
LW		 949 spin_lock(&uap->port.lock);
950}
951
952static void pl011_dma_rx_irq(struct uart_amba_port *uap)
953{
954 struct pl011_dmarx_data *dmarx = &uap->dmarx;
955 struct dma_chan *rxchan = dmarx->chan;
956 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
957 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
958 size_t pending;
959 struct dma_tx_state state;
960 enum dma_status dmastat;
961
962 /*
963 * Pause the transfer so we can trust the current counter,
964 * do this before we pause the PL011 block, else we may
965 * overflow the FIFO.
966 */
967 if (dmaengine_pause(rxchan))
968 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
969 dmastat = rxchan->device->device_tx_status(rxchan,
970 dmarx->cookie, &state);
971 if (dmastat != DMA_PAUSED)
972 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
973
974 /* Disable RX DMA - incoming data will wait in the FIFO */
975 uap->dmacr &= ~UART011_RXDMAE;
9f25bc51 976 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32
LW		 977 uap->dmarx.running = false;
978
979 pending = sgbuf->sg.length - state.residue;
980 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
981 /* Then we terminate the transfer - we now know our residue */
982 dmaengine_terminate_all(rxchan);
983
984 /*
985 * This will take the chars we have so far and insert
986 * into the framework.
987 */
988 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
989
990 /* Switch buffer & re-trigger DMA job */
991 dmarx->use_buf_b = !dmarx->use_buf_b;
992 if (pl011_dma_rx_trigger_dma(uap)) {
993 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
994 "fall back to interrupt mode\n");
995 uap->im |= UART011_RXIM;
9f25bc51 996 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 997 }
998}
999
1000static void pl011_dma_rx_callback(void *data)
1001{
1002 struct uart_amba_port *uap = data;
1003 struct pl011_dmarx_data *dmarx = &uap->dmarx;
6dc01aa6 1004 struct dma_chan *rxchan = dmarx->chan;
ead76f32 1005 bool lastbuf = dmarx->use_buf_b;
6dc01aa6
CM		 1006 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1007 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1008 size_t pending;
1009 struct dma_tx_state state;
ead76f32
LW		 1010 int ret;
1011
1012 /*
1013 * This completion interrupt occurs typically when the
1014 * RX buffer is totally stuffed but no timeout has yet
1015 * occurred. When that happens, we just want the RX
1016 * routine to flush out the secondary DMA buffer while
1017 * we immediately trigger the next DMA job.
1018 */
1019 spin_lock_irq(&uap->port.lock);
6dc01aa6
CM		 1020 /*
1021 * Rx data can be taken by the UART interrupts during
1022 * the DMA irq handler. So we check the residue here.
1023 */
1024 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1025 pending = sgbuf->sg.length - state.residue;
1026 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1027 /* Then we terminate the transfer - we now know our residue */
1028 dmaengine_terminate_all(rxchan);
1029
ead76f32
LW		 1030 uap->dmarx.running = false;
1031 dmarx->use_buf_b = !lastbuf;
1032 ret = pl011_dma_rx_trigger_dma(uap);
1033
6dc01aa6 1034 pl011_dma_rx_chars(uap, pending, lastbuf, false);
ead76f32
LW		 1035 spin_unlock_irq(&uap->port.lock);
1036 /*
1037 * Do this check after we picked the DMA chars so we don't
1038 * get some IRQ immediately from RX.
1039 */
1040 if (ret) {
1041 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1042 "fall back to interrupt mode\n");
1043 uap->im |= UART011_RXIM;
9f25bc51 1044 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1045 }
1046}
1047
1048/*
1049 * Stop accepting received characters, when we're shutting down or
1050 * suspending this port.
1051 * Locking: called with port lock held and IRQs disabled.
1052 */
1053static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1054{
1055 /* FIXME. Just disable the DMA enable */
1056 uap->dmacr &= ~UART011_RXDMAE;
9f25bc51 1057 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32 1058}
68b65f73 1059
cb06ff10
CM		 1060/*
1061 * Timer handler for Rx DMA polling.
1062 * Every polling, It checks the residue in the dma buffer and transfer
1063 * data to the tty. Also, last_residue is updated for the next polling.
1064 */
f7f73096 1065static void pl011_dma_rx_poll(struct timer_list *t)
cb06ff10 1066{
f7f73096 1067 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
cb06ff10
CM		 1068 struct tty_port *port = &uap->port.state->port;
1069 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1070 struct dma_chan *rxchan = uap->dmarx.chan;
1071 unsigned long flags = 0;
1072 unsigned int dmataken = 0;
1073 unsigned int size = 0;
1074 struct pl011_sgbuf *sgbuf;
1075 int dma_count;
1076 struct dma_tx_state state;
1077
1078 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1079 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1080 if (likely(state.residue < dmarx->last_residue)) {
1081 dmataken = sgbuf->sg.length - dmarx->last_residue;
1082 size = dmarx->last_residue - state.residue;
1083 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1084 size);
1085 if (dma_count == size)
1086 dmarx->last_residue = state.residue;
1087 dmarx->last_jiffies = jiffies;
1088 }
1089 tty_flip_buffer_push(port);
1090
1091 /*
1092 * If no data is received in poll_timeout, the driver will fall back
1093 * to interrupt mode. We will retrigger DMA at the first interrupt.
1094 */
1095 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1096 > uap->dmarx.poll_timeout) {
1097
1098 spin_lock_irqsave(&uap->port.lock, flags);
1099 pl011_dma_rx_stop(uap);
c25a1ad7 1100 uap->im |= UART011_RXIM;
9f25bc51 1101 pl011_write(uap->im, uap, REG_IMSC);
cb06ff10
CM		 1102 spin_unlock_irqrestore(&uap->port.lock, flags);
1103
1104 uap->dmarx.running = false;
1105 dmaengine_terminate_all(rxchan);
1106 del_timer(&uap->dmarx.timer);
1107 } else {
1108 mod_timer(&uap->dmarx.timer,
1109 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1110 }
1111}
1112
68b65f73
RK		 1113static void pl011_dma_startup(struct uart_amba_port *uap)
1114{
ead76f32
LW		 1115 int ret;
1116
1c9be310
JRO		 1117 if (!uap->dma_probed)
1118 pl011_dma_probe(uap);
1119
68b65f73
RK		 1120 if (!uap->dmatx.chan)
1121 return;
1122
4c0be45b 1123 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
68b65f73
RK		 1124 if (!uap->dmatx.buf) {
1125 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1126 uap->port.fifosize = uap->fifosize;
1127 return;
1128 }
1129
1130 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1131
1132 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1133 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
ead76f32
LW		 1134 uap->using_tx_dma = true;
1135
1136 if (!uap->dmarx.chan)
1137 goto skip_rx;
1138
1139 /* Allocate and map DMA RX buffers */
1140 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1141 DMA_FROM_DEVICE);
1142 if (ret) {
1143 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1144 "RX buffer A", ret);
1145 goto skip_rx;
1146 }
68b65f73 1147
ead76f32
LW		 1148 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1149 DMA_FROM_DEVICE);
1150 if (ret) {
1151 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1152 "RX buffer B", ret);
1153 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1154 DMA_FROM_DEVICE);
1155 goto skip_rx;
1156 }
1157
1158 uap->using_rx_dma = true;
68b65f73 1159
ead76f32 1160skip_rx:
68b65f73
RK		 1161 /* Turn on DMA error (RX/TX will be enabled on demand) */
1162 uap->dmacr |= UART011_DMAONERR;
9f25bc51 1163 pl011_write(uap->dmacr, uap, REG_DMACR);
38d62436
RK		 1164
1165 /*
1166 * ST Micro variants has some specific dma burst threshold
1167 * compensation. Set this to 16 bytes, so burst will only
1168 * be issued above/below 16 bytes.
1169 */
1170 if (uap->vendor->dma_threshold)
75836339 1171 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
9f25bc51 1172 uap, REG_ST_DMAWM);
ead76f32
LW		 1173
1174 if (uap->using_rx_dma) {
1175 if (pl011_dma_rx_trigger_dma(uap))
1176 dev_dbg(uap->port.dev, "could not trigger initial "
1177 "RX DMA job, fall back to interrupt mode\n");
cb06ff10 1178 if (uap->dmarx.poll_rate) {
f7f73096 1179 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
cb06ff10
CM		 1180 mod_timer(&uap->dmarx.timer,
1181 jiffies +
1182 msecs_to_jiffies(uap->dmarx.poll_rate));
1183 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1184 uap->dmarx.last_jiffies = jiffies;
1185 }
ead76f32 1186 }
68b65f73
RK		 1187}
1188
1189static void pl011_dma_shutdown(struct uart_amba_port *uap)
1190{
ead76f32 1191 if (!(uap->using_tx_dma || uap->using_rx_dma))
68b65f73
RK		 1192 return;
1193
1194 /* Disable RX and TX DMA */
0e125a5f 1195 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
2f2fd089 1196 cpu_relax();
68b65f73
RK		 1197
1198 spin_lock_irq(&uap->port.lock);
1199 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
9f25bc51 1200 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 1201 spin_unlock_irq(&uap->port.lock);
1202
ead76f32
LW		 1203 if (uap->using_tx_dma) {
1204 /* In theory, this should already be done by pl011_dma_flush_buffer */
1205 dmaengine_terminate_all(uap->dmatx.chan);
1206 if (uap->dmatx.queued) {
1207 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1208 DMA_TO_DEVICE);
1209 uap->dmatx.queued = false;
1210 }
1211
1212 kfree(uap->dmatx.buf);
1213 uap->using_tx_dma = false;
68b65f73
RK		 1214 }
1215
ead76f32
LW		 1216 if (uap->using_rx_dma) {
1217 dmaengine_terminate_all(uap->dmarx.chan);
1218 /* Clean up the RX DMA */
1219 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1220 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
cb06ff10
CM		 1221 if (uap->dmarx.poll_rate)
1222 del_timer_sync(&uap->dmarx.timer);
ead76f32
LW		 1223 uap->using_rx_dma = false;
1224 }
1225}
68b65f73 1226
ead76f32
LW		 1227static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1228{
1229 return uap->using_rx_dma;
68b65f73
RK		 1230}
1231
ead76f32
LW		 1232static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1233{
1234 return uap->using_rx_dma && uap->dmarx.running;
1235}
1236
68b65f73
RK		 1237#else
1238/* Blank functions if the DMA engine is not available */
1c9be310 1239static inline void pl011_dma_probe(struct uart_amba_port *uap)
68b65f73
RK		 1240{
1241}
1242
1243static inline void pl011_dma_remove(struct uart_amba_port *uap)
1244{
1245}
1246
1247static inline void pl011_dma_startup(struct uart_amba_port *uap)
1248{
1249}
1250
1251static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1252{
1253}
1254
1255static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1256{
1257 return false;
1258}
1259
1260static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1261{
1262}
1263
1264static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1265{
1266 return false;
1267}
1268
ead76f32
LW		 1269static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1270{
1271}
1272
1273static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1274{
1275}
1276
1277static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1278{
1279 return -EIO;
1280}
1281
1282static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1283{
1284 return false;
1285}
1286
1287static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1288{
1289 return false;
1290}
1291
68b65f73
RK		 1292#define pl011_dma_flush_buffer NULL
1293#endif
1294
b129a8cc 1295static void pl011_stop_tx(struct uart_port *port)
1da177e4 1296{
a5820c24
DT		 1297 struct uart_amba_port *uap =
1298 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1299
1300 uap->im &= ~UART011_TXIM;
9f25bc51 1301 pl011_write(uap->im, uap, REG_IMSC);
68b65f73 1302 pl011_dma_tx_stop(uap);
1da177e4
LT		 1303}
1304
7d05587c 1305static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
734745ca
DM		 1306
1307/* Start TX with programmed I/O only (no DMA) */
1308static void pl011_start_tx_pio(struct uart_amba_port *uap)
1309{
7d05587c
J		 1310 if (pl011_tx_chars(uap, false)) {
1311 uap->im |= UART011_TXIM;
1312 pl011_write(uap->im, uap, REG_IMSC);
1313 }
734745ca
DM		 1314}
1315
b129a8cc 1316static void pl011_start_tx(struct uart_port *port)
1da177e4 1317{
a5820c24
DT		 1318 struct uart_amba_port *uap =
1319 container_of(port, struct uart_amba_port, port);
1da177e4 1320
734745ca
DM		 1321 if (!pl011_dma_tx_start(uap))
1322 pl011_start_tx_pio(uap);
1da177e4
LT		 1323}
1324
1325static void pl011_stop_rx(struct uart_port *port)
1326{
a5820c24
DT		 1327 struct uart_amba_port *uap =
1328 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1329
1330 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1331 UART011_PEIM|UART011_BEIM|UART011_OEIM);
9f25bc51 1332 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1333
1334 pl011_dma_rx_stop(uap);
1da177e4
LT		 1335}
1336
1337static void pl011_enable_ms(struct uart_port *port)
1338{
a5820c24
DT		 1339 struct uart_amba_port *uap =
1340 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1341
1342 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
9f25bc51 1343 pl011_write(uap->im, uap, REG_IMSC);
1da177e4
LT		 1344}
1345
7d12e780 1346static void pl011_rx_chars(struct uart_amba_port *uap)
b83286bf
FE		 1347__releases(&uap->port.lock)
1348__acquires(&uap->port.lock)
1da177e4 1349{
29772c4e 1350 pl011_fifo_to_tty(uap);
1da177e4 1351
2389b272 1352 spin_unlock(&uap->port.lock);
2e124b4a 1353 tty_flip_buffer_push(&uap->port.state->port);
ead76f32
LW		 1354 /*
1355 * If we were temporarily out of DMA mode for a while,
1356 * attempt to switch back to DMA mode again.
1357 */
1358 if (pl011_dma_rx_available(uap)) {
1359 if (pl011_dma_rx_trigger_dma(uap)) {
1360 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1361 "fall back to interrupt mode again\n");
1362 uap->im |= UART011_RXIM;
9f25bc51 1363 pl011_write(uap->im, uap, REG_IMSC);
cb06ff10 1364 } else {
89fa28db 1365#ifdef CONFIG_DMA_ENGINE
cb06ff10
CM		 1366 /* Start Rx DMA poll */
1367 if (uap->dmarx.poll_rate) {
1368 uap->dmarx.last_jiffies = jiffies;
1369 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1370 mod_timer(&uap->dmarx.timer,
1371 jiffies +
1372 msecs_to_jiffies(uap->dmarx.poll_rate));
1373 }
89fa28db 1374#endif
cb06ff10 1375 }
ead76f32 1376 }
2389b272 1377 spin_lock(&uap->port.lock);
1da177e4
LT		 1378}
1379
1e84d223
DM		 1380static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1381 bool from_irq)
734745ca 1382{
1e84d223 1383 if (unlikely(!from_irq) &&
9f25bc51 1384 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1e84d223
DM		 1385 return false; /* unable to transmit character */
1386
9f25bc51 1387 pl011_write(c, uap, REG_DR);
734745ca
DM		 1388 uap->port.icount.tx++;
1389
1e84d223 1390 return true;
734745ca
DM		 1391}
1392
7d05587c
J		 1393/* Returns true if tx interrupts have to be (kept) enabled */
1394static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1da177e4 1395{
ebd2c8f6 1396 struct circ_buf *xmit = &uap->port.state->xmit;
1e84d223 1397 int count = uap->fifosize >> 1;
734745ca 1398
1da177e4 1399 if (uap->port.x_char) {
1e84d223 1400 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
7d05587c 1401 return true;
1da177e4 1402 uap->port.x_char = 0;
734745ca 1403 --count;
1da177e4
LT		 1404 }
1405 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
b129a8cc 1406 pl011_stop_tx(&uap->port);
7d05587c 1407 return false;
1da177e4
LT		 1408 }
1409
68b65f73
RK		 1410 /* If we are using DMA mode, try to send some characters. */
1411 if (pl011_dma_tx_irq(uap))
7d05587c 1412 return true;
68b65f73 1413
1e84d223
DM		 1414 do {
1415 if (likely(from_irq) && count-- == 0)
1da177e4 1416 break;
1e84d223
DM		 1417
1418 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1419 break;
1420
1421 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1422 } while (!uart_circ_empty(xmit));
1da177e4
LT		 1423
1424 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1425 uart_write_wakeup(&uap->port);
1426
7d05587c 1427 if (uart_circ_empty(xmit)) {
b129a8cc 1428 pl011_stop_tx(&uap->port);
7d05587c
J		 1429 return false;
1430 }
1431 return true;
1da177e4
LT		 1432}
1433
1434static void pl011_modem_status(struct uart_amba_port *uap)
1435{
1436 unsigned int status, delta;
1437
9f25bc51 1438 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1da177e4
LT		 1439
1440 delta = status ^ uap->old_status;
1441 uap->old_status = status;
1442
1443 if (!delta)
1444 return;
1445
1446 if (delta & UART01x_FR_DCD)
1447 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1448
0e125a5f 1449 if (delta & uap->vendor->fr_dsr)
1da177e4
LT		 1450 uap->port.icount.dsr++;
1451
0e125a5f
SG		 1452 if (delta & uap->vendor->fr_cts)
1453 uart_handle_cts_change(&uap->port,
1454 status & uap->vendor->fr_cts);
1da177e4 1455
bdc04e31 1456 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1da177e4
LT		 1457}
1458
9c4ef4b0
AP		 1459static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1460{
1461 unsigned int dummy_read;
1462
1463 if (!uap->vendor->cts_event_workaround)
1464 return;
1465
1466 /* workaround to make sure that all bits are unlocked.. */
9f25bc51 1467 pl011_write(0x00, uap, REG_ICR);
9c4ef4b0
AP		 1468
1469 /*
1470 * WA: introduce 26ns(1 uart clk) delay before W1C;
1471 * single apb access will incur 2 pclk(133.12Mhz) delay,
1472 * so add 2 dummy reads
1473 */
9f25bc51
RK		 1474 dummy_read = pl011_read(uap, REG_ICR);
1475 dummy_read = pl011_read(uap, REG_ICR);
9c4ef4b0
AP		 1476}
1477
7d12e780 1478static irqreturn_t pl011_int(int irq, void *dev_id)
1da177e4
LT		 1479{
1480 struct uart_amba_port *uap = dev_id;
963cc981 1481 unsigned long flags;
1da177e4 1482 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
075167ed 1483 u16 imsc;
1da177e4
LT		 1484 int handled = 0;
1485
963cc981 1486 spin_lock_irqsave(&uap->port.lock, flags);
9f25bc51
RK		 1487 imsc = pl011_read(uap, REG_IMSC);
1488 status = pl011_read(uap, REG_RIS) & imsc;
1da177e4
LT		 1489 if (status) {
1490 do {
9c4ef4b0 1491 check_apply_cts_event_workaround(uap);
f11c9841 1492
75836339
RK		 1493 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1494 UART011_RXIS),
9f25bc51 1495 uap, REG_ICR);
1da177e4 1496
ead76f32
LW		 1497 if (status & (UART011_RTIS|UART011_RXIS)) {
1498 if (pl011_dma_rx_running(uap))
1499 pl011_dma_rx_irq(uap);
1500 else
1501 pl011_rx_chars(uap);
1502 }
1da177e4
LT		 1503 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1504 UART011_CTSMIS|UART011_RIMIS))
1505 pl011_modem_status(uap);
1e84d223
DM		 1506 if (status & UART011_TXIS)
1507 pl011_tx_chars(uap, true);
1da177e4 1508
4fd0690b 1509 if (pass_counter-- == 0)
1da177e4
LT		 1510 break;
1511
9f25bc51 1512 status = pl011_read(uap, REG_RIS) & imsc;
1da177e4
LT		 1513 } while (status != 0);
1514 handled = 1;
1515 }
1516
963cc981 1517 spin_unlock_irqrestore(&uap->port.lock, flags);
1da177e4
LT		 1518
1519 return IRQ_RETVAL(handled);
1520}
1521
e643f87f 1522static unsigned int pl011_tx_empty(struct uart_port *port)
1da177e4 1523{
a5820c24
DT		 1524 struct uart_amba_port *uap =
1525 container_of(port, struct uart_amba_port, port);
d8a4995b
CC		 1526
1527 /* Allow feature register bits to be inverted to work around errata */
1528 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1529
0e125a5f
SG		 1530 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1531 0 : TIOCSER_TEMT;
1da177e4
LT		 1532}
1533
e643f87f 1534static unsigned int pl011_get_mctrl(struct uart_port *port)
1da177e4 1535{
a5820c24
DT		 1536 struct uart_amba_port *uap =
1537 container_of(port, struct uart_amba_port, port);
1da177e4 1538 unsigned int result = 0;
9f25bc51 1539 unsigned int status = pl011_read(uap, REG_FR);
1da177e4 1540
5159f407 1541#define TIOCMBIT(uartbit, tiocmbit) \
1da177e4
LT		 1542 if (status & uartbit) \
1543 result |= tiocmbit
1544
5159f407 1545 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
0e125a5f
SG		 1546 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1547 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1548 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
5159f407 1549#undef TIOCMBIT
1da177e4
LT		 1550 return result;
1551}
1552
1553static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1554{
a5820c24
DT		 1555 struct uart_amba_port *uap =
1556 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1557 unsigned int cr;
1558
9f25bc51 1559 cr = pl011_read(uap, REG_CR);
1da177e4 1560
5159f407 1561#define TIOCMBIT(tiocmbit, uartbit) \
1da177e4
LT		 1562 if (mctrl & tiocmbit) \
1563 cr |= uartbit; \
1564 else \
1565 cr &= ~uartbit
1566
5159f407
JS		 1567 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1568 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1569 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1570 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1571 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
3b43816f 1572
2a76fa28 1573 if (port->status & UPSTAT_AUTORTS) {
3b43816f
RV		 1574 /* We need to disable auto-RTS if we want to turn RTS off */
1575 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1576 }
5159f407 1577#undef TIOCMBIT
1da177e4 1578
9f25bc51 1579 pl011_write(cr, uap, REG_CR);
1da177e4
LT		 1580}
1581
1582static void pl011_break_ctl(struct uart_port *port, int break_state)
1583{
a5820c24
DT		 1584 struct uart_amba_port *uap =
1585 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1586 unsigned long flags;
1587 unsigned int lcr_h;
1588
1589 spin_lock_irqsave(&uap->port.lock, flags);
e4df9a80 1590 lcr_h = pl011_read(uap, REG_LCRH_TX);
1da177e4
LT		 1591 if (break_state == -1)
1592 lcr_h |= UART01x_LCRH_BRK;
1593 else
1594 lcr_h &= ~UART01x_LCRH_BRK;
e4df9a80 1595 pl011_write(lcr_h, uap, REG_LCRH_TX);
1da177e4
LT		 1596 spin_unlock_irqrestore(&uap->port.lock, flags);
1597}
1598
84b5ae15 1599#ifdef CONFIG_CONSOLE_POLL
5c8124a0
AV		 1600
1601static void pl011_quiesce_irqs(struct uart_port *port)
1602{
a5820c24
DT		 1603 struct uart_amba_port *uap =
1604 container_of(port, struct uart_amba_port, port);
5c8124a0 1605
9f25bc51 1606 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
5c8124a0
AV		 1607 /*
1608 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1609 * we simply mask it. start_tx() will unmask it.
1610 *
1611 * Note we can race with start_tx(), and if the race happens, the
1612 * polling user might get another interrupt just after we clear it.
1613 * But it should be OK and can happen even w/o the race, e.g.
1614 * controller immediately got some new data and raised the IRQ.
1615 *
1616 * And whoever uses polling routines assumes that it manages the device
1617 * (including tx queue), so we're also fine with start_tx()'s caller
1618 * side.
1619 */
9f25bc51
RK		 1620 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1621 REG_IMSC);
5c8124a0
AV		 1622}
1623
e643f87f 1624static int pl011_get_poll_char(struct uart_port *port)
84b5ae15 1625{
a5820c24
DT		 1626 struct uart_amba_port *uap =
1627 container_of(port, struct uart_amba_port, port);
84b5ae15
JW		 1628 unsigned int status;
1629
5c8124a0
AV		 1630 /*
1631 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1632 * debugger.
1633 */
1634 pl011_quiesce_irqs(port);
1635
9f25bc51 1636 status = pl011_read(uap, REG_FR);
f5316b4a
JW		 1637 if (status & UART01x_FR_RXFE)
1638 return NO_POLL_CHAR;
84b5ae15 1639
9f25bc51 1640 return pl011_read(uap, REG_DR);
84b5ae15
JW		 1641}
1642
e643f87f 1643static void pl011_put_poll_char(struct uart_port *port,
84b5ae15
JW		 1644 unsigned char ch)
1645{
a5820c24
DT		 1646 struct uart_amba_port *uap =
1647 container_of(port, struct uart_amba_port, port);
84b5ae15 1648
9f25bc51 1649 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2f2fd089 1650 cpu_relax();
84b5ae15 1651
9f25bc51 1652 pl011_write(ch, uap, REG_DR);
84b5ae15
JW		 1653}
1654
1655#endif /* CONFIG_CONSOLE_POLL */
1656
b3564c2c 1657static int pl011_hwinit(struct uart_port *port)
1da177e4 1658{
a5820c24
DT		 1659 struct uart_amba_port *uap =
1660 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1661 int retval;
1662
78d80c5a 1663 /* Optionaly enable pins to be muxed in and configured */
2b996fc5 1664 pinctrl_pm_select_default_state(port->dev);
78d80c5a 1665
1da177e4
LT		 1666 /*
1667 * Try to enable the clock producer.
1668 */
1c4c4394 1669 retval = clk_prepare_enable(uap->clk);
1da177e4 1670 if (retval)
7f6d942a 1671 return retval;
1da177e4
LT		 1672
1673 uap->port.uartclk = clk_get_rate(uap->clk);
1674
9b96fbac 1675 /* Clear pending error and receive interrupts */
75836339
RK		 1676 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1677 UART011_FEIS | UART011_RTIS | UART011_RXIS,
9f25bc51 1678 uap, REG_ICR);
9b96fbac 1679
b3564c2c
AV		 1680 /*
1681 * Save interrupts enable mask, and enable RX interrupts in case if
1682 * the interrupt is used for NMI entry.
1683 */
9f25bc51
RK		 1684 uap->im = pl011_read(uap, REG_IMSC);
1685 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
b3564c2c 1686
574de559 1687 if (dev_get_platdata(uap->port.dev)) {
b3564c2c
AV		 1688 struct amba_pl011_data *plat;
1689
574de559 1690 plat = dev_get_platdata(uap->port.dev);
b3564c2c
AV		 1691 if (plat->init)
1692 plat->init();
1693 }
1694 return 0;
b3564c2c
AV		 1695}
1696
7fe9a5a9
RK		 1697static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1698{
e4df9a80
RK		 1699 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1700 pl011_reg_to_offset(uap, REG_LCRH_TX);
7fe9a5a9
RK		 1701}
1702
b60f2f66
JM		 1703static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1704{
e4df9a80 1705 pl011_write(lcr_h, uap, REG_LCRH_RX);
7fe9a5a9 1706 if (pl011_split_lcrh(uap)) {
b60f2f66
JM		 1707 int i;
1708 /*
1709 * Wait 10 PCLKs before writing LCRH_TX register,
1710 * to get this delay write read only register 10 times
1711 */
1712 for (i = 0; i < 10; ++i)
9f25bc51 1713 pl011_write(0xff, uap, REG_MIS);
e4df9a80 1714 pl011_write(lcr_h, uap, REG_LCRH_TX);
b60f2f66
JM		 1715 }
1716}
1717
867b8e8e
AP		 1718static int pl011_allocate_irq(struct uart_amba_port *uap)
1719{
9f25bc51 1720 pl011_write(uap->im, uap, REG_IMSC);
867b8e8e
AP		 1721
1722 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1723}
1724
1725/*
1726 * Enable interrupts, only timeouts when using DMA
1727 * if initial RX DMA job failed, start in interrupt mode
1728 * as well.
1729 */
1730static void pl011_enable_interrupts(struct uart_amba_port *uap)
1731{
c4207f58
DM		 1732 unsigned int i;
1733
867b8e8e
AP		 1734 spin_lock_irq(&uap->port.lock);
1735
1736 /* Clear out any spuriously appearing RX interrupts */
9f25bc51 1737 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
c4207f58
DM		 1738
1739 /*
1740 * RXIS is asserted only when the RX FIFO transitions from below
1741 * to above the trigger threshold. If the RX FIFO is already
1742 * full to the threshold this can't happen and RXIS will now be
1743 * stuck off. Drain the RX FIFO explicitly to fix this:
1744 */
1745 for (i = 0; i < uap->fifosize * 2; ++i) {
1746 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1747 break;
1748
1749 pl011_read(uap, REG_DR);
1750 }
1751
867b8e8e
AP		 1752 uap->im = UART011_RTIM;
1753 if (!pl011_dma_rx_running(uap))
1754 uap->im |= UART011_RXIM;
9f25bc51 1755 pl011_write(uap->im, uap, REG_IMSC);
867b8e8e
AP		 1756 spin_unlock_irq(&uap->port.lock);
1757}
1758
b3564c2c
AV		 1759static int pl011_startup(struct uart_port *port)
1760{
a5820c24
DT		 1761 struct uart_amba_port *uap =
1762 container_of(port, struct uart_amba_port, port);
734745ca 1763 unsigned int cr;
b3564c2c
AV		 1764 int retval;
1765
1766 retval = pl011_hwinit(port);
1767 if (retval)
1768 goto clk_dis;
1769
867b8e8e 1770 retval = pl011_allocate_irq(uap);
1da177e4
LT		 1771 if (retval)
1772 goto clk_dis;
1773
9f25bc51 1774 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1da177e4 1775
734745ca 1776 spin_lock_irq(&uap->port.lock);
570d2910 1777
d8d8ffa4
SKS		 1778 /* restore RTS and DTR */
1779 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1780 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
9f25bc51 1781 pl011_write(cr, uap, REG_CR);
1da177e4 1782
fe433907
JM		 1783 spin_unlock_irq(&uap->port.lock);
1784
1da177e4
LT		 1785 /*
1786 * initialise the old status of the modem signals
1787 */
9f25bc51 1788 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1da177e4 1789
68b65f73
RK		 1790 /* Startup DMA */
1791 pl011_dma_startup(uap);
1792
867b8e8e 1793 pl011_enable_interrupts(uap);
1da177e4
LT		 1794
1795 return 0;
1796
1797 clk_dis:
1c4c4394 1798 clk_disable_unprepare(uap->clk);
1da177e4
LT		 1799 return retval;
1800}
1801
0dd1e247
AP		 1802static int sbsa_uart_startup(struct uart_port *port)
1803{
1804 struct uart_amba_port *uap =
1805 container_of(port, struct uart_amba_port, port);
1806 int retval;
1807
1808 retval = pl011_hwinit(port);
1809 if (retval)
1810 return retval;
1811
1812 retval = pl011_allocate_irq(uap);
1813 if (retval)
1814 return retval;
1815
1816 /* The SBSA UART does not support any modem status lines. */
1817 uap->old_status = 0;
1818
1819 pl011_enable_interrupts(uap);
1820
1821 return 0;
1822}
1823
ec489aa8
LW		 1824static void pl011_shutdown_channel(struct uart_amba_port *uap,
1825 unsigned int lcrh)
1826{
f11c9841 1827 unsigned long val;
ec489aa8 1828
b2a4e24c 1829 val = pl011_read(uap, lcrh);
f11c9841 1830 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
b2a4e24c 1831 pl011_write(val, uap, lcrh);
ec489aa8
LW		 1832}
1833
95166a3f
AP		 1834/*
1835 * disable the port. It should not disable RTS and DTR.
1836 * Also RTS and DTR state should be preserved to restore
1837 * it during startup().
1838 */
1839static void pl011_disable_uart(struct uart_amba_port *uap)
1da177e4 1840{
d8d8ffa4 1841 unsigned int cr;
1da177e4 1842
2a76fa28 1843 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
fe433907 1844 spin_lock_irq(&uap->port.lock);
9f25bc51 1845 cr = pl011_read(uap, REG_CR);
d8d8ffa4
SKS		 1846 uap->old_cr = cr;
1847 cr &= UART011_CR_RTS | UART011_CR_DTR;
1848 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
9f25bc51 1849 pl011_write(cr, uap, REG_CR);
fe433907 1850 spin_unlock_irq(&uap->port.lock);
1da177e4
LT		 1851
1852 /*
1853 * disable break condition and fifos
1854 */
e4df9a80 1855 pl011_shutdown_channel(uap, REG_LCRH_RX);
7fe9a5a9 1856 if (pl011_split_lcrh(uap))
e4df9a80 1857 pl011_shutdown_channel(uap, REG_LCRH_TX);
95166a3f
AP		 1858}
1859
1860static void pl011_disable_interrupts(struct uart_amba_port *uap)
1861{
1862 spin_lock_irq(&uap->port.lock);
1863
1864 /* mask all interrupts and clear all pending ones */
1865 uap->im = 0;
9f25bc51
RK		 1866 pl011_write(uap->im, uap, REG_IMSC);
1867 pl011_write(0xffff, uap, REG_ICR);
95166a3f
AP		 1868
1869 spin_unlock_irq(&uap->port.lock);
1870}
1871
1872static void pl011_shutdown(struct uart_port *port)
1873{
1874 struct uart_amba_port *uap =
1875 container_of(port, struct uart_amba_port, port);
1876
1877 pl011_disable_interrupts(uap);
1878
1879 pl011_dma_shutdown(uap);
1880
1881 free_irq(uap->port.irq, uap);
1882
1883 pl011_disable_uart(uap);
1da177e4
LT		 1884
1885 /*
1886 * Shut down the clock producer
1887 */
1c4c4394 1888 clk_disable_unprepare(uap->clk);
78d80c5a 1889 /* Optionally let pins go into sleep states */
2b996fc5 1890 pinctrl_pm_select_sleep_state(port->dev);
c16d51a3 1891
574de559 1892 if (dev_get_platdata(uap->port.dev)) {
c16d51a3
SKS		 1893 struct amba_pl011_data *plat;
1894
574de559 1895 plat = dev_get_platdata(uap->port.dev);
c16d51a3
SKS		 1896 if (plat->exit)
1897 plat->exit();
1898 }
1899
36f339d1
PH		 1900 if (uap->port.ops->flush_buffer)
1901 uap->port.ops->flush_buffer(port);
1da177e4
LT		 1902}
1903
0dd1e247
AP		 1904static void sbsa_uart_shutdown(struct uart_port *port)
1905{
1906 struct uart_amba_port *uap =
1907 container_of(port, struct uart_amba_port, port);
1908
1909 pl011_disable_interrupts(uap);
1910
1911 free_irq(uap->port.irq, uap);
1912
1913 if (uap->port.ops->flush_buffer)
1914 uap->port.ops->flush_buffer(port);
1915}
1916
ef5a9358
AP		 1917static void
1918pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1919{
1920 port->read_status_mask = UART011_DR_OE | 255;
1921 if (termios->c_iflag & INPCK)
1922 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1923 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1924 port->read_status_mask |= UART011_DR_BE;
1925
1926 /*
1927 * Characters to ignore
1928 */
1929 port->ignore_status_mask = 0;
1930 if (termios->c_iflag & IGNPAR)
1931 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1932 if (termios->c_iflag & IGNBRK) {
1933 port->ignore_status_mask |= UART011_DR_BE;
1934 /*
1935 * If we're ignoring parity and break indicators,
1936 * ignore overruns too (for real raw support).
1937 */
1938 if (termios->c_iflag & IGNPAR)
1939 port->ignore_status_mask |= UART011_DR_OE;
1940 }
1941
1942 /*
1943 * Ignore all characters if CREAD is not set.
1944 */
1945 if ((termios->c_cflag & CREAD) == 0)
1946 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1947}
1948
1da177e4 1949static void
606d099c
AC		 1950pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1951 struct ktermios *old)
1da177e4 1952{
a5820c24
DT		 1953 struct uart_amba_port *uap =
1954 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1955 unsigned int lcr_h, old_cr;
1956 unsigned long flags;
c19f12b5
RK		 1957 unsigned int baud, quot, clkdiv;
1958
1959 if (uap->vendor->oversampling)
1960 clkdiv = 8;
1961 else
1962 clkdiv = 16;
1da177e4
LT		 1963
1964 /*
1965 * Ask the core to calculate the divisor for us.
1966 */
ac3e3fb4 1967 baud = uart_get_baud_rate(port, termios, old, 0,
c19f12b5 1968 port->uartclk / clkdiv);
89fa28db 1969#ifdef CONFIG_DMA_ENGINE
cb06ff10
CM		 1970 /*
1971 * Adjust RX DMA polling rate with baud rate if not specified.
1972 */
1973 if (uap->dmarx.auto_poll_rate)
1974 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
89fa28db 1975#endif
ac3e3fb4
LW		 1976
1977 if (baud > port->uartclk/16)
1978 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1979 else
1980 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1da177e4
LT		 1981
1982 switch (termios->c_cflag & CSIZE) {
1983 case CS5:
1984 lcr_h = UART01x_LCRH_WLEN_5;
1985 break;
1986 case CS6:
1987 lcr_h = UART01x_LCRH_WLEN_6;
1988 break;
1989 case CS7:
1990 lcr_h = UART01x_LCRH_WLEN_7;
1991 break;
1992 default: // CS8
1993 lcr_h = UART01x_LCRH_WLEN_8;
1994 break;
1995 }
1996 if (termios->c_cflag & CSTOPB)
1997 lcr_h |= UART01x_LCRH_STP2;
1998 if (termios->c_cflag & PARENB) {
1999 lcr_h |= UART01x_LCRH_PEN;
2000 if (!(termios->c_cflag & PARODD))
2001 lcr_h |= UART01x_LCRH_EPS;
bb70002c
ES		 2002 if (termios->c_cflag & CMSPAR)
2003 lcr_h |= UART011_LCRH_SPS;
1da177e4 2004 }
ffca2b11 2005 if (uap->fifosize > 1)
1da177e4
LT		 2006 lcr_h |= UART01x_LCRH_FEN;
2007
2008 spin_lock_irqsave(&port->lock, flags);
2009
2010 /*
2011 * Update the per-port timeout.
2012 */
2013 uart_update_timeout(port, termios->c_cflag, baud);
2014
ef5a9358 2015 pl011_setup_status_masks(port, termios);
1da177e4
LT		 2016
2017 if (UART_ENABLE_MS(port, termios->c_cflag))
2018 pl011_enable_ms(port);
2019
2020 /* first, disable everything */
9f25bc51
RK		 2021 old_cr = pl011_read(uap, REG_CR);
2022 pl011_write(0, uap, REG_CR);
1da177e4 2023
3b43816f
RV		 2024 if (termios->c_cflag & CRTSCTS) {
2025 if (old_cr & UART011_CR_RTS)
2026 old_cr |= UART011_CR_RTSEN;
2027
2028 old_cr |= UART011_CR_CTSEN;
2a76fa28 2029 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
3b43816f
RV		 2030 } else {
2031 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2a76fa28 2032 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
3b43816f
RV		 2033 }
2034
c19f12b5
RK		 2035 if (uap->vendor->oversampling) {
2036 if (baud > port->uartclk / 16)
ac3e3fb4
LW		 2037 old_cr |= ST_UART011_CR_OVSFACT;
2038 else
2039 old_cr &= ~ST_UART011_CR_OVSFACT;
2040 }
2041
c5dd553b
LW		 2042 /*
2043 * Workaround for the ST Micro oversampling variants to
2044 * increase the bitrate slightly, by lowering the divisor,
2045 * to avoid delayed sampling of start bit at high speeds,
2046 * else we see data corruption.
2047 */
2048 if (uap->vendor->oversampling) {
2049 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2050 quot -= 1;
2051 else if ((baud > 3250000) && (quot > 2))
2052 quot -= 2;
2053 }
1da177e4 2054 /* Set baud rate */
9f25bc51
RK		 2055 pl011_write(quot & 0x3f, uap, REG_FBRD);
2056 pl011_write(quot >> 6, uap, REG_IBRD);
1da177e4
LT		 2057
2058 /*
2059 * ----------v----------v----------v----------v-----
e4df9a80 2060 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
9f25bc51 2061 * REG_FBRD & REG_IBRD.
1da177e4
LT		 2062 * ----------^----------^----------^----------^-----
2063 */
b60f2f66 2064 pl011_write_lcr_h(uap, lcr_h);
9f25bc51 2065 pl011_write(old_cr, uap, REG_CR);
1da177e4
LT		 2066
2067 spin_unlock_irqrestore(&port->lock, flags);
2068}
2069
0dd1e247
AP		 2070static void
2071sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2072 struct ktermios *old)
2073{
2074 struct uart_amba_port *uap =
2075 container_of(port, struct uart_amba_port, port);
2076 unsigned long flags;
2077
2078 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2079
2080 /* The SBSA UART only supports 8n1 without hardware flow control. */
2081 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2082 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2083 termios->c_cflag |= CS8 | CLOCAL;
2084
2085 spin_lock_irqsave(&port->lock, flags);
2086 uart_update_timeout(port, CS8, uap->fixed_baud);
2087 pl011_setup_status_masks(port, termios);
2088 spin_unlock_irqrestore(&port->lock, flags);
2089}
2090
1da177e4
LT		 2091static const char *pl011_type(struct uart_port *port)
2092{
a5820c24
DT		 2093 struct uart_amba_port *uap =
2094 container_of(port, struct uart_amba_port, port);
e8a7ba86 2095 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1da177e4
LT		 2096}
2097
2098/*
2099 * Release the memory region(s) being used by 'port'
2100 */
e643f87f 2101static void pl011_release_port(struct uart_port *port)
1da177e4
LT		 2102{
2103 release_mem_region(port->mapbase, SZ_4K);
2104}
2105
2106/*
2107 * Request the memory region(s) being used by 'port'
2108 */
e643f87f 2109static int pl011_request_port(struct uart_port *port)
1da177e4
LT		 2110{
2111 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2112 != NULL ? 0 : -EBUSY;
2113}
2114
2115/*
2116 * Configure/autoconfigure the port.
2117 */
e643f87f 2118static void pl011_config_port(struct uart_port *port, int flags)
1da177e4
LT		 2119{
2120 if (flags & UART_CONFIG_TYPE) {
2121 port->type = PORT_AMBA;
e643f87f 2122 pl011_request_port(port);
1da177e4
LT		 2123 }
2124}
2125
2126/*
2127 * verify the new serial_struct (for TIOCSSERIAL).
2128 */
e643f87f 2129static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1da177e4
LT		 2130{
2131 int ret = 0;
2132 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2133 ret = -EINVAL;
a62c4133 2134 if (ser->irq < 0 || ser->irq >= nr_irqs)
1da177e4
LT		 2135 ret = -EINVAL;
2136 if (ser->baud_base < 9600)
2137 ret = -EINVAL;
2138 return ret;
2139}
2140
2331e068 2141static const struct uart_ops amba_pl011_pops = {
e643f87f 2142 .tx_empty = pl011_tx_empty,
1da177e4 2143 .set_mctrl = pl011_set_mctrl,
e643f87f 2144 .get_mctrl = pl011_get_mctrl,
1da177e4
LT		 2145 .stop_tx = pl011_stop_tx,
2146 .start_tx = pl011_start_tx,
2147 .stop_rx = pl011_stop_rx,
2148 .enable_ms = pl011_enable_ms,
2149 .break_ctl = pl011_break_ctl,
2150 .startup = pl011_startup,
2151 .shutdown = pl011_shutdown,
68b65f73 2152 .flush_buffer = pl011_dma_flush_buffer,
1da177e4
LT		 2153 .set_termios = pl011_set_termios,
2154 .type = pl011_type,
e643f87f
LW		 2155 .release_port = pl011_release_port,
2156 .request_port = pl011_request_port,
2157 .config_port = pl011_config_port,
2158 .verify_port = pl011_verify_port,
84b5ae15 2159#ifdef CONFIG_CONSOLE_POLL
b3564c2c 2160 .poll_init = pl011_hwinit,
e643f87f
LW		 2161 .poll_get_char = pl011_get_poll_char,
2162 .poll_put_char = pl011_put_poll_char,
84b5ae15 2163#endif
1da177e4
LT		 2164};
2165
0dd1e247
AP		 2166static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2167{
2168}
2169
2170static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2171{
2172 return 0;
2173}
2174
2175static const struct uart_ops sbsa_uart_pops = {
2176 .tx_empty = pl011_tx_empty,
2177 .set_mctrl = sbsa_uart_set_mctrl,
2178 .get_mctrl = sbsa_uart_get_mctrl,
2179 .stop_tx = pl011_stop_tx,
2180 .start_tx = pl011_start_tx,
2181 .stop_rx = pl011_stop_rx,
2182 .startup = sbsa_uart_startup,
2183 .shutdown = sbsa_uart_shutdown,
2184 .set_termios = sbsa_uart_set_termios,
2185 .type = pl011_type,
2186 .release_port = pl011_release_port,
2187 .request_port = pl011_request_port,
2188 .config_port = pl011_config_port,
2189 .verify_port = pl011_verify_port,
2190#ifdef CONFIG_CONSOLE_POLL
2191 .poll_init = pl011_hwinit,
2192 .poll_get_char = pl011_get_poll_char,
2193 .poll_put_char = pl011_put_poll_char,
2194#endif
2195};
2196
1da177e4
LT		 2197static struct uart_amba_port *amba_ports[UART_NR];
2198
2199#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2200
d358788f 2201static void pl011_console_putchar(struct uart_port *port, int ch)
1da177e4 2202{
a5820c24
DT		 2203 struct uart_amba_port *uap =
2204 container_of(port, struct uart_amba_port, port);
1da177e4 2205
9f25bc51 2206 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2f2fd089 2207 cpu_relax();
9f25bc51 2208 pl011_write(ch, uap, REG_DR);
1da177e4
LT		 2209}
2210
2211static void
2212pl011_console_write(struct console *co, const char *s, unsigned int count)
2213{
2214 struct uart_amba_port *uap = amba_ports[co->index];
2f2fd089 2215 unsigned int old_cr = 0, new_cr;
ef605fdb
RV		 2216 unsigned long flags;
2217 int locked = 1;
1da177e4
LT		 2218
2219 clk_enable(uap->clk);
2220
ef605fdb
RV		 2221 local_irq_save(flags);
2222 if (uap->port.sysrq)
2223 locked = 0;
2224 else if (oops_in_progress)
2225 locked = spin_trylock(&uap->port.lock);
2226 else
2227 spin_lock(&uap->port.lock);
2228
1da177e4
LT		 2229 /*
2230 * First save the CR then disable the interrupts
2231 */
71eec483 2232 if (!uap->vendor->always_enabled) {
9f25bc51 2233 old_cr = pl011_read(uap, REG_CR);
71eec483
AP		 2234 new_cr = old_cr & ~UART011_CR_CTSEN;
2235 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
9f25bc51 2236 pl011_write(new_cr, uap, REG_CR);
71eec483 2237 }
1da177e4 2238
d358788f 2239 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1da177e4
LT		 2240
2241 /*
d8a4995b
CC		 2242 * Finally, wait for transmitter to become empty and restore the
2243 * TCR. Allow feature register bits to be inverted to work around
2244 * errata.
1da177e4 2245 */
d8a4995b
CC		 2246 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2247 & uap->vendor->fr_busy)
2f2fd089 2248 cpu_relax();
71eec483 2249 if (!uap->vendor->always_enabled)
9f25bc51 2250 pl011_write(old_cr, uap, REG_CR);
1da177e4 2251
ef605fdb
RV		 2252 if (locked)
2253 spin_unlock(&uap->port.lock);
2254 local_irq_restore(flags);
2255
1da177e4
LT		 2256 clk_disable(uap->clk);
2257}
2258
2259static void __init
2260pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2261 int *parity, int *bits)
2262{
9f25bc51 2263 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
1da177e4
LT		 2264 unsigned int lcr_h, ibrd, fbrd;
2265
e4df9a80 2266 lcr_h = pl011_read(uap, REG_LCRH_TX);
1da177e4
LT		 2267
2268 *parity = 'n';
2269 if (lcr_h & UART01x_LCRH_PEN) {
2270 if (lcr_h & UART01x_LCRH_EPS)
2271 *parity = 'e';
2272 else
2273 *parity = 'o';
2274 }
2275
2276 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2277 *bits = 7;
2278 else
2279 *bits = 8;
2280
9f25bc51
RK		 2281 ibrd = pl011_read(uap, REG_IBRD);
2282 fbrd = pl011_read(uap, REG_FBRD);
1da177e4
LT		 2283
2284 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
ac3e3fb4 2285
c19f12b5 2286 if (uap->vendor->oversampling) {
9f25bc51 2287 if (pl011_read(uap, REG_CR)
ac3e3fb4
LW		 2288 & ST_UART011_CR_OVSFACT)
2289 *baud *= 2;
2290 }
1da177e4
LT		 2291 }
2292}
2293
2294static int __init pl011_console_setup(struct console *co, char *options)
2295{
2296 struct uart_amba_port *uap;
2297 int baud = 38400;
2298 int bits = 8;
2299 int parity = 'n';
2300 int flow = 'n';
4b4851c6 2301 int ret;
1da177e4
LT		 2302
2303 /*
2304 * Check whether an invalid uart number has been specified, and
2305 * if so, search for the first available port that does have
2306 * console support.
2307 */
2308 if (co->index >= UART_NR)
2309 co->index = 0;
2310 uap = amba_ports[co->index];
d28122a5
RK		 2311 if (!uap)
2312 return -ENODEV;
1da177e4 2313
78d80c5a 2314 /* Allow pins to be muxed in and configured */
2b996fc5 2315 pinctrl_pm_select_default_state(uap->port.dev);
78d80c5a 2316
4b4851c6
RK		 2317 ret = clk_prepare(uap->clk);
2318 if (ret)
2319 return ret;
2320
574de559 2321 if (dev_get_platdata(uap->port.dev)) {
c16d51a3
SKS		 2322 struct amba_pl011_data *plat;
2323
574de559 2324 plat = dev_get_platdata(uap->port.dev);
c16d51a3
SKS		 2325 if (plat->init)
2326 plat->init();
2327 }
2328
1da177e4
LT		 2329 uap->port.uartclk = clk_get_rate(uap->clk);
2330
cefc2d1d
AP		 2331 if (uap->vendor->fixed_options) {
2332 baud = uap->fixed_baud;
2333 } else {
2334 if (options)
2335 uart_parse_options(options,
2336 &baud, &parity, &bits, &flow);
2337 else
2338 pl011_console_get_options(uap, &baud, &parity, &bits);
2339 }
1da177e4
LT		 2340
2341 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2342}
2343
10879ae5
AM		 2344/**
2345 * pl011_console_match - non-standard console matching
2346 * @co: registering console
2347 * @name: name from console command line
2348 * @idx: index from console command line
2349 * @options: ptr to option string from console command line
2350 *
2351 * Only attempts to match console command lines of the form:
2352 * console=pl011,mmio|mmio32,<addr>[,<options>]
2353 * console=pl011,0x<addr>[,<options>]
2354 * This form is used to register an initial earlycon boot console and
2355 * replace it with the amba_console at pl011 driver init.
2356 *
2357 * Performs console setup for a match (as required by interface)
2358 * If no <options> are specified, then assume the h/w is already setup.
2359 *
2360 * Returns 0 if console matches; otherwise non-zero to use default matching
2361 */
2362static int __init pl011_console_match(struct console *co, char *name, int idx,
2363 char *options)
2364{
2365 unsigned char iotype;
2366 resource_size_t addr;
2367 int i;
2368
37ef38f3
TT		 2369 /*
2370 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2371 * have a distinct console name, so make sure we check for that.
2372 * The actual implementation of the erratum occurs in the probe
2373 * function.
2374 */
2375 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
10879ae5
AM		 2376 return -ENODEV;
2377
2378 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2379 return -ENODEV;
2380
2381 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2382 return -ENODEV;
2383
2384 /* try to match the port specified on the command line */
2385 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2386 struct uart_port *port;
2387
2388 if (!amba_ports[i])
2389 continue;
2390
2391 port = &amba_ports[i]->port;
2392
2393 if (port->mapbase != addr)
2394 continue;
2395
2396 co->index = i;
2397 port->cons = co;
2398 return pl011_console_setup(co, options);
2399 }
2400
2401 return -ENODEV;
2402}
2403
2d93486c 2404static struct uart_driver amba_reg;
1da177e4
LT		 2405static struct console amba_console = {
2406 .name = "ttyAMA",
2407 .write = pl011_console_write,
2408 .device = uart_console_device,
2409 .setup = pl011_console_setup,
10879ae5 2410 .match = pl011_console_match,
7951ffc9 2411 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2412 .index = -1,
2413 .data = &amba_reg,
2414};
2415
2416#define AMBA_CONSOLE (&amba_console)
0d3c673e 2417
d8a4995b
CC		 2418static void qdf2400_e44_putc(struct uart_port *port, int c)
2419{
2420 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2421 cpu_relax();
2422 writel(c, port->membase + UART01x_DR);
2423 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2424 cpu_relax();
2425}
2426
2427static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2428{
2429 struct earlycon_device *dev = con->data;
2430
2431 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2432}
2433
0d3c673e
RH		 2434static void pl011_putc(struct uart_port *port, int c)
2435{
cdf091ca 2436 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2f2fd089 2437 cpu_relax();
3b78fae7
TT		 2438 if (port->iotype == UPIO_MEM32)
2439 writel(c, port->membase + UART01x_DR);
2440 else
2441 writeb(c, port->membase + UART01x_DR);
e06690bf 2442 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2f2fd089 2443 cpu_relax();
0d3c673e
RH		 2444}
2445
2446static void pl011_early_write(struct console *con, const char *s, unsigned n)
2447{
2448 struct earlycon_device *dev = con->data;
2449
2450 uart_console_write(&dev->port, s, n, pl011_putc);
2451}
2452
e53e597f
TT		 2453/*
2454 * On non-ACPI systems, earlycon is enabled by specifying
2455 * "earlycon=pl011,<address>" on the kernel command line.
2456 *
2457 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2458 * by specifying only "earlycon" on the command line. Because it requires
2459 * SPCR, the console starts after ACPI is parsed, which is later than a
2460 * traditional early console.
2461 *
2462 * To get the traditional early console that starts before ACPI is parsed,
2463 * specify the full "earlycon=pl011,<address>" option.
2464 */
0d3c673e
RH		 2465static int __init pl011_early_console_setup(struct earlycon_device *device,
2466 const char *opt)
2467{
2468 if (!device->port.membase)
2469 return -ENODEV;
2470
5a0722b8 2471 device->con->write = pl011_early_write;
e53e597f 2472
0d3c673e
RH		 2473 return 0;
2474}
45e0f0f5 2475OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
fcb32159 2476OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
5a0722b8
TT		 2477
2478/*
2479 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2480 * Erratum 44, traditional earlycon can be enabled by specifying
2481 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2482 *
2483 * Alternatively, you can just specify "earlycon", and the early console
2484 * will be enabled with the information from the SPCR table. In this
2485 * case, the SPCR code will detect the need for the E44 work-around,
2486 * and set the console name to "qdf2400_e44".
2487 */
2488static int __init
2489qdf2400_e44_early_console_setup(struct earlycon_device *device,
2490 const char *opt)
2491{
2492 if (!device->port.membase)
2493 return -ENODEV;
2494
2495 device->con->write = qdf2400_e44_early_write;
2496 return 0;
2497}
2498EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
0d3c673e 2499
1da177e4
LT		 2500#else
2501#define AMBA_CONSOLE NULL
2502#endif
2503
2504static struct uart_driver amba_reg = {
2505 .owner = THIS_MODULE,
2506 .driver_name = "ttyAMA",
2507 .dev_name = "ttyAMA",
2508 .major = SERIAL_AMBA_MAJOR,
2509 .minor = SERIAL_AMBA_MINOR,
2510 .nr = UART_NR,
2511 .cons = AMBA_CONSOLE,
2512};
2513
32614aad
ML		 2514static int pl011_probe_dt_alias(int index, struct device *dev)
2515{
2516 struct device_node *np;
2517 static bool seen_dev_with_alias = false;
2518 static bool seen_dev_without_alias = false;
2519 int ret = index;
2520
2521 if (!IS_ENABLED(CONFIG_OF))
2522 return ret;
2523
2524 np = dev->of_node;
2525 if (!np)
2526 return ret;
2527
2528 ret = of_alias_get_id(np, "serial");
287980e4 2529 if (ret < 0) {
32614aad
ML		 2530 seen_dev_without_alias = true;
2531 ret = index;
2532 } else {
2533 seen_dev_with_alias = true;
2534 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2535 dev_warn(dev, "requested serial port %d not available.\n", ret);
2536 ret = index;
2537 }
2538 }
2539
2540 if (seen_dev_with_alias && seen_dev_without_alias)
2541 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2542
2543 return ret;
2544}
2545
49bb3c86
AP		 2546/* unregisters the driver also if no more ports are left */
2547static void pl011_unregister_port(struct uart_amba_port *uap)
2548{
2549 int i;
2550 bool busy = false;
2551
2552 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2553 if (amba_ports[i] == uap)
2554 amba_ports[i] = NULL;
2555 else if (amba_ports[i])
2556 busy = true;
2557 }
2558 pl011_dma_remove(uap);
2559 if (!busy)
2560 uart_unregister_driver(&amba_reg);
2561}
2562
3873e2d7 2563static int pl011_find_free_port(void)
1da177e4 2564{
3873e2d7 2565 int i;
1da177e4
LT		 2566
2567 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2568 if (amba_ports[i] == NULL)
3873e2d7 2569 return i;
1da177e4 2570
3873e2d7
AP		 2571 return -EBUSY;
2572}
1da177e4 2573
3873e2d7
AP		 2574static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2575 struct resource *mmiobase, int index)
2576{
2577 void __iomem *base;
32614aad 2578
3873e2d7 2579 base = devm_ioremap_resource(dev, mmiobase);
97a60eac
KK		 2580 if (IS_ERR(base))
2581 return PTR_ERR(base);
1da177e4 2582
3873e2d7 2583 index = pl011_probe_dt_alias(index, dev);
1da177e4 2584
d8d8ffa4 2585 uap->old_cr = 0;
3873e2d7
AP		 2586 uap->port.dev = dev;
2587 uap->port.mapbase = mmiobase->start;
1da177e4 2588 uap->port.membase = base;
ffca2b11 2589 uap->port.fifosize = uap->fifosize;
1da177e4 2590 uap->port.flags = UPF_BOOT_AUTOCONF;
3873e2d7 2591 uap->port.line = index;
1da177e4 2592
3873e2d7 2593 amba_ports[index] = uap;
c3d8b76f 2594
3873e2d7
AP		 2595 return 0;
2596}
e8a7ba86 2597
3873e2d7
AP		 2598static int pl011_register_port(struct uart_amba_port *uap)
2599{
2600 int ret;
1da177e4 2601
3873e2d7 2602 /* Ensure interrupts from this UART are masked and cleared */
9f25bc51
RK		 2603 pl011_write(0, uap, REG_IMSC);
2604 pl011_write(0xffff, uap, REG_ICR);
ef2889f7
TB		 2605
2606 if (!amba_reg.state) {
2607 ret = uart_register_driver(&amba_reg);
2608 if (ret < 0) {
3873e2d7 2609 dev_err(uap->port.dev,
1c9be310 2610 "Failed to register AMBA-PL011 driver\n");
ef2889f7
TB		 2611 return ret;
2612 }
2613 }
2614
1da177e4 2615 ret = uart_add_one_port(&amba_reg, &uap->port);
49bb3c86
AP		 2616 if (ret)
2617 pl011_unregister_port(uap);
7f6d942a 2618
1da177e4
LT		 2619 return ret;
2620}
2621
3873e2d7
AP		 2622static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2623{
2624 struct uart_amba_port *uap;
2625 struct vendor_data *vendor = id->data;
2626 int portnr, ret;
2627
2628 portnr = pl011_find_free_port();
2629 if (portnr < 0)
2630 return portnr;
2631
2632 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2633 GFP_KERNEL);
2634 if (!uap)
2635 return -ENOMEM;
2636
2637 uap->clk = devm_clk_get(&dev->dev, NULL);
2638 if (IS_ERR(uap->clk))
2639 return PTR_ERR(uap->clk);
2640
439403bd 2641 uap->reg_offset = vendor->reg_offset;
3873e2d7 2642 uap->vendor = vendor;
3873e2d7 2643 uap->fifosize = vendor->get_fifosize(dev);
3b78fae7 2644 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
3873e2d7
AP		 2645 uap->port.irq = dev->irq[0];
2646 uap->port.ops = &amba_pl011_pops;
2647
2648 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2649
2650 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2651 if (ret)
2652 return ret;
2653
2654 amba_set_drvdata(dev, uap);
2655
2656 return pl011_register_port(uap);
2657}
2658
1da177e4
LT		 2659static int pl011_remove(struct amba_device *dev)
2660{
2661 struct uart_amba_port *uap = amba_get_drvdata(dev);
1da177e4 2662
1da177e4 2663 uart_remove_one_port(&amba_reg, &uap->port);
49bb3c86 2664 pl011_unregister_port(uap);
1da177e4
LT		 2665 return 0;
2666}
2667
d0ce850d
UH		 2668#ifdef CONFIG_PM_SLEEP
2669static int pl011_suspend(struct device *dev)
b736b89f 2670{
d0ce850d 2671 struct uart_amba_port *uap = dev_get_drvdata(dev);
b736b89f
LC		 2672
2673 if (!uap)
2674 return -EINVAL;
2675
2676 return uart_suspend_port(&amba_reg, &uap->port);
2677}
2678
d0ce850d 2679static int pl011_resume(struct device *dev)
b736b89f 2680{
d0ce850d 2681 struct uart_amba_port *uap = dev_get_drvdata(dev);
b736b89f
LC		 2682
2683 if (!uap)
2684 return -EINVAL;
2685
2686 return uart_resume_port(&amba_reg, &uap->port);
2687}
2688#endif
2689
d0ce850d
UH		 2690static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2691
0dd1e247
AP		 2692static int sbsa_uart_probe(struct platform_device *pdev)
2693{
2694 struct uart_amba_port *uap;
2695 struct resource *r;
2696 int portnr, ret;
2697 int baudrate;
2698
2699 /*
2700 * Check the mandatory baud rate parameter in the DT node early
2701 * so that we can easily exit with the error.
2702 */
2703 if (pdev->dev.of_node) {
2704 struct device_node *np = pdev->dev.of_node;
2705
2706 ret = of_property_read_u32(np, "current-speed", &baudrate);
2707 if (ret)
2708 return ret;
2709 } else {
2710 baudrate = 115200;
2711 }
2712
2713 portnr = pl011_find_free_port();
2714 if (portnr < 0)
2715 return portnr;
2716
2717 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2718 GFP_KERNEL);
2719 if (!uap)
2720 return -ENOMEM;
2721
394a9e2c
JS		 2722 ret = platform_get_irq(pdev, 0);
2723 if (ret < 0) {
35aa33cf
KW		 2724 if (ret != -EPROBE_DEFER)
2725 dev_err(&pdev->dev, "cannot obtain irq\n");
394a9e2c
JS		 2726 return ret;
2727 }
2728 uap->port.irq = ret;
2729
37ef38f3
TT		 2730#ifdef CONFIG_ACPI_SPCR_TABLE
2731 if (qdf2400_e44_present) {
2732 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2733 uap->vendor = &vendor_qdt_qdf2400_e44;
2734 } else
2735#endif
2736 uap->vendor = &vendor_sbsa;
2737
2738 uap->reg_offset = uap->vendor->reg_offset;
0dd1e247 2739 uap->fifosize = 32;
37ef38f3 2740 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
0dd1e247
AP		 2741 uap->port.ops = &sbsa_uart_pops;
2742 uap->fixed_baud = baudrate;
2743
2744 snprintf(uap->type, sizeof(uap->type), "SBSA");
2745
2746 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2747
2748 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2749 if (ret)
2750 return ret;
2751
2752 platform_set_drvdata(pdev, uap);
2753
2754 return pl011_register_port(uap);
2755}
2756
2757static int sbsa_uart_remove(struct platform_device *pdev)
2758{
2759 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2760
2761 uart_remove_one_port(&amba_reg, &uap->port);
2762 pl011_unregister_port(uap);
2763 return 0;
2764}
2765
2766static const struct of_device_id sbsa_uart_of_match[] = {
2767 { .compatible = "arm,sbsa-uart", },
2768 {},
2769};
2770MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2771
3db9ab0b
GG		 2772static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2773 { "ARMH0011", 0 },
2774 {},
2775};
2776MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2777
0dd1e247
AP		 2778static struct platform_driver arm_sbsa_uart_platform_driver = {
2779 .probe = sbsa_uart_probe,
2780 .remove = sbsa_uart_remove,
2781 .driver = {
2782 .name = "sbsa-uart",
2783 .of_match_table = of_match_ptr(sbsa_uart_of_match),
3db9ab0b 2784 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
64237fce 2785 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
0dd1e247
AP		 2786 },
2787};
2788
a704ddc2 2789static const struct amba_id pl011_ids[] = {
1da177e4
LT		 2790 {
2791 .id = 0x00041011,
2792 .mask = 0x000fffff,
5926a295
AR		 2793 .data = &vendor_arm,
2794 },
2795 {
2796 .id = 0x00380802,
2797 .mask = 0x00ffffff,
2798 .data = &vendor_st,
1da177e4 2799 },
2426fbc7
SG		 2800 {
2801 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2802 .mask = 0x00ffffff,
2803 .data = &vendor_zte,
2804 },
1da177e4
LT		 2805 { 0, 0 },
2806};
2807
60f7a33b
DM		 2808MODULE_DEVICE_TABLE(amba, pl011_ids);
2809
1da177e4
LT		 2810static struct amba_driver pl011_driver = {
2811 .drv = {
2812 .name = "uart-pl011",
d0ce850d 2813 .pm = &pl011_dev_pm_ops,
64237fce 2814 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
1da177e4
LT		 2815 },
2816 .id_table = pl011_ids,
2817 .probe = pl011_probe,
2818 .remove = pl011_remove,
2819};
2820
2821static int __init pl011_init(void)
2822{
1da177e4
LT		 2823 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2824
0dd1e247
AP		 2825 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2826 pr_warn("could not register SBSA UART platform driver\n");
062a68a5 2827 return amba_driver_register(&pl011_driver);
1da177e4
LT		 2828}
2829
2830static void __exit pl011_exit(void)
2831{
0dd1e247 2832 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
1da177e4 2833 amba_driver_unregister(&pl011_driver);
1da177e4
LT		 2834}
2835
4dd9e742
AR		 2836/*
2837 * While this can be a module, if builtin it's most likely the console
2838 * So let's leave module_exit but move module_init to an earlier place
2839 */
2840arch_initcall(pl011_init);
1da177e4
LT		 2841module_exit(pl011_exit);
2842
2843MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2844MODULE_DESCRIPTION("ARM AMBA serial port driver");
2845MODULE_LICENSE("GPL");
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