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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for AMBA serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright 1999 ARM Limited | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 8 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
1da177e4 LT |
24 | * This is a generic driver for ARM AMBA-type serial ports. They |
25 | * have a lot of 16550-like features, but are not register compatible. | |
26 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
27 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
28 | * required, these have to be supplied via some other means (eg, GPIO) | |
29 | * and hooked into this driver. | |
30 | */ | |
1da177e4 | 31 | |
cb06ff10 | 32 | |
1da177e4 LT |
33 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
34 | #define SUPPORT_SYSRQ | |
35 | #endif | |
36 | ||
37 | #include <linux/module.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/console.h> | |
41 | #include <linux/sysrq.h> | |
42 | #include <linux/device.h> | |
43 | #include <linux/tty.h> | |
44 | #include <linux/tty_flip.h> | |
45 | #include <linux/serial_core.h> | |
46 | #include <linux/serial.h> | |
a62c80e5 RK |
47 | #include <linux/amba/bus.h> |
48 | #include <linux/amba/serial.h> | |
f8ce2547 | 49 | #include <linux/clk.h> |
5a0e3ad6 | 50 | #include <linux/slab.h> |
68b65f73 RK |
51 | #include <linux/dmaengine.h> |
52 | #include <linux/dma-mapping.h> | |
53 | #include <linux/scatterlist.h> | |
c16d51a3 | 54 | #include <linux/delay.h> |
258aea76 | 55 | #include <linux/types.h> |
32614aad ML |
56 | #include <linux/of.h> |
57 | #include <linux/of_device.h> | |
258e0551 | 58 | #include <linux/pinctrl/consumer.h> |
cb70706c | 59 | #include <linux/sizes.h> |
de609582 | 60 | #include <linux/io.h> |
3db9ab0b | 61 | #include <linux/acpi.h> |
1da177e4 | 62 | |
9f25bc51 RK |
63 | #include "amba-pl011.h" |
64 | ||
1da177e4 LT |
65 | #define UART_NR 14 |
66 | ||
67 | #define SERIAL_AMBA_MAJOR 204 | |
68 | #define SERIAL_AMBA_MINOR 64 | |
69 | #define SERIAL_AMBA_NR UART_NR | |
70 | ||
71 | #define AMBA_ISR_PASS_LIMIT 256 | |
72 | ||
b63d4f0f RK |
73 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
74 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 75 | |
debb7f64 RK |
76 | static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { |
77 | [REG_DR] = UART01x_DR, | |
78 | [REG_ST_DMAWM] = ST_UART011_DMAWM, | |
79 | [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, | |
80 | [REG_FR] = UART01x_FR, | |
81 | [REG_ST_LCRH_RX] = ST_UART011_LCRH_RX, | |
82 | [REG_IBRD] = UART011_IBRD, | |
83 | [REG_FBRD] = UART011_FBRD, | |
84 | [REG_LCRH] = UART011_LCRH, | |
85 | [REG_ST_LCRH_TX] = ST_UART011_LCRH_TX, | |
86 | [REG_CR] = UART011_CR, | |
87 | [REG_IFLS] = UART011_IFLS, | |
88 | [REG_IMSC] = UART011_IMSC, | |
89 | [REG_RIS] = UART011_RIS, | |
90 | [REG_MIS] = UART011_MIS, | |
91 | [REG_ICR] = UART011_ICR, | |
92 | [REG_DMACR] = UART011_DMACR, | |
93 | [REG_ST_XFCR] = ST_UART011_XFCR, | |
94 | [REG_ST_XON1] = ST_UART011_XON1, | |
95 | [REG_ST_XON2] = ST_UART011_XON2, | |
96 | [REG_ST_XOFF1] = ST_UART011_XOFF1, | |
97 | [REG_ST_XOFF2] = ST_UART011_XOFF2, | |
98 | [REG_ST_ITCR] = ST_UART011_ITCR, | |
99 | [REG_ST_ITIP] = ST_UART011_ITIP, | |
100 | [REG_ST_ABCR] = ST_UART011_ABCR, | |
101 | [REG_ST_ABIMSC] = ST_UART011_ABIMSC, | |
102 | }; | |
103 | ||
5926a295 AR |
104 | /* There is by now at least one vendor with differing details, so handle it */ |
105 | struct vendor_data { | |
439403bd | 106 | const u16 *reg_offset; |
5926a295 | 107 | unsigned int ifls; |
ec489aa8 LW |
108 | unsigned int lcrh_tx; |
109 | unsigned int lcrh_rx; | |
ac3e3fb4 | 110 | bool oversampling; |
38d62436 | 111 | bool dma_threshold; |
4fd0690b | 112 | bool cts_event_workaround; |
71eec483 | 113 | bool always_enabled; |
cefc2d1d | 114 | bool fixed_options; |
78506f22 | 115 | |
ea33640a | 116 | unsigned int (*get_fifosize)(struct amba_device *dev); |
5926a295 AR |
117 | }; |
118 | ||
ea33640a | 119 | static unsigned int get_fifosize_arm(struct amba_device *dev) |
78506f22 | 120 | { |
ea33640a | 121 | return amba_rev(dev) < 3 ? 16 : 32; |
78506f22 JK |
122 | } |
123 | ||
5926a295 | 124 | static struct vendor_data vendor_arm = { |
439403bd | 125 | .reg_offset = pl011_std_offsets, |
5926a295 | 126 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, |
9f25bc51 RK |
127 | .lcrh_tx = REG_LCRH, |
128 | .lcrh_rx = REG_LCRH, | |
ac3e3fb4 | 129 | .oversampling = false, |
38d62436 | 130 | .dma_threshold = false, |
4fd0690b | 131 | .cts_event_workaround = false, |
71eec483 | 132 | .always_enabled = false, |
cefc2d1d | 133 | .fixed_options = false, |
78506f22 | 134 | .get_fifosize = get_fifosize_arm, |
5926a295 AR |
135 | }; |
136 | ||
0dd1e247 | 137 | static struct vendor_data vendor_sbsa = { |
439403bd | 138 | .reg_offset = pl011_std_offsets, |
0dd1e247 AP |
139 | .oversampling = false, |
140 | .dma_threshold = false, | |
141 | .cts_event_workaround = false, | |
142 | .always_enabled = true, | |
143 | .fixed_options = true, | |
144 | }; | |
145 | ||
ea33640a | 146 | static unsigned int get_fifosize_st(struct amba_device *dev) |
78506f22 JK |
147 | { |
148 | return 64; | |
149 | } | |
150 | ||
5926a295 | 151 | static struct vendor_data vendor_st = { |
439403bd | 152 | .reg_offset = pl011_std_offsets, |
5926a295 | 153 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, |
9f25bc51 RK |
154 | .lcrh_tx = REG_ST_LCRH_TX, |
155 | .lcrh_rx = REG_ST_LCRH_RX, | |
ac3e3fb4 | 156 | .oversampling = true, |
38d62436 | 157 | .dma_threshold = true, |
4fd0690b | 158 | .cts_event_workaround = true, |
71eec483 | 159 | .always_enabled = false, |
cefc2d1d | 160 | .fixed_options = false, |
78506f22 | 161 | .get_fifosize = get_fifosize_st, |
1da177e4 LT |
162 | }; |
163 | ||
68b65f73 | 164 | /* Deals with DMA transactions */ |
ead76f32 LW |
165 | |
166 | struct pl011_sgbuf { | |
167 | struct scatterlist sg; | |
168 | char *buf; | |
169 | }; | |
170 | ||
171 | struct pl011_dmarx_data { | |
172 | struct dma_chan *chan; | |
173 | struct completion complete; | |
174 | bool use_buf_b; | |
175 | struct pl011_sgbuf sgbuf_a; | |
176 | struct pl011_sgbuf sgbuf_b; | |
177 | dma_cookie_t cookie; | |
178 | bool running; | |
cb06ff10 CM |
179 | struct timer_list timer; |
180 | unsigned int last_residue; | |
181 | unsigned long last_jiffies; | |
182 | bool auto_poll_rate; | |
183 | unsigned int poll_rate; | |
184 | unsigned int poll_timeout; | |
ead76f32 LW |
185 | }; |
186 | ||
68b65f73 RK |
187 | struct pl011_dmatx_data { |
188 | struct dma_chan *chan; | |
189 | struct scatterlist sg; | |
190 | char *buf; | |
191 | bool queued; | |
192 | }; | |
193 | ||
c19f12b5 RK |
194 | /* |
195 | * We wrap our port structure around the generic uart_port. | |
196 | */ | |
197 | struct uart_amba_port { | |
198 | struct uart_port port; | |
debb7f64 | 199 | const u16 *reg_offset; |
c19f12b5 RK |
200 | struct clk *clk; |
201 | const struct vendor_data *vendor; | |
68b65f73 | 202 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
203 | unsigned int im; /* interrupt mask */ |
204 | unsigned int old_status; | |
ffca2b11 | 205 | unsigned int fifosize; /* vendor-specific */ |
c19f12b5 RK |
206 | unsigned int lcrh_tx; /* vendor-specific */ |
207 | unsigned int lcrh_rx; /* vendor-specific */ | |
d8d8ffa4 | 208 | unsigned int old_cr; /* state during shutdown */ |
c19f12b5 | 209 | bool autorts; |
cefc2d1d | 210 | unsigned int fixed_baud; /* vendor-set fixed baud rate */ |
c19f12b5 | 211 | char type[12]; |
68b65f73 RK |
212 | #ifdef CONFIG_DMA_ENGINE |
213 | /* DMA stuff */ | |
ead76f32 LW |
214 | bool using_tx_dma; |
215 | bool using_rx_dma; | |
216 | struct pl011_dmarx_data dmarx; | |
68b65f73 | 217 | struct pl011_dmatx_data dmatx; |
1c9be310 | 218 | bool dma_probed; |
68b65f73 RK |
219 | #endif |
220 | }; | |
221 | ||
9f25bc51 RK |
222 | static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, |
223 | unsigned int reg) | |
224 | { | |
debb7f64 | 225 | return uap->reg_offset[reg]; |
9f25bc51 RK |
226 | } |
227 | ||
b2a4e24c RK |
228 | static unsigned int pl011_read(const struct uart_amba_port *uap, |
229 | unsigned int reg) | |
75836339 | 230 | { |
9f25bc51 | 231 | return readw(uap->port.membase + pl011_reg_to_offset(uap, reg)); |
75836339 RK |
232 | } |
233 | ||
b2a4e24c RK |
234 | static void pl011_write(unsigned int val, const struct uart_amba_port *uap, |
235 | unsigned int reg) | |
75836339 | 236 | { |
9f25bc51 | 237 | writew(val, uap->port.membase + pl011_reg_to_offset(uap, reg)); |
75836339 RK |
238 | } |
239 | ||
29772c4e LW |
240 | /* |
241 | * Reads up to 256 characters from the FIFO or until it's empty and | |
242 | * inserts them into the TTY layer. Returns the number of characters | |
243 | * read from the FIFO. | |
244 | */ | |
245 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) | |
246 | { | |
71a5cd8a TT |
247 | u16 status; |
248 | unsigned int ch, flag, max_count = 256; | |
29772c4e LW |
249 | int fifotaken = 0; |
250 | ||
251 | while (max_count--) { | |
9f25bc51 | 252 | status = pl011_read(uap, REG_FR); |
29772c4e LW |
253 | if (status & UART01x_FR_RXFE) |
254 | break; | |
255 | ||
256 | /* Take chars from the FIFO and update status */ | |
9f25bc51 | 257 | ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; |
29772c4e LW |
258 | flag = TTY_NORMAL; |
259 | uap->port.icount.rx++; | |
260 | fifotaken++; | |
261 | ||
262 | if (unlikely(ch & UART_DR_ERROR)) { | |
263 | if (ch & UART011_DR_BE) { | |
264 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
265 | uap->port.icount.brk++; | |
266 | if (uart_handle_break(&uap->port)) | |
267 | continue; | |
268 | } else if (ch & UART011_DR_PE) | |
269 | uap->port.icount.parity++; | |
270 | else if (ch & UART011_DR_FE) | |
271 | uap->port.icount.frame++; | |
272 | if (ch & UART011_DR_OE) | |
273 | uap->port.icount.overrun++; | |
274 | ||
275 | ch &= uap->port.read_status_mask; | |
276 | ||
277 | if (ch & UART011_DR_BE) | |
278 | flag = TTY_BREAK; | |
279 | else if (ch & UART011_DR_PE) | |
280 | flag = TTY_PARITY; | |
281 | else if (ch & UART011_DR_FE) | |
282 | flag = TTY_FRAME; | |
283 | } | |
284 | ||
285 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) | |
286 | continue; | |
287 | ||
288 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
289 | } | |
290 | ||
291 | return fifotaken; | |
292 | } | |
293 | ||
294 | ||
68b65f73 RK |
295 | /* |
296 | * All the DMA operation mode stuff goes inside this ifdef. | |
297 | * This assumes that you have a generic DMA device interface, | |
298 | * no custom DMA interfaces are supported. | |
299 | */ | |
300 | #ifdef CONFIG_DMA_ENGINE | |
301 | ||
302 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
303 | ||
ead76f32 LW |
304 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
305 | enum dma_data_direction dir) | |
306 | { | |
cb06ff10 CM |
307 | dma_addr_t dma_addr; |
308 | ||
309 | sg->buf = dma_alloc_coherent(chan->device->dev, | |
310 | PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); | |
ead76f32 LW |
311 | if (!sg->buf) |
312 | return -ENOMEM; | |
313 | ||
cb06ff10 CM |
314 | sg_init_table(&sg->sg, 1); |
315 | sg_set_page(&sg->sg, phys_to_page(dma_addr), | |
316 | PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); | |
317 | sg_dma_address(&sg->sg) = dma_addr; | |
c64be923 | 318 | sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; |
ead76f32 | 319 | |
ead76f32 LW |
320 | return 0; |
321 | } | |
322 | ||
323 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |
324 | enum dma_data_direction dir) | |
325 | { | |
326 | if (sg->buf) { | |
cb06ff10 CM |
327 | dma_free_coherent(chan->device->dev, |
328 | PL011_DMA_BUFFER_SIZE, sg->buf, | |
329 | sg_dma_address(&sg->sg)); | |
ead76f32 LW |
330 | } |
331 | } | |
332 | ||
1c9be310 | 333 | static void pl011_dma_probe(struct uart_amba_port *uap) |
68b65f73 RK |
334 | { |
335 | /* DMA is the sole user of the platform data right now */ | |
574de559 | 336 | struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); |
1c9be310 | 337 | struct device *dev = uap->port.dev; |
68b65f73 | 338 | struct dma_slave_config tx_conf = { |
9f25bc51 RK |
339 | .dst_addr = uap->port.mapbase + |
340 | pl011_reg_to_offset(uap, REG_DR), | |
68b65f73 | 341 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, |
a485df4b | 342 | .direction = DMA_MEM_TO_DEV, |
68b65f73 | 343 | .dst_maxburst = uap->fifosize >> 1, |
258aea76 | 344 | .device_fc = false, |
68b65f73 RK |
345 | }; |
346 | struct dma_chan *chan; | |
347 | dma_cap_mask_t mask; | |
348 | ||
1c9be310 JRO |
349 | uap->dma_probed = true; |
350 | chan = dma_request_slave_channel_reason(dev, "tx"); | |
351 | if (IS_ERR(chan)) { | |
352 | if (PTR_ERR(chan) == -EPROBE_DEFER) { | |
1c9be310 JRO |
353 | uap->dma_probed = false; |
354 | return; | |
355 | } | |
68b65f73 | 356 | |
787b0c1f AB |
357 | /* We need platform data */ |
358 | if (!plat || !plat->dma_filter) { | |
359 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
360 | return; | |
361 | } | |
362 | ||
363 | /* Try to acquire a generic DMA engine slave TX channel */ | |
364 | dma_cap_zero(mask); | |
365 | dma_cap_set(DMA_SLAVE, mask); | |
366 | ||
367 | chan = dma_request_channel(mask, plat->dma_filter, | |
368 | plat->dma_tx_param); | |
369 | if (!chan) { | |
370 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
371 | return; | |
372 | } | |
68b65f73 RK |
373 | } |
374 | ||
375 | dmaengine_slave_config(chan, &tx_conf); | |
376 | uap->dmatx.chan = chan; | |
377 | ||
378 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
379 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
380 | |
381 | /* Optionally make use of an RX channel as well */ | |
787b0c1f | 382 | chan = dma_request_slave_channel(dev, "rx"); |
0d3c673e | 383 | |
787b0c1f AB |
384 | if (!chan && plat->dma_rx_param) { |
385 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); | |
386 | ||
387 | if (!chan) { | |
388 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
389 | return; | |
390 | } | |
391 | } | |
392 | ||
393 | if (chan) { | |
ead76f32 | 394 | struct dma_slave_config rx_conf = { |
9f25bc51 RK |
395 | .src_addr = uap->port.mapbase + |
396 | pl011_reg_to_offset(uap, REG_DR), | |
ead76f32 | 397 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, |
a485df4b | 398 | .direction = DMA_DEV_TO_MEM, |
b2aeb775 | 399 | .src_maxburst = uap->fifosize >> 2, |
258aea76 | 400 | .device_fc = false, |
ead76f32 | 401 | }; |
2d3b7d6e AJ |
402 | struct dma_slave_caps caps; |
403 | ||
404 | /* | |
405 | * Some DMA controllers provide information on their capabilities. | |
406 | * If the controller does, check for suitable residue processing | |
407 | * otherwise assime all is well. | |
408 | */ | |
409 | if (0 == dma_get_slave_caps(chan, &caps)) { | |
410 | if (caps.residue_granularity == | |
411 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { | |
412 | dma_release_channel(chan); | |
413 | dev_info(uap->port.dev, | |
414 | "RX DMA disabled - no residue processing\n"); | |
415 | return; | |
416 | } | |
417 | } | |
ead76f32 LW |
418 | dmaengine_slave_config(chan, &rx_conf); |
419 | uap->dmarx.chan = chan; | |
420 | ||
98267d33 | 421 | uap->dmarx.auto_poll_rate = false; |
8f898bfd | 422 | if (plat && plat->dma_rx_poll_enable) { |
cb06ff10 CM |
423 | /* Set poll rate if specified. */ |
424 | if (plat->dma_rx_poll_rate) { | |
425 | uap->dmarx.auto_poll_rate = false; | |
426 | uap->dmarx.poll_rate = plat->dma_rx_poll_rate; | |
427 | } else { | |
428 | /* | |
429 | * 100 ms defaults to poll rate if not | |
430 | * specified. This will be adjusted with | |
431 | * the baud rate at set_termios. | |
432 | */ | |
433 | uap->dmarx.auto_poll_rate = true; | |
434 | uap->dmarx.poll_rate = 100; | |
435 | } | |
436 | /* 3 secs defaults poll_timeout if not specified. */ | |
437 | if (plat->dma_rx_poll_timeout) | |
438 | uap->dmarx.poll_timeout = | |
439 | plat->dma_rx_poll_timeout; | |
440 | else | |
441 | uap->dmarx.poll_timeout = 3000; | |
98267d33 AJ |
442 | } else if (!plat && dev->of_node) { |
443 | uap->dmarx.auto_poll_rate = of_property_read_bool( | |
444 | dev->of_node, "auto-poll"); | |
445 | if (uap->dmarx.auto_poll_rate) { | |
446 | u32 x; | |
447 | ||
448 | if (0 == of_property_read_u32(dev->of_node, | |
449 | "poll-rate-ms", &x)) | |
450 | uap->dmarx.poll_rate = x; | |
451 | else | |
452 | uap->dmarx.poll_rate = 100; | |
453 | if (0 == of_property_read_u32(dev->of_node, | |
454 | "poll-timeout-ms", &x)) | |
455 | uap->dmarx.poll_timeout = x; | |
456 | else | |
457 | uap->dmarx.poll_timeout = 3000; | |
458 | } | |
459 | } | |
ead76f32 LW |
460 | dev_info(uap->port.dev, "DMA channel RX %s\n", |
461 | dma_chan_name(uap->dmarx.chan)); | |
462 | } | |
68b65f73 RK |
463 | } |
464 | ||
68b65f73 RK |
465 | static void pl011_dma_remove(struct uart_amba_port *uap) |
466 | { | |
68b65f73 RK |
467 | if (uap->dmatx.chan) |
468 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
469 | if (uap->dmarx.chan) |
470 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
471 | } |
472 | ||
734745ca | 473 | /* Forward declare these for the refill routine */ |
68b65f73 | 474 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); |
734745ca | 475 | static void pl011_start_tx_pio(struct uart_amba_port *uap); |
68b65f73 RK |
476 | |
477 | /* | |
478 | * The current DMA TX buffer has been sent. | |
479 | * Try to queue up another DMA buffer. | |
480 | */ | |
481 | static void pl011_dma_tx_callback(void *data) | |
482 | { | |
483 | struct uart_amba_port *uap = data; | |
484 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
485 | unsigned long flags; | |
486 | u16 dmacr; | |
487 | ||
488 | spin_lock_irqsave(&uap->port.lock, flags); | |
489 | if (uap->dmatx.queued) | |
490 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
491 | DMA_TO_DEVICE); | |
492 | ||
493 | dmacr = uap->dmacr; | |
494 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
9f25bc51 | 495 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
496 | |
497 | /* | |
498 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
499 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
500 | * | |
501 | * Note: we need to be careful here of a potential race between DMA | |
502 | * and the rest of the driver - if the driver disables TX DMA while | |
503 | * a TX buffer completing, we must update the tx queued status to | |
504 | * get further refills (hence we check dmacr). | |
505 | */ | |
506 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
507 | uart_circ_empty(&uap->port.state->xmit)) { | |
508 | uap->dmatx.queued = false; | |
509 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
510 | return; | |
511 | } | |
512 | ||
734745ca | 513 | if (pl011_dma_tx_refill(uap) <= 0) |
68b65f73 RK |
514 | /* |
515 | * We didn't queue a DMA buffer for some reason, but we | |
516 | * have data pending to be sent. Re-enable the TX IRQ. | |
517 | */ | |
734745ca DM |
518 | pl011_start_tx_pio(uap); |
519 | ||
68b65f73 RK |
520 | spin_unlock_irqrestore(&uap->port.lock, flags); |
521 | } | |
522 | ||
523 | /* | |
524 | * Try to refill the TX DMA buffer. | |
525 | * Locking: called with port lock held and IRQs disabled. | |
526 | * Returns: | |
527 | * 1 if we queued up a TX DMA buffer. | |
528 | * 0 if we didn't want to handle this by DMA | |
529 | * <0 on error | |
530 | */ | |
531 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
532 | { | |
533 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
534 | struct dma_chan *chan = dmatx->chan; | |
535 | struct dma_device *dma_dev = chan->device; | |
536 | struct dma_async_tx_descriptor *desc; | |
537 | struct circ_buf *xmit = &uap->port.state->xmit; | |
538 | unsigned int count; | |
539 | ||
540 | /* | |
541 | * Try to avoid the overhead involved in using DMA if the | |
542 | * transaction fits in the first half of the FIFO, by using | |
543 | * the standard interrupt handling. This ensures that we | |
544 | * issue a uart_write_wakeup() at the appropriate time. | |
545 | */ | |
546 | count = uart_circ_chars_pending(xmit); | |
547 | if (count < (uap->fifosize >> 1)) { | |
548 | uap->dmatx.queued = false; | |
549 | return 0; | |
550 | } | |
551 | ||
552 | /* | |
553 | * Bodge: don't send the last character by DMA, as this | |
554 | * will prevent XON from notifying us to restart DMA. | |
555 | */ | |
556 | count -= 1; | |
557 | ||
558 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
559 | if (count > PL011_DMA_BUFFER_SIZE) | |
560 | count = PL011_DMA_BUFFER_SIZE; | |
561 | ||
562 | if (xmit->tail < xmit->head) | |
563 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
564 | else { | |
565 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
e2a545a6 AJ |
566 | size_t second; |
567 | ||
568 | if (first > count) | |
569 | first = count; | |
570 | second = count - first; | |
68b65f73 RK |
571 | |
572 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
573 | if (second) | |
574 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
575 | } | |
576 | ||
577 | dmatx->sg.length = count; | |
578 | ||
579 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
580 | uap->dmatx.queued = false; | |
581 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
582 | return -EBUSY; | |
583 | } | |
584 | ||
16052827 | 585 | desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, |
68b65f73 RK |
586 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
587 | if (!desc) { | |
588 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
589 | uap->dmatx.queued = false; | |
590 | /* | |
591 | * If DMA cannot be used right now, we complete this | |
592 | * transaction via IRQ and let the TTY layer retry. | |
593 | */ | |
594 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
595 | return -EBUSY; | |
596 | } | |
597 | ||
598 | /* Some data to go along to the callback */ | |
599 | desc->callback = pl011_dma_tx_callback; | |
600 | desc->callback_param = uap; | |
601 | ||
602 | /* All errors should happen at prepare time */ | |
603 | dmaengine_submit(desc); | |
604 | ||
605 | /* Fire the DMA transaction */ | |
606 | dma_dev->device_issue_pending(chan); | |
607 | ||
608 | uap->dmacr |= UART011_TXDMAE; | |
9f25bc51 | 609 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
610 | uap->dmatx.queued = true; |
611 | ||
612 | /* | |
613 | * Now we know that DMA will fire, so advance the ring buffer | |
614 | * with the stuff we just dispatched. | |
615 | */ | |
616 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
617 | uap->port.icount.tx += count; | |
618 | ||
619 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
620 | uart_write_wakeup(&uap->port); | |
621 | ||
622 | return 1; | |
623 | } | |
624 | ||
625 | /* | |
626 | * We received a transmit interrupt without a pending X-char but with | |
627 | * pending characters. | |
628 | * Locking: called with port lock held and IRQs disabled. | |
629 | * Returns: | |
630 | * false if we want to use PIO to transmit | |
631 | * true if we queued a DMA buffer | |
632 | */ | |
633 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
634 | { | |
ead76f32 | 635 | if (!uap->using_tx_dma) |
68b65f73 RK |
636 | return false; |
637 | ||
638 | /* | |
639 | * If we already have a TX buffer queued, but received a | |
640 | * TX interrupt, it will be because we've just sent an X-char. | |
641 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
642 | */ | |
643 | if (uap->dmatx.queued) { | |
644 | uap->dmacr |= UART011_TXDMAE; | |
9f25bc51 | 645 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 | 646 | uap->im &= ~UART011_TXIM; |
9f25bc51 | 647 | pl011_write(uap->im, uap, REG_IMSC); |
68b65f73 RK |
648 | return true; |
649 | } | |
650 | ||
651 | /* | |
652 | * We don't have a TX buffer queued, so try to queue one. | |
25985edc | 653 | * If we successfully queued a buffer, mask the TX IRQ. |
68b65f73 RK |
654 | */ |
655 | if (pl011_dma_tx_refill(uap) > 0) { | |
656 | uap->im &= ~UART011_TXIM; | |
9f25bc51 | 657 | pl011_write(uap->im, uap, REG_IMSC); |
68b65f73 RK |
658 | return true; |
659 | } | |
660 | return false; | |
661 | } | |
662 | ||
663 | /* | |
664 | * Stop the DMA transmit (eg, due to received XOFF). | |
665 | * Locking: called with port lock held and IRQs disabled. | |
666 | */ | |
667 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
668 | { | |
669 | if (uap->dmatx.queued) { | |
670 | uap->dmacr &= ~UART011_TXDMAE; | |
9f25bc51 | 671 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
672 | } |
673 | } | |
674 | ||
675 | /* | |
676 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
677 | * character queued for send, try to get that character out ASAP. | |
678 | * Locking: called with port lock held and IRQs disabled. | |
679 | * Returns: | |
680 | * false if we want the TX IRQ to be enabled | |
681 | * true if we have a buffer queued | |
682 | */ | |
683 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
684 | { | |
685 | u16 dmacr; | |
686 | ||
ead76f32 | 687 | if (!uap->using_tx_dma) |
68b65f73 RK |
688 | return false; |
689 | ||
690 | if (!uap->port.x_char) { | |
691 | /* no X-char, try to push chars out in DMA mode */ | |
692 | bool ret = true; | |
693 | ||
694 | if (!uap->dmatx.queued) { | |
695 | if (pl011_dma_tx_refill(uap) > 0) { | |
696 | uap->im &= ~UART011_TXIM; | |
9f25bc51 | 697 | pl011_write(uap->im, uap, REG_IMSC); |
734745ca | 698 | } else |
68b65f73 | 699 | ret = false; |
68b65f73 RK |
700 | } else if (!(uap->dmacr & UART011_TXDMAE)) { |
701 | uap->dmacr |= UART011_TXDMAE; | |
9f25bc51 | 702 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
703 | } |
704 | return ret; | |
705 | } | |
706 | ||
707 | /* | |
708 | * We have an X-char to send. Disable DMA to prevent it loading | |
709 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
710 | */ | |
711 | dmacr = uap->dmacr; | |
712 | uap->dmacr &= ~UART011_TXDMAE; | |
9f25bc51 | 713 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 | 714 | |
9f25bc51 | 715 | if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { |
68b65f73 RK |
716 | /* |
717 | * No space in the FIFO, so enable the transmit interrupt | |
718 | * so we know when there is space. Note that once we've | |
719 | * loaded the character, we should just re-enable DMA. | |
720 | */ | |
721 | return false; | |
722 | } | |
723 | ||
9f25bc51 | 724 | pl011_write(uap->port.x_char, uap, REG_DR); |
68b65f73 RK |
725 | uap->port.icount.tx++; |
726 | uap->port.x_char = 0; | |
727 | ||
728 | /* Success - restore the DMA state */ | |
729 | uap->dmacr = dmacr; | |
9f25bc51 | 730 | pl011_write(dmacr, uap, REG_DMACR); |
68b65f73 RK |
731 | |
732 | return true; | |
733 | } | |
734 | ||
735 | /* | |
736 | * Flush the transmit buffer. | |
737 | * Locking: called with port lock held and IRQs disabled. | |
738 | */ | |
739 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
b83286bf FE |
740 | __releases(&uap->port.lock) |
741 | __acquires(&uap->port.lock) | |
68b65f73 | 742 | { |
a5820c24 DT |
743 | struct uart_amba_port *uap = |
744 | container_of(port, struct uart_amba_port, port); | |
68b65f73 | 745 | |
ead76f32 | 746 | if (!uap->using_tx_dma) |
68b65f73 RK |
747 | return; |
748 | ||
749 | /* Avoid deadlock with the DMA engine callback */ | |
750 | spin_unlock(&uap->port.lock); | |
751 | dmaengine_terminate_all(uap->dmatx.chan); | |
752 | spin_lock(&uap->port.lock); | |
753 | if (uap->dmatx.queued) { | |
754 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
755 | DMA_TO_DEVICE); | |
756 | uap->dmatx.queued = false; | |
757 | uap->dmacr &= ~UART011_TXDMAE; | |
9f25bc51 | 758 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
759 | } |
760 | } | |
761 | ||
ead76f32 LW |
762 | static void pl011_dma_rx_callback(void *data); |
763 | ||
764 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
765 | { | |
766 | struct dma_chan *rxchan = uap->dmarx.chan; | |
ead76f32 LW |
767 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
768 | struct dma_async_tx_descriptor *desc; | |
769 | struct pl011_sgbuf *sgbuf; | |
770 | ||
771 | if (!rxchan) | |
772 | return -EIO; | |
773 | ||
774 | /* Start the RX DMA job */ | |
775 | sgbuf = uap->dmarx.use_buf_b ? | |
776 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
16052827 | 777 | desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, |
a485df4b | 778 | DMA_DEV_TO_MEM, |
ead76f32 LW |
779 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
780 | /* | |
781 | * If the DMA engine is busy and cannot prepare a | |
782 | * channel, no big deal, the driver will fall back | |
783 | * to interrupt mode as a result of this error code. | |
784 | */ | |
785 | if (!desc) { | |
786 | uap->dmarx.running = false; | |
787 | dmaengine_terminate_all(rxchan); | |
788 | return -EBUSY; | |
789 | } | |
790 | ||
791 | /* Some data to go along to the callback */ | |
792 | desc->callback = pl011_dma_rx_callback; | |
793 | desc->callback_param = uap; | |
794 | dmarx->cookie = dmaengine_submit(desc); | |
795 | dma_async_issue_pending(rxchan); | |
796 | ||
797 | uap->dmacr |= UART011_RXDMAE; | |
9f25bc51 | 798 | pl011_write(uap->dmacr, uap, REG_DMACR); |
ead76f32 LW |
799 | uap->dmarx.running = true; |
800 | ||
801 | uap->im &= ~UART011_RXIM; | |
9f25bc51 | 802 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
803 | |
804 | return 0; | |
805 | } | |
806 | ||
807 | /* | |
808 | * This is called when either the DMA job is complete, or | |
809 | * the FIFO timeout interrupt occurred. This must be called | |
810 | * with the port spinlock uap->port.lock held. | |
811 | */ | |
812 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
813 | u32 pending, bool use_buf_b, | |
814 | bool readfifo) | |
815 | { | |
05c7cd39 | 816 | struct tty_port *port = &uap->port.state->port; |
ead76f32 LW |
817 | struct pl011_sgbuf *sgbuf = use_buf_b ? |
818 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
ead76f32 LW |
819 | int dma_count = 0; |
820 | u32 fifotaken = 0; /* only used for vdbg() */ | |
821 | ||
cb06ff10 CM |
822 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
823 | int dmataken = 0; | |
824 | ||
825 | if (uap->dmarx.poll_rate) { | |
826 | /* The data can be taken by polling */ | |
827 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
828 | /* Recalculate the pending size */ | |
829 | if (pending >= dmataken) | |
830 | pending -= dmataken; | |
831 | } | |
832 | ||
833 | /* Pick the remain data from the DMA */ | |
ead76f32 | 834 | if (pending) { |
ead76f32 LW |
835 | |
836 | /* | |
837 | * First take all chars in the DMA pipe, then look in the FIFO. | |
838 | * Note that tty_insert_flip_buf() tries to take as many chars | |
839 | * as it can. | |
840 | */ | |
cb06ff10 CM |
841 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, |
842 | pending); | |
ead76f32 LW |
843 | |
844 | uap->port.icount.rx += dma_count; | |
845 | if (dma_count < pending) | |
846 | dev_warn(uap->port.dev, | |
847 | "couldn't insert all characters (TTY is full?)\n"); | |
848 | } | |
849 | ||
cb06ff10 CM |
850 | /* Reset the last_residue for Rx DMA poll */ |
851 | if (uap->dmarx.poll_rate) | |
852 | dmarx->last_residue = sgbuf->sg.length; | |
853 | ||
ead76f32 LW |
854 | /* |
855 | * Only continue with trying to read the FIFO if all DMA chars have | |
856 | * been taken first. | |
857 | */ | |
858 | if (dma_count == pending && readfifo) { | |
859 | /* Clear any error flags */ | |
75836339 | 860 | pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | |
9f25bc51 | 861 | UART011_FEIS, uap, REG_ICR); |
ead76f32 LW |
862 | |
863 | /* | |
864 | * If we read all the DMA'd characters, and we had an | |
29772c4e LW |
865 | * incomplete buffer, that could be due to an rx error, or |
866 | * maybe we just timed out. Read any pending chars and check | |
867 | * the error status. | |
868 | * | |
869 | * Error conditions will only occur in the FIFO, these will | |
870 | * trigger an immediate interrupt and stop the DMA job, so we | |
871 | * will always find the error in the FIFO, never in the DMA | |
872 | * buffer. | |
ead76f32 | 873 | */ |
29772c4e | 874 | fifotaken = pl011_fifo_to_tty(uap); |
ead76f32 LW |
875 | } |
876 | ||
877 | spin_unlock(&uap->port.lock); | |
878 | dev_vdbg(uap->port.dev, | |
879 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
880 | dma_count, fifotaken); | |
2e124b4a | 881 | tty_flip_buffer_push(port); |
ead76f32 LW |
882 | spin_lock(&uap->port.lock); |
883 | } | |
884 | ||
885 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
886 | { | |
887 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
888 | struct dma_chan *rxchan = dmarx->chan; | |
889 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? | |
890 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
891 | size_t pending; | |
892 | struct dma_tx_state state; | |
893 | enum dma_status dmastat; | |
894 | ||
895 | /* | |
896 | * Pause the transfer so we can trust the current counter, | |
897 | * do this before we pause the PL011 block, else we may | |
898 | * overflow the FIFO. | |
899 | */ | |
900 | if (dmaengine_pause(rxchan)) | |
901 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
902 | dmastat = rxchan->device->device_tx_status(rxchan, | |
903 | dmarx->cookie, &state); | |
904 | if (dmastat != DMA_PAUSED) | |
905 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
906 | ||
907 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
908 | uap->dmacr &= ~UART011_RXDMAE; | |
9f25bc51 | 909 | pl011_write(uap->dmacr, uap, REG_DMACR); |
ead76f32 LW |
910 | uap->dmarx.running = false; |
911 | ||
912 | pending = sgbuf->sg.length - state.residue; | |
913 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
914 | /* Then we terminate the transfer - we now know our residue */ | |
915 | dmaengine_terminate_all(rxchan); | |
916 | ||
917 | /* | |
918 | * This will take the chars we have so far and insert | |
919 | * into the framework. | |
920 | */ | |
921 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
922 | ||
923 | /* Switch buffer & re-trigger DMA job */ | |
924 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
925 | if (pl011_dma_rx_trigger_dma(uap)) { | |
926 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
927 | "fall back to interrupt mode\n"); | |
928 | uap->im |= UART011_RXIM; | |
9f25bc51 | 929 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
930 | } |
931 | } | |
932 | ||
933 | static void pl011_dma_rx_callback(void *data) | |
934 | { | |
935 | struct uart_amba_port *uap = data; | |
936 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
6dc01aa6 | 937 | struct dma_chan *rxchan = dmarx->chan; |
ead76f32 | 938 | bool lastbuf = dmarx->use_buf_b; |
6dc01aa6 CM |
939 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? |
940 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
941 | size_t pending; | |
942 | struct dma_tx_state state; | |
ead76f32 LW |
943 | int ret; |
944 | ||
945 | /* | |
946 | * This completion interrupt occurs typically when the | |
947 | * RX buffer is totally stuffed but no timeout has yet | |
948 | * occurred. When that happens, we just want the RX | |
949 | * routine to flush out the secondary DMA buffer while | |
950 | * we immediately trigger the next DMA job. | |
951 | */ | |
952 | spin_lock_irq(&uap->port.lock); | |
6dc01aa6 CM |
953 | /* |
954 | * Rx data can be taken by the UART interrupts during | |
955 | * the DMA irq handler. So we check the residue here. | |
956 | */ | |
957 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
958 | pending = sgbuf->sg.length - state.residue; | |
959 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
960 | /* Then we terminate the transfer - we now know our residue */ | |
961 | dmaengine_terminate_all(rxchan); | |
962 | ||
ead76f32 LW |
963 | uap->dmarx.running = false; |
964 | dmarx->use_buf_b = !lastbuf; | |
965 | ret = pl011_dma_rx_trigger_dma(uap); | |
966 | ||
6dc01aa6 | 967 | pl011_dma_rx_chars(uap, pending, lastbuf, false); |
ead76f32 LW |
968 | spin_unlock_irq(&uap->port.lock); |
969 | /* | |
970 | * Do this check after we picked the DMA chars so we don't | |
971 | * get some IRQ immediately from RX. | |
972 | */ | |
973 | if (ret) { | |
974 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
975 | "fall back to interrupt mode\n"); | |
976 | uap->im |= UART011_RXIM; | |
9f25bc51 | 977 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
978 | } |
979 | } | |
980 | ||
981 | /* | |
982 | * Stop accepting received characters, when we're shutting down or | |
983 | * suspending this port. | |
984 | * Locking: called with port lock held and IRQs disabled. | |
985 | */ | |
986 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
987 | { | |
988 | /* FIXME. Just disable the DMA enable */ | |
989 | uap->dmacr &= ~UART011_RXDMAE; | |
9f25bc51 | 990 | pl011_write(uap->dmacr, uap, REG_DMACR); |
ead76f32 | 991 | } |
68b65f73 | 992 | |
cb06ff10 CM |
993 | /* |
994 | * Timer handler for Rx DMA polling. | |
995 | * Every polling, It checks the residue in the dma buffer and transfer | |
996 | * data to the tty. Also, last_residue is updated for the next polling. | |
997 | */ | |
998 | static void pl011_dma_rx_poll(unsigned long args) | |
999 | { | |
1000 | struct uart_amba_port *uap = (struct uart_amba_port *)args; | |
1001 | struct tty_port *port = &uap->port.state->port; | |
1002 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
1003 | struct dma_chan *rxchan = uap->dmarx.chan; | |
1004 | unsigned long flags = 0; | |
1005 | unsigned int dmataken = 0; | |
1006 | unsigned int size = 0; | |
1007 | struct pl011_sgbuf *sgbuf; | |
1008 | int dma_count; | |
1009 | struct dma_tx_state state; | |
1010 | ||
1011 | sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
1012 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
1013 | if (likely(state.residue < dmarx->last_residue)) { | |
1014 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
1015 | size = dmarx->last_residue - state.residue; | |
1016 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, | |
1017 | size); | |
1018 | if (dma_count == size) | |
1019 | dmarx->last_residue = state.residue; | |
1020 | dmarx->last_jiffies = jiffies; | |
1021 | } | |
1022 | tty_flip_buffer_push(port); | |
1023 | ||
1024 | /* | |
1025 | * If no data is received in poll_timeout, the driver will fall back | |
1026 | * to interrupt mode. We will retrigger DMA at the first interrupt. | |
1027 | */ | |
1028 | if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) | |
1029 | > uap->dmarx.poll_timeout) { | |
1030 | ||
1031 | spin_lock_irqsave(&uap->port.lock, flags); | |
1032 | pl011_dma_rx_stop(uap); | |
c25a1ad7 | 1033 | uap->im |= UART011_RXIM; |
9f25bc51 | 1034 | pl011_write(uap->im, uap, REG_IMSC); |
cb06ff10 CM |
1035 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1036 | ||
1037 | uap->dmarx.running = false; | |
1038 | dmaengine_terminate_all(rxchan); | |
1039 | del_timer(&uap->dmarx.timer); | |
1040 | } else { | |
1041 | mod_timer(&uap->dmarx.timer, | |
1042 | jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1043 | } | |
1044 | } | |
1045 | ||
68b65f73 RK |
1046 | static void pl011_dma_startup(struct uart_amba_port *uap) |
1047 | { | |
ead76f32 LW |
1048 | int ret; |
1049 | ||
1c9be310 JRO |
1050 | if (!uap->dma_probed) |
1051 | pl011_dma_probe(uap); | |
1052 | ||
68b65f73 RK |
1053 | if (!uap->dmatx.chan) |
1054 | return; | |
1055 | ||
4c0be45b | 1056 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); |
68b65f73 RK |
1057 | if (!uap->dmatx.buf) { |
1058 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
1059 | uap->port.fifosize = uap->fifosize; | |
1060 | return; | |
1061 | } | |
1062 | ||
1063 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
1064 | ||
1065 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
1066 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
1067 | uap->using_tx_dma = true; |
1068 | ||
1069 | if (!uap->dmarx.chan) | |
1070 | goto skip_rx; | |
1071 | ||
1072 | /* Allocate and map DMA RX buffers */ | |
1073 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1074 | DMA_FROM_DEVICE); | |
1075 | if (ret) { | |
1076 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1077 | "RX buffer A", ret); | |
1078 | goto skip_rx; | |
1079 | } | |
68b65f73 | 1080 | |
ead76f32 LW |
1081 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
1082 | DMA_FROM_DEVICE); | |
1083 | if (ret) { | |
1084 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1085 | "RX buffer B", ret); | |
1086 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1087 | DMA_FROM_DEVICE); | |
1088 | goto skip_rx; | |
1089 | } | |
1090 | ||
1091 | uap->using_rx_dma = true; | |
68b65f73 | 1092 | |
ead76f32 | 1093 | skip_rx: |
68b65f73 RK |
1094 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
1095 | uap->dmacr |= UART011_DMAONERR; | |
9f25bc51 | 1096 | pl011_write(uap->dmacr, uap, REG_DMACR); |
38d62436 RK |
1097 | |
1098 | /* | |
1099 | * ST Micro variants has some specific dma burst threshold | |
1100 | * compensation. Set this to 16 bytes, so burst will only | |
1101 | * be issued above/below 16 bytes. | |
1102 | */ | |
1103 | if (uap->vendor->dma_threshold) | |
75836339 | 1104 | pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, |
9f25bc51 | 1105 | uap, REG_ST_DMAWM); |
ead76f32 LW |
1106 | |
1107 | if (uap->using_rx_dma) { | |
1108 | if (pl011_dma_rx_trigger_dma(uap)) | |
1109 | dev_dbg(uap->port.dev, "could not trigger initial " | |
1110 | "RX DMA job, fall back to interrupt mode\n"); | |
cb06ff10 CM |
1111 | if (uap->dmarx.poll_rate) { |
1112 | init_timer(&(uap->dmarx.timer)); | |
1113 | uap->dmarx.timer.function = pl011_dma_rx_poll; | |
1114 | uap->dmarx.timer.data = (unsigned long)uap; | |
1115 | mod_timer(&uap->dmarx.timer, | |
1116 | jiffies + | |
1117 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1118 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1119 | uap->dmarx.last_jiffies = jiffies; | |
1120 | } | |
ead76f32 | 1121 | } |
68b65f73 RK |
1122 | } |
1123 | ||
1124 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1125 | { | |
ead76f32 | 1126 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
1127 | return; |
1128 | ||
1129 | /* Disable RX and TX DMA */ | |
9f25bc51 | 1130 | while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY) |
68b65f73 RK |
1131 | barrier(); |
1132 | ||
1133 | spin_lock_irq(&uap->port.lock); | |
1134 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
9f25bc51 | 1135 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
1136 | spin_unlock_irq(&uap->port.lock); |
1137 | ||
ead76f32 LW |
1138 | if (uap->using_tx_dma) { |
1139 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
1140 | dmaengine_terminate_all(uap->dmatx.chan); | |
1141 | if (uap->dmatx.queued) { | |
1142 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
1143 | DMA_TO_DEVICE); | |
1144 | uap->dmatx.queued = false; | |
1145 | } | |
1146 | ||
1147 | kfree(uap->dmatx.buf); | |
1148 | uap->using_tx_dma = false; | |
68b65f73 RK |
1149 | } |
1150 | ||
ead76f32 LW |
1151 | if (uap->using_rx_dma) { |
1152 | dmaengine_terminate_all(uap->dmarx.chan); | |
1153 | /* Clean up the RX DMA */ | |
1154 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); | |
1155 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); | |
cb06ff10 CM |
1156 | if (uap->dmarx.poll_rate) |
1157 | del_timer_sync(&uap->dmarx.timer); | |
ead76f32 LW |
1158 | uap->using_rx_dma = false; |
1159 | } | |
1160 | } | |
68b65f73 | 1161 | |
ead76f32 LW |
1162 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
1163 | { | |
1164 | return uap->using_rx_dma; | |
68b65f73 RK |
1165 | } |
1166 | ||
ead76f32 LW |
1167 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
1168 | { | |
1169 | return uap->using_rx_dma && uap->dmarx.running; | |
1170 | } | |
1171 | ||
68b65f73 RK |
1172 | #else |
1173 | /* Blank functions if the DMA engine is not available */ | |
1c9be310 | 1174 | static inline void pl011_dma_probe(struct uart_amba_port *uap) |
68b65f73 RK |
1175 | { |
1176 | } | |
1177 | ||
1178 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
1179 | { | |
1180 | } | |
1181 | ||
1182 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
1183 | { | |
1184 | } | |
1185 | ||
1186 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1187 | { | |
1188 | } | |
1189 | ||
1190 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
1191 | { | |
1192 | return false; | |
1193 | } | |
1194 | ||
1195 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
1196 | { | |
1197 | } | |
1198 | ||
1199 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
1200 | { | |
1201 | return false; | |
1202 | } | |
1203 | ||
ead76f32 LW |
1204 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
1205 | { | |
1206 | } | |
1207 | ||
1208 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1209 | { | |
1210 | } | |
1211 | ||
1212 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
1213 | { | |
1214 | return -EIO; | |
1215 | } | |
1216 | ||
1217 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
1218 | { | |
1219 | return false; | |
1220 | } | |
1221 | ||
1222 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
1223 | { | |
1224 | return false; | |
1225 | } | |
1226 | ||
68b65f73 RK |
1227 | #define pl011_dma_flush_buffer NULL |
1228 | #endif | |
1229 | ||
b129a8cc | 1230 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 | 1231 | { |
a5820c24 DT |
1232 | struct uart_amba_port *uap = |
1233 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1234 | |
1235 | uap->im &= ~UART011_TXIM; | |
9f25bc51 | 1236 | pl011_write(uap->im, uap, REG_IMSC); |
68b65f73 | 1237 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
1238 | } |
1239 | ||
1e84d223 | 1240 | static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); |
734745ca DM |
1241 | |
1242 | /* Start TX with programmed I/O only (no DMA) */ | |
1243 | static void pl011_start_tx_pio(struct uart_amba_port *uap) | |
1244 | { | |
1245 | uap->im |= UART011_TXIM; | |
9f25bc51 | 1246 | pl011_write(uap->im, uap, REG_IMSC); |
1e84d223 | 1247 | pl011_tx_chars(uap, false); |
734745ca DM |
1248 | } |
1249 | ||
b129a8cc | 1250 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 | 1251 | { |
a5820c24 DT |
1252 | struct uart_amba_port *uap = |
1253 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1254 | |
734745ca DM |
1255 | if (!pl011_dma_tx_start(uap)) |
1256 | pl011_start_tx_pio(uap); | |
1da177e4 LT |
1257 | } |
1258 | ||
1259 | static void pl011_stop_rx(struct uart_port *port) | |
1260 | { | |
a5820c24 DT |
1261 | struct uart_amba_port *uap = |
1262 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1263 | |
1264 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
1265 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
9f25bc51 | 1266 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
1267 | |
1268 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1269 | } |
1270 | ||
1271 | static void pl011_enable_ms(struct uart_port *port) | |
1272 | { | |
a5820c24 DT |
1273 | struct uart_amba_port *uap = |
1274 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1275 | |
1276 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
9f25bc51 | 1277 | pl011_write(uap->im, uap, REG_IMSC); |
1da177e4 LT |
1278 | } |
1279 | ||
7d12e780 | 1280 | static void pl011_rx_chars(struct uart_amba_port *uap) |
b83286bf FE |
1281 | __releases(&uap->port.lock) |
1282 | __acquires(&uap->port.lock) | |
1da177e4 | 1283 | { |
29772c4e | 1284 | pl011_fifo_to_tty(uap); |
1da177e4 | 1285 | |
2389b272 | 1286 | spin_unlock(&uap->port.lock); |
2e124b4a | 1287 | tty_flip_buffer_push(&uap->port.state->port); |
ead76f32 LW |
1288 | /* |
1289 | * If we were temporarily out of DMA mode for a while, | |
1290 | * attempt to switch back to DMA mode again. | |
1291 | */ | |
1292 | if (pl011_dma_rx_available(uap)) { | |
1293 | if (pl011_dma_rx_trigger_dma(uap)) { | |
1294 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " | |
1295 | "fall back to interrupt mode again\n"); | |
1296 | uap->im |= UART011_RXIM; | |
9f25bc51 | 1297 | pl011_write(uap->im, uap, REG_IMSC); |
cb06ff10 | 1298 | } else { |
89fa28db | 1299 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1300 | /* Start Rx DMA poll */ |
1301 | if (uap->dmarx.poll_rate) { | |
1302 | uap->dmarx.last_jiffies = jiffies; | |
1303 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1304 | mod_timer(&uap->dmarx.timer, | |
1305 | jiffies + | |
1306 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1307 | } | |
89fa28db | 1308 | #endif |
cb06ff10 | 1309 | } |
ead76f32 | 1310 | } |
2389b272 | 1311 | spin_lock(&uap->port.lock); |
1da177e4 LT |
1312 | } |
1313 | ||
1e84d223 DM |
1314 | static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, |
1315 | bool from_irq) | |
734745ca | 1316 | { |
1e84d223 | 1317 | if (unlikely(!from_irq) && |
9f25bc51 | 1318 | pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
1e84d223 DM |
1319 | return false; /* unable to transmit character */ |
1320 | ||
9f25bc51 | 1321 | pl011_write(c, uap, REG_DR); |
734745ca DM |
1322 | uap->port.icount.tx++; |
1323 | ||
1e84d223 | 1324 | return true; |
734745ca DM |
1325 | } |
1326 | ||
1e84d223 | 1327 | static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) |
1da177e4 | 1328 | { |
ebd2c8f6 | 1329 | struct circ_buf *xmit = &uap->port.state->xmit; |
1e84d223 | 1330 | int count = uap->fifosize >> 1; |
734745ca | 1331 | |
1da177e4 | 1332 | if (uap->port.x_char) { |
1e84d223 DM |
1333 | if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) |
1334 | return; | |
1da177e4 | 1335 | uap->port.x_char = 0; |
734745ca | 1336 | --count; |
1da177e4 LT |
1337 | } |
1338 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1339 | pl011_stop_tx(&uap->port); |
1e84d223 | 1340 | return; |
1da177e4 LT |
1341 | } |
1342 | ||
68b65f73 RK |
1343 | /* If we are using DMA mode, try to send some characters. */ |
1344 | if (pl011_dma_tx_irq(uap)) | |
1e84d223 | 1345 | return; |
68b65f73 | 1346 | |
1e84d223 DM |
1347 | do { |
1348 | if (likely(from_irq) && count-- == 0) | |
1da177e4 | 1349 | break; |
1e84d223 DM |
1350 | |
1351 | if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) | |
1352 | break; | |
1353 | ||
1354 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1355 | } while (!uart_circ_empty(xmit)); | |
1da177e4 LT |
1356 | |
1357 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1358 | uart_write_wakeup(&uap->port); | |
1359 | ||
1e84d223 | 1360 | if (uart_circ_empty(xmit)) |
b129a8cc | 1361 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1362 | } |
1363 | ||
1364 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1365 | { | |
1366 | unsigned int status, delta; | |
1367 | ||
9f25bc51 | 1368 | status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 LT |
1369 | |
1370 | delta = status ^ uap->old_status; | |
1371 | uap->old_status = status; | |
1372 | ||
1373 | if (!delta) | |
1374 | return; | |
1375 | ||
1376 | if (delta & UART01x_FR_DCD) | |
1377 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1378 | ||
062a68a5 | 1379 | if (delta & UART01x_FR_DSR) |
1da177e4 LT |
1380 | uap->port.icount.dsr++; |
1381 | ||
062a68a5 GKH |
1382 | if (delta & UART01x_FR_CTS) |
1383 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
1da177e4 | 1384 | |
bdc04e31 | 1385 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1386 | } |
1387 | ||
9c4ef4b0 AP |
1388 | static void check_apply_cts_event_workaround(struct uart_amba_port *uap) |
1389 | { | |
1390 | unsigned int dummy_read; | |
1391 | ||
1392 | if (!uap->vendor->cts_event_workaround) | |
1393 | return; | |
1394 | ||
1395 | /* workaround to make sure that all bits are unlocked.. */ | |
9f25bc51 | 1396 | pl011_write(0x00, uap, REG_ICR); |
9c4ef4b0 AP |
1397 | |
1398 | /* | |
1399 | * WA: introduce 26ns(1 uart clk) delay before W1C; | |
1400 | * single apb access will incur 2 pclk(133.12Mhz) delay, | |
1401 | * so add 2 dummy reads | |
1402 | */ | |
9f25bc51 RK |
1403 | dummy_read = pl011_read(uap, REG_ICR); |
1404 | dummy_read = pl011_read(uap, REG_ICR); | |
9c4ef4b0 AP |
1405 | } |
1406 | ||
7d12e780 | 1407 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1408 | { |
1409 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1410 | unsigned long flags; |
1da177e4 | 1411 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
075167ed | 1412 | u16 imsc; |
1da177e4 LT |
1413 | int handled = 0; |
1414 | ||
963cc981 | 1415 | spin_lock_irqsave(&uap->port.lock, flags); |
9f25bc51 RK |
1416 | imsc = pl011_read(uap, REG_IMSC); |
1417 | status = pl011_read(uap, REG_RIS) & imsc; | |
1da177e4 LT |
1418 | if (status) { |
1419 | do { | |
9c4ef4b0 | 1420 | check_apply_cts_event_workaround(uap); |
f11c9841 | 1421 | |
75836339 RK |
1422 | pl011_write(status & ~(UART011_TXIS|UART011_RTIS| |
1423 | UART011_RXIS), | |
9f25bc51 | 1424 | uap, REG_ICR); |
1da177e4 | 1425 | |
ead76f32 LW |
1426 | if (status & (UART011_RTIS|UART011_RXIS)) { |
1427 | if (pl011_dma_rx_running(uap)) | |
1428 | pl011_dma_rx_irq(uap); | |
1429 | else | |
1430 | pl011_rx_chars(uap); | |
1431 | } | |
1da177e4 LT |
1432 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1433 | UART011_CTSMIS|UART011_RIMIS)) | |
1434 | pl011_modem_status(uap); | |
1e84d223 DM |
1435 | if (status & UART011_TXIS) |
1436 | pl011_tx_chars(uap, true); | |
1da177e4 | 1437 | |
4fd0690b | 1438 | if (pass_counter-- == 0) |
1da177e4 LT |
1439 | break; |
1440 | ||
9f25bc51 | 1441 | status = pl011_read(uap, REG_RIS) & imsc; |
1da177e4 LT |
1442 | } while (status != 0); |
1443 | handled = 1; | |
1444 | } | |
1445 | ||
963cc981 | 1446 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
1447 | |
1448 | return IRQ_RETVAL(handled); | |
1449 | } | |
1450 | ||
e643f87f | 1451 | static unsigned int pl011_tx_empty(struct uart_port *port) |
1da177e4 | 1452 | { |
a5820c24 DT |
1453 | struct uart_amba_port *uap = |
1454 | container_of(port, struct uart_amba_port, port); | |
9f25bc51 | 1455 | unsigned int status = pl011_read(uap, REG_FR); |
062a68a5 | 1456 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; |
1da177e4 LT |
1457 | } |
1458 | ||
e643f87f | 1459 | static unsigned int pl011_get_mctrl(struct uart_port *port) |
1da177e4 | 1460 | { |
a5820c24 DT |
1461 | struct uart_amba_port *uap = |
1462 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1463 | unsigned int result = 0; |
9f25bc51 | 1464 | unsigned int status = pl011_read(uap, REG_FR); |
1da177e4 | 1465 | |
5159f407 | 1466 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
1467 | if (status & uartbit) \ |
1468 | result |= tiocmbit | |
1469 | ||
5159f407 | 1470 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
062a68a5 GKH |
1471 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); |
1472 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
1473 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
5159f407 | 1474 | #undef TIOCMBIT |
1da177e4 LT |
1475 | return result; |
1476 | } | |
1477 | ||
1478 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1479 | { | |
a5820c24 DT |
1480 | struct uart_amba_port *uap = |
1481 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1482 | unsigned int cr; |
1483 | ||
9f25bc51 | 1484 | cr = pl011_read(uap, REG_CR); |
1da177e4 | 1485 | |
5159f407 | 1486 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
1487 | if (mctrl & tiocmbit) \ |
1488 | cr |= uartbit; \ | |
1489 | else \ | |
1490 | cr &= ~uartbit | |
1491 | ||
5159f407 JS |
1492 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
1493 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
1494 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
1495 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
1496 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
1497 | |
1498 | if (uap->autorts) { | |
1499 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
1500 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
1501 | } | |
5159f407 | 1502 | #undef TIOCMBIT |
1da177e4 | 1503 | |
9f25bc51 | 1504 | pl011_write(cr, uap, REG_CR); |
1da177e4 LT |
1505 | } |
1506 | ||
1507 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1508 | { | |
a5820c24 DT |
1509 | struct uart_amba_port *uap = |
1510 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1511 | unsigned long flags; |
1512 | unsigned int lcr_h; | |
1513 | ||
1514 | spin_lock_irqsave(&uap->port.lock, flags); | |
b2a4e24c | 1515 | lcr_h = pl011_read(uap, uap->lcrh_tx); |
1da177e4 LT |
1516 | if (break_state == -1) |
1517 | lcr_h |= UART01x_LCRH_BRK; | |
1518 | else | |
1519 | lcr_h &= ~UART01x_LCRH_BRK; | |
b2a4e24c | 1520 | pl011_write(lcr_h, uap, uap->lcrh_tx); |
1da177e4 LT |
1521 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1522 | } | |
1523 | ||
84b5ae15 | 1524 | #ifdef CONFIG_CONSOLE_POLL |
5c8124a0 AV |
1525 | |
1526 | static void pl011_quiesce_irqs(struct uart_port *port) | |
1527 | { | |
a5820c24 DT |
1528 | struct uart_amba_port *uap = |
1529 | container_of(port, struct uart_amba_port, port); | |
5c8124a0 | 1530 | |
9f25bc51 | 1531 | pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); |
5c8124a0 AV |
1532 | /* |
1533 | * There is no way to clear TXIM as this is "ready to transmit IRQ", so | |
1534 | * we simply mask it. start_tx() will unmask it. | |
1535 | * | |
1536 | * Note we can race with start_tx(), and if the race happens, the | |
1537 | * polling user might get another interrupt just after we clear it. | |
1538 | * But it should be OK and can happen even w/o the race, e.g. | |
1539 | * controller immediately got some new data and raised the IRQ. | |
1540 | * | |
1541 | * And whoever uses polling routines assumes that it manages the device | |
1542 | * (including tx queue), so we're also fine with start_tx()'s caller | |
1543 | * side. | |
1544 | */ | |
9f25bc51 RK |
1545 | pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, |
1546 | REG_IMSC); | |
5c8124a0 AV |
1547 | } |
1548 | ||
e643f87f | 1549 | static int pl011_get_poll_char(struct uart_port *port) |
84b5ae15 | 1550 | { |
a5820c24 DT |
1551 | struct uart_amba_port *uap = |
1552 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 JW |
1553 | unsigned int status; |
1554 | ||
5c8124a0 AV |
1555 | /* |
1556 | * The caller might need IRQs lowered, e.g. if used with KDB NMI | |
1557 | * debugger. | |
1558 | */ | |
1559 | pl011_quiesce_irqs(port); | |
1560 | ||
9f25bc51 | 1561 | status = pl011_read(uap, REG_FR); |
f5316b4a JW |
1562 | if (status & UART01x_FR_RXFE) |
1563 | return NO_POLL_CHAR; | |
84b5ae15 | 1564 | |
9f25bc51 | 1565 | return pl011_read(uap, REG_DR); |
84b5ae15 JW |
1566 | } |
1567 | ||
e643f87f | 1568 | static void pl011_put_poll_char(struct uart_port *port, |
84b5ae15 JW |
1569 | unsigned char ch) |
1570 | { | |
a5820c24 DT |
1571 | struct uart_amba_port *uap = |
1572 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 | 1573 | |
9f25bc51 | 1574 | while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
84b5ae15 JW |
1575 | barrier(); |
1576 | ||
9f25bc51 | 1577 | pl011_write(ch, uap, REG_DR); |
84b5ae15 JW |
1578 | } |
1579 | ||
1580 | #endif /* CONFIG_CONSOLE_POLL */ | |
1581 | ||
b3564c2c | 1582 | static int pl011_hwinit(struct uart_port *port) |
1da177e4 | 1583 | { |
a5820c24 DT |
1584 | struct uart_amba_port *uap = |
1585 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1586 | int retval; |
1587 | ||
78d80c5a | 1588 | /* Optionaly enable pins to be muxed in and configured */ |
2b996fc5 | 1589 | pinctrl_pm_select_default_state(port->dev); |
78d80c5a | 1590 | |
1da177e4 LT |
1591 | /* |
1592 | * Try to enable the clock producer. | |
1593 | */ | |
1c4c4394 | 1594 | retval = clk_prepare_enable(uap->clk); |
1da177e4 | 1595 | if (retval) |
7f6d942a | 1596 | return retval; |
1da177e4 LT |
1597 | |
1598 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1599 | ||
9b96fbac | 1600 | /* Clear pending error and receive interrupts */ |
75836339 RK |
1601 | pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | |
1602 | UART011_FEIS | UART011_RTIS | UART011_RXIS, | |
9f25bc51 | 1603 | uap, REG_ICR); |
9b96fbac | 1604 | |
b3564c2c AV |
1605 | /* |
1606 | * Save interrupts enable mask, and enable RX interrupts in case if | |
1607 | * the interrupt is used for NMI entry. | |
1608 | */ | |
9f25bc51 RK |
1609 | uap->im = pl011_read(uap, REG_IMSC); |
1610 | pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); | |
b3564c2c | 1611 | |
574de559 | 1612 | if (dev_get_platdata(uap->port.dev)) { |
b3564c2c AV |
1613 | struct amba_pl011_data *plat; |
1614 | ||
574de559 | 1615 | plat = dev_get_platdata(uap->port.dev); |
b3564c2c AV |
1616 | if (plat->init) |
1617 | plat->init(); | |
1618 | } | |
1619 | return 0; | |
b3564c2c AV |
1620 | } |
1621 | ||
7fe9a5a9 RK |
1622 | static bool pl011_split_lcrh(const struct uart_amba_port *uap) |
1623 | { | |
9f25bc51 RK |
1624 | return pl011_reg_to_offset(uap, uap->lcrh_rx) != |
1625 | pl011_reg_to_offset(uap, uap->lcrh_tx); | |
7fe9a5a9 RK |
1626 | } |
1627 | ||
b60f2f66 JM |
1628 | static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) |
1629 | { | |
b2a4e24c | 1630 | pl011_write(lcr_h, uap, uap->lcrh_rx); |
7fe9a5a9 | 1631 | if (pl011_split_lcrh(uap)) { |
b60f2f66 JM |
1632 | int i; |
1633 | /* | |
1634 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1635 | * to get this delay write read only register 10 times | |
1636 | */ | |
1637 | for (i = 0; i < 10; ++i) | |
9f25bc51 | 1638 | pl011_write(0xff, uap, REG_MIS); |
b2a4e24c | 1639 | pl011_write(lcr_h, uap, uap->lcrh_tx); |
b60f2f66 JM |
1640 | } |
1641 | } | |
1642 | ||
867b8e8e AP |
1643 | static int pl011_allocate_irq(struct uart_amba_port *uap) |
1644 | { | |
9f25bc51 | 1645 | pl011_write(uap->im, uap, REG_IMSC); |
867b8e8e AP |
1646 | |
1647 | return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
1648 | } | |
1649 | ||
1650 | /* | |
1651 | * Enable interrupts, only timeouts when using DMA | |
1652 | * if initial RX DMA job failed, start in interrupt mode | |
1653 | * as well. | |
1654 | */ | |
1655 | static void pl011_enable_interrupts(struct uart_amba_port *uap) | |
1656 | { | |
1657 | spin_lock_irq(&uap->port.lock); | |
1658 | ||
1659 | /* Clear out any spuriously appearing RX interrupts */ | |
9f25bc51 | 1660 | pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); |
867b8e8e AP |
1661 | uap->im = UART011_RTIM; |
1662 | if (!pl011_dma_rx_running(uap)) | |
1663 | uap->im |= UART011_RXIM; | |
9f25bc51 | 1664 | pl011_write(uap->im, uap, REG_IMSC); |
867b8e8e AP |
1665 | spin_unlock_irq(&uap->port.lock); |
1666 | } | |
1667 | ||
b3564c2c AV |
1668 | static int pl011_startup(struct uart_port *port) |
1669 | { | |
a5820c24 DT |
1670 | struct uart_amba_port *uap = |
1671 | container_of(port, struct uart_amba_port, port); | |
734745ca | 1672 | unsigned int cr; |
b3564c2c AV |
1673 | int retval; |
1674 | ||
1675 | retval = pl011_hwinit(port); | |
1676 | if (retval) | |
1677 | goto clk_dis; | |
1678 | ||
867b8e8e | 1679 | retval = pl011_allocate_irq(uap); |
1da177e4 LT |
1680 | if (retval) |
1681 | goto clk_dis; | |
1682 | ||
9f25bc51 | 1683 | pl011_write(uap->vendor->ifls, uap, REG_IFLS); |
1da177e4 | 1684 | |
734745ca | 1685 | spin_lock_irq(&uap->port.lock); |
570d2910 | 1686 | |
d8d8ffa4 SKS |
1687 | /* restore RTS and DTR */ |
1688 | cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); | |
1689 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
9f25bc51 | 1690 | pl011_write(cr, uap, REG_CR); |
1da177e4 | 1691 | |
fe433907 JM |
1692 | spin_unlock_irq(&uap->port.lock); |
1693 | ||
1da177e4 LT |
1694 | /* |
1695 | * initialise the old status of the modem signals | |
1696 | */ | |
9f25bc51 | 1697 | uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 | 1698 | |
68b65f73 RK |
1699 | /* Startup DMA */ |
1700 | pl011_dma_startup(uap); | |
1701 | ||
867b8e8e | 1702 | pl011_enable_interrupts(uap); |
1da177e4 LT |
1703 | |
1704 | return 0; | |
1705 | ||
1706 | clk_dis: | |
1c4c4394 | 1707 | clk_disable_unprepare(uap->clk); |
1da177e4 LT |
1708 | return retval; |
1709 | } | |
1710 | ||
0dd1e247 AP |
1711 | static int sbsa_uart_startup(struct uart_port *port) |
1712 | { | |
1713 | struct uart_amba_port *uap = | |
1714 | container_of(port, struct uart_amba_port, port); | |
1715 | int retval; | |
1716 | ||
1717 | retval = pl011_hwinit(port); | |
1718 | if (retval) | |
1719 | return retval; | |
1720 | ||
1721 | retval = pl011_allocate_irq(uap); | |
1722 | if (retval) | |
1723 | return retval; | |
1724 | ||
1725 | /* The SBSA UART does not support any modem status lines. */ | |
1726 | uap->old_status = 0; | |
1727 | ||
1728 | pl011_enable_interrupts(uap); | |
1729 | ||
1730 | return 0; | |
1731 | } | |
1732 | ||
ec489aa8 LW |
1733 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
1734 | unsigned int lcrh) | |
1735 | { | |
f11c9841 | 1736 | unsigned long val; |
ec489aa8 | 1737 | |
b2a4e24c | 1738 | val = pl011_read(uap, lcrh); |
f11c9841 | 1739 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); |
b2a4e24c | 1740 | pl011_write(val, uap, lcrh); |
ec489aa8 LW |
1741 | } |
1742 | ||
95166a3f AP |
1743 | /* |
1744 | * disable the port. It should not disable RTS and DTR. | |
1745 | * Also RTS and DTR state should be preserved to restore | |
1746 | * it during startup(). | |
1747 | */ | |
1748 | static void pl011_disable_uart(struct uart_amba_port *uap) | |
1da177e4 | 1749 | { |
d8d8ffa4 | 1750 | unsigned int cr; |
1da177e4 | 1751 | |
3b43816f | 1752 | uap->autorts = false; |
fe433907 | 1753 | spin_lock_irq(&uap->port.lock); |
9f25bc51 | 1754 | cr = pl011_read(uap, REG_CR); |
d8d8ffa4 SKS |
1755 | uap->old_cr = cr; |
1756 | cr &= UART011_CR_RTS | UART011_CR_DTR; | |
1757 | cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
9f25bc51 | 1758 | pl011_write(cr, uap, REG_CR); |
fe433907 | 1759 | spin_unlock_irq(&uap->port.lock); |
1da177e4 LT |
1760 | |
1761 | /* | |
1762 | * disable break condition and fifos | |
1763 | */ | |
ec489aa8 | 1764 | pl011_shutdown_channel(uap, uap->lcrh_rx); |
7fe9a5a9 | 1765 | if (pl011_split_lcrh(uap)) |
ec489aa8 | 1766 | pl011_shutdown_channel(uap, uap->lcrh_tx); |
95166a3f AP |
1767 | } |
1768 | ||
1769 | static void pl011_disable_interrupts(struct uart_amba_port *uap) | |
1770 | { | |
1771 | spin_lock_irq(&uap->port.lock); | |
1772 | ||
1773 | /* mask all interrupts and clear all pending ones */ | |
1774 | uap->im = 0; | |
9f25bc51 RK |
1775 | pl011_write(uap->im, uap, REG_IMSC); |
1776 | pl011_write(0xffff, uap, REG_ICR); | |
95166a3f AP |
1777 | |
1778 | spin_unlock_irq(&uap->port.lock); | |
1779 | } | |
1780 | ||
1781 | static void pl011_shutdown(struct uart_port *port) | |
1782 | { | |
1783 | struct uart_amba_port *uap = | |
1784 | container_of(port, struct uart_amba_port, port); | |
1785 | ||
1786 | pl011_disable_interrupts(uap); | |
1787 | ||
1788 | pl011_dma_shutdown(uap); | |
1789 | ||
1790 | free_irq(uap->port.irq, uap); | |
1791 | ||
1792 | pl011_disable_uart(uap); | |
1da177e4 LT |
1793 | |
1794 | /* | |
1795 | * Shut down the clock producer | |
1796 | */ | |
1c4c4394 | 1797 | clk_disable_unprepare(uap->clk); |
78d80c5a | 1798 | /* Optionally let pins go into sleep states */ |
2b996fc5 | 1799 | pinctrl_pm_select_sleep_state(port->dev); |
c16d51a3 | 1800 | |
574de559 | 1801 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
1802 | struct amba_pl011_data *plat; |
1803 | ||
574de559 | 1804 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
1805 | if (plat->exit) |
1806 | plat->exit(); | |
1807 | } | |
1808 | ||
36f339d1 PH |
1809 | if (uap->port.ops->flush_buffer) |
1810 | uap->port.ops->flush_buffer(port); | |
1da177e4 LT |
1811 | } |
1812 | ||
0dd1e247 AP |
1813 | static void sbsa_uart_shutdown(struct uart_port *port) |
1814 | { | |
1815 | struct uart_amba_port *uap = | |
1816 | container_of(port, struct uart_amba_port, port); | |
1817 | ||
1818 | pl011_disable_interrupts(uap); | |
1819 | ||
1820 | free_irq(uap->port.irq, uap); | |
1821 | ||
1822 | if (uap->port.ops->flush_buffer) | |
1823 | uap->port.ops->flush_buffer(port); | |
1824 | } | |
1825 | ||
ef5a9358 AP |
1826 | static void |
1827 | pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) | |
1828 | { | |
1829 | port->read_status_mask = UART011_DR_OE | 255; | |
1830 | if (termios->c_iflag & INPCK) | |
1831 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; | |
1832 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) | |
1833 | port->read_status_mask |= UART011_DR_BE; | |
1834 | ||
1835 | /* | |
1836 | * Characters to ignore | |
1837 | */ | |
1838 | port->ignore_status_mask = 0; | |
1839 | if (termios->c_iflag & IGNPAR) | |
1840 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; | |
1841 | if (termios->c_iflag & IGNBRK) { | |
1842 | port->ignore_status_mask |= UART011_DR_BE; | |
1843 | /* | |
1844 | * If we're ignoring parity and break indicators, | |
1845 | * ignore overruns too (for real raw support). | |
1846 | */ | |
1847 | if (termios->c_iflag & IGNPAR) | |
1848 | port->ignore_status_mask |= UART011_DR_OE; | |
1849 | } | |
1850 | ||
1851 | /* | |
1852 | * Ignore all characters if CREAD is not set. | |
1853 | */ | |
1854 | if ((termios->c_cflag & CREAD) == 0) | |
1855 | port->ignore_status_mask |= UART_DUMMY_DR_RX; | |
1856 | } | |
1857 | ||
1da177e4 | 1858 | static void |
606d099c AC |
1859 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1860 | struct ktermios *old) | |
1da177e4 | 1861 | { |
a5820c24 DT |
1862 | struct uart_amba_port *uap = |
1863 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1864 | unsigned int lcr_h, old_cr; |
1865 | unsigned long flags; | |
c19f12b5 RK |
1866 | unsigned int baud, quot, clkdiv; |
1867 | ||
1868 | if (uap->vendor->oversampling) | |
1869 | clkdiv = 8; | |
1870 | else | |
1871 | clkdiv = 16; | |
1da177e4 LT |
1872 | |
1873 | /* | |
1874 | * Ask the core to calculate the divisor for us. | |
1875 | */ | |
ac3e3fb4 | 1876 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1877 | port->uartclk / clkdiv); |
89fa28db | 1878 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1879 | /* |
1880 | * Adjust RX DMA polling rate with baud rate if not specified. | |
1881 | */ | |
1882 | if (uap->dmarx.auto_poll_rate) | |
1883 | uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); | |
89fa28db | 1884 | #endif |
ac3e3fb4 LW |
1885 | |
1886 | if (baud > port->uartclk/16) | |
1887 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1888 | else | |
1889 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1890 | |
1891 | switch (termios->c_cflag & CSIZE) { | |
1892 | case CS5: | |
1893 | lcr_h = UART01x_LCRH_WLEN_5; | |
1894 | break; | |
1895 | case CS6: | |
1896 | lcr_h = UART01x_LCRH_WLEN_6; | |
1897 | break; | |
1898 | case CS7: | |
1899 | lcr_h = UART01x_LCRH_WLEN_7; | |
1900 | break; | |
1901 | default: // CS8 | |
1902 | lcr_h = UART01x_LCRH_WLEN_8; | |
1903 | break; | |
1904 | } | |
1905 | if (termios->c_cflag & CSTOPB) | |
1906 | lcr_h |= UART01x_LCRH_STP2; | |
1907 | if (termios->c_cflag & PARENB) { | |
1908 | lcr_h |= UART01x_LCRH_PEN; | |
1909 | if (!(termios->c_cflag & PARODD)) | |
1910 | lcr_h |= UART01x_LCRH_EPS; | |
1911 | } | |
ffca2b11 | 1912 | if (uap->fifosize > 1) |
1da177e4 LT |
1913 | lcr_h |= UART01x_LCRH_FEN; |
1914 | ||
1915 | spin_lock_irqsave(&port->lock, flags); | |
1916 | ||
1917 | /* | |
1918 | * Update the per-port timeout. | |
1919 | */ | |
1920 | uart_update_timeout(port, termios->c_cflag, baud); | |
1921 | ||
ef5a9358 | 1922 | pl011_setup_status_masks(port, termios); |
1da177e4 LT |
1923 | |
1924 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1925 | pl011_enable_ms(port); | |
1926 | ||
1927 | /* first, disable everything */ | |
9f25bc51 RK |
1928 | old_cr = pl011_read(uap, REG_CR); |
1929 | pl011_write(0, uap, REG_CR); | |
1da177e4 | 1930 | |
3b43816f RV |
1931 | if (termios->c_cflag & CRTSCTS) { |
1932 | if (old_cr & UART011_CR_RTS) | |
1933 | old_cr |= UART011_CR_RTSEN; | |
1934 | ||
1935 | old_cr |= UART011_CR_CTSEN; | |
1936 | uap->autorts = true; | |
1937 | } else { | |
1938 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1939 | uap->autorts = false; | |
1940 | } | |
1941 | ||
c19f12b5 RK |
1942 | if (uap->vendor->oversampling) { |
1943 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1944 | old_cr |= ST_UART011_CR_OVSFACT; |
1945 | else | |
1946 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1947 | } | |
1948 | ||
c5dd553b LW |
1949 | /* |
1950 | * Workaround for the ST Micro oversampling variants to | |
1951 | * increase the bitrate slightly, by lowering the divisor, | |
1952 | * to avoid delayed sampling of start bit at high speeds, | |
1953 | * else we see data corruption. | |
1954 | */ | |
1955 | if (uap->vendor->oversampling) { | |
1956 | if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) | |
1957 | quot -= 1; | |
1958 | else if ((baud > 3250000) && (quot > 2)) | |
1959 | quot -= 2; | |
1960 | } | |
1da177e4 | 1961 | /* Set baud rate */ |
9f25bc51 RK |
1962 | pl011_write(quot & 0x3f, uap, REG_FBRD); |
1963 | pl011_write(quot >> 6, uap, REG_IBRD); | |
1da177e4 LT |
1964 | |
1965 | /* | |
1966 | * ----------v----------v----------v----------v----- | |
c5dd553b | 1967 | * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER |
9f25bc51 | 1968 | * REG_FBRD & REG_IBRD. |
1da177e4 LT |
1969 | * ----------^----------^----------^----------^----- |
1970 | */ | |
b60f2f66 | 1971 | pl011_write_lcr_h(uap, lcr_h); |
9f25bc51 | 1972 | pl011_write(old_cr, uap, REG_CR); |
1da177e4 LT |
1973 | |
1974 | spin_unlock_irqrestore(&port->lock, flags); | |
1975 | } | |
1976 | ||
0dd1e247 AP |
1977 | static void |
1978 | sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, | |
1979 | struct ktermios *old) | |
1980 | { | |
1981 | struct uart_amba_port *uap = | |
1982 | container_of(port, struct uart_amba_port, port); | |
1983 | unsigned long flags; | |
1984 | ||
1985 | tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); | |
1986 | ||
1987 | /* The SBSA UART only supports 8n1 without hardware flow control. */ | |
1988 | termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); | |
1989 | termios->c_cflag &= ~(CMSPAR | CRTSCTS); | |
1990 | termios->c_cflag |= CS8 | CLOCAL; | |
1991 | ||
1992 | spin_lock_irqsave(&port->lock, flags); | |
1993 | uart_update_timeout(port, CS8, uap->fixed_baud); | |
1994 | pl011_setup_status_masks(port, termios); | |
1995 | spin_unlock_irqrestore(&port->lock, flags); | |
1996 | } | |
1997 | ||
1da177e4 LT |
1998 | static const char *pl011_type(struct uart_port *port) |
1999 | { | |
a5820c24 DT |
2000 | struct uart_amba_port *uap = |
2001 | container_of(port, struct uart_amba_port, port); | |
e8a7ba86 | 2002 | return uap->port.type == PORT_AMBA ? uap->type : NULL; |
1da177e4 LT |
2003 | } |
2004 | ||
2005 | /* | |
2006 | * Release the memory region(s) being used by 'port' | |
2007 | */ | |
e643f87f | 2008 | static void pl011_release_port(struct uart_port *port) |
1da177e4 LT |
2009 | { |
2010 | release_mem_region(port->mapbase, SZ_4K); | |
2011 | } | |
2012 | ||
2013 | /* | |
2014 | * Request the memory region(s) being used by 'port' | |
2015 | */ | |
e643f87f | 2016 | static int pl011_request_port(struct uart_port *port) |
1da177e4 LT |
2017 | { |
2018 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
2019 | != NULL ? 0 : -EBUSY; | |
2020 | } | |
2021 | ||
2022 | /* | |
2023 | * Configure/autoconfigure the port. | |
2024 | */ | |
e643f87f | 2025 | static void pl011_config_port(struct uart_port *port, int flags) |
1da177e4 LT |
2026 | { |
2027 | if (flags & UART_CONFIG_TYPE) { | |
2028 | port->type = PORT_AMBA; | |
e643f87f | 2029 | pl011_request_port(port); |
1da177e4 LT |
2030 | } |
2031 | } | |
2032 | ||
2033 | /* | |
2034 | * verify the new serial_struct (for TIOCSSERIAL). | |
2035 | */ | |
e643f87f | 2036 | static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) |
1da177e4 LT |
2037 | { |
2038 | int ret = 0; | |
2039 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
2040 | ret = -EINVAL; | |
a62c4133 | 2041 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
2042 | ret = -EINVAL; |
2043 | if (ser->baud_base < 9600) | |
2044 | ret = -EINVAL; | |
2045 | return ret; | |
2046 | } | |
2047 | ||
2048 | static struct uart_ops amba_pl011_pops = { | |
e643f87f | 2049 | .tx_empty = pl011_tx_empty, |
1da177e4 | 2050 | .set_mctrl = pl011_set_mctrl, |
e643f87f | 2051 | .get_mctrl = pl011_get_mctrl, |
1da177e4 LT |
2052 | .stop_tx = pl011_stop_tx, |
2053 | .start_tx = pl011_start_tx, | |
2054 | .stop_rx = pl011_stop_rx, | |
2055 | .enable_ms = pl011_enable_ms, | |
2056 | .break_ctl = pl011_break_ctl, | |
2057 | .startup = pl011_startup, | |
2058 | .shutdown = pl011_shutdown, | |
68b65f73 | 2059 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
2060 | .set_termios = pl011_set_termios, |
2061 | .type = pl011_type, | |
e643f87f LW |
2062 | .release_port = pl011_release_port, |
2063 | .request_port = pl011_request_port, | |
2064 | .config_port = pl011_config_port, | |
2065 | .verify_port = pl011_verify_port, | |
84b5ae15 | 2066 | #ifdef CONFIG_CONSOLE_POLL |
b3564c2c | 2067 | .poll_init = pl011_hwinit, |
e643f87f LW |
2068 | .poll_get_char = pl011_get_poll_char, |
2069 | .poll_put_char = pl011_put_poll_char, | |
84b5ae15 | 2070 | #endif |
1da177e4 LT |
2071 | }; |
2072 | ||
0dd1e247 AP |
2073 | static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
2074 | { | |
2075 | } | |
2076 | ||
2077 | static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) | |
2078 | { | |
2079 | return 0; | |
2080 | } | |
2081 | ||
2082 | static const struct uart_ops sbsa_uart_pops = { | |
2083 | .tx_empty = pl011_tx_empty, | |
2084 | .set_mctrl = sbsa_uart_set_mctrl, | |
2085 | .get_mctrl = sbsa_uart_get_mctrl, | |
2086 | .stop_tx = pl011_stop_tx, | |
2087 | .start_tx = pl011_start_tx, | |
2088 | .stop_rx = pl011_stop_rx, | |
2089 | .startup = sbsa_uart_startup, | |
2090 | .shutdown = sbsa_uart_shutdown, | |
2091 | .set_termios = sbsa_uart_set_termios, | |
2092 | .type = pl011_type, | |
2093 | .release_port = pl011_release_port, | |
2094 | .request_port = pl011_request_port, | |
2095 | .config_port = pl011_config_port, | |
2096 | .verify_port = pl011_verify_port, | |
2097 | #ifdef CONFIG_CONSOLE_POLL | |
2098 | .poll_init = pl011_hwinit, | |
2099 | .poll_get_char = pl011_get_poll_char, | |
2100 | .poll_put_char = pl011_put_poll_char, | |
2101 | #endif | |
2102 | }; | |
2103 | ||
1da177e4 LT |
2104 | static struct uart_amba_port *amba_ports[UART_NR]; |
2105 | ||
2106 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
2107 | ||
d358788f | 2108 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 2109 | { |
a5820c24 DT |
2110 | struct uart_amba_port *uap = |
2111 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 2112 | |
9f25bc51 | 2113 | while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
d358788f | 2114 | barrier(); |
9f25bc51 | 2115 | pl011_write(ch, uap, REG_DR); |
1da177e4 LT |
2116 | } |
2117 | ||
2118 | static void | |
2119 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
2120 | { | |
2121 | struct uart_amba_port *uap = amba_ports[co->index]; | |
71eec483 | 2122 | unsigned int status, old_cr = 0, new_cr; |
ef605fdb RV |
2123 | unsigned long flags; |
2124 | int locked = 1; | |
1da177e4 LT |
2125 | |
2126 | clk_enable(uap->clk); | |
2127 | ||
ef605fdb RV |
2128 | local_irq_save(flags); |
2129 | if (uap->port.sysrq) | |
2130 | locked = 0; | |
2131 | else if (oops_in_progress) | |
2132 | locked = spin_trylock(&uap->port.lock); | |
2133 | else | |
2134 | spin_lock(&uap->port.lock); | |
2135 | ||
1da177e4 LT |
2136 | /* |
2137 | * First save the CR then disable the interrupts | |
2138 | */ | |
71eec483 | 2139 | if (!uap->vendor->always_enabled) { |
9f25bc51 | 2140 | old_cr = pl011_read(uap, REG_CR); |
71eec483 AP |
2141 | new_cr = old_cr & ~UART011_CR_CTSEN; |
2142 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
9f25bc51 | 2143 | pl011_write(new_cr, uap, REG_CR); |
71eec483 | 2144 | } |
1da177e4 | 2145 | |
d358788f | 2146 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
2147 | |
2148 | /* | |
2149 | * Finally, wait for transmitter to become empty | |
2150 | * and restore the TCR | |
2151 | */ | |
2152 | do { | |
9f25bc51 | 2153 | status = pl011_read(uap, REG_FR); |
062a68a5 | 2154 | } while (status & UART01x_FR_BUSY); |
71eec483 | 2155 | if (!uap->vendor->always_enabled) |
9f25bc51 | 2156 | pl011_write(old_cr, uap, REG_CR); |
1da177e4 | 2157 | |
ef605fdb RV |
2158 | if (locked) |
2159 | spin_unlock(&uap->port.lock); | |
2160 | local_irq_restore(flags); | |
2161 | ||
1da177e4 LT |
2162 | clk_disable(uap->clk); |
2163 | } | |
2164 | ||
2165 | static void __init | |
2166 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
2167 | int *parity, int *bits) | |
2168 | { | |
9f25bc51 | 2169 | if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { |
1da177e4 LT |
2170 | unsigned int lcr_h, ibrd, fbrd; |
2171 | ||
b2a4e24c | 2172 | lcr_h = pl011_read(uap, uap->lcrh_tx); |
1da177e4 LT |
2173 | |
2174 | *parity = 'n'; | |
2175 | if (lcr_h & UART01x_LCRH_PEN) { | |
2176 | if (lcr_h & UART01x_LCRH_EPS) | |
2177 | *parity = 'e'; | |
2178 | else | |
2179 | *parity = 'o'; | |
2180 | } | |
2181 | ||
2182 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
2183 | *bits = 7; | |
2184 | else | |
2185 | *bits = 8; | |
2186 | ||
9f25bc51 RK |
2187 | ibrd = pl011_read(uap, REG_IBRD); |
2188 | fbrd = pl011_read(uap, REG_FBRD); | |
1da177e4 LT |
2189 | |
2190 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 2191 | |
c19f12b5 | 2192 | if (uap->vendor->oversampling) { |
9f25bc51 | 2193 | if (pl011_read(uap, REG_CR) |
ac3e3fb4 LW |
2194 | & ST_UART011_CR_OVSFACT) |
2195 | *baud *= 2; | |
2196 | } | |
1da177e4 LT |
2197 | } |
2198 | } | |
2199 | ||
2200 | static int __init pl011_console_setup(struct console *co, char *options) | |
2201 | { | |
2202 | struct uart_amba_port *uap; | |
2203 | int baud = 38400; | |
2204 | int bits = 8; | |
2205 | int parity = 'n'; | |
2206 | int flow = 'n'; | |
4b4851c6 | 2207 | int ret; |
1da177e4 LT |
2208 | |
2209 | /* | |
2210 | * Check whether an invalid uart number has been specified, and | |
2211 | * if so, search for the first available port that does have | |
2212 | * console support. | |
2213 | */ | |
2214 | if (co->index >= UART_NR) | |
2215 | co->index = 0; | |
2216 | uap = amba_ports[co->index]; | |
d28122a5 RK |
2217 | if (!uap) |
2218 | return -ENODEV; | |
1da177e4 | 2219 | |
78d80c5a | 2220 | /* Allow pins to be muxed in and configured */ |
2b996fc5 | 2221 | pinctrl_pm_select_default_state(uap->port.dev); |
78d80c5a | 2222 | |
4b4851c6 RK |
2223 | ret = clk_prepare(uap->clk); |
2224 | if (ret) | |
2225 | return ret; | |
2226 | ||
574de559 | 2227 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
2228 | struct amba_pl011_data *plat; |
2229 | ||
574de559 | 2230 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
2231 | if (plat->init) |
2232 | plat->init(); | |
2233 | } | |
2234 | ||
1da177e4 LT |
2235 | uap->port.uartclk = clk_get_rate(uap->clk); |
2236 | ||
cefc2d1d AP |
2237 | if (uap->vendor->fixed_options) { |
2238 | baud = uap->fixed_baud; | |
2239 | } else { | |
2240 | if (options) | |
2241 | uart_parse_options(options, | |
2242 | &baud, &parity, &bits, &flow); | |
2243 | else | |
2244 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
2245 | } | |
1da177e4 LT |
2246 | |
2247 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
2248 | } | |
2249 | ||
2d93486c | 2250 | static struct uart_driver amba_reg; |
1da177e4 LT |
2251 | static struct console amba_console = { |
2252 | .name = "ttyAMA", | |
2253 | .write = pl011_console_write, | |
2254 | .device = uart_console_device, | |
2255 | .setup = pl011_console_setup, | |
2256 | .flags = CON_PRINTBUFFER, | |
2257 | .index = -1, | |
2258 | .data = &amba_reg, | |
2259 | }; | |
2260 | ||
2261 | #define AMBA_CONSOLE (&amba_console) | |
0d3c673e RH |
2262 | |
2263 | static void pl011_putc(struct uart_port *port, int c) | |
2264 | { | |
9f25bc51 | 2265 | while (readl(port->membase + REG_FR) & UART01x_FR_TXFF) |
0d3c673e | 2266 | ; |
9f25bc51 RK |
2267 | writeb(c, port->membase + REG_DR); |
2268 | while (readl(port->membase + REG_FR) & UART01x_FR_BUSY) | |
0d3c673e RH |
2269 | ; |
2270 | } | |
2271 | ||
2272 | static void pl011_early_write(struct console *con, const char *s, unsigned n) | |
2273 | { | |
2274 | struct earlycon_device *dev = con->data; | |
2275 | ||
2276 | uart_console_write(&dev->port, s, n, pl011_putc); | |
2277 | } | |
2278 | ||
2279 | static int __init pl011_early_console_setup(struct earlycon_device *device, | |
2280 | const char *opt) | |
2281 | { | |
2282 | if (!device->port.membase) | |
2283 | return -ENODEV; | |
2284 | ||
2285 | device->con->write = pl011_early_write; | |
2286 | return 0; | |
2287 | } | |
2288 | EARLYCON_DECLARE(pl011, pl011_early_console_setup); | |
45e0f0f5 | 2289 | OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); |
0d3c673e | 2290 | |
1da177e4 LT |
2291 | #else |
2292 | #define AMBA_CONSOLE NULL | |
2293 | #endif | |
2294 | ||
2295 | static struct uart_driver amba_reg = { | |
2296 | .owner = THIS_MODULE, | |
2297 | .driver_name = "ttyAMA", | |
2298 | .dev_name = "ttyAMA", | |
2299 | .major = SERIAL_AMBA_MAJOR, | |
2300 | .minor = SERIAL_AMBA_MINOR, | |
2301 | .nr = UART_NR, | |
2302 | .cons = AMBA_CONSOLE, | |
2303 | }; | |
2304 | ||
32614aad ML |
2305 | static int pl011_probe_dt_alias(int index, struct device *dev) |
2306 | { | |
2307 | struct device_node *np; | |
2308 | static bool seen_dev_with_alias = false; | |
2309 | static bool seen_dev_without_alias = false; | |
2310 | int ret = index; | |
2311 | ||
2312 | if (!IS_ENABLED(CONFIG_OF)) | |
2313 | return ret; | |
2314 | ||
2315 | np = dev->of_node; | |
2316 | if (!np) | |
2317 | return ret; | |
2318 | ||
2319 | ret = of_alias_get_id(np, "serial"); | |
2320 | if (IS_ERR_VALUE(ret)) { | |
2321 | seen_dev_without_alias = true; | |
2322 | ret = index; | |
2323 | } else { | |
2324 | seen_dev_with_alias = true; | |
2325 | if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { | |
2326 | dev_warn(dev, "requested serial port %d not available.\n", ret); | |
2327 | ret = index; | |
2328 | } | |
2329 | } | |
2330 | ||
2331 | if (seen_dev_with_alias && seen_dev_without_alias) | |
2332 | dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); | |
2333 | ||
2334 | return ret; | |
2335 | } | |
2336 | ||
49bb3c86 AP |
2337 | /* unregisters the driver also if no more ports are left */ |
2338 | static void pl011_unregister_port(struct uart_amba_port *uap) | |
2339 | { | |
2340 | int i; | |
2341 | bool busy = false; | |
2342 | ||
2343 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { | |
2344 | if (amba_ports[i] == uap) | |
2345 | amba_ports[i] = NULL; | |
2346 | else if (amba_ports[i]) | |
2347 | busy = true; | |
2348 | } | |
2349 | pl011_dma_remove(uap); | |
2350 | if (!busy) | |
2351 | uart_unregister_driver(&amba_reg); | |
2352 | } | |
2353 | ||
3873e2d7 | 2354 | static int pl011_find_free_port(void) |
1da177e4 | 2355 | { |
3873e2d7 | 2356 | int i; |
1da177e4 LT |
2357 | |
2358 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
2359 | if (amba_ports[i] == NULL) | |
3873e2d7 | 2360 | return i; |
1da177e4 | 2361 | |
3873e2d7 AP |
2362 | return -EBUSY; |
2363 | } | |
1da177e4 | 2364 | |
3873e2d7 AP |
2365 | static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, |
2366 | struct resource *mmiobase, int index) | |
2367 | { | |
2368 | void __iomem *base; | |
32614aad | 2369 | |
3873e2d7 | 2370 | base = devm_ioremap_resource(dev, mmiobase); |
97a60eac KK |
2371 | if (IS_ERR(base)) |
2372 | return PTR_ERR(base); | |
1da177e4 | 2373 | |
3873e2d7 | 2374 | index = pl011_probe_dt_alias(index, dev); |
1da177e4 | 2375 | |
d8d8ffa4 | 2376 | uap->old_cr = 0; |
3873e2d7 AP |
2377 | uap->port.dev = dev; |
2378 | uap->port.mapbase = mmiobase->start; | |
1da177e4 LT |
2379 | uap->port.membase = base; |
2380 | uap->port.iotype = UPIO_MEM; | |
ffca2b11 | 2381 | uap->port.fifosize = uap->fifosize; |
1da177e4 | 2382 | uap->port.flags = UPF_BOOT_AUTOCONF; |
3873e2d7 | 2383 | uap->port.line = index; |
1da177e4 | 2384 | |
3873e2d7 | 2385 | amba_ports[index] = uap; |
c3d8b76f | 2386 | |
3873e2d7 AP |
2387 | return 0; |
2388 | } | |
e8a7ba86 | 2389 | |
3873e2d7 AP |
2390 | static int pl011_register_port(struct uart_amba_port *uap) |
2391 | { | |
2392 | int ret; | |
1da177e4 | 2393 | |
3873e2d7 | 2394 | /* Ensure interrupts from this UART are masked and cleared */ |
9f25bc51 RK |
2395 | pl011_write(0, uap, REG_IMSC); |
2396 | pl011_write(0xffff, uap, REG_ICR); | |
ef2889f7 TB |
2397 | |
2398 | if (!amba_reg.state) { | |
2399 | ret = uart_register_driver(&amba_reg); | |
2400 | if (ret < 0) { | |
3873e2d7 | 2401 | dev_err(uap->port.dev, |
1c9be310 | 2402 | "Failed to register AMBA-PL011 driver\n"); |
ef2889f7 TB |
2403 | return ret; |
2404 | } | |
2405 | } | |
2406 | ||
1da177e4 | 2407 | ret = uart_add_one_port(&amba_reg, &uap->port); |
49bb3c86 AP |
2408 | if (ret) |
2409 | pl011_unregister_port(uap); | |
7f6d942a | 2410 | |
1da177e4 LT |
2411 | return ret; |
2412 | } | |
2413 | ||
3873e2d7 AP |
2414 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
2415 | { | |
2416 | struct uart_amba_port *uap; | |
2417 | struct vendor_data *vendor = id->data; | |
2418 | int portnr, ret; | |
2419 | ||
2420 | portnr = pl011_find_free_port(); | |
2421 | if (portnr < 0) | |
2422 | return portnr; | |
2423 | ||
2424 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), | |
2425 | GFP_KERNEL); | |
2426 | if (!uap) | |
2427 | return -ENOMEM; | |
2428 | ||
2429 | uap->clk = devm_clk_get(&dev->dev, NULL); | |
2430 | if (IS_ERR(uap->clk)) | |
2431 | return PTR_ERR(uap->clk); | |
2432 | ||
439403bd | 2433 | uap->reg_offset = vendor->reg_offset; |
3873e2d7 AP |
2434 | uap->vendor = vendor; |
2435 | uap->lcrh_rx = vendor->lcrh_rx; | |
2436 | uap->lcrh_tx = vendor->lcrh_tx; | |
2437 | uap->fifosize = vendor->get_fifosize(dev); | |
2438 | uap->port.irq = dev->irq[0]; | |
2439 | uap->port.ops = &amba_pl011_pops; | |
2440 | ||
2441 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); | |
2442 | ||
2443 | ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); | |
2444 | if (ret) | |
2445 | return ret; | |
2446 | ||
2447 | amba_set_drvdata(dev, uap); | |
2448 | ||
2449 | return pl011_register_port(uap); | |
2450 | } | |
2451 | ||
1da177e4 LT |
2452 | static int pl011_remove(struct amba_device *dev) |
2453 | { | |
2454 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1da177e4 | 2455 | |
1da177e4 | 2456 | uart_remove_one_port(&amba_reg, &uap->port); |
49bb3c86 | 2457 | pl011_unregister_port(uap); |
1da177e4 LT |
2458 | return 0; |
2459 | } | |
2460 | ||
d0ce850d UH |
2461 | #ifdef CONFIG_PM_SLEEP |
2462 | static int pl011_suspend(struct device *dev) | |
b736b89f | 2463 | { |
d0ce850d | 2464 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2465 | |
2466 | if (!uap) | |
2467 | return -EINVAL; | |
2468 | ||
2469 | return uart_suspend_port(&amba_reg, &uap->port); | |
2470 | } | |
2471 | ||
d0ce850d | 2472 | static int pl011_resume(struct device *dev) |
b736b89f | 2473 | { |
d0ce850d | 2474 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2475 | |
2476 | if (!uap) | |
2477 | return -EINVAL; | |
2478 | ||
2479 | return uart_resume_port(&amba_reg, &uap->port); | |
2480 | } | |
2481 | #endif | |
2482 | ||
d0ce850d UH |
2483 | static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); |
2484 | ||
0dd1e247 AP |
2485 | static int sbsa_uart_probe(struct platform_device *pdev) |
2486 | { | |
2487 | struct uart_amba_port *uap; | |
2488 | struct resource *r; | |
2489 | int portnr, ret; | |
2490 | int baudrate; | |
2491 | ||
2492 | /* | |
2493 | * Check the mandatory baud rate parameter in the DT node early | |
2494 | * so that we can easily exit with the error. | |
2495 | */ | |
2496 | if (pdev->dev.of_node) { | |
2497 | struct device_node *np = pdev->dev.of_node; | |
2498 | ||
2499 | ret = of_property_read_u32(np, "current-speed", &baudrate); | |
2500 | if (ret) | |
2501 | return ret; | |
2502 | } else { | |
2503 | baudrate = 115200; | |
2504 | } | |
2505 | ||
2506 | portnr = pl011_find_free_port(); | |
2507 | if (portnr < 0) | |
2508 | return portnr; | |
2509 | ||
2510 | uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), | |
2511 | GFP_KERNEL); | |
2512 | if (!uap) | |
2513 | return -ENOMEM; | |
2514 | ||
439403bd | 2515 | uap->reg_offset = vendor_sbsa.reg_offset; |
0dd1e247 AP |
2516 | uap->vendor = &vendor_sbsa; |
2517 | uap->fifosize = 32; | |
2518 | uap->port.irq = platform_get_irq(pdev, 0); | |
2519 | uap->port.ops = &sbsa_uart_pops; | |
2520 | uap->fixed_baud = baudrate; | |
2521 | ||
2522 | snprintf(uap->type, sizeof(uap->type), "SBSA"); | |
2523 | ||
2524 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2525 | ||
2526 | ret = pl011_setup_port(&pdev->dev, uap, r, portnr); | |
2527 | if (ret) | |
2528 | return ret; | |
2529 | ||
2530 | platform_set_drvdata(pdev, uap); | |
2531 | ||
2532 | return pl011_register_port(uap); | |
2533 | } | |
2534 | ||
2535 | static int sbsa_uart_remove(struct platform_device *pdev) | |
2536 | { | |
2537 | struct uart_amba_port *uap = platform_get_drvdata(pdev); | |
2538 | ||
2539 | uart_remove_one_port(&amba_reg, &uap->port); | |
2540 | pl011_unregister_port(uap); | |
2541 | return 0; | |
2542 | } | |
2543 | ||
2544 | static const struct of_device_id sbsa_uart_of_match[] = { | |
2545 | { .compatible = "arm,sbsa-uart", }, | |
2546 | {}, | |
2547 | }; | |
2548 | MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); | |
2549 | ||
3db9ab0b GG |
2550 | static const struct acpi_device_id sbsa_uart_acpi_match[] = { |
2551 | { "ARMH0011", 0 }, | |
2552 | {}, | |
2553 | }; | |
2554 | MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); | |
2555 | ||
0dd1e247 AP |
2556 | static struct platform_driver arm_sbsa_uart_platform_driver = { |
2557 | .probe = sbsa_uart_probe, | |
2558 | .remove = sbsa_uart_remove, | |
2559 | .driver = { | |
2560 | .name = "sbsa-uart", | |
2561 | .of_match_table = of_match_ptr(sbsa_uart_of_match), | |
3db9ab0b | 2562 | .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), |
0dd1e247 AP |
2563 | }, |
2564 | }; | |
2565 | ||
2c39c9e1 | 2566 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
2567 | { |
2568 | .id = 0x00041011, | |
2569 | .mask = 0x000fffff, | |
5926a295 AR |
2570 | .data = &vendor_arm, |
2571 | }, | |
2572 | { | |
2573 | .id = 0x00380802, | |
2574 | .mask = 0x00ffffff, | |
2575 | .data = &vendor_st, | |
1da177e4 LT |
2576 | }, |
2577 | { 0, 0 }, | |
2578 | }; | |
2579 | ||
60f7a33b DM |
2580 | MODULE_DEVICE_TABLE(amba, pl011_ids); |
2581 | ||
1da177e4 LT |
2582 | static struct amba_driver pl011_driver = { |
2583 | .drv = { | |
2584 | .name = "uart-pl011", | |
d0ce850d | 2585 | .pm = &pl011_dev_pm_ops, |
1da177e4 LT |
2586 | }, |
2587 | .id_table = pl011_ids, | |
2588 | .probe = pl011_probe, | |
2589 | .remove = pl011_remove, | |
2590 | }; | |
2591 | ||
2592 | static int __init pl011_init(void) | |
2593 | { | |
1da177e4 LT |
2594 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); |
2595 | ||
0dd1e247 AP |
2596 | if (platform_driver_register(&arm_sbsa_uart_platform_driver)) |
2597 | pr_warn("could not register SBSA UART platform driver\n"); | |
062a68a5 | 2598 | return amba_driver_register(&pl011_driver); |
1da177e4 LT |
2599 | } |
2600 | ||
2601 | static void __exit pl011_exit(void) | |
2602 | { | |
0dd1e247 | 2603 | platform_driver_unregister(&arm_sbsa_uart_platform_driver); |
1da177e4 | 2604 | amba_driver_unregister(&pl011_driver); |
1da177e4 LT |
2605 | } |
2606 | ||
4dd9e742 AR |
2607 | /* |
2608 | * While this can be a module, if builtin it's most likely the console | |
2609 | * So let's leave module_exit but move module_init to an earlier place | |
2610 | */ | |
2611 | arch_initcall(pl011_init); | |
1da177e4 LT |
2612 | module_exit(pl011_exit); |
2613 | ||
2614 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
2615 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
2616 | MODULE_LICENSE("GPL"); |