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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for AMBA serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright 1999 ARM Limited | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 8 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
1da177e4 LT |
24 | * This is a generic driver for ARM AMBA-type serial ports. They |
25 | * have a lot of 16550-like features, but are not register compatible. | |
26 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
27 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
28 | * required, these have to be supplied via some other means (eg, GPIO) | |
29 | * and hooked into this driver. | |
30 | */ | |
1da177e4 | 31 | |
cb06ff10 | 32 | |
1da177e4 LT |
33 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
34 | #define SUPPORT_SYSRQ | |
35 | #endif | |
36 | ||
37 | #include <linux/module.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/console.h> | |
41 | #include <linux/sysrq.h> | |
42 | #include <linux/device.h> | |
43 | #include <linux/tty.h> | |
44 | #include <linux/tty_flip.h> | |
45 | #include <linux/serial_core.h> | |
46 | #include <linux/serial.h> | |
a62c80e5 RK |
47 | #include <linux/amba/bus.h> |
48 | #include <linux/amba/serial.h> | |
f8ce2547 | 49 | #include <linux/clk.h> |
5a0e3ad6 | 50 | #include <linux/slab.h> |
68b65f73 RK |
51 | #include <linux/dmaengine.h> |
52 | #include <linux/dma-mapping.h> | |
53 | #include <linux/scatterlist.h> | |
c16d51a3 | 54 | #include <linux/delay.h> |
258aea76 | 55 | #include <linux/types.h> |
32614aad ML |
56 | #include <linux/of.h> |
57 | #include <linux/of_device.h> | |
258e0551 | 58 | #include <linux/pinctrl/consumer.h> |
cb70706c | 59 | #include <linux/sizes.h> |
de609582 | 60 | #include <linux/io.h> |
3db9ab0b | 61 | #include <linux/acpi.h> |
1da177e4 | 62 | |
9f25bc51 RK |
63 | #include "amba-pl011.h" |
64 | ||
1da177e4 LT |
65 | #define UART_NR 14 |
66 | ||
67 | #define SERIAL_AMBA_MAJOR 204 | |
68 | #define SERIAL_AMBA_MINOR 64 | |
69 | #define SERIAL_AMBA_NR UART_NR | |
70 | ||
71 | #define AMBA_ISR_PASS_LIMIT 256 | |
72 | ||
b63d4f0f RK |
73 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
74 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 75 | |
debb7f64 RK |
76 | static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { |
77 | [REG_DR] = UART01x_DR, | |
debb7f64 | 78 | [REG_FR] = UART01x_FR, |
e4df9a80 RK |
79 | [REG_LCRH_RX] = UART011_LCRH, |
80 | [REG_LCRH_TX] = UART011_LCRH, | |
debb7f64 RK |
81 | [REG_IBRD] = UART011_IBRD, |
82 | [REG_FBRD] = UART011_FBRD, | |
debb7f64 RK |
83 | [REG_CR] = UART011_CR, |
84 | [REG_IFLS] = UART011_IFLS, | |
85 | [REG_IMSC] = UART011_IMSC, | |
86 | [REG_RIS] = UART011_RIS, | |
87 | [REG_MIS] = UART011_MIS, | |
88 | [REG_ICR] = UART011_ICR, | |
89 | [REG_DMACR] = UART011_DMACR, | |
debb7f64 RK |
90 | }; |
91 | ||
5926a295 AR |
92 | /* There is by now at least one vendor with differing details, so handle it */ |
93 | struct vendor_data { | |
439403bd | 94 | const u16 *reg_offset; |
5926a295 | 95 | unsigned int ifls; |
84c3e03b | 96 | bool access_32b; |
ac3e3fb4 | 97 | bool oversampling; |
38d62436 | 98 | bool dma_threshold; |
4fd0690b | 99 | bool cts_event_workaround; |
71eec483 | 100 | bool always_enabled; |
cefc2d1d | 101 | bool fixed_options; |
78506f22 | 102 | |
ea33640a | 103 | unsigned int (*get_fifosize)(struct amba_device *dev); |
5926a295 AR |
104 | }; |
105 | ||
ea33640a | 106 | static unsigned int get_fifosize_arm(struct amba_device *dev) |
78506f22 | 107 | { |
ea33640a | 108 | return amba_rev(dev) < 3 ? 16 : 32; |
78506f22 JK |
109 | } |
110 | ||
5926a295 | 111 | static struct vendor_data vendor_arm = { |
439403bd | 112 | .reg_offset = pl011_std_offsets, |
5926a295 | 113 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, |
ac3e3fb4 | 114 | .oversampling = false, |
38d62436 | 115 | .dma_threshold = false, |
4fd0690b | 116 | .cts_event_workaround = false, |
71eec483 | 117 | .always_enabled = false, |
cefc2d1d | 118 | .fixed_options = false, |
78506f22 | 119 | .get_fifosize = get_fifosize_arm, |
5926a295 AR |
120 | }; |
121 | ||
0dd1e247 | 122 | static struct vendor_data vendor_sbsa = { |
439403bd | 123 | .reg_offset = pl011_std_offsets, |
1aabf523 | 124 | .access_32b = true, |
0dd1e247 AP |
125 | .oversampling = false, |
126 | .dma_threshold = false, | |
127 | .cts_event_workaround = false, | |
128 | .always_enabled = true, | |
129 | .fixed_options = true, | |
130 | }; | |
131 | ||
bf69ff8a RK |
132 | static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { |
133 | [REG_DR] = UART01x_DR, | |
134 | [REG_ST_DMAWM] = ST_UART011_DMAWM, | |
135 | [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, | |
136 | [REG_FR] = UART01x_FR, | |
e4df9a80 RK |
137 | [REG_LCRH_RX] = ST_UART011_LCRH_RX, |
138 | [REG_LCRH_TX] = ST_UART011_LCRH_TX, | |
bf69ff8a RK |
139 | [REG_IBRD] = UART011_IBRD, |
140 | [REG_FBRD] = UART011_FBRD, | |
bf69ff8a RK |
141 | [REG_CR] = UART011_CR, |
142 | [REG_IFLS] = UART011_IFLS, | |
143 | [REG_IMSC] = UART011_IMSC, | |
144 | [REG_RIS] = UART011_RIS, | |
145 | [REG_MIS] = UART011_MIS, | |
146 | [REG_ICR] = UART011_ICR, | |
147 | [REG_DMACR] = UART011_DMACR, | |
148 | [REG_ST_XFCR] = ST_UART011_XFCR, | |
149 | [REG_ST_XON1] = ST_UART011_XON1, | |
150 | [REG_ST_XON2] = ST_UART011_XON2, | |
151 | [REG_ST_XOFF1] = ST_UART011_XOFF1, | |
152 | [REG_ST_XOFF2] = ST_UART011_XOFF2, | |
153 | [REG_ST_ITCR] = ST_UART011_ITCR, | |
154 | [REG_ST_ITIP] = ST_UART011_ITIP, | |
155 | [REG_ST_ABCR] = ST_UART011_ABCR, | |
156 | [REG_ST_ABIMSC] = ST_UART011_ABIMSC, | |
157 | }; | |
158 | ||
ea33640a | 159 | static unsigned int get_fifosize_st(struct amba_device *dev) |
78506f22 JK |
160 | { |
161 | return 64; | |
162 | } | |
163 | ||
5926a295 | 164 | static struct vendor_data vendor_st = { |
bf69ff8a | 165 | .reg_offset = pl011_st_offsets, |
5926a295 | 166 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, |
ac3e3fb4 | 167 | .oversampling = true, |
38d62436 | 168 | .dma_threshold = true, |
4fd0690b | 169 | .cts_event_workaround = true, |
71eec483 | 170 | .always_enabled = false, |
cefc2d1d | 171 | .fixed_options = false, |
78506f22 | 172 | .get_fifosize = get_fifosize_st, |
1da177e4 LT |
173 | }; |
174 | ||
7ec75871 RK |
175 | static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = { |
176 | [REG_DR] = ZX_UART011_DR, | |
177 | [REG_FR] = ZX_UART011_FR, | |
178 | [REG_LCRH_RX] = ZX_UART011_LCRH, | |
179 | [REG_LCRH_TX] = ZX_UART011_LCRH, | |
180 | [REG_IBRD] = ZX_UART011_IBRD, | |
181 | [REG_FBRD] = ZX_UART011_FBRD, | |
182 | [REG_CR] = ZX_UART011_CR, | |
183 | [REG_IFLS] = ZX_UART011_IFLS, | |
184 | [REG_IMSC] = ZX_UART011_IMSC, | |
185 | [REG_RIS] = ZX_UART011_RIS, | |
186 | [REG_MIS] = ZX_UART011_MIS, | |
187 | [REG_ICR] = ZX_UART011_ICR, | |
188 | [REG_DMACR] = ZX_UART011_DMACR, | |
189 | }; | |
190 | ||
ff52a9a0 | 191 | static struct vendor_data vendor_zte __maybe_unused = { |
7ec75871 RK |
192 | .reg_offset = pl011_zte_offsets, |
193 | .access_32b = true, | |
194 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
195 | .get_fifosize = get_fifosize_arm, | |
196 | }; | |
197 | ||
68b65f73 | 198 | /* Deals with DMA transactions */ |
ead76f32 LW |
199 | |
200 | struct pl011_sgbuf { | |
201 | struct scatterlist sg; | |
202 | char *buf; | |
203 | }; | |
204 | ||
205 | struct pl011_dmarx_data { | |
206 | struct dma_chan *chan; | |
207 | struct completion complete; | |
208 | bool use_buf_b; | |
209 | struct pl011_sgbuf sgbuf_a; | |
210 | struct pl011_sgbuf sgbuf_b; | |
211 | dma_cookie_t cookie; | |
212 | bool running; | |
cb06ff10 CM |
213 | struct timer_list timer; |
214 | unsigned int last_residue; | |
215 | unsigned long last_jiffies; | |
216 | bool auto_poll_rate; | |
217 | unsigned int poll_rate; | |
218 | unsigned int poll_timeout; | |
ead76f32 LW |
219 | }; |
220 | ||
68b65f73 RK |
221 | struct pl011_dmatx_data { |
222 | struct dma_chan *chan; | |
223 | struct scatterlist sg; | |
224 | char *buf; | |
225 | bool queued; | |
226 | }; | |
227 | ||
c19f12b5 RK |
228 | /* |
229 | * We wrap our port structure around the generic uart_port. | |
230 | */ | |
231 | struct uart_amba_port { | |
232 | struct uart_port port; | |
debb7f64 | 233 | const u16 *reg_offset; |
c19f12b5 RK |
234 | struct clk *clk; |
235 | const struct vendor_data *vendor; | |
68b65f73 | 236 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
237 | unsigned int im; /* interrupt mask */ |
238 | unsigned int old_status; | |
ffca2b11 | 239 | unsigned int fifosize; /* vendor-specific */ |
d8d8ffa4 | 240 | unsigned int old_cr; /* state during shutdown */ |
c19f12b5 | 241 | bool autorts; |
cefc2d1d | 242 | unsigned int fixed_baud; /* vendor-set fixed baud rate */ |
c19f12b5 | 243 | char type[12]; |
68b65f73 RK |
244 | #ifdef CONFIG_DMA_ENGINE |
245 | /* DMA stuff */ | |
ead76f32 LW |
246 | bool using_tx_dma; |
247 | bool using_rx_dma; | |
248 | struct pl011_dmarx_data dmarx; | |
68b65f73 | 249 | struct pl011_dmatx_data dmatx; |
1c9be310 | 250 | bool dma_probed; |
68b65f73 RK |
251 | #endif |
252 | }; | |
253 | ||
9f25bc51 RK |
254 | static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, |
255 | unsigned int reg) | |
256 | { | |
debb7f64 | 257 | return uap->reg_offset[reg]; |
9f25bc51 RK |
258 | } |
259 | ||
b2a4e24c RK |
260 | static unsigned int pl011_read(const struct uart_amba_port *uap, |
261 | unsigned int reg) | |
75836339 | 262 | { |
84c3e03b RK |
263 | void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); |
264 | ||
3b78fae7 TT |
265 | return (uap->port.iotype == UPIO_MEM32) ? |
266 | readl_relaxed(addr) : readw_relaxed(addr); | |
75836339 RK |
267 | } |
268 | ||
b2a4e24c RK |
269 | static void pl011_write(unsigned int val, const struct uart_amba_port *uap, |
270 | unsigned int reg) | |
75836339 | 271 | { |
84c3e03b RK |
272 | void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); |
273 | ||
3b78fae7 | 274 | if (uap->port.iotype == UPIO_MEM32) |
f5ce6edd | 275 | writel_relaxed(val, addr); |
84c3e03b | 276 | else |
f5ce6edd | 277 | writew_relaxed(val, addr); |
75836339 RK |
278 | } |
279 | ||
29772c4e LW |
280 | /* |
281 | * Reads up to 256 characters from the FIFO or until it's empty and | |
282 | * inserts them into the TTY layer. Returns the number of characters | |
283 | * read from the FIFO. | |
284 | */ | |
285 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) | |
286 | { | |
71a5cd8a TT |
287 | u16 status; |
288 | unsigned int ch, flag, max_count = 256; | |
29772c4e LW |
289 | int fifotaken = 0; |
290 | ||
291 | while (max_count--) { | |
9f25bc51 | 292 | status = pl011_read(uap, REG_FR); |
29772c4e LW |
293 | if (status & UART01x_FR_RXFE) |
294 | break; | |
295 | ||
296 | /* Take chars from the FIFO and update status */ | |
9f25bc51 | 297 | ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; |
29772c4e LW |
298 | flag = TTY_NORMAL; |
299 | uap->port.icount.rx++; | |
300 | fifotaken++; | |
301 | ||
302 | if (unlikely(ch & UART_DR_ERROR)) { | |
303 | if (ch & UART011_DR_BE) { | |
304 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
305 | uap->port.icount.brk++; | |
306 | if (uart_handle_break(&uap->port)) | |
307 | continue; | |
308 | } else if (ch & UART011_DR_PE) | |
309 | uap->port.icount.parity++; | |
310 | else if (ch & UART011_DR_FE) | |
311 | uap->port.icount.frame++; | |
312 | if (ch & UART011_DR_OE) | |
313 | uap->port.icount.overrun++; | |
314 | ||
315 | ch &= uap->port.read_status_mask; | |
316 | ||
317 | if (ch & UART011_DR_BE) | |
318 | flag = TTY_BREAK; | |
319 | else if (ch & UART011_DR_PE) | |
320 | flag = TTY_PARITY; | |
321 | else if (ch & UART011_DR_FE) | |
322 | flag = TTY_FRAME; | |
323 | } | |
324 | ||
325 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) | |
326 | continue; | |
327 | ||
328 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
329 | } | |
330 | ||
331 | return fifotaken; | |
332 | } | |
333 | ||
334 | ||
68b65f73 RK |
335 | /* |
336 | * All the DMA operation mode stuff goes inside this ifdef. | |
337 | * This assumes that you have a generic DMA device interface, | |
338 | * no custom DMA interfaces are supported. | |
339 | */ | |
340 | #ifdef CONFIG_DMA_ENGINE | |
341 | ||
342 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
343 | ||
ead76f32 LW |
344 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
345 | enum dma_data_direction dir) | |
346 | { | |
cb06ff10 CM |
347 | dma_addr_t dma_addr; |
348 | ||
349 | sg->buf = dma_alloc_coherent(chan->device->dev, | |
350 | PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); | |
ead76f32 LW |
351 | if (!sg->buf) |
352 | return -ENOMEM; | |
353 | ||
cb06ff10 CM |
354 | sg_init_table(&sg->sg, 1); |
355 | sg_set_page(&sg->sg, phys_to_page(dma_addr), | |
356 | PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); | |
357 | sg_dma_address(&sg->sg) = dma_addr; | |
c64be923 | 358 | sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; |
ead76f32 | 359 | |
ead76f32 LW |
360 | return 0; |
361 | } | |
362 | ||
363 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |
364 | enum dma_data_direction dir) | |
365 | { | |
366 | if (sg->buf) { | |
cb06ff10 CM |
367 | dma_free_coherent(chan->device->dev, |
368 | PL011_DMA_BUFFER_SIZE, sg->buf, | |
369 | sg_dma_address(&sg->sg)); | |
ead76f32 LW |
370 | } |
371 | } | |
372 | ||
1c9be310 | 373 | static void pl011_dma_probe(struct uart_amba_port *uap) |
68b65f73 RK |
374 | { |
375 | /* DMA is the sole user of the platform data right now */ | |
574de559 | 376 | struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); |
1c9be310 | 377 | struct device *dev = uap->port.dev; |
68b65f73 | 378 | struct dma_slave_config tx_conf = { |
9f25bc51 RK |
379 | .dst_addr = uap->port.mapbase + |
380 | pl011_reg_to_offset(uap, REG_DR), | |
68b65f73 | 381 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, |
a485df4b | 382 | .direction = DMA_MEM_TO_DEV, |
68b65f73 | 383 | .dst_maxburst = uap->fifosize >> 1, |
258aea76 | 384 | .device_fc = false, |
68b65f73 RK |
385 | }; |
386 | struct dma_chan *chan; | |
387 | dma_cap_mask_t mask; | |
388 | ||
1c9be310 JRO |
389 | uap->dma_probed = true; |
390 | chan = dma_request_slave_channel_reason(dev, "tx"); | |
391 | if (IS_ERR(chan)) { | |
392 | if (PTR_ERR(chan) == -EPROBE_DEFER) { | |
1c9be310 JRO |
393 | uap->dma_probed = false; |
394 | return; | |
395 | } | |
68b65f73 | 396 | |
787b0c1f AB |
397 | /* We need platform data */ |
398 | if (!plat || !plat->dma_filter) { | |
399 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
400 | return; | |
401 | } | |
402 | ||
403 | /* Try to acquire a generic DMA engine slave TX channel */ | |
404 | dma_cap_zero(mask); | |
405 | dma_cap_set(DMA_SLAVE, mask); | |
406 | ||
407 | chan = dma_request_channel(mask, plat->dma_filter, | |
408 | plat->dma_tx_param); | |
409 | if (!chan) { | |
410 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
411 | return; | |
412 | } | |
68b65f73 RK |
413 | } |
414 | ||
415 | dmaengine_slave_config(chan, &tx_conf); | |
416 | uap->dmatx.chan = chan; | |
417 | ||
418 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
419 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
420 | |
421 | /* Optionally make use of an RX channel as well */ | |
787b0c1f | 422 | chan = dma_request_slave_channel(dev, "rx"); |
0d3c673e | 423 | |
d9e105ca | 424 | if (!chan && plat && plat->dma_rx_param) { |
787b0c1f AB |
425 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); |
426 | ||
427 | if (!chan) { | |
428 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
429 | return; | |
430 | } | |
431 | } | |
432 | ||
433 | if (chan) { | |
ead76f32 | 434 | struct dma_slave_config rx_conf = { |
9f25bc51 RK |
435 | .src_addr = uap->port.mapbase + |
436 | pl011_reg_to_offset(uap, REG_DR), | |
ead76f32 | 437 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, |
a485df4b | 438 | .direction = DMA_DEV_TO_MEM, |
b2aeb775 | 439 | .src_maxburst = uap->fifosize >> 2, |
258aea76 | 440 | .device_fc = false, |
ead76f32 | 441 | }; |
2d3b7d6e AJ |
442 | struct dma_slave_caps caps; |
443 | ||
444 | /* | |
445 | * Some DMA controllers provide information on their capabilities. | |
446 | * If the controller does, check for suitable residue processing | |
447 | * otherwise assime all is well. | |
448 | */ | |
449 | if (0 == dma_get_slave_caps(chan, &caps)) { | |
450 | if (caps.residue_granularity == | |
451 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { | |
452 | dma_release_channel(chan); | |
453 | dev_info(uap->port.dev, | |
454 | "RX DMA disabled - no residue processing\n"); | |
455 | return; | |
456 | } | |
457 | } | |
ead76f32 LW |
458 | dmaengine_slave_config(chan, &rx_conf); |
459 | uap->dmarx.chan = chan; | |
460 | ||
98267d33 | 461 | uap->dmarx.auto_poll_rate = false; |
8f898bfd | 462 | if (plat && plat->dma_rx_poll_enable) { |
cb06ff10 CM |
463 | /* Set poll rate if specified. */ |
464 | if (plat->dma_rx_poll_rate) { | |
465 | uap->dmarx.auto_poll_rate = false; | |
466 | uap->dmarx.poll_rate = plat->dma_rx_poll_rate; | |
467 | } else { | |
468 | /* | |
469 | * 100 ms defaults to poll rate if not | |
470 | * specified. This will be adjusted with | |
471 | * the baud rate at set_termios. | |
472 | */ | |
473 | uap->dmarx.auto_poll_rate = true; | |
474 | uap->dmarx.poll_rate = 100; | |
475 | } | |
476 | /* 3 secs defaults poll_timeout if not specified. */ | |
477 | if (plat->dma_rx_poll_timeout) | |
478 | uap->dmarx.poll_timeout = | |
479 | plat->dma_rx_poll_timeout; | |
480 | else | |
481 | uap->dmarx.poll_timeout = 3000; | |
98267d33 AJ |
482 | } else if (!plat && dev->of_node) { |
483 | uap->dmarx.auto_poll_rate = of_property_read_bool( | |
484 | dev->of_node, "auto-poll"); | |
485 | if (uap->dmarx.auto_poll_rate) { | |
486 | u32 x; | |
487 | ||
488 | if (0 == of_property_read_u32(dev->of_node, | |
489 | "poll-rate-ms", &x)) | |
490 | uap->dmarx.poll_rate = x; | |
491 | else | |
492 | uap->dmarx.poll_rate = 100; | |
493 | if (0 == of_property_read_u32(dev->of_node, | |
494 | "poll-timeout-ms", &x)) | |
495 | uap->dmarx.poll_timeout = x; | |
496 | else | |
497 | uap->dmarx.poll_timeout = 3000; | |
498 | } | |
499 | } | |
ead76f32 LW |
500 | dev_info(uap->port.dev, "DMA channel RX %s\n", |
501 | dma_chan_name(uap->dmarx.chan)); | |
502 | } | |
68b65f73 RK |
503 | } |
504 | ||
68b65f73 RK |
505 | static void pl011_dma_remove(struct uart_amba_port *uap) |
506 | { | |
68b65f73 RK |
507 | if (uap->dmatx.chan) |
508 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
509 | if (uap->dmarx.chan) |
510 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
511 | } |
512 | ||
734745ca | 513 | /* Forward declare these for the refill routine */ |
68b65f73 | 514 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); |
734745ca | 515 | static void pl011_start_tx_pio(struct uart_amba_port *uap); |
68b65f73 RK |
516 | |
517 | /* | |
518 | * The current DMA TX buffer has been sent. | |
519 | * Try to queue up another DMA buffer. | |
520 | */ | |
521 | static void pl011_dma_tx_callback(void *data) | |
522 | { | |
523 | struct uart_amba_port *uap = data; | |
524 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
525 | unsigned long flags; | |
526 | u16 dmacr; | |
527 | ||
528 | spin_lock_irqsave(&uap->port.lock, flags); | |
529 | if (uap->dmatx.queued) | |
530 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
531 | DMA_TO_DEVICE); | |
532 | ||
533 | dmacr = uap->dmacr; | |
534 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
9f25bc51 | 535 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
536 | |
537 | /* | |
538 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
539 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
540 | * | |
541 | * Note: we need to be careful here of a potential race between DMA | |
542 | * and the rest of the driver - if the driver disables TX DMA while | |
543 | * a TX buffer completing, we must update the tx queued status to | |
544 | * get further refills (hence we check dmacr). | |
545 | */ | |
546 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
547 | uart_circ_empty(&uap->port.state->xmit)) { | |
548 | uap->dmatx.queued = false; | |
549 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
550 | return; | |
551 | } | |
552 | ||
734745ca | 553 | if (pl011_dma_tx_refill(uap) <= 0) |
68b65f73 RK |
554 | /* |
555 | * We didn't queue a DMA buffer for some reason, but we | |
556 | * have data pending to be sent. Re-enable the TX IRQ. | |
557 | */ | |
734745ca DM |
558 | pl011_start_tx_pio(uap); |
559 | ||
68b65f73 RK |
560 | spin_unlock_irqrestore(&uap->port.lock, flags); |
561 | } | |
562 | ||
563 | /* | |
564 | * Try to refill the TX DMA buffer. | |
565 | * Locking: called with port lock held and IRQs disabled. | |
566 | * Returns: | |
567 | * 1 if we queued up a TX DMA buffer. | |
568 | * 0 if we didn't want to handle this by DMA | |
569 | * <0 on error | |
570 | */ | |
571 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
572 | { | |
573 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
574 | struct dma_chan *chan = dmatx->chan; | |
575 | struct dma_device *dma_dev = chan->device; | |
576 | struct dma_async_tx_descriptor *desc; | |
577 | struct circ_buf *xmit = &uap->port.state->xmit; | |
578 | unsigned int count; | |
579 | ||
580 | /* | |
581 | * Try to avoid the overhead involved in using DMA if the | |
582 | * transaction fits in the first half of the FIFO, by using | |
583 | * the standard interrupt handling. This ensures that we | |
584 | * issue a uart_write_wakeup() at the appropriate time. | |
585 | */ | |
586 | count = uart_circ_chars_pending(xmit); | |
587 | if (count < (uap->fifosize >> 1)) { | |
588 | uap->dmatx.queued = false; | |
589 | return 0; | |
590 | } | |
591 | ||
592 | /* | |
593 | * Bodge: don't send the last character by DMA, as this | |
594 | * will prevent XON from notifying us to restart DMA. | |
595 | */ | |
596 | count -= 1; | |
597 | ||
598 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
599 | if (count > PL011_DMA_BUFFER_SIZE) | |
600 | count = PL011_DMA_BUFFER_SIZE; | |
601 | ||
602 | if (xmit->tail < xmit->head) | |
603 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
604 | else { | |
605 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
e2a545a6 AJ |
606 | size_t second; |
607 | ||
608 | if (first > count) | |
609 | first = count; | |
610 | second = count - first; | |
68b65f73 RK |
611 | |
612 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
613 | if (second) | |
614 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
615 | } | |
616 | ||
617 | dmatx->sg.length = count; | |
618 | ||
619 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
620 | uap->dmatx.queued = false; | |
621 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
622 | return -EBUSY; | |
623 | } | |
624 | ||
16052827 | 625 | desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, |
68b65f73 RK |
626 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
627 | if (!desc) { | |
628 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
629 | uap->dmatx.queued = false; | |
630 | /* | |
631 | * If DMA cannot be used right now, we complete this | |
632 | * transaction via IRQ and let the TTY layer retry. | |
633 | */ | |
634 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
635 | return -EBUSY; | |
636 | } | |
637 | ||
638 | /* Some data to go along to the callback */ | |
639 | desc->callback = pl011_dma_tx_callback; | |
640 | desc->callback_param = uap; | |
641 | ||
642 | /* All errors should happen at prepare time */ | |
643 | dmaengine_submit(desc); | |
644 | ||
645 | /* Fire the DMA transaction */ | |
646 | dma_dev->device_issue_pending(chan); | |
647 | ||
648 | uap->dmacr |= UART011_TXDMAE; | |
9f25bc51 | 649 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
650 | uap->dmatx.queued = true; |
651 | ||
652 | /* | |
653 | * Now we know that DMA will fire, so advance the ring buffer | |
654 | * with the stuff we just dispatched. | |
655 | */ | |
656 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
657 | uap->port.icount.tx += count; | |
658 | ||
659 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
660 | uart_write_wakeup(&uap->port); | |
661 | ||
662 | return 1; | |
663 | } | |
664 | ||
665 | /* | |
666 | * We received a transmit interrupt without a pending X-char but with | |
667 | * pending characters. | |
668 | * Locking: called with port lock held and IRQs disabled. | |
669 | * Returns: | |
670 | * false if we want to use PIO to transmit | |
671 | * true if we queued a DMA buffer | |
672 | */ | |
673 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
674 | { | |
ead76f32 | 675 | if (!uap->using_tx_dma) |
68b65f73 RK |
676 | return false; |
677 | ||
678 | /* | |
679 | * If we already have a TX buffer queued, but received a | |
680 | * TX interrupt, it will be because we've just sent an X-char. | |
681 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
682 | */ | |
683 | if (uap->dmatx.queued) { | |
684 | uap->dmacr |= UART011_TXDMAE; | |
9f25bc51 | 685 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 | 686 | uap->im &= ~UART011_TXIM; |
9f25bc51 | 687 | pl011_write(uap->im, uap, REG_IMSC); |
68b65f73 RK |
688 | return true; |
689 | } | |
690 | ||
691 | /* | |
692 | * We don't have a TX buffer queued, so try to queue one. | |
25985edc | 693 | * If we successfully queued a buffer, mask the TX IRQ. |
68b65f73 RK |
694 | */ |
695 | if (pl011_dma_tx_refill(uap) > 0) { | |
696 | uap->im &= ~UART011_TXIM; | |
9f25bc51 | 697 | pl011_write(uap->im, uap, REG_IMSC); |
68b65f73 RK |
698 | return true; |
699 | } | |
700 | return false; | |
701 | } | |
702 | ||
703 | /* | |
704 | * Stop the DMA transmit (eg, due to received XOFF). | |
705 | * Locking: called with port lock held and IRQs disabled. | |
706 | */ | |
707 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
708 | { | |
709 | if (uap->dmatx.queued) { | |
710 | uap->dmacr &= ~UART011_TXDMAE; | |
9f25bc51 | 711 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
712 | } |
713 | } | |
714 | ||
715 | /* | |
716 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
717 | * character queued for send, try to get that character out ASAP. | |
718 | * Locking: called with port lock held and IRQs disabled. | |
719 | * Returns: | |
720 | * false if we want the TX IRQ to be enabled | |
721 | * true if we have a buffer queued | |
722 | */ | |
723 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
724 | { | |
725 | u16 dmacr; | |
726 | ||
ead76f32 | 727 | if (!uap->using_tx_dma) |
68b65f73 RK |
728 | return false; |
729 | ||
730 | if (!uap->port.x_char) { | |
731 | /* no X-char, try to push chars out in DMA mode */ | |
732 | bool ret = true; | |
733 | ||
734 | if (!uap->dmatx.queued) { | |
735 | if (pl011_dma_tx_refill(uap) > 0) { | |
736 | uap->im &= ~UART011_TXIM; | |
9f25bc51 | 737 | pl011_write(uap->im, uap, REG_IMSC); |
734745ca | 738 | } else |
68b65f73 | 739 | ret = false; |
68b65f73 RK |
740 | } else if (!(uap->dmacr & UART011_TXDMAE)) { |
741 | uap->dmacr |= UART011_TXDMAE; | |
9f25bc51 | 742 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
743 | } |
744 | return ret; | |
745 | } | |
746 | ||
747 | /* | |
748 | * We have an X-char to send. Disable DMA to prevent it loading | |
749 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
750 | */ | |
751 | dmacr = uap->dmacr; | |
752 | uap->dmacr &= ~UART011_TXDMAE; | |
9f25bc51 | 753 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 | 754 | |
9f25bc51 | 755 | if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { |
68b65f73 RK |
756 | /* |
757 | * No space in the FIFO, so enable the transmit interrupt | |
758 | * so we know when there is space. Note that once we've | |
759 | * loaded the character, we should just re-enable DMA. | |
760 | */ | |
761 | return false; | |
762 | } | |
763 | ||
9f25bc51 | 764 | pl011_write(uap->port.x_char, uap, REG_DR); |
68b65f73 RK |
765 | uap->port.icount.tx++; |
766 | uap->port.x_char = 0; | |
767 | ||
768 | /* Success - restore the DMA state */ | |
769 | uap->dmacr = dmacr; | |
9f25bc51 | 770 | pl011_write(dmacr, uap, REG_DMACR); |
68b65f73 RK |
771 | |
772 | return true; | |
773 | } | |
774 | ||
775 | /* | |
776 | * Flush the transmit buffer. | |
777 | * Locking: called with port lock held and IRQs disabled. | |
778 | */ | |
779 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
b83286bf FE |
780 | __releases(&uap->port.lock) |
781 | __acquires(&uap->port.lock) | |
68b65f73 | 782 | { |
a5820c24 DT |
783 | struct uart_amba_port *uap = |
784 | container_of(port, struct uart_amba_port, port); | |
68b65f73 | 785 | |
ead76f32 | 786 | if (!uap->using_tx_dma) |
68b65f73 RK |
787 | return; |
788 | ||
789 | /* Avoid deadlock with the DMA engine callback */ | |
790 | spin_unlock(&uap->port.lock); | |
791 | dmaengine_terminate_all(uap->dmatx.chan); | |
792 | spin_lock(&uap->port.lock); | |
793 | if (uap->dmatx.queued) { | |
794 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
795 | DMA_TO_DEVICE); | |
796 | uap->dmatx.queued = false; | |
797 | uap->dmacr &= ~UART011_TXDMAE; | |
9f25bc51 | 798 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
799 | } |
800 | } | |
801 | ||
ead76f32 LW |
802 | static void pl011_dma_rx_callback(void *data); |
803 | ||
804 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
805 | { | |
806 | struct dma_chan *rxchan = uap->dmarx.chan; | |
ead76f32 LW |
807 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
808 | struct dma_async_tx_descriptor *desc; | |
809 | struct pl011_sgbuf *sgbuf; | |
810 | ||
811 | if (!rxchan) | |
812 | return -EIO; | |
813 | ||
814 | /* Start the RX DMA job */ | |
815 | sgbuf = uap->dmarx.use_buf_b ? | |
816 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
16052827 | 817 | desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, |
a485df4b | 818 | DMA_DEV_TO_MEM, |
ead76f32 LW |
819 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
820 | /* | |
821 | * If the DMA engine is busy and cannot prepare a | |
822 | * channel, no big deal, the driver will fall back | |
823 | * to interrupt mode as a result of this error code. | |
824 | */ | |
825 | if (!desc) { | |
826 | uap->dmarx.running = false; | |
827 | dmaengine_terminate_all(rxchan); | |
828 | return -EBUSY; | |
829 | } | |
830 | ||
831 | /* Some data to go along to the callback */ | |
832 | desc->callback = pl011_dma_rx_callback; | |
833 | desc->callback_param = uap; | |
834 | dmarx->cookie = dmaengine_submit(desc); | |
835 | dma_async_issue_pending(rxchan); | |
836 | ||
837 | uap->dmacr |= UART011_RXDMAE; | |
9f25bc51 | 838 | pl011_write(uap->dmacr, uap, REG_DMACR); |
ead76f32 LW |
839 | uap->dmarx.running = true; |
840 | ||
841 | uap->im &= ~UART011_RXIM; | |
9f25bc51 | 842 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
843 | |
844 | return 0; | |
845 | } | |
846 | ||
847 | /* | |
848 | * This is called when either the DMA job is complete, or | |
849 | * the FIFO timeout interrupt occurred. This must be called | |
850 | * with the port spinlock uap->port.lock held. | |
851 | */ | |
852 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
853 | u32 pending, bool use_buf_b, | |
854 | bool readfifo) | |
855 | { | |
05c7cd39 | 856 | struct tty_port *port = &uap->port.state->port; |
ead76f32 LW |
857 | struct pl011_sgbuf *sgbuf = use_buf_b ? |
858 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
ead76f32 LW |
859 | int dma_count = 0; |
860 | u32 fifotaken = 0; /* only used for vdbg() */ | |
861 | ||
cb06ff10 CM |
862 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
863 | int dmataken = 0; | |
864 | ||
865 | if (uap->dmarx.poll_rate) { | |
866 | /* The data can be taken by polling */ | |
867 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
868 | /* Recalculate the pending size */ | |
869 | if (pending >= dmataken) | |
870 | pending -= dmataken; | |
871 | } | |
872 | ||
873 | /* Pick the remain data from the DMA */ | |
ead76f32 | 874 | if (pending) { |
ead76f32 LW |
875 | |
876 | /* | |
877 | * First take all chars in the DMA pipe, then look in the FIFO. | |
878 | * Note that tty_insert_flip_buf() tries to take as many chars | |
879 | * as it can. | |
880 | */ | |
cb06ff10 CM |
881 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, |
882 | pending); | |
ead76f32 LW |
883 | |
884 | uap->port.icount.rx += dma_count; | |
885 | if (dma_count < pending) | |
886 | dev_warn(uap->port.dev, | |
887 | "couldn't insert all characters (TTY is full?)\n"); | |
888 | } | |
889 | ||
cb06ff10 CM |
890 | /* Reset the last_residue for Rx DMA poll */ |
891 | if (uap->dmarx.poll_rate) | |
892 | dmarx->last_residue = sgbuf->sg.length; | |
893 | ||
ead76f32 LW |
894 | /* |
895 | * Only continue with trying to read the FIFO if all DMA chars have | |
896 | * been taken first. | |
897 | */ | |
898 | if (dma_count == pending && readfifo) { | |
899 | /* Clear any error flags */ | |
75836339 | 900 | pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | |
9f25bc51 | 901 | UART011_FEIS, uap, REG_ICR); |
ead76f32 LW |
902 | |
903 | /* | |
904 | * If we read all the DMA'd characters, and we had an | |
29772c4e LW |
905 | * incomplete buffer, that could be due to an rx error, or |
906 | * maybe we just timed out. Read any pending chars and check | |
907 | * the error status. | |
908 | * | |
909 | * Error conditions will only occur in the FIFO, these will | |
910 | * trigger an immediate interrupt and stop the DMA job, so we | |
911 | * will always find the error in the FIFO, never in the DMA | |
912 | * buffer. | |
ead76f32 | 913 | */ |
29772c4e | 914 | fifotaken = pl011_fifo_to_tty(uap); |
ead76f32 LW |
915 | } |
916 | ||
917 | spin_unlock(&uap->port.lock); | |
918 | dev_vdbg(uap->port.dev, | |
919 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
920 | dma_count, fifotaken); | |
2e124b4a | 921 | tty_flip_buffer_push(port); |
ead76f32 LW |
922 | spin_lock(&uap->port.lock); |
923 | } | |
924 | ||
925 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
926 | { | |
927 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
928 | struct dma_chan *rxchan = dmarx->chan; | |
929 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? | |
930 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
931 | size_t pending; | |
932 | struct dma_tx_state state; | |
933 | enum dma_status dmastat; | |
934 | ||
935 | /* | |
936 | * Pause the transfer so we can trust the current counter, | |
937 | * do this before we pause the PL011 block, else we may | |
938 | * overflow the FIFO. | |
939 | */ | |
940 | if (dmaengine_pause(rxchan)) | |
941 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
942 | dmastat = rxchan->device->device_tx_status(rxchan, | |
943 | dmarx->cookie, &state); | |
944 | if (dmastat != DMA_PAUSED) | |
945 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
946 | ||
947 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
948 | uap->dmacr &= ~UART011_RXDMAE; | |
9f25bc51 | 949 | pl011_write(uap->dmacr, uap, REG_DMACR); |
ead76f32 LW |
950 | uap->dmarx.running = false; |
951 | ||
952 | pending = sgbuf->sg.length - state.residue; | |
953 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
954 | /* Then we terminate the transfer - we now know our residue */ | |
955 | dmaengine_terminate_all(rxchan); | |
956 | ||
957 | /* | |
958 | * This will take the chars we have so far and insert | |
959 | * into the framework. | |
960 | */ | |
961 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
962 | ||
963 | /* Switch buffer & re-trigger DMA job */ | |
964 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
965 | if (pl011_dma_rx_trigger_dma(uap)) { | |
966 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
967 | "fall back to interrupt mode\n"); | |
968 | uap->im |= UART011_RXIM; | |
9f25bc51 | 969 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
970 | } |
971 | } | |
972 | ||
973 | static void pl011_dma_rx_callback(void *data) | |
974 | { | |
975 | struct uart_amba_port *uap = data; | |
976 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
6dc01aa6 | 977 | struct dma_chan *rxchan = dmarx->chan; |
ead76f32 | 978 | bool lastbuf = dmarx->use_buf_b; |
6dc01aa6 CM |
979 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? |
980 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
981 | size_t pending; | |
982 | struct dma_tx_state state; | |
ead76f32 LW |
983 | int ret; |
984 | ||
985 | /* | |
986 | * This completion interrupt occurs typically when the | |
987 | * RX buffer is totally stuffed but no timeout has yet | |
988 | * occurred. When that happens, we just want the RX | |
989 | * routine to flush out the secondary DMA buffer while | |
990 | * we immediately trigger the next DMA job. | |
991 | */ | |
992 | spin_lock_irq(&uap->port.lock); | |
6dc01aa6 CM |
993 | /* |
994 | * Rx data can be taken by the UART interrupts during | |
995 | * the DMA irq handler. So we check the residue here. | |
996 | */ | |
997 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
998 | pending = sgbuf->sg.length - state.residue; | |
999 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
1000 | /* Then we terminate the transfer - we now know our residue */ | |
1001 | dmaengine_terminate_all(rxchan); | |
1002 | ||
ead76f32 LW |
1003 | uap->dmarx.running = false; |
1004 | dmarx->use_buf_b = !lastbuf; | |
1005 | ret = pl011_dma_rx_trigger_dma(uap); | |
1006 | ||
6dc01aa6 | 1007 | pl011_dma_rx_chars(uap, pending, lastbuf, false); |
ead76f32 LW |
1008 | spin_unlock_irq(&uap->port.lock); |
1009 | /* | |
1010 | * Do this check after we picked the DMA chars so we don't | |
1011 | * get some IRQ immediately from RX. | |
1012 | */ | |
1013 | if (ret) { | |
1014 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
1015 | "fall back to interrupt mode\n"); | |
1016 | uap->im |= UART011_RXIM; | |
9f25bc51 | 1017 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
1018 | } |
1019 | } | |
1020 | ||
1021 | /* | |
1022 | * Stop accepting received characters, when we're shutting down or | |
1023 | * suspending this port. | |
1024 | * Locking: called with port lock held and IRQs disabled. | |
1025 | */ | |
1026 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1027 | { | |
1028 | /* FIXME. Just disable the DMA enable */ | |
1029 | uap->dmacr &= ~UART011_RXDMAE; | |
9f25bc51 | 1030 | pl011_write(uap->dmacr, uap, REG_DMACR); |
ead76f32 | 1031 | } |
68b65f73 | 1032 | |
cb06ff10 CM |
1033 | /* |
1034 | * Timer handler for Rx DMA polling. | |
1035 | * Every polling, It checks the residue in the dma buffer and transfer | |
1036 | * data to the tty. Also, last_residue is updated for the next polling. | |
1037 | */ | |
1038 | static void pl011_dma_rx_poll(unsigned long args) | |
1039 | { | |
1040 | struct uart_amba_port *uap = (struct uart_amba_port *)args; | |
1041 | struct tty_port *port = &uap->port.state->port; | |
1042 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
1043 | struct dma_chan *rxchan = uap->dmarx.chan; | |
1044 | unsigned long flags = 0; | |
1045 | unsigned int dmataken = 0; | |
1046 | unsigned int size = 0; | |
1047 | struct pl011_sgbuf *sgbuf; | |
1048 | int dma_count; | |
1049 | struct dma_tx_state state; | |
1050 | ||
1051 | sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
1052 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
1053 | if (likely(state.residue < dmarx->last_residue)) { | |
1054 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
1055 | size = dmarx->last_residue - state.residue; | |
1056 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, | |
1057 | size); | |
1058 | if (dma_count == size) | |
1059 | dmarx->last_residue = state.residue; | |
1060 | dmarx->last_jiffies = jiffies; | |
1061 | } | |
1062 | tty_flip_buffer_push(port); | |
1063 | ||
1064 | /* | |
1065 | * If no data is received in poll_timeout, the driver will fall back | |
1066 | * to interrupt mode. We will retrigger DMA at the first interrupt. | |
1067 | */ | |
1068 | if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) | |
1069 | > uap->dmarx.poll_timeout) { | |
1070 | ||
1071 | spin_lock_irqsave(&uap->port.lock, flags); | |
1072 | pl011_dma_rx_stop(uap); | |
c25a1ad7 | 1073 | uap->im |= UART011_RXIM; |
9f25bc51 | 1074 | pl011_write(uap->im, uap, REG_IMSC); |
cb06ff10 CM |
1075 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1076 | ||
1077 | uap->dmarx.running = false; | |
1078 | dmaengine_terminate_all(rxchan); | |
1079 | del_timer(&uap->dmarx.timer); | |
1080 | } else { | |
1081 | mod_timer(&uap->dmarx.timer, | |
1082 | jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1083 | } | |
1084 | } | |
1085 | ||
68b65f73 RK |
1086 | static void pl011_dma_startup(struct uart_amba_port *uap) |
1087 | { | |
ead76f32 LW |
1088 | int ret; |
1089 | ||
1c9be310 JRO |
1090 | if (!uap->dma_probed) |
1091 | pl011_dma_probe(uap); | |
1092 | ||
68b65f73 RK |
1093 | if (!uap->dmatx.chan) |
1094 | return; | |
1095 | ||
4c0be45b | 1096 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); |
68b65f73 RK |
1097 | if (!uap->dmatx.buf) { |
1098 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
1099 | uap->port.fifosize = uap->fifosize; | |
1100 | return; | |
1101 | } | |
1102 | ||
1103 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
1104 | ||
1105 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
1106 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
1107 | uap->using_tx_dma = true; |
1108 | ||
1109 | if (!uap->dmarx.chan) | |
1110 | goto skip_rx; | |
1111 | ||
1112 | /* Allocate and map DMA RX buffers */ | |
1113 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1114 | DMA_FROM_DEVICE); | |
1115 | if (ret) { | |
1116 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1117 | "RX buffer A", ret); | |
1118 | goto skip_rx; | |
1119 | } | |
68b65f73 | 1120 | |
ead76f32 LW |
1121 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
1122 | DMA_FROM_DEVICE); | |
1123 | if (ret) { | |
1124 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1125 | "RX buffer B", ret); | |
1126 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1127 | DMA_FROM_DEVICE); | |
1128 | goto skip_rx; | |
1129 | } | |
1130 | ||
1131 | uap->using_rx_dma = true; | |
68b65f73 | 1132 | |
ead76f32 | 1133 | skip_rx: |
68b65f73 RK |
1134 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
1135 | uap->dmacr |= UART011_DMAONERR; | |
9f25bc51 | 1136 | pl011_write(uap->dmacr, uap, REG_DMACR); |
38d62436 RK |
1137 | |
1138 | /* | |
1139 | * ST Micro variants has some specific dma burst threshold | |
1140 | * compensation. Set this to 16 bytes, so burst will only | |
1141 | * be issued above/below 16 bytes. | |
1142 | */ | |
1143 | if (uap->vendor->dma_threshold) | |
75836339 | 1144 | pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, |
9f25bc51 | 1145 | uap, REG_ST_DMAWM); |
ead76f32 LW |
1146 | |
1147 | if (uap->using_rx_dma) { | |
1148 | if (pl011_dma_rx_trigger_dma(uap)) | |
1149 | dev_dbg(uap->port.dev, "could not trigger initial " | |
1150 | "RX DMA job, fall back to interrupt mode\n"); | |
cb06ff10 CM |
1151 | if (uap->dmarx.poll_rate) { |
1152 | init_timer(&(uap->dmarx.timer)); | |
1153 | uap->dmarx.timer.function = pl011_dma_rx_poll; | |
1154 | uap->dmarx.timer.data = (unsigned long)uap; | |
1155 | mod_timer(&uap->dmarx.timer, | |
1156 | jiffies + | |
1157 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1158 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1159 | uap->dmarx.last_jiffies = jiffies; | |
1160 | } | |
ead76f32 | 1161 | } |
68b65f73 RK |
1162 | } |
1163 | ||
1164 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1165 | { | |
ead76f32 | 1166 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
1167 | return; |
1168 | ||
1169 | /* Disable RX and TX DMA */ | |
9f25bc51 | 1170 | while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY) |
2f2fd089 | 1171 | cpu_relax(); |
68b65f73 RK |
1172 | |
1173 | spin_lock_irq(&uap->port.lock); | |
1174 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
9f25bc51 | 1175 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
1176 | spin_unlock_irq(&uap->port.lock); |
1177 | ||
ead76f32 LW |
1178 | if (uap->using_tx_dma) { |
1179 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
1180 | dmaengine_terminate_all(uap->dmatx.chan); | |
1181 | if (uap->dmatx.queued) { | |
1182 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
1183 | DMA_TO_DEVICE); | |
1184 | uap->dmatx.queued = false; | |
1185 | } | |
1186 | ||
1187 | kfree(uap->dmatx.buf); | |
1188 | uap->using_tx_dma = false; | |
68b65f73 RK |
1189 | } |
1190 | ||
ead76f32 LW |
1191 | if (uap->using_rx_dma) { |
1192 | dmaengine_terminate_all(uap->dmarx.chan); | |
1193 | /* Clean up the RX DMA */ | |
1194 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); | |
1195 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); | |
cb06ff10 CM |
1196 | if (uap->dmarx.poll_rate) |
1197 | del_timer_sync(&uap->dmarx.timer); | |
ead76f32 LW |
1198 | uap->using_rx_dma = false; |
1199 | } | |
1200 | } | |
68b65f73 | 1201 | |
ead76f32 LW |
1202 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
1203 | { | |
1204 | return uap->using_rx_dma; | |
68b65f73 RK |
1205 | } |
1206 | ||
ead76f32 LW |
1207 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
1208 | { | |
1209 | return uap->using_rx_dma && uap->dmarx.running; | |
1210 | } | |
1211 | ||
68b65f73 RK |
1212 | #else |
1213 | /* Blank functions if the DMA engine is not available */ | |
1c9be310 | 1214 | static inline void pl011_dma_probe(struct uart_amba_port *uap) |
68b65f73 RK |
1215 | { |
1216 | } | |
1217 | ||
1218 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
1219 | { | |
1220 | } | |
1221 | ||
1222 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
1223 | { | |
1224 | } | |
1225 | ||
1226 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1227 | { | |
1228 | } | |
1229 | ||
1230 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
1231 | { | |
1232 | return false; | |
1233 | } | |
1234 | ||
1235 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
1236 | { | |
1237 | } | |
1238 | ||
1239 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
1240 | { | |
1241 | return false; | |
1242 | } | |
1243 | ||
ead76f32 LW |
1244 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
1245 | { | |
1246 | } | |
1247 | ||
1248 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1249 | { | |
1250 | } | |
1251 | ||
1252 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
1253 | { | |
1254 | return -EIO; | |
1255 | } | |
1256 | ||
1257 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
1258 | { | |
1259 | return false; | |
1260 | } | |
1261 | ||
1262 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
1263 | { | |
1264 | return false; | |
1265 | } | |
1266 | ||
68b65f73 RK |
1267 | #define pl011_dma_flush_buffer NULL |
1268 | #endif | |
1269 | ||
b129a8cc | 1270 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 | 1271 | { |
a5820c24 DT |
1272 | struct uart_amba_port *uap = |
1273 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1274 | |
1275 | uap->im &= ~UART011_TXIM; | |
9f25bc51 | 1276 | pl011_write(uap->im, uap, REG_IMSC); |
68b65f73 | 1277 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
1278 | } |
1279 | ||
1e84d223 | 1280 | static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); |
734745ca DM |
1281 | |
1282 | /* Start TX with programmed I/O only (no DMA) */ | |
1283 | static void pl011_start_tx_pio(struct uart_amba_port *uap) | |
1284 | { | |
1285 | uap->im |= UART011_TXIM; | |
9f25bc51 | 1286 | pl011_write(uap->im, uap, REG_IMSC); |
1e84d223 | 1287 | pl011_tx_chars(uap, false); |
734745ca DM |
1288 | } |
1289 | ||
b129a8cc | 1290 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 | 1291 | { |
a5820c24 DT |
1292 | struct uart_amba_port *uap = |
1293 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1294 | |
734745ca DM |
1295 | if (!pl011_dma_tx_start(uap)) |
1296 | pl011_start_tx_pio(uap); | |
1da177e4 LT |
1297 | } |
1298 | ||
1299 | static void pl011_stop_rx(struct uart_port *port) | |
1300 | { | |
a5820c24 DT |
1301 | struct uart_amba_port *uap = |
1302 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1303 | |
1304 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
1305 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
9f25bc51 | 1306 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
1307 | |
1308 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1309 | } |
1310 | ||
1311 | static void pl011_enable_ms(struct uart_port *port) | |
1312 | { | |
a5820c24 DT |
1313 | struct uart_amba_port *uap = |
1314 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1315 | |
1316 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
9f25bc51 | 1317 | pl011_write(uap->im, uap, REG_IMSC); |
1da177e4 LT |
1318 | } |
1319 | ||
7d12e780 | 1320 | static void pl011_rx_chars(struct uart_amba_port *uap) |
b83286bf FE |
1321 | __releases(&uap->port.lock) |
1322 | __acquires(&uap->port.lock) | |
1da177e4 | 1323 | { |
29772c4e | 1324 | pl011_fifo_to_tty(uap); |
1da177e4 | 1325 | |
2389b272 | 1326 | spin_unlock(&uap->port.lock); |
2e124b4a | 1327 | tty_flip_buffer_push(&uap->port.state->port); |
ead76f32 LW |
1328 | /* |
1329 | * If we were temporarily out of DMA mode for a while, | |
1330 | * attempt to switch back to DMA mode again. | |
1331 | */ | |
1332 | if (pl011_dma_rx_available(uap)) { | |
1333 | if (pl011_dma_rx_trigger_dma(uap)) { | |
1334 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " | |
1335 | "fall back to interrupt mode again\n"); | |
1336 | uap->im |= UART011_RXIM; | |
9f25bc51 | 1337 | pl011_write(uap->im, uap, REG_IMSC); |
cb06ff10 | 1338 | } else { |
89fa28db | 1339 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1340 | /* Start Rx DMA poll */ |
1341 | if (uap->dmarx.poll_rate) { | |
1342 | uap->dmarx.last_jiffies = jiffies; | |
1343 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1344 | mod_timer(&uap->dmarx.timer, | |
1345 | jiffies + | |
1346 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1347 | } | |
89fa28db | 1348 | #endif |
cb06ff10 | 1349 | } |
ead76f32 | 1350 | } |
2389b272 | 1351 | spin_lock(&uap->port.lock); |
1da177e4 LT |
1352 | } |
1353 | ||
1e84d223 DM |
1354 | static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, |
1355 | bool from_irq) | |
734745ca | 1356 | { |
1e84d223 | 1357 | if (unlikely(!from_irq) && |
9f25bc51 | 1358 | pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
1e84d223 DM |
1359 | return false; /* unable to transmit character */ |
1360 | ||
9f25bc51 | 1361 | pl011_write(c, uap, REG_DR); |
734745ca DM |
1362 | uap->port.icount.tx++; |
1363 | ||
1e84d223 | 1364 | return true; |
734745ca DM |
1365 | } |
1366 | ||
1e84d223 | 1367 | static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) |
1da177e4 | 1368 | { |
ebd2c8f6 | 1369 | struct circ_buf *xmit = &uap->port.state->xmit; |
1e84d223 | 1370 | int count = uap->fifosize >> 1; |
734745ca | 1371 | |
1da177e4 | 1372 | if (uap->port.x_char) { |
1e84d223 DM |
1373 | if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) |
1374 | return; | |
1da177e4 | 1375 | uap->port.x_char = 0; |
734745ca | 1376 | --count; |
1da177e4 LT |
1377 | } |
1378 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1379 | pl011_stop_tx(&uap->port); |
1e84d223 | 1380 | return; |
1da177e4 LT |
1381 | } |
1382 | ||
68b65f73 RK |
1383 | /* If we are using DMA mode, try to send some characters. */ |
1384 | if (pl011_dma_tx_irq(uap)) | |
1e84d223 | 1385 | return; |
68b65f73 | 1386 | |
1e84d223 DM |
1387 | do { |
1388 | if (likely(from_irq) && count-- == 0) | |
1da177e4 | 1389 | break; |
1e84d223 DM |
1390 | |
1391 | if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) | |
1392 | break; | |
1393 | ||
1394 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1395 | } while (!uart_circ_empty(xmit)); | |
1da177e4 LT |
1396 | |
1397 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1398 | uart_write_wakeup(&uap->port); | |
1399 | ||
1e84d223 | 1400 | if (uart_circ_empty(xmit)) |
b129a8cc | 1401 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1402 | } |
1403 | ||
1404 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1405 | { | |
1406 | unsigned int status, delta; | |
1407 | ||
9f25bc51 | 1408 | status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 LT |
1409 | |
1410 | delta = status ^ uap->old_status; | |
1411 | uap->old_status = status; | |
1412 | ||
1413 | if (!delta) | |
1414 | return; | |
1415 | ||
1416 | if (delta & UART01x_FR_DCD) | |
1417 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1418 | ||
062a68a5 | 1419 | if (delta & UART01x_FR_DSR) |
1da177e4 LT |
1420 | uap->port.icount.dsr++; |
1421 | ||
062a68a5 GKH |
1422 | if (delta & UART01x_FR_CTS) |
1423 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
1da177e4 | 1424 | |
bdc04e31 | 1425 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1426 | } |
1427 | ||
9c4ef4b0 AP |
1428 | static void check_apply_cts_event_workaround(struct uart_amba_port *uap) |
1429 | { | |
1430 | unsigned int dummy_read; | |
1431 | ||
1432 | if (!uap->vendor->cts_event_workaround) | |
1433 | return; | |
1434 | ||
1435 | /* workaround to make sure that all bits are unlocked.. */ | |
9f25bc51 | 1436 | pl011_write(0x00, uap, REG_ICR); |
9c4ef4b0 AP |
1437 | |
1438 | /* | |
1439 | * WA: introduce 26ns(1 uart clk) delay before W1C; | |
1440 | * single apb access will incur 2 pclk(133.12Mhz) delay, | |
1441 | * so add 2 dummy reads | |
1442 | */ | |
9f25bc51 RK |
1443 | dummy_read = pl011_read(uap, REG_ICR); |
1444 | dummy_read = pl011_read(uap, REG_ICR); | |
9c4ef4b0 AP |
1445 | } |
1446 | ||
7d12e780 | 1447 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1448 | { |
1449 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1450 | unsigned long flags; |
1da177e4 | 1451 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
075167ed | 1452 | u16 imsc; |
1da177e4 LT |
1453 | int handled = 0; |
1454 | ||
963cc981 | 1455 | spin_lock_irqsave(&uap->port.lock, flags); |
9f25bc51 RK |
1456 | imsc = pl011_read(uap, REG_IMSC); |
1457 | status = pl011_read(uap, REG_RIS) & imsc; | |
1da177e4 LT |
1458 | if (status) { |
1459 | do { | |
9c4ef4b0 | 1460 | check_apply_cts_event_workaround(uap); |
f11c9841 | 1461 | |
75836339 RK |
1462 | pl011_write(status & ~(UART011_TXIS|UART011_RTIS| |
1463 | UART011_RXIS), | |
9f25bc51 | 1464 | uap, REG_ICR); |
1da177e4 | 1465 | |
ead76f32 LW |
1466 | if (status & (UART011_RTIS|UART011_RXIS)) { |
1467 | if (pl011_dma_rx_running(uap)) | |
1468 | pl011_dma_rx_irq(uap); | |
1469 | else | |
1470 | pl011_rx_chars(uap); | |
1471 | } | |
1da177e4 LT |
1472 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1473 | UART011_CTSMIS|UART011_RIMIS)) | |
1474 | pl011_modem_status(uap); | |
1e84d223 DM |
1475 | if (status & UART011_TXIS) |
1476 | pl011_tx_chars(uap, true); | |
1da177e4 | 1477 | |
4fd0690b | 1478 | if (pass_counter-- == 0) |
1da177e4 LT |
1479 | break; |
1480 | ||
9f25bc51 | 1481 | status = pl011_read(uap, REG_RIS) & imsc; |
1da177e4 LT |
1482 | } while (status != 0); |
1483 | handled = 1; | |
1484 | } | |
1485 | ||
963cc981 | 1486 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
1487 | |
1488 | return IRQ_RETVAL(handled); | |
1489 | } | |
1490 | ||
e643f87f | 1491 | static unsigned int pl011_tx_empty(struct uart_port *port) |
1da177e4 | 1492 | { |
a5820c24 DT |
1493 | struct uart_amba_port *uap = |
1494 | container_of(port, struct uart_amba_port, port); | |
9f25bc51 | 1495 | unsigned int status = pl011_read(uap, REG_FR); |
062a68a5 | 1496 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; |
1da177e4 LT |
1497 | } |
1498 | ||
e643f87f | 1499 | static unsigned int pl011_get_mctrl(struct uart_port *port) |
1da177e4 | 1500 | { |
a5820c24 DT |
1501 | struct uart_amba_port *uap = |
1502 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1503 | unsigned int result = 0; |
9f25bc51 | 1504 | unsigned int status = pl011_read(uap, REG_FR); |
1da177e4 | 1505 | |
5159f407 | 1506 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
1507 | if (status & uartbit) \ |
1508 | result |= tiocmbit | |
1509 | ||
5159f407 | 1510 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
062a68a5 GKH |
1511 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); |
1512 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
1513 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
5159f407 | 1514 | #undef TIOCMBIT |
1da177e4 LT |
1515 | return result; |
1516 | } | |
1517 | ||
1518 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1519 | { | |
a5820c24 DT |
1520 | struct uart_amba_port *uap = |
1521 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1522 | unsigned int cr; |
1523 | ||
9f25bc51 | 1524 | cr = pl011_read(uap, REG_CR); |
1da177e4 | 1525 | |
5159f407 | 1526 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
1527 | if (mctrl & tiocmbit) \ |
1528 | cr |= uartbit; \ | |
1529 | else \ | |
1530 | cr &= ~uartbit | |
1531 | ||
5159f407 JS |
1532 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
1533 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
1534 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
1535 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
1536 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
1537 | |
1538 | if (uap->autorts) { | |
1539 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
1540 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
1541 | } | |
5159f407 | 1542 | #undef TIOCMBIT |
1da177e4 | 1543 | |
9f25bc51 | 1544 | pl011_write(cr, uap, REG_CR); |
1da177e4 LT |
1545 | } |
1546 | ||
1547 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1548 | { | |
a5820c24 DT |
1549 | struct uart_amba_port *uap = |
1550 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1551 | unsigned long flags; |
1552 | unsigned int lcr_h; | |
1553 | ||
1554 | spin_lock_irqsave(&uap->port.lock, flags); | |
e4df9a80 | 1555 | lcr_h = pl011_read(uap, REG_LCRH_TX); |
1da177e4 LT |
1556 | if (break_state == -1) |
1557 | lcr_h |= UART01x_LCRH_BRK; | |
1558 | else | |
1559 | lcr_h &= ~UART01x_LCRH_BRK; | |
e4df9a80 | 1560 | pl011_write(lcr_h, uap, REG_LCRH_TX); |
1da177e4 LT |
1561 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1562 | } | |
1563 | ||
84b5ae15 | 1564 | #ifdef CONFIG_CONSOLE_POLL |
5c8124a0 AV |
1565 | |
1566 | static void pl011_quiesce_irqs(struct uart_port *port) | |
1567 | { | |
a5820c24 DT |
1568 | struct uart_amba_port *uap = |
1569 | container_of(port, struct uart_amba_port, port); | |
5c8124a0 | 1570 | |
9f25bc51 | 1571 | pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); |
5c8124a0 AV |
1572 | /* |
1573 | * There is no way to clear TXIM as this is "ready to transmit IRQ", so | |
1574 | * we simply mask it. start_tx() will unmask it. | |
1575 | * | |
1576 | * Note we can race with start_tx(), and if the race happens, the | |
1577 | * polling user might get another interrupt just after we clear it. | |
1578 | * But it should be OK and can happen even w/o the race, e.g. | |
1579 | * controller immediately got some new data and raised the IRQ. | |
1580 | * | |
1581 | * And whoever uses polling routines assumes that it manages the device | |
1582 | * (including tx queue), so we're also fine with start_tx()'s caller | |
1583 | * side. | |
1584 | */ | |
9f25bc51 RK |
1585 | pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, |
1586 | REG_IMSC); | |
5c8124a0 AV |
1587 | } |
1588 | ||
e643f87f | 1589 | static int pl011_get_poll_char(struct uart_port *port) |
84b5ae15 | 1590 | { |
a5820c24 DT |
1591 | struct uart_amba_port *uap = |
1592 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 JW |
1593 | unsigned int status; |
1594 | ||
5c8124a0 AV |
1595 | /* |
1596 | * The caller might need IRQs lowered, e.g. if used with KDB NMI | |
1597 | * debugger. | |
1598 | */ | |
1599 | pl011_quiesce_irqs(port); | |
1600 | ||
9f25bc51 | 1601 | status = pl011_read(uap, REG_FR); |
f5316b4a JW |
1602 | if (status & UART01x_FR_RXFE) |
1603 | return NO_POLL_CHAR; | |
84b5ae15 | 1604 | |
9f25bc51 | 1605 | return pl011_read(uap, REG_DR); |
84b5ae15 JW |
1606 | } |
1607 | ||
e643f87f | 1608 | static void pl011_put_poll_char(struct uart_port *port, |
84b5ae15 JW |
1609 | unsigned char ch) |
1610 | { | |
a5820c24 DT |
1611 | struct uart_amba_port *uap = |
1612 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 | 1613 | |
9f25bc51 | 1614 | while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
2f2fd089 | 1615 | cpu_relax(); |
84b5ae15 | 1616 | |
9f25bc51 | 1617 | pl011_write(ch, uap, REG_DR); |
84b5ae15 JW |
1618 | } |
1619 | ||
1620 | #endif /* CONFIG_CONSOLE_POLL */ | |
1621 | ||
b3564c2c | 1622 | static int pl011_hwinit(struct uart_port *port) |
1da177e4 | 1623 | { |
a5820c24 DT |
1624 | struct uart_amba_port *uap = |
1625 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1626 | int retval; |
1627 | ||
78d80c5a | 1628 | /* Optionaly enable pins to be muxed in and configured */ |
2b996fc5 | 1629 | pinctrl_pm_select_default_state(port->dev); |
78d80c5a | 1630 | |
1da177e4 LT |
1631 | /* |
1632 | * Try to enable the clock producer. | |
1633 | */ | |
1c4c4394 | 1634 | retval = clk_prepare_enable(uap->clk); |
1da177e4 | 1635 | if (retval) |
7f6d942a | 1636 | return retval; |
1da177e4 LT |
1637 | |
1638 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1639 | ||
9b96fbac | 1640 | /* Clear pending error and receive interrupts */ |
75836339 RK |
1641 | pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | |
1642 | UART011_FEIS | UART011_RTIS | UART011_RXIS, | |
9f25bc51 | 1643 | uap, REG_ICR); |
9b96fbac | 1644 | |
b3564c2c AV |
1645 | /* |
1646 | * Save interrupts enable mask, and enable RX interrupts in case if | |
1647 | * the interrupt is used for NMI entry. | |
1648 | */ | |
9f25bc51 RK |
1649 | uap->im = pl011_read(uap, REG_IMSC); |
1650 | pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); | |
b3564c2c | 1651 | |
574de559 | 1652 | if (dev_get_platdata(uap->port.dev)) { |
b3564c2c AV |
1653 | struct amba_pl011_data *plat; |
1654 | ||
574de559 | 1655 | plat = dev_get_platdata(uap->port.dev); |
b3564c2c AV |
1656 | if (plat->init) |
1657 | plat->init(); | |
1658 | } | |
1659 | return 0; | |
b3564c2c AV |
1660 | } |
1661 | ||
7fe9a5a9 RK |
1662 | static bool pl011_split_lcrh(const struct uart_amba_port *uap) |
1663 | { | |
e4df9a80 RK |
1664 | return pl011_reg_to_offset(uap, REG_LCRH_RX) != |
1665 | pl011_reg_to_offset(uap, REG_LCRH_TX); | |
7fe9a5a9 RK |
1666 | } |
1667 | ||
b60f2f66 JM |
1668 | static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) |
1669 | { | |
e4df9a80 | 1670 | pl011_write(lcr_h, uap, REG_LCRH_RX); |
7fe9a5a9 | 1671 | if (pl011_split_lcrh(uap)) { |
b60f2f66 JM |
1672 | int i; |
1673 | /* | |
1674 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1675 | * to get this delay write read only register 10 times | |
1676 | */ | |
1677 | for (i = 0; i < 10; ++i) | |
9f25bc51 | 1678 | pl011_write(0xff, uap, REG_MIS); |
e4df9a80 | 1679 | pl011_write(lcr_h, uap, REG_LCRH_TX); |
b60f2f66 JM |
1680 | } |
1681 | } | |
1682 | ||
867b8e8e AP |
1683 | static int pl011_allocate_irq(struct uart_amba_port *uap) |
1684 | { | |
9f25bc51 | 1685 | pl011_write(uap->im, uap, REG_IMSC); |
867b8e8e AP |
1686 | |
1687 | return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
1688 | } | |
1689 | ||
1690 | /* | |
1691 | * Enable interrupts, only timeouts when using DMA | |
1692 | * if initial RX DMA job failed, start in interrupt mode | |
1693 | * as well. | |
1694 | */ | |
1695 | static void pl011_enable_interrupts(struct uart_amba_port *uap) | |
1696 | { | |
1697 | spin_lock_irq(&uap->port.lock); | |
1698 | ||
1699 | /* Clear out any spuriously appearing RX interrupts */ | |
9f25bc51 | 1700 | pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); |
867b8e8e AP |
1701 | uap->im = UART011_RTIM; |
1702 | if (!pl011_dma_rx_running(uap)) | |
1703 | uap->im |= UART011_RXIM; | |
9f25bc51 | 1704 | pl011_write(uap->im, uap, REG_IMSC); |
867b8e8e AP |
1705 | spin_unlock_irq(&uap->port.lock); |
1706 | } | |
1707 | ||
b3564c2c AV |
1708 | static int pl011_startup(struct uart_port *port) |
1709 | { | |
a5820c24 DT |
1710 | struct uart_amba_port *uap = |
1711 | container_of(port, struct uart_amba_port, port); | |
734745ca | 1712 | unsigned int cr; |
b3564c2c AV |
1713 | int retval; |
1714 | ||
1715 | retval = pl011_hwinit(port); | |
1716 | if (retval) | |
1717 | goto clk_dis; | |
1718 | ||
867b8e8e | 1719 | retval = pl011_allocate_irq(uap); |
1da177e4 LT |
1720 | if (retval) |
1721 | goto clk_dis; | |
1722 | ||
9f25bc51 | 1723 | pl011_write(uap->vendor->ifls, uap, REG_IFLS); |
1da177e4 | 1724 | |
734745ca | 1725 | spin_lock_irq(&uap->port.lock); |
570d2910 | 1726 | |
d8d8ffa4 SKS |
1727 | /* restore RTS and DTR */ |
1728 | cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); | |
1729 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
9f25bc51 | 1730 | pl011_write(cr, uap, REG_CR); |
1da177e4 | 1731 | |
fe433907 JM |
1732 | spin_unlock_irq(&uap->port.lock); |
1733 | ||
1da177e4 LT |
1734 | /* |
1735 | * initialise the old status of the modem signals | |
1736 | */ | |
9f25bc51 | 1737 | uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 | 1738 | |
68b65f73 RK |
1739 | /* Startup DMA */ |
1740 | pl011_dma_startup(uap); | |
1741 | ||
867b8e8e | 1742 | pl011_enable_interrupts(uap); |
1da177e4 LT |
1743 | |
1744 | return 0; | |
1745 | ||
1746 | clk_dis: | |
1c4c4394 | 1747 | clk_disable_unprepare(uap->clk); |
1da177e4 LT |
1748 | return retval; |
1749 | } | |
1750 | ||
0dd1e247 AP |
1751 | static int sbsa_uart_startup(struct uart_port *port) |
1752 | { | |
1753 | struct uart_amba_port *uap = | |
1754 | container_of(port, struct uart_amba_port, port); | |
1755 | int retval; | |
1756 | ||
1757 | retval = pl011_hwinit(port); | |
1758 | if (retval) | |
1759 | return retval; | |
1760 | ||
1761 | retval = pl011_allocate_irq(uap); | |
1762 | if (retval) | |
1763 | return retval; | |
1764 | ||
1765 | /* The SBSA UART does not support any modem status lines. */ | |
1766 | uap->old_status = 0; | |
1767 | ||
1768 | pl011_enable_interrupts(uap); | |
1769 | ||
1770 | return 0; | |
1771 | } | |
1772 | ||
ec489aa8 LW |
1773 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
1774 | unsigned int lcrh) | |
1775 | { | |
f11c9841 | 1776 | unsigned long val; |
ec489aa8 | 1777 | |
b2a4e24c | 1778 | val = pl011_read(uap, lcrh); |
f11c9841 | 1779 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); |
b2a4e24c | 1780 | pl011_write(val, uap, lcrh); |
ec489aa8 LW |
1781 | } |
1782 | ||
95166a3f AP |
1783 | /* |
1784 | * disable the port. It should not disable RTS and DTR. | |
1785 | * Also RTS and DTR state should be preserved to restore | |
1786 | * it during startup(). | |
1787 | */ | |
1788 | static void pl011_disable_uart(struct uart_amba_port *uap) | |
1da177e4 | 1789 | { |
d8d8ffa4 | 1790 | unsigned int cr; |
1da177e4 | 1791 | |
3b43816f | 1792 | uap->autorts = false; |
fe433907 | 1793 | spin_lock_irq(&uap->port.lock); |
9f25bc51 | 1794 | cr = pl011_read(uap, REG_CR); |
d8d8ffa4 SKS |
1795 | uap->old_cr = cr; |
1796 | cr &= UART011_CR_RTS | UART011_CR_DTR; | |
1797 | cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
9f25bc51 | 1798 | pl011_write(cr, uap, REG_CR); |
fe433907 | 1799 | spin_unlock_irq(&uap->port.lock); |
1da177e4 LT |
1800 | |
1801 | /* | |
1802 | * disable break condition and fifos | |
1803 | */ | |
e4df9a80 | 1804 | pl011_shutdown_channel(uap, REG_LCRH_RX); |
7fe9a5a9 | 1805 | if (pl011_split_lcrh(uap)) |
e4df9a80 | 1806 | pl011_shutdown_channel(uap, REG_LCRH_TX); |
95166a3f AP |
1807 | } |
1808 | ||
1809 | static void pl011_disable_interrupts(struct uart_amba_port *uap) | |
1810 | { | |
1811 | spin_lock_irq(&uap->port.lock); | |
1812 | ||
1813 | /* mask all interrupts and clear all pending ones */ | |
1814 | uap->im = 0; | |
9f25bc51 RK |
1815 | pl011_write(uap->im, uap, REG_IMSC); |
1816 | pl011_write(0xffff, uap, REG_ICR); | |
95166a3f AP |
1817 | |
1818 | spin_unlock_irq(&uap->port.lock); | |
1819 | } | |
1820 | ||
1821 | static void pl011_shutdown(struct uart_port *port) | |
1822 | { | |
1823 | struct uart_amba_port *uap = | |
1824 | container_of(port, struct uart_amba_port, port); | |
1825 | ||
1826 | pl011_disable_interrupts(uap); | |
1827 | ||
1828 | pl011_dma_shutdown(uap); | |
1829 | ||
1830 | free_irq(uap->port.irq, uap); | |
1831 | ||
1832 | pl011_disable_uart(uap); | |
1da177e4 LT |
1833 | |
1834 | /* | |
1835 | * Shut down the clock producer | |
1836 | */ | |
1c4c4394 | 1837 | clk_disable_unprepare(uap->clk); |
78d80c5a | 1838 | /* Optionally let pins go into sleep states */ |
2b996fc5 | 1839 | pinctrl_pm_select_sleep_state(port->dev); |
c16d51a3 | 1840 | |
574de559 | 1841 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
1842 | struct amba_pl011_data *plat; |
1843 | ||
574de559 | 1844 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
1845 | if (plat->exit) |
1846 | plat->exit(); | |
1847 | } | |
1848 | ||
36f339d1 PH |
1849 | if (uap->port.ops->flush_buffer) |
1850 | uap->port.ops->flush_buffer(port); | |
1da177e4 LT |
1851 | } |
1852 | ||
0dd1e247 AP |
1853 | static void sbsa_uart_shutdown(struct uart_port *port) |
1854 | { | |
1855 | struct uart_amba_port *uap = | |
1856 | container_of(port, struct uart_amba_port, port); | |
1857 | ||
1858 | pl011_disable_interrupts(uap); | |
1859 | ||
1860 | free_irq(uap->port.irq, uap); | |
1861 | ||
1862 | if (uap->port.ops->flush_buffer) | |
1863 | uap->port.ops->flush_buffer(port); | |
1864 | } | |
1865 | ||
ef5a9358 AP |
1866 | static void |
1867 | pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) | |
1868 | { | |
1869 | port->read_status_mask = UART011_DR_OE | 255; | |
1870 | if (termios->c_iflag & INPCK) | |
1871 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; | |
1872 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) | |
1873 | port->read_status_mask |= UART011_DR_BE; | |
1874 | ||
1875 | /* | |
1876 | * Characters to ignore | |
1877 | */ | |
1878 | port->ignore_status_mask = 0; | |
1879 | if (termios->c_iflag & IGNPAR) | |
1880 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; | |
1881 | if (termios->c_iflag & IGNBRK) { | |
1882 | port->ignore_status_mask |= UART011_DR_BE; | |
1883 | /* | |
1884 | * If we're ignoring parity and break indicators, | |
1885 | * ignore overruns too (for real raw support). | |
1886 | */ | |
1887 | if (termios->c_iflag & IGNPAR) | |
1888 | port->ignore_status_mask |= UART011_DR_OE; | |
1889 | } | |
1890 | ||
1891 | /* | |
1892 | * Ignore all characters if CREAD is not set. | |
1893 | */ | |
1894 | if ((termios->c_cflag & CREAD) == 0) | |
1895 | port->ignore_status_mask |= UART_DUMMY_DR_RX; | |
1896 | } | |
1897 | ||
1da177e4 | 1898 | static void |
606d099c AC |
1899 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1900 | struct ktermios *old) | |
1da177e4 | 1901 | { |
a5820c24 DT |
1902 | struct uart_amba_port *uap = |
1903 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1904 | unsigned int lcr_h, old_cr; |
1905 | unsigned long flags; | |
c19f12b5 RK |
1906 | unsigned int baud, quot, clkdiv; |
1907 | ||
1908 | if (uap->vendor->oversampling) | |
1909 | clkdiv = 8; | |
1910 | else | |
1911 | clkdiv = 16; | |
1da177e4 LT |
1912 | |
1913 | /* | |
1914 | * Ask the core to calculate the divisor for us. | |
1915 | */ | |
ac3e3fb4 | 1916 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1917 | port->uartclk / clkdiv); |
89fa28db | 1918 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1919 | /* |
1920 | * Adjust RX DMA polling rate with baud rate if not specified. | |
1921 | */ | |
1922 | if (uap->dmarx.auto_poll_rate) | |
1923 | uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); | |
89fa28db | 1924 | #endif |
ac3e3fb4 LW |
1925 | |
1926 | if (baud > port->uartclk/16) | |
1927 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1928 | else | |
1929 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1930 | |
1931 | switch (termios->c_cflag & CSIZE) { | |
1932 | case CS5: | |
1933 | lcr_h = UART01x_LCRH_WLEN_5; | |
1934 | break; | |
1935 | case CS6: | |
1936 | lcr_h = UART01x_LCRH_WLEN_6; | |
1937 | break; | |
1938 | case CS7: | |
1939 | lcr_h = UART01x_LCRH_WLEN_7; | |
1940 | break; | |
1941 | default: // CS8 | |
1942 | lcr_h = UART01x_LCRH_WLEN_8; | |
1943 | break; | |
1944 | } | |
1945 | if (termios->c_cflag & CSTOPB) | |
1946 | lcr_h |= UART01x_LCRH_STP2; | |
1947 | if (termios->c_cflag & PARENB) { | |
1948 | lcr_h |= UART01x_LCRH_PEN; | |
1949 | if (!(termios->c_cflag & PARODD)) | |
1950 | lcr_h |= UART01x_LCRH_EPS; | |
bb70002c ES |
1951 | if (termios->c_cflag & CMSPAR) |
1952 | lcr_h |= UART011_LCRH_SPS; | |
1da177e4 | 1953 | } |
ffca2b11 | 1954 | if (uap->fifosize > 1) |
1da177e4 LT |
1955 | lcr_h |= UART01x_LCRH_FEN; |
1956 | ||
1957 | spin_lock_irqsave(&port->lock, flags); | |
1958 | ||
1959 | /* | |
1960 | * Update the per-port timeout. | |
1961 | */ | |
1962 | uart_update_timeout(port, termios->c_cflag, baud); | |
1963 | ||
ef5a9358 | 1964 | pl011_setup_status_masks(port, termios); |
1da177e4 LT |
1965 | |
1966 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1967 | pl011_enable_ms(port); | |
1968 | ||
1969 | /* first, disable everything */ | |
9f25bc51 RK |
1970 | old_cr = pl011_read(uap, REG_CR); |
1971 | pl011_write(0, uap, REG_CR); | |
1da177e4 | 1972 | |
3b43816f RV |
1973 | if (termios->c_cflag & CRTSCTS) { |
1974 | if (old_cr & UART011_CR_RTS) | |
1975 | old_cr |= UART011_CR_RTSEN; | |
1976 | ||
1977 | old_cr |= UART011_CR_CTSEN; | |
1978 | uap->autorts = true; | |
1979 | } else { | |
1980 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1981 | uap->autorts = false; | |
1982 | } | |
1983 | ||
c19f12b5 RK |
1984 | if (uap->vendor->oversampling) { |
1985 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1986 | old_cr |= ST_UART011_CR_OVSFACT; |
1987 | else | |
1988 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1989 | } | |
1990 | ||
c5dd553b LW |
1991 | /* |
1992 | * Workaround for the ST Micro oversampling variants to | |
1993 | * increase the bitrate slightly, by lowering the divisor, | |
1994 | * to avoid delayed sampling of start bit at high speeds, | |
1995 | * else we see data corruption. | |
1996 | */ | |
1997 | if (uap->vendor->oversampling) { | |
1998 | if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) | |
1999 | quot -= 1; | |
2000 | else if ((baud > 3250000) && (quot > 2)) | |
2001 | quot -= 2; | |
2002 | } | |
1da177e4 | 2003 | /* Set baud rate */ |
9f25bc51 RK |
2004 | pl011_write(quot & 0x3f, uap, REG_FBRD); |
2005 | pl011_write(quot >> 6, uap, REG_IBRD); | |
1da177e4 LT |
2006 | |
2007 | /* | |
2008 | * ----------v----------v----------v----------v----- | |
e4df9a80 | 2009 | * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER |
9f25bc51 | 2010 | * REG_FBRD & REG_IBRD. |
1da177e4 LT |
2011 | * ----------^----------^----------^----------^----- |
2012 | */ | |
b60f2f66 | 2013 | pl011_write_lcr_h(uap, lcr_h); |
9f25bc51 | 2014 | pl011_write(old_cr, uap, REG_CR); |
1da177e4 LT |
2015 | |
2016 | spin_unlock_irqrestore(&port->lock, flags); | |
2017 | } | |
2018 | ||
0dd1e247 AP |
2019 | static void |
2020 | sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, | |
2021 | struct ktermios *old) | |
2022 | { | |
2023 | struct uart_amba_port *uap = | |
2024 | container_of(port, struct uart_amba_port, port); | |
2025 | unsigned long flags; | |
2026 | ||
2027 | tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); | |
2028 | ||
2029 | /* The SBSA UART only supports 8n1 without hardware flow control. */ | |
2030 | termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); | |
2031 | termios->c_cflag &= ~(CMSPAR | CRTSCTS); | |
2032 | termios->c_cflag |= CS8 | CLOCAL; | |
2033 | ||
2034 | spin_lock_irqsave(&port->lock, flags); | |
2035 | uart_update_timeout(port, CS8, uap->fixed_baud); | |
2036 | pl011_setup_status_masks(port, termios); | |
2037 | spin_unlock_irqrestore(&port->lock, flags); | |
2038 | } | |
2039 | ||
1da177e4 LT |
2040 | static const char *pl011_type(struct uart_port *port) |
2041 | { | |
a5820c24 DT |
2042 | struct uart_amba_port *uap = |
2043 | container_of(port, struct uart_amba_port, port); | |
e8a7ba86 | 2044 | return uap->port.type == PORT_AMBA ? uap->type : NULL; |
1da177e4 LT |
2045 | } |
2046 | ||
2047 | /* | |
2048 | * Release the memory region(s) being used by 'port' | |
2049 | */ | |
e643f87f | 2050 | static void pl011_release_port(struct uart_port *port) |
1da177e4 LT |
2051 | { |
2052 | release_mem_region(port->mapbase, SZ_4K); | |
2053 | } | |
2054 | ||
2055 | /* | |
2056 | * Request the memory region(s) being used by 'port' | |
2057 | */ | |
e643f87f | 2058 | static int pl011_request_port(struct uart_port *port) |
1da177e4 LT |
2059 | { |
2060 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
2061 | != NULL ? 0 : -EBUSY; | |
2062 | } | |
2063 | ||
2064 | /* | |
2065 | * Configure/autoconfigure the port. | |
2066 | */ | |
e643f87f | 2067 | static void pl011_config_port(struct uart_port *port, int flags) |
1da177e4 LT |
2068 | { |
2069 | if (flags & UART_CONFIG_TYPE) { | |
2070 | port->type = PORT_AMBA; | |
e643f87f | 2071 | pl011_request_port(port); |
1da177e4 LT |
2072 | } |
2073 | } | |
2074 | ||
2075 | /* | |
2076 | * verify the new serial_struct (for TIOCSSERIAL). | |
2077 | */ | |
e643f87f | 2078 | static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) |
1da177e4 LT |
2079 | { |
2080 | int ret = 0; | |
2081 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
2082 | ret = -EINVAL; | |
a62c4133 | 2083 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
2084 | ret = -EINVAL; |
2085 | if (ser->baud_base < 9600) | |
2086 | ret = -EINVAL; | |
2087 | return ret; | |
2088 | } | |
2089 | ||
2090 | static struct uart_ops amba_pl011_pops = { | |
e643f87f | 2091 | .tx_empty = pl011_tx_empty, |
1da177e4 | 2092 | .set_mctrl = pl011_set_mctrl, |
e643f87f | 2093 | .get_mctrl = pl011_get_mctrl, |
1da177e4 LT |
2094 | .stop_tx = pl011_stop_tx, |
2095 | .start_tx = pl011_start_tx, | |
2096 | .stop_rx = pl011_stop_rx, | |
2097 | .enable_ms = pl011_enable_ms, | |
2098 | .break_ctl = pl011_break_ctl, | |
2099 | .startup = pl011_startup, | |
2100 | .shutdown = pl011_shutdown, | |
68b65f73 | 2101 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
2102 | .set_termios = pl011_set_termios, |
2103 | .type = pl011_type, | |
e643f87f LW |
2104 | .release_port = pl011_release_port, |
2105 | .request_port = pl011_request_port, | |
2106 | .config_port = pl011_config_port, | |
2107 | .verify_port = pl011_verify_port, | |
84b5ae15 | 2108 | #ifdef CONFIG_CONSOLE_POLL |
b3564c2c | 2109 | .poll_init = pl011_hwinit, |
e643f87f LW |
2110 | .poll_get_char = pl011_get_poll_char, |
2111 | .poll_put_char = pl011_put_poll_char, | |
84b5ae15 | 2112 | #endif |
1da177e4 LT |
2113 | }; |
2114 | ||
0dd1e247 AP |
2115 | static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
2116 | { | |
2117 | } | |
2118 | ||
2119 | static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) | |
2120 | { | |
2121 | return 0; | |
2122 | } | |
2123 | ||
2124 | static const struct uart_ops sbsa_uart_pops = { | |
2125 | .tx_empty = pl011_tx_empty, | |
2126 | .set_mctrl = sbsa_uart_set_mctrl, | |
2127 | .get_mctrl = sbsa_uart_get_mctrl, | |
2128 | .stop_tx = pl011_stop_tx, | |
2129 | .start_tx = pl011_start_tx, | |
2130 | .stop_rx = pl011_stop_rx, | |
2131 | .startup = sbsa_uart_startup, | |
2132 | .shutdown = sbsa_uart_shutdown, | |
2133 | .set_termios = sbsa_uart_set_termios, | |
2134 | .type = pl011_type, | |
2135 | .release_port = pl011_release_port, | |
2136 | .request_port = pl011_request_port, | |
2137 | .config_port = pl011_config_port, | |
2138 | .verify_port = pl011_verify_port, | |
2139 | #ifdef CONFIG_CONSOLE_POLL | |
2140 | .poll_init = pl011_hwinit, | |
2141 | .poll_get_char = pl011_get_poll_char, | |
2142 | .poll_put_char = pl011_put_poll_char, | |
2143 | #endif | |
2144 | }; | |
2145 | ||
1da177e4 LT |
2146 | static struct uart_amba_port *amba_ports[UART_NR]; |
2147 | ||
2148 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
2149 | ||
d358788f | 2150 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 2151 | { |
a5820c24 DT |
2152 | struct uart_amba_port *uap = |
2153 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 2154 | |
9f25bc51 | 2155 | while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
2f2fd089 | 2156 | cpu_relax(); |
9f25bc51 | 2157 | pl011_write(ch, uap, REG_DR); |
1da177e4 LT |
2158 | } |
2159 | ||
2160 | static void | |
2161 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
2162 | { | |
2163 | struct uart_amba_port *uap = amba_ports[co->index]; | |
2f2fd089 | 2164 | unsigned int old_cr = 0, new_cr; |
ef605fdb RV |
2165 | unsigned long flags; |
2166 | int locked = 1; | |
1da177e4 LT |
2167 | |
2168 | clk_enable(uap->clk); | |
2169 | ||
ef605fdb RV |
2170 | local_irq_save(flags); |
2171 | if (uap->port.sysrq) | |
2172 | locked = 0; | |
2173 | else if (oops_in_progress) | |
2174 | locked = spin_trylock(&uap->port.lock); | |
2175 | else | |
2176 | spin_lock(&uap->port.lock); | |
2177 | ||
1da177e4 LT |
2178 | /* |
2179 | * First save the CR then disable the interrupts | |
2180 | */ | |
71eec483 | 2181 | if (!uap->vendor->always_enabled) { |
9f25bc51 | 2182 | old_cr = pl011_read(uap, REG_CR); |
71eec483 AP |
2183 | new_cr = old_cr & ~UART011_CR_CTSEN; |
2184 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
9f25bc51 | 2185 | pl011_write(new_cr, uap, REG_CR); |
71eec483 | 2186 | } |
1da177e4 | 2187 | |
d358788f | 2188 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
2189 | |
2190 | /* | |
2191 | * Finally, wait for transmitter to become empty | |
2192 | * and restore the TCR | |
2193 | */ | |
2f2fd089 TT |
2194 | while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY) |
2195 | cpu_relax(); | |
71eec483 | 2196 | if (!uap->vendor->always_enabled) |
9f25bc51 | 2197 | pl011_write(old_cr, uap, REG_CR); |
1da177e4 | 2198 | |
ef605fdb RV |
2199 | if (locked) |
2200 | spin_unlock(&uap->port.lock); | |
2201 | local_irq_restore(flags); | |
2202 | ||
1da177e4 LT |
2203 | clk_disable(uap->clk); |
2204 | } | |
2205 | ||
2206 | static void __init | |
2207 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
2208 | int *parity, int *bits) | |
2209 | { | |
9f25bc51 | 2210 | if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { |
1da177e4 LT |
2211 | unsigned int lcr_h, ibrd, fbrd; |
2212 | ||
e4df9a80 | 2213 | lcr_h = pl011_read(uap, REG_LCRH_TX); |
1da177e4 LT |
2214 | |
2215 | *parity = 'n'; | |
2216 | if (lcr_h & UART01x_LCRH_PEN) { | |
2217 | if (lcr_h & UART01x_LCRH_EPS) | |
2218 | *parity = 'e'; | |
2219 | else | |
2220 | *parity = 'o'; | |
2221 | } | |
2222 | ||
2223 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
2224 | *bits = 7; | |
2225 | else | |
2226 | *bits = 8; | |
2227 | ||
9f25bc51 RK |
2228 | ibrd = pl011_read(uap, REG_IBRD); |
2229 | fbrd = pl011_read(uap, REG_FBRD); | |
1da177e4 LT |
2230 | |
2231 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 2232 | |
c19f12b5 | 2233 | if (uap->vendor->oversampling) { |
9f25bc51 | 2234 | if (pl011_read(uap, REG_CR) |
ac3e3fb4 LW |
2235 | & ST_UART011_CR_OVSFACT) |
2236 | *baud *= 2; | |
2237 | } | |
1da177e4 LT |
2238 | } |
2239 | } | |
2240 | ||
2241 | static int __init pl011_console_setup(struct console *co, char *options) | |
2242 | { | |
2243 | struct uart_amba_port *uap; | |
2244 | int baud = 38400; | |
2245 | int bits = 8; | |
2246 | int parity = 'n'; | |
2247 | int flow = 'n'; | |
4b4851c6 | 2248 | int ret; |
1da177e4 LT |
2249 | |
2250 | /* | |
2251 | * Check whether an invalid uart number has been specified, and | |
2252 | * if so, search for the first available port that does have | |
2253 | * console support. | |
2254 | */ | |
2255 | if (co->index >= UART_NR) | |
2256 | co->index = 0; | |
2257 | uap = amba_ports[co->index]; | |
d28122a5 RK |
2258 | if (!uap) |
2259 | return -ENODEV; | |
1da177e4 | 2260 | |
78d80c5a | 2261 | /* Allow pins to be muxed in and configured */ |
2b996fc5 | 2262 | pinctrl_pm_select_default_state(uap->port.dev); |
78d80c5a | 2263 | |
4b4851c6 RK |
2264 | ret = clk_prepare(uap->clk); |
2265 | if (ret) | |
2266 | return ret; | |
2267 | ||
574de559 | 2268 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
2269 | struct amba_pl011_data *plat; |
2270 | ||
574de559 | 2271 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
2272 | if (plat->init) |
2273 | plat->init(); | |
2274 | } | |
2275 | ||
1da177e4 LT |
2276 | uap->port.uartclk = clk_get_rate(uap->clk); |
2277 | ||
cefc2d1d AP |
2278 | if (uap->vendor->fixed_options) { |
2279 | baud = uap->fixed_baud; | |
2280 | } else { | |
2281 | if (options) | |
2282 | uart_parse_options(options, | |
2283 | &baud, &parity, &bits, &flow); | |
2284 | else | |
2285 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
2286 | } | |
1da177e4 LT |
2287 | |
2288 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
2289 | } | |
2290 | ||
2d93486c | 2291 | static struct uart_driver amba_reg; |
1da177e4 LT |
2292 | static struct console amba_console = { |
2293 | .name = "ttyAMA", | |
2294 | .write = pl011_console_write, | |
2295 | .device = uart_console_device, | |
2296 | .setup = pl011_console_setup, | |
2297 | .flags = CON_PRINTBUFFER, | |
2298 | .index = -1, | |
2299 | .data = &amba_reg, | |
2300 | }; | |
2301 | ||
2302 | #define AMBA_CONSOLE (&amba_console) | |
0d3c673e RH |
2303 | |
2304 | static void pl011_putc(struct uart_port *port, int c) | |
2305 | { | |
cdf091ca | 2306 | while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) |
2f2fd089 | 2307 | cpu_relax(); |
3b78fae7 TT |
2308 | if (port->iotype == UPIO_MEM32) |
2309 | writel(c, port->membase + UART01x_DR); | |
2310 | else | |
2311 | writeb(c, port->membase + UART01x_DR); | |
cdf091ca | 2312 | while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) |
2f2fd089 | 2313 | cpu_relax(); |
0d3c673e RH |
2314 | } |
2315 | ||
2316 | static void pl011_early_write(struct console *con, const char *s, unsigned n) | |
2317 | { | |
2318 | struct earlycon_device *dev = con->data; | |
2319 | ||
2320 | uart_console_write(&dev->port, s, n, pl011_putc); | |
2321 | } | |
2322 | ||
2323 | static int __init pl011_early_console_setup(struct earlycon_device *device, | |
2324 | const char *opt) | |
2325 | { | |
2326 | if (!device->port.membase) | |
2327 | return -ENODEV; | |
2328 | ||
2329 | device->con->write = pl011_early_write; | |
2330 | return 0; | |
2331 | } | |
45e0f0f5 | 2332 | OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); |
0d3c673e | 2333 | |
1da177e4 LT |
2334 | #else |
2335 | #define AMBA_CONSOLE NULL | |
2336 | #endif | |
2337 | ||
2338 | static struct uart_driver amba_reg = { | |
2339 | .owner = THIS_MODULE, | |
2340 | .driver_name = "ttyAMA", | |
2341 | .dev_name = "ttyAMA", | |
2342 | .major = SERIAL_AMBA_MAJOR, | |
2343 | .minor = SERIAL_AMBA_MINOR, | |
2344 | .nr = UART_NR, | |
2345 | .cons = AMBA_CONSOLE, | |
2346 | }; | |
2347 | ||
32614aad ML |
2348 | static int pl011_probe_dt_alias(int index, struct device *dev) |
2349 | { | |
2350 | struct device_node *np; | |
2351 | static bool seen_dev_with_alias = false; | |
2352 | static bool seen_dev_without_alias = false; | |
2353 | int ret = index; | |
2354 | ||
2355 | if (!IS_ENABLED(CONFIG_OF)) | |
2356 | return ret; | |
2357 | ||
2358 | np = dev->of_node; | |
2359 | if (!np) | |
2360 | return ret; | |
2361 | ||
2362 | ret = of_alias_get_id(np, "serial"); | |
287980e4 | 2363 | if (ret < 0) { |
32614aad ML |
2364 | seen_dev_without_alias = true; |
2365 | ret = index; | |
2366 | } else { | |
2367 | seen_dev_with_alias = true; | |
2368 | if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { | |
2369 | dev_warn(dev, "requested serial port %d not available.\n", ret); | |
2370 | ret = index; | |
2371 | } | |
2372 | } | |
2373 | ||
2374 | if (seen_dev_with_alias && seen_dev_without_alias) | |
2375 | dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); | |
2376 | ||
2377 | return ret; | |
2378 | } | |
2379 | ||
49bb3c86 AP |
2380 | /* unregisters the driver also if no more ports are left */ |
2381 | static void pl011_unregister_port(struct uart_amba_port *uap) | |
2382 | { | |
2383 | int i; | |
2384 | bool busy = false; | |
2385 | ||
2386 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { | |
2387 | if (amba_ports[i] == uap) | |
2388 | amba_ports[i] = NULL; | |
2389 | else if (amba_ports[i]) | |
2390 | busy = true; | |
2391 | } | |
2392 | pl011_dma_remove(uap); | |
2393 | if (!busy) | |
2394 | uart_unregister_driver(&amba_reg); | |
2395 | } | |
2396 | ||
3873e2d7 | 2397 | static int pl011_find_free_port(void) |
1da177e4 | 2398 | { |
3873e2d7 | 2399 | int i; |
1da177e4 LT |
2400 | |
2401 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
2402 | if (amba_ports[i] == NULL) | |
3873e2d7 | 2403 | return i; |
1da177e4 | 2404 | |
3873e2d7 AP |
2405 | return -EBUSY; |
2406 | } | |
1da177e4 | 2407 | |
3873e2d7 AP |
2408 | static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, |
2409 | struct resource *mmiobase, int index) | |
2410 | { | |
2411 | void __iomem *base; | |
32614aad | 2412 | |
3873e2d7 | 2413 | base = devm_ioremap_resource(dev, mmiobase); |
97a60eac KK |
2414 | if (IS_ERR(base)) |
2415 | return PTR_ERR(base); | |
1da177e4 | 2416 | |
3873e2d7 | 2417 | index = pl011_probe_dt_alias(index, dev); |
1da177e4 | 2418 | |
d8d8ffa4 | 2419 | uap->old_cr = 0; |
3873e2d7 AP |
2420 | uap->port.dev = dev; |
2421 | uap->port.mapbase = mmiobase->start; | |
1da177e4 | 2422 | uap->port.membase = base; |
ffca2b11 | 2423 | uap->port.fifosize = uap->fifosize; |
1da177e4 | 2424 | uap->port.flags = UPF_BOOT_AUTOCONF; |
3873e2d7 | 2425 | uap->port.line = index; |
1da177e4 | 2426 | |
3873e2d7 | 2427 | amba_ports[index] = uap; |
c3d8b76f | 2428 | |
3873e2d7 AP |
2429 | return 0; |
2430 | } | |
e8a7ba86 | 2431 | |
3873e2d7 AP |
2432 | static int pl011_register_port(struct uart_amba_port *uap) |
2433 | { | |
2434 | int ret; | |
1da177e4 | 2435 | |
3873e2d7 | 2436 | /* Ensure interrupts from this UART are masked and cleared */ |
9f25bc51 RK |
2437 | pl011_write(0, uap, REG_IMSC); |
2438 | pl011_write(0xffff, uap, REG_ICR); | |
ef2889f7 TB |
2439 | |
2440 | if (!amba_reg.state) { | |
2441 | ret = uart_register_driver(&amba_reg); | |
2442 | if (ret < 0) { | |
3873e2d7 | 2443 | dev_err(uap->port.dev, |
1c9be310 | 2444 | "Failed to register AMBA-PL011 driver\n"); |
ef2889f7 TB |
2445 | return ret; |
2446 | } | |
2447 | } | |
2448 | ||
1da177e4 | 2449 | ret = uart_add_one_port(&amba_reg, &uap->port); |
49bb3c86 AP |
2450 | if (ret) |
2451 | pl011_unregister_port(uap); | |
7f6d942a | 2452 | |
1da177e4 LT |
2453 | return ret; |
2454 | } | |
2455 | ||
3873e2d7 AP |
2456 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
2457 | { | |
2458 | struct uart_amba_port *uap; | |
2459 | struct vendor_data *vendor = id->data; | |
2460 | int portnr, ret; | |
2461 | ||
2462 | portnr = pl011_find_free_port(); | |
2463 | if (portnr < 0) | |
2464 | return portnr; | |
2465 | ||
2466 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), | |
2467 | GFP_KERNEL); | |
2468 | if (!uap) | |
2469 | return -ENOMEM; | |
2470 | ||
2471 | uap->clk = devm_clk_get(&dev->dev, NULL); | |
2472 | if (IS_ERR(uap->clk)) | |
2473 | return PTR_ERR(uap->clk); | |
2474 | ||
439403bd | 2475 | uap->reg_offset = vendor->reg_offset; |
3873e2d7 | 2476 | uap->vendor = vendor; |
3873e2d7 | 2477 | uap->fifosize = vendor->get_fifosize(dev); |
3b78fae7 | 2478 | uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM; |
3873e2d7 AP |
2479 | uap->port.irq = dev->irq[0]; |
2480 | uap->port.ops = &amba_pl011_pops; | |
2481 | ||
2482 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); | |
2483 | ||
2484 | ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); | |
2485 | if (ret) | |
2486 | return ret; | |
2487 | ||
2488 | amba_set_drvdata(dev, uap); | |
2489 | ||
2490 | return pl011_register_port(uap); | |
2491 | } | |
2492 | ||
1da177e4 LT |
2493 | static int pl011_remove(struct amba_device *dev) |
2494 | { | |
2495 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1da177e4 | 2496 | |
1da177e4 | 2497 | uart_remove_one_port(&amba_reg, &uap->port); |
49bb3c86 | 2498 | pl011_unregister_port(uap); |
1da177e4 LT |
2499 | return 0; |
2500 | } | |
2501 | ||
d0ce850d UH |
2502 | #ifdef CONFIG_PM_SLEEP |
2503 | static int pl011_suspend(struct device *dev) | |
b736b89f | 2504 | { |
d0ce850d | 2505 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2506 | |
2507 | if (!uap) | |
2508 | return -EINVAL; | |
2509 | ||
2510 | return uart_suspend_port(&amba_reg, &uap->port); | |
2511 | } | |
2512 | ||
d0ce850d | 2513 | static int pl011_resume(struct device *dev) |
b736b89f | 2514 | { |
d0ce850d | 2515 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2516 | |
2517 | if (!uap) | |
2518 | return -EINVAL; | |
2519 | ||
2520 | return uart_resume_port(&amba_reg, &uap->port); | |
2521 | } | |
2522 | #endif | |
2523 | ||
d0ce850d UH |
2524 | static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); |
2525 | ||
0dd1e247 AP |
2526 | static int sbsa_uart_probe(struct platform_device *pdev) |
2527 | { | |
2528 | struct uart_amba_port *uap; | |
2529 | struct resource *r; | |
2530 | int portnr, ret; | |
2531 | int baudrate; | |
2532 | ||
2533 | /* | |
2534 | * Check the mandatory baud rate parameter in the DT node early | |
2535 | * so that we can easily exit with the error. | |
2536 | */ | |
2537 | if (pdev->dev.of_node) { | |
2538 | struct device_node *np = pdev->dev.of_node; | |
2539 | ||
2540 | ret = of_property_read_u32(np, "current-speed", &baudrate); | |
2541 | if (ret) | |
2542 | return ret; | |
2543 | } else { | |
2544 | baudrate = 115200; | |
2545 | } | |
2546 | ||
2547 | portnr = pl011_find_free_port(); | |
2548 | if (portnr < 0) | |
2549 | return portnr; | |
2550 | ||
2551 | uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), | |
2552 | GFP_KERNEL); | |
2553 | if (!uap) | |
2554 | return -ENOMEM; | |
2555 | ||
439403bd | 2556 | uap->reg_offset = vendor_sbsa.reg_offset; |
0dd1e247 AP |
2557 | uap->vendor = &vendor_sbsa; |
2558 | uap->fifosize = 32; | |
3b78fae7 | 2559 | uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM; |
0dd1e247 AP |
2560 | uap->port.irq = platform_get_irq(pdev, 0); |
2561 | uap->port.ops = &sbsa_uart_pops; | |
2562 | uap->fixed_baud = baudrate; | |
2563 | ||
2564 | snprintf(uap->type, sizeof(uap->type), "SBSA"); | |
2565 | ||
2566 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2567 | ||
2568 | ret = pl011_setup_port(&pdev->dev, uap, r, portnr); | |
2569 | if (ret) | |
2570 | return ret; | |
2571 | ||
2572 | platform_set_drvdata(pdev, uap); | |
2573 | ||
2574 | return pl011_register_port(uap); | |
2575 | } | |
2576 | ||
2577 | static int sbsa_uart_remove(struct platform_device *pdev) | |
2578 | { | |
2579 | struct uart_amba_port *uap = platform_get_drvdata(pdev); | |
2580 | ||
2581 | uart_remove_one_port(&amba_reg, &uap->port); | |
2582 | pl011_unregister_port(uap); | |
2583 | return 0; | |
2584 | } | |
2585 | ||
2586 | static const struct of_device_id sbsa_uart_of_match[] = { | |
2587 | { .compatible = "arm,sbsa-uart", }, | |
2588 | {}, | |
2589 | }; | |
2590 | MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); | |
2591 | ||
3db9ab0b GG |
2592 | static const struct acpi_device_id sbsa_uart_acpi_match[] = { |
2593 | { "ARMH0011", 0 }, | |
2594 | {}, | |
2595 | }; | |
2596 | MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); | |
2597 | ||
0dd1e247 AP |
2598 | static struct platform_driver arm_sbsa_uart_platform_driver = { |
2599 | .probe = sbsa_uart_probe, | |
2600 | .remove = sbsa_uart_remove, | |
2601 | .driver = { | |
2602 | .name = "sbsa-uart", | |
2603 | .of_match_table = of_match_ptr(sbsa_uart_of_match), | |
3db9ab0b | 2604 | .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), |
0dd1e247 AP |
2605 | }, |
2606 | }; | |
2607 | ||
2c39c9e1 | 2608 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
2609 | { |
2610 | .id = 0x00041011, | |
2611 | .mask = 0x000fffff, | |
5926a295 AR |
2612 | .data = &vendor_arm, |
2613 | }, | |
2614 | { | |
2615 | .id = 0x00380802, | |
2616 | .mask = 0x00ffffff, | |
2617 | .data = &vendor_st, | |
1da177e4 LT |
2618 | }, |
2619 | { 0, 0 }, | |
2620 | }; | |
2621 | ||
60f7a33b DM |
2622 | MODULE_DEVICE_TABLE(amba, pl011_ids); |
2623 | ||
1da177e4 LT |
2624 | static struct amba_driver pl011_driver = { |
2625 | .drv = { | |
2626 | .name = "uart-pl011", | |
d0ce850d | 2627 | .pm = &pl011_dev_pm_ops, |
1da177e4 LT |
2628 | }, |
2629 | .id_table = pl011_ids, | |
2630 | .probe = pl011_probe, | |
2631 | .remove = pl011_remove, | |
2632 | }; | |
2633 | ||
2634 | static int __init pl011_init(void) | |
2635 | { | |
1da177e4 LT |
2636 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); |
2637 | ||
0dd1e247 AP |
2638 | if (platform_driver_register(&arm_sbsa_uart_platform_driver)) |
2639 | pr_warn("could not register SBSA UART platform driver\n"); | |
062a68a5 | 2640 | return amba_driver_register(&pl011_driver); |
1da177e4 LT |
2641 | } |
2642 | ||
2643 | static void __exit pl011_exit(void) | |
2644 | { | |
0dd1e247 | 2645 | platform_driver_unregister(&arm_sbsa_uart_platform_driver); |
1da177e4 | 2646 | amba_driver_unregister(&pl011_driver); |
1da177e4 LT |
2647 | } |
2648 | ||
4dd9e742 AR |
2649 | /* |
2650 | * While this can be a module, if builtin it's most likely the console | |
2651 | * So let's leave module_exit but move module_init to an earlier place | |
2652 | */ | |
2653 | arch_initcall(pl011_init); | |
1da177e4 LT |
2654 | module_exit(pl011_exit); |
2655 | ||
2656 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
2657 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
2658 | MODULE_LICENSE("GPL"); |