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serial: rewrite pxa2xx-uart to use 8250_core
[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / amba-pl011.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
68b65f73 8 * Copyright (C) 2010 ST-Ericsson SA
1da177e4
LT		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
1da177e4
LT		 24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
1da177e4 31
cb06ff10 32
1da177e4
LT		 33#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34#define SUPPORT_SYSRQ
35#endif
36
37#include <linux/module.h>
38#include <linux/ioport.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/sysrq.h>
42#include <linux/device.h>
43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46#include <linux/serial.h>
a62c80e5
RK		 47#include <linux/amba/bus.h>
48#include <linux/amba/serial.h>
f8ce2547 49#include <linux/clk.h>
5a0e3ad6 50#include <linux/slab.h>
68b65f73
RK		 51#include <linux/dmaengine.h>
52#include <linux/dma-mapping.h>
53#include <linux/scatterlist.h>
c16d51a3 54#include <linux/delay.h>
258aea76 55#include <linux/types.h>
32614aad
ML		 56#include <linux/of.h>
57#include <linux/of_device.h>
258e0551 58#include <linux/pinctrl/consumer.h>
cb70706c 59#include <linux/sizes.h>
de609582 60#include <linux/io.h>
3db9ab0b 61#include <linux/acpi.h>
1da177e4 62
9f25bc51
RK		 63#include "amba-pl011.h"
64
1da177e4
LT		 65#define UART_NR 14
66
67#define SERIAL_AMBA_MAJOR 204
68#define SERIAL_AMBA_MINOR 64
69#define SERIAL_AMBA_NR UART_NR
70
71#define AMBA_ISR_PASS_LIMIT 256
72
b63d4f0f
RK		 73#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
74#define UART_DUMMY_DR_RX (1 << 16)
1da177e4 75
debb7f64
RK		 76static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
77 [REG_DR] = UART01x_DR,
debb7f64 78 [REG_FR] = UART01x_FR,
e4df9a80
RK		 79 [REG_LCRH_RX] = UART011_LCRH,
80 [REG_LCRH_TX] = UART011_LCRH,
debb7f64
RK		 81 [REG_IBRD] = UART011_IBRD,
82 [REG_FBRD] = UART011_FBRD,
debb7f64
RK		 83 [REG_CR] = UART011_CR,
84 [REG_IFLS] = UART011_IFLS,
85 [REG_IMSC] = UART011_IMSC,
86 [REG_RIS] = UART011_RIS,
87 [REG_MIS] = UART011_MIS,
88 [REG_ICR] = UART011_ICR,
89 [REG_DMACR] = UART011_DMACR,
debb7f64
RK		 90};
91
5926a295
AR		 92/* There is by now at least one vendor with differing details, so handle it */
93struct vendor_data {
439403bd 94 const u16 *reg_offset;
5926a295 95 unsigned int ifls;
0e125a5f
SG		 96 unsigned int fr_busy;
97 unsigned int fr_dsr;
98 unsigned int fr_cts;
99 unsigned int fr_ri;
84c3e03b 100 bool access_32b;
ac3e3fb4 101 bool oversampling;
38d62436 102 bool dma_threshold;
4fd0690b 103 bool cts_event_workaround;
71eec483 104 bool always_enabled;
cefc2d1d 105 bool fixed_options;
78506f22 106
ea33640a 107 unsigned int (*get_fifosize)(struct amba_device *dev);
5926a295
AR		 108};
109
ea33640a 110static unsigned int get_fifosize_arm(struct amba_device *dev)
78506f22 111{
ea33640a 112 return amba_rev(dev) < 3 ? 16 : 32;
78506f22
JK		 113}
114
5926a295 115static struct vendor_data vendor_arm = {
439403bd 116 .reg_offset = pl011_std_offsets,
5926a295 117 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
0e125a5f
SG		 118 .fr_busy = UART01x_FR_BUSY,
119 .fr_dsr = UART01x_FR_DSR,
120 .fr_cts = UART01x_FR_CTS,
121 .fr_ri = UART011_FR_RI,
ac3e3fb4 122 .oversampling = false,
38d62436 123 .dma_threshold = false,
4fd0690b 124 .cts_event_workaround = false,
71eec483 125 .always_enabled = false,
cefc2d1d 126 .fixed_options = false,
78506f22 127 .get_fifosize = get_fifosize_arm,
5926a295
AR		 128};
129
0dd1e247 130static struct vendor_data vendor_sbsa = {
439403bd 131 .reg_offset = pl011_std_offsets,
0e125a5f
SG		 132 .fr_busy = UART01x_FR_BUSY,
133 .fr_dsr = UART01x_FR_DSR,
134 .fr_cts = UART01x_FR_CTS,
135 .fr_ri = UART011_FR_RI,
1aabf523 136 .access_32b = true,
0dd1e247
AP		 137 .oversampling = false,
138 .dma_threshold = false,
139 .cts_event_workaround = false,
140 .always_enabled = true,
141 .fixed_options = true,
142};
143
bf69ff8a
RK		 144static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
145 [REG_DR] = UART01x_DR,
146 [REG_ST_DMAWM] = ST_UART011_DMAWM,
147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
148 [REG_FR] = UART01x_FR,
e4df9a80
RK		 149 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
150 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
bf69ff8a
RK		 151 [REG_IBRD] = UART011_IBRD,
152 [REG_FBRD] = UART011_FBRD,
bf69ff8a
RK		 153 [REG_CR] = UART011_CR,
154 [REG_IFLS] = UART011_IFLS,
155 [REG_IMSC] = UART011_IMSC,
156 [REG_RIS] = UART011_RIS,
157 [REG_MIS] = UART011_MIS,
158 [REG_ICR] = UART011_ICR,
159 [REG_DMACR] = UART011_DMACR,
160 [REG_ST_XFCR] = ST_UART011_XFCR,
161 [REG_ST_XON1] = ST_UART011_XON1,
162 [REG_ST_XON2] = ST_UART011_XON2,
163 [REG_ST_XOFF1] = ST_UART011_XOFF1,
164 [REG_ST_XOFF2] = ST_UART011_XOFF2,
165 [REG_ST_ITCR] = ST_UART011_ITCR,
166 [REG_ST_ITIP] = ST_UART011_ITIP,
167 [REG_ST_ABCR] = ST_UART011_ABCR,
168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
169};
170
ea33640a 171static unsigned int get_fifosize_st(struct amba_device *dev)
78506f22
JK		 172{
173 return 64;
174}
175
5926a295 176static struct vendor_data vendor_st = {
bf69ff8a 177 .reg_offset = pl011_st_offsets,
5926a295 178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
0e125a5f
SG		 179 .fr_busy = UART01x_FR_BUSY,
180 .fr_dsr = UART01x_FR_DSR,
181 .fr_cts = UART01x_FR_CTS,
182 .fr_ri = UART011_FR_RI,
ac3e3fb4 183 .oversampling = true,
38d62436 184 .dma_threshold = true,
4fd0690b 185 .cts_event_workaround = true,
71eec483 186 .always_enabled = false,
cefc2d1d 187 .fixed_options = false,
78506f22 188 .get_fifosize = get_fifosize_st,
1da177e4
LT		 189};
190
7ec75871
RK		 191static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
192 [REG_DR] = ZX_UART011_DR,
193 [REG_FR] = ZX_UART011_FR,
194 [REG_LCRH_RX] = ZX_UART011_LCRH,
195 [REG_LCRH_TX] = ZX_UART011_LCRH,
196 [REG_IBRD] = ZX_UART011_IBRD,
197 [REG_FBRD] = ZX_UART011_FBRD,
198 [REG_CR] = ZX_UART011_CR,
199 [REG_IFLS] = ZX_UART011_IFLS,
200 [REG_IMSC] = ZX_UART011_IMSC,
201 [REG_RIS] = ZX_UART011_RIS,
202 [REG_MIS] = ZX_UART011_MIS,
203 [REG_ICR] = ZX_UART011_ICR,
204 [REG_DMACR] = ZX_UART011_DMACR,
205};
206
9c267ddb
SG		 207static unsigned int get_fifosize_zte(struct amba_device *dev)
208{
209 return 16;
210}
211
2426fbc7 212static struct vendor_data vendor_zte = {
7ec75871
RK		 213 .reg_offset = pl011_zte_offsets,
214 .access_32b = true,
215 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
0e125a5f
SG		 216 .fr_busy = ZX_UART01x_FR_BUSY,
217 .fr_dsr = ZX_UART01x_FR_DSR,
218 .fr_cts = ZX_UART01x_FR_CTS,
219 .fr_ri = ZX_UART011_FR_RI,
9c267ddb 220 .get_fifosize = get_fifosize_zte,
7ec75871
RK		 221};
222
68b65f73 223/* Deals with DMA transactions */
ead76f32
LW		 224
225struct pl011_sgbuf {
226 struct scatterlist sg;
227 char *buf;
228};
229
230struct pl011_dmarx_data {
231 struct dma_chan *chan;
232 struct completion complete;
233 bool use_buf_b;
234 struct pl011_sgbuf sgbuf_a;
235 struct pl011_sgbuf sgbuf_b;
236 dma_cookie_t cookie;
237 bool running;
cb06ff10
CM		 238 struct timer_list timer;
239 unsigned int last_residue;
240 unsigned long last_jiffies;
241 bool auto_poll_rate;
242 unsigned int poll_rate;
243 unsigned int poll_timeout;
ead76f32
LW		 244};
245
68b65f73
RK		 246struct pl011_dmatx_data {
247 struct dma_chan *chan;
248 struct scatterlist sg;
249 char *buf;
250 bool queued;
251};
252
c19f12b5
RK		 253/*
254 * We wrap our port structure around the generic uart_port.
255 */
256struct uart_amba_port {
257 struct uart_port port;
debb7f64 258 const u16 *reg_offset;
c19f12b5
RK		 259 struct clk *clk;
260 const struct vendor_data *vendor;
68b65f73 261 unsigned int dmacr; /* dma control reg */
c19f12b5
RK		 262 unsigned int im; /* interrupt mask */
263 unsigned int old_status;
ffca2b11 264 unsigned int fifosize; /* vendor-specific */
d8d8ffa4 265 unsigned int old_cr; /* state during shutdown */
c19f12b5 266 bool autorts;
cefc2d1d 267 unsigned int fixed_baud; /* vendor-set fixed baud rate */
c19f12b5 268 char type[12];
68b65f73
RK		 269#ifdef CONFIG_DMA_ENGINE
270 /* DMA stuff */
ead76f32
LW		 271 bool using_tx_dma;
272 bool using_rx_dma;
273 struct pl011_dmarx_data dmarx;
68b65f73 274 struct pl011_dmatx_data dmatx;
1c9be310 275 bool dma_probed;
68b65f73
RK		 276#endif
277};
278
9f25bc51
RK		 279static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
280 unsigned int reg)
281{
debb7f64 282 return uap->reg_offset[reg];
9f25bc51
RK		 283}
284
b2a4e24c
RK		 285static unsigned int pl011_read(const struct uart_amba_port *uap,
286 unsigned int reg)
75836339 287{
84c3e03b
RK		 288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
289
3b78fae7
TT		 290 return (uap->port.iotype == UPIO_MEM32) ?
291 readl_relaxed(addr) : readw_relaxed(addr);
75836339
RK		 292}
293
b2a4e24c
RK		 294static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
295 unsigned int reg)
75836339 296{
84c3e03b
RK		 297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
298
3b78fae7 299 if (uap->port.iotype == UPIO_MEM32)
f5ce6edd 300 writel_relaxed(val, addr);
84c3e03b 301 else
f5ce6edd 302 writew_relaxed(val, addr);
75836339
RK		 303}
304
29772c4e
LW		 305/*
306 * Reads up to 256 characters from the FIFO or until it's empty and
307 * inserts them into the TTY layer. Returns the number of characters
308 * read from the FIFO.
309 */
310static int pl011_fifo_to_tty(struct uart_amba_port *uap)
311{
71a5cd8a
TT		 312 u16 status;
313 unsigned int ch, flag, max_count = 256;
29772c4e
LW		 314 int fifotaken = 0;
315
316 while (max_count--) {
9f25bc51 317 status = pl011_read(uap, REG_FR);
29772c4e
LW		 318 if (status & UART01x_FR_RXFE)
319 break;
320
321 /* Take chars from the FIFO and update status */
9f25bc51 322 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
29772c4e
LW		 323 flag = TTY_NORMAL;
324 uap->port.icount.rx++;
325 fifotaken++;
326
327 if (unlikely(ch & UART_DR_ERROR)) {
328 if (ch & UART011_DR_BE) {
329 ch &= ~(UART011_DR_FE | UART011_DR_PE);
330 uap->port.icount.brk++;
331 if (uart_handle_break(&uap->port))
332 continue;
333 } else if (ch & UART011_DR_PE)
334 uap->port.icount.parity++;
335 else if (ch & UART011_DR_FE)
336 uap->port.icount.frame++;
337 if (ch & UART011_DR_OE)
338 uap->port.icount.overrun++;
339
340 ch &= uap->port.read_status_mask;
341
342 if (ch & UART011_DR_BE)
343 flag = TTY_BREAK;
344 else if (ch & UART011_DR_PE)
345 flag = TTY_PARITY;
346 else if (ch & UART011_DR_FE)
347 flag = TTY_FRAME;
348 }
349
350 if (uart_handle_sysrq_char(&uap->port, ch & 255))
351 continue;
352
353 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
354 }
355
356 return fifotaken;
357}
358
359
68b65f73
RK		 360/*
361 * All the DMA operation mode stuff goes inside this ifdef.
362 * This assumes that you have a generic DMA device interface,
363 * no custom DMA interfaces are supported.
364 */
365#ifdef CONFIG_DMA_ENGINE
366
367#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
368
ead76f32
LW		 369static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
370 enum dma_data_direction dir)
371{
cb06ff10
CM		 372 dma_addr_t dma_addr;
373
374 sg->buf = dma_alloc_coherent(chan->device->dev,
375 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
ead76f32
LW		 376 if (!sg->buf)
377 return -ENOMEM;
378
cb06ff10
CM		 379 sg_init_table(&sg->sg, 1);
380 sg_set_page(&sg->sg, phys_to_page(dma_addr),
381 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
382 sg_dma_address(&sg->sg) = dma_addr;
c64be923 383 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
ead76f32 384
ead76f32
LW		 385 return 0;
386}
387
388static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
389 enum dma_data_direction dir)
390{
391 if (sg->buf) {
cb06ff10
CM		 392 dma_free_coherent(chan->device->dev,
393 PL011_DMA_BUFFER_SIZE, sg->buf,
394 sg_dma_address(&sg->sg));
ead76f32
LW		 395 }
396}
397
1c9be310 398static void pl011_dma_probe(struct uart_amba_port *uap)
68b65f73
RK		 399{
400 /* DMA is the sole user of the platform data right now */
574de559 401 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
1c9be310 402 struct device *dev = uap->port.dev;
68b65f73 403 struct dma_slave_config tx_conf = {
9f25bc51
RK		 404 .dst_addr = uap->port.mapbase +
405 pl011_reg_to_offset(uap, REG_DR),
68b65f73 406 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 407 .direction = DMA_MEM_TO_DEV,
68b65f73 408 .dst_maxburst = uap->fifosize >> 1,
258aea76 409 .device_fc = false,
68b65f73
RK		 410 };
411 struct dma_chan *chan;
412 dma_cap_mask_t mask;
413
1c9be310
JRO		 414 uap->dma_probed = true;
415 chan = dma_request_slave_channel_reason(dev, "tx");
416 if (IS_ERR(chan)) {
417 if (PTR_ERR(chan) == -EPROBE_DEFER) {
1c9be310
JRO		 418 uap->dma_probed = false;
419 return;
420 }
68b65f73 421
787b0c1f
AB		 422 /* We need platform data */
423 if (!plat || !plat->dma_filter) {
424 dev_info(uap->port.dev, "no DMA platform data\n");
425 return;
426 }
427
428 /* Try to acquire a generic DMA engine slave TX channel */
429 dma_cap_zero(mask);
430 dma_cap_set(DMA_SLAVE, mask);
431
432 chan = dma_request_channel(mask, plat->dma_filter,
433 plat->dma_tx_param);
434 if (!chan) {
435 dev_err(uap->port.dev, "no TX DMA channel!\n");
436 return;
437 }
68b65f73
RK		 438 }
439
440 dmaengine_slave_config(chan, &tx_conf);
441 uap->dmatx.chan = chan;
442
443 dev_info(uap->port.dev, "DMA channel TX %s\n",
444 dma_chan_name(uap->dmatx.chan));
ead76f32
LW		 445
446 /* Optionally make use of an RX channel as well */
787b0c1f 447 chan = dma_request_slave_channel(dev, "rx");
0d3c673e 448
d9e105ca 449 if (!chan && plat && plat->dma_rx_param) {
787b0c1f
AB		 450 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
451
452 if (!chan) {
453 dev_err(uap->port.dev, "no RX DMA channel!\n");
454 return;
455 }
456 }
457
458 if (chan) {
ead76f32 459 struct dma_slave_config rx_conf = {
9f25bc51
RK		 460 .src_addr = uap->port.mapbase +
461 pl011_reg_to_offset(uap, REG_DR),
ead76f32 462 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 463 .direction = DMA_DEV_TO_MEM,
b2aeb775 464 .src_maxburst = uap->fifosize >> 2,
258aea76 465 .device_fc = false,
ead76f32 466 };
2d3b7d6e
AJ		 467 struct dma_slave_caps caps;
468
469 /*
470 * Some DMA controllers provide information on their capabilities.
471 * If the controller does, check for suitable residue processing
472 * otherwise assime all is well.
473 */
474 if (0 == dma_get_slave_caps(chan, &caps)) {
475 if (caps.residue_granularity ==
476 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
477 dma_release_channel(chan);
478 dev_info(uap->port.dev,
479 "RX DMA disabled - no residue processing\n");
480 return;
481 }
482 }
ead76f32
LW		 483 dmaengine_slave_config(chan, &rx_conf);
484 uap->dmarx.chan = chan;
485
98267d33 486 uap->dmarx.auto_poll_rate = false;
8f898bfd 487 if (plat && plat->dma_rx_poll_enable) {
cb06ff10
CM		 488 /* Set poll rate if specified. */
489 if (plat->dma_rx_poll_rate) {
490 uap->dmarx.auto_poll_rate = false;
491 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
492 } else {
493 /*
494 * 100 ms defaults to poll rate if not
495 * specified. This will be adjusted with
496 * the baud rate at set_termios.
497 */
498 uap->dmarx.auto_poll_rate = true;
499 uap->dmarx.poll_rate = 100;
500 }
501 /* 3 secs defaults poll_timeout if not specified. */
502 if (plat->dma_rx_poll_timeout)
503 uap->dmarx.poll_timeout =
504 plat->dma_rx_poll_timeout;
505 else
506 uap->dmarx.poll_timeout = 3000;
98267d33
AJ		 507 } else if (!plat && dev->of_node) {
508 uap->dmarx.auto_poll_rate = of_property_read_bool(
509 dev->of_node, "auto-poll");
510 if (uap->dmarx.auto_poll_rate) {
511 u32 x;
512
513 if (0 == of_property_read_u32(dev->of_node,
514 "poll-rate-ms", &x))
515 uap->dmarx.poll_rate = x;
516 else
517 uap->dmarx.poll_rate = 100;
518 if (0 == of_property_read_u32(dev->of_node,
519 "poll-timeout-ms", &x))
520 uap->dmarx.poll_timeout = x;
521 else
522 uap->dmarx.poll_timeout = 3000;
523 }
524 }
ead76f32
LW		 525 dev_info(uap->port.dev, "DMA channel RX %s\n",
526 dma_chan_name(uap->dmarx.chan));
527 }
68b65f73
RK		 528}
529
68b65f73
RK		 530static void pl011_dma_remove(struct uart_amba_port *uap)
531{
68b65f73
RK		 532 if (uap->dmatx.chan)
533 dma_release_channel(uap->dmatx.chan);
ead76f32
LW		 534 if (uap->dmarx.chan)
535 dma_release_channel(uap->dmarx.chan);
68b65f73
RK		 536}
537
734745ca 538/* Forward declare these for the refill routine */
68b65f73 539static int pl011_dma_tx_refill(struct uart_amba_port *uap);
734745ca 540static void pl011_start_tx_pio(struct uart_amba_port *uap);
68b65f73
RK		 541
542/*
543 * The current DMA TX buffer has been sent.
544 * Try to queue up another DMA buffer.
545 */
546static void pl011_dma_tx_callback(void *data)
547{
548 struct uart_amba_port *uap = data;
549 struct pl011_dmatx_data *dmatx = &uap->dmatx;
550 unsigned long flags;
551 u16 dmacr;
552
553 spin_lock_irqsave(&uap->port.lock, flags);
554 if (uap->dmatx.queued)
555 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
556 DMA_TO_DEVICE);
557
558 dmacr = uap->dmacr;
559 uap->dmacr = dmacr & ~UART011_TXDMAE;
9f25bc51 560 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 561
562 /*
563 * If TX DMA was disabled, it means that we've stopped the DMA for
564 * some reason (eg, XOFF received, or we want to send an X-char.)
565 *
566 * Note: we need to be careful here of a potential race between DMA
567 * and the rest of the driver - if the driver disables TX DMA while
568 * a TX buffer completing, we must update the tx queued status to
569 * get further refills (hence we check dmacr).
570 */
571 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
572 uart_circ_empty(&uap->port.state->xmit)) {
573 uap->dmatx.queued = false;
574 spin_unlock_irqrestore(&uap->port.lock, flags);
575 return;
576 }
577
734745ca 578 if (pl011_dma_tx_refill(uap) <= 0)
68b65f73
RK		 579 /*
580 * We didn't queue a DMA buffer for some reason, but we
581 * have data pending to be sent. Re-enable the TX IRQ.
582 */
734745ca
DM		 583 pl011_start_tx_pio(uap);
584
68b65f73
RK		 585 spin_unlock_irqrestore(&uap->port.lock, flags);
586}
587
588/*
589 * Try to refill the TX DMA buffer.
590 * Locking: called with port lock held and IRQs disabled.
591 * Returns:
592 * 1 if we queued up a TX DMA buffer.
593 * 0 if we didn't want to handle this by DMA
594 * <0 on error
595 */
596static int pl011_dma_tx_refill(struct uart_amba_port *uap)
597{
598 struct pl011_dmatx_data *dmatx = &uap->dmatx;
599 struct dma_chan *chan = dmatx->chan;
600 struct dma_device *dma_dev = chan->device;
601 struct dma_async_tx_descriptor *desc;
602 struct circ_buf *xmit = &uap->port.state->xmit;
603 unsigned int count;
604
605 /*
606 * Try to avoid the overhead involved in using DMA if the
607 * transaction fits in the first half of the FIFO, by using
608 * the standard interrupt handling. This ensures that we
609 * issue a uart_write_wakeup() at the appropriate time.
610 */
611 count = uart_circ_chars_pending(xmit);
612 if (count < (uap->fifosize >> 1)) {
613 uap->dmatx.queued = false;
614 return 0;
615 }
616
617 /*
618 * Bodge: don't send the last character by DMA, as this
619 * will prevent XON from notifying us to restart DMA.
620 */
621 count -= 1;
622
623 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
624 if (count > PL011_DMA_BUFFER_SIZE)
625 count = PL011_DMA_BUFFER_SIZE;
626
627 if (xmit->tail < xmit->head)
628 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
629 else {
630 size_t first = UART_XMIT_SIZE - xmit->tail;
e2a545a6
AJ		 631 size_t second;
632
633 if (first > count)
634 first = count;
635 second = count - first;
68b65f73
RK		 636
637 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
638 if (second)
639 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
640 }
641
642 dmatx->sg.length = count;
643
644 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
645 uap->dmatx.queued = false;
646 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
647 return -EBUSY;
648 }
649
16052827 650 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
68b65f73
RK		 651 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
652 if (!desc) {
653 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
654 uap->dmatx.queued = false;
655 /*
656 * If DMA cannot be used right now, we complete this
657 * transaction via IRQ and let the TTY layer retry.
658 */
659 dev_dbg(uap->port.dev, "TX DMA busy\n");
660 return -EBUSY;
661 }
662
663 /* Some data to go along to the callback */
664 desc->callback = pl011_dma_tx_callback;
665 desc->callback_param = uap;
666
667 /* All errors should happen at prepare time */
668 dmaengine_submit(desc);
669
670 /* Fire the DMA transaction */
671 dma_dev->device_issue_pending(chan);
672
673 uap->dmacr |= UART011_TXDMAE;
9f25bc51 674 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 675 uap->dmatx.queued = true;
676
677 /*
678 * Now we know that DMA will fire, so advance the ring buffer
679 * with the stuff we just dispatched.
680 */
681 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
682 uap->port.icount.tx += count;
683
684 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
685 uart_write_wakeup(&uap->port);
686
687 return 1;
688}
689
690/*
691 * We received a transmit interrupt without a pending X-char but with
692 * pending characters.
693 * Locking: called with port lock held and IRQs disabled.
694 * Returns:
695 * false if we want to use PIO to transmit
696 * true if we queued a DMA buffer
697 */
698static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
699{
ead76f32 700 if (!uap->using_tx_dma)
68b65f73
RK		 701 return false;
702
703 /*
704 * If we already have a TX buffer queued, but received a
705 * TX interrupt, it will be because we've just sent an X-char.
706 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
707 */
708 if (uap->dmatx.queued) {
709 uap->dmacr |= UART011_TXDMAE;
9f25bc51 710 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73 711 uap->im &= ~UART011_TXIM;
9f25bc51 712 pl011_write(uap->im, uap, REG_IMSC);
68b65f73
RK		 713 return true;
714 }
715
716 /*
717 * We don't have a TX buffer queued, so try to queue one.
25985edc 718 * If we successfully queued a buffer, mask the TX IRQ.
68b65f73
RK		 719 */
720 if (pl011_dma_tx_refill(uap) > 0) {
721 uap->im &= ~UART011_TXIM;
9f25bc51 722 pl011_write(uap->im, uap, REG_IMSC);
68b65f73
RK		 723 return true;
724 }
725 return false;
726}
727
728/*
729 * Stop the DMA transmit (eg, due to received XOFF).
730 * Locking: called with port lock held and IRQs disabled.
731 */
732static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
733{
734 if (uap->dmatx.queued) {
735 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 736 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 737 }
738}
739
740/*
741 * Try to start a DMA transmit, or in the case of an XON/OFF
742 * character queued for send, try to get that character out ASAP.
743 * Locking: called with port lock held and IRQs disabled.
744 * Returns:
745 * false if we want the TX IRQ to be enabled
746 * true if we have a buffer queued
747 */
748static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
749{
750 u16 dmacr;
751
ead76f32 752 if (!uap->using_tx_dma)
68b65f73
RK		 753 return false;
754
755 if (!uap->port.x_char) {
756 /* no X-char, try to push chars out in DMA mode */
757 bool ret = true;
758
759 if (!uap->dmatx.queued) {
760 if (pl011_dma_tx_refill(uap) > 0) {
761 uap->im &= ~UART011_TXIM;
9f25bc51 762 pl011_write(uap->im, uap, REG_IMSC);
734745ca 763 } else
68b65f73 764 ret = false;
68b65f73
RK		 765 } else if (!(uap->dmacr & UART011_TXDMAE)) {
766 uap->dmacr |= UART011_TXDMAE;
9f25bc51 767 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 768 }
769 return ret;
770 }
771
772 /*
773 * We have an X-char to send. Disable DMA to prevent it loading
774 * the TX fifo, and then see if we can stuff it into the FIFO.
775 */
776 dmacr = uap->dmacr;
777 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 778 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73 779
9f25bc51 780 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
68b65f73
RK		 781 /*
782 * No space in the FIFO, so enable the transmit interrupt
783 * so we know when there is space. Note that once we've
784 * loaded the character, we should just re-enable DMA.
785 */
786 return false;
787 }
788
9f25bc51 789 pl011_write(uap->port.x_char, uap, REG_DR);
68b65f73
RK		 790 uap->port.icount.tx++;
791 uap->port.x_char = 0;
792
793 /* Success - restore the DMA state */
794 uap->dmacr = dmacr;
9f25bc51 795 pl011_write(dmacr, uap, REG_DMACR);
68b65f73
RK		 796
797 return true;
798}
799
800/*
801 * Flush the transmit buffer.
802 * Locking: called with port lock held and IRQs disabled.
803 */
804static void pl011_dma_flush_buffer(struct uart_port *port)
b83286bf
FE		 805__releases(&uap->port.lock)
806__acquires(&uap->port.lock)
68b65f73 807{
a5820c24
DT		 808 struct uart_amba_port *uap =
809 container_of(port, struct uart_amba_port, port);
68b65f73 810
ead76f32 811 if (!uap->using_tx_dma)
68b65f73
RK		 812 return;
813
814 /* Avoid deadlock with the DMA engine callback */
815 spin_unlock(&uap->port.lock);
816 dmaengine_terminate_all(uap->dmatx.chan);
817 spin_lock(&uap->port.lock);
818 if (uap->dmatx.queued) {
819 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
820 DMA_TO_DEVICE);
821 uap->dmatx.queued = false;
822 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 823 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 824 }
825}
826
ead76f32
LW		 827static void pl011_dma_rx_callback(void *data);
828
829static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
830{
831 struct dma_chan *rxchan = uap->dmarx.chan;
ead76f32
LW		 832 struct pl011_dmarx_data *dmarx = &uap->dmarx;
833 struct dma_async_tx_descriptor *desc;
834 struct pl011_sgbuf *sgbuf;
835
836 if (!rxchan)
837 return -EIO;
838
839 /* Start the RX DMA job */
840 sgbuf = uap->dmarx.use_buf_b ?
841 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
16052827 842 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
a485df4b 843 DMA_DEV_TO_MEM,
ead76f32
LW		 844 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
845 /*
846 * If the DMA engine is busy and cannot prepare a
847 * channel, no big deal, the driver will fall back
848 * to interrupt mode as a result of this error code.
849 */
850 if (!desc) {
851 uap->dmarx.running = false;
852 dmaengine_terminate_all(rxchan);
853 return -EBUSY;
854 }
855
856 /* Some data to go along to the callback */
857 desc->callback = pl011_dma_rx_callback;
858 desc->callback_param = uap;
859 dmarx->cookie = dmaengine_submit(desc);
860 dma_async_issue_pending(rxchan);
861
862 uap->dmacr |= UART011_RXDMAE;
9f25bc51 863 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32
LW		 864 uap->dmarx.running = true;
865
866 uap->im &= ~UART011_RXIM;
9f25bc51 867 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 868
869 return 0;
870}
871
872/*
873 * This is called when either the DMA job is complete, or
874 * the FIFO timeout interrupt occurred. This must be called
875 * with the port spinlock uap->port.lock held.
876 */
877static void pl011_dma_rx_chars(struct uart_amba_port *uap,
878 u32 pending, bool use_buf_b,
879 bool readfifo)
880{
05c7cd39 881 struct tty_port *port = &uap->port.state->port;
ead76f32
LW		 882 struct pl011_sgbuf *sgbuf = use_buf_b ?
883 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
ead76f32
LW		 884 int dma_count = 0;
885 u32 fifotaken = 0; /* only used for vdbg() */
886
cb06ff10
CM		 887 struct pl011_dmarx_data *dmarx = &uap->dmarx;
888 int dmataken = 0;
889
890 if (uap->dmarx.poll_rate) {
891 /* The data can be taken by polling */
892 dmataken = sgbuf->sg.length - dmarx->last_residue;
893 /* Recalculate the pending size */
894 if (pending >= dmataken)
895 pending -= dmataken;
896 }
897
898 /* Pick the remain data from the DMA */
ead76f32 899 if (pending) {
ead76f32
LW		 900
901 /*
902 * First take all chars in the DMA pipe, then look in the FIFO.
903 * Note that tty_insert_flip_buf() tries to take as many chars
904 * as it can.
905 */
cb06ff10
CM		 906 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
907 pending);
ead76f32
LW		 908
909 uap->port.icount.rx += dma_count;
910 if (dma_count < pending)
911 dev_warn(uap->port.dev,
912 "couldn't insert all characters (TTY is full?)\n");
913 }
914
cb06ff10
CM		 915 /* Reset the last_residue for Rx DMA poll */
916 if (uap->dmarx.poll_rate)
917 dmarx->last_residue = sgbuf->sg.length;
918
ead76f32
LW		 919 /*
920 * Only continue with trying to read the FIFO if all DMA chars have
921 * been taken first.
922 */
923 if (dma_count == pending && readfifo) {
924 /* Clear any error flags */
75836339 925 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
9f25bc51 926 UART011_FEIS, uap, REG_ICR);
ead76f32
LW		 927
928 /*
929 * If we read all the DMA'd characters, and we had an
29772c4e
LW		 930 * incomplete buffer, that could be due to an rx error, or
931 * maybe we just timed out. Read any pending chars and check
932 * the error status.
933 *
934 * Error conditions will only occur in the FIFO, these will
935 * trigger an immediate interrupt and stop the DMA job, so we
936 * will always find the error in the FIFO, never in the DMA
937 * buffer.
ead76f32 938 */
29772c4e 939 fifotaken = pl011_fifo_to_tty(uap);
ead76f32
LW		 940 }
941
942 spin_unlock(&uap->port.lock);
943 dev_vdbg(uap->port.dev,
944 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
945 dma_count, fifotaken);
2e124b4a 946 tty_flip_buffer_push(port);
ead76f32
LW		 947 spin_lock(&uap->port.lock);
948}
949
950static void pl011_dma_rx_irq(struct uart_amba_port *uap)
951{
952 struct pl011_dmarx_data *dmarx = &uap->dmarx;
953 struct dma_chan *rxchan = dmarx->chan;
954 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
955 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
956 size_t pending;
957 struct dma_tx_state state;
958 enum dma_status dmastat;
959
960 /*
961 * Pause the transfer so we can trust the current counter,
962 * do this before we pause the PL011 block, else we may
963 * overflow the FIFO.
964 */
965 if (dmaengine_pause(rxchan))
966 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
967 dmastat = rxchan->device->device_tx_status(rxchan,
968 dmarx->cookie, &state);
969 if (dmastat != DMA_PAUSED)
970 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
971
972 /* Disable RX DMA - incoming data will wait in the FIFO */
973 uap->dmacr &= ~UART011_RXDMAE;
9f25bc51 974 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32
LW		 975 uap->dmarx.running = false;
976
977 pending = sgbuf->sg.length - state.residue;
978 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
979 /* Then we terminate the transfer - we now know our residue */
980 dmaengine_terminate_all(rxchan);
981
982 /*
983 * This will take the chars we have so far and insert
984 * into the framework.
985 */
986 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
987
988 /* Switch buffer & re-trigger DMA job */
989 dmarx->use_buf_b = !dmarx->use_buf_b;
990 if (pl011_dma_rx_trigger_dma(uap)) {
991 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
992 "fall back to interrupt mode\n");
993 uap->im |= UART011_RXIM;
9f25bc51 994 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 995 }
996}
997
998static void pl011_dma_rx_callback(void *data)
999{
1000 struct uart_amba_port *uap = data;
1001 struct pl011_dmarx_data *dmarx = &uap->dmarx;
6dc01aa6 1002 struct dma_chan *rxchan = dmarx->chan;
ead76f32 1003 bool lastbuf = dmarx->use_buf_b;
6dc01aa6
CM		 1004 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1005 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1006 size_t pending;
1007 struct dma_tx_state state;
ead76f32
LW		 1008 int ret;
1009
1010 /*
1011 * This completion interrupt occurs typically when the
1012 * RX buffer is totally stuffed but no timeout has yet
1013 * occurred. When that happens, we just want the RX
1014 * routine to flush out the secondary DMA buffer while
1015 * we immediately trigger the next DMA job.
1016 */
1017 spin_lock_irq(&uap->port.lock);
6dc01aa6
CM		 1018 /*
1019 * Rx data can be taken by the UART interrupts during
1020 * the DMA irq handler. So we check the residue here.
1021 */
1022 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1023 pending = sgbuf->sg.length - state.residue;
1024 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1025 /* Then we terminate the transfer - we now know our residue */
1026 dmaengine_terminate_all(rxchan);
1027
ead76f32
LW		 1028 uap->dmarx.running = false;
1029 dmarx->use_buf_b = !lastbuf;
1030 ret = pl011_dma_rx_trigger_dma(uap);
1031
6dc01aa6 1032 pl011_dma_rx_chars(uap, pending, lastbuf, false);
ead76f32
LW		 1033 spin_unlock_irq(&uap->port.lock);
1034 /*
1035 * Do this check after we picked the DMA chars so we don't
1036 * get some IRQ immediately from RX.
1037 */
1038 if (ret) {
1039 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1040 "fall back to interrupt mode\n");
1041 uap->im |= UART011_RXIM;
9f25bc51 1042 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1043 }
1044}
1045
1046/*
1047 * Stop accepting received characters, when we're shutting down or
1048 * suspending this port.
1049 * Locking: called with port lock held and IRQs disabled.
1050 */
1051static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1052{
1053 /* FIXME. Just disable the DMA enable */
1054 uap->dmacr &= ~UART011_RXDMAE;
9f25bc51 1055 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32 1056}
68b65f73 1057
cb06ff10
CM		 1058/*
1059 * Timer handler for Rx DMA polling.
1060 * Every polling, It checks the residue in the dma buffer and transfer
1061 * data to the tty. Also, last_residue is updated for the next polling.
1062 */
1063static void pl011_dma_rx_poll(unsigned long args)
1064{
1065 struct uart_amba_port *uap = (struct uart_amba_port *)args;
1066 struct tty_port *port = &uap->port.state->port;
1067 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1068 struct dma_chan *rxchan = uap->dmarx.chan;
1069 unsigned long flags = 0;
1070 unsigned int dmataken = 0;
1071 unsigned int size = 0;
1072 struct pl011_sgbuf *sgbuf;
1073 int dma_count;
1074 struct dma_tx_state state;
1075
1076 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1077 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1078 if (likely(state.residue < dmarx->last_residue)) {
1079 dmataken = sgbuf->sg.length - dmarx->last_residue;
1080 size = dmarx->last_residue - state.residue;
1081 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1082 size);
1083 if (dma_count == size)
1084 dmarx->last_residue = state.residue;
1085 dmarx->last_jiffies = jiffies;
1086 }
1087 tty_flip_buffer_push(port);
1088
1089 /*
1090 * If no data is received in poll_timeout, the driver will fall back
1091 * to interrupt mode. We will retrigger DMA at the first interrupt.
1092 */
1093 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1094 > uap->dmarx.poll_timeout) {
1095
1096 spin_lock_irqsave(&uap->port.lock, flags);
1097 pl011_dma_rx_stop(uap);
c25a1ad7 1098 uap->im |= UART011_RXIM;
9f25bc51 1099 pl011_write(uap->im, uap, REG_IMSC);
cb06ff10
CM		 1100 spin_unlock_irqrestore(&uap->port.lock, flags);
1101
1102 uap->dmarx.running = false;
1103 dmaengine_terminate_all(rxchan);
1104 del_timer(&uap->dmarx.timer);
1105 } else {
1106 mod_timer(&uap->dmarx.timer,
1107 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1108 }
1109}
1110
68b65f73
RK		 1111static void pl011_dma_startup(struct uart_amba_port *uap)
1112{
ead76f32
LW		 1113 int ret;
1114
1c9be310
JRO		 1115 if (!uap->dma_probed)
1116 pl011_dma_probe(uap);
1117
68b65f73
RK		 1118 if (!uap->dmatx.chan)
1119 return;
1120
4c0be45b 1121 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
68b65f73
RK		 1122 if (!uap->dmatx.buf) {
1123 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1124 uap->port.fifosize = uap->fifosize;
1125 return;
1126 }
1127
1128 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1129
1130 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1131 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
ead76f32
LW		 1132 uap->using_tx_dma = true;
1133
1134 if (!uap->dmarx.chan)
1135 goto skip_rx;
1136
1137 /* Allocate and map DMA RX buffers */
1138 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1139 DMA_FROM_DEVICE);
1140 if (ret) {
1141 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1142 "RX buffer A", ret);
1143 goto skip_rx;
1144 }
68b65f73 1145
ead76f32
LW		 1146 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1147 DMA_FROM_DEVICE);
1148 if (ret) {
1149 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1150 "RX buffer B", ret);
1151 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1152 DMA_FROM_DEVICE);
1153 goto skip_rx;
1154 }
1155
1156 uap->using_rx_dma = true;
68b65f73 1157
ead76f32 1158skip_rx:
68b65f73
RK		 1159 /* Turn on DMA error (RX/TX will be enabled on demand) */
1160 uap->dmacr |= UART011_DMAONERR;
9f25bc51 1161 pl011_write(uap->dmacr, uap, REG_DMACR);
38d62436
RK		 1162
1163 /*
1164 * ST Micro variants has some specific dma burst threshold
1165 * compensation. Set this to 16 bytes, so burst will only
1166 * be issued above/below 16 bytes.
1167 */
1168 if (uap->vendor->dma_threshold)
75836339 1169 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
9f25bc51 1170 uap, REG_ST_DMAWM);
ead76f32
LW		 1171
1172 if (uap->using_rx_dma) {
1173 if (pl011_dma_rx_trigger_dma(uap))
1174 dev_dbg(uap->port.dev, "could not trigger initial "
1175 "RX DMA job, fall back to interrupt mode\n");
cb06ff10
CM		 1176 if (uap->dmarx.poll_rate) {
1177 init_timer(&(uap->dmarx.timer));
1178 uap->dmarx.timer.function = pl011_dma_rx_poll;
1179 uap->dmarx.timer.data = (unsigned long)uap;
1180 mod_timer(&uap->dmarx.timer,
1181 jiffies +
1182 msecs_to_jiffies(uap->dmarx.poll_rate));
1183 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1184 uap->dmarx.last_jiffies = jiffies;
1185 }
ead76f32 1186 }
68b65f73
RK		 1187}
1188
1189static void pl011_dma_shutdown(struct uart_amba_port *uap)
1190{
ead76f32 1191 if (!(uap->using_tx_dma || uap->using_rx_dma))
68b65f73
RK		 1192 return;
1193
1194 /* Disable RX and TX DMA */
0e125a5f 1195 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
2f2fd089 1196 cpu_relax();
68b65f73
RK		 1197
1198 spin_lock_irq(&uap->port.lock);
1199 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
9f25bc51 1200 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 1201 spin_unlock_irq(&uap->port.lock);
1202
ead76f32
LW		 1203 if (uap->using_tx_dma) {
1204 /* In theory, this should already be done by pl011_dma_flush_buffer */
1205 dmaengine_terminate_all(uap->dmatx.chan);
1206 if (uap->dmatx.queued) {
1207 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1208 DMA_TO_DEVICE);
1209 uap->dmatx.queued = false;
1210 }
1211
1212 kfree(uap->dmatx.buf);
1213 uap->using_tx_dma = false;
68b65f73
RK		 1214 }
1215
ead76f32
LW		 1216 if (uap->using_rx_dma) {
1217 dmaengine_terminate_all(uap->dmarx.chan);
1218 /* Clean up the RX DMA */
1219 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1220 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
cb06ff10
CM		 1221 if (uap->dmarx.poll_rate)
1222 del_timer_sync(&uap->dmarx.timer);
ead76f32
LW		 1223 uap->using_rx_dma = false;
1224 }
1225}
68b65f73 1226
ead76f32
LW		 1227static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1228{
1229 return uap->using_rx_dma;
68b65f73
RK		 1230}
1231
ead76f32
LW		 1232static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1233{
1234 return uap->using_rx_dma && uap->dmarx.running;
1235}
1236
68b65f73
RK		 1237#else
1238/* Blank functions if the DMA engine is not available */
1c9be310 1239static inline void pl011_dma_probe(struct uart_amba_port *uap)
68b65f73
RK		 1240{
1241}
1242
1243static inline void pl011_dma_remove(struct uart_amba_port *uap)
1244{
1245}
1246
1247static inline void pl011_dma_startup(struct uart_amba_port *uap)
1248{
1249}
1250
1251static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1252{
1253}
1254
1255static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1256{
1257 return false;
1258}
1259
1260static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1261{
1262}
1263
1264static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1265{
1266 return false;
1267}
1268
ead76f32
LW		 1269static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1270{
1271}
1272
1273static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1274{
1275}
1276
1277static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1278{
1279 return -EIO;
1280}
1281
1282static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1283{
1284 return false;
1285}
1286
1287static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1288{
1289 return false;
1290}
1291
68b65f73
RK		 1292#define pl011_dma_flush_buffer NULL
1293#endif
1294
b129a8cc 1295static void pl011_stop_tx(struct uart_port *port)
1da177e4 1296{
a5820c24
DT		 1297 struct uart_amba_port *uap =
1298 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1299
1300 uap->im &= ~UART011_TXIM;
9f25bc51 1301 pl011_write(uap->im, uap, REG_IMSC);
68b65f73 1302 pl011_dma_tx_stop(uap);
1da177e4
LT		 1303}
1304
1e84d223 1305static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
734745ca
DM		 1306
1307/* Start TX with programmed I/O only (no DMA) */
1308static void pl011_start_tx_pio(struct uart_amba_port *uap)
1309{
1310 uap->im |= UART011_TXIM;
9f25bc51 1311 pl011_write(uap->im, uap, REG_IMSC);
1e84d223 1312 pl011_tx_chars(uap, false);
734745ca
DM		 1313}
1314
b129a8cc 1315static void pl011_start_tx(struct uart_port *port)
1da177e4 1316{
a5820c24
DT		 1317 struct uart_amba_port *uap =
1318 container_of(port, struct uart_amba_port, port);
1da177e4 1319
734745ca
DM		 1320 if (!pl011_dma_tx_start(uap))
1321 pl011_start_tx_pio(uap);
1da177e4
LT		 1322}
1323
1324static void pl011_stop_rx(struct uart_port *port)
1325{
a5820c24
DT		 1326 struct uart_amba_port *uap =
1327 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1328
1329 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1330 UART011_PEIM|UART011_BEIM|UART011_OEIM);
9f25bc51 1331 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1332
1333 pl011_dma_rx_stop(uap);
1da177e4
LT		 1334}
1335
1336static void pl011_enable_ms(struct uart_port *port)
1337{
a5820c24
DT		 1338 struct uart_amba_port *uap =
1339 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1340
1341 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
9f25bc51 1342 pl011_write(uap->im, uap, REG_IMSC);
1da177e4
LT		 1343}
1344
7d12e780 1345static void pl011_rx_chars(struct uart_amba_port *uap)
b83286bf
FE		 1346__releases(&uap->port.lock)
1347__acquires(&uap->port.lock)
1da177e4 1348{
29772c4e 1349 pl011_fifo_to_tty(uap);
1da177e4 1350
2389b272 1351 spin_unlock(&uap->port.lock);
2e124b4a 1352 tty_flip_buffer_push(&uap->port.state->port);
ead76f32
LW		 1353 /*
1354 * If we were temporarily out of DMA mode for a while,
1355 * attempt to switch back to DMA mode again.
1356 */
1357 if (pl011_dma_rx_available(uap)) {
1358 if (pl011_dma_rx_trigger_dma(uap)) {
1359 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1360 "fall back to interrupt mode again\n");
1361 uap->im |= UART011_RXIM;
9f25bc51 1362 pl011_write(uap->im, uap, REG_IMSC);
cb06ff10 1363 } else {
89fa28db 1364#ifdef CONFIG_DMA_ENGINE
cb06ff10
CM		 1365 /* Start Rx DMA poll */
1366 if (uap->dmarx.poll_rate) {
1367 uap->dmarx.last_jiffies = jiffies;
1368 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1369 mod_timer(&uap->dmarx.timer,
1370 jiffies +
1371 msecs_to_jiffies(uap->dmarx.poll_rate));
1372 }
89fa28db 1373#endif
cb06ff10 1374 }
ead76f32 1375 }
2389b272 1376 spin_lock(&uap->port.lock);
1da177e4
LT		 1377}
1378
1e84d223
DM		 1379static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1380 bool from_irq)
734745ca 1381{
1e84d223 1382 if (unlikely(!from_irq) &&
9f25bc51 1383 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1e84d223
DM		 1384 return false; /* unable to transmit character */
1385
9f25bc51 1386 pl011_write(c, uap, REG_DR);
734745ca
DM		 1387 uap->port.icount.tx++;
1388
1e84d223 1389 return true;
734745ca
DM		 1390}
1391
1e84d223 1392static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1da177e4 1393{
ebd2c8f6 1394 struct circ_buf *xmit = &uap->port.state->xmit;
1e84d223 1395 int count = uap->fifosize >> 1;
734745ca 1396
1da177e4 1397 if (uap->port.x_char) {
1e84d223
DM		 1398 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1399 return;
1da177e4 1400 uap->port.x_char = 0;
734745ca 1401 --count;
1da177e4
LT		 1402 }
1403 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
b129a8cc 1404 pl011_stop_tx(&uap->port);
1e84d223 1405 return;
1da177e4
LT		 1406 }
1407
68b65f73
RK		 1408 /* If we are using DMA mode, try to send some characters. */
1409 if (pl011_dma_tx_irq(uap))
1e84d223 1410 return;
68b65f73 1411
1e84d223
DM		 1412 do {
1413 if (likely(from_irq) && count-- == 0)
1da177e4 1414 break;
1e84d223
DM		 1415
1416 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1417 break;
1418
1419 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1420 } while (!uart_circ_empty(xmit));
1da177e4
LT		 1421
1422 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1423 uart_write_wakeup(&uap->port);
1424
1e84d223 1425 if (uart_circ_empty(xmit))
b129a8cc 1426 pl011_stop_tx(&uap->port);
1da177e4
LT		 1427}
1428
1429static void pl011_modem_status(struct uart_amba_port *uap)
1430{
1431 unsigned int status, delta;
1432
9f25bc51 1433 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1da177e4
LT		 1434
1435 delta = status ^ uap->old_status;
1436 uap->old_status = status;
1437
1438 if (!delta)
1439 return;
1440
1441 if (delta & UART01x_FR_DCD)
1442 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1443
0e125a5f 1444 if (delta & uap->vendor->fr_dsr)
1da177e4
LT		 1445 uap->port.icount.dsr++;
1446
0e125a5f
SG		 1447 if (delta & uap->vendor->fr_cts)
1448 uart_handle_cts_change(&uap->port,
1449 status & uap->vendor->fr_cts);
1da177e4 1450
bdc04e31 1451 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1da177e4
LT		 1452}
1453
9c4ef4b0
AP		 1454static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1455{
1456 unsigned int dummy_read;
1457
1458 if (!uap->vendor->cts_event_workaround)
1459 return;
1460
1461 /* workaround to make sure that all bits are unlocked.. */
9f25bc51 1462 pl011_write(0x00, uap, REG_ICR);
9c4ef4b0
AP		 1463
1464 /*
1465 * WA: introduce 26ns(1 uart clk) delay before W1C;
1466 * single apb access will incur 2 pclk(133.12Mhz) delay,
1467 * so add 2 dummy reads
1468 */
9f25bc51
RK		 1469 dummy_read = pl011_read(uap, REG_ICR);
1470 dummy_read = pl011_read(uap, REG_ICR);
9c4ef4b0
AP		 1471}
1472
7d12e780 1473static irqreturn_t pl011_int(int irq, void *dev_id)
1da177e4
LT		 1474{
1475 struct uart_amba_port *uap = dev_id;
963cc981 1476 unsigned long flags;
1da177e4 1477 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
075167ed 1478 u16 imsc;
1da177e4
LT		 1479 int handled = 0;
1480
963cc981 1481 spin_lock_irqsave(&uap->port.lock, flags);
9f25bc51
RK		 1482 imsc = pl011_read(uap, REG_IMSC);
1483 status = pl011_read(uap, REG_RIS) & imsc;
1da177e4
LT		 1484 if (status) {
1485 do {
9c4ef4b0 1486 check_apply_cts_event_workaround(uap);
f11c9841 1487
75836339
RK		 1488 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1489 UART011_RXIS),
9f25bc51 1490 uap, REG_ICR);
1da177e4 1491
ead76f32
LW		 1492 if (status & (UART011_RTIS|UART011_RXIS)) {
1493 if (pl011_dma_rx_running(uap))
1494 pl011_dma_rx_irq(uap);
1495 else
1496 pl011_rx_chars(uap);
1497 }
1da177e4
LT		 1498 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1499 UART011_CTSMIS|UART011_RIMIS))
1500 pl011_modem_status(uap);
1e84d223
DM		 1501 if (status & UART011_TXIS)
1502 pl011_tx_chars(uap, true);
1da177e4 1503
4fd0690b 1504 if (pass_counter-- == 0)
1da177e4
LT		 1505 break;
1506
9f25bc51 1507 status = pl011_read(uap, REG_RIS) & imsc;
1da177e4
LT		 1508 } while (status != 0);
1509 handled = 1;
1510 }
1511
963cc981 1512 spin_unlock_irqrestore(&uap->port.lock, flags);
1da177e4
LT		 1513
1514 return IRQ_RETVAL(handled);
1515}
1516
e643f87f 1517static unsigned int pl011_tx_empty(struct uart_port *port)
1da177e4 1518{
a5820c24
DT		 1519 struct uart_amba_port *uap =
1520 container_of(port, struct uart_amba_port, port);
9f25bc51 1521 unsigned int status = pl011_read(uap, REG_FR);
0e125a5f
SG		 1522 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1523 0 : TIOCSER_TEMT;
1da177e4
LT		 1524}
1525
e643f87f 1526static unsigned int pl011_get_mctrl(struct uart_port *port)
1da177e4 1527{
a5820c24
DT		 1528 struct uart_amba_port *uap =
1529 container_of(port, struct uart_amba_port, port);
1da177e4 1530 unsigned int result = 0;
9f25bc51 1531 unsigned int status = pl011_read(uap, REG_FR);
1da177e4 1532
5159f407 1533#define TIOCMBIT(uartbit, tiocmbit) \
1da177e4
LT		 1534 if (status & uartbit) \
1535 result |= tiocmbit
1536
5159f407 1537 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
0e125a5f
SG		 1538 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1539 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1540 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
5159f407 1541#undef TIOCMBIT
1da177e4
LT		 1542 return result;
1543}
1544
1545static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1546{
a5820c24
DT		 1547 struct uart_amba_port *uap =
1548 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1549 unsigned int cr;
1550
9f25bc51 1551 cr = pl011_read(uap, REG_CR);
1da177e4 1552
5159f407 1553#define TIOCMBIT(tiocmbit, uartbit) \
1da177e4
LT		 1554 if (mctrl & tiocmbit) \
1555 cr |= uartbit; \
1556 else \
1557 cr &= ~uartbit
1558
5159f407
JS		 1559 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1560 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1561 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1562 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1563 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
3b43816f
RV		 1564
1565 if (uap->autorts) {
1566 /* We need to disable auto-RTS if we want to turn RTS off */
1567 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1568 }
5159f407 1569#undef TIOCMBIT
1da177e4 1570
9f25bc51 1571 pl011_write(cr, uap, REG_CR);
1da177e4
LT		 1572}
1573
1574static void pl011_break_ctl(struct uart_port *port, int break_state)
1575{
a5820c24
DT		 1576 struct uart_amba_port *uap =
1577 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1578 unsigned long flags;
1579 unsigned int lcr_h;
1580
1581 spin_lock_irqsave(&uap->port.lock, flags);
e4df9a80 1582 lcr_h = pl011_read(uap, REG_LCRH_TX);
1da177e4
LT		 1583 if (break_state == -1)
1584 lcr_h |= UART01x_LCRH_BRK;
1585 else
1586 lcr_h &= ~UART01x_LCRH_BRK;
e4df9a80 1587 pl011_write(lcr_h, uap, REG_LCRH_TX);
1da177e4
LT		 1588 spin_unlock_irqrestore(&uap->port.lock, flags);
1589}
1590
84b5ae15 1591#ifdef CONFIG_CONSOLE_POLL
5c8124a0
AV		 1592
1593static void pl011_quiesce_irqs(struct uart_port *port)
1594{
a5820c24
DT		 1595 struct uart_amba_port *uap =
1596 container_of(port, struct uart_amba_port, port);
5c8124a0 1597
9f25bc51 1598 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
5c8124a0
AV		 1599 /*
1600 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1601 * we simply mask it. start_tx() will unmask it.
1602 *
1603 * Note we can race with start_tx(), and if the race happens, the
1604 * polling user might get another interrupt just after we clear it.
1605 * But it should be OK and can happen even w/o the race, e.g.
1606 * controller immediately got some new data and raised the IRQ.
1607 *
1608 * And whoever uses polling routines assumes that it manages the device
1609 * (including tx queue), so we're also fine with start_tx()'s caller
1610 * side.
1611 */
9f25bc51
RK		 1612 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1613 REG_IMSC);
5c8124a0
AV		 1614}
1615
e643f87f 1616static int pl011_get_poll_char(struct uart_port *port)
84b5ae15 1617{
a5820c24
DT		 1618 struct uart_amba_port *uap =
1619 container_of(port, struct uart_amba_port, port);
84b5ae15
JW		 1620 unsigned int status;
1621
5c8124a0
AV		 1622 /*
1623 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1624 * debugger.
1625 */
1626 pl011_quiesce_irqs(port);
1627
9f25bc51 1628 status = pl011_read(uap, REG_FR);
f5316b4a
JW		 1629 if (status & UART01x_FR_RXFE)
1630 return NO_POLL_CHAR;
84b5ae15 1631
9f25bc51 1632 return pl011_read(uap, REG_DR);
84b5ae15
JW		 1633}
1634
e643f87f 1635static void pl011_put_poll_char(struct uart_port *port,
84b5ae15
JW		 1636 unsigned char ch)
1637{
a5820c24
DT		 1638 struct uart_amba_port *uap =
1639 container_of(port, struct uart_amba_port, port);
84b5ae15 1640
9f25bc51 1641 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2f2fd089 1642 cpu_relax();
84b5ae15 1643
9f25bc51 1644 pl011_write(ch, uap, REG_DR);
84b5ae15
JW		 1645}
1646
1647#endif /* CONFIG_CONSOLE_POLL */
1648
b3564c2c 1649static int pl011_hwinit(struct uart_port *port)
1da177e4 1650{
a5820c24
DT		 1651 struct uart_amba_port *uap =
1652 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1653 int retval;
1654
78d80c5a 1655 /* Optionaly enable pins to be muxed in and configured */
2b996fc5 1656 pinctrl_pm_select_default_state(port->dev);
78d80c5a 1657
1da177e4
LT		 1658 /*
1659 * Try to enable the clock producer.
1660 */
1c4c4394 1661 retval = clk_prepare_enable(uap->clk);
1da177e4 1662 if (retval)
7f6d942a 1663 return retval;
1da177e4
LT		 1664
1665 uap->port.uartclk = clk_get_rate(uap->clk);
1666
9b96fbac 1667 /* Clear pending error and receive interrupts */
75836339
RK		 1668 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1669 UART011_FEIS | UART011_RTIS | UART011_RXIS,
9f25bc51 1670 uap, REG_ICR);
9b96fbac 1671
b3564c2c
AV		 1672 /*
1673 * Save interrupts enable mask, and enable RX interrupts in case if
1674 * the interrupt is used for NMI entry.
1675 */
9f25bc51
RK		 1676 uap->im = pl011_read(uap, REG_IMSC);
1677 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
b3564c2c 1678
574de559 1679 if (dev_get_platdata(uap->port.dev)) {
b3564c2c
AV		 1680 struct amba_pl011_data *plat;
1681
574de559 1682 plat = dev_get_platdata(uap->port.dev);
b3564c2c
AV		 1683 if (plat->init)
1684 plat->init();
1685 }
1686 return 0;
b3564c2c
AV		 1687}
1688
7fe9a5a9
RK		 1689static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1690{
e4df9a80
RK		 1691 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1692 pl011_reg_to_offset(uap, REG_LCRH_TX);
7fe9a5a9
RK		 1693}
1694
b60f2f66
JM		 1695static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1696{
e4df9a80 1697 pl011_write(lcr_h, uap, REG_LCRH_RX);
7fe9a5a9 1698 if (pl011_split_lcrh(uap)) {
b60f2f66
JM		 1699 int i;
1700 /*
1701 * Wait 10 PCLKs before writing LCRH_TX register,
1702 * to get this delay write read only register 10 times
1703 */
1704 for (i = 0; i < 10; ++i)
9f25bc51 1705 pl011_write(0xff, uap, REG_MIS);
e4df9a80 1706 pl011_write(lcr_h, uap, REG_LCRH_TX);
b60f2f66
JM		 1707 }
1708}
1709
867b8e8e
AP		 1710static int pl011_allocate_irq(struct uart_amba_port *uap)
1711{
9f25bc51 1712 pl011_write(uap->im, uap, REG_IMSC);
867b8e8e
AP		 1713
1714 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1715}
1716
1717/*
1718 * Enable interrupts, only timeouts when using DMA
1719 * if initial RX DMA job failed, start in interrupt mode
1720 * as well.
1721 */
1722static void pl011_enable_interrupts(struct uart_amba_port *uap)
1723{
1724 spin_lock_irq(&uap->port.lock);
1725
1726 /* Clear out any spuriously appearing RX interrupts */
9f25bc51 1727 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
867b8e8e
AP		 1728 uap->im = UART011_RTIM;
1729 if (!pl011_dma_rx_running(uap))
1730 uap->im |= UART011_RXIM;
9f25bc51 1731 pl011_write(uap->im, uap, REG_IMSC);
867b8e8e
AP		 1732 spin_unlock_irq(&uap->port.lock);
1733}
1734
b3564c2c
AV		 1735static int pl011_startup(struct uart_port *port)
1736{
a5820c24
DT		 1737 struct uart_amba_port *uap =
1738 container_of(port, struct uart_amba_port, port);
734745ca 1739 unsigned int cr;
b3564c2c
AV		 1740 int retval;
1741
1742 retval = pl011_hwinit(port);
1743 if (retval)
1744 goto clk_dis;
1745
867b8e8e 1746 retval = pl011_allocate_irq(uap);
1da177e4
LT		 1747 if (retval)
1748 goto clk_dis;
1749
9f25bc51 1750 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1da177e4 1751
734745ca 1752 spin_lock_irq(&uap->port.lock);
570d2910 1753
d8d8ffa4
SKS		 1754 /* restore RTS and DTR */
1755 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1756 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
9f25bc51 1757 pl011_write(cr, uap, REG_CR);
1da177e4 1758
fe433907
JM		 1759 spin_unlock_irq(&uap->port.lock);
1760
1da177e4
LT		 1761 /*
1762 * initialise the old status of the modem signals
1763 */
9f25bc51 1764 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1da177e4 1765
68b65f73
RK		 1766 /* Startup DMA */
1767 pl011_dma_startup(uap);
1768
867b8e8e 1769 pl011_enable_interrupts(uap);
1da177e4
LT		 1770
1771 return 0;
1772
1773 clk_dis:
1c4c4394 1774 clk_disable_unprepare(uap->clk);
1da177e4
LT		 1775 return retval;
1776}
1777
0dd1e247
AP		 1778static int sbsa_uart_startup(struct uart_port *port)
1779{
1780 struct uart_amba_port *uap =
1781 container_of(port, struct uart_amba_port, port);
1782 int retval;
1783
1784 retval = pl011_hwinit(port);
1785 if (retval)
1786 return retval;
1787
1788 retval = pl011_allocate_irq(uap);
1789 if (retval)
1790 return retval;
1791
1792 /* The SBSA UART does not support any modem status lines. */
1793 uap->old_status = 0;
1794
1795 pl011_enable_interrupts(uap);
1796
1797 return 0;
1798}
1799
ec489aa8
LW		 1800static void pl011_shutdown_channel(struct uart_amba_port *uap,
1801 unsigned int lcrh)
1802{
f11c9841 1803 unsigned long val;
ec489aa8 1804
b2a4e24c 1805 val = pl011_read(uap, lcrh);
f11c9841 1806 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
b2a4e24c 1807 pl011_write(val, uap, lcrh);
ec489aa8
LW		 1808}
1809
95166a3f
AP		 1810/*
1811 * disable the port. It should not disable RTS and DTR.
1812 * Also RTS and DTR state should be preserved to restore
1813 * it during startup().
1814 */
1815static void pl011_disable_uart(struct uart_amba_port *uap)
1da177e4 1816{
d8d8ffa4 1817 unsigned int cr;
1da177e4 1818
3b43816f 1819 uap->autorts = false;
fe433907 1820 spin_lock_irq(&uap->port.lock);
9f25bc51 1821 cr = pl011_read(uap, REG_CR);
d8d8ffa4
SKS		 1822 uap->old_cr = cr;
1823 cr &= UART011_CR_RTS | UART011_CR_DTR;
1824 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
9f25bc51 1825 pl011_write(cr, uap, REG_CR);
fe433907 1826 spin_unlock_irq(&uap->port.lock);
1da177e4
LT		 1827
1828 /*
1829 * disable break condition and fifos
1830 */
e4df9a80 1831 pl011_shutdown_channel(uap, REG_LCRH_RX);
7fe9a5a9 1832 if (pl011_split_lcrh(uap))
e4df9a80 1833 pl011_shutdown_channel(uap, REG_LCRH_TX);
95166a3f
AP		 1834}
1835
1836static void pl011_disable_interrupts(struct uart_amba_port *uap)
1837{
1838 spin_lock_irq(&uap->port.lock);
1839
1840 /* mask all interrupts and clear all pending ones */
1841 uap->im = 0;
9f25bc51
RK		 1842 pl011_write(uap->im, uap, REG_IMSC);
1843 pl011_write(0xffff, uap, REG_ICR);
95166a3f
AP		 1844
1845 spin_unlock_irq(&uap->port.lock);
1846}
1847
1848static void pl011_shutdown(struct uart_port *port)
1849{
1850 struct uart_amba_port *uap =
1851 container_of(port, struct uart_amba_port, port);
1852
1853 pl011_disable_interrupts(uap);
1854
1855 pl011_dma_shutdown(uap);
1856
1857 free_irq(uap->port.irq, uap);
1858
1859 pl011_disable_uart(uap);
1da177e4
LT		 1860
1861 /*
1862 * Shut down the clock producer
1863 */
1c4c4394 1864 clk_disable_unprepare(uap->clk);
78d80c5a 1865 /* Optionally let pins go into sleep states */
2b996fc5 1866 pinctrl_pm_select_sleep_state(port->dev);
c16d51a3 1867
574de559 1868 if (dev_get_platdata(uap->port.dev)) {
c16d51a3
SKS		 1869 struct amba_pl011_data *plat;
1870
574de559 1871 plat = dev_get_platdata(uap->port.dev);
c16d51a3
SKS		 1872 if (plat->exit)
1873 plat->exit();
1874 }
1875
36f339d1
PH		 1876 if (uap->port.ops->flush_buffer)
1877 uap->port.ops->flush_buffer(port);
1da177e4
LT		 1878}
1879
0dd1e247
AP		 1880static void sbsa_uart_shutdown(struct uart_port *port)
1881{
1882 struct uart_amba_port *uap =
1883 container_of(port, struct uart_amba_port, port);
1884
1885 pl011_disable_interrupts(uap);
1886
1887 free_irq(uap->port.irq, uap);
1888
1889 if (uap->port.ops->flush_buffer)
1890 uap->port.ops->flush_buffer(port);
1891}
1892
ef5a9358
AP		 1893static void
1894pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1895{
1896 port->read_status_mask = UART011_DR_OE | 255;
1897 if (termios->c_iflag & INPCK)
1898 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1899 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1900 port->read_status_mask |= UART011_DR_BE;
1901
1902 /*
1903 * Characters to ignore
1904 */
1905 port->ignore_status_mask = 0;
1906 if (termios->c_iflag & IGNPAR)
1907 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1908 if (termios->c_iflag & IGNBRK) {
1909 port->ignore_status_mask |= UART011_DR_BE;
1910 /*
1911 * If we're ignoring parity and break indicators,
1912 * ignore overruns too (for real raw support).
1913 */
1914 if (termios->c_iflag & IGNPAR)
1915 port->ignore_status_mask |= UART011_DR_OE;
1916 }
1917
1918 /*
1919 * Ignore all characters if CREAD is not set.
1920 */
1921 if ((termios->c_cflag & CREAD) == 0)
1922 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1923}
1924
1da177e4 1925static void
606d099c
AC		 1926pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1927 struct ktermios *old)
1da177e4 1928{
a5820c24
DT		 1929 struct uart_amba_port *uap =
1930 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1931 unsigned int lcr_h, old_cr;
1932 unsigned long flags;
c19f12b5
RK		 1933 unsigned int baud, quot, clkdiv;
1934
1935 if (uap->vendor->oversampling)
1936 clkdiv = 8;
1937 else
1938 clkdiv = 16;
1da177e4
LT		 1939
1940 /*
1941 * Ask the core to calculate the divisor for us.
1942 */
ac3e3fb4 1943 baud = uart_get_baud_rate(port, termios, old, 0,
c19f12b5 1944 port->uartclk / clkdiv);
89fa28db 1945#ifdef CONFIG_DMA_ENGINE
cb06ff10
CM		 1946 /*
1947 * Adjust RX DMA polling rate with baud rate if not specified.
1948 */
1949 if (uap->dmarx.auto_poll_rate)
1950 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
89fa28db 1951#endif
ac3e3fb4
LW		 1952
1953 if (baud > port->uartclk/16)
1954 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1955 else
1956 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1da177e4
LT		 1957
1958 switch (termios->c_cflag & CSIZE) {
1959 case CS5:
1960 lcr_h = UART01x_LCRH_WLEN_5;
1961 break;
1962 case CS6:
1963 lcr_h = UART01x_LCRH_WLEN_6;
1964 break;
1965 case CS7:
1966 lcr_h = UART01x_LCRH_WLEN_7;
1967 break;
1968 default: // CS8
1969 lcr_h = UART01x_LCRH_WLEN_8;
1970 break;
1971 }
1972 if (termios->c_cflag & CSTOPB)
1973 lcr_h |= UART01x_LCRH_STP2;
1974 if (termios->c_cflag & PARENB) {
1975 lcr_h |= UART01x_LCRH_PEN;
1976 if (!(termios->c_cflag & PARODD))
1977 lcr_h |= UART01x_LCRH_EPS;
bb70002c
ES		 1978 if (termios->c_cflag & CMSPAR)
1979 lcr_h |= UART011_LCRH_SPS;
1da177e4 1980 }
ffca2b11 1981 if (uap->fifosize > 1)
1da177e4
LT		 1982 lcr_h |= UART01x_LCRH_FEN;
1983
1984 spin_lock_irqsave(&port->lock, flags);
1985
1986 /*
1987 * Update the per-port timeout.
1988 */
1989 uart_update_timeout(port, termios->c_cflag, baud);
1990
ef5a9358 1991 pl011_setup_status_masks(port, termios);
1da177e4
LT		 1992
1993 if (UART_ENABLE_MS(port, termios->c_cflag))
1994 pl011_enable_ms(port);
1995
1996 /* first, disable everything */
9f25bc51
RK		 1997 old_cr = pl011_read(uap, REG_CR);
1998 pl011_write(0, uap, REG_CR);
1da177e4 1999
3b43816f
RV		 2000 if (termios->c_cflag & CRTSCTS) {
2001 if (old_cr & UART011_CR_RTS)
2002 old_cr |= UART011_CR_RTSEN;
2003
2004 old_cr |= UART011_CR_CTSEN;
2005 uap->autorts = true;
2006 } else {
2007 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2008 uap->autorts = false;
2009 }
2010
c19f12b5
RK		 2011 if (uap->vendor->oversampling) {
2012 if (baud > port->uartclk / 16)
ac3e3fb4
LW		 2013 old_cr |= ST_UART011_CR_OVSFACT;
2014 else
2015 old_cr &= ~ST_UART011_CR_OVSFACT;
2016 }
2017
c5dd553b
LW		 2018 /*
2019 * Workaround for the ST Micro oversampling variants to
2020 * increase the bitrate slightly, by lowering the divisor,
2021 * to avoid delayed sampling of start bit at high speeds,
2022 * else we see data corruption.
2023 */
2024 if (uap->vendor->oversampling) {
2025 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2026 quot -= 1;
2027 else if ((baud > 3250000) && (quot > 2))
2028 quot -= 2;
2029 }
1da177e4 2030 /* Set baud rate */
9f25bc51
RK		 2031 pl011_write(quot & 0x3f, uap, REG_FBRD);
2032 pl011_write(quot >> 6, uap, REG_IBRD);
1da177e4
LT		 2033
2034 /*
2035 * ----------v----------v----------v----------v-----
e4df9a80 2036 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
9f25bc51 2037 * REG_FBRD & REG_IBRD.
1da177e4
LT		 2038 * ----------^----------^----------^----------^-----
2039 */
b60f2f66 2040 pl011_write_lcr_h(uap, lcr_h);
9f25bc51 2041 pl011_write(old_cr, uap, REG_CR);
1da177e4
LT		 2042
2043 spin_unlock_irqrestore(&port->lock, flags);
2044}
2045
0dd1e247
AP		 2046static void
2047sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2048 struct ktermios *old)
2049{
2050 struct uart_amba_port *uap =
2051 container_of(port, struct uart_amba_port, port);
2052 unsigned long flags;
2053
2054 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2055
2056 /* The SBSA UART only supports 8n1 without hardware flow control. */
2057 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2058 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2059 termios->c_cflag |= CS8 | CLOCAL;
2060
2061 spin_lock_irqsave(&port->lock, flags);
2062 uart_update_timeout(port, CS8, uap->fixed_baud);
2063 pl011_setup_status_masks(port, termios);
2064 spin_unlock_irqrestore(&port->lock, flags);
2065}
2066
1da177e4
LT		 2067static const char *pl011_type(struct uart_port *port)
2068{
a5820c24
DT		 2069 struct uart_amba_port *uap =
2070 container_of(port, struct uart_amba_port, port);
e8a7ba86 2071 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1da177e4
LT		 2072}
2073
2074/*
2075 * Release the memory region(s) being used by 'port'
2076 */
e643f87f 2077static void pl011_release_port(struct uart_port *port)
1da177e4
LT		 2078{
2079 release_mem_region(port->mapbase, SZ_4K);
2080}
2081
2082/*
2083 * Request the memory region(s) being used by 'port'
2084 */
e643f87f 2085static int pl011_request_port(struct uart_port *port)
1da177e4
LT		 2086{
2087 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2088 != NULL ? 0 : -EBUSY;
2089}
2090
2091/*
2092 * Configure/autoconfigure the port.
2093 */
e643f87f 2094static void pl011_config_port(struct uart_port *port, int flags)
1da177e4
LT		 2095{
2096 if (flags & UART_CONFIG_TYPE) {
2097 port->type = PORT_AMBA;
e643f87f 2098 pl011_request_port(port);
1da177e4
LT		 2099 }
2100}
2101
2102/*
2103 * verify the new serial_struct (for TIOCSSERIAL).
2104 */
e643f87f 2105static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1da177e4
LT		 2106{
2107 int ret = 0;
2108 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2109 ret = -EINVAL;
a62c4133 2110 if (ser->irq < 0 || ser->irq >= nr_irqs)
1da177e4
LT		 2111 ret = -EINVAL;
2112 if (ser->baud_base < 9600)
2113 ret = -EINVAL;
2114 return ret;
2115}
2116
2117static struct uart_ops amba_pl011_pops = {
e643f87f 2118 .tx_empty = pl011_tx_empty,
1da177e4 2119 .set_mctrl = pl011_set_mctrl,
e643f87f 2120 .get_mctrl = pl011_get_mctrl,
1da177e4
LT		 2121 .stop_tx = pl011_stop_tx,
2122 .start_tx = pl011_start_tx,
2123 .stop_rx = pl011_stop_rx,
2124 .enable_ms = pl011_enable_ms,
2125 .break_ctl = pl011_break_ctl,
2126 .startup = pl011_startup,
2127 .shutdown = pl011_shutdown,
68b65f73 2128 .flush_buffer = pl011_dma_flush_buffer,
1da177e4
LT		 2129 .set_termios = pl011_set_termios,
2130 .type = pl011_type,
e643f87f
LW		 2131 .release_port = pl011_release_port,
2132 .request_port = pl011_request_port,
2133 .config_port = pl011_config_port,
2134 .verify_port = pl011_verify_port,
84b5ae15 2135#ifdef CONFIG_CONSOLE_POLL
b3564c2c 2136 .poll_init = pl011_hwinit,
e643f87f
LW		 2137 .poll_get_char = pl011_get_poll_char,
2138 .poll_put_char = pl011_put_poll_char,
84b5ae15 2139#endif
1da177e4
LT		 2140};
2141
0dd1e247
AP		 2142static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2143{
2144}
2145
2146static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2147{
2148 return 0;
2149}
2150
2151static const struct uart_ops sbsa_uart_pops = {
2152 .tx_empty = pl011_tx_empty,
2153 .set_mctrl = sbsa_uart_set_mctrl,
2154 .get_mctrl = sbsa_uart_get_mctrl,
2155 .stop_tx = pl011_stop_tx,
2156 .start_tx = pl011_start_tx,
2157 .stop_rx = pl011_stop_rx,
2158 .startup = sbsa_uart_startup,
2159 .shutdown = sbsa_uart_shutdown,
2160 .set_termios = sbsa_uart_set_termios,
2161 .type = pl011_type,
2162 .release_port = pl011_release_port,
2163 .request_port = pl011_request_port,
2164 .config_port = pl011_config_port,
2165 .verify_port = pl011_verify_port,
2166#ifdef CONFIG_CONSOLE_POLL
2167 .poll_init = pl011_hwinit,
2168 .poll_get_char = pl011_get_poll_char,
2169 .poll_put_char = pl011_put_poll_char,
2170#endif
2171};
2172
1da177e4
LT		 2173static struct uart_amba_port *amba_ports[UART_NR];
2174
2175#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2176
d358788f 2177static void pl011_console_putchar(struct uart_port *port, int ch)
1da177e4 2178{
a5820c24
DT		 2179 struct uart_amba_port *uap =
2180 container_of(port, struct uart_amba_port, port);
1da177e4 2181
9f25bc51 2182 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2f2fd089 2183 cpu_relax();
9f25bc51 2184 pl011_write(ch, uap, REG_DR);
1da177e4
LT		 2185}
2186
2187static void
2188pl011_console_write(struct console *co, const char *s, unsigned int count)
2189{
2190 struct uart_amba_port *uap = amba_ports[co->index];
2f2fd089 2191 unsigned int old_cr = 0, new_cr;
ef605fdb
RV		 2192 unsigned long flags;
2193 int locked = 1;
1da177e4
LT		 2194
2195 clk_enable(uap->clk);
2196
ef605fdb
RV		 2197 local_irq_save(flags);
2198 if (uap->port.sysrq)
2199 locked = 0;
2200 else if (oops_in_progress)
2201 locked = spin_trylock(&uap->port.lock);
2202 else
2203 spin_lock(&uap->port.lock);
2204
1da177e4
LT		 2205 /*
2206 * First save the CR then disable the interrupts
2207 */
71eec483 2208 if (!uap->vendor->always_enabled) {
9f25bc51 2209 old_cr = pl011_read(uap, REG_CR);
71eec483
AP		 2210 new_cr = old_cr & ~UART011_CR_CTSEN;
2211 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
9f25bc51 2212 pl011_write(new_cr, uap, REG_CR);
71eec483 2213 }
1da177e4 2214
d358788f 2215 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1da177e4
LT		 2216
2217 /*
2218 * Finally, wait for transmitter to become empty
2219 * and restore the TCR
2220 */
0e125a5f 2221 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
2f2fd089 2222 cpu_relax();
71eec483 2223 if (!uap->vendor->always_enabled)
9f25bc51 2224 pl011_write(old_cr, uap, REG_CR);
1da177e4 2225
ef605fdb
RV		 2226 if (locked)
2227 spin_unlock(&uap->port.lock);
2228 local_irq_restore(flags);
2229
1da177e4
LT		 2230 clk_disable(uap->clk);
2231}
2232
2233static void __init
2234pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2235 int *parity, int *bits)
2236{
9f25bc51 2237 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
1da177e4
LT		 2238 unsigned int lcr_h, ibrd, fbrd;
2239
e4df9a80 2240 lcr_h = pl011_read(uap, REG_LCRH_TX);
1da177e4
LT		 2241
2242 *parity = 'n';
2243 if (lcr_h & UART01x_LCRH_PEN) {
2244 if (lcr_h & UART01x_LCRH_EPS)
2245 *parity = 'e';
2246 else
2247 *parity = 'o';
2248 }
2249
2250 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2251 *bits = 7;
2252 else
2253 *bits = 8;
2254
9f25bc51
RK		 2255 ibrd = pl011_read(uap, REG_IBRD);
2256 fbrd = pl011_read(uap, REG_FBRD);
1da177e4
LT		 2257
2258 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
ac3e3fb4 2259
c19f12b5 2260 if (uap->vendor->oversampling) {
9f25bc51 2261 if (pl011_read(uap, REG_CR)
ac3e3fb4
LW		 2262 & ST_UART011_CR_OVSFACT)
2263 *baud *= 2;
2264 }
1da177e4
LT		 2265 }
2266}
2267
2268static int __init pl011_console_setup(struct console *co, char *options)
2269{
2270 struct uart_amba_port *uap;
2271 int baud = 38400;
2272 int bits = 8;
2273 int parity = 'n';
2274 int flow = 'n';
4b4851c6 2275 int ret;
1da177e4
LT		 2276
2277 /*
2278 * Check whether an invalid uart number has been specified, and
2279 * if so, search for the first available port that does have
2280 * console support.
2281 */
2282 if (co->index >= UART_NR)
2283 co->index = 0;
2284 uap = amba_ports[co->index];
d28122a5
RK		 2285 if (!uap)
2286 return -ENODEV;
1da177e4 2287
78d80c5a 2288 /* Allow pins to be muxed in and configured */
2b996fc5 2289 pinctrl_pm_select_default_state(uap->port.dev);
78d80c5a 2290
4b4851c6
RK		 2291 ret = clk_prepare(uap->clk);
2292 if (ret)
2293 return ret;
2294
574de559 2295 if (dev_get_platdata(uap->port.dev)) {
c16d51a3
SKS		 2296 struct amba_pl011_data *plat;
2297
574de559 2298 plat = dev_get_platdata(uap->port.dev);
c16d51a3
SKS		 2299 if (plat->init)
2300 plat->init();
2301 }
2302
1da177e4
LT		 2303 uap->port.uartclk = clk_get_rate(uap->clk);
2304
cefc2d1d
AP		 2305 if (uap->vendor->fixed_options) {
2306 baud = uap->fixed_baud;
2307 } else {
2308 if (options)
2309 uart_parse_options(options,
2310 &baud, &parity, &bits, &flow);
2311 else
2312 pl011_console_get_options(uap, &baud, &parity, &bits);
2313 }
1da177e4
LT		 2314
2315 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2316}
2317
2d93486c 2318static struct uart_driver amba_reg;
1da177e4
LT		 2319static struct console amba_console = {
2320 .name = "ttyAMA",
2321 .write = pl011_console_write,
2322 .device = uart_console_device,
2323 .setup = pl011_console_setup,
2324 .flags = CON_PRINTBUFFER,
2325 .index = -1,
2326 .data = &amba_reg,
2327};
2328
2329#define AMBA_CONSOLE (&amba_console)
0d3c673e
RH		 2330
2331static void pl011_putc(struct uart_port *port, int c)
2332{
cdf091ca 2333 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2f2fd089 2334 cpu_relax();
3b78fae7
TT		 2335 if (port->iotype == UPIO_MEM32)
2336 writel(c, port->membase + UART01x_DR);
2337 else
2338 writeb(c, port->membase + UART01x_DR);
e06690bf 2339 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2f2fd089 2340 cpu_relax();
0d3c673e
RH		 2341}
2342
2343static void pl011_early_write(struct console *con, const char *s, unsigned n)
2344{
2345 struct earlycon_device *dev = con->data;
2346
2347 uart_console_write(&dev->port, s, n, pl011_putc);
2348}
2349
2350static int __init pl011_early_console_setup(struct earlycon_device *device,
2351 const char *opt)
2352{
2353 if (!device->port.membase)
2354 return -ENODEV;
2355
2356 device->con->write = pl011_early_write;
2357 return 0;
2358}
45e0f0f5 2359OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
0d3c673e 2360
1da177e4
LT		 2361#else
2362#define AMBA_CONSOLE NULL
2363#endif
2364
2365static struct uart_driver amba_reg = {
2366 .owner = THIS_MODULE,
2367 .driver_name = "ttyAMA",
2368 .dev_name = "ttyAMA",
2369 .major = SERIAL_AMBA_MAJOR,
2370 .minor = SERIAL_AMBA_MINOR,
2371 .nr = UART_NR,
2372 .cons = AMBA_CONSOLE,
2373};
2374
32614aad
ML		 2375static int pl011_probe_dt_alias(int index, struct device *dev)
2376{
2377 struct device_node *np;
2378 static bool seen_dev_with_alias = false;
2379 static bool seen_dev_without_alias = false;
2380 int ret = index;
2381
2382 if (!IS_ENABLED(CONFIG_OF))
2383 return ret;
2384
2385 np = dev->of_node;
2386 if (!np)
2387 return ret;
2388
2389 ret = of_alias_get_id(np, "serial");
287980e4 2390 if (ret < 0) {
32614aad
ML		 2391 seen_dev_without_alias = true;
2392 ret = index;
2393 } else {
2394 seen_dev_with_alias = true;
2395 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2396 dev_warn(dev, "requested serial port %d not available.\n", ret);
2397 ret = index;
2398 }
2399 }
2400
2401 if (seen_dev_with_alias && seen_dev_without_alias)
2402 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2403
2404 return ret;
2405}
2406
49bb3c86
AP		 2407/* unregisters the driver also if no more ports are left */
2408static void pl011_unregister_port(struct uart_amba_port *uap)
2409{
2410 int i;
2411 bool busy = false;
2412
2413 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2414 if (amba_ports[i] == uap)
2415 amba_ports[i] = NULL;
2416 else if (amba_ports[i])
2417 busy = true;
2418 }
2419 pl011_dma_remove(uap);
2420 if (!busy)
2421 uart_unregister_driver(&amba_reg);
2422}
2423
3873e2d7 2424static int pl011_find_free_port(void)
1da177e4 2425{
3873e2d7 2426 int i;
1da177e4
LT		 2427
2428 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2429 if (amba_ports[i] == NULL)
3873e2d7 2430 return i;
1da177e4 2431
3873e2d7
AP		 2432 return -EBUSY;
2433}
1da177e4 2434
3873e2d7
AP		 2435static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2436 struct resource *mmiobase, int index)
2437{
2438 void __iomem *base;
32614aad 2439
3873e2d7 2440 base = devm_ioremap_resource(dev, mmiobase);
97a60eac
KK		 2441 if (IS_ERR(base))
2442 return PTR_ERR(base);
1da177e4 2443
3873e2d7 2444 index = pl011_probe_dt_alias(index, dev);
1da177e4 2445
d8d8ffa4 2446 uap->old_cr = 0;
3873e2d7
AP		 2447 uap->port.dev = dev;
2448 uap->port.mapbase = mmiobase->start;
1da177e4 2449 uap->port.membase = base;
ffca2b11 2450 uap->port.fifosize = uap->fifosize;
1da177e4 2451 uap->port.flags = UPF_BOOT_AUTOCONF;
3873e2d7 2452 uap->port.line = index;
1da177e4 2453
3873e2d7 2454 amba_ports[index] = uap;
c3d8b76f 2455
3873e2d7
AP		 2456 return 0;
2457}
e8a7ba86 2458
3873e2d7
AP		 2459static int pl011_register_port(struct uart_amba_port *uap)
2460{
2461 int ret;
1da177e4 2462
3873e2d7 2463 /* Ensure interrupts from this UART are masked and cleared */
9f25bc51
RK		 2464 pl011_write(0, uap, REG_IMSC);
2465 pl011_write(0xffff, uap, REG_ICR);
ef2889f7
TB		 2466
2467 if (!amba_reg.state) {
2468 ret = uart_register_driver(&amba_reg);
2469 if (ret < 0) {
3873e2d7 2470 dev_err(uap->port.dev,
1c9be310 2471 "Failed to register AMBA-PL011 driver\n");
ef2889f7
TB		 2472 return ret;
2473 }
2474 }
2475
1da177e4 2476 ret = uart_add_one_port(&amba_reg, &uap->port);
49bb3c86
AP		 2477 if (ret)
2478 pl011_unregister_port(uap);
7f6d942a 2479
1da177e4
LT		 2480 return ret;
2481}
2482
3873e2d7
AP		 2483static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2484{
2485 struct uart_amba_port *uap;
2486 struct vendor_data *vendor = id->data;
2487 int portnr, ret;
2488
2489 portnr = pl011_find_free_port();
2490 if (portnr < 0)
2491 return portnr;
2492
2493 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2494 GFP_KERNEL);
2495 if (!uap)
2496 return -ENOMEM;
2497
2498 uap->clk = devm_clk_get(&dev->dev, NULL);
2499 if (IS_ERR(uap->clk))
2500 return PTR_ERR(uap->clk);
2501
439403bd 2502 uap->reg_offset = vendor->reg_offset;
3873e2d7 2503 uap->vendor = vendor;
3873e2d7 2504 uap->fifosize = vendor->get_fifosize(dev);
3b78fae7 2505 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
3873e2d7
AP		 2506 uap->port.irq = dev->irq[0];
2507 uap->port.ops = &amba_pl011_pops;
2508
2509 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2510
2511 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2512 if (ret)
2513 return ret;
2514
2515 amba_set_drvdata(dev, uap);
2516
2517 return pl011_register_port(uap);
2518}
2519
1da177e4
LT		 2520static int pl011_remove(struct amba_device *dev)
2521{
2522 struct uart_amba_port *uap = amba_get_drvdata(dev);
1da177e4 2523
1da177e4 2524 uart_remove_one_port(&amba_reg, &uap->port);
49bb3c86 2525 pl011_unregister_port(uap);
1da177e4
LT		 2526 return 0;
2527}
2528
d0ce850d
UH		 2529#ifdef CONFIG_PM_SLEEP
2530static int pl011_suspend(struct device *dev)
b736b89f 2531{
d0ce850d 2532 struct uart_amba_port *uap = dev_get_drvdata(dev);
b736b89f
LC		 2533
2534 if (!uap)
2535 return -EINVAL;
2536
2537 return uart_suspend_port(&amba_reg, &uap->port);
2538}
2539
d0ce850d 2540static int pl011_resume(struct device *dev)
b736b89f 2541{
d0ce850d 2542 struct uart_amba_port *uap = dev_get_drvdata(dev);
b736b89f
LC		 2543
2544 if (!uap)
2545 return -EINVAL;
2546
2547 return uart_resume_port(&amba_reg, &uap->port);
2548}
2549#endif
2550
d0ce850d
UH		 2551static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2552
0dd1e247
AP		 2553static int sbsa_uart_probe(struct platform_device *pdev)
2554{
2555 struct uart_amba_port *uap;
2556 struct resource *r;
2557 int portnr, ret;
2558 int baudrate;
2559
2560 /*
2561 * Check the mandatory baud rate parameter in the DT node early
2562 * so that we can easily exit with the error.
2563 */
2564 if (pdev->dev.of_node) {
2565 struct device_node *np = pdev->dev.of_node;
2566
2567 ret = of_property_read_u32(np, "current-speed", &baudrate);
2568 if (ret)
2569 return ret;
2570 } else {
2571 baudrate = 115200;
2572 }
2573
2574 portnr = pl011_find_free_port();
2575 if (portnr < 0)
2576 return portnr;
2577
2578 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2579 GFP_KERNEL);
2580 if (!uap)
2581 return -ENOMEM;
2582
394a9e2c
JS		 2583 ret = platform_get_irq(pdev, 0);
2584 if (ret < 0) {
35aa33cf
KW		 2585 if (ret != -EPROBE_DEFER)
2586 dev_err(&pdev->dev, "cannot obtain irq\n");
394a9e2c
JS		 2587 return ret;
2588 }
2589 uap->port.irq = ret;
2590
439403bd 2591 uap->reg_offset = vendor_sbsa.reg_offset;
0dd1e247
AP		 2592 uap->vendor = &vendor_sbsa;
2593 uap->fifosize = 32;
3b78fae7 2594 uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM;
0dd1e247
AP		 2595 uap->port.ops = &sbsa_uart_pops;
2596 uap->fixed_baud = baudrate;
2597
2598 snprintf(uap->type, sizeof(uap->type), "SBSA");
2599
2600 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2601
2602 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2603 if (ret)
2604 return ret;
2605
2606 platform_set_drvdata(pdev, uap);
2607
2608 return pl011_register_port(uap);
2609}
2610
2611static int sbsa_uart_remove(struct platform_device *pdev)
2612{
2613 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2614
2615 uart_remove_one_port(&amba_reg, &uap->port);
2616 pl011_unregister_port(uap);
2617 return 0;
2618}
2619
2620static const struct of_device_id sbsa_uart_of_match[] = {
2621 { .compatible = "arm,sbsa-uart", },
2622 {},
2623};
2624MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2625
3db9ab0b
GG		 2626static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2627 { "ARMH0011", 0 },
2628 {},
2629};
2630MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2631
0dd1e247
AP		 2632static struct platform_driver arm_sbsa_uart_platform_driver = {
2633 .probe = sbsa_uart_probe,
2634 .remove = sbsa_uart_remove,
2635 .driver = {
2636 .name = "sbsa-uart",
2637 .of_match_table = of_match_ptr(sbsa_uart_of_match),
3db9ab0b 2638 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
0dd1e247
AP		 2639 },
2640};
2641
2c39c9e1 2642static struct amba_id pl011_ids[] = {
1da177e4
LT		 2643 {
2644 .id = 0x00041011,
2645 .mask = 0x000fffff,
5926a295
AR		 2646 .data = &vendor_arm,
2647 },
2648 {
2649 .id = 0x00380802,
2650 .mask = 0x00ffffff,
2651 .data = &vendor_st,
1da177e4 2652 },
2426fbc7
SG		 2653 {
2654 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2655 .mask = 0x00ffffff,
2656 .data = &vendor_zte,
2657 },
1da177e4
LT		 2658 { 0, 0 },
2659};
2660
60f7a33b
DM		 2661MODULE_DEVICE_TABLE(amba, pl011_ids);
2662
1da177e4
LT		 2663static struct amba_driver pl011_driver = {
2664 .drv = {
2665 .name = "uart-pl011",
d0ce850d 2666 .pm = &pl011_dev_pm_ops,
1da177e4
LT		 2667 },
2668 .id_table = pl011_ids,
2669 .probe = pl011_probe,
2670 .remove = pl011_remove,
2671};
2672
2673static int __init pl011_init(void)
2674{
1da177e4
LT		 2675 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2676
0dd1e247
AP		 2677 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2678 pr_warn("could not register SBSA UART platform driver\n");
062a68a5 2679 return amba_driver_register(&pl011_driver);
1da177e4
LT		 2680}
2681
2682static void __exit pl011_exit(void)
2683{
0dd1e247 2684 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
1da177e4 2685 amba_driver_unregister(&pl011_driver);
1da177e4
LT		 2686}
2687
4dd9e742
AR		 2688/*
2689 * While this can be a module, if builtin it's most likely the console
2690 * So let's leave module_exit but move module_init to an earlier place
2691 */
2692arch_initcall(pl011_init);
1da177e4
LT		 2693module_exit(pl011_exit);
2694
2695MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2696MODULE_DESCRIPTION("ARM AMBA serial port driver");
2697MODULE_LICENSE("GPL");
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