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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for AMBA serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright 1999 ARM Limited | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 8 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
1da177e4 LT |
24 | * This is a generic driver for ARM AMBA-type serial ports. They |
25 | * have a lot of 16550-like features, but are not register compatible. | |
26 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
27 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
28 | * required, these have to be supplied via some other means (eg, GPIO) | |
29 | * and hooked into this driver. | |
30 | */ | |
1da177e4 LT |
31 | |
32 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
33 | #define SUPPORT_SYSRQ | |
34 | #endif | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/ioport.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/console.h> | |
40 | #include <linux/sysrq.h> | |
41 | #include <linux/device.h> | |
42 | #include <linux/tty.h> | |
43 | #include <linux/tty_flip.h> | |
44 | #include <linux/serial_core.h> | |
45 | #include <linux/serial.h> | |
a62c80e5 RK |
46 | #include <linux/amba/bus.h> |
47 | #include <linux/amba/serial.h> | |
f8ce2547 | 48 | #include <linux/clk.h> |
5a0e3ad6 | 49 | #include <linux/slab.h> |
68b65f73 RK |
50 | #include <linux/dmaengine.h> |
51 | #include <linux/dma-mapping.h> | |
52 | #include <linux/scatterlist.h> | |
c16d51a3 | 53 | #include <linux/delay.h> |
1da177e4 LT |
54 | |
55 | #include <asm/io.h> | |
c6b8fdad | 56 | #include <asm/sizes.h> |
1da177e4 LT |
57 | |
58 | #define UART_NR 14 | |
59 | ||
60 | #define SERIAL_AMBA_MAJOR 204 | |
61 | #define SERIAL_AMBA_MINOR 64 | |
62 | #define SERIAL_AMBA_NR UART_NR | |
63 | ||
64 | #define AMBA_ISR_PASS_LIMIT 256 | |
65 | ||
b63d4f0f RK |
66 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
67 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 68 | |
c16d51a3 SKS |
69 | |
70 | #define UART_WA_SAVE_NR 14 | |
71 | ||
72 | static void pl011_lockup_wa(unsigned long data); | |
73 | static const u32 uart_wa_reg[UART_WA_SAVE_NR] = { | |
74 | ST_UART011_DMAWM, | |
75 | ST_UART011_TIMEOUT, | |
76 | ST_UART011_LCRH_RX, | |
77 | UART011_IBRD, | |
78 | UART011_FBRD, | |
79 | ST_UART011_LCRH_TX, | |
80 | UART011_IFLS, | |
81 | ST_UART011_XFCR, | |
82 | ST_UART011_XON1, | |
83 | ST_UART011_XON2, | |
84 | ST_UART011_XOFF1, | |
85 | ST_UART011_XOFF2, | |
86 | UART011_CR, | |
87 | UART011_IMSC | |
88 | }; | |
89 | ||
90 | static u32 uart_wa_regdata[UART_WA_SAVE_NR]; | |
91 | static DECLARE_TASKLET(pl011_lockup_tlet, pl011_lockup_wa, 0); | |
92 | ||
5926a295 AR |
93 | /* There is by now at least one vendor with differing details, so handle it */ |
94 | struct vendor_data { | |
95 | unsigned int ifls; | |
96 | unsigned int fifosize; | |
ec489aa8 LW |
97 | unsigned int lcrh_tx; |
98 | unsigned int lcrh_rx; | |
ac3e3fb4 | 99 | bool oversampling; |
c16d51a3 | 100 | bool interrupt_may_hang; /* vendor-specific */ |
38d62436 | 101 | bool dma_threshold; |
5926a295 AR |
102 | }; |
103 | ||
104 | static struct vendor_data vendor_arm = { | |
105 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
106 | .fifosize = 16, | |
ec489aa8 LW |
107 | .lcrh_tx = UART011_LCRH, |
108 | .lcrh_rx = UART011_LCRH, | |
ac3e3fb4 | 109 | .oversampling = false, |
38d62436 | 110 | .dma_threshold = false, |
5926a295 AR |
111 | }; |
112 | ||
113 | static struct vendor_data vendor_st = { | |
114 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, | |
115 | .fifosize = 64, | |
ec489aa8 LW |
116 | .lcrh_tx = ST_UART011_LCRH_TX, |
117 | .lcrh_rx = ST_UART011_LCRH_RX, | |
ac3e3fb4 | 118 | .oversampling = true, |
c16d51a3 | 119 | .interrupt_may_hang = true, |
38d62436 | 120 | .dma_threshold = true, |
1da177e4 LT |
121 | }; |
122 | ||
c16d51a3 SKS |
123 | static struct uart_amba_port *amba_ports[UART_NR]; |
124 | ||
68b65f73 | 125 | /* Deals with DMA transactions */ |
ead76f32 LW |
126 | |
127 | struct pl011_sgbuf { | |
128 | struct scatterlist sg; | |
129 | char *buf; | |
130 | }; | |
131 | ||
132 | struct pl011_dmarx_data { | |
133 | struct dma_chan *chan; | |
134 | struct completion complete; | |
135 | bool use_buf_b; | |
136 | struct pl011_sgbuf sgbuf_a; | |
137 | struct pl011_sgbuf sgbuf_b; | |
138 | dma_cookie_t cookie; | |
139 | bool running; | |
140 | }; | |
141 | ||
68b65f73 RK |
142 | struct pl011_dmatx_data { |
143 | struct dma_chan *chan; | |
144 | struct scatterlist sg; | |
145 | char *buf; | |
146 | bool queued; | |
147 | }; | |
148 | ||
c19f12b5 RK |
149 | /* |
150 | * We wrap our port structure around the generic uart_port. | |
151 | */ | |
152 | struct uart_amba_port { | |
153 | struct uart_port port; | |
154 | struct clk *clk; | |
155 | const struct vendor_data *vendor; | |
68b65f73 | 156 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
157 | unsigned int im; /* interrupt mask */ |
158 | unsigned int old_status; | |
ffca2b11 | 159 | unsigned int fifosize; /* vendor-specific */ |
c19f12b5 RK |
160 | unsigned int lcrh_tx; /* vendor-specific */ |
161 | unsigned int lcrh_rx; /* vendor-specific */ | |
d8d8ffa4 | 162 | unsigned int old_cr; /* state during shutdown */ |
c19f12b5 RK |
163 | bool autorts; |
164 | char type[12]; | |
c16d51a3 | 165 | bool interrupt_may_hang; /* vendor-specific */ |
68b65f73 RK |
166 | #ifdef CONFIG_DMA_ENGINE |
167 | /* DMA stuff */ | |
ead76f32 LW |
168 | bool using_tx_dma; |
169 | bool using_rx_dma; | |
170 | struct pl011_dmarx_data dmarx; | |
68b65f73 RK |
171 | struct pl011_dmatx_data dmatx; |
172 | #endif | |
173 | }; | |
174 | ||
29772c4e LW |
175 | /* |
176 | * Reads up to 256 characters from the FIFO or until it's empty and | |
177 | * inserts them into the TTY layer. Returns the number of characters | |
178 | * read from the FIFO. | |
179 | */ | |
180 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) | |
181 | { | |
182 | u16 status, ch; | |
183 | unsigned int flag, max_count = 256; | |
184 | int fifotaken = 0; | |
185 | ||
186 | while (max_count--) { | |
187 | status = readw(uap->port.membase + UART01x_FR); | |
188 | if (status & UART01x_FR_RXFE) | |
189 | break; | |
190 | ||
191 | /* Take chars from the FIFO and update status */ | |
192 | ch = readw(uap->port.membase + UART01x_DR) | | |
193 | UART_DUMMY_DR_RX; | |
194 | flag = TTY_NORMAL; | |
195 | uap->port.icount.rx++; | |
196 | fifotaken++; | |
197 | ||
198 | if (unlikely(ch & UART_DR_ERROR)) { | |
199 | if (ch & UART011_DR_BE) { | |
200 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
201 | uap->port.icount.brk++; | |
202 | if (uart_handle_break(&uap->port)) | |
203 | continue; | |
204 | } else if (ch & UART011_DR_PE) | |
205 | uap->port.icount.parity++; | |
206 | else if (ch & UART011_DR_FE) | |
207 | uap->port.icount.frame++; | |
208 | if (ch & UART011_DR_OE) | |
209 | uap->port.icount.overrun++; | |
210 | ||
211 | ch &= uap->port.read_status_mask; | |
212 | ||
213 | if (ch & UART011_DR_BE) | |
214 | flag = TTY_BREAK; | |
215 | else if (ch & UART011_DR_PE) | |
216 | flag = TTY_PARITY; | |
217 | else if (ch & UART011_DR_FE) | |
218 | flag = TTY_FRAME; | |
219 | } | |
220 | ||
221 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) | |
222 | continue; | |
223 | ||
224 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
225 | } | |
226 | ||
227 | return fifotaken; | |
228 | } | |
229 | ||
230 | ||
68b65f73 RK |
231 | /* |
232 | * All the DMA operation mode stuff goes inside this ifdef. | |
233 | * This assumes that you have a generic DMA device interface, | |
234 | * no custom DMA interfaces are supported. | |
235 | */ | |
236 | #ifdef CONFIG_DMA_ENGINE | |
237 | ||
238 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
239 | ||
ead76f32 LW |
240 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
241 | enum dma_data_direction dir) | |
242 | { | |
243 | sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL); | |
244 | if (!sg->buf) | |
245 | return -ENOMEM; | |
246 | ||
247 | sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE); | |
248 | ||
249 | if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) { | |
250 | kfree(sg->buf); | |
251 | return -EINVAL; | |
252 | } | |
253 | return 0; | |
254 | } | |
255 | ||
256 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |
257 | enum dma_data_direction dir) | |
258 | { | |
259 | if (sg->buf) { | |
260 | dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir); | |
261 | kfree(sg->buf); | |
262 | } | |
263 | } | |
264 | ||
68b65f73 RK |
265 | static void pl011_dma_probe_initcall(struct uart_amba_port *uap) |
266 | { | |
267 | /* DMA is the sole user of the platform data right now */ | |
268 | struct amba_pl011_data *plat = uap->port.dev->platform_data; | |
269 | struct dma_slave_config tx_conf = { | |
270 | .dst_addr = uap->port.mapbase + UART01x_DR, | |
271 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 272 | .direction = DMA_MEM_TO_DEV, |
68b65f73 RK |
273 | .dst_maxburst = uap->fifosize >> 1, |
274 | }; | |
275 | struct dma_chan *chan; | |
276 | dma_cap_mask_t mask; | |
277 | ||
278 | /* We need platform data */ | |
279 | if (!plat || !plat->dma_filter) { | |
280 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
281 | return; | |
282 | } | |
283 | ||
ead76f32 | 284 | /* Try to acquire a generic DMA engine slave TX channel */ |
68b65f73 RK |
285 | dma_cap_zero(mask); |
286 | dma_cap_set(DMA_SLAVE, mask); | |
287 | ||
288 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param); | |
289 | if (!chan) { | |
290 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
291 | return; | |
292 | } | |
293 | ||
294 | dmaengine_slave_config(chan, &tx_conf); | |
295 | uap->dmatx.chan = chan; | |
296 | ||
297 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
298 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
299 | |
300 | /* Optionally make use of an RX channel as well */ | |
301 | if (plat->dma_rx_param) { | |
302 | struct dma_slave_config rx_conf = { | |
303 | .src_addr = uap->port.mapbase + UART01x_DR, | |
304 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 305 | .direction = DMA_DEV_TO_MEM, |
ead76f32 LW |
306 | .src_maxburst = uap->fifosize >> 1, |
307 | }; | |
308 | ||
309 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); | |
310 | if (!chan) { | |
311 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
312 | return; | |
313 | } | |
314 | ||
315 | dmaengine_slave_config(chan, &rx_conf); | |
316 | uap->dmarx.chan = chan; | |
317 | ||
318 | dev_info(uap->port.dev, "DMA channel RX %s\n", | |
319 | dma_chan_name(uap->dmarx.chan)); | |
320 | } | |
68b65f73 RK |
321 | } |
322 | ||
323 | #ifndef MODULE | |
324 | /* | |
325 | * Stack up the UARTs and let the above initcall be done at device | |
326 | * initcall time, because the serial driver is called as an arch | |
327 | * initcall, and at this time the DMA subsystem is not yet registered. | |
328 | * At this point the driver will switch over to using DMA where desired. | |
329 | */ | |
330 | struct dma_uap { | |
331 | struct list_head node; | |
332 | struct uart_amba_port *uap; | |
c19f12b5 RK |
333 | }; |
334 | ||
68b65f73 RK |
335 | static LIST_HEAD(pl011_dma_uarts); |
336 | ||
337 | static int __init pl011_dma_initcall(void) | |
338 | { | |
339 | struct list_head *node, *tmp; | |
340 | ||
341 | list_for_each_safe(node, tmp, &pl011_dma_uarts) { | |
342 | struct dma_uap *dmau = list_entry(node, struct dma_uap, node); | |
343 | pl011_dma_probe_initcall(dmau->uap); | |
344 | list_del(node); | |
345 | kfree(dmau); | |
346 | } | |
347 | return 0; | |
348 | } | |
349 | ||
350 | device_initcall(pl011_dma_initcall); | |
351 | ||
352 | static void pl011_dma_probe(struct uart_amba_port *uap) | |
353 | { | |
354 | struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL); | |
355 | if (dmau) { | |
356 | dmau->uap = uap; | |
357 | list_add_tail(&dmau->node, &pl011_dma_uarts); | |
358 | } | |
359 | } | |
360 | #else | |
361 | static void pl011_dma_probe(struct uart_amba_port *uap) | |
362 | { | |
363 | pl011_dma_probe_initcall(uap); | |
364 | } | |
365 | #endif | |
366 | ||
367 | static void pl011_dma_remove(struct uart_amba_port *uap) | |
368 | { | |
369 | /* TODO: remove the initcall if it has not yet executed */ | |
370 | if (uap->dmatx.chan) | |
371 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
372 | if (uap->dmarx.chan) |
373 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
374 | } |
375 | ||
68b65f73 RK |
376 | /* Forward declare this for the refill routine */ |
377 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); | |
378 | ||
379 | /* | |
380 | * The current DMA TX buffer has been sent. | |
381 | * Try to queue up another DMA buffer. | |
382 | */ | |
383 | static void pl011_dma_tx_callback(void *data) | |
384 | { | |
385 | struct uart_amba_port *uap = data; | |
386 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
387 | unsigned long flags; | |
388 | u16 dmacr; | |
389 | ||
390 | spin_lock_irqsave(&uap->port.lock, flags); | |
391 | if (uap->dmatx.queued) | |
392 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
393 | DMA_TO_DEVICE); | |
394 | ||
395 | dmacr = uap->dmacr; | |
396 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
397 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
398 | ||
399 | /* | |
400 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
401 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
402 | * | |
403 | * Note: we need to be careful here of a potential race between DMA | |
404 | * and the rest of the driver - if the driver disables TX DMA while | |
405 | * a TX buffer completing, we must update the tx queued status to | |
406 | * get further refills (hence we check dmacr). | |
407 | */ | |
408 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
409 | uart_circ_empty(&uap->port.state->xmit)) { | |
410 | uap->dmatx.queued = false; | |
411 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
412 | return; | |
413 | } | |
414 | ||
415 | if (pl011_dma_tx_refill(uap) <= 0) { | |
416 | /* | |
417 | * We didn't queue a DMA buffer for some reason, but we | |
418 | * have data pending to be sent. Re-enable the TX IRQ. | |
419 | */ | |
420 | uap->im |= UART011_TXIM; | |
421 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
422 | } | |
423 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
424 | } | |
425 | ||
426 | /* | |
427 | * Try to refill the TX DMA buffer. | |
428 | * Locking: called with port lock held and IRQs disabled. | |
429 | * Returns: | |
430 | * 1 if we queued up a TX DMA buffer. | |
431 | * 0 if we didn't want to handle this by DMA | |
432 | * <0 on error | |
433 | */ | |
434 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
435 | { | |
436 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
437 | struct dma_chan *chan = dmatx->chan; | |
438 | struct dma_device *dma_dev = chan->device; | |
439 | struct dma_async_tx_descriptor *desc; | |
440 | struct circ_buf *xmit = &uap->port.state->xmit; | |
441 | unsigned int count; | |
442 | ||
443 | /* | |
444 | * Try to avoid the overhead involved in using DMA if the | |
445 | * transaction fits in the first half of the FIFO, by using | |
446 | * the standard interrupt handling. This ensures that we | |
447 | * issue a uart_write_wakeup() at the appropriate time. | |
448 | */ | |
449 | count = uart_circ_chars_pending(xmit); | |
450 | if (count < (uap->fifosize >> 1)) { | |
451 | uap->dmatx.queued = false; | |
452 | return 0; | |
453 | } | |
454 | ||
455 | /* | |
456 | * Bodge: don't send the last character by DMA, as this | |
457 | * will prevent XON from notifying us to restart DMA. | |
458 | */ | |
459 | count -= 1; | |
460 | ||
461 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
462 | if (count > PL011_DMA_BUFFER_SIZE) | |
463 | count = PL011_DMA_BUFFER_SIZE; | |
464 | ||
465 | if (xmit->tail < xmit->head) | |
466 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
467 | else { | |
468 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
469 | size_t second = xmit->head; | |
470 | ||
471 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
472 | if (second) | |
473 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
474 | } | |
475 | ||
476 | dmatx->sg.length = count; | |
477 | ||
478 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
479 | uap->dmatx.queued = false; | |
480 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
481 | return -EBUSY; | |
482 | } | |
483 | ||
a485df4b | 484 | desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, |
68b65f73 RK |
485 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
486 | if (!desc) { | |
487 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
488 | uap->dmatx.queued = false; | |
489 | /* | |
490 | * If DMA cannot be used right now, we complete this | |
491 | * transaction via IRQ and let the TTY layer retry. | |
492 | */ | |
493 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
494 | return -EBUSY; | |
495 | } | |
496 | ||
497 | /* Some data to go along to the callback */ | |
498 | desc->callback = pl011_dma_tx_callback; | |
499 | desc->callback_param = uap; | |
500 | ||
501 | /* All errors should happen at prepare time */ | |
502 | dmaengine_submit(desc); | |
503 | ||
504 | /* Fire the DMA transaction */ | |
505 | dma_dev->device_issue_pending(chan); | |
506 | ||
507 | uap->dmacr |= UART011_TXDMAE; | |
508 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
509 | uap->dmatx.queued = true; | |
510 | ||
511 | /* | |
512 | * Now we know that DMA will fire, so advance the ring buffer | |
513 | * with the stuff we just dispatched. | |
514 | */ | |
515 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
516 | uap->port.icount.tx += count; | |
517 | ||
518 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
519 | uart_write_wakeup(&uap->port); | |
520 | ||
521 | return 1; | |
522 | } | |
523 | ||
524 | /* | |
525 | * We received a transmit interrupt without a pending X-char but with | |
526 | * pending characters. | |
527 | * Locking: called with port lock held and IRQs disabled. | |
528 | * Returns: | |
529 | * false if we want to use PIO to transmit | |
530 | * true if we queued a DMA buffer | |
531 | */ | |
532 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
533 | { | |
ead76f32 | 534 | if (!uap->using_tx_dma) |
68b65f73 RK |
535 | return false; |
536 | ||
537 | /* | |
538 | * If we already have a TX buffer queued, but received a | |
539 | * TX interrupt, it will be because we've just sent an X-char. | |
540 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
541 | */ | |
542 | if (uap->dmatx.queued) { | |
543 | uap->dmacr |= UART011_TXDMAE; | |
544 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
545 | uap->im &= ~UART011_TXIM; | |
546 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
547 | return true; | |
548 | } | |
549 | ||
550 | /* | |
551 | * We don't have a TX buffer queued, so try to queue one. | |
25985edc | 552 | * If we successfully queued a buffer, mask the TX IRQ. |
68b65f73 RK |
553 | */ |
554 | if (pl011_dma_tx_refill(uap) > 0) { | |
555 | uap->im &= ~UART011_TXIM; | |
556 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
557 | return true; | |
558 | } | |
559 | return false; | |
560 | } | |
561 | ||
562 | /* | |
563 | * Stop the DMA transmit (eg, due to received XOFF). | |
564 | * Locking: called with port lock held and IRQs disabled. | |
565 | */ | |
566 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
567 | { | |
568 | if (uap->dmatx.queued) { | |
569 | uap->dmacr &= ~UART011_TXDMAE; | |
570 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
571 | } | |
572 | } | |
573 | ||
574 | /* | |
575 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
576 | * character queued for send, try to get that character out ASAP. | |
577 | * Locking: called with port lock held and IRQs disabled. | |
578 | * Returns: | |
579 | * false if we want the TX IRQ to be enabled | |
580 | * true if we have a buffer queued | |
581 | */ | |
582 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
583 | { | |
584 | u16 dmacr; | |
585 | ||
ead76f32 | 586 | if (!uap->using_tx_dma) |
68b65f73 RK |
587 | return false; |
588 | ||
589 | if (!uap->port.x_char) { | |
590 | /* no X-char, try to push chars out in DMA mode */ | |
591 | bool ret = true; | |
592 | ||
593 | if (!uap->dmatx.queued) { | |
594 | if (pl011_dma_tx_refill(uap) > 0) { | |
595 | uap->im &= ~UART011_TXIM; | |
596 | ret = true; | |
597 | } else { | |
598 | uap->im |= UART011_TXIM; | |
599 | ret = false; | |
600 | } | |
601 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
602 | } else if (!(uap->dmacr & UART011_TXDMAE)) { | |
603 | uap->dmacr |= UART011_TXDMAE; | |
604 | writew(uap->dmacr, | |
605 | uap->port.membase + UART011_DMACR); | |
606 | } | |
607 | return ret; | |
608 | } | |
609 | ||
610 | /* | |
611 | * We have an X-char to send. Disable DMA to prevent it loading | |
612 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
613 | */ | |
614 | dmacr = uap->dmacr; | |
615 | uap->dmacr &= ~UART011_TXDMAE; | |
616 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
617 | ||
618 | if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { | |
619 | /* | |
620 | * No space in the FIFO, so enable the transmit interrupt | |
621 | * so we know when there is space. Note that once we've | |
622 | * loaded the character, we should just re-enable DMA. | |
623 | */ | |
624 | return false; | |
625 | } | |
626 | ||
627 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
628 | uap->port.icount.tx++; | |
629 | uap->port.x_char = 0; | |
630 | ||
631 | /* Success - restore the DMA state */ | |
632 | uap->dmacr = dmacr; | |
633 | writew(dmacr, uap->port.membase + UART011_DMACR); | |
634 | ||
635 | return true; | |
636 | } | |
637 | ||
638 | /* | |
639 | * Flush the transmit buffer. | |
640 | * Locking: called with port lock held and IRQs disabled. | |
641 | */ | |
642 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
643 | { | |
644 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
645 | ||
ead76f32 | 646 | if (!uap->using_tx_dma) |
68b65f73 RK |
647 | return; |
648 | ||
649 | /* Avoid deadlock with the DMA engine callback */ | |
650 | spin_unlock(&uap->port.lock); | |
651 | dmaengine_terminate_all(uap->dmatx.chan); | |
652 | spin_lock(&uap->port.lock); | |
653 | if (uap->dmatx.queued) { | |
654 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
655 | DMA_TO_DEVICE); | |
656 | uap->dmatx.queued = false; | |
657 | uap->dmacr &= ~UART011_TXDMAE; | |
658 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
659 | } | |
660 | } | |
661 | ||
ead76f32 LW |
662 | static void pl011_dma_rx_callback(void *data); |
663 | ||
664 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
665 | { | |
666 | struct dma_chan *rxchan = uap->dmarx.chan; | |
667 | struct dma_device *dma_dev; | |
668 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
669 | struct dma_async_tx_descriptor *desc; | |
670 | struct pl011_sgbuf *sgbuf; | |
671 | ||
672 | if (!rxchan) | |
673 | return -EIO; | |
674 | ||
675 | /* Start the RX DMA job */ | |
676 | sgbuf = uap->dmarx.use_buf_b ? | |
677 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
678 | dma_dev = rxchan->device; | |
679 | desc = rxchan->device->device_prep_slave_sg(rxchan, &sgbuf->sg, 1, | |
a485df4b | 680 | DMA_DEV_TO_MEM, |
ead76f32 LW |
681 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
682 | /* | |
683 | * If the DMA engine is busy and cannot prepare a | |
684 | * channel, no big deal, the driver will fall back | |
685 | * to interrupt mode as a result of this error code. | |
686 | */ | |
687 | if (!desc) { | |
688 | uap->dmarx.running = false; | |
689 | dmaengine_terminate_all(rxchan); | |
690 | return -EBUSY; | |
691 | } | |
692 | ||
693 | /* Some data to go along to the callback */ | |
694 | desc->callback = pl011_dma_rx_callback; | |
695 | desc->callback_param = uap; | |
696 | dmarx->cookie = dmaengine_submit(desc); | |
697 | dma_async_issue_pending(rxchan); | |
698 | ||
699 | uap->dmacr |= UART011_RXDMAE; | |
700 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
701 | uap->dmarx.running = true; | |
702 | ||
703 | uap->im &= ~UART011_RXIM; | |
704 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | /* | |
710 | * This is called when either the DMA job is complete, or | |
711 | * the FIFO timeout interrupt occurred. This must be called | |
712 | * with the port spinlock uap->port.lock held. | |
713 | */ | |
714 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
715 | u32 pending, bool use_buf_b, | |
716 | bool readfifo) | |
717 | { | |
718 | struct tty_struct *tty = uap->port.state->port.tty; | |
719 | struct pl011_sgbuf *sgbuf = use_buf_b ? | |
720 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
721 | struct device *dev = uap->dmarx.chan->device->dev; | |
ead76f32 LW |
722 | int dma_count = 0; |
723 | u32 fifotaken = 0; /* only used for vdbg() */ | |
724 | ||
725 | /* Pick everything from the DMA first */ | |
726 | if (pending) { | |
727 | /* Sync in buffer */ | |
728 | dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE); | |
729 | ||
730 | /* | |
731 | * First take all chars in the DMA pipe, then look in the FIFO. | |
732 | * Note that tty_insert_flip_buf() tries to take as many chars | |
733 | * as it can. | |
734 | */ | |
735 | dma_count = tty_insert_flip_string(uap->port.state->port.tty, | |
736 | sgbuf->buf, pending); | |
737 | ||
738 | /* Return buffer to device */ | |
739 | dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE); | |
740 | ||
741 | uap->port.icount.rx += dma_count; | |
742 | if (dma_count < pending) | |
743 | dev_warn(uap->port.dev, | |
744 | "couldn't insert all characters (TTY is full?)\n"); | |
745 | } | |
746 | ||
747 | /* | |
748 | * Only continue with trying to read the FIFO if all DMA chars have | |
749 | * been taken first. | |
750 | */ | |
751 | if (dma_count == pending && readfifo) { | |
752 | /* Clear any error flags */ | |
753 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
754 | uap->port.membase + UART011_ICR); | |
755 | ||
756 | /* | |
757 | * If we read all the DMA'd characters, and we had an | |
29772c4e LW |
758 | * incomplete buffer, that could be due to an rx error, or |
759 | * maybe we just timed out. Read any pending chars and check | |
760 | * the error status. | |
761 | * | |
762 | * Error conditions will only occur in the FIFO, these will | |
763 | * trigger an immediate interrupt and stop the DMA job, so we | |
764 | * will always find the error in the FIFO, never in the DMA | |
765 | * buffer. | |
ead76f32 | 766 | */ |
29772c4e | 767 | fifotaken = pl011_fifo_to_tty(uap); |
ead76f32 LW |
768 | } |
769 | ||
770 | spin_unlock(&uap->port.lock); | |
771 | dev_vdbg(uap->port.dev, | |
772 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
773 | dma_count, fifotaken); | |
774 | tty_flip_buffer_push(tty); | |
775 | spin_lock(&uap->port.lock); | |
776 | } | |
777 | ||
778 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
779 | { | |
780 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
781 | struct dma_chan *rxchan = dmarx->chan; | |
782 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? | |
783 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
784 | size_t pending; | |
785 | struct dma_tx_state state; | |
786 | enum dma_status dmastat; | |
787 | ||
788 | /* | |
789 | * Pause the transfer so we can trust the current counter, | |
790 | * do this before we pause the PL011 block, else we may | |
791 | * overflow the FIFO. | |
792 | */ | |
793 | if (dmaengine_pause(rxchan)) | |
794 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
795 | dmastat = rxchan->device->device_tx_status(rxchan, | |
796 | dmarx->cookie, &state); | |
797 | if (dmastat != DMA_PAUSED) | |
798 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
799 | ||
800 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
801 | uap->dmacr &= ~UART011_RXDMAE; | |
802 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
803 | uap->dmarx.running = false; | |
804 | ||
805 | pending = sgbuf->sg.length - state.residue; | |
806 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
807 | /* Then we terminate the transfer - we now know our residue */ | |
808 | dmaengine_terminate_all(rxchan); | |
809 | ||
810 | /* | |
811 | * This will take the chars we have so far and insert | |
812 | * into the framework. | |
813 | */ | |
814 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
815 | ||
816 | /* Switch buffer & re-trigger DMA job */ | |
817 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
818 | if (pl011_dma_rx_trigger_dma(uap)) { | |
819 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
820 | "fall back to interrupt mode\n"); | |
821 | uap->im |= UART011_RXIM; | |
822 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
823 | } | |
824 | } | |
825 | ||
826 | static void pl011_dma_rx_callback(void *data) | |
827 | { | |
828 | struct uart_amba_port *uap = data; | |
829 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
830 | bool lastbuf = dmarx->use_buf_b; | |
831 | int ret; | |
832 | ||
833 | /* | |
834 | * This completion interrupt occurs typically when the | |
835 | * RX buffer is totally stuffed but no timeout has yet | |
836 | * occurred. When that happens, we just want the RX | |
837 | * routine to flush out the secondary DMA buffer while | |
838 | * we immediately trigger the next DMA job. | |
839 | */ | |
840 | spin_lock_irq(&uap->port.lock); | |
841 | uap->dmarx.running = false; | |
842 | dmarx->use_buf_b = !lastbuf; | |
843 | ret = pl011_dma_rx_trigger_dma(uap); | |
844 | ||
845 | pl011_dma_rx_chars(uap, PL011_DMA_BUFFER_SIZE, lastbuf, false); | |
846 | spin_unlock_irq(&uap->port.lock); | |
847 | /* | |
848 | * Do this check after we picked the DMA chars so we don't | |
849 | * get some IRQ immediately from RX. | |
850 | */ | |
851 | if (ret) { | |
852 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
853 | "fall back to interrupt mode\n"); | |
854 | uap->im |= UART011_RXIM; | |
855 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
856 | } | |
857 | } | |
858 | ||
859 | /* | |
860 | * Stop accepting received characters, when we're shutting down or | |
861 | * suspending this port. | |
862 | * Locking: called with port lock held and IRQs disabled. | |
863 | */ | |
864 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
865 | { | |
866 | /* FIXME. Just disable the DMA enable */ | |
867 | uap->dmacr &= ~UART011_RXDMAE; | |
868 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
869 | } | |
68b65f73 RK |
870 | |
871 | static void pl011_dma_startup(struct uart_amba_port *uap) | |
872 | { | |
ead76f32 LW |
873 | int ret; |
874 | ||
68b65f73 RK |
875 | if (!uap->dmatx.chan) |
876 | return; | |
877 | ||
878 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL); | |
879 | if (!uap->dmatx.buf) { | |
880 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
881 | uap->port.fifosize = uap->fifosize; | |
882 | return; | |
883 | } | |
884 | ||
885 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
886 | ||
887 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
888 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
889 | uap->using_tx_dma = true; |
890 | ||
891 | if (!uap->dmarx.chan) | |
892 | goto skip_rx; | |
893 | ||
894 | /* Allocate and map DMA RX buffers */ | |
895 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
896 | DMA_FROM_DEVICE); | |
897 | if (ret) { | |
898 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
899 | "RX buffer A", ret); | |
900 | goto skip_rx; | |
901 | } | |
68b65f73 | 902 | |
ead76f32 LW |
903 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
904 | DMA_FROM_DEVICE); | |
905 | if (ret) { | |
906 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
907 | "RX buffer B", ret); | |
908 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
909 | DMA_FROM_DEVICE); | |
910 | goto skip_rx; | |
911 | } | |
912 | ||
913 | uap->using_rx_dma = true; | |
68b65f73 | 914 | |
ead76f32 | 915 | skip_rx: |
68b65f73 RK |
916 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
917 | uap->dmacr |= UART011_DMAONERR; | |
918 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
38d62436 RK |
919 | |
920 | /* | |
921 | * ST Micro variants has some specific dma burst threshold | |
922 | * compensation. Set this to 16 bytes, so burst will only | |
923 | * be issued above/below 16 bytes. | |
924 | */ | |
925 | if (uap->vendor->dma_threshold) | |
926 | writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, | |
927 | uap->port.membase + ST_UART011_DMAWM); | |
ead76f32 LW |
928 | |
929 | if (uap->using_rx_dma) { | |
930 | if (pl011_dma_rx_trigger_dma(uap)) | |
931 | dev_dbg(uap->port.dev, "could not trigger initial " | |
932 | "RX DMA job, fall back to interrupt mode\n"); | |
933 | } | |
68b65f73 RK |
934 | } |
935 | ||
936 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
937 | { | |
ead76f32 | 938 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
939 | return; |
940 | ||
941 | /* Disable RX and TX DMA */ | |
942 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
943 | barrier(); | |
944 | ||
945 | spin_lock_irq(&uap->port.lock); | |
946 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
947 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
948 | spin_unlock_irq(&uap->port.lock); | |
949 | ||
ead76f32 LW |
950 | if (uap->using_tx_dma) { |
951 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
952 | dmaengine_terminate_all(uap->dmatx.chan); | |
953 | if (uap->dmatx.queued) { | |
954 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
955 | DMA_TO_DEVICE); | |
956 | uap->dmatx.queued = false; | |
957 | } | |
958 | ||
959 | kfree(uap->dmatx.buf); | |
960 | uap->using_tx_dma = false; | |
68b65f73 RK |
961 | } |
962 | ||
ead76f32 LW |
963 | if (uap->using_rx_dma) { |
964 | dmaengine_terminate_all(uap->dmarx.chan); | |
965 | /* Clean up the RX DMA */ | |
966 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); | |
967 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); | |
968 | uap->using_rx_dma = false; | |
969 | } | |
970 | } | |
68b65f73 | 971 | |
ead76f32 LW |
972 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
973 | { | |
974 | return uap->using_rx_dma; | |
68b65f73 RK |
975 | } |
976 | ||
ead76f32 LW |
977 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
978 | { | |
979 | return uap->using_rx_dma && uap->dmarx.running; | |
980 | } | |
981 | ||
982 | ||
68b65f73 RK |
983 | #else |
984 | /* Blank functions if the DMA engine is not available */ | |
985 | static inline void pl011_dma_probe(struct uart_amba_port *uap) | |
986 | { | |
987 | } | |
988 | ||
989 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
990 | { | |
991 | } | |
992 | ||
993 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
994 | { | |
995 | } | |
996 | ||
997 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
998 | { | |
999 | } | |
1000 | ||
1001 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
1002 | { | |
1003 | return false; | |
1004 | } | |
1005 | ||
1006 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
1007 | { | |
1008 | } | |
1009 | ||
1010 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
1011 | { | |
1012 | return false; | |
1013 | } | |
1014 | ||
ead76f32 LW |
1015 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
1016 | { | |
1017 | } | |
1018 | ||
1019 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1020 | { | |
1021 | } | |
1022 | ||
1023 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
1024 | { | |
1025 | return -EIO; | |
1026 | } | |
1027 | ||
1028 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
1029 | { | |
1030 | return false; | |
1031 | } | |
1032 | ||
1033 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
1034 | { | |
1035 | return false; | |
1036 | } | |
1037 | ||
68b65f73 RK |
1038 | #define pl011_dma_flush_buffer NULL |
1039 | #endif | |
1040 | ||
1041 | ||
c16d51a3 SKS |
1042 | /* |
1043 | * pl011_lockup_wa | |
1044 | * This workaround aims to break the deadlock situation | |
1045 | * when after long transfer over uart in hardware flow | |
1046 | * control, uart interrupt registers cannot be cleared. | |
1047 | * Hence uart transfer gets blocked. | |
1048 | * | |
1049 | * It is seen that during such deadlock condition ICR | |
1050 | * don't get cleared even on multiple write. This leads | |
1051 | * pass_counter to decrease and finally reach zero. This | |
1052 | * can be taken as trigger point to run this UART_BT_WA. | |
1053 | * | |
1054 | */ | |
1055 | static void pl011_lockup_wa(unsigned long data) | |
1056 | { | |
1057 | struct uart_amba_port *uap = amba_ports[0]; | |
1058 | void __iomem *base = uap->port.membase; | |
1059 | struct circ_buf *xmit = &uap->port.state->xmit; | |
1060 | struct tty_struct *tty = uap->port.state->port.tty; | |
1061 | int buf_empty_retries = 200; | |
1062 | int loop; | |
1063 | ||
1064 | /* Stop HCI layer from submitting data for tx */ | |
1065 | tty->hw_stopped = 1; | |
1066 | while (!uart_circ_empty(xmit)) { | |
1067 | if (buf_empty_retries-- == 0) | |
1068 | break; | |
1069 | udelay(100); | |
1070 | } | |
1071 | ||
1072 | /* Backup registers */ | |
1073 | for (loop = 0; loop < UART_WA_SAVE_NR; loop++) | |
1074 | uart_wa_regdata[loop] = readl(base + uart_wa_reg[loop]); | |
1075 | ||
1076 | /* Disable UART so that FIFO data is flushed out */ | |
1077 | writew(0x00, uap->port.membase + UART011_CR); | |
1078 | ||
1079 | /* Soft reset UART module */ | |
1080 | if (uap->port.dev->platform_data) { | |
1081 | struct amba_pl011_data *plat; | |
1082 | ||
1083 | plat = uap->port.dev->platform_data; | |
1084 | if (plat->reset) | |
1085 | plat->reset(); | |
1086 | } | |
1087 | ||
1088 | /* Restore registers */ | |
1089 | for (loop = 0; loop < UART_WA_SAVE_NR; loop++) | |
1090 | writew(uart_wa_regdata[loop] , | |
1091 | uap->port.membase + uart_wa_reg[loop]); | |
1092 | ||
1093 | /* Initialise the old status of the modem signals */ | |
1094 | uap->old_status = readw(uap->port.membase + UART01x_FR) & | |
1095 | UART01x_FR_MODEM_ANY; | |
1096 | ||
1097 | if (readl(base + UART011_MIS) & 0x2) | |
1098 | printk(KERN_EMERG "UART_BT_WA: ***FAILED***\n"); | |
1099 | ||
1100 | /* Start Tx/Rx */ | |
1101 | tty->hw_stopped = 0; | |
1102 | } | |
1103 | ||
b129a8cc | 1104 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 LT |
1105 | { |
1106 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1107 | ||
1108 | uap->im &= ~UART011_TXIM; | |
1109 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
68b65f73 | 1110 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
1111 | } |
1112 | ||
b129a8cc | 1113 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 LT |
1114 | { |
1115 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1116 | ||
68b65f73 RK |
1117 | if (!pl011_dma_tx_start(uap)) { |
1118 | uap->im |= UART011_TXIM; | |
1119 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1120 | } | |
1da177e4 LT |
1121 | } |
1122 | ||
1123 | static void pl011_stop_rx(struct uart_port *port) | |
1124 | { | |
1125 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1126 | ||
1127 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
1128 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
1129 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
ead76f32 LW |
1130 | |
1131 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1132 | } |
1133 | ||
1134 | static void pl011_enable_ms(struct uart_port *port) | |
1135 | { | |
1136 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1137 | ||
1138 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
1139 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1140 | } | |
1141 | ||
7d12e780 | 1142 | static void pl011_rx_chars(struct uart_amba_port *uap) |
1da177e4 | 1143 | { |
ebd2c8f6 | 1144 | struct tty_struct *tty = uap->port.state->port.tty; |
1da177e4 | 1145 | |
29772c4e | 1146 | pl011_fifo_to_tty(uap); |
1da177e4 | 1147 | |
2389b272 | 1148 | spin_unlock(&uap->port.lock); |
1da177e4 | 1149 | tty_flip_buffer_push(tty); |
ead76f32 LW |
1150 | /* |
1151 | * If we were temporarily out of DMA mode for a while, | |
1152 | * attempt to switch back to DMA mode again. | |
1153 | */ | |
1154 | if (pl011_dma_rx_available(uap)) { | |
1155 | if (pl011_dma_rx_trigger_dma(uap)) { | |
1156 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " | |
1157 | "fall back to interrupt mode again\n"); | |
1158 | uap->im |= UART011_RXIM; | |
1159 | } else | |
1160 | uap->im &= ~UART011_RXIM; | |
1161 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1162 | } | |
2389b272 | 1163 | spin_lock(&uap->port.lock); |
1da177e4 LT |
1164 | } |
1165 | ||
1166 | static void pl011_tx_chars(struct uart_amba_port *uap) | |
1167 | { | |
ebd2c8f6 | 1168 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
1169 | int count; |
1170 | ||
1171 | if (uap->port.x_char) { | |
1172 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
1173 | uap->port.icount.tx++; | |
1174 | uap->port.x_char = 0; | |
1175 | return; | |
1176 | } | |
1177 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1178 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1179 | return; |
1180 | } | |
1181 | ||
68b65f73 RK |
1182 | /* If we are using DMA mode, try to send some characters. */ |
1183 | if (pl011_dma_tx_irq(uap)) | |
1184 | return; | |
1185 | ||
ffca2b11 | 1186 | count = uap->fifosize >> 1; |
1da177e4 LT |
1187 | do { |
1188 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); | |
1189 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1190 | uap->port.icount.tx++; | |
1191 | if (uart_circ_empty(xmit)) | |
1192 | break; | |
1193 | } while (--count > 0); | |
1194 | ||
1195 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1196 | uart_write_wakeup(&uap->port); | |
1197 | ||
1198 | if (uart_circ_empty(xmit)) | |
b129a8cc | 1199 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1200 | } |
1201 | ||
1202 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1203 | { | |
1204 | unsigned int status, delta; | |
1205 | ||
1206 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1207 | ||
1208 | delta = status ^ uap->old_status; | |
1209 | uap->old_status = status; | |
1210 | ||
1211 | if (!delta) | |
1212 | return; | |
1213 | ||
1214 | if (delta & UART01x_FR_DCD) | |
1215 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1216 | ||
1217 | if (delta & UART01x_FR_DSR) | |
1218 | uap->port.icount.dsr++; | |
1219 | ||
1220 | if (delta & UART01x_FR_CTS) | |
1221 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
1222 | ||
bdc04e31 | 1223 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1224 | } |
1225 | ||
7d12e780 | 1226 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1227 | { |
1228 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1229 | unsigned long flags; |
1da177e4 LT |
1230 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
1231 | int handled = 0; | |
1232 | ||
963cc981 | 1233 | spin_lock_irqsave(&uap->port.lock, flags); |
1da177e4 LT |
1234 | |
1235 | status = readw(uap->port.membase + UART011_MIS); | |
1236 | if (status) { | |
1237 | do { | |
1238 | writew(status & ~(UART011_TXIS|UART011_RTIS| | |
1239 | UART011_RXIS), | |
1240 | uap->port.membase + UART011_ICR); | |
1241 | ||
ead76f32 LW |
1242 | if (status & (UART011_RTIS|UART011_RXIS)) { |
1243 | if (pl011_dma_rx_running(uap)) | |
1244 | pl011_dma_rx_irq(uap); | |
1245 | else | |
1246 | pl011_rx_chars(uap); | |
1247 | } | |
1da177e4 LT |
1248 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1249 | UART011_CTSMIS|UART011_RIMIS)) | |
1250 | pl011_modem_status(uap); | |
1251 | if (status & UART011_TXIS) | |
1252 | pl011_tx_chars(uap); | |
1253 | ||
c16d51a3 SKS |
1254 | if (pass_counter-- == 0) { |
1255 | if (uap->interrupt_may_hang) | |
1256 | tasklet_schedule(&pl011_lockup_tlet); | |
1da177e4 | 1257 | break; |
c16d51a3 | 1258 | } |
1da177e4 LT |
1259 | |
1260 | status = readw(uap->port.membase + UART011_MIS); | |
1261 | } while (status != 0); | |
1262 | handled = 1; | |
1263 | } | |
1264 | ||
963cc981 | 1265 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
1266 | |
1267 | return IRQ_RETVAL(handled); | |
1268 | } | |
1269 | ||
1270 | static unsigned int pl01x_tx_empty(struct uart_port *port) | |
1271 | { | |
1272 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1273 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1274 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
1275 | } | |
1276 | ||
1277 | static unsigned int pl01x_get_mctrl(struct uart_port *port) | |
1278 | { | |
1279 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1280 | unsigned int result = 0; | |
1281 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1282 | ||
5159f407 | 1283 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
1284 | if (status & uartbit) \ |
1285 | result |= tiocmbit | |
1286 | ||
5159f407 JS |
1287 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
1288 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); | |
1289 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
1290 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
1291 | #undef TIOCMBIT | |
1da177e4 LT |
1292 | return result; |
1293 | } | |
1294 | ||
1295 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1296 | { | |
1297 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1298 | unsigned int cr; | |
1299 | ||
1300 | cr = readw(uap->port.membase + UART011_CR); | |
1301 | ||
5159f407 | 1302 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
1303 | if (mctrl & tiocmbit) \ |
1304 | cr |= uartbit; \ | |
1305 | else \ | |
1306 | cr &= ~uartbit | |
1307 | ||
5159f407 JS |
1308 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
1309 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
1310 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
1311 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
1312 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
1313 | |
1314 | if (uap->autorts) { | |
1315 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
1316 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
1317 | } | |
5159f407 | 1318 | #undef TIOCMBIT |
1da177e4 LT |
1319 | |
1320 | writew(cr, uap->port.membase + UART011_CR); | |
1321 | } | |
1322 | ||
1323 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1324 | { | |
1325 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1326 | unsigned long flags; | |
1327 | unsigned int lcr_h; | |
1328 | ||
1329 | spin_lock_irqsave(&uap->port.lock, flags); | |
ec489aa8 | 1330 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1331 | if (break_state == -1) |
1332 | lcr_h |= UART01x_LCRH_BRK; | |
1333 | else | |
1334 | lcr_h &= ~UART01x_LCRH_BRK; | |
ec489aa8 | 1335 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1336 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1337 | } | |
1338 | ||
84b5ae15 JW |
1339 | #ifdef CONFIG_CONSOLE_POLL |
1340 | static int pl010_get_poll_char(struct uart_port *port) | |
1341 | { | |
1342 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1343 | unsigned int status; | |
1344 | ||
f5316b4a JW |
1345 | status = readw(uap->port.membase + UART01x_FR); |
1346 | if (status & UART01x_FR_RXFE) | |
1347 | return NO_POLL_CHAR; | |
84b5ae15 JW |
1348 | |
1349 | return readw(uap->port.membase + UART01x_DR); | |
1350 | } | |
1351 | ||
1352 | static void pl010_put_poll_char(struct uart_port *port, | |
1353 | unsigned char ch) | |
1354 | { | |
1355 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1356 | ||
1357 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) | |
1358 | barrier(); | |
1359 | ||
1360 | writew(ch, uap->port.membase + UART01x_DR); | |
1361 | } | |
1362 | ||
1363 | #endif /* CONFIG_CONSOLE_POLL */ | |
1364 | ||
1da177e4 LT |
1365 | static int pl011_startup(struct uart_port *port) |
1366 | { | |
1367 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1368 | unsigned int cr; | |
1369 | int retval; | |
1370 | ||
4b4851c6 RK |
1371 | retval = clk_prepare(uap->clk); |
1372 | if (retval) | |
1373 | goto out; | |
1374 | ||
1da177e4 LT |
1375 | /* |
1376 | * Try to enable the clock producer. | |
1377 | */ | |
1378 | retval = clk_enable(uap->clk); | |
1379 | if (retval) | |
4b4851c6 | 1380 | goto clk_unprep; |
1da177e4 LT |
1381 | |
1382 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1383 | ||
1384 | /* | |
1385 | * Allocate the IRQ | |
1386 | */ | |
1387 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
1388 | if (retval) | |
1389 | goto clk_dis; | |
1390 | ||
c19f12b5 | 1391 | writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); |
1da177e4 LT |
1392 | |
1393 | /* | |
1394 | * Provoke TX FIFO interrupt into asserting. | |
1395 | */ | |
1396 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; | |
1397 | writew(cr, uap->port.membase + UART011_CR); | |
1398 | writew(0, uap->port.membase + UART011_FBRD); | |
1399 | writew(1, uap->port.membase + UART011_IBRD); | |
ec489aa8 LW |
1400 | writew(0, uap->port.membase + uap->lcrh_rx); |
1401 | if (uap->lcrh_tx != uap->lcrh_rx) { | |
1402 | int i; | |
1403 | /* | |
1404 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1405 | * to get this delay write read only register 10 times | |
1406 | */ | |
1407 | for (i = 0; i < 10; ++i) | |
1408 | writew(0xff, uap->port.membase + UART011_MIS); | |
1409 | writew(0, uap->port.membase + uap->lcrh_tx); | |
1410 | } | |
1da177e4 LT |
1411 | writew(0, uap->port.membase + UART01x_DR); |
1412 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
1413 | barrier(); | |
1414 | ||
d8d8ffa4 SKS |
1415 | /* restore RTS and DTR */ |
1416 | cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); | |
1417 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
1da177e4 LT |
1418 | writew(cr, uap->port.membase + UART011_CR); |
1419 | ||
5063e2c5 RK |
1420 | /* Clear pending error interrupts */ |
1421 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
1422 | uap->port.membase + UART011_ICR); | |
1423 | ||
1da177e4 LT |
1424 | /* |
1425 | * initialise the old status of the modem signals | |
1426 | */ | |
1427 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1428 | ||
68b65f73 RK |
1429 | /* Startup DMA */ |
1430 | pl011_dma_startup(uap); | |
1431 | ||
1da177e4 | 1432 | /* |
ead76f32 LW |
1433 | * Finally, enable interrupts, only timeouts when using DMA |
1434 | * if initial RX DMA job failed, start in interrupt mode | |
1435 | * as well. | |
1da177e4 LT |
1436 | */ |
1437 | spin_lock_irq(&uap->port.lock); | |
ead76f32 LW |
1438 | uap->im = UART011_RTIM; |
1439 | if (!pl011_dma_rx_running(uap)) | |
1440 | uap->im |= UART011_RXIM; | |
1da177e4 LT |
1441 | writew(uap->im, uap->port.membase + UART011_IMSC); |
1442 | spin_unlock_irq(&uap->port.lock); | |
1443 | ||
c16d51a3 SKS |
1444 | if (uap->port.dev->platform_data) { |
1445 | struct amba_pl011_data *plat; | |
1446 | ||
1447 | plat = uap->port.dev->platform_data; | |
1448 | if (plat->init) | |
1449 | plat->init(); | |
1450 | } | |
1451 | ||
1da177e4 LT |
1452 | return 0; |
1453 | ||
1454 | clk_dis: | |
1455 | clk_disable(uap->clk); | |
4b4851c6 RK |
1456 | clk_unprep: |
1457 | clk_unprepare(uap->clk); | |
1da177e4 LT |
1458 | out: |
1459 | return retval; | |
1460 | } | |
1461 | ||
ec489aa8 LW |
1462 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
1463 | unsigned int lcrh) | |
1464 | { | |
1465 | unsigned long val; | |
1466 | ||
1467 | val = readw(uap->port.membase + lcrh); | |
1468 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
1469 | writew(val, uap->port.membase + lcrh); | |
1470 | } | |
1471 | ||
1da177e4 LT |
1472 | static void pl011_shutdown(struct uart_port *port) |
1473 | { | |
1474 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
d8d8ffa4 | 1475 | unsigned int cr; |
1da177e4 LT |
1476 | |
1477 | /* | |
1478 | * disable all interrupts | |
1479 | */ | |
1480 | spin_lock_irq(&uap->port.lock); | |
1481 | uap->im = 0; | |
1482 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1483 | writew(0xffff, uap->port.membase + UART011_ICR); | |
1484 | spin_unlock_irq(&uap->port.lock); | |
1485 | ||
68b65f73 RK |
1486 | pl011_dma_shutdown(uap); |
1487 | ||
1da177e4 LT |
1488 | /* |
1489 | * Free the interrupt | |
1490 | */ | |
1491 | free_irq(uap->port.irq, uap); | |
1492 | ||
1493 | /* | |
1494 | * disable the port | |
d8d8ffa4 SKS |
1495 | * disable the port. It should not disable RTS and DTR. |
1496 | * Also RTS and DTR state should be preserved to restore | |
1497 | * it during startup(). | |
1da177e4 | 1498 | */ |
3b43816f | 1499 | uap->autorts = false; |
d8d8ffa4 SKS |
1500 | cr = readw(uap->port.membase + UART011_CR); |
1501 | uap->old_cr = cr; | |
1502 | cr &= UART011_CR_RTS | UART011_CR_DTR; | |
1503 | cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1504 | writew(cr, uap->port.membase + UART011_CR); | |
1da177e4 LT |
1505 | |
1506 | /* | |
1507 | * disable break condition and fifos | |
1508 | */ | |
ec489aa8 LW |
1509 | pl011_shutdown_channel(uap, uap->lcrh_rx); |
1510 | if (uap->lcrh_rx != uap->lcrh_tx) | |
1511 | pl011_shutdown_channel(uap, uap->lcrh_tx); | |
1da177e4 LT |
1512 | |
1513 | /* | |
1514 | * Shut down the clock producer | |
1515 | */ | |
1516 | clk_disable(uap->clk); | |
4b4851c6 | 1517 | clk_unprepare(uap->clk); |
c16d51a3 SKS |
1518 | |
1519 | if (uap->port.dev->platform_data) { | |
1520 | struct amba_pl011_data *plat; | |
1521 | ||
1522 | plat = uap->port.dev->platform_data; | |
1523 | if (plat->exit) | |
1524 | plat->exit(); | |
1525 | } | |
1526 | ||
1da177e4 LT |
1527 | } |
1528 | ||
1529 | static void | |
606d099c AC |
1530 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1531 | struct ktermios *old) | |
1da177e4 | 1532 | { |
3b43816f | 1533 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 LT |
1534 | unsigned int lcr_h, old_cr; |
1535 | unsigned long flags; | |
c19f12b5 RK |
1536 | unsigned int baud, quot, clkdiv; |
1537 | ||
1538 | if (uap->vendor->oversampling) | |
1539 | clkdiv = 8; | |
1540 | else | |
1541 | clkdiv = 16; | |
1da177e4 LT |
1542 | |
1543 | /* | |
1544 | * Ask the core to calculate the divisor for us. | |
1545 | */ | |
ac3e3fb4 | 1546 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1547 | port->uartclk / clkdiv); |
ac3e3fb4 LW |
1548 | |
1549 | if (baud > port->uartclk/16) | |
1550 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1551 | else | |
1552 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1553 | |
1554 | switch (termios->c_cflag & CSIZE) { | |
1555 | case CS5: | |
1556 | lcr_h = UART01x_LCRH_WLEN_5; | |
1557 | break; | |
1558 | case CS6: | |
1559 | lcr_h = UART01x_LCRH_WLEN_6; | |
1560 | break; | |
1561 | case CS7: | |
1562 | lcr_h = UART01x_LCRH_WLEN_7; | |
1563 | break; | |
1564 | default: // CS8 | |
1565 | lcr_h = UART01x_LCRH_WLEN_8; | |
1566 | break; | |
1567 | } | |
1568 | if (termios->c_cflag & CSTOPB) | |
1569 | lcr_h |= UART01x_LCRH_STP2; | |
1570 | if (termios->c_cflag & PARENB) { | |
1571 | lcr_h |= UART01x_LCRH_PEN; | |
1572 | if (!(termios->c_cflag & PARODD)) | |
1573 | lcr_h |= UART01x_LCRH_EPS; | |
1574 | } | |
ffca2b11 | 1575 | if (uap->fifosize > 1) |
1da177e4 LT |
1576 | lcr_h |= UART01x_LCRH_FEN; |
1577 | ||
1578 | spin_lock_irqsave(&port->lock, flags); | |
1579 | ||
1580 | /* | |
1581 | * Update the per-port timeout. | |
1582 | */ | |
1583 | uart_update_timeout(port, termios->c_cflag, baud); | |
1584 | ||
b63d4f0f | 1585 | port->read_status_mask = UART011_DR_OE | 255; |
1da177e4 | 1586 | if (termios->c_iflag & INPCK) |
b63d4f0f | 1587 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1588 | if (termios->c_iflag & (BRKINT | PARMRK)) |
b63d4f0f | 1589 | port->read_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1590 | |
1591 | /* | |
1592 | * Characters to ignore | |
1593 | */ | |
1594 | port->ignore_status_mask = 0; | |
1595 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1596 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1597 | if (termios->c_iflag & IGNBRK) { |
b63d4f0f | 1598 | port->ignore_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1599 | /* |
1600 | * If we're ignoring parity and break indicators, | |
1601 | * ignore overruns too (for real raw support). | |
1602 | */ | |
1603 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1604 | port->ignore_status_mask |= UART011_DR_OE; |
1da177e4 LT |
1605 | } |
1606 | ||
1607 | /* | |
1608 | * Ignore all characters if CREAD is not set. | |
1609 | */ | |
1610 | if ((termios->c_cflag & CREAD) == 0) | |
b63d4f0f | 1611 | port->ignore_status_mask |= UART_DUMMY_DR_RX; |
1da177e4 LT |
1612 | |
1613 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1614 | pl011_enable_ms(port); | |
1615 | ||
1616 | /* first, disable everything */ | |
1617 | old_cr = readw(port->membase + UART011_CR); | |
1618 | writew(0, port->membase + UART011_CR); | |
1619 | ||
3b43816f RV |
1620 | if (termios->c_cflag & CRTSCTS) { |
1621 | if (old_cr & UART011_CR_RTS) | |
1622 | old_cr |= UART011_CR_RTSEN; | |
1623 | ||
1624 | old_cr |= UART011_CR_CTSEN; | |
1625 | uap->autorts = true; | |
1626 | } else { | |
1627 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1628 | uap->autorts = false; | |
1629 | } | |
1630 | ||
c19f12b5 RK |
1631 | if (uap->vendor->oversampling) { |
1632 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1633 | old_cr |= ST_UART011_CR_OVSFACT; |
1634 | else | |
1635 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1636 | } | |
1637 | ||
1da177e4 LT |
1638 | /* Set baud rate */ |
1639 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
1640 | writew(quot >> 6, port->membase + UART011_IBRD); | |
1641 | ||
1642 | /* | |
1643 | * ----------v----------v----------v----------v----- | |
1644 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L | |
1645 | * ----------^----------^----------^----------^----- | |
1646 | */ | |
ec489aa8 LW |
1647 | writew(lcr_h, port->membase + uap->lcrh_rx); |
1648 | if (uap->lcrh_rx != uap->lcrh_tx) { | |
1649 | int i; | |
1650 | /* | |
1651 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1652 | * to get this delay write read only register 10 times | |
1653 | */ | |
1654 | for (i = 0; i < 10; ++i) | |
1655 | writew(0xff, uap->port.membase + UART011_MIS); | |
1656 | writew(lcr_h, port->membase + uap->lcrh_tx); | |
1657 | } | |
1da177e4 LT |
1658 | writew(old_cr, port->membase + UART011_CR); |
1659 | ||
1660 | spin_unlock_irqrestore(&port->lock, flags); | |
1661 | } | |
1662 | ||
1663 | static const char *pl011_type(struct uart_port *port) | |
1664 | { | |
e8a7ba86 RK |
1665 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1666 | return uap->port.type == PORT_AMBA ? uap->type : NULL; | |
1da177e4 LT |
1667 | } |
1668 | ||
1669 | /* | |
1670 | * Release the memory region(s) being used by 'port' | |
1671 | */ | |
1672 | static void pl010_release_port(struct uart_port *port) | |
1673 | { | |
1674 | release_mem_region(port->mapbase, SZ_4K); | |
1675 | } | |
1676 | ||
1677 | /* | |
1678 | * Request the memory region(s) being used by 'port' | |
1679 | */ | |
1680 | static int pl010_request_port(struct uart_port *port) | |
1681 | { | |
1682 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
1683 | != NULL ? 0 : -EBUSY; | |
1684 | } | |
1685 | ||
1686 | /* | |
1687 | * Configure/autoconfigure the port. | |
1688 | */ | |
1689 | static void pl010_config_port(struct uart_port *port, int flags) | |
1690 | { | |
1691 | if (flags & UART_CONFIG_TYPE) { | |
1692 | port->type = PORT_AMBA; | |
1693 | pl010_request_port(port); | |
1694 | } | |
1695 | } | |
1696 | ||
1697 | /* | |
1698 | * verify the new serial_struct (for TIOCSSERIAL). | |
1699 | */ | |
1700 | static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1701 | { | |
1702 | int ret = 0; | |
1703 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
1704 | ret = -EINVAL; | |
a62c4133 | 1705 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
1706 | ret = -EINVAL; |
1707 | if (ser->baud_base < 9600) | |
1708 | ret = -EINVAL; | |
1709 | return ret; | |
1710 | } | |
1711 | ||
1712 | static struct uart_ops amba_pl011_pops = { | |
1713 | .tx_empty = pl01x_tx_empty, | |
1714 | .set_mctrl = pl011_set_mctrl, | |
1715 | .get_mctrl = pl01x_get_mctrl, | |
1716 | .stop_tx = pl011_stop_tx, | |
1717 | .start_tx = pl011_start_tx, | |
1718 | .stop_rx = pl011_stop_rx, | |
1719 | .enable_ms = pl011_enable_ms, | |
1720 | .break_ctl = pl011_break_ctl, | |
1721 | .startup = pl011_startup, | |
1722 | .shutdown = pl011_shutdown, | |
68b65f73 | 1723 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
1724 | .set_termios = pl011_set_termios, |
1725 | .type = pl011_type, | |
1726 | .release_port = pl010_release_port, | |
1727 | .request_port = pl010_request_port, | |
1728 | .config_port = pl010_config_port, | |
1729 | .verify_port = pl010_verify_port, | |
84b5ae15 JW |
1730 | #ifdef CONFIG_CONSOLE_POLL |
1731 | .poll_get_char = pl010_get_poll_char, | |
1732 | .poll_put_char = pl010_put_poll_char, | |
1733 | #endif | |
1da177e4 LT |
1734 | }; |
1735 | ||
1736 | static struct uart_amba_port *amba_ports[UART_NR]; | |
1737 | ||
1738 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
1739 | ||
d358788f | 1740 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 1741 | { |
d358788f | 1742 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 | 1743 | |
d358788f RK |
1744 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
1745 | barrier(); | |
1da177e4 LT |
1746 | writew(ch, uap->port.membase + UART01x_DR); |
1747 | } | |
1748 | ||
1749 | static void | |
1750 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
1751 | { | |
1752 | struct uart_amba_port *uap = amba_ports[co->index]; | |
1753 | unsigned int status, old_cr, new_cr; | |
ef605fdb RV |
1754 | unsigned long flags; |
1755 | int locked = 1; | |
1da177e4 LT |
1756 | |
1757 | clk_enable(uap->clk); | |
1758 | ||
ef605fdb RV |
1759 | local_irq_save(flags); |
1760 | if (uap->port.sysrq) | |
1761 | locked = 0; | |
1762 | else if (oops_in_progress) | |
1763 | locked = spin_trylock(&uap->port.lock); | |
1764 | else | |
1765 | spin_lock(&uap->port.lock); | |
1766 | ||
1da177e4 LT |
1767 | /* |
1768 | * First save the CR then disable the interrupts | |
1769 | */ | |
1770 | old_cr = readw(uap->port.membase + UART011_CR); | |
1771 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
1772 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1773 | writew(new_cr, uap->port.membase + UART011_CR); | |
1774 | ||
d358788f | 1775 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
1776 | |
1777 | /* | |
1778 | * Finally, wait for transmitter to become empty | |
1779 | * and restore the TCR | |
1780 | */ | |
1781 | do { | |
1782 | status = readw(uap->port.membase + UART01x_FR); | |
1783 | } while (status & UART01x_FR_BUSY); | |
1784 | writew(old_cr, uap->port.membase + UART011_CR); | |
1785 | ||
ef605fdb RV |
1786 | if (locked) |
1787 | spin_unlock(&uap->port.lock); | |
1788 | local_irq_restore(flags); | |
1789 | ||
1da177e4 LT |
1790 | clk_disable(uap->clk); |
1791 | } | |
1792 | ||
1793 | static void __init | |
1794 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
1795 | int *parity, int *bits) | |
1796 | { | |
1797 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
1798 | unsigned int lcr_h, ibrd, fbrd; | |
1799 | ||
ec489aa8 | 1800 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1801 | |
1802 | *parity = 'n'; | |
1803 | if (lcr_h & UART01x_LCRH_PEN) { | |
1804 | if (lcr_h & UART01x_LCRH_EPS) | |
1805 | *parity = 'e'; | |
1806 | else | |
1807 | *parity = 'o'; | |
1808 | } | |
1809 | ||
1810 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
1811 | *bits = 7; | |
1812 | else | |
1813 | *bits = 8; | |
1814 | ||
1815 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
1816 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
1817 | ||
1818 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 1819 | |
c19f12b5 | 1820 | if (uap->vendor->oversampling) { |
ac3e3fb4 LW |
1821 | if (readw(uap->port.membase + UART011_CR) |
1822 | & ST_UART011_CR_OVSFACT) | |
1823 | *baud *= 2; | |
1824 | } | |
1da177e4 LT |
1825 | } |
1826 | } | |
1827 | ||
1828 | static int __init pl011_console_setup(struct console *co, char *options) | |
1829 | { | |
1830 | struct uart_amba_port *uap; | |
1831 | int baud = 38400; | |
1832 | int bits = 8; | |
1833 | int parity = 'n'; | |
1834 | int flow = 'n'; | |
4b4851c6 | 1835 | int ret; |
1da177e4 LT |
1836 | |
1837 | /* | |
1838 | * Check whether an invalid uart number has been specified, and | |
1839 | * if so, search for the first available port that does have | |
1840 | * console support. | |
1841 | */ | |
1842 | if (co->index >= UART_NR) | |
1843 | co->index = 0; | |
1844 | uap = amba_ports[co->index]; | |
d28122a5 RK |
1845 | if (!uap) |
1846 | return -ENODEV; | |
1da177e4 | 1847 | |
4b4851c6 RK |
1848 | ret = clk_prepare(uap->clk); |
1849 | if (ret) | |
1850 | return ret; | |
1851 | ||
c16d51a3 SKS |
1852 | if (uap->port.dev->platform_data) { |
1853 | struct amba_pl011_data *plat; | |
1854 | ||
1855 | plat = uap->port.dev->platform_data; | |
1856 | if (plat->init) | |
1857 | plat->init(); | |
1858 | } | |
1859 | ||
1da177e4 LT |
1860 | uap->port.uartclk = clk_get_rate(uap->clk); |
1861 | ||
1862 | if (options) | |
1863 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1864 | else | |
1865 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
1866 | ||
1867 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
1868 | } | |
1869 | ||
2d93486c | 1870 | static struct uart_driver amba_reg; |
1da177e4 LT |
1871 | static struct console amba_console = { |
1872 | .name = "ttyAMA", | |
1873 | .write = pl011_console_write, | |
1874 | .device = uart_console_device, | |
1875 | .setup = pl011_console_setup, | |
1876 | .flags = CON_PRINTBUFFER, | |
1877 | .index = -1, | |
1878 | .data = &amba_reg, | |
1879 | }; | |
1880 | ||
1881 | #define AMBA_CONSOLE (&amba_console) | |
1882 | #else | |
1883 | #define AMBA_CONSOLE NULL | |
1884 | #endif | |
1885 | ||
1886 | static struct uart_driver amba_reg = { | |
1887 | .owner = THIS_MODULE, | |
1888 | .driver_name = "ttyAMA", | |
1889 | .dev_name = "ttyAMA", | |
1890 | .major = SERIAL_AMBA_MAJOR, | |
1891 | .minor = SERIAL_AMBA_MINOR, | |
1892 | .nr = UART_NR, | |
1893 | .cons = AMBA_CONSOLE, | |
1894 | }; | |
1895 | ||
aa25afad | 1896 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
1da177e4 LT |
1897 | { |
1898 | struct uart_amba_port *uap; | |
5926a295 | 1899 | struct vendor_data *vendor = id->data; |
1da177e4 LT |
1900 | void __iomem *base; |
1901 | int i, ret; | |
1902 | ||
1903 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1904 | if (amba_ports[i] == NULL) | |
1905 | break; | |
1906 | ||
1907 | if (i == ARRAY_SIZE(amba_ports)) { | |
1908 | ret = -EBUSY; | |
1909 | goto out; | |
1910 | } | |
1911 | ||
dd00cc48 | 1912 | uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); |
1da177e4 LT |
1913 | if (uap == NULL) { |
1914 | ret = -ENOMEM; | |
1915 | goto out; | |
1916 | } | |
1917 | ||
dc890c2d | 1918 | base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1919 | if (!base) { |
1920 | ret = -ENOMEM; | |
1921 | goto free; | |
1922 | } | |
1923 | ||
ee569c43 | 1924 | uap->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
1925 | if (IS_ERR(uap->clk)) { |
1926 | ret = PTR_ERR(uap->clk); | |
1927 | goto unmap; | |
1928 | } | |
1929 | ||
c19f12b5 | 1930 | uap->vendor = vendor; |
ec489aa8 LW |
1931 | uap->lcrh_rx = vendor->lcrh_rx; |
1932 | uap->lcrh_tx = vendor->lcrh_tx; | |
d8d8ffa4 | 1933 | uap->old_cr = 0; |
ffca2b11 | 1934 | uap->fifosize = vendor->fifosize; |
c16d51a3 | 1935 | uap->interrupt_may_hang = vendor->interrupt_may_hang; |
1da177e4 LT |
1936 | uap->port.dev = &dev->dev; |
1937 | uap->port.mapbase = dev->res.start; | |
1938 | uap->port.membase = base; | |
1939 | uap->port.iotype = UPIO_MEM; | |
1940 | uap->port.irq = dev->irq[0]; | |
ffca2b11 | 1941 | uap->port.fifosize = uap->fifosize; |
1da177e4 LT |
1942 | uap->port.ops = &amba_pl011_pops; |
1943 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
1944 | uap->port.line = i; | |
68b65f73 | 1945 | pl011_dma_probe(uap); |
1da177e4 | 1946 | |
e8a7ba86 RK |
1947 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); |
1948 | ||
1da177e4 LT |
1949 | amba_ports[i] = uap; |
1950 | ||
1951 | amba_set_drvdata(dev, uap); | |
1952 | ret = uart_add_one_port(&amba_reg, &uap->port); | |
1953 | if (ret) { | |
1954 | amba_set_drvdata(dev, NULL); | |
1955 | amba_ports[i] = NULL; | |
68b65f73 | 1956 | pl011_dma_remove(uap); |
1da177e4 LT |
1957 | clk_put(uap->clk); |
1958 | unmap: | |
1959 | iounmap(base); | |
1960 | free: | |
1961 | kfree(uap); | |
1962 | } | |
1963 | out: | |
1964 | return ret; | |
1965 | } | |
1966 | ||
1967 | static int pl011_remove(struct amba_device *dev) | |
1968 | { | |
1969 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1970 | int i; | |
1971 | ||
1972 | amba_set_drvdata(dev, NULL); | |
1973 | ||
1974 | uart_remove_one_port(&amba_reg, &uap->port); | |
1975 | ||
1976 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1977 | if (amba_ports[i] == uap) | |
1978 | amba_ports[i] = NULL; | |
1979 | ||
68b65f73 | 1980 | pl011_dma_remove(uap); |
1da177e4 | 1981 | iounmap(uap->port.membase); |
1da177e4 LT |
1982 | clk_put(uap->clk); |
1983 | kfree(uap); | |
1984 | return 0; | |
1985 | } | |
1986 | ||
b736b89f LC |
1987 | #ifdef CONFIG_PM |
1988 | static int pl011_suspend(struct amba_device *dev, pm_message_t state) | |
1989 | { | |
1990 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1991 | ||
1992 | if (!uap) | |
1993 | return -EINVAL; | |
1994 | ||
1995 | return uart_suspend_port(&amba_reg, &uap->port); | |
1996 | } | |
1997 | ||
1998 | static int pl011_resume(struct amba_device *dev) | |
1999 | { | |
2000 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
2001 | ||
2002 | if (!uap) | |
2003 | return -EINVAL; | |
2004 | ||
2005 | return uart_resume_port(&amba_reg, &uap->port); | |
2006 | } | |
2007 | #endif | |
2008 | ||
2c39c9e1 | 2009 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
2010 | { |
2011 | .id = 0x00041011, | |
2012 | .mask = 0x000fffff, | |
5926a295 AR |
2013 | .data = &vendor_arm, |
2014 | }, | |
2015 | { | |
2016 | .id = 0x00380802, | |
2017 | .mask = 0x00ffffff, | |
2018 | .data = &vendor_st, | |
1da177e4 LT |
2019 | }, |
2020 | { 0, 0 }, | |
2021 | }; | |
2022 | ||
60f7a33b DM |
2023 | MODULE_DEVICE_TABLE(amba, pl011_ids); |
2024 | ||
1da177e4 LT |
2025 | static struct amba_driver pl011_driver = { |
2026 | .drv = { | |
2027 | .name = "uart-pl011", | |
2028 | }, | |
2029 | .id_table = pl011_ids, | |
2030 | .probe = pl011_probe, | |
2031 | .remove = pl011_remove, | |
b736b89f LC |
2032 | #ifdef CONFIG_PM |
2033 | .suspend = pl011_suspend, | |
2034 | .resume = pl011_resume, | |
2035 | #endif | |
1da177e4 LT |
2036 | }; |
2037 | ||
2038 | static int __init pl011_init(void) | |
2039 | { | |
2040 | int ret; | |
2041 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); | |
2042 | ||
2043 | ret = uart_register_driver(&amba_reg); | |
2044 | if (ret == 0) { | |
2045 | ret = amba_driver_register(&pl011_driver); | |
2046 | if (ret) | |
2047 | uart_unregister_driver(&amba_reg); | |
2048 | } | |
2049 | return ret; | |
2050 | } | |
2051 | ||
2052 | static void __exit pl011_exit(void) | |
2053 | { | |
2054 | amba_driver_unregister(&pl011_driver); | |
2055 | uart_unregister_driver(&amba_reg); | |
2056 | } | |
2057 | ||
4dd9e742 AR |
2058 | /* |
2059 | * While this can be a module, if builtin it's most likely the console | |
2060 | * So let's leave module_exit but move module_init to an earlier place | |
2061 | */ | |
2062 | arch_initcall(pl011_init); | |
1da177e4 LT |
2063 | module_exit(pl011_exit); |
2064 | ||
2065 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
2066 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
2067 | MODULE_LICENSE("GPL"); |