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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for AMBA serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright 1999 ARM Limited | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 8 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
1da177e4 LT |
24 | * This is a generic driver for ARM AMBA-type serial ports. They |
25 | * have a lot of 16550-like features, but are not register compatible. | |
26 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
27 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
28 | * required, these have to be supplied via some other means (eg, GPIO) | |
29 | * and hooked into this driver. | |
30 | */ | |
1da177e4 | 31 | |
cb06ff10 | 32 | |
1da177e4 LT |
33 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
34 | #define SUPPORT_SYSRQ | |
35 | #endif | |
36 | ||
37 | #include <linux/module.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/console.h> | |
41 | #include <linux/sysrq.h> | |
42 | #include <linux/device.h> | |
43 | #include <linux/tty.h> | |
44 | #include <linux/tty_flip.h> | |
45 | #include <linux/serial_core.h> | |
46 | #include <linux/serial.h> | |
a62c80e5 RK |
47 | #include <linux/amba/bus.h> |
48 | #include <linux/amba/serial.h> | |
f8ce2547 | 49 | #include <linux/clk.h> |
5a0e3ad6 | 50 | #include <linux/slab.h> |
68b65f73 RK |
51 | #include <linux/dmaengine.h> |
52 | #include <linux/dma-mapping.h> | |
53 | #include <linux/scatterlist.h> | |
c16d51a3 | 54 | #include <linux/delay.h> |
258aea76 | 55 | #include <linux/types.h> |
32614aad ML |
56 | #include <linux/of.h> |
57 | #include <linux/of_device.h> | |
258e0551 | 58 | #include <linux/pinctrl/consumer.h> |
cb70706c | 59 | #include <linux/sizes.h> |
de609582 | 60 | #include <linux/io.h> |
1da177e4 LT |
61 | |
62 | #define UART_NR 14 | |
63 | ||
64 | #define SERIAL_AMBA_MAJOR 204 | |
65 | #define SERIAL_AMBA_MINOR 64 | |
66 | #define SERIAL_AMBA_NR UART_NR | |
67 | ||
68 | #define AMBA_ISR_PASS_LIMIT 256 | |
69 | ||
b63d4f0f RK |
70 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
71 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 72 | |
5926a295 AR |
73 | /* There is by now at least one vendor with differing details, so handle it */ |
74 | struct vendor_data { | |
75 | unsigned int ifls; | |
ec489aa8 LW |
76 | unsigned int lcrh_tx; |
77 | unsigned int lcrh_rx; | |
ac3e3fb4 | 78 | bool oversampling; |
38d62436 | 79 | bool dma_threshold; |
4fd0690b | 80 | bool cts_event_workaround; |
78506f22 | 81 | |
ea33640a | 82 | unsigned int (*get_fifosize)(struct amba_device *dev); |
5926a295 AR |
83 | }; |
84 | ||
ea33640a | 85 | static unsigned int get_fifosize_arm(struct amba_device *dev) |
78506f22 | 86 | { |
ea33640a | 87 | return amba_rev(dev) < 3 ? 16 : 32; |
78506f22 JK |
88 | } |
89 | ||
5926a295 AR |
90 | static struct vendor_data vendor_arm = { |
91 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
ec489aa8 LW |
92 | .lcrh_tx = UART011_LCRH, |
93 | .lcrh_rx = UART011_LCRH, | |
ac3e3fb4 | 94 | .oversampling = false, |
38d62436 | 95 | .dma_threshold = false, |
4fd0690b | 96 | .cts_event_workaround = false, |
78506f22 | 97 | .get_fifosize = get_fifosize_arm, |
5926a295 AR |
98 | }; |
99 | ||
ea33640a | 100 | static unsigned int get_fifosize_st(struct amba_device *dev) |
78506f22 JK |
101 | { |
102 | return 64; | |
103 | } | |
104 | ||
5926a295 AR |
105 | static struct vendor_data vendor_st = { |
106 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, | |
ec489aa8 LW |
107 | .lcrh_tx = ST_UART011_LCRH_TX, |
108 | .lcrh_rx = ST_UART011_LCRH_RX, | |
ac3e3fb4 | 109 | .oversampling = true, |
38d62436 | 110 | .dma_threshold = true, |
4fd0690b | 111 | .cts_event_workaround = true, |
78506f22 | 112 | .get_fifosize = get_fifosize_st, |
1da177e4 LT |
113 | }; |
114 | ||
68b65f73 | 115 | /* Deals with DMA transactions */ |
ead76f32 LW |
116 | |
117 | struct pl011_sgbuf { | |
118 | struct scatterlist sg; | |
119 | char *buf; | |
120 | }; | |
121 | ||
122 | struct pl011_dmarx_data { | |
123 | struct dma_chan *chan; | |
124 | struct completion complete; | |
125 | bool use_buf_b; | |
126 | struct pl011_sgbuf sgbuf_a; | |
127 | struct pl011_sgbuf sgbuf_b; | |
128 | dma_cookie_t cookie; | |
129 | bool running; | |
cb06ff10 CM |
130 | struct timer_list timer; |
131 | unsigned int last_residue; | |
132 | unsigned long last_jiffies; | |
133 | bool auto_poll_rate; | |
134 | unsigned int poll_rate; | |
135 | unsigned int poll_timeout; | |
ead76f32 LW |
136 | }; |
137 | ||
68b65f73 RK |
138 | struct pl011_dmatx_data { |
139 | struct dma_chan *chan; | |
140 | struct scatterlist sg; | |
141 | char *buf; | |
142 | bool queued; | |
143 | }; | |
144 | ||
c19f12b5 RK |
145 | /* |
146 | * We wrap our port structure around the generic uart_port. | |
147 | */ | |
148 | struct uart_amba_port { | |
149 | struct uart_port port; | |
150 | struct clk *clk; | |
151 | const struct vendor_data *vendor; | |
68b65f73 | 152 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
153 | unsigned int im; /* interrupt mask */ |
154 | unsigned int old_status; | |
ffca2b11 | 155 | unsigned int fifosize; /* vendor-specific */ |
c19f12b5 RK |
156 | unsigned int lcrh_tx; /* vendor-specific */ |
157 | unsigned int lcrh_rx; /* vendor-specific */ | |
d8d8ffa4 | 158 | unsigned int old_cr; /* state during shutdown */ |
c19f12b5 RK |
159 | bool autorts; |
160 | char type[12]; | |
68b65f73 RK |
161 | #ifdef CONFIG_DMA_ENGINE |
162 | /* DMA stuff */ | |
ead76f32 LW |
163 | bool using_tx_dma; |
164 | bool using_rx_dma; | |
165 | struct pl011_dmarx_data dmarx; | |
68b65f73 RK |
166 | struct pl011_dmatx_data dmatx; |
167 | #endif | |
168 | }; | |
169 | ||
29772c4e LW |
170 | /* |
171 | * Reads up to 256 characters from the FIFO or until it's empty and | |
172 | * inserts them into the TTY layer. Returns the number of characters | |
173 | * read from the FIFO. | |
174 | */ | |
175 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) | |
176 | { | |
177 | u16 status, ch; | |
178 | unsigned int flag, max_count = 256; | |
179 | int fifotaken = 0; | |
180 | ||
181 | while (max_count--) { | |
182 | status = readw(uap->port.membase + UART01x_FR); | |
183 | if (status & UART01x_FR_RXFE) | |
184 | break; | |
185 | ||
186 | /* Take chars from the FIFO and update status */ | |
187 | ch = readw(uap->port.membase + UART01x_DR) | | |
188 | UART_DUMMY_DR_RX; | |
189 | flag = TTY_NORMAL; | |
190 | uap->port.icount.rx++; | |
191 | fifotaken++; | |
192 | ||
193 | if (unlikely(ch & UART_DR_ERROR)) { | |
194 | if (ch & UART011_DR_BE) { | |
195 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
196 | uap->port.icount.brk++; | |
197 | if (uart_handle_break(&uap->port)) | |
198 | continue; | |
199 | } else if (ch & UART011_DR_PE) | |
200 | uap->port.icount.parity++; | |
201 | else if (ch & UART011_DR_FE) | |
202 | uap->port.icount.frame++; | |
203 | if (ch & UART011_DR_OE) | |
204 | uap->port.icount.overrun++; | |
205 | ||
206 | ch &= uap->port.read_status_mask; | |
207 | ||
208 | if (ch & UART011_DR_BE) | |
209 | flag = TTY_BREAK; | |
210 | else if (ch & UART011_DR_PE) | |
211 | flag = TTY_PARITY; | |
212 | else if (ch & UART011_DR_FE) | |
213 | flag = TTY_FRAME; | |
214 | } | |
215 | ||
216 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) | |
217 | continue; | |
218 | ||
219 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
220 | } | |
221 | ||
222 | return fifotaken; | |
223 | } | |
224 | ||
225 | ||
68b65f73 RK |
226 | /* |
227 | * All the DMA operation mode stuff goes inside this ifdef. | |
228 | * This assumes that you have a generic DMA device interface, | |
229 | * no custom DMA interfaces are supported. | |
230 | */ | |
231 | #ifdef CONFIG_DMA_ENGINE | |
232 | ||
233 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
234 | ||
ead76f32 LW |
235 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
236 | enum dma_data_direction dir) | |
237 | { | |
cb06ff10 CM |
238 | dma_addr_t dma_addr; |
239 | ||
240 | sg->buf = dma_alloc_coherent(chan->device->dev, | |
241 | PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); | |
ead76f32 LW |
242 | if (!sg->buf) |
243 | return -ENOMEM; | |
244 | ||
cb06ff10 CM |
245 | sg_init_table(&sg->sg, 1); |
246 | sg_set_page(&sg->sg, phys_to_page(dma_addr), | |
247 | PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); | |
248 | sg_dma_address(&sg->sg) = dma_addr; | |
ead76f32 | 249 | |
ead76f32 LW |
250 | return 0; |
251 | } | |
252 | ||
253 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |
254 | enum dma_data_direction dir) | |
255 | { | |
256 | if (sg->buf) { | |
cb06ff10 CM |
257 | dma_free_coherent(chan->device->dev, |
258 | PL011_DMA_BUFFER_SIZE, sg->buf, | |
259 | sg_dma_address(&sg->sg)); | |
ead76f32 LW |
260 | } |
261 | } | |
262 | ||
787b0c1f | 263 | static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *uap) |
68b65f73 RK |
264 | { |
265 | /* DMA is the sole user of the platform data right now */ | |
574de559 | 266 | struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); |
68b65f73 RK |
267 | struct dma_slave_config tx_conf = { |
268 | .dst_addr = uap->port.mapbase + UART01x_DR, | |
269 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 270 | .direction = DMA_MEM_TO_DEV, |
68b65f73 | 271 | .dst_maxburst = uap->fifosize >> 1, |
258aea76 | 272 | .device_fc = false, |
68b65f73 RK |
273 | }; |
274 | struct dma_chan *chan; | |
275 | dma_cap_mask_t mask; | |
276 | ||
787b0c1f | 277 | chan = dma_request_slave_channel(dev, "tx"); |
68b65f73 | 278 | |
68b65f73 | 279 | if (!chan) { |
787b0c1f AB |
280 | /* We need platform data */ |
281 | if (!plat || !plat->dma_filter) { | |
282 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
283 | return; | |
284 | } | |
285 | ||
286 | /* Try to acquire a generic DMA engine slave TX channel */ | |
287 | dma_cap_zero(mask); | |
288 | dma_cap_set(DMA_SLAVE, mask); | |
289 | ||
290 | chan = dma_request_channel(mask, plat->dma_filter, | |
291 | plat->dma_tx_param); | |
292 | if (!chan) { | |
293 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
294 | return; | |
295 | } | |
68b65f73 RK |
296 | } |
297 | ||
298 | dmaengine_slave_config(chan, &tx_conf); | |
299 | uap->dmatx.chan = chan; | |
300 | ||
301 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
302 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
303 | |
304 | /* Optionally make use of an RX channel as well */ | |
787b0c1f AB |
305 | chan = dma_request_slave_channel(dev, "rx"); |
306 | ||
307 | if (!chan && plat->dma_rx_param) { | |
308 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); | |
309 | ||
310 | if (!chan) { | |
311 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
312 | return; | |
313 | } | |
314 | } | |
315 | ||
316 | if (chan) { | |
ead76f32 LW |
317 | struct dma_slave_config rx_conf = { |
318 | .src_addr = uap->port.mapbase + UART01x_DR, | |
319 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 320 | .direction = DMA_DEV_TO_MEM, |
ead76f32 | 321 | .src_maxburst = uap->fifosize >> 1, |
258aea76 | 322 | .device_fc = false, |
ead76f32 LW |
323 | }; |
324 | ||
ead76f32 LW |
325 | dmaengine_slave_config(chan, &rx_conf); |
326 | uap->dmarx.chan = chan; | |
327 | ||
8f898bfd | 328 | if (plat && plat->dma_rx_poll_enable) { |
cb06ff10 CM |
329 | /* Set poll rate if specified. */ |
330 | if (plat->dma_rx_poll_rate) { | |
331 | uap->dmarx.auto_poll_rate = false; | |
332 | uap->dmarx.poll_rate = plat->dma_rx_poll_rate; | |
333 | } else { | |
334 | /* | |
335 | * 100 ms defaults to poll rate if not | |
336 | * specified. This will be adjusted with | |
337 | * the baud rate at set_termios. | |
338 | */ | |
339 | uap->dmarx.auto_poll_rate = true; | |
340 | uap->dmarx.poll_rate = 100; | |
341 | } | |
342 | /* 3 secs defaults poll_timeout if not specified. */ | |
343 | if (plat->dma_rx_poll_timeout) | |
344 | uap->dmarx.poll_timeout = | |
345 | plat->dma_rx_poll_timeout; | |
346 | else | |
347 | uap->dmarx.poll_timeout = 3000; | |
348 | } else | |
349 | uap->dmarx.auto_poll_rate = false; | |
350 | ||
ead76f32 LW |
351 | dev_info(uap->port.dev, "DMA channel RX %s\n", |
352 | dma_chan_name(uap->dmarx.chan)); | |
353 | } | |
68b65f73 RK |
354 | } |
355 | ||
356 | #ifndef MODULE | |
357 | /* | |
358 | * Stack up the UARTs and let the above initcall be done at device | |
359 | * initcall time, because the serial driver is called as an arch | |
360 | * initcall, and at this time the DMA subsystem is not yet registered. | |
361 | * At this point the driver will switch over to using DMA where desired. | |
362 | */ | |
363 | struct dma_uap { | |
364 | struct list_head node; | |
365 | struct uart_amba_port *uap; | |
787b0c1f | 366 | struct device *dev; |
c19f12b5 RK |
367 | }; |
368 | ||
68b65f73 RK |
369 | static LIST_HEAD(pl011_dma_uarts); |
370 | ||
371 | static int __init pl011_dma_initcall(void) | |
372 | { | |
373 | struct list_head *node, *tmp; | |
374 | ||
375 | list_for_each_safe(node, tmp, &pl011_dma_uarts) { | |
376 | struct dma_uap *dmau = list_entry(node, struct dma_uap, node); | |
787b0c1f | 377 | pl011_dma_probe_initcall(dmau->dev, dmau->uap); |
68b65f73 RK |
378 | list_del(node); |
379 | kfree(dmau); | |
380 | } | |
381 | return 0; | |
382 | } | |
383 | ||
384 | device_initcall(pl011_dma_initcall); | |
385 | ||
787b0c1f | 386 | static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) |
68b65f73 RK |
387 | { |
388 | struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL); | |
389 | if (dmau) { | |
390 | dmau->uap = uap; | |
787b0c1f | 391 | dmau->dev = dev; |
68b65f73 RK |
392 | list_add_tail(&dmau->node, &pl011_dma_uarts); |
393 | } | |
394 | } | |
395 | #else | |
787b0c1f | 396 | static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) |
68b65f73 | 397 | { |
787b0c1f | 398 | pl011_dma_probe_initcall(dev, uap); |
68b65f73 RK |
399 | } |
400 | #endif | |
401 | ||
402 | static void pl011_dma_remove(struct uart_amba_port *uap) | |
403 | { | |
404 | /* TODO: remove the initcall if it has not yet executed */ | |
405 | if (uap->dmatx.chan) | |
406 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
407 | if (uap->dmarx.chan) |
408 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
409 | } |
410 | ||
68b65f73 RK |
411 | /* Forward declare this for the refill routine */ |
412 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); | |
413 | ||
414 | /* | |
415 | * The current DMA TX buffer has been sent. | |
416 | * Try to queue up another DMA buffer. | |
417 | */ | |
418 | static void pl011_dma_tx_callback(void *data) | |
419 | { | |
420 | struct uart_amba_port *uap = data; | |
421 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
422 | unsigned long flags; | |
423 | u16 dmacr; | |
424 | ||
425 | spin_lock_irqsave(&uap->port.lock, flags); | |
426 | if (uap->dmatx.queued) | |
427 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
428 | DMA_TO_DEVICE); | |
429 | ||
430 | dmacr = uap->dmacr; | |
431 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
432 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
433 | ||
434 | /* | |
435 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
436 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
437 | * | |
438 | * Note: we need to be careful here of a potential race between DMA | |
439 | * and the rest of the driver - if the driver disables TX DMA while | |
440 | * a TX buffer completing, we must update the tx queued status to | |
441 | * get further refills (hence we check dmacr). | |
442 | */ | |
443 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
444 | uart_circ_empty(&uap->port.state->xmit)) { | |
445 | uap->dmatx.queued = false; | |
446 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
447 | return; | |
448 | } | |
449 | ||
450 | if (pl011_dma_tx_refill(uap) <= 0) { | |
451 | /* | |
452 | * We didn't queue a DMA buffer for some reason, but we | |
453 | * have data pending to be sent. Re-enable the TX IRQ. | |
454 | */ | |
455 | uap->im |= UART011_TXIM; | |
456 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
457 | } | |
458 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
459 | } | |
460 | ||
461 | /* | |
462 | * Try to refill the TX DMA buffer. | |
463 | * Locking: called with port lock held and IRQs disabled. | |
464 | * Returns: | |
465 | * 1 if we queued up a TX DMA buffer. | |
466 | * 0 if we didn't want to handle this by DMA | |
467 | * <0 on error | |
468 | */ | |
469 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
470 | { | |
471 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
472 | struct dma_chan *chan = dmatx->chan; | |
473 | struct dma_device *dma_dev = chan->device; | |
474 | struct dma_async_tx_descriptor *desc; | |
475 | struct circ_buf *xmit = &uap->port.state->xmit; | |
476 | unsigned int count; | |
477 | ||
478 | /* | |
479 | * Try to avoid the overhead involved in using DMA if the | |
480 | * transaction fits in the first half of the FIFO, by using | |
481 | * the standard interrupt handling. This ensures that we | |
482 | * issue a uart_write_wakeup() at the appropriate time. | |
483 | */ | |
484 | count = uart_circ_chars_pending(xmit); | |
485 | if (count < (uap->fifosize >> 1)) { | |
486 | uap->dmatx.queued = false; | |
487 | return 0; | |
488 | } | |
489 | ||
490 | /* | |
491 | * Bodge: don't send the last character by DMA, as this | |
492 | * will prevent XON from notifying us to restart DMA. | |
493 | */ | |
494 | count -= 1; | |
495 | ||
496 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
497 | if (count > PL011_DMA_BUFFER_SIZE) | |
498 | count = PL011_DMA_BUFFER_SIZE; | |
499 | ||
500 | if (xmit->tail < xmit->head) | |
501 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
502 | else { | |
503 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
504 | size_t second = xmit->head; | |
505 | ||
506 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
507 | if (second) | |
508 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
509 | } | |
510 | ||
511 | dmatx->sg.length = count; | |
512 | ||
513 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
514 | uap->dmatx.queued = false; | |
515 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
516 | return -EBUSY; | |
517 | } | |
518 | ||
16052827 | 519 | desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, |
68b65f73 RK |
520 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
521 | if (!desc) { | |
522 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
523 | uap->dmatx.queued = false; | |
524 | /* | |
525 | * If DMA cannot be used right now, we complete this | |
526 | * transaction via IRQ and let the TTY layer retry. | |
527 | */ | |
528 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
529 | return -EBUSY; | |
530 | } | |
531 | ||
532 | /* Some data to go along to the callback */ | |
533 | desc->callback = pl011_dma_tx_callback; | |
534 | desc->callback_param = uap; | |
535 | ||
536 | /* All errors should happen at prepare time */ | |
537 | dmaengine_submit(desc); | |
538 | ||
539 | /* Fire the DMA transaction */ | |
540 | dma_dev->device_issue_pending(chan); | |
541 | ||
542 | uap->dmacr |= UART011_TXDMAE; | |
543 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
544 | uap->dmatx.queued = true; | |
545 | ||
546 | /* | |
547 | * Now we know that DMA will fire, so advance the ring buffer | |
548 | * with the stuff we just dispatched. | |
549 | */ | |
550 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
551 | uap->port.icount.tx += count; | |
552 | ||
553 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
554 | uart_write_wakeup(&uap->port); | |
555 | ||
556 | return 1; | |
557 | } | |
558 | ||
559 | /* | |
560 | * We received a transmit interrupt without a pending X-char but with | |
561 | * pending characters. | |
562 | * Locking: called with port lock held and IRQs disabled. | |
563 | * Returns: | |
564 | * false if we want to use PIO to transmit | |
565 | * true if we queued a DMA buffer | |
566 | */ | |
567 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
568 | { | |
ead76f32 | 569 | if (!uap->using_tx_dma) |
68b65f73 RK |
570 | return false; |
571 | ||
572 | /* | |
573 | * If we already have a TX buffer queued, but received a | |
574 | * TX interrupt, it will be because we've just sent an X-char. | |
575 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
576 | */ | |
577 | if (uap->dmatx.queued) { | |
578 | uap->dmacr |= UART011_TXDMAE; | |
579 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
580 | uap->im &= ~UART011_TXIM; | |
581 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
582 | return true; | |
583 | } | |
584 | ||
585 | /* | |
586 | * We don't have a TX buffer queued, so try to queue one. | |
25985edc | 587 | * If we successfully queued a buffer, mask the TX IRQ. |
68b65f73 RK |
588 | */ |
589 | if (pl011_dma_tx_refill(uap) > 0) { | |
590 | uap->im &= ~UART011_TXIM; | |
591 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
592 | return true; | |
593 | } | |
594 | return false; | |
595 | } | |
596 | ||
597 | /* | |
598 | * Stop the DMA transmit (eg, due to received XOFF). | |
599 | * Locking: called with port lock held and IRQs disabled. | |
600 | */ | |
601 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
602 | { | |
603 | if (uap->dmatx.queued) { | |
604 | uap->dmacr &= ~UART011_TXDMAE; | |
605 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
606 | } | |
607 | } | |
608 | ||
609 | /* | |
610 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
611 | * character queued for send, try to get that character out ASAP. | |
612 | * Locking: called with port lock held and IRQs disabled. | |
613 | * Returns: | |
614 | * false if we want the TX IRQ to be enabled | |
615 | * true if we have a buffer queued | |
616 | */ | |
617 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
618 | { | |
619 | u16 dmacr; | |
620 | ||
ead76f32 | 621 | if (!uap->using_tx_dma) |
68b65f73 RK |
622 | return false; |
623 | ||
624 | if (!uap->port.x_char) { | |
625 | /* no X-char, try to push chars out in DMA mode */ | |
626 | bool ret = true; | |
627 | ||
628 | if (!uap->dmatx.queued) { | |
629 | if (pl011_dma_tx_refill(uap) > 0) { | |
630 | uap->im &= ~UART011_TXIM; | |
631 | ret = true; | |
632 | } else { | |
633 | uap->im |= UART011_TXIM; | |
634 | ret = false; | |
635 | } | |
636 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
637 | } else if (!(uap->dmacr & UART011_TXDMAE)) { | |
638 | uap->dmacr |= UART011_TXDMAE; | |
639 | writew(uap->dmacr, | |
640 | uap->port.membase + UART011_DMACR); | |
641 | } | |
642 | return ret; | |
643 | } | |
644 | ||
645 | /* | |
646 | * We have an X-char to send. Disable DMA to prevent it loading | |
647 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
648 | */ | |
649 | dmacr = uap->dmacr; | |
650 | uap->dmacr &= ~UART011_TXDMAE; | |
651 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
652 | ||
653 | if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { | |
654 | /* | |
655 | * No space in the FIFO, so enable the transmit interrupt | |
656 | * so we know when there is space. Note that once we've | |
657 | * loaded the character, we should just re-enable DMA. | |
658 | */ | |
659 | return false; | |
660 | } | |
661 | ||
662 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
663 | uap->port.icount.tx++; | |
664 | uap->port.x_char = 0; | |
665 | ||
666 | /* Success - restore the DMA state */ | |
667 | uap->dmacr = dmacr; | |
668 | writew(dmacr, uap->port.membase + UART011_DMACR); | |
669 | ||
670 | return true; | |
671 | } | |
672 | ||
673 | /* | |
674 | * Flush the transmit buffer. | |
675 | * Locking: called with port lock held and IRQs disabled. | |
676 | */ | |
677 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
b83286bf FE |
678 | __releases(&uap->port.lock) |
679 | __acquires(&uap->port.lock) | |
68b65f73 RK |
680 | { |
681 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
682 | ||
ead76f32 | 683 | if (!uap->using_tx_dma) |
68b65f73 RK |
684 | return; |
685 | ||
686 | /* Avoid deadlock with the DMA engine callback */ | |
687 | spin_unlock(&uap->port.lock); | |
688 | dmaengine_terminate_all(uap->dmatx.chan); | |
689 | spin_lock(&uap->port.lock); | |
690 | if (uap->dmatx.queued) { | |
691 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
692 | DMA_TO_DEVICE); | |
693 | uap->dmatx.queued = false; | |
694 | uap->dmacr &= ~UART011_TXDMAE; | |
695 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
696 | } | |
697 | } | |
698 | ||
ead76f32 LW |
699 | static void pl011_dma_rx_callback(void *data); |
700 | ||
701 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
702 | { | |
703 | struct dma_chan *rxchan = uap->dmarx.chan; | |
ead76f32 LW |
704 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
705 | struct dma_async_tx_descriptor *desc; | |
706 | struct pl011_sgbuf *sgbuf; | |
707 | ||
708 | if (!rxchan) | |
709 | return -EIO; | |
710 | ||
711 | /* Start the RX DMA job */ | |
712 | sgbuf = uap->dmarx.use_buf_b ? | |
713 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
16052827 | 714 | desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, |
a485df4b | 715 | DMA_DEV_TO_MEM, |
ead76f32 LW |
716 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
717 | /* | |
718 | * If the DMA engine is busy and cannot prepare a | |
719 | * channel, no big deal, the driver will fall back | |
720 | * to interrupt mode as a result of this error code. | |
721 | */ | |
722 | if (!desc) { | |
723 | uap->dmarx.running = false; | |
724 | dmaengine_terminate_all(rxchan); | |
725 | return -EBUSY; | |
726 | } | |
727 | ||
728 | /* Some data to go along to the callback */ | |
729 | desc->callback = pl011_dma_rx_callback; | |
730 | desc->callback_param = uap; | |
731 | dmarx->cookie = dmaengine_submit(desc); | |
732 | dma_async_issue_pending(rxchan); | |
733 | ||
734 | uap->dmacr |= UART011_RXDMAE; | |
735 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
736 | uap->dmarx.running = true; | |
737 | ||
738 | uap->im &= ~UART011_RXIM; | |
739 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
740 | ||
741 | return 0; | |
742 | } | |
743 | ||
744 | /* | |
745 | * This is called when either the DMA job is complete, or | |
746 | * the FIFO timeout interrupt occurred. This must be called | |
747 | * with the port spinlock uap->port.lock held. | |
748 | */ | |
749 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
750 | u32 pending, bool use_buf_b, | |
751 | bool readfifo) | |
752 | { | |
05c7cd39 | 753 | struct tty_port *port = &uap->port.state->port; |
ead76f32 LW |
754 | struct pl011_sgbuf *sgbuf = use_buf_b ? |
755 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
ead76f32 LW |
756 | int dma_count = 0; |
757 | u32 fifotaken = 0; /* only used for vdbg() */ | |
758 | ||
cb06ff10 CM |
759 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
760 | int dmataken = 0; | |
761 | ||
762 | if (uap->dmarx.poll_rate) { | |
763 | /* The data can be taken by polling */ | |
764 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
765 | /* Recalculate the pending size */ | |
766 | if (pending >= dmataken) | |
767 | pending -= dmataken; | |
768 | } | |
769 | ||
770 | /* Pick the remain data from the DMA */ | |
ead76f32 | 771 | if (pending) { |
ead76f32 LW |
772 | |
773 | /* | |
774 | * First take all chars in the DMA pipe, then look in the FIFO. | |
775 | * Note that tty_insert_flip_buf() tries to take as many chars | |
776 | * as it can. | |
777 | */ | |
cb06ff10 CM |
778 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, |
779 | pending); | |
ead76f32 LW |
780 | |
781 | uap->port.icount.rx += dma_count; | |
782 | if (dma_count < pending) | |
783 | dev_warn(uap->port.dev, | |
784 | "couldn't insert all characters (TTY is full?)\n"); | |
785 | } | |
786 | ||
cb06ff10 CM |
787 | /* Reset the last_residue for Rx DMA poll */ |
788 | if (uap->dmarx.poll_rate) | |
789 | dmarx->last_residue = sgbuf->sg.length; | |
790 | ||
ead76f32 LW |
791 | /* |
792 | * Only continue with trying to read the FIFO if all DMA chars have | |
793 | * been taken first. | |
794 | */ | |
795 | if (dma_count == pending && readfifo) { | |
796 | /* Clear any error flags */ | |
797 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
798 | uap->port.membase + UART011_ICR); | |
799 | ||
800 | /* | |
801 | * If we read all the DMA'd characters, and we had an | |
29772c4e LW |
802 | * incomplete buffer, that could be due to an rx error, or |
803 | * maybe we just timed out. Read any pending chars and check | |
804 | * the error status. | |
805 | * | |
806 | * Error conditions will only occur in the FIFO, these will | |
807 | * trigger an immediate interrupt and stop the DMA job, so we | |
808 | * will always find the error in the FIFO, never in the DMA | |
809 | * buffer. | |
ead76f32 | 810 | */ |
29772c4e | 811 | fifotaken = pl011_fifo_to_tty(uap); |
ead76f32 LW |
812 | } |
813 | ||
814 | spin_unlock(&uap->port.lock); | |
815 | dev_vdbg(uap->port.dev, | |
816 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
817 | dma_count, fifotaken); | |
2e124b4a | 818 | tty_flip_buffer_push(port); |
ead76f32 LW |
819 | spin_lock(&uap->port.lock); |
820 | } | |
821 | ||
822 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
823 | { | |
824 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
825 | struct dma_chan *rxchan = dmarx->chan; | |
826 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? | |
827 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
828 | size_t pending; | |
829 | struct dma_tx_state state; | |
830 | enum dma_status dmastat; | |
831 | ||
832 | /* | |
833 | * Pause the transfer so we can trust the current counter, | |
834 | * do this before we pause the PL011 block, else we may | |
835 | * overflow the FIFO. | |
836 | */ | |
837 | if (dmaengine_pause(rxchan)) | |
838 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
839 | dmastat = rxchan->device->device_tx_status(rxchan, | |
840 | dmarx->cookie, &state); | |
841 | if (dmastat != DMA_PAUSED) | |
842 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
843 | ||
844 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
845 | uap->dmacr &= ~UART011_RXDMAE; | |
846 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
847 | uap->dmarx.running = false; | |
848 | ||
849 | pending = sgbuf->sg.length - state.residue; | |
850 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
851 | /* Then we terminate the transfer - we now know our residue */ | |
852 | dmaengine_terminate_all(rxchan); | |
853 | ||
854 | /* | |
855 | * This will take the chars we have so far and insert | |
856 | * into the framework. | |
857 | */ | |
858 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
859 | ||
860 | /* Switch buffer & re-trigger DMA job */ | |
861 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
862 | if (pl011_dma_rx_trigger_dma(uap)) { | |
863 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
864 | "fall back to interrupt mode\n"); | |
865 | uap->im |= UART011_RXIM; | |
866 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
867 | } | |
868 | } | |
869 | ||
870 | static void pl011_dma_rx_callback(void *data) | |
871 | { | |
872 | struct uart_amba_port *uap = data; | |
873 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
6dc01aa6 | 874 | struct dma_chan *rxchan = dmarx->chan; |
ead76f32 | 875 | bool lastbuf = dmarx->use_buf_b; |
6dc01aa6 CM |
876 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? |
877 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
878 | size_t pending; | |
879 | struct dma_tx_state state; | |
ead76f32 LW |
880 | int ret; |
881 | ||
882 | /* | |
883 | * This completion interrupt occurs typically when the | |
884 | * RX buffer is totally stuffed but no timeout has yet | |
885 | * occurred. When that happens, we just want the RX | |
886 | * routine to flush out the secondary DMA buffer while | |
887 | * we immediately trigger the next DMA job. | |
888 | */ | |
889 | spin_lock_irq(&uap->port.lock); | |
6dc01aa6 CM |
890 | /* |
891 | * Rx data can be taken by the UART interrupts during | |
892 | * the DMA irq handler. So we check the residue here. | |
893 | */ | |
894 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
895 | pending = sgbuf->sg.length - state.residue; | |
896 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
897 | /* Then we terminate the transfer - we now know our residue */ | |
898 | dmaengine_terminate_all(rxchan); | |
899 | ||
ead76f32 LW |
900 | uap->dmarx.running = false; |
901 | dmarx->use_buf_b = !lastbuf; | |
902 | ret = pl011_dma_rx_trigger_dma(uap); | |
903 | ||
6dc01aa6 | 904 | pl011_dma_rx_chars(uap, pending, lastbuf, false); |
ead76f32 LW |
905 | spin_unlock_irq(&uap->port.lock); |
906 | /* | |
907 | * Do this check after we picked the DMA chars so we don't | |
908 | * get some IRQ immediately from RX. | |
909 | */ | |
910 | if (ret) { | |
911 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
912 | "fall back to interrupt mode\n"); | |
913 | uap->im |= UART011_RXIM; | |
914 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
915 | } | |
916 | } | |
917 | ||
918 | /* | |
919 | * Stop accepting received characters, when we're shutting down or | |
920 | * suspending this port. | |
921 | * Locking: called with port lock held and IRQs disabled. | |
922 | */ | |
923 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
924 | { | |
925 | /* FIXME. Just disable the DMA enable */ | |
926 | uap->dmacr &= ~UART011_RXDMAE; | |
927 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
928 | } | |
68b65f73 | 929 | |
cb06ff10 CM |
930 | /* |
931 | * Timer handler for Rx DMA polling. | |
932 | * Every polling, It checks the residue in the dma buffer and transfer | |
933 | * data to the tty. Also, last_residue is updated for the next polling. | |
934 | */ | |
935 | static void pl011_dma_rx_poll(unsigned long args) | |
936 | { | |
937 | struct uart_amba_port *uap = (struct uart_amba_port *)args; | |
938 | struct tty_port *port = &uap->port.state->port; | |
939 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
940 | struct dma_chan *rxchan = uap->dmarx.chan; | |
941 | unsigned long flags = 0; | |
942 | unsigned int dmataken = 0; | |
943 | unsigned int size = 0; | |
944 | struct pl011_sgbuf *sgbuf; | |
945 | int dma_count; | |
946 | struct dma_tx_state state; | |
947 | ||
948 | sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
949 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
950 | if (likely(state.residue < dmarx->last_residue)) { | |
951 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
952 | size = dmarx->last_residue - state.residue; | |
953 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, | |
954 | size); | |
955 | if (dma_count == size) | |
956 | dmarx->last_residue = state.residue; | |
957 | dmarx->last_jiffies = jiffies; | |
958 | } | |
959 | tty_flip_buffer_push(port); | |
960 | ||
961 | /* | |
962 | * If no data is received in poll_timeout, the driver will fall back | |
963 | * to interrupt mode. We will retrigger DMA at the first interrupt. | |
964 | */ | |
965 | if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) | |
966 | > uap->dmarx.poll_timeout) { | |
967 | ||
968 | spin_lock_irqsave(&uap->port.lock, flags); | |
969 | pl011_dma_rx_stop(uap); | |
970 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
971 | ||
972 | uap->dmarx.running = false; | |
973 | dmaengine_terminate_all(rxchan); | |
974 | del_timer(&uap->dmarx.timer); | |
975 | } else { | |
976 | mod_timer(&uap->dmarx.timer, | |
977 | jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); | |
978 | } | |
979 | } | |
980 | ||
68b65f73 RK |
981 | static void pl011_dma_startup(struct uart_amba_port *uap) |
982 | { | |
ead76f32 LW |
983 | int ret; |
984 | ||
68b65f73 RK |
985 | if (!uap->dmatx.chan) |
986 | return; | |
987 | ||
988 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL); | |
989 | if (!uap->dmatx.buf) { | |
990 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
991 | uap->port.fifosize = uap->fifosize; | |
992 | return; | |
993 | } | |
994 | ||
995 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
996 | ||
997 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
998 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
999 | uap->using_tx_dma = true; |
1000 | ||
1001 | if (!uap->dmarx.chan) | |
1002 | goto skip_rx; | |
1003 | ||
1004 | /* Allocate and map DMA RX buffers */ | |
1005 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1006 | DMA_FROM_DEVICE); | |
1007 | if (ret) { | |
1008 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1009 | "RX buffer A", ret); | |
1010 | goto skip_rx; | |
1011 | } | |
68b65f73 | 1012 | |
ead76f32 LW |
1013 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
1014 | DMA_FROM_DEVICE); | |
1015 | if (ret) { | |
1016 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1017 | "RX buffer B", ret); | |
1018 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1019 | DMA_FROM_DEVICE); | |
1020 | goto skip_rx; | |
1021 | } | |
1022 | ||
1023 | uap->using_rx_dma = true; | |
68b65f73 | 1024 | |
ead76f32 | 1025 | skip_rx: |
68b65f73 RK |
1026 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
1027 | uap->dmacr |= UART011_DMAONERR; | |
1028 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
38d62436 RK |
1029 | |
1030 | /* | |
1031 | * ST Micro variants has some specific dma burst threshold | |
1032 | * compensation. Set this to 16 bytes, so burst will only | |
1033 | * be issued above/below 16 bytes. | |
1034 | */ | |
1035 | if (uap->vendor->dma_threshold) | |
1036 | writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, | |
1037 | uap->port.membase + ST_UART011_DMAWM); | |
ead76f32 LW |
1038 | |
1039 | if (uap->using_rx_dma) { | |
1040 | if (pl011_dma_rx_trigger_dma(uap)) | |
1041 | dev_dbg(uap->port.dev, "could not trigger initial " | |
1042 | "RX DMA job, fall back to interrupt mode\n"); | |
cb06ff10 CM |
1043 | if (uap->dmarx.poll_rate) { |
1044 | init_timer(&(uap->dmarx.timer)); | |
1045 | uap->dmarx.timer.function = pl011_dma_rx_poll; | |
1046 | uap->dmarx.timer.data = (unsigned long)uap; | |
1047 | mod_timer(&uap->dmarx.timer, | |
1048 | jiffies + | |
1049 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1050 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1051 | uap->dmarx.last_jiffies = jiffies; | |
1052 | } | |
ead76f32 | 1053 | } |
68b65f73 RK |
1054 | } |
1055 | ||
1056 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1057 | { | |
ead76f32 | 1058 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
1059 | return; |
1060 | ||
1061 | /* Disable RX and TX DMA */ | |
1062 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
1063 | barrier(); | |
1064 | ||
1065 | spin_lock_irq(&uap->port.lock); | |
1066 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
1067 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
1068 | spin_unlock_irq(&uap->port.lock); | |
1069 | ||
ead76f32 LW |
1070 | if (uap->using_tx_dma) { |
1071 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
1072 | dmaengine_terminate_all(uap->dmatx.chan); | |
1073 | if (uap->dmatx.queued) { | |
1074 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
1075 | DMA_TO_DEVICE); | |
1076 | uap->dmatx.queued = false; | |
1077 | } | |
1078 | ||
1079 | kfree(uap->dmatx.buf); | |
1080 | uap->using_tx_dma = false; | |
68b65f73 RK |
1081 | } |
1082 | ||
ead76f32 LW |
1083 | if (uap->using_rx_dma) { |
1084 | dmaengine_terminate_all(uap->dmarx.chan); | |
1085 | /* Clean up the RX DMA */ | |
1086 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); | |
1087 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); | |
cb06ff10 CM |
1088 | if (uap->dmarx.poll_rate) |
1089 | del_timer_sync(&uap->dmarx.timer); | |
ead76f32 LW |
1090 | uap->using_rx_dma = false; |
1091 | } | |
1092 | } | |
68b65f73 | 1093 | |
ead76f32 LW |
1094 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
1095 | { | |
1096 | return uap->using_rx_dma; | |
68b65f73 RK |
1097 | } |
1098 | ||
ead76f32 LW |
1099 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
1100 | { | |
1101 | return uap->using_rx_dma && uap->dmarx.running; | |
1102 | } | |
1103 | ||
68b65f73 RK |
1104 | #else |
1105 | /* Blank functions if the DMA engine is not available */ | |
aabdd290 | 1106 | static inline void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) |
68b65f73 RK |
1107 | { |
1108 | } | |
1109 | ||
1110 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
1111 | { | |
1112 | } | |
1113 | ||
1114 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
1115 | { | |
1116 | } | |
1117 | ||
1118 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1119 | { | |
1120 | } | |
1121 | ||
1122 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
1123 | { | |
1124 | return false; | |
1125 | } | |
1126 | ||
1127 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
1128 | { | |
1129 | } | |
1130 | ||
1131 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
1132 | { | |
1133 | return false; | |
1134 | } | |
1135 | ||
ead76f32 LW |
1136 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
1137 | { | |
1138 | } | |
1139 | ||
1140 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1141 | { | |
1142 | } | |
1143 | ||
1144 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
1145 | { | |
1146 | return -EIO; | |
1147 | } | |
1148 | ||
1149 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
1150 | { | |
1151 | return false; | |
1152 | } | |
1153 | ||
1154 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
1155 | { | |
1156 | return false; | |
1157 | } | |
1158 | ||
68b65f73 RK |
1159 | #define pl011_dma_flush_buffer NULL |
1160 | #endif | |
1161 | ||
b129a8cc | 1162 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 LT |
1163 | { |
1164 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1165 | ||
1166 | uap->im &= ~UART011_TXIM; | |
1167 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
68b65f73 | 1168 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
1169 | } |
1170 | ||
b129a8cc | 1171 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 LT |
1172 | { |
1173 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1174 | ||
68b65f73 RK |
1175 | if (!pl011_dma_tx_start(uap)) { |
1176 | uap->im |= UART011_TXIM; | |
1177 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1178 | } | |
1da177e4 LT |
1179 | } |
1180 | ||
1181 | static void pl011_stop_rx(struct uart_port *port) | |
1182 | { | |
1183 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1184 | ||
1185 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
1186 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
1187 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
ead76f32 LW |
1188 | |
1189 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1190 | } |
1191 | ||
1192 | static void pl011_enable_ms(struct uart_port *port) | |
1193 | { | |
1194 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1195 | ||
1196 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
1197 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1198 | } | |
1199 | ||
7d12e780 | 1200 | static void pl011_rx_chars(struct uart_amba_port *uap) |
b83286bf FE |
1201 | __releases(&uap->port.lock) |
1202 | __acquires(&uap->port.lock) | |
1da177e4 | 1203 | { |
29772c4e | 1204 | pl011_fifo_to_tty(uap); |
1da177e4 | 1205 | |
2389b272 | 1206 | spin_unlock(&uap->port.lock); |
2e124b4a | 1207 | tty_flip_buffer_push(&uap->port.state->port); |
ead76f32 LW |
1208 | /* |
1209 | * If we were temporarily out of DMA mode for a while, | |
1210 | * attempt to switch back to DMA mode again. | |
1211 | */ | |
1212 | if (pl011_dma_rx_available(uap)) { | |
1213 | if (pl011_dma_rx_trigger_dma(uap)) { | |
1214 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " | |
1215 | "fall back to interrupt mode again\n"); | |
1216 | uap->im |= UART011_RXIM; | |
cb06ff10 | 1217 | } else { |
ead76f32 | 1218 | uap->im &= ~UART011_RXIM; |
89fa28db | 1219 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1220 | /* Start Rx DMA poll */ |
1221 | if (uap->dmarx.poll_rate) { | |
1222 | uap->dmarx.last_jiffies = jiffies; | |
1223 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1224 | mod_timer(&uap->dmarx.timer, | |
1225 | jiffies + | |
1226 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1227 | } | |
89fa28db | 1228 | #endif |
cb06ff10 CM |
1229 | } |
1230 | ||
ead76f32 LW |
1231 | writew(uap->im, uap->port.membase + UART011_IMSC); |
1232 | } | |
2389b272 | 1233 | spin_lock(&uap->port.lock); |
1da177e4 LT |
1234 | } |
1235 | ||
1236 | static void pl011_tx_chars(struct uart_amba_port *uap) | |
1237 | { | |
ebd2c8f6 | 1238 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
1239 | int count; |
1240 | ||
1241 | if (uap->port.x_char) { | |
1242 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
1243 | uap->port.icount.tx++; | |
1244 | uap->port.x_char = 0; | |
1245 | return; | |
1246 | } | |
1247 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1248 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1249 | return; |
1250 | } | |
1251 | ||
68b65f73 RK |
1252 | /* If we are using DMA mode, try to send some characters. */ |
1253 | if (pl011_dma_tx_irq(uap)) | |
1254 | return; | |
1255 | ||
ffca2b11 | 1256 | count = uap->fifosize >> 1; |
1da177e4 LT |
1257 | do { |
1258 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); | |
1259 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1260 | uap->port.icount.tx++; | |
1261 | if (uart_circ_empty(xmit)) | |
1262 | break; | |
1263 | } while (--count > 0); | |
1264 | ||
1265 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1266 | uart_write_wakeup(&uap->port); | |
1267 | ||
1268 | if (uart_circ_empty(xmit)) | |
b129a8cc | 1269 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1270 | } |
1271 | ||
1272 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1273 | { | |
1274 | unsigned int status, delta; | |
1275 | ||
1276 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1277 | ||
1278 | delta = status ^ uap->old_status; | |
1279 | uap->old_status = status; | |
1280 | ||
1281 | if (!delta) | |
1282 | return; | |
1283 | ||
1284 | if (delta & UART01x_FR_DCD) | |
1285 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1286 | ||
1287 | if (delta & UART01x_FR_DSR) | |
1288 | uap->port.icount.dsr++; | |
1289 | ||
1290 | if (delta & UART01x_FR_CTS) | |
1291 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
1292 | ||
bdc04e31 | 1293 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1294 | } |
1295 | ||
7d12e780 | 1296 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1297 | { |
1298 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1299 | unsigned long flags; |
1da177e4 LT |
1300 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
1301 | int handled = 0; | |
4fd0690b | 1302 | unsigned int dummy_read; |
1da177e4 | 1303 | |
963cc981 | 1304 | spin_lock_irqsave(&uap->port.lock, flags); |
1da177e4 LT |
1305 | status = readw(uap->port.membase + UART011_MIS); |
1306 | if (status) { | |
1307 | do { | |
4fd0690b R |
1308 | if (uap->vendor->cts_event_workaround) { |
1309 | /* workaround to make sure that all bits are unlocked.. */ | |
1310 | writew(0x00, uap->port.membase + UART011_ICR); | |
1311 | ||
1312 | /* | |
1313 | * WA: introduce 26ns(1 uart clk) delay before W1C; | |
1314 | * single apb access will incur 2 pclk(133.12Mhz) delay, | |
1315 | * so add 2 dummy reads | |
1316 | */ | |
1317 | dummy_read = readw(uap->port.membase + UART011_ICR); | |
1318 | dummy_read = readw(uap->port.membase + UART011_ICR); | |
1319 | } | |
1320 | ||
1da177e4 LT |
1321 | writew(status & ~(UART011_TXIS|UART011_RTIS| |
1322 | UART011_RXIS), | |
1323 | uap->port.membase + UART011_ICR); | |
1324 | ||
ead76f32 LW |
1325 | if (status & (UART011_RTIS|UART011_RXIS)) { |
1326 | if (pl011_dma_rx_running(uap)) | |
1327 | pl011_dma_rx_irq(uap); | |
1328 | else | |
1329 | pl011_rx_chars(uap); | |
1330 | } | |
1da177e4 LT |
1331 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1332 | UART011_CTSMIS|UART011_RIMIS)) | |
1333 | pl011_modem_status(uap); | |
1334 | if (status & UART011_TXIS) | |
1335 | pl011_tx_chars(uap); | |
1336 | ||
4fd0690b | 1337 | if (pass_counter-- == 0) |
1da177e4 LT |
1338 | break; |
1339 | ||
1340 | status = readw(uap->port.membase + UART011_MIS); | |
1341 | } while (status != 0); | |
1342 | handled = 1; | |
1343 | } | |
1344 | ||
963cc981 | 1345 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
1346 | |
1347 | return IRQ_RETVAL(handled); | |
1348 | } | |
1349 | ||
e643f87f | 1350 | static unsigned int pl011_tx_empty(struct uart_port *port) |
1da177e4 LT |
1351 | { |
1352 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1353 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1354 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
1355 | } | |
1356 | ||
e643f87f | 1357 | static unsigned int pl011_get_mctrl(struct uart_port *port) |
1da177e4 LT |
1358 | { |
1359 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1360 | unsigned int result = 0; | |
1361 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1362 | ||
5159f407 | 1363 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
1364 | if (status & uartbit) \ |
1365 | result |= tiocmbit | |
1366 | ||
5159f407 JS |
1367 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
1368 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); | |
1369 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
1370 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
1371 | #undef TIOCMBIT | |
1da177e4 LT |
1372 | return result; |
1373 | } | |
1374 | ||
1375 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1376 | { | |
1377 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1378 | unsigned int cr; | |
1379 | ||
1380 | cr = readw(uap->port.membase + UART011_CR); | |
1381 | ||
5159f407 | 1382 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
1383 | if (mctrl & tiocmbit) \ |
1384 | cr |= uartbit; \ | |
1385 | else \ | |
1386 | cr &= ~uartbit | |
1387 | ||
5159f407 JS |
1388 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
1389 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
1390 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
1391 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
1392 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
1393 | |
1394 | if (uap->autorts) { | |
1395 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
1396 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
1397 | } | |
5159f407 | 1398 | #undef TIOCMBIT |
1da177e4 LT |
1399 | |
1400 | writew(cr, uap->port.membase + UART011_CR); | |
1401 | } | |
1402 | ||
1403 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1404 | { | |
1405 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1406 | unsigned long flags; | |
1407 | unsigned int lcr_h; | |
1408 | ||
1409 | spin_lock_irqsave(&uap->port.lock, flags); | |
ec489aa8 | 1410 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1411 | if (break_state == -1) |
1412 | lcr_h |= UART01x_LCRH_BRK; | |
1413 | else | |
1414 | lcr_h &= ~UART01x_LCRH_BRK; | |
ec489aa8 | 1415 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1416 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1417 | } | |
1418 | ||
84b5ae15 | 1419 | #ifdef CONFIG_CONSOLE_POLL |
5c8124a0 AV |
1420 | |
1421 | static void pl011_quiesce_irqs(struct uart_port *port) | |
1422 | { | |
1423 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1424 | unsigned char __iomem *regs = uap->port.membase; | |
1425 | ||
1426 | writew(readw(regs + UART011_MIS), regs + UART011_ICR); | |
1427 | /* | |
1428 | * There is no way to clear TXIM as this is "ready to transmit IRQ", so | |
1429 | * we simply mask it. start_tx() will unmask it. | |
1430 | * | |
1431 | * Note we can race with start_tx(), and if the race happens, the | |
1432 | * polling user might get another interrupt just after we clear it. | |
1433 | * But it should be OK and can happen even w/o the race, e.g. | |
1434 | * controller immediately got some new data and raised the IRQ. | |
1435 | * | |
1436 | * And whoever uses polling routines assumes that it manages the device | |
1437 | * (including tx queue), so we're also fine with start_tx()'s caller | |
1438 | * side. | |
1439 | */ | |
1440 | writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC); | |
1441 | } | |
1442 | ||
e643f87f | 1443 | static int pl011_get_poll_char(struct uart_port *port) |
84b5ae15 JW |
1444 | { |
1445 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1446 | unsigned int status; | |
1447 | ||
5c8124a0 AV |
1448 | /* |
1449 | * The caller might need IRQs lowered, e.g. if used with KDB NMI | |
1450 | * debugger. | |
1451 | */ | |
1452 | pl011_quiesce_irqs(port); | |
1453 | ||
f5316b4a JW |
1454 | status = readw(uap->port.membase + UART01x_FR); |
1455 | if (status & UART01x_FR_RXFE) | |
1456 | return NO_POLL_CHAR; | |
84b5ae15 JW |
1457 | |
1458 | return readw(uap->port.membase + UART01x_DR); | |
1459 | } | |
1460 | ||
e643f87f | 1461 | static void pl011_put_poll_char(struct uart_port *port, |
84b5ae15 JW |
1462 | unsigned char ch) |
1463 | { | |
1464 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1465 | ||
1466 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) | |
1467 | barrier(); | |
1468 | ||
1469 | writew(ch, uap->port.membase + UART01x_DR); | |
1470 | } | |
1471 | ||
1472 | #endif /* CONFIG_CONSOLE_POLL */ | |
1473 | ||
b3564c2c | 1474 | static int pl011_hwinit(struct uart_port *port) |
1da177e4 LT |
1475 | { |
1476 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1da177e4 LT |
1477 | int retval; |
1478 | ||
78d80c5a | 1479 | /* Optionaly enable pins to be muxed in and configured */ |
2b996fc5 | 1480 | pinctrl_pm_select_default_state(port->dev); |
78d80c5a | 1481 | |
1da177e4 LT |
1482 | /* |
1483 | * Try to enable the clock producer. | |
1484 | */ | |
1c4c4394 | 1485 | retval = clk_prepare_enable(uap->clk); |
1da177e4 | 1486 | if (retval) |
1c4c4394 | 1487 | goto out; |
1da177e4 LT |
1488 | |
1489 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1490 | ||
9b96fbac LW |
1491 | /* Clear pending error and receive interrupts */ |
1492 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS | | |
1493 | UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR); | |
1494 | ||
b3564c2c AV |
1495 | /* |
1496 | * Save interrupts enable mask, and enable RX interrupts in case if | |
1497 | * the interrupt is used for NMI entry. | |
1498 | */ | |
1499 | uap->im = readw(uap->port.membase + UART011_IMSC); | |
1500 | writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC); | |
1501 | ||
574de559 | 1502 | if (dev_get_platdata(uap->port.dev)) { |
b3564c2c AV |
1503 | struct amba_pl011_data *plat; |
1504 | ||
574de559 | 1505 | plat = dev_get_platdata(uap->port.dev); |
b3564c2c AV |
1506 | if (plat->init) |
1507 | plat->init(); | |
1508 | } | |
1509 | return 0; | |
1510 | out: | |
1511 | return retval; | |
1512 | } | |
1513 | ||
b60f2f66 JM |
1514 | static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) |
1515 | { | |
1516 | writew(lcr_h, uap->port.membase + uap->lcrh_rx); | |
1517 | if (uap->lcrh_rx != uap->lcrh_tx) { | |
1518 | int i; | |
1519 | /* | |
1520 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1521 | * to get this delay write read only register 10 times | |
1522 | */ | |
1523 | for (i = 0; i < 10; ++i) | |
1524 | writew(0xff, uap->port.membase + UART011_MIS); | |
1525 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); | |
1526 | } | |
1527 | } | |
1528 | ||
b3564c2c AV |
1529 | static int pl011_startup(struct uart_port *port) |
1530 | { | |
1531 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1532 | unsigned int cr; | |
1533 | int retval; | |
1534 | ||
1535 | retval = pl011_hwinit(port); | |
1536 | if (retval) | |
1537 | goto clk_dis; | |
1538 | ||
1539 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1540 | ||
1da177e4 LT |
1541 | /* |
1542 | * Allocate the IRQ | |
1543 | */ | |
1544 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
1545 | if (retval) | |
1546 | goto clk_dis; | |
1547 | ||
c19f12b5 | 1548 | writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); |
1da177e4 LT |
1549 | |
1550 | /* | |
1551 | * Provoke TX FIFO interrupt into asserting. | |
1552 | */ | |
fe433907 JM |
1553 | spin_lock_irq(&uap->port.lock); |
1554 | ||
1da177e4 LT |
1555 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; |
1556 | writew(cr, uap->port.membase + UART011_CR); | |
1557 | writew(0, uap->port.membase + UART011_FBRD); | |
1558 | writew(1, uap->port.membase + UART011_IBRD); | |
b60f2f66 | 1559 | pl011_write_lcr_h(uap, 0); |
1da177e4 LT |
1560 | writew(0, uap->port.membase + UART01x_DR); |
1561 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
1562 | barrier(); | |
1563 | ||
d8d8ffa4 SKS |
1564 | /* restore RTS and DTR */ |
1565 | cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); | |
1566 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
1da177e4 LT |
1567 | writew(cr, uap->port.membase + UART011_CR); |
1568 | ||
fe433907 JM |
1569 | spin_unlock_irq(&uap->port.lock); |
1570 | ||
1da177e4 LT |
1571 | /* |
1572 | * initialise the old status of the modem signals | |
1573 | */ | |
1574 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1575 | ||
68b65f73 RK |
1576 | /* Startup DMA */ |
1577 | pl011_dma_startup(uap); | |
1578 | ||
1da177e4 | 1579 | /* |
ead76f32 LW |
1580 | * Finally, enable interrupts, only timeouts when using DMA |
1581 | * if initial RX DMA job failed, start in interrupt mode | |
1582 | * as well. | |
1da177e4 LT |
1583 | */ |
1584 | spin_lock_irq(&uap->port.lock); | |
9b96fbac LW |
1585 | /* Clear out any spuriously appearing RX interrupts */ |
1586 | writew(UART011_RTIS | UART011_RXIS, | |
1587 | uap->port.membase + UART011_ICR); | |
ead76f32 LW |
1588 | uap->im = UART011_RTIM; |
1589 | if (!pl011_dma_rx_running(uap)) | |
1590 | uap->im |= UART011_RXIM; | |
1da177e4 LT |
1591 | writew(uap->im, uap->port.membase + UART011_IMSC); |
1592 | spin_unlock_irq(&uap->port.lock); | |
1593 | ||
1594 | return 0; | |
1595 | ||
1596 | clk_dis: | |
1c4c4394 | 1597 | clk_disable_unprepare(uap->clk); |
1da177e4 LT |
1598 | return retval; |
1599 | } | |
1600 | ||
ec489aa8 LW |
1601 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
1602 | unsigned int lcrh) | |
1603 | { | |
1604 | unsigned long val; | |
1605 | ||
1606 | val = readw(uap->port.membase + lcrh); | |
1607 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
1608 | writew(val, uap->port.membase + lcrh); | |
1609 | } | |
1610 | ||
1da177e4 LT |
1611 | static void pl011_shutdown(struct uart_port *port) |
1612 | { | |
1613 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
d8d8ffa4 | 1614 | unsigned int cr; |
1da177e4 LT |
1615 | |
1616 | /* | |
1617 | * disable all interrupts | |
1618 | */ | |
1619 | spin_lock_irq(&uap->port.lock); | |
1620 | uap->im = 0; | |
1621 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1622 | writew(0xffff, uap->port.membase + UART011_ICR); | |
1623 | spin_unlock_irq(&uap->port.lock); | |
1624 | ||
68b65f73 RK |
1625 | pl011_dma_shutdown(uap); |
1626 | ||
1da177e4 LT |
1627 | /* |
1628 | * Free the interrupt | |
1629 | */ | |
1630 | free_irq(uap->port.irq, uap); | |
1631 | ||
1632 | /* | |
1633 | * disable the port | |
d8d8ffa4 SKS |
1634 | * disable the port. It should not disable RTS and DTR. |
1635 | * Also RTS and DTR state should be preserved to restore | |
1636 | * it during startup(). | |
1da177e4 | 1637 | */ |
3b43816f | 1638 | uap->autorts = false; |
fe433907 | 1639 | spin_lock_irq(&uap->port.lock); |
d8d8ffa4 SKS |
1640 | cr = readw(uap->port.membase + UART011_CR); |
1641 | uap->old_cr = cr; | |
1642 | cr &= UART011_CR_RTS | UART011_CR_DTR; | |
1643 | cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1644 | writew(cr, uap->port.membase + UART011_CR); | |
fe433907 | 1645 | spin_unlock_irq(&uap->port.lock); |
1da177e4 LT |
1646 | |
1647 | /* | |
1648 | * disable break condition and fifos | |
1649 | */ | |
ec489aa8 LW |
1650 | pl011_shutdown_channel(uap, uap->lcrh_rx); |
1651 | if (uap->lcrh_rx != uap->lcrh_tx) | |
1652 | pl011_shutdown_channel(uap, uap->lcrh_tx); | |
1da177e4 LT |
1653 | |
1654 | /* | |
1655 | * Shut down the clock producer | |
1656 | */ | |
1c4c4394 | 1657 | clk_disable_unprepare(uap->clk); |
78d80c5a | 1658 | /* Optionally let pins go into sleep states */ |
2b996fc5 | 1659 | pinctrl_pm_select_sleep_state(port->dev); |
c16d51a3 | 1660 | |
574de559 | 1661 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
1662 | struct amba_pl011_data *plat; |
1663 | ||
574de559 | 1664 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
1665 | if (plat->exit) |
1666 | plat->exit(); | |
1667 | } | |
1668 | ||
1da177e4 LT |
1669 | } |
1670 | ||
1671 | static void | |
606d099c AC |
1672 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1673 | struct ktermios *old) | |
1da177e4 | 1674 | { |
3b43816f | 1675 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 LT |
1676 | unsigned int lcr_h, old_cr; |
1677 | unsigned long flags; | |
c19f12b5 RK |
1678 | unsigned int baud, quot, clkdiv; |
1679 | ||
1680 | if (uap->vendor->oversampling) | |
1681 | clkdiv = 8; | |
1682 | else | |
1683 | clkdiv = 16; | |
1da177e4 LT |
1684 | |
1685 | /* | |
1686 | * Ask the core to calculate the divisor for us. | |
1687 | */ | |
ac3e3fb4 | 1688 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1689 | port->uartclk / clkdiv); |
89fa28db | 1690 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1691 | /* |
1692 | * Adjust RX DMA polling rate with baud rate if not specified. | |
1693 | */ | |
1694 | if (uap->dmarx.auto_poll_rate) | |
1695 | uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); | |
89fa28db | 1696 | #endif |
ac3e3fb4 LW |
1697 | |
1698 | if (baud > port->uartclk/16) | |
1699 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1700 | else | |
1701 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1702 | |
1703 | switch (termios->c_cflag & CSIZE) { | |
1704 | case CS5: | |
1705 | lcr_h = UART01x_LCRH_WLEN_5; | |
1706 | break; | |
1707 | case CS6: | |
1708 | lcr_h = UART01x_LCRH_WLEN_6; | |
1709 | break; | |
1710 | case CS7: | |
1711 | lcr_h = UART01x_LCRH_WLEN_7; | |
1712 | break; | |
1713 | default: // CS8 | |
1714 | lcr_h = UART01x_LCRH_WLEN_8; | |
1715 | break; | |
1716 | } | |
1717 | if (termios->c_cflag & CSTOPB) | |
1718 | lcr_h |= UART01x_LCRH_STP2; | |
1719 | if (termios->c_cflag & PARENB) { | |
1720 | lcr_h |= UART01x_LCRH_PEN; | |
1721 | if (!(termios->c_cflag & PARODD)) | |
1722 | lcr_h |= UART01x_LCRH_EPS; | |
1723 | } | |
ffca2b11 | 1724 | if (uap->fifosize > 1) |
1da177e4 LT |
1725 | lcr_h |= UART01x_LCRH_FEN; |
1726 | ||
1727 | spin_lock_irqsave(&port->lock, flags); | |
1728 | ||
1729 | /* | |
1730 | * Update the per-port timeout. | |
1731 | */ | |
1732 | uart_update_timeout(port, termios->c_cflag, baud); | |
1733 | ||
b63d4f0f | 1734 | port->read_status_mask = UART011_DR_OE | 255; |
1da177e4 | 1735 | if (termios->c_iflag & INPCK) |
b63d4f0f | 1736 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1737 | if (termios->c_iflag & (BRKINT | PARMRK)) |
b63d4f0f | 1738 | port->read_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1739 | |
1740 | /* | |
1741 | * Characters to ignore | |
1742 | */ | |
1743 | port->ignore_status_mask = 0; | |
1744 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1745 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1746 | if (termios->c_iflag & IGNBRK) { |
b63d4f0f | 1747 | port->ignore_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1748 | /* |
1749 | * If we're ignoring parity and break indicators, | |
1750 | * ignore overruns too (for real raw support). | |
1751 | */ | |
1752 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1753 | port->ignore_status_mask |= UART011_DR_OE; |
1da177e4 LT |
1754 | } |
1755 | ||
1756 | /* | |
1757 | * Ignore all characters if CREAD is not set. | |
1758 | */ | |
1759 | if ((termios->c_cflag & CREAD) == 0) | |
b63d4f0f | 1760 | port->ignore_status_mask |= UART_DUMMY_DR_RX; |
1da177e4 LT |
1761 | |
1762 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1763 | pl011_enable_ms(port); | |
1764 | ||
1765 | /* first, disable everything */ | |
1766 | old_cr = readw(port->membase + UART011_CR); | |
1767 | writew(0, port->membase + UART011_CR); | |
1768 | ||
3b43816f RV |
1769 | if (termios->c_cflag & CRTSCTS) { |
1770 | if (old_cr & UART011_CR_RTS) | |
1771 | old_cr |= UART011_CR_RTSEN; | |
1772 | ||
1773 | old_cr |= UART011_CR_CTSEN; | |
1774 | uap->autorts = true; | |
1775 | } else { | |
1776 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1777 | uap->autorts = false; | |
1778 | } | |
1779 | ||
c19f12b5 RK |
1780 | if (uap->vendor->oversampling) { |
1781 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1782 | old_cr |= ST_UART011_CR_OVSFACT; |
1783 | else | |
1784 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1785 | } | |
1786 | ||
c5dd553b LW |
1787 | /* |
1788 | * Workaround for the ST Micro oversampling variants to | |
1789 | * increase the bitrate slightly, by lowering the divisor, | |
1790 | * to avoid delayed sampling of start bit at high speeds, | |
1791 | * else we see data corruption. | |
1792 | */ | |
1793 | if (uap->vendor->oversampling) { | |
1794 | if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) | |
1795 | quot -= 1; | |
1796 | else if ((baud > 3250000) && (quot > 2)) | |
1797 | quot -= 2; | |
1798 | } | |
1da177e4 LT |
1799 | /* Set baud rate */ |
1800 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
1801 | writew(quot >> 6, port->membase + UART011_IBRD); | |
1802 | ||
1803 | /* | |
1804 | * ----------v----------v----------v----------v----- | |
c5dd553b LW |
1805 | * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER |
1806 | * UART011_FBRD & UART011_IBRD. | |
1da177e4 LT |
1807 | * ----------^----------^----------^----------^----- |
1808 | */ | |
b60f2f66 | 1809 | pl011_write_lcr_h(uap, lcr_h); |
1da177e4 LT |
1810 | writew(old_cr, port->membase + UART011_CR); |
1811 | ||
1812 | spin_unlock_irqrestore(&port->lock, flags); | |
1813 | } | |
1814 | ||
1815 | static const char *pl011_type(struct uart_port *port) | |
1816 | { | |
e8a7ba86 RK |
1817 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1818 | return uap->port.type == PORT_AMBA ? uap->type : NULL; | |
1da177e4 LT |
1819 | } |
1820 | ||
1821 | /* | |
1822 | * Release the memory region(s) being used by 'port' | |
1823 | */ | |
e643f87f | 1824 | static void pl011_release_port(struct uart_port *port) |
1da177e4 LT |
1825 | { |
1826 | release_mem_region(port->mapbase, SZ_4K); | |
1827 | } | |
1828 | ||
1829 | /* | |
1830 | * Request the memory region(s) being used by 'port' | |
1831 | */ | |
e643f87f | 1832 | static int pl011_request_port(struct uart_port *port) |
1da177e4 LT |
1833 | { |
1834 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
1835 | != NULL ? 0 : -EBUSY; | |
1836 | } | |
1837 | ||
1838 | /* | |
1839 | * Configure/autoconfigure the port. | |
1840 | */ | |
e643f87f | 1841 | static void pl011_config_port(struct uart_port *port, int flags) |
1da177e4 LT |
1842 | { |
1843 | if (flags & UART_CONFIG_TYPE) { | |
1844 | port->type = PORT_AMBA; | |
e643f87f | 1845 | pl011_request_port(port); |
1da177e4 LT |
1846 | } |
1847 | } | |
1848 | ||
1849 | /* | |
1850 | * verify the new serial_struct (for TIOCSSERIAL). | |
1851 | */ | |
e643f87f | 1852 | static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) |
1da177e4 LT |
1853 | { |
1854 | int ret = 0; | |
1855 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
1856 | ret = -EINVAL; | |
a62c4133 | 1857 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
1858 | ret = -EINVAL; |
1859 | if (ser->baud_base < 9600) | |
1860 | ret = -EINVAL; | |
1861 | return ret; | |
1862 | } | |
1863 | ||
1864 | static struct uart_ops amba_pl011_pops = { | |
e643f87f | 1865 | .tx_empty = pl011_tx_empty, |
1da177e4 | 1866 | .set_mctrl = pl011_set_mctrl, |
e643f87f | 1867 | .get_mctrl = pl011_get_mctrl, |
1da177e4 LT |
1868 | .stop_tx = pl011_stop_tx, |
1869 | .start_tx = pl011_start_tx, | |
1870 | .stop_rx = pl011_stop_rx, | |
1871 | .enable_ms = pl011_enable_ms, | |
1872 | .break_ctl = pl011_break_ctl, | |
1873 | .startup = pl011_startup, | |
1874 | .shutdown = pl011_shutdown, | |
68b65f73 | 1875 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
1876 | .set_termios = pl011_set_termios, |
1877 | .type = pl011_type, | |
e643f87f LW |
1878 | .release_port = pl011_release_port, |
1879 | .request_port = pl011_request_port, | |
1880 | .config_port = pl011_config_port, | |
1881 | .verify_port = pl011_verify_port, | |
84b5ae15 | 1882 | #ifdef CONFIG_CONSOLE_POLL |
b3564c2c | 1883 | .poll_init = pl011_hwinit, |
e643f87f LW |
1884 | .poll_get_char = pl011_get_poll_char, |
1885 | .poll_put_char = pl011_put_poll_char, | |
84b5ae15 | 1886 | #endif |
1da177e4 LT |
1887 | }; |
1888 | ||
1889 | static struct uart_amba_port *amba_ports[UART_NR]; | |
1890 | ||
1891 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
1892 | ||
d358788f | 1893 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 1894 | { |
d358788f | 1895 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 | 1896 | |
d358788f RK |
1897 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
1898 | barrier(); | |
1da177e4 LT |
1899 | writew(ch, uap->port.membase + UART01x_DR); |
1900 | } | |
1901 | ||
1902 | static void | |
1903 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
1904 | { | |
1905 | struct uart_amba_port *uap = amba_ports[co->index]; | |
1906 | unsigned int status, old_cr, new_cr; | |
ef605fdb RV |
1907 | unsigned long flags; |
1908 | int locked = 1; | |
1da177e4 LT |
1909 | |
1910 | clk_enable(uap->clk); | |
1911 | ||
ef605fdb RV |
1912 | local_irq_save(flags); |
1913 | if (uap->port.sysrq) | |
1914 | locked = 0; | |
1915 | else if (oops_in_progress) | |
1916 | locked = spin_trylock(&uap->port.lock); | |
1917 | else | |
1918 | spin_lock(&uap->port.lock); | |
1919 | ||
1da177e4 LT |
1920 | /* |
1921 | * First save the CR then disable the interrupts | |
1922 | */ | |
1923 | old_cr = readw(uap->port.membase + UART011_CR); | |
1924 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
1925 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1926 | writew(new_cr, uap->port.membase + UART011_CR); | |
1927 | ||
d358788f | 1928 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
1929 | |
1930 | /* | |
1931 | * Finally, wait for transmitter to become empty | |
1932 | * and restore the TCR | |
1933 | */ | |
1934 | do { | |
1935 | status = readw(uap->port.membase + UART01x_FR); | |
1936 | } while (status & UART01x_FR_BUSY); | |
1937 | writew(old_cr, uap->port.membase + UART011_CR); | |
1938 | ||
ef605fdb RV |
1939 | if (locked) |
1940 | spin_unlock(&uap->port.lock); | |
1941 | local_irq_restore(flags); | |
1942 | ||
1da177e4 LT |
1943 | clk_disable(uap->clk); |
1944 | } | |
1945 | ||
1946 | static void __init | |
1947 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
1948 | int *parity, int *bits) | |
1949 | { | |
1950 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
1951 | unsigned int lcr_h, ibrd, fbrd; | |
1952 | ||
ec489aa8 | 1953 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1954 | |
1955 | *parity = 'n'; | |
1956 | if (lcr_h & UART01x_LCRH_PEN) { | |
1957 | if (lcr_h & UART01x_LCRH_EPS) | |
1958 | *parity = 'e'; | |
1959 | else | |
1960 | *parity = 'o'; | |
1961 | } | |
1962 | ||
1963 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
1964 | *bits = 7; | |
1965 | else | |
1966 | *bits = 8; | |
1967 | ||
1968 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
1969 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
1970 | ||
1971 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 1972 | |
c19f12b5 | 1973 | if (uap->vendor->oversampling) { |
ac3e3fb4 LW |
1974 | if (readw(uap->port.membase + UART011_CR) |
1975 | & ST_UART011_CR_OVSFACT) | |
1976 | *baud *= 2; | |
1977 | } | |
1da177e4 LT |
1978 | } |
1979 | } | |
1980 | ||
1981 | static int __init pl011_console_setup(struct console *co, char *options) | |
1982 | { | |
1983 | struct uart_amba_port *uap; | |
1984 | int baud = 38400; | |
1985 | int bits = 8; | |
1986 | int parity = 'n'; | |
1987 | int flow = 'n'; | |
4b4851c6 | 1988 | int ret; |
1da177e4 LT |
1989 | |
1990 | /* | |
1991 | * Check whether an invalid uart number has been specified, and | |
1992 | * if so, search for the first available port that does have | |
1993 | * console support. | |
1994 | */ | |
1995 | if (co->index >= UART_NR) | |
1996 | co->index = 0; | |
1997 | uap = amba_ports[co->index]; | |
d28122a5 RK |
1998 | if (!uap) |
1999 | return -ENODEV; | |
1da177e4 | 2000 | |
78d80c5a | 2001 | /* Allow pins to be muxed in and configured */ |
2b996fc5 | 2002 | pinctrl_pm_select_default_state(uap->port.dev); |
78d80c5a | 2003 | |
4b4851c6 RK |
2004 | ret = clk_prepare(uap->clk); |
2005 | if (ret) | |
2006 | return ret; | |
2007 | ||
574de559 | 2008 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
2009 | struct amba_pl011_data *plat; |
2010 | ||
574de559 | 2011 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
2012 | if (plat->init) |
2013 | plat->init(); | |
2014 | } | |
2015 | ||
1da177e4 LT |
2016 | uap->port.uartclk = clk_get_rate(uap->clk); |
2017 | ||
2018 | if (options) | |
2019 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2020 | else | |
2021 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
2022 | ||
2023 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
2024 | } | |
2025 | ||
2d93486c | 2026 | static struct uart_driver amba_reg; |
1da177e4 LT |
2027 | static struct console amba_console = { |
2028 | .name = "ttyAMA", | |
2029 | .write = pl011_console_write, | |
2030 | .device = uart_console_device, | |
2031 | .setup = pl011_console_setup, | |
2032 | .flags = CON_PRINTBUFFER, | |
2033 | .index = -1, | |
2034 | .data = &amba_reg, | |
2035 | }; | |
2036 | ||
2037 | #define AMBA_CONSOLE (&amba_console) | |
2038 | #else | |
2039 | #define AMBA_CONSOLE NULL | |
2040 | #endif | |
2041 | ||
2042 | static struct uart_driver amba_reg = { | |
2043 | .owner = THIS_MODULE, | |
2044 | .driver_name = "ttyAMA", | |
2045 | .dev_name = "ttyAMA", | |
2046 | .major = SERIAL_AMBA_MAJOR, | |
2047 | .minor = SERIAL_AMBA_MINOR, | |
2048 | .nr = UART_NR, | |
2049 | .cons = AMBA_CONSOLE, | |
2050 | }; | |
2051 | ||
32614aad ML |
2052 | static int pl011_probe_dt_alias(int index, struct device *dev) |
2053 | { | |
2054 | struct device_node *np; | |
2055 | static bool seen_dev_with_alias = false; | |
2056 | static bool seen_dev_without_alias = false; | |
2057 | int ret = index; | |
2058 | ||
2059 | if (!IS_ENABLED(CONFIG_OF)) | |
2060 | return ret; | |
2061 | ||
2062 | np = dev->of_node; | |
2063 | if (!np) | |
2064 | return ret; | |
2065 | ||
2066 | ret = of_alias_get_id(np, "serial"); | |
2067 | if (IS_ERR_VALUE(ret)) { | |
2068 | seen_dev_without_alias = true; | |
2069 | ret = index; | |
2070 | } else { | |
2071 | seen_dev_with_alias = true; | |
2072 | if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { | |
2073 | dev_warn(dev, "requested serial port %d not available.\n", ret); | |
2074 | ret = index; | |
2075 | } | |
2076 | } | |
2077 | ||
2078 | if (seen_dev_with_alias && seen_dev_without_alias) | |
2079 | dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); | |
2080 | ||
2081 | return ret; | |
2082 | } | |
2083 | ||
aa25afad | 2084 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
1da177e4 LT |
2085 | { |
2086 | struct uart_amba_port *uap; | |
5926a295 | 2087 | struct vendor_data *vendor = id->data; |
1da177e4 LT |
2088 | void __iomem *base; |
2089 | int i, ret; | |
2090 | ||
2091 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
2092 | if (amba_ports[i] == NULL) | |
2093 | break; | |
2094 | ||
2095 | if (i == ARRAY_SIZE(amba_ports)) { | |
2096 | ret = -EBUSY; | |
2097 | goto out; | |
2098 | } | |
2099 | ||
de609582 LW |
2100 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), |
2101 | GFP_KERNEL); | |
1da177e4 LT |
2102 | if (uap == NULL) { |
2103 | ret = -ENOMEM; | |
2104 | goto out; | |
2105 | } | |
2106 | ||
32614aad ML |
2107 | i = pl011_probe_dt_alias(i, &dev->dev); |
2108 | ||
de609582 LW |
2109 | base = devm_ioremap(&dev->dev, dev->res.start, |
2110 | resource_size(&dev->res)); | |
1da177e4 LT |
2111 | if (!base) { |
2112 | ret = -ENOMEM; | |
de609582 | 2113 | goto out; |
1da177e4 LT |
2114 | } |
2115 | ||
de609582 | 2116 | uap->clk = devm_clk_get(&dev->dev, NULL); |
1da177e4 LT |
2117 | if (IS_ERR(uap->clk)) { |
2118 | ret = PTR_ERR(uap->clk); | |
de609582 | 2119 | goto out; |
1da177e4 LT |
2120 | } |
2121 | ||
c19f12b5 | 2122 | uap->vendor = vendor; |
ec489aa8 LW |
2123 | uap->lcrh_rx = vendor->lcrh_rx; |
2124 | uap->lcrh_tx = vendor->lcrh_tx; | |
d8d8ffa4 | 2125 | uap->old_cr = 0; |
ea33640a | 2126 | uap->fifosize = vendor->get_fifosize(dev); |
1da177e4 LT |
2127 | uap->port.dev = &dev->dev; |
2128 | uap->port.mapbase = dev->res.start; | |
2129 | uap->port.membase = base; | |
2130 | uap->port.iotype = UPIO_MEM; | |
2131 | uap->port.irq = dev->irq[0]; | |
ffca2b11 | 2132 | uap->port.fifosize = uap->fifosize; |
1da177e4 LT |
2133 | uap->port.ops = &amba_pl011_pops; |
2134 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
2135 | uap->port.line = i; | |
787b0c1f | 2136 | pl011_dma_probe(&dev->dev, uap); |
1da177e4 | 2137 | |
c3d8b76f LW |
2138 | /* Ensure interrupts from this UART are masked and cleared */ |
2139 | writew(0, uap->port.membase + UART011_IMSC); | |
2140 | writew(0xffff, uap->port.membase + UART011_ICR); | |
2141 | ||
e8a7ba86 RK |
2142 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); |
2143 | ||
1da177e4 LT |
2144 | amba_ports[i] = uap; |
2145 | ||
2146 | amba_set_drvdata(dev, uap); | |
2147 | ret = uart_add_one_port(&amba_reg, &uap->port); | |
2148 | if (ret) { | |
1da177e4 | 2149 | amba_ports[i] = NULL; |
68b65f73 | 2150 | pl011_dma_remove(uap); |
1da177e4 LT |
2151 | } |
2152 | out: | |
2153 | return ret; | |
2154 | } | |
2155 | ||
2156 | static int pl011_remove(struct amba_device *dev) | |
2157 | { | |
2158 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
2159 | int i; | |
2160 | ||
1da177e4 LT |
2161 | uart_remove_one_port(&amba_reg, &uap->port); |
2162 | ||
2163 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
2164 | if (amba_ports[i] == uap) | |
2165 | amba_ports[i] = NULL; | |
2166 | ||
68b65f73 | 2167 | pl011_dma_remove(uap); |
1da177e4 LT |
2168 | return 0; |
2169 | } | |
2170 | ||
d0ce850d UH |
2171 | #ifdef CONFIG_PM_SLEEP |
2172 | static int pl011_suspend(struct device *dev) | |
b736b89f | 2173 | { |
d0ce850d | 2174 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2175 | |
2176 | if (!uap) | |
2177 | return -EINVAL; | |
2178 | ||
2179 | return uart_suspend_port(&amba_reg, &uap->port); | |
2180 | } | |
2181 | ||
d0ce850d | 2182 | static int pl011_resume(struct device *dev) |
b736b89f | 2183 | { |
d0ce850d | 2184 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2185 | |
2186 | if (!uap) | |
2187 | return -EINVAL; | |
2188 | ||
2189 | return uart_resume_port(&amba_reg, &uap->port); | |
2190 | } | |
2191 | #endif | |
2192 | ||
d0ce850d UH |
2193 | static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); |
2194 | ||
2c39c9e1 | 2195 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
2196 | { |
2197 | .id = 0x00041011, | |
2198 | .mask = 0x000fffff, | |
5926a295 AR |
2199 | .data = &vendor_arm, |
2200 | }, | |
2201 | { | |
2202 | .id = 0x00380802, | |
2203 | .mask = 0x00ffffff, | |
2204 | .data = &vendor_st, | |
1da177e4 LT |
2205 | }, |
2206 | { 0, 0 }, | |
2207 | }; | |
2208 | ||
60f7a33b DM |
2209 | MODULE_DEVICE_TABLE(amba, pl011_ids); |
2210 | ||
1da177e4 LT |
2211 | static struct amba_driver pl011_driver = { |
2212 | .drv = { | |
2213 | .name = "uart-pl011", | |
d0ce850d | 2214 | .pm = &pl011_dev_pm_ops, |
1da177e4 LT |
2215 | }, |
2216 | .id_table = pl011_ids, | |
2217 | .probe = pl011_probe, | |
2218 | .remove = pl011_remove, | |
2219 | }; | |
2220 | ||
2221 | static int __init pl011_init(void) | |
2222 | { | |
2223 | int ret; | |
2224 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); | |
2225 | ||
2226 | ret = uart_register_driver(&amba_reg); | |
2227 | if (ret == 0) { | |
2228 | ret = amba_driver_register(&pl011_driver); | |
2229 | if (ret) | |
2230 | uart_unregister_driver(&amba_reg); | |
2231 | } | |
2232 | return ret; | |
2233 | } | |
2234 | ||
2235 | static void __exit pl011_exit(void) | |
2236 | { | |
2237 | amba_driver_unregister(&pl011_driver); | |
2238 | uart_unregister_driver(&amba_reg); | |
2239 | } | |
2240 | ||
4dd9e742 AR |
2241 | /* |
2242 | * While this can be a module, if builtin it's most likely the console | |
2243 | * So let's leave module_exit but move module_init to an earlier place | |
2244 | */ | |
2245 | arch_initcall(pl011_init); | |
1da177e4 LT |
2246 | module_exit(pl011_exit); |
2247 | ||
2248 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
2249 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
2250 | MODULE_LICENSE("GPL"); |