]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/char/amba.c | |
3 | * | |
4 | * Driver for AMBA serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
8 | * Copyright 1999 ARM Limited | |
9 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 10 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
1da177e4 LT |
26 | * This is a generic driver for ARM AMBA-type serial ports. They |
27 | * have a lot of 16550-like features, but are not register compatible. | |
28 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
29 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
30 | * required, these have to be supplied via some other means (eg, GPIO) | |
31 | * and hooked into this driver. | |
32 | */ | |
1da177e4 LT |
33 | |
34 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
35 | #define SUPPORT_SYSRQ | |
36 | #endif | |
37 | ||
38 | #include <linux/module.h> | |
39 | #include <linux/ioport.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/console.h> | |
42 | #include <linux/sysrq.h> | |
43 | #include <linux/device.h> | |
44 | #include <linux/tty.h> | |
45 | #include <linux/tty_flip.h> | |
46 | #include <linux/serial_core.h> | |
47 | #include <linux/serial.h> | |
a62c80e5 RK |
48 | #include <linux/amba/bus.h> |
49 | #include <linux/amba/serial.h> | |
f8ce2547 | 50 | #include <linux/clk.h> |
5a0e3ad6 | 51 | #include <linux/slab.h> |
68b65f73 RK |
52 | #include <linux/dmaengine.h> |
53 | #include <linux/dma-mapping.h> | |
54 | #include <linux/scatterlist.h> | |
1da177e4 LT |
55 | |
56 | #include <asm/io.h> | |
c6b8fdad | 57 | #include <asm/sizes.h> |
1da177e4 LT |
58 | |
59 | #define UART_NR 14 | |
60 | ||
61 | #define SERIAL_AMBA_MAJOR 204 | |
62 | #define SERIAL_AMBA_MINOR 64 | |
63 | #define SERIAL_AMBA_NR UART_NR | |
64 | ||
65 | #define AMBA_ISR_PASS_LIMIT 256 | |
66 | ||
b63d4f0f RK |
67 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
68 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 69 | |
5926a295 AR |
70 | /* There is by now at least one vendor with differing details, so handle it */ |
71 | struct vendor_data { | |
72 | unsigned int ifls; | |
73 | unsigned int fifosize; | |
ec489aa8 LW |
74 | unsigned int lcrh_tx; |
75 | unsigned int lcrh_rx; | |
ac3e3fb4 | 76 | bool oversampling; |
38d62436 | 77 | bool dma_threshold; |
5926a295 AR |
78 | }; |
79 | ||
80 | static struct vendor_data vendor_arm = { | |
81 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
82 | .fifosize = 16, | |
ec489aa8 LW |
83 | .lcrh_tx = UART011_LCRH, |
84 | .lcrh_rx = UART011_LCRH, | |
ac3e3fb4 | 85 | .oversampling = false, |
38d62436 | 86 | .dma_threshold = false, |
5926a295 AR |
87 | }; |
88 | ||
89 | static struct vendor_data vendor_st = { | |
90 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, | |
91 | .fifosize = 64, | |
ec489aa8 LW |
92 | .lcrh_tx = ST_UART011_LCRH_TX, |
93 | .lcrh_rx = ST_UART011_LCRH_RX, | |
ac3e3fb4 | 94 | .oversampling = true, |
38d62436 | 95 | .dma_threshold = true, |
1da177e4 LT |
96 | }; |
97 | ||
68b65f73 | 98 | /* Deals with DMA transactions */ |
ead76f32 LW |
99 | |
100 | struct pl011_sgbuf { | |
101 | struct scatterlist sg; | |
102 | char *buf; | |
103 | }; | |
104 | ||
105 | struct pl011_dmarx_data { | |
106 | struct dma_chan *chan; | |
107 | struct completion complete; | |
108 | bool use_buf_b; | |
109 | struct pl011_sgbuf sgbuf_a; | |
110 | struct pl011_sgbuf sgbuf_b; | |
111 | dma_cookie_t cookie; | |
112 | bool running; | |
113 | }; | |
114 | ||
68b65f73 RK |
115 | struct pl011_dmatx_data { |
116 | struct dma_chan *chan; | |
117 | struct scatterlist sg; | |
118 | char *buf; | |
119 | bool queued; | |
120 | }; | |
121 | ||
c19f12b5 RK |
122 | /* |
123 | * We wrap our port structure around the generic uart_port. | |
124 | */ | |
125 | struct uart_amba_port { | |
126 | struct uart_port port; | |
127 | struct clk *clk; | |
128 | const struct vendor_data *vendor; | |
68b65f73 | 129 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
130 | unsigned int im; /* interrupt mask */ |
131 | unsigned int old_status; | |
ffca2b11 | 132 | unsigned int fifosize; /* vendor-specific */ |
c19f12b5 RK |
133 | unsigned int lcrh_tx; /* vendor-specific */ |
134 | unsigned int lcrh_rx; /* vendor-specific */ | |
135 | bool autorts; | |
136 | char type[12]; | |
68b65f73 RK |
137 | #ifdef CONFIG_DMA_ENGINE |
138 | /* DMA stuff */ | |
ead76f32 LW |
139 | bool using_tx_dma; |
140 | bool using_rx_dma; | |
141 | struct pl011_dmarx_data dmarx; | |
68b65f73 RK |
142 | struct pl011_dmatx_data dmatx; |
143 | #endif | |
144 | }; | |
145 | ||
146 | /* | |
147 | * All the DMA operation mode stuff goes inside this ifdef. | |
148 | * This assumes that you have a generic DMA device interface, | |
149 | * no custom DMA interfaces are supported. | |
150 | */ | |
151 | #ifdef CONFIG_DMA_ENGINE | |
152 | ||
153 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
154 | ||
ead76f32 LW |
155 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
156 | enum dma_data_direction dir) | |
157 | { | |
158 | sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL); | |
159 | if (!sg->buf) | |
160 | return -ENOMEM; | |
161 | ||
162 | sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE); | |
163 | ||
164 | if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) { | |
165 | kfree(sg->buf); | |
166 | return -EINVAL; | |
167 | } | |
168 | return 0; | |
169 | } | |
170 | ||
171 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |
172 | enum dma_data_direction dir) | |
173 | { | |
174 | if (sg->buf) { | |
175 | dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir); | |
176 | kfree(sg->buf); | |
177 | } | |
178 | } | |
179 | ||
68b65f73 RK |
180 | static void pl011_dma_probe_initcall(struct uart_amba_port *uap) |
181 | { | |
182 | /* DMA is the sole user of the platform data right now */ | |
183 | struct amba_pl011_data *plat = uap->port.dev->platform_data; | |
184 | struct dma_slave_config tx_conf = { | |
185 | .dst_addr = uap->port.mapbase + UART01x_DR, | |
186 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
187 | .direction = DMA_TO_DEVICE, | |
188 | .dst_maxburst = uap->fifosize >> 1, | |
189 | }; | |
190 | struct dma_chan *chan; | |
191 | dma_cap_mask_t mask; | |
192 | ||
193 | /* We need platform data */ | |
194 | if (!plat || !plat->dma_filter) { | |
195 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
196 | return; | |
197 | } | |
198 | ||
ead76f32 | 199 | /* Try to acquire a generic DMA engine slave TX channel */ |
68b65f73 RK |
200 | dma_cap_zero(mask); |
201 | dma_cap_set(DMA_SLAVE, mask); | |
202 | ||
203 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param); | |
204 | if (!chan) { | |
205 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
206 | return; | |
207 | } | |
208 | ||
209 | dmaengine_slave_config(chan, &tx_conf); | |
210 | uap->dmatx.chan = chan; | |
211 | ||
212 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
213 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
214 | |
215 | /* Optionally make use of an RX channel as well */ | |
216 | if (plat->dma_rx_param) { | |
217 | struct dma_slave_config rx_conf = { | |
218 | .src_addr = uap->port.mapbase + UART01x_DR, | |
219 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
220 | .direction = DMA_FROM_DEVICE, | |
221 | .src_maxburst = uap->fifosize >> 1, | |
222 | }; | |
223 | ||
224 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); | |
225 | if (!chan) { | |
226 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
227 | return; | |
228 | } | |
229 | ||
230 | dmaengine_slave_config(chan, &rx_conf); | |
231 | uap->dmarx.chan = chan; | |
232 | ||
233 | dev_info(uap->port.dev, "DMA channel RX %s\n", | |
234 | dma_chan_name(uap->dmarx.chan)); | |
235 | } | |
68b65f73 RK |
236 | } |
237 | ||
238 | #ifndef MODULE | |
239 | /* | |
240 | * Stack up the UARTs and let the above initcall be done at device | |
241 | * initcall time, because the serial driver is called as an arch | |
242 | * initcall, and at this time the DMA subsystem is not yet registered. | |
243 | * At this point the driver will switch over to using DMA where desired. | |
244 | */ | |
245 | struct dma_uap { | |
246 | struct list_head node; | |
247 | struct uart_amba_port *uap; | |
c19f12b5 RK |
248 | }; |
249 | ||
68b65f73 RK |
250 | static LIST_HEAD(pl011_dma_uarts); |
251 | ||
252 | static int __init pl011_dma_initcall(void) | |
253 | { | |
254 | struct list_head *node, *tmp; | |
255 | ||
256 | list_for_each_safe(node, tmp, &pl011_dma_uarts) { | |
257 | struct dma_uap *dmau = list_entry(node, struct dma_uap, node); | |
258 | pl011_dma_probe_initcall(dmau->uap); | |
259 | list_del(node); | |
260 | kfree(dmau); | |
261 | } | |
262 | return 0; | |
263 | } | |
264 | ||
265 | device_initcall(pl011_dma_initcall); | |
266 | ||
267 | static void pl011_dma_probe(struct uart_amba_port *uap) | |
268 | { | |
269 | struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL); | |
270 | if (dmau) { | |
271 | dmau->uap = uap; | |
272 | list_add_tail(&dmau->node, &pl011_dma_uarts); | |
273 | } | |
274 | } | |
275 | #else | |
276 | static void pl011_dma_probe(struct uart_amba_port *uap) | |
277 | { | |
278 | pl011_dma_probe_initcall(uap); | |
279 | } | |
280 | #endif | |
281 | ||
282 | static void pl011_dma_remove(struct uart_amba_port *uap) | |
283 | { | |
284 | /* TODO: remove the initcall if it has not yet executed */ | |
285 | if (uap->dmatx.chan) | |
286 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
287 | if (uap->dmarx.chan) |
288 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
289 | } |
290 | ||
68b65f73 RK |
291 | /* Forward declare this for the refill routine */ |
292 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); | |
293 | ||
294 | /* | |
295 | * The current DMA TX buffer has been sent. | |
296 | * Try to queue up another DMA buffer. | |
297 | */ | |
298 | static void pl011_dma_tx_callback(void *data) | |
299 | { | |
300 | struct uart_amba_port *uap = data; | |
301 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
302 | unsigned long flags; | |
303 | u16 dmacr; | |
304 | ||
305 | spin_lock_irqsave(&uap->port.lock, flags); | |
306 | if (uap->dmatx.queued) | |
307 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
308 | DMA_TO_DEVICE); | |
309 | ||
310 | dmacr = uap->dmacr; | |
311 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
312 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
313 | ||
314 | /* | |
315 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
316 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
317 | * | |
318 | * Note: we need to be careful here of a potential race between DMA | |
319 | * and the rest of the driver - if the driver disables TX DMA while | |
320 | * a TX buffer completing, we must update the tx queued status to | |
321 | * get further refills (hence we check dmacr). | |
322 | */ | |
323 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
324 | uart_circ_empty(&uap->port.state->xmit)) { | |
325 | uap->dmatx.queued = false; | |
326 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
327 | return; | |
328 | } | |
329 | ||
330 | if (pl011_dma_tx_refill(uap) <= 0) { | |
331 | /* | |
332 | * We didn't queue a DMA buffer for some reason, but we | |
333 | * have data pending to be sent. Re-enable the TX IRQ. | |
334 | */ | |
335 | uap->im |= UART011_TXIM; | |
336 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
337 | } | |
338 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
339 | } | |
340 | ||
341 | /* | |
342 | * Try to refill the TX DMA buffer. | |
343 | * Locking: called with port lock held and IRQs disabled. | |
344 | * Returns: | |
345 | * 1 if we queued up a TX DMA buffer. | |
346 | * 0 if we didn't want to handle this by DMA | |
347 | * <0 on error | |
348 | */ | |
349 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
350 | { | |
351 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
352 | struct dma_chan *chan = dmatx->chan; | |
353 | struct dma_device *dma_dev = chan->device; | |
354 | struct dma_async_tx_descriptor *desc; | |
355 | struct circ_buf *xmit = &uap->port.state->xmit; | |
356 | unsigned int count; | |
357 | ||
358 | /* | |
359 | * Try to avoid the overhead involved in using DMA if the | |
360 | * transaction fits in the first half of the FIFO, by using | |
361 | * the standard interrupt handling. This ensures that we | |
362 | * issue a uart_write_wakeup() at the appropriate time. | |
363 | */ | |
364 | count = uart_circ_chars_pending(xmit); | |
365 | if (count < (uap->fifosize >> 1)) { | |
366 | uap->dmatx.queued = false; | |
367 | return 0; | |
368 | } | |
369 | ||
370 | /* | |
371 | * Bodge: don't send the last character by DMA, as this | |
372 | * will prevent XON from notifying us to restart DMA. | |
373 | */ | |
374 | count -= 1; | |
375 | ||
376 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
377 | if (count > PL011_DMA_BUFFER_SIZE) | |
378 | count = PL011_DMA_BUFFER_SIZE; | |
379 | ||
380 | if (xmit->tail < xmit->head) | |
381 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
382 | else { | |
383 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
384 | size_t second = xmit->head; | |
385 | ||
386 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
387 | if (second) | |
388 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
389 | } | |
390 | ||
391 | dmatx->sg.length = count; | |
392 | ||
393 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
394 | uap->dmatx.queued = false; | |
395 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
396 | return -EBUSY; | |
397 | } | |
398 | ||
399 | desc = dma_dev->device_prep_slave_sg(chan, &dmatx->sg, 1, DMA_TO_DEVICE, | |
400 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
401 | if (!desc) { | |
402 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
403 | uap->dmatx.queued = false; | |
404 | /* | |
405 | * If DMA cannot be used right now, we complete this | |
406 | * transaction via IRQ and let the TTY layer retry. | |
407 | */ | |
408 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
409 | return -EBUSY; | |
410 | } | |
411 | ||
412 | /* Some data to go along to the callback */ | |
413 | desc->callback = pl011_dma_tx_callback; | |
414 | desc->callback_param = uap; | |
415 | ||
416 | /* All errors should happen at prepare time */ | |
417 | dmaengine_submit(desc); | |
418 | ||
419 | /* Fire the DMA transaction */ | |
420 | dma_dev->device_issue_pending(chan); | |
421 | ||
422 | uap->dmacr |= UART011_TXDMAE; | |
423 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
424 | uap->dmatx.queued = true; | |
425 | ||
426 | /* | |
427 | * Now we know that DMA will fire, so advance the ring buffer | |
428 | * with the stuff we just dispatched. | |
429 | */ | |
430 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
431 | uap->port.icount.tx += count; | |
432 | ||
433 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
434 | uart_write_wakeup(&uap->port); | |
435 | ||
436 | return 1; | |
437 | } | |
438 | ||
439 | /* | |
440 | * We received a transmit interrupt without a pending X-char but with | |
441 | * pending characters. | |
442 | * Locking: called with port lock held and IRQs disabled. | |
443 | * Returns: | |
444 | * false if we want to use PIO to transmit | |
445 | * true if we queued a DMA buffer | |
446 | */ | |
447 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
448 | { | |
ead76f32 | 449 | if (!uap->using_tx_dma) |
68b65f73 RK |
450 | return false; |
451 | ||
452 | /* | |
453 | * If we already have a TX buffer queued, but received a | |
454 | * TX interrupt, it will be because we've just sent an X-char. | |
455 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
456 | */ | |
457 | if (uap->dmatx.queued) { | |
458 | uap->dmacr |= UART011_TXDMAE; | |
459 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
460 | uap->im &= ~UART011_TXIM; | |
461 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
462 | return true; | |
463 | } | |
464 | ||
465 | /* | |
466 | * We don't have a TX buffer queued, so try to queue one. | |
467 | * If we succesfully queued a buffer, mask the TX IRQ. | |
468 | */ | |
469 | if (pl011_dma_tx_refill(uap) > 0) { | |
470 | uap->im &= ~UART011_TXIM; | |
471 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
472 | return true; | |
473 | } | |
474 | return false; | |
475 | } | |
476 | ||
477 | /* | |
478 | * Stop the DMA transmit (eg, due to received XOFF). | |
479 | * Locking: called with port lock held and IRQs disabled. | |
480 | */ | |
481 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
482 | { | |
483 | if (uap->dmatx.queued) { | |
484 | uap->dmacr &= ~UART011_TXDMAE; | |
485 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
486 | } | |
487 | } | |
488 | ||
489 | /* | |
490 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
491 | * character queued for send, try to get that character out ASAP. | |
492 | * Locking: called with port lock held and IRQs disabled. | |
493 | * Returns: | |
494 | * false if we want the TX IRQ to be enabled | |
495 | * true if we have a buffer queued | |
496 | */ | |
497 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
498 | { | |
499 | u16 dmacr; | |
500 | ||
ead76f32 | 501 | if (!uap->using_tx_dma) |
68b65f73 RK |
502 | return false; |
503 | ||
504 | if (!uap->port.x_char) { | |
505 | /* no X-char, try to push chars out in DMA mode */ | |
506 | bool ret = true; | |
507 | ||
508 | if (!uap->dmatx.queued) { | |
509 | if (pl011_dma_tx_refill(uap) > 0) { | |
510 | uap->im &= ~UART011_TXIM; | |
511 | ret = true; | |
512 | } else { | |
513 | uap->im |= UART011_TXIM; | |
514 | ret = false; | |
515 | } | |
516 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
517 | } else if (!(uap->dmacr & UART011_TXDMAE)) { | |
518 | uap->dmacr |= UART011_TXDMAE; | |
519 | writew(uap->dmacr, | |
520 | uap->port.membase + UART011_DMACR); | |
521 | } | |
522 | return ret; | |
523 | } | |
524 | ||
525 | /* | |
526 | * We have an X-char to send. Disable DMA to prevent it loading | |
527 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
528 | */ | |
529 | dmacr = uap->dmacr; | |
530 | uap->dmacr &= ~UART011_TXDMAE; | |
531 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
532 | ||
533 | if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { | |
534 | /* | |
535 | * No space in the FIFO, so enable the transmit interrupt | |
536 | * so we know when there is space. Note that once we've | |
537 | * loaded the character, we should just re-enable DMA. | |
538 | */ | |
539 | return false; | |
540 | } | |
541 | ||
542 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
543 | uap->port.icount.tx++; | |
544 | uap->port.x_char = 0; | |
545 | ||
546 | /* Success - restore the DMA state */ | |
547 | uap->dmacr = dmacr; | |
548 | writew(dmacr, uap->port.membase + UART011_DMACR); | |
549 | ||
550 | return true; | |
551 | } | |
552 | ||
553 | /* | |
554 | * Flush the transmit buffer. | |
555 | * Locking: called with port lock held and IRQs disabled. | |
556 | */ | |
557 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
558 | { | |
559 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
560 | ||
ead76f32 | 561 | if (!uap->using_tx_dma) |
68b65f73 RK |
562 | return; |
563 | ||
564 | /* Avoid deadlock with the DMA engine callback */ | |
565 | spin_unlock(&uap->port.lock); | |
566 | dmaengine_terminate_all(uap->dmatx.chan); | |
567 | spin_lock(&uap->port.lock); | |
568 | if (uap->dmatx.queued) { | |
569 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
570 | DMA_TO_DEVICE); | |
571 | uap->dmatx.queued = false; | |
572 | uap->dmacr &= ~UART011_TXDMAE; | |
573 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
574 | } | |
575 | } | |
576 | ||
ead76f32 LW |
577 | static void pl011_dma_rx_callback(void *data); |
578 | ||
579 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
580 | { | |
581 | struct dma_chan *rxchan = uap->dmarx.chan; | |
582 | struct dma_device *dma_dev; | |
583 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
584 | struct dma_async_tx_descriptor *desc; | |
585 | struct pl011_sgbuf *sgbuf; | |
586 | ||
587 | if (!rxchan) | |
588 | return -EIO; | |
589 | ||
590 | /* Start the RX DMA job */ | |
591 | sgbuf = uap->dmarx.use_buf_b ? | |
592 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
593 | dma_dev = rxchan->device; | |
594 | desc = rxchan->device->device_prep_slave_sg(rxchan, &sgbuf->sg, 1, | |
595 | DMA_FROM_DEVICE, | |
596 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
597 | /* | |
598 | * If the DMA engine is busy and cannot prepare a | |
599 | * channel, no big deal, the driver will fall back | |
600 | * to interrupt mode as a result of this error code. | |
601 | */ | |
602 | if (!desc) { | |
603 | uap->dmarx.running = false; | |
604 | dmaengine_terminate_all(rxchan); | |
605 | return -EBUSY; | |
606 | } | |
607 | ||
608 | /* Some data to go along to the callback */ | |
609 | desc->callback = pl011_dma_rx_callback; | |
610 | desc->callback_param = uap; | |
611 | dmarx->cookie = dmaengine_submit(desc); | |
612 | dma_async_issue_pending(rxchan); | |
613 | ||
614 | uap->dmacr |= UART011_RXDMAE; | |
615 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
616 | uap->dmarx.running = true; | |
617 | ||
618 | uap->im &= ~UART011_RXIM; | |
619 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
620 | ||
621 | return 0; | |
622 | } | |
623 | ||
624 | /* | |
625 | * This is called when either the DMA job is complete, or | |
626 | * the FIFO timeout interrupt occurred. This must be called | |
627 | * with the port spinlock uap->port.lock held. | |
628 | */ | |
629 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
630 | u32 pending, bool use_buf_b, | |
631 | bool readfifo) | |
632 | { | |
633 | struct tty_struct *tty = uap->port.state->port.tty; | |
634 | struct pl011_sgbuf *sgbuf = use_buf_b ? | |
635 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
636 | struct device *dev = uap->dmarx.chan->device->dev; | |
637 | unsigned int status, ch, flag; | |
638 | int dma_count = 0; | |
639 | u32 fifotaken = 0; /* only used for vdbg() */ | |
640 | ||
641 | /* Pick everything from the DMA first */ | |
642 | if (pending) { | |
643 | /* Sync in buffer */ | |
644 | dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE); | |
645 | ||
646 | /* | |
647 | * First take all chars in the DMA pipe, then look in the FIFO. | |
648 | * Note that tty_insert_flip_buf() tries to take as many chars | |
649 | * as it can. | |
650 | */ | |
651 | dma_count = tty_insert_flip_string(uap->port.state->port.tty, | |
652 | sgbuf->buf, pending); | |
653 | ||
654 | /* Return buffer to device */ | |
655 | dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE); | |
656 | ||
657 | uap->port.icount.rx += dma_count; | |
658 | if (dma_count < pending) | |
659 | dev_warn(uap->port.dev, | |
660 | "couldn't insert all characters (TTY is full?)\n"); | |
661 | } | |
662 | ||
663 | /* | |
664 | * Only continue with trying to read the FIFO if all DMA chars have | |
665 | * been taken first. | |
666 | */ | |
667 | if (dma_count == pending && readfifo) { | |
668 | /* Clear any error flags */ | |
669 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
670 | uap->port.membase + UART011_ICR); | |
671 | ||
672 | /* | |
673 | * If we read all the DMA'd characters, and we had an | |
674 | * incomplete buffer, that could be due to an rx error, | |
675 | * or maybe we just timed out. Read any pending chars | |
676 | * and check the error status. | |
677 | */ | |
678 | while (1) { | |
679 | status = readw(uap->port.membase + UART01x_FR); | |
680 | if (status & UART01x_FR_RXFE) | |
681 | break; | |
682 | ||
683 | /* Take chars from the FIFO and update status */ | |
684 | ch = readw(uap->port.membase + UART01x_DR) | | |
685 | UART_DUMMY_DR_RX; | |
686 | flag = TTY_NORMAL; | |
687 | uap->port.icount.rx++; | |
688 | fifotaken++; | |
689 | ||
690 | /* | |
691 | * Error conditions will only occur in the FIFO, | |
692 | * these will trigger an immediate interrupt and | |
693 | * stop the DMA job, so we will always find the | |
694 | * error in the FIFO, never in the DMA buffer. | |
695 | */ | |
696 | if (unlikely(ch & UART_DR_ERROR)) { | |
697 | if (ch & UART011_DR_BE) { | |
698 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
699 | uap->port.icount.brk++; | |
700 | if (uart_handle_break(&uap->port)) | |
701 | continue; | |
702 | } else if (ch & UART011_DR_PE) | |
703 | uap->port.icount.parity++; | |
704 | else if (ch & UART011_DR_FE) | |
705 | uap->port.icount.frame++; | |
706 | if (ch & UART011_DR_OE) | |
707 | uap->port.icount.overrun++; | |
708 | ||
709 | ch &= uap->port.read_status_mask; | |
710 | ||
711 | if (ch & UART011_DR_BE) | |
712 | flag = TTY_BREAK; | |
713 | else if (ch & UART011_DR_PE) | |
714 | flag = TTY_PARITY; | |
715 | else if (ch & UART011_DR_FE) | |
716 | flag = TTY_FRAME; | |
717 | } | |
718 | ||
719 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) | |
720 | continue; | |
721 | ||
722 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
723 | } | |
724 | } | |
725 | ||
726 | spin_unlock(&uap->port.lock); | |
727 | dev_vdbg(uap->port.dev, | |
728 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
729 | dma_count, fifotaken); | |
730 | tty_flip_buffer_push(tty); | |
731 | spin_lock(&uap->port.lock); | |
732 | } | |
733 | ||
734 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
735 | { | |
736 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
737 | struct dma_chan *rxchan = dmarx->chan; | |
738 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? | |
739 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
740 | size_t pending; | |
741 | struct dma_tx_state state; | |
742 | enum dma_status dmastat; | |
743 | ||
744 | /* | |
745 | * Pause the transfer so we can trust the current counter, | |
746 | * do this before we pause the PL011 block, else we may | |
747 | * overflow the FIFO. | |
748 | */ | |
749 | if (dmaengine_pause(rxchan)) | |
750 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
751 | dmastat = rxchan->device->device_tx_status(rxchan, | |
752 | dmarx->cookie, &state); | |
753 | if (dmastat != DMA_PAUSED) | |
754 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
755 | ||
756 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
757 | uap->dmacr &= ~UART011_RXDMAE; | |
758 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
759 | uap->dmarx.running = false; | |
760 | ||
761 | pending = sgbuf->sg.length - state.residue; | |
762 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
763 | /* Then we terminate the transfer - we now know our residue */ | |
764 | dmaengine_terminate_all(rxchan); | |
765 | ||
766 | /* | |
767 | * This will take the chars we have so far and insert | |
768 | * into the framework. | |
769 | */ | |
770 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
771 | ||
772 | /* Switch buffer & re-trigger DMA job */ | |
773 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
774 | if (pl011_dma_rx_trigger_dma(uap)) { | |
775 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
776 | "fall back to interrupt mode\n"); | |
777 | uap->im |= UART011_RXIM; | |
778 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
779 | } | |
780 | } | |
781 | ||
782 | static void pl011_dma_rx_callback(void *data) | |
783 | { | |
784 | struct uart_amba_port *uap = data; | |
785 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
786 | bool lastbuf = dmarx->use_buf_b; | |
787 | int ret; | |
788 | ||
789 | /* | |
790 | * This completion interrupt occurs typically when the | |
791 | * RX buffer is totally stuffed but no timeout has yet | |
792 | * occurred. When that happens, we just want the RX | |
793 | * routine to flush out the secondary DMA buffer while | |
794 | * we immediately trigger the next DMA job. | |
795 | */ | |
796 | spin_lock_irq(&uap->port.lock); | |
797 | uap->dmarx.running = false; | |
798 | dmarx->use_buf_b = !lastbuf; | |
799 | ret = pl011_dma_rx_trigger_dma(uap); | |
800 | ||
801 | pl011_dma_rx_chars(uap, PL011_DMA_BUFFER_SIZE, lastbuf, false); | |
802 | spin_unlock_irq(&uap->port.lock); | |
803 | /* | |
804 | * Do this check after we picked the DMA chars so we don't | |
805 | * get some IRQ immediately from RX. | |
806 | */ | |
807 | if (ret) { | |
808 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
809 | "fall back to interrupt mode\n"); | |
810 | uap->im |= UART011_RXIM; | |
811 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
812 | } | |
813 | } | |
814 | ||
815 | /* | |
816 | * Stop accepting received characters, when we're shutting down or | |
817 | * suspending this port. | |
818 | * Locking: called with port lock held and IRQs disabled. | |
819 | */ | |
820 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
821 | { | |
822 | /* FIXME. Just disable the DMA enable */ | |
823 | uap->dmacr &= ~UART011_RXDMAE; | |
824 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
825 | } | |
68b65f73 RK |
826 | |
827 | static void pl011_dma_startup(struct uart_amba_port *uap) | |
828 | { | |
ead76f32 LW |
829 | int ret; |
830 | ||
68b65f73 RK |
831 | if (!uap->dmatx.chan) |
832 | return; | |
833 | ||
834 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL); | |
835 | if (!uap->dmatx.buf) { | |
836 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
837 | uap->port.fifosize = uap->fifosize; | |
838 | return; | |
839 | } | |
840 | ||
841 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
842 | ||
843 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
844 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
845 | uap->using_tx_dma = true; |
846 | ||
847 | if (!uap->dmarx.chan) | |
848 | goto skip_rx; | |
849 | ||
850 | /* Allocate and map DMA RX buffers */ | |
851 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
852 | DMA_FROM_DEVICE); | |
853 | if (ret) { | |
854 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
855 | "RX buffer A", ret); | |
856 | goto skip_rx; | |
857 | } | |
68b65f73 | 858 | |
ead76f32 LW |
859 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
860 | DMA_FROM_DEVICE); | |
861 | if (ret) { | |
862 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
863 | "RX buffer B", ret); | |
864 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
865 | DMA_FROM_DEVICE); | |
866 | goto skip_rx; | |
867 | } | |
868 | ||
869 | uap->using_rx_dma = true; | |
870 | ||
871 | skip_rx: | |
68b65f73 RK |
872 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
873 | uap->dmacr |= UART011_DMAONERR; | |
874 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
38d62436 RK |
875 | |
876 | /* | |
877 | * ST Micro variants has some specific dma burst threshold | |
878 | * compensation. Set this to 16 bytes, so burst will only | |
879 | * be issued above/below 16 bytes. | |
880 | */ | |
881 | if (uap->vendor->dma_threshold) | |
882 | writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, | |
883 | uap->port.membase + ST_UART011_DMAWM); | |
ead76f32 LW |
884 | |
885 | if (uap->using_rx_dma) { | |
886 | if (pl011_dma_rx_trigger_dma(uap)) | |
887 | dev_dbg(uap->port.dev, "could not trigger initial " | |
888 | "RX DMA job, fall back to interrupt mode\n"); | |
889 | } | |
68b65f73 RK |
890 | } |
891 | ||
892 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
893 | { | |
ead76f32 | 894 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
895 | return; |
896 | ||
897 | /* Disable RX and TX DMA */ | |
898 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
899 | barrier(); | |
900 | ||
901 | spin_lock_irq(&uap->port.lock); | |
902 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
903 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
904 | spin_unlock_irq(&uap->port.lock); | |
905 | ||
ead76f32 LW |
906 | if (uap->using_tx_dma) { |
907 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
908 | dmaengine_terminate_all(uap->dmatx.chan); | |
909 | if (uap->dmatx.queued) { | |
910 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
911 | DMA_TO_DEVICE); | |
912 | uap->dmatx.queued = false; | |
913 | } | |
914 | ||
915 | kfree(uap->dmatx.buf); | |
916 | uap->using_tx_dma = false; | |
68b65f73 RK |
917 | } |
918 | ||
ead76f32 LW |
919 | if (uap->using_rx_dma) { |
920 | dmaengine_terminate_all(uap->dmarx.chan); | |
921 | /* Clean up the RX DMA */ | |
922 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); | |
923 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); | |
924 | uap->using_rx_dma = false; | |
925 | } | |
926 | } | |
68b65f73 | 927 | |
ead76f32 LW |
928 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
929 | { | |
930 | return uap->using_rx_dma; | |
68b65f73 RK |
931 | } |
932 | ||
ead76f32 LW |
933 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
934 | { | |
935 | return uap->using_rx_dma && uap->dmarx.running; | |
936 | } | |
937 | ||
938 | ||
68b65f73 RK |
939 | #else |
940 | /* Blank functions if the DMA engine is not available */ | |
941 | static inline void pl011_dma_probe(struct uart_amba_port *uap) | |
942 | { | |
943 | } | |
944 | ||
945 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
946 | { | |
947 | } | |
948 | ||
949 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
950 | { | |
951 | } | |
952 | ||
953 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
954 | { | |
955 | } | |
956 | ||
957 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
958 | { | |
959 | return false; | |
960 | } | |
961 | ||
962 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
963 | { | |
964 | } | |
965 | ||
966 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
967 | { | |
968 | return false; | |
969 | } | |
970 | ||
ead76f32 LW |
971 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
972 | { | |
973 | } | |
974 | ||
975 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
976 | { | |
977 | } | |
978 | ||
979 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
980 | { | |
981 | return -EIO; | |
982 | } | |
983 | ||
984 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
985 | { | |
986 | return false; | |
987 | } | |
988 | ||
989 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
990 | { | |
991 | return false; | |
992 | } | |
993 | ||
68b65f73 RK |
994 | #define pl011_dma_flush_buffer NULL |
995 | #endif | |
996 | ||
997 | ||
b129a8cc | 998 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 LT |
999 | { |
1000 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1001 | ||
1002 | uap->im &= ~UART011_TXIM; | |
1003 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
68b65f73 | 1004 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
1005 | } |
1006 | ||
b129a8cc | 1007 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 LT |
1008 | { |
1009 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1010 | ||
68b65f73 RK |
1011 | if (!pl011_dma_tx_start(uap)) { |
1012 | uap->im |= UART011_TXIM; | |
1013 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1014 | } | |
1da177e4 LT |
1015 | } |
1016 | ||
1017 | static void pl011_stop_rx(struct uart_port *port) | |
1018 | { | |
1019 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1020 | ||
1021 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
1022 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
1023 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
ead76f32 LW |
1024 | |
1025 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1026 | } |
1027 | ||
1028 | static void pl011_enable_ms(struct uart_port *port) | |
1029 | { | |
1030 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1031 | ||
1032 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
1033 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1034 | } | |
1035 | ||
7d12e780 | 1036 | static void pl011_rx_chars(struct uart_amba_port *uap) |
1da177e4 | 1037 | { |
ebd2c8f6 | 1038 | struct tty_struct *tty = uap->port.state->port.tty; |
b63d4f0f | 1039 | unsigned int status, ch, flag, max_count = 256; |
1da177e4 LT |
1040 | |
1041 | status = readw(uap->port.membase + UART01x_FR); | |
1042 | while ((status & UART01x_FR_RXFE) == 0 && max_count--) { | |
b63d4f0f | 1043 | ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX; |
1da177e4 LT |
1044 | flag = TTY_NORMAL; |
1045 | uap->port.icount.rx++; | |
1046 | ||
1047 | /* | |
1048 | * Note that the error handling code is | |
1049 | * out of the main execution path | |
1050 | */ | |
b63d4f0f RK |
1051 | if (unlikely(ch & UART_DR_ERROR)) { |
1052 | if (ch & UART011_DR_BE) { | |
1053 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
1da177e4 LT |
1054 | uap->port.icount.brk++; |
1055 | if (uart_handle_break(&uap->port)) | |
1056 | goto ignore_char; | |
b63d4f0f | 1057 | } else if (ch & UART011_DR_PE) |
1da177e4 | 1058 | uap->port.icount.parity++; |
b63d4f0f | 1059 | else if (ch & UART011_DR_FE) |
1da177e4 | 1060 | uap->port.icount.frame++; |
b63d4f0f | 1061 | if (ch & UART011_DR_OE) |
1da177e4 LT |
1062 | uap->port.icount.overrun++; |
1063 | ||
b63d4f0f | 1064 | ch &= uap->port.read_status_mask; |
1da177e4 | 1065 | |
b63d4f0f | 1066 | if (ch & UART011_DR_BE) |
1da177e4 | 1067 | flag = TTY_BREAK; |
b63d4f0f | 1068 | else if (ch & UART011_DR_PE) |
1da177e4 | 1069 | flag = TTY_PARITY; |
b63d4f0f | 1070 | else if (ch & UART011_DR_FE) |
1da177e4 LT |
1071 | flag = TTY_FRAME; |
1072 | } | |
1073 | ||
7d12e780 | 1074 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) |
1da177e4 LT |
1075 | goto ignore_char; |
1076 | ||
b63d4f0f | 1077 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); |
05ab3014 | 1078 | |
1da177e4 LT |
1079 | ignore_char: |
1080 | status = readw(uap->port.membase + UART01x_FR); | |
1081 | } | |
2389b272 | 1082 | spin_unlock(&uap->port.lock); |
1da177e4 | 1083 | tty_flip_buffer_push(tty); |
ead76f32 LW |
1084 | /* |
1085 | * If we were temporarily out of DMA mode for a while, | |
1086 | * attempt to switch back to DMA mode again. | |
1087 | */ | |
1088 | if (pl011_dma_rx_available(uap)) { | |
1089 | if (pl011_dma_rx_trigger_dma(uap)) { | |
1090 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " | |
1091 | "fall back to interrupt mode again\n"); | |
1092 | uap->im |= UART011_RXIM; | |
1093 | } else | |
1094 | uap->im &= ~UART011_RXIM; | |
1095 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1096 | } | |
2389b272 | 1097 | spin_lock(&uap->port.lock); |
1da177e4 LT |
1098 | } |
1099 | ||
1100 | static void pl011_tx_chars(struct uart_amba_port *uap) | |
1101 | { | |
ebd2c8f6 | 1102 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
1103 | int count; |
1104 | ||
1105 | if (uap->port.x_char) { | |
1106 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
1107 | uap->port.icount.tx++; | |
1108 | uap->port.x_char = 0; | |
1109 | return; | |
1110 | } | |
1111 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1112 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1113 | return; |
1114 | } | |
1115 | ||
68b65f73 RK |
1116 | /* If we are using DMA mode, try to send some characters. */ |
1117 | if (pl011_dma_tx_irq(uap)) | |
1118 | return; | |
1119 | ||
ffca2b11 | 1120 | count = uap->fifosize >> 1; |
1da177e4 LT |
1121 | do { |
1122 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); | |
1123 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1124 | uap->port.icount.tx++; | |
1125 | if (uart_circ_empty(xmit)) | |
1126 | break; | |
1127 | } while (--count > 0); | |
1128 | ||
1129 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1130 | uart_write_wakeup(&uap->port); | |
1131 | ||
1132 | if (uart_circ_empty(xmit)) | |
b129a8cc | 1133 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1134 | } |
1135 | ||
1136 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1137 | { | |
1138 | unsigned int status, delta; | |
1139 | ||
1140 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1141 | ||
1142 | delta = status ^ uap->old_status; | |
1143 | uap->old_status = status; | |
1144 | ||
1145 | if (!delta) | |
1146 | return; | |
1147 | ||
1148 | if (delta & UART01x_FR_DCD) | |
1149 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1150 | ||
1151 | if (delta & UART01x_FR_DSR) | |
1152 | uap->port.icount.dsr++; | |
1153 | ||
1154 | if (delta & UART01x_FR_CTS) | |
1155 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
1156 | ||
bdc04e31 | 1157 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1158 | } |
1159 | ||
7d12e780 | 1160 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1161 | { |
1162 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1163 | unsigned long flags; |
1da177e4 LT |
1164 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
1165 | int handled = 0; | |
1166 | ||
963cc981 | 1167 | spin_lock_irqsave(&uap->port.lock, flags); |
1da177e4 LT |
1168 | |
1169 | status = readw(uap->port.membase + UART011_MIS); | |
1170 | if (status) { | |
1171 | do { | |
1172 | writew(status & ~(UART011_TXIS|UART011_RTIS| | |
1173 | UART011_RXIS), | |
1174 | uap->port.membase + UART011_ICR); | |
1175 | ||
ead76f32 LW |
1176 | if (status & (UART011_RTIS|UART011_RXIS)) { |
1177 | if (pl011_dma_rx_running(uap)) | |
1178 | pl011_dma_rx_irq(uap); | |
1179 | else | |
1180 | pl011_rx_chars(uap); | |
1181 | } | |
1da177e4 LT |
1182 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1183 | UART011_CTSMIS|UART011_RIMIS)) | |
1184 | pl011_modem_status(uap); | |
1185 | if (status & UART011_TXIS) | |
1186 | pl011_tx_chars(uap); | |
1187 | ||
1188 | if (pass_counter-- == 0) | |
1189 | break; | |
1190 | ||
1191 | status = readw(uap->port.membase + UART011_MIS); | |
1192 | } while (status != 0); | |
1193 | handled = 1; | |
1194 | } | |
1195 | ||
963cc981 | 1196 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
1197 | |
1198 | return IRQ_RETVAL(handled); | |
1199 | } | |
1200 | ||
1201 | static unsigned int pl01x_tx_empty(struct uart_port *port) | |
1202 | { | |
1203 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1204 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1205 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
1206 | } | |
1207 | ||
1208 | static unsigned int pl01x_get_mctrl(struct uart_port *port) | |
1209 | { | |
1210 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1211 | unsigned int result = 0; | |
1212 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1213 | ||
5159f407 | 1214 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
1215 | if (status & uartbit) \ |
1216 | result |= tiocmbit | |
1217 | ||
5159f407 JS |
1218 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
1219 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); | |
1220 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
1221 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
1222 | #undef TIOCMBIT | |
1da177e4 LT |
1223 | return result; |
1224 | } | |
1225 | ||
1226 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1227 | { | |
1228 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1229 | unsigned int cr; | |
1230 | ||
1231 | cr = readw(uap->port.membase + UART011_CR); | |
1232 | ||
5159f407 | 1233 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
1234 | if (mctrl & tiocmbit) \ |
1235 | cr |= uartbit; \ | |
1236 | else \ | |
1237 | cr &= ~uartbit | |
1238 | ||
5159f407 JS |
1239 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
1240 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
1241 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
1242 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
1243 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
1244 | |
1245 | if (uap->autorts) { | |
1246 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
1247 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
1248 | } | |
5159f407 | 1249 | #undef TIOCMBIT |
1da177e4 LT |
1250 | |
1251 | writew(cr, uap->port.membase + UART011_CR); | |
1252 | } | |
1253 | ||
1254 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1255 | { | |
1256 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1257 | unsigned long flags; | |
1258 | unsigned int lcr_h; | |
1259 | ||
1260 | spin_lock_irqsave(&uap->port.lock, flags); | |
ec489aa8 | 1261 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1262 | if (break_state == -1) |
1263 | lcr_h |= UART01x_LCRH_BRK; | |
1264 | else | |
1265 | lcr_h &= ~UART01x_LCRH_BRK; | |
ec489aa8 | 1266 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1267 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1268 | } | |
1269 | ||
84b5ae15 JW |
1270 | #ifdef CONFIG_CONSOLE_POLL |
1271 | static int pl010_get_poll_char(struct uart_port *port) | |
1272 | { | |
1273 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1274 | unsigned int status; | |
1275 | ||
f5316b4a JW |
1276 | status = readw(uap->port.membase + UART01x_FR); |
1277 | if (status & UART01x_FR_RXFE) | |
1278 | return NO_POLL_CHAR; | |
84b5ae15 JW |
1279 | |
1280 | return readw(uap->port.membase + UART01x_DR); | |
1281 | } | |
1282 | ||
1283 | static void pl010_put_poll_char(struct uart_port *port, | |
1284 | unsigned char ch) | |
1285 | { | |
1286 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1287 | ||
1288 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) | |
1289 | barrier(); | |
1290 | ||
1291 | writew(ch, uap->port.membase + UART01x_DR); | |
1292 | } | |
1293 | ||
1294 | #endif /* CONFIG_CONSOLE_POLL */ | |
1295 | ||
1da177e4 LT |
1296 | static int pl011_startup(struct uart_port *port) |
1297 | { | |
1298 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1299 | unsigned int cr; | |
1300 | int retval; | |
1301 | ||
1302 | /* | |
1303 | * Try to enable the clock producer. | |
1304 | */ | |
1305 | retval = clk_enable(uap->clk); | |
1306 | if (retval) | |
1307 | goto out; | |
1308 | ||
1309 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1310 | ||
1311 | /* | |
1312 | * Allocate the IRQ | |
1313 | */ | |
1314 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
1315 | if (retval) | |
1316 | goto clk_dis; | |
1317 | ||
c19f12b5 | 1318 | writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); |
1da177e4 LT |
1319 | |
1320 | /* | |
1321 | * Provoke TX FIFO interrupt into asserting. | |
1322 | */ | |
1323 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; | |
1324 | writew(cr, uap->port.membase + UART011_CR); | |
1325 | writew(0, uap->port.membase + UART011_FBRD); | |
1326 | writew(1, uap->port.membase + UART011_IBRD); | |
ec489aa8 LW |
1327 | writew(0, uap->port.membase + uap->lcrh_rx); |
1328 | if (uap->lcrh_tx != uap->lcrh_rx) { | |
1329 | int i; | |
1330 | /* | |
1331 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1332 | * to get this delay write read only register 10 times | |
1333 | */ | |
1334 | for (i = 0; i < 10; ++i) | |
1335 | writew(0xff, uap->port.membase + UART011_MIS); | |
1336 | writew(0, uap->port.membase + uap->lcrh_tx); | |
1337 | } | |
1da177e4 LT |
1338 | writew(0, uap->port.membase + UART01x_DR); |
1339 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
1340 | barrier(); | |
1341 | ||
1342 | cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
1343 | writew(cr, uap->port.membase + UART011_CR); | |
1344 | ||
5063e2c5 RK |
1345 | /* Clear pending error interrupts */ |
1346 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
1347 | uap->port.membase + UART011_ICR); | |
1348 | ||
1da177e4 LT |
1349 | /* |
1350 | * initialise the old status of the modem signals | |
1351 | */ | |
1352 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1353 | ||
68b65f73 RK |
1354 | /* Startup DMA */ |
1355 | pl011_dma_startup(uap); | |
1356 | ||
1da177e4 | 1357 | /* |
ead76f32 LW |
1358 | * Finally, enable interrupts, only timeouts when using DMA |
1359 | * if initial RX DMA job failed, start in interrupt mode | |
1360 | * as well. | |
1da177e4 LT |
1361 | */ |
1362 | spin_lock_irq(&uap->port.lock); | |
ead76f32 LW |
1363 | uap->im = UART011_RTIM; |
1364 | if (!pl011_dma_rx_running(uap)) | |
1365 | uap->im |= UART011_RXIM; | |
1da177e4 LT |
1366 | writew(uap->im, uap->port.membase + UART011_IMSC); |
1367 | spin_unlock_irq(&uap->port.lock); | |
1368 | ||
1369 | return 0; | |
1370 | ||
1371 | clk_dis: | |
1372 | clk_disable(uap->clk); | |
1373 | out: | |
1374 | return retval; | |
1375 | } | |
1376 | ||
ec489aa8 LW |
1377 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
1378 | unsigned int lcrh) | |
1379 | { | |
1380 | unsigned long val; | |
1381 | ||
1382 | val = readw(uap->port.membase + lcrh); | |
1383 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
1384 | writew(val, uap->port.membase + lcrh); | |
1385 | } | |
1386 | ||
1da177e4 LT |
1387 | static void pl011_shutdown(struct uart_port *port) |
1388 | { | |
1389 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
1da177e4 LT |
1390 | |
1391 | /* | |
1392 | * disable all interrupts | |
1393 | */ | |
1394 | spin_lock_irq(&uap->port.lock); | |
1395 | uap->im = 0; | |
1396 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1397 | writew(0xffff, uap->port.membase + UART011_ICR); | |
1398 | spin_unlock_irq(&uap->port.lock); | |
1399 | ||
68b65f73 RK |
1400 | pl011_dma_shutdown(uap); |
1401 | ||
1da177e4 LT |
1402 | /* |
1403 | * Free the interrupt | |
1404 | */ | |
1405 | free_irq(uap->port.irq, uap); | |
1406 | ||
1407 | /* | |
1408 | * disable the port | |
1409 | */ | |
3b43816f | 1410 | uap->autorts = false; |
1da177e4 LT |
1411 | writew(UART01x_CR_UARTEN | UART011_CR_TXE, uap->port.membase + UART011_CR); |
1412 | ||
1413 | /* | |
1414 | * disable break condition and fifos | |
1415 | */ | |
ec489aa8 LW |
1416 | pl011_shutdown_channel(uap, uap->lcrh_rx); |
1417 | if (uap->lcrh_rx != uap->lcrh_tx) | |
1418 | pl011_shutdown_channel(uap, uap->lcrh_tx); | |
1da177e4 LT |
1419 | |
1420 | /* | |
1421 | * Shut down the clock producer | |
1422 | */ | |
1423 | clk_disable(uap->clk); | |
1424 | } | |
1425 | ||
1426 | static void | |
606d099c AC |
1427 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1428 | struct ktermios *old) | |
1da177e4 | 1429 | { |
3b43816f | 1430 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 LT |
1431 | unsigned int lcr_h, old_cr; |
1432 | unsigned long flags; | |
c19f12b5 RK |
1433 | unsigned int baud, quot, clkdiv; |
1434 | ||
1435 | if (uap->vendor->oversampling) | |
1436 | clkdiv = 8; | |
1437 | else | |
1438 | clkdiv = 16; | |
1da177e4 LT |
1439 | |
1440 | /* | |
1441 | * Ask the core to calculate the divisor for us. | |
1442 | */ | |
ac3e3fb4 | 1443 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1444 | port->uartclk / clkdiv); |
ac3e3fb4 LW |
1445 | |
1446 | if (baud > port->uartclk/16) | |
1447 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1448 | else | |
1449 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1450 | |
1451 | switch (termios->c_cflag & CSIZE) { | |
1452 | case CS5: | |
1453 | lcr_h = UART01x_LCRH_WLEN_5; | |
1454 | break; | |
1455 | case CS6: | |
1456 | lcr_h = UART01x_LCRH_WLEN_6; | |
1457 | break; | |
1458 | case CS7: | |
1459 | lcr_h = UART01x_LCRH_WLEN_7; | |
1460 | break; | |
1461 | default: // CS8 | |
1462 | lcr_h = UART01x_LCRH_WLEN_8; | |
1463 | break; | |
1464 | } | |
1465 | if (termios->c_cflag & CSTOPB) | |
1466 | lcr_h |= UART01x_LCRH_STP2; | |
1467 | if (termios->c_cflag & PARENB) { | |
1468 | lcr_h |= UART01x_LCRH_PEN; | |
1469 | if (!(termios->c_cflag & PARODD)) | |
1470 | lcr_h |= UART01x_LCRH_EPS; | |
1471 | } | |
ffca2b11 | 1472 | if (uap->fifosize > 1) |
1da177e4 LT |
1473 | lcr_h |= UART01x_LCRH_FEN; |
1474 | ||
1475 | spin_lock_irqsave(&port->lock, flags); | |
1476 | ||
1477 | /* | |
1478 | * Update the per-port timeout. | |
1479 | */ | |
1480 | uart_update_timeout(port, termios->c_cflag, baud); | |
1481 | ||
b63d4f0f | 1482 | port->read_status_mask = UART011_DR_OE | 255; |
1da177e4 | 1483 | if (termios->c_iflag & INPCK) |
b63d4f0f | 1484 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1485 | if (termios->c_iflag & (BRKINT | PARMRK)) |
b63d4f0f | 1486 | port->read_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1487 | |
1488 | /* | |
1489 | * Characters to ignore | |
1490 | */ | |
1491 | port->ignore_status_mask = 0; | |
1492 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1493 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1494 | if (termios->c_iflag & IGNBRK) { |
b63d4f0f | 1495 | port->ignore_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1496 | /* |
1497 | * If we're ignoring parity and break indicators, | |
1498 | * ignore overruns too (for real raw support). | |
1499 | */ | |
1500 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1501 | port->ignore_status_mask |= UART011_DR_OE; |
1da177e4 LT |
1502 | } |
1503 | ||
1504 | /* | |
1505 | * Ignore all characters if CREAD is not set. | |
1506 | */ | |
1507 | if ((termios->c_cflag & CREAD) == 0) | |
b63d4f0f | 1508 | port->ignore_status_mask |= UART_DUMMY_DR_RX; |
1da177e4 LT |
1509 | |
1510 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1511 | pl011_enable_ms(port); | |
1512 | ||
1513 | /* first, disable everything */ | |
1514 | old_cr = readw(port->membase + UART011_CR); | |
1515 | writew(0, port->membase + UART011_CR); | |
1516 | ||
3b43816f RV |
1517 | if (termios->c_cflag & CRTSCTS) { |
1518 | if (old_cr & UART011_CR_RTS) | |
1519 | old_cr |= UART011_CR_RTSEN; | |
1520 | ||
1521 | old_cr |= UART011_CR_CTSEN; | |
1522 | uap->autorts = true; | |
1523 | } else { | |
1524 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1525 | uap->autorts = false; | |
1526 | } | |
1527 | ||
c19f12b5 RK |
1528 | if (uap->vendor->oversampling) { |
1529 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1530 | old_cr |= ST_UART011_CR_OVSFACT; |
1531 | else | |
1532 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1533 | } | |
1534 | ||
1da177e4 LT |
1535 | /* Set baud rate */ |
1536 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
1537 | writew(quot >> 6, port->membase + UART011_IBRD); | |
1538 | ||
1539 | /* | |
1540 | * ----------v----------v----------v----------v----- | |
1541 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L | |
1542 | * ----------^----------^----------^----------^----- | |
1543 | */ | |
ec489aa8 LW |
1544 | writew(lcr_h, port->membase + uap->lcrh_rx); |
1545 | if (uap->lcrh_rx != uap->lcrh_tx) { | |
1546 | int i; | |
1547 | /* | |
1548 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1549 | * to get this delay write read only register 10 times | |
1550 | */ | |
1551 | for (i = 0; i < 10; ++i) | |
1552 | writew(0xff, uap->port.membase + UART011_MIS); | |
1553 | writew(lcr_h, port->membase + uap->lcrh_tx); | |
1554 | } | |
1da177e4 LT |
1555 | writew(old_cr, port->membase + UART011_CR); |
1556 | ||
1557 | spin_unlock_irqrestore(&port->lock, flags); | |
1558 | } | |
1559 | ||
1560 | static const char *pl011_type(struct uart_port *port) | |
1561 | { | |
e8a7ba86 RK |
1562 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1563 | return uap->port.type == PORT_AMBA ? uap->type : NULL; | |
1da177e4 LT |
1564 | } |
1565 | ||
1566 | /* | |
1567 | * Release the memory region(s) being used by 'port' | |
1568 | */ | |
1569 | static void pl010_release_port(struct uart_port *port) | |
1570 | { | |
1571 | release_mem_region(port->mapbase, SZ_4K); | |
1572 | } | |
1573 | ||
1574 | /* | |
1575 | * Request the memory region(s) being used by 'port' | |
1576 | */ | |
1577 | static int pl010_request_port(struct uart_port *port) | |
1578 | { | |
1579 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
1580 | != NULL ? 0 : -EBUSY; | |
1581 | } | |
1582 | ||
1583 | /* | |
1584 | * Configure/autoconfigure the port. | |
1585 | */ | |
1586 | static void pl010_config_port(struct uart_port *port, int flags) | |
1587 | { | |
1588 | if (flags & UART_CONFIG_TYPE) { | |
1589 | port->type = PORT_AMBA; | |
1590 | pl010_request_port(port); | |
1591 | } | |
1592 | } | |
1593 | ||
1594 | /* | |
1595 | * verify the new serial_struct (for TIOCSSERIAL). | |
1596 | */ | |
1597 | static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1598 | { | |
1599 | int ret = 0; | |
1600 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
1601 | ret = -EINVAL; | |
a62c4133 | 1602 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
1603 | ret = -EINVAL; |
1604 | if (ser->baud_base < 9600) | |
1605 | ret = -EINVAL; | |
1606 | return ret; | |
1607 | } | |
1608 | ||
1609 | static struct uart_ops amba_pl011_pops = { | |
1610 | .tx_empty = pl01x_tx_empty, | |
1611 | .set_mctrl = pl011_set_mctrl, | |
1612 | .get_mctrl = pl01x_get_mctrl, | |
1613 | .stop_tx = pl011_stop_tx, | |
1614 | .start_tx = pl011_start_tx, | |
1615 | .stop_rx = pl011_stop_rx, | |
1616 | .enable_ms = pl011_enable_ms, | |
1617 | .break_ctl = pl011_break_ctl, | |
1618 | .startup = pl011_startup, | |
1619 | .shutdown = pl011_shutdown, | |
68b65f73 | 1620 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
1621 | .set_termios = pl011_set_termios, |
1622 | .type = pl011_type, | |
1623 | .release_port = pl010_release_port, | |
1624 | .request_port = pl010_request_port, | |
1625 | .config_port = pl010_config_port, | |
1626 | .verify_port = pl010_verify_port, | |
84b5ae15 JW |
1627 | #ifdef CONFIG_CONSOLE_POLL |
1628 | .poll_get_char = pl010_get_poll_char, | |
1629 | .poll_put_char = pl010_put_poll_char, | |
1630 | #endif | |
1da177e4 LT |
1631 | }; |
1632 | ||
1633 | static struct uart_amba_port *amba_ports[UART_NR]; | |
1634 | ||
1635 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
1636 | ||
d358788f | 1637 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 1638 | { |
d358788f | 1639 | struct uart_amba_port *uap = (struct uart_amba_port *)port; |
1da177e4 | 1640 | |
d358788f RK |
1641 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
1642 | barrier(); | |
1da177e4 LT |
1643 | writew(ch, uap->port.membase + UART01x_DR); |
1644 | } | |
1645 | ||
1646 | static void | |
1647 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
1648 | { | |
1649 | struct uart_amba_port *uap = amba_ports[co->index]; | |
1650 | unsigned int status, old_cr, new_cr; | |
1da177e4 LT |
1651 | |
1652 | clk_enable(uap->clk); | |
1653 | ||
1654 | /* | |
1655 | * First save the CR then disable the interrupts | |
1656 | */ | |
1657 | old_cr = readw(uap->port.membase + UART011_CR); | |
1658 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
1659 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1660 | writew(new_cr, uap->port.membase + UART011_CR); | |
1661 | ||
d358788f | 1662 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
1663 | |
1664 | /* | |
1665 | * Finally, wait for transmitter to become empty | |
1666 | * and restore the TCR | |
1667 | */ | |
1668 | do { | |
1669 | status = readw(uap->port.membase + UART01x_FR); | |
1670 | } while (status & UART01x_FR_BUSY); | |
1671 | writew(old_cr, uap->port.membase + UART011_CR); | |
1672 | ||
1673 | clk_disable(uap->clk); | |
1674 | } | |
1675 | ||
1676 | static void __init | |
1677 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
1678 | int *parity, int *bits) | |
1679 | { | |
1680 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
1681 | unsigned int lcr_h, ibrd, fbrd; | |
1682 | ||
ec489aa8 | 1683 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1684 | |
1685 | *parity = 'n'; | |
1686 | if (lcr_h & UART01x_LCRH_PEN) { | |
1687 | if (lcr_h & UART01x_LCRH_EPS) | |
1688 | *parity = 'e'; | |
1689 | else | |
1690 | *parity = 'o'; | |
1691 | } | |
1692 | ||
1693 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
1694 | *bits = 7; | |
1695 | else | |
1696 | *bits = 8; | |
1697 | ||
1698 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
1699 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
1700 | ||
1701 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 1702 | |
c19f12b5 | 1703 | if (uap->vendor->oversampling) { |
ac3e3fb4 LW |
1704 | if (readw(uap->port.membase + UART011_CR) |
1705 | & ST_UART011_CR_OVSFACT) | |
1706 | *baud *= 2; | |
1707 | } | |
1da177e4 LT |
1708 | } |
1709 | } | |
1710 | ||
1711 | static int __init pl011_console_setup(struct console *co, char *options) | |
1712 | { | |
1713 | struct uart_amba_port *uap; | |
1714 | int baud = 38400; | |
1715 | int bits = 8; | |
1716 | int parity = 'n'; | |
1717 | int flow = 'n'; | |
1718 | ||
1719 | /* | |
1720 | * Check whether an invalid uart number has been specified, and | |
1721 | * if so, search for the first available port that does have | |
1722 | * console support. | |
1723 | */ | |
1724 | if (co->index >= UART_NR) | |
1725 | co->index = 0; | |
1726 | uap = amba_ports[co->index]; | |
d28122a5 RK |
1727 | if (!uap) |
1728 | return -ENODEV; | |
1da177e4 LT |
1729 | |
1730 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1731 | ||
1732 | if (options) | |
1733 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1734 | else | |
1735 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
1736 | ||
1737 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
1738 | } | |
1739 | ||
2d93486c | 1740 | static struct uart_driver amba_reg; |
1da177e4 LT |
1741 | static struct console amba_console = { |
1742 | .name = "ttyAMA", | |
1743 | .write = pl011_console_write, | |
1744 | .device = uart_console_device, | |
1745 | .setup = pl011_console_setup, | |
1746 | .flags = CON_PRINTBUFFER, | |
1747 | .index = -1, | |
1748 | .data = &amba_reg, | |
1749 | }; | |
1750 | ||
1751 | #define AMBA_CONSOLE (&amba_console) | |
1752 | #else | |
1753 | #define AMBA_CONSOLE NULL | |
1754 | #endif | |
1755 | ||
1756 | static struct uart_driver amba_reg = { | |
1757 | .owner = THIS_MODULE, | |
1758 | .driver_name = "ttyAMA", | |
1759 | .dev_name = "ttyAMA", | |
1760 | .major = SERIAL_AMBA_MAJOR, | |
1761 | .minor = SERIAL_AMBA_MINOR, | |
1762 | .nr = UART_NR, | |
1763 | .cons = AMBA_CONSOLE, | |
1764 | }; | |
1765 | ||
03fbdb15 | 1766 | static int pl011_probe(struct amba_device *dev, struct amba_id *id) |
1da177e4 LT |
1767 | { |
1768 | struct uart_amba_port *uap; | |
5926a295 | 1769 | struct vendor_data *vendor = id->data; |
1da177e4 LT |
1770 | void __iomem *base; |
1771 | int i, ret; | |
1772 | ||
1773 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1774 | if (amba_ports[i] == NULL) | |
1775 | break; | |
1776 | ||
1777 | if (i == ARRAY_SIZE(amba_ports)) { | |
1778 | ret = -EBUSY; | |
1779 | goto out; | |
1780 | } | |
1781 | ||
dd00cc48 | 1782 | uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); |
1da177e4 LT |
1783 | if (uap == NULL) { |
1784 | ret = -ENOMEM; | |
1785 | goto out; | |
1786 | } | |
1787 | ||
dc890c2d | 1788 | base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1789 | if (!base) { |
1790 | ret = -ENOMEM; | |
1791 | goto free; | |
1792 | } | |
1793 | ||
ee569c43 | 1794 | uap->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
1795 | if (IS_ERR(uap->clk)) { |
1796 | ret = PTR_ERR(uap->clk); | |
1797 | goto unmap; | |
1798 | } | |
1799 | ||
c19f12b5 | 1800 | uap->vendor = vendor; |
ec489aa8 LW |
1801 | uap->lcrh_rx = vendor->lcrh_rx; |
1802 | uap->lcrh_tx = vendor->lcrh_tx; | |
ffca2b11 | 1803 | uap->fifosize = vendor->fifosize; |
1da177e4 LT |
1804 | uap->port.dev = &dev->dev; |
1805 | uap->port.mapbase = dev->res.start; | |
1806 | uap->port.membase = base; | |
1807 | uap->port.iotype = UPIO_MEM; | |
1808 | uap->port.irq = dev->irq[0]; | |
ffca2b11 | 1809 | uap->port.fifosize = uap->fifosize; |
1da177e4 LT |
1810 | uap->port.ops = &amba_pl011_pops; |
1811 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
1812 | uap->port.line = i; | |
68b65f73 | 1813 | pl011_dma_probe(uap); |
1da177e4 | 1814 | |
e8a7ba86 RK |
1815 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); |
1816 | ||
1da177e4 LT |
1817 | amba_ports[i] = uap; |
1818 | ||
1819 | amba_set_drvdata(dev, uap); | |
1820 | ret = uart_add_one_port(&amba_reg, &uap->port); | |
1821 | if (ret) { | |
1822 | amba_set_drvdata(dev, NULL); | |
1823 | amba_ports[i] = NULL; | |
68b65f73 | 1824 | pl011_dma_remove(uap); |
1da177e4 LT |
1825 | clk_put(uap->clk); |
1826 | unmap: | |
1827 | iounmap(base); | |
1828 | free: | |
1829 | kfree(uap); | |
1830 | } | |
1831 | out: | |
1832 | return ret; | |
1833 | } | |
1834 | ||
1835 | static int pl011_remove(struct amba_device *dev) | |
1836 | { | |
1837 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1838 | int i; | |
1839 | ||
1840 | amba_set_drvdata(dev, NULL); | |
1841 | ||
1842 | uart_remove_one_port(&amba_reg, &uap->port); | |
1843 | ||
1844 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1845 | if (amba_ports[i] == uap) | |
1846 | amba_ports[i] = NULL; | |
1847 | ||
68b65f73 | 1848 | pl011_dma_remove(uap); |
1da177e4 | 1849 | iounmap(uap->port.membase); |
1da177e4 LT |
1850 | clk_put(uap->clk); |
1851 | kfree(uap); | |
1852 | return 0; | |
1853 | } | |
1854 | ||
b736b89f LC |
1855 | #ifdef CONFIG_PM |
1856 | static int pl011_suspend(struct amba_device *dev, pm_message_t state) | |
1857 | { | |
1858 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1859 | ||
1860 | if (!uap) | |
1861 | return -EINVAL; | |
1862 | ||
1863 | return uart_suspend_port(&amba_reg, &uap->port); | |
1864 | } | |
1865 | ||
1866 | static int pl011_resume(struct amba_device *dev) | |
1867 | { | |
1868 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1869 | ||
1870 | if (!uap) | |
1871 | return -EINVAL; | |
1872 | ||
1873 | return uart_resume_port(&amba_reg, &uap->port); | |
1874 | } | |
1875 | #endif | |
1876 | ||
2c39c9e1 | 1877 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
1878 | { |
1879 | .id = 0x00041011, | |
1880 | .mask = 0x000fffff, | |
5926a295 AR |
1881 | .data = &vendor_arm, |
1882 | }, | |
1883 | { | |
1884 | .id = 0x00380802, | |
1885 | .mask = 0x00ffffff, | |
1886 | .data = &vendor_st, | |
1da177e4 LT |
1887 | }, |
1888 | { 0, 0 }, | |
1889 | }; | |
1890 | ||
1891 | static struct amba_driver pl011_driver = { | |
1892 | .drv = { | |
1893 | .name = "uart-pl011", | |
1894 | }, | |
1895 | .id_table = pl011_ids, | |
1896 | .probe = pl011_probe, | |
1897 | .remove = pl011_remove, | |
b736b89f LC |
1898 | #ifdef CONFIG_PM |
1899 | .suspend = pl011_suspend, | |
1900 | .resume = pl011_resume, | |
1901 | #endif | |
1da177e4 LT |
1902 | }; |
1903 | ||
1904 | static int __init pl011_init(void) | |
1905 | { | |
1906 | int ret; | |
1907 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); | |
1908 | ||
1909 | ret = uart_register_driver(&amba_reg); | |
1910 | if (ret == 0) { | |
1911 | ret = amba_driver_register(&pl011_driver); | |
1912 | if (ret) | |
1913 | uart_unregister_driver(&amba_reg); | |
1914 | } | |
1915 | return ret; | |
1916 | } | |
1917 | ||
1918 | static void __exit pl011_exit(void) | |
1919 | { | |
1920 | amba_driver_unregister(&pl011_driver); | |
1921 | uart_unregister_driver(&amba_reg); | |
1922 | } | |
1923 | ||
4dd9e742 AR |
1924 | /* |
1925 | * While this can be a module, if builtin it's most likely the console | |
1926 | * So let's leave module_exit but move module_init to an earlier place | |
1927 | */ | |
1928 | arch_initcall(pl011_init); | |
1da177e4 LT |
1929 | module_exit(pl011_exit); |
1930 | ||
1931 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
1932 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
1933 | MODULE_LICENSE("GPL"); |