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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for AMBA serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright 1999 ARM Limited | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 8 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
1da177e4 LT |
24 | * This is a generic driver for ARM AMBA-type serial ports. They |
25 | * have a lot of 16550-like features, but are not register compatible. | |
26 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
27 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
28 | * required, these have to be supplied via some other means (eg, GPIO) | |
29 | * and hooked into this driver. | |
30 | */ | |
1da177e4 | 31 | |
cb06ff10 | 32 | |
1da177e4 LT |
33 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
34 | #define SUPPORT_SYSRQ | |
35 | #endif | |
36 | ||
37 | #include <linux/module.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/console.h> | |
41 | #include <linux/sysrq.h> | |
42 | #include <linux/device.h> | |
43 | #include <linux/tty.h> | |
44 | #include <linux/tty_flip.h> | |
45 | #include <linux/serial_core.h> | |
46 | #include <linux/serial.h> | |
a62c80e5 RK |
47 | #include <linux/amba/bus.h> |
48 | #include <linux/amba/serial.h> | |
f8ce2547 | 49 | #include <linux/clk.h> |
5a0e3ad6 | 50 | #include <linux/slab.h> |
68b65f73 RK |
51 | #include <linux/dmaengine.h> |
52 | #include <linux/dma-mapping.h> | |
53 | #include <linux/scatterlist.h> | |
c16d51a3 | 54 | #include <linux/delay.h> |
258aea76 | 55 | #include <linux/types.h> |
32614aad ML |
56 | #include <linux/of.h> |
57 | #include <linux/of_device.h> | |
258e0551 | 58 | #include <linux/pinctrl/consumer.h> |
cb70706c | 59 | #include <linux/sizes.h> |
de609582 | 60 | #include <linux/io.h> |
734745ca | 61 | #include <linux/workqueue.h> |
1da177e4 LT |
62 | |
63 | #define UART_NR 14 | |
64 | ||
65 | #define SERIAL_AMBA_MAJOR 204 | |
66 | #define SERIAL_AMBA_MINOR 64 | |
67 | #define SERIAL_AMBA_NR UART_NR | |
68 | ||
69 | #define AMBA_ISR_PASS_LIMIT 256 | |
70 | ||
b63d4f0f RK |
71 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
72 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 73 | |
5926a295 AR |
74 | /* There is by now at least one vendor with differing details, so handle it */ |
75 | struct vendor_data { | |
76 | unsigned int ifls; | |
ec489aa8 LW |
77 | unsigned int lcrh_tx; |
78 | unsigned int lcrh_rx; | |
ac3e3fb4 | 79 | bool oversampling; |
38d62436 | 80 | bool dma_threshold; |
4fd0690b | 81 | bool cts_event_workaround; |
78506f22 | 82 | |
ea33640a | 83 | unsigned int (*get_fifosize)(struct amba_device *dev); |
5926a295 AR |
84 | }; |
85 | ||
ea33640a | 86 | static unsigned int get_fifosize_arm(struct amba_device *dev) |
78506f22 | 87 | { |
ea33640a | 88 | return amba_rev(dev) < 3 ? 16 : 32; |
78506f22 JK |
89 | } |
90 | ||
5926a295 AR |
91 | static struct vendor_data vendor_arm = { |
92 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
ec489aa8 LW |
93 | .lcrh_tx = UART011_LCRH, |
94 | .lcrh_rx = UART011_LCRH, | |
ac3e3fb4 | 95 | .oversampling = false, |
38d62436 | 96 | .dma_threshold = false, |
4fd0690b | 97 | .cts_event_workaround = false, |
78506f22 | 98 | .get_fifosize = get_fifosize_arm, |
5926a295 AR |
99 | }; |
100 | ||
ea33640a | 101 | static unsigned int get_fifosize_st(struct amba_device *dev) |
78506f22 JK |
102 | { |
103 | return 64; | |
104 | } | |
105 | ||
5926a295 AR |
106 | static struct vendor_data vendor_st = { |
107 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, | |
ec489aa8 LW |
108 | .lcrh_tx = ST_UART011_LCRH_TX, |
109 | .lcrh_rx = ST_UART011_LCRH_RX, | |
ac3e3fb4 | 110 | .oversampling = true, |
38d62436 | 111 | .dma_threshold = true, |
4fd0690b | 112 | .cts_event_workaround = true, |
78506f22 | 113 | .get_fifosize = get_fifosize_st, |
1da177e4 LT |
114 | }; |
115 | ||
68b65f73 | 116 | /* Deals with DMA transactions */ |
ead76f32 LW |
117 | |
118 | struct pl011_sgbuf { | |
119 | struct scatterlist sg; | |
120 | char *buf; | |
121 | }; | |
122 | ||
123 | struct pl011_dmarx_data { | |
124 | struct dma_chan *chan; | |
125 | struct completion complete; | |
126 | bool use_buf_b; | |
127 | struct pl011_sgbuf sgbuf_a; | |
128 | struct pl011_sgbuf sgbuf_b; | |
129 | dma_cookie_t cookie; | |
130 | bool running; | |
cb06ff10 CM |
131 | struct timer_list timer; |
132 | unsigned int last_residue; | |
133 | unsigned long last_jiffies; | |
134 | bool auto_poll_rate; | |
135 | unsigned int poll_rate; | |
136 | unsigned int poll_timeout; | |
ead76f32 LW |
137 | }; |
138 | ||
68b65f73 RK |
139 | struct pl011_dmatx_data { |
140 | struct dma_chan *chan; | |
141 | struct scatterlist sg; | |
142 | char *buf; | |
143 | bool queued; | |
144 | }; | |
145 | ||
c19f12b5 RK |
146 | /* |
147 | * We wrap our port structure around the generic uart_port. | |
148 | */ | |
149 | struct uart_amba_port { | |
150 | struct uart_port port; | |
151 | struct clk *clk; | |
152 | const struct vendor_data *vendor; | |
68b65f73 | 153 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
154 | unsigned int im; /* interrupt mask */ |
155 | unsigned int old_status; | |
ffca2b11 | 156 | unsigned int fifosize; /* vendor-specific */ |
c19f12b5 RK |
157 | unsigned int lcrh_tx; /* vendor-specific */ |
158 | unsigned int lcrh_rx; /* vendor-specific */ | |
d8d8ffa4 | 159 | unsigned int old_cr; /* state during shutdown */ |
734745ca | 160 | struct delayed_work tx_softirq_work; |
c19f12b5 | 161 | bool autorts; |
734745ca | 162 | unsigned int tx_irq_seen; /* 0=none, 1=1, 2=2 or more */ |
c19f12b5 | 163 | char type[12]; |
68b65f73 RK |
164 | #ifdef CONFIG_DMA_ENGINE |
165 | /* DMA stuff */ | |
ead76f32 LW |
166 | bool using_tx_dma; |
167 | bool using_rx_dma; | |
168 | struct pl011_dmarx_data dmarx; | |
68b65f73 RK |
169 | struct pl011_dmatx_data dmatx; |
170 | #endif | |
171 | }; | |
172 | ||
29772c4e LW |
173 | /* |
174 | * Reads up to 256 characters from the FIFO or until it's empty and | |
175 | * inserts them into the TTY layer. Returns the number of characters | |
176 | * read from the FIFO. | |
177 | */ | |
178 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) | |
179 | { | |
180 | u16 status, ch; | |
181 | unsigned int flag, max_count = 256; | |
182 | int fifotaken = 0; | |
183 | ||
184 | while (max_count--) { | |
185 | status = readw(uap->port.membase + UART01x_FR); | |
186 | if (status & UART01x_FR_RXFE) | |
187 | break; | |
188 | ||
189 | /* Take chars from the FIFO and update status */ | |
190 | ch = readw(uap->port.membase + UART01x_DR) | | |
191 | UART_DUMMY_DR_RX; | |
192 | flag = TTY_NORMAL; | |
193 | uap->port.icount.rx++; | |
194 | fifotaken++; | |
195 | ||
196 | if (unlikely(ch & UART_DR_ERROR)) { | |
197 | if (ch & UART011_DR_BE) { | |
198 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
199 | uap->port.icount.brk++; | |
200 | if (uart_handle_break(&uap->port)) | |
201 | continue; | |
202 | } else if (ch & UART011_DR_PE) | |
203 | uap->port.icount.parity++; | |
204 | else if (ch & UART011_DR_FE) | |
205 | uap->port.icount.frame++; | |
206 | if (ch & UART011_DR_OE) | |
207 | uap->port.icount.overrun++; | |
208 | ||
209 | ch &= uap->port.read_status_mask; | |
210 | ||
211 | if (ch & UART011_DR_BE) | |
212 | flag = TTY_BREAK; | |
213 | else if (ch & UART011_DR_PE) | |
214 | flag = TTY_PARITY; | |
215 | else if (ch & UART011_DR_FE) | |
216 | flag = TTY_FRAME; | |
217 | } | |
218 | ||
219 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) | |
220 | continue; | |
221 | ||
222 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
223 | } | |
224 | ||
225 | return fifotaken; | |
226 | } | |
227 | ||
228 | ||
68b65f73 RK |
229 | /* |
230 | * All the DMA operation mode stuff goes inside this ifdef. | |
231 | * This assumes that you have a generic DMA device interface, | |
232 | * no custom DMA interfaces are supported. | |
233 | */ | |
234 | #ifdef CONFIG_DMA_ENGINE | |
235 | ||
236 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
237 | ||
ead76f32 LW |
238 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
239 | enum dma_data_direction dir) | |
240 | { | |
cb06ff10 CM |
241 | dma_addr_t dma_addr; |
242 | ||
243 | sg->buf = dma_alloc_coherent(chan->device->dev, | |
244 | PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); | |
ead76f32 LW |
245 | if (!sg->buf) |
246 | return -ENOMEM; | |
247 | ||
cb06ff10 CM |
248 | sg_init_table(&sg->sg, 1); |
249 | sg_set_page(&sg->sg, phys_to_page(dma_addr), | |
250 | PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); | |
251 | sg_dma_address(&sg->sg) = dma_addr; | |
c64be923 | 252 | sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; |
ead76f32 | 253 | |
ead76f32 LW |
254 | return 0; |
255 | } | |
256 | ||
257 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |
258 | enum dma_data_direction dir) | |
259 | { | |
260 | if (sg->buf) { | |
cb06ff10 CM |
261 | dma_free_coherent(chan->device->dev, |
262 | PL011_DMA_BUFFER_SIZE, sg->buf, | |
263 | sg_dma_address(&sg->sg)); | |
ead76f32 LW |
264 | } |
265 | } | |
266 | ||
787b0c1f | 267 | static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *uap) |
68b65f73 RK |
268 | { |
269 | /* DMA is the sole user of the platform data right now */ | |
574de559 | 270 | struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); |
68b65f73 RK |
271 | struct dma_slave_config tx_conf = { |
272 | .dst_addr = uap->port.mapbase + UART01x_DR, | |
273 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 274 | .direction = DMA_MEM_TO_DEV, |
68b65f73 | 275 | .dst_maxburst = uap->fifosize >> 1, |
258aea76 | 276 | .device_fc = false, |
68b65f73 RK |
277 | }; |
278 | struct dma_chan *chan; | |
279 | dma_cap_mask_t mask; | |
280 | ||
787b0c1f | 281 | chan = dma_request_slave_channel(dev, "tx"); |
68b65f73 | 282 | |
68b65f73 | 283 | if (!chan) { |
787b0c1f AB |
284 | /* We need platform data */ |
285 | if (!plat || !plat->dma_filter) { | |
286 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
287 | return; | |
288 | } | |
289 | ||
290 | /* Try to acquire a generic DMA engine slave TX channel */ | |
291 | dma_cap_zero(mask); | |
292 | dma_cap_set(DMA_SLAVE, mask); | |
293 | ||
294 | chan = dma_request_channel(mask, plat->dma_filter, | |
295 | plat->dma_tx_param); | |
296 | if (!chan) { | |
297 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
298 | return; | |
299 | } | |
68b65f73 RK |
300 | } |
301 | ||
302 | dmaengine_slave_config(chan, &tx_conf); | |
303 | uap->dmatx.chan = chan; | |
304 | ||
305 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
306 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
307 | |
308 | /* Optionally make use of an RX channel as well */ | |
787b0c1f | 309 | chan = dma_request_slave_channel(dev, "rx"); |
0d3c673e | 310 | |
787b0c1f AB |
311 | if (!chan && plat->dma_rx_param) { |
312 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); | |
313 | ||
314 | if (!chan) { | |
315 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
316 | return; | |
317 | } | |
318 | } | |
319 | ||
320 | if (chan) { | |
ead76f32 LW |
321 | struct dma_slave_config rx_conf = { |
322 | .src_addr = uap->port.mapbase + UART01x_DR, | |
323 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 324 | .direction = DMA_DEV_TO_MEM, |
b2aeb775 | 325 | .src_maxburst = uap->fifosize >> 2, |
258aea76 | 326 | .device_fc = false, |
ead76f32 | 327 | }; |
2d3b7d6e AJ |
328 | struct dma_slave_caps caps; |
329 | ||
330 | /* | |
331 | * Some DMA controllers provide information on their capabilities. | |
332 | * If the controller does, check for suitable residue processing | |
333 | * otherwise assime all is well. | |
334 | */ | |
335 | if (0 == dma_get_slave_caps(chan, &caps)) { | |
336 | if (caps.residue_granularity == | |
337 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { | |
338 | dma_release_channel(chan); | |
339 | dev_info(uap->port.dev, | |
340 | "RX DMA disabled - no residue processing\n"); | |
341 | return; | |
342 | } | |
343 | } | |
ead76f32 LW |
344 | dmaengine_slave_config(chan, &rx_conf); |
345 | uap->dmarx.chan = chan; | |
346 | ||
98267d33 | 347 | uap->dmarx.auto_poll_rate = false; |
8f898bfd | 348 | if (plat && plat->dma_rx_poll_enable) { |
cb06ff10 CM |
349 | /* Set poll rate if specified. */ |
350 | if (plat->dma_rx_poll_rate) { | |
351 | uap->dmarx.auto_poll_rate = false; | |
352 | uap->dmarx.poll_rate = plat->dma_rx_poll_rate; | |
353 | } else { | |
354 | /* | |
355 | * 100 ms defaults to poll rate if not | |
356 | * specified. This will be adjusted with | |
357 | * the baud rate at set_termios. | |
358 | */ | |
359 | uap->dmarx.auto_poll_rate = true; | |
360 | uap->dmarx.poll_rate = 100; | |
361 | } | |
362 | /* 3 secs defaults poll_timeout if not specified. */ | |
363 | if (plat->dma_rx_poll_timeout) | |
364 | uap->dmarx.poll_timeout = | |
365 | plat->dma_rx_poll_timeout; | |
366 | else | |
367 | uap->dmarx.poll_timeout = 3000; | |
98267d33 AJ |
368 | } else if (!plat && dev->of_node) { |
369 | uap->dmarx.auto_poll_rate = of_property_read_bool( | |
370 | dev->of_node, "auto-poll"); | |
371 | if (uap->dmarx.auto_poll_rate) { | |
372 | u32 x; | |
373 | ||
374 | if (0 == of_property_read_u32(dev->of_node, | |
375 | "poll-rate-ms", &x)) | |
376 | uap->dmarx.poll_rate = x; | |
377 | else | |
378 | uap->dmarx.poll_rate = 100; | |
379 | if (0 == of_property_read_u32(dev->of_node, | |
380 | "poll-timeout-ms", &x)) | |
381 | uap->dmarx.poll_timeout = x; | |
382 | else | |
383 | uap->dmarx.poll_timeout = 3000; | |
384 | } | |
385 | } | |
ead76f32 LW |
386 | dev_info(uap->port.dev, "DMA channel RX %s\n", |
387 | dma_chan_name(uap->dmarx.chan)); | |
388 | } | |
68b65f73 RK |
389 | } |
390 | ||
391 | #ifndef MODULE | |
392 | /* | |
393 | * Stack up the UARTs and let the above initcall be done at device | |
394 | * initcall time, because the serial driver is called as an arch | |
395 | * initcall, and at this time the DMA subsystem is not yet registered. | |
396 | * At this point the driver will switch over to using DMA where desired. | |
397 | */ | |
398 | struct dma_uap { | |
399 | struct list_head node; | |
400 | struct uart_amba_port *uap; | |
787b0c1f | 401 | struct device *dev; |
c19f12b5 RK |
402 | }; |
403 | ||
68b65f73 RK |
404 | static LIST_HEAD(pl011_dma_uarts); |
405 | ||
406 | static int __init pl011_dma_initcall(void) | |
407 | { | |
408 | struct list_head *node, *tmp; | |
409 | ||
410 | list_for_each_safe(node, tmp, &pl011_dma_uarts) { | |
411 | struct dma_uap *dmau = list_entry(node, struct dma_uap, node); | |
787b0c1f | 412 | pl011_dma_probe_initcall(dmau->dev, dmau->uap); |
68b65f73 RK |
413 | list_del(node); |
414 | kfree(dmau); | |
415 | } | |
416 | return 0; | |
417 | } | |
418 | ||
419 | device_initcall(pl011_dma_initcall); | |
420 | ||
787b0c1f | 421 | static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) |
68b65f73 RK |
422 | { |
423 | struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL); | |
424 | if (dmau) { | |
425 | dmau->uap = uap; | |
787b0c1f | 426 | dmau->dev = dev; |
68b65f73 RK |
427 | list_add_tail(&dmau->node, &pl011_dma_uarts); |
428 | } | |
429 | } | |
430 | #else | |
787b0c1f | 431 | static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) |
68b65f73 | 432 | { |
787b0c1f | 433 | pl011_dma_probe_initcall(dev, uap); |
68b65f73 RK |
434 | } |
435 | #endif | |
436 | ||
437 | static void pl011_dma_remove(struct uart_amba_port *uap) | |
438 | { | |
439 | /* TODO: remove the initcall if it has not yet executed */ | |
440 | if (uap->dmatx.chan) | |
441 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
442 | if (uap->dmarx.chan) |
443 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
444 | } |
445 | ||
734745ca | 446 | /* Forward declare these for the refill routine */ |
68b65f73 | 447 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); |
734745ca | 448 | static void pl011_start_tx_pio(struct uart_amba_port *uap); |
68b65f73 RK |
449 | |
450 | /* | |
451 | * The current DMA TX buffer has been sent. | |
452 | * Try to queue up another DMA buffer. | |
453 | */ | |
454 | static void pl011_dma_tx_callback(void *data) | |
455 | { | |
456 | struct uart_amba_port *uap = data; | |
457 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
458 | unsigned long flags; | |
459 | u16 dmacr; | |
460 | ||
461 | spin_lock_irqsave(&uap->port.lock, flags); | |
462 | if (uap->dmatx.queued) | |
463 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
464 | DMA_TO_DEVICE); | |
465 | ||
466 | dmacr = uap->dmacr; | |
467 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
468 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
469 | ||
470 | /* | |
471 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
472 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
473 | * | |
474 | * Note: we need to be careful here of a potential race between DMA | |
475 | * and the rest of the driver - if the driver disables TX DMA while | |
476 | * a TX buffer completing, we must update the tx queued status to | |
477 | * get further refills (hence we check dmacr). | |
478 | */ | |
479 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
480 | uart_circ_empty(&uap->port.state->xmit)) { | |
481 | uap->dmatx.queued = false; | |
482 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
483 | return; | |
484 | } | |
485 | ||
734745ca | 486 | if (pl011_dma_tx_refill(uap) <= 0) |
68b65f73 RK |
487 | /* |
488 | * We didn't queue a DMA buffer for some reason, but we | |
489 | * have data pending to be sent. Re-enable the TX IRQ. | |
490 | */ | |
734745ca DM |
491 | pl011_start_tx_pio(uap); |
492 | ||
68b65f73 RK |
493 | spin_unlock_irqrestore(&uap->port.lock, flags); |
494 | } | |
495 | ||
496 | /* | |
497 | * Try to refill the TX DMA buffer. | |
498 | * Locking: called with port lock held and IRQs disabled. | |
499 | * Returns: | |
500 | * 1 if we queued up a TX DMA buffer. | |
501 | * 0 if we didn't want to handle this by DMA | |
502 | * <0 on error | |
503 | */ | |
504 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
505 | { | |
506 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
507 | struct dma_chan *chan = dmatx->chan; | |
508 | struct dma_device *dma_dev = chan->device; | |
509 | struct dma_async_tx_descriptor *desc; | |
510 | struct circ_buf *xmit = &uap->port.state->xmit; | |
511 | unsigned int count; | |
512 | ||
513 | /* | |
514 | * Try to avoid the overhead involved in using DMA if the | |
515 | * transaction fits in the first half of the FIFO, by using | |
516 | * the standard interrupt handling. This ensures that we | |
517 | * issue a uart_write_wakeup() at the appropriate time. | |
518 | */ | |
519 | count = uart_circ_chars_pending(xmit); | |
520 | if (count < (uap->fifosize >> 1)) { | |
521 | uap->dmatx.queued = false; | |
522 | return 0; | |
523 | } | |
524 | ||
525 | /* | |
526 | * Bodge: don't send the last character by DMA, as this | |
527 | * will prevent XON from notifying us to restart DMA. | |
528 | */ | |
529 | count -= 1; | |
530 | ||
531 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
532 | if (count > PL011_DMA_BUFFER_SIZE) | |
533 | count = PL011_DMA_BUFFER_SIZE; | |
534 | ||
535 | if (xmit->tail < xmit->head) | |
536 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
537 | else { | |
538 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
e2a545a6 AJ |
539 | size_t second; |
540 | ||
541 | if (first > count) | |
542 | first = count; | |
543 | second = count - first; | |
68b65f73 RK |
544 | |
545 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
546 | if (second) | |
547 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
548 | } | |
549 | ||
550 | dmatx->sg.length = count; | |
551 | ||
552 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
553 | uap->dmatx.queued = false; | |
554 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
555 | return -EBUSY; | |
556 | } | |
557 | ||
16052827 | 558 | desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, |
68b65f73 RK |
559 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
560 | if (!desc) { | |
561 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
562 | uap->dmatx.queued = false; | |
563 | /* | |
564 | * If DMA cannot be used right now, we complete this | |
565 | * transaction via IRQ and let the TTY layer retry. | |
566 | */ | |
567 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
568 | return -EBUSY; | |
569 | } | |
570 | ||
571 | /* Some data to go along to the callback */ | |
572 | desc->callback = pl011_dma_tx_callback; | |
573 | desc->callback_param = uap; | |
574 | ||
575 | /* All errors should happen at prepare time */ | |
576 | dmaengine_submit(desc); | |
577 | ||
578 | /* Fire the DMA transaction */ | |
579 | dma_dev->device_issue_pending(chan); | |
580 | ||
581 | uap->dmacr |= UART011_TXDMAE; | |
582 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
583 | uap->dmatx.queued = true; | |
584 | ||
585 | /* | |
586 | * Now we know that DMA will fire, so advance the ring buffer | |
587 | * with the stuff we just dispatched. | |
588 | */ | |
589 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
590 | uap->port.icount.tx += count; | |
591 | ||
592 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
593 | uart_write_wakeup(&uap->port); | |
594 | ||
595 | return 1; | |
596 | } | |
597 | ||
598 | /* | |
599 | * We received a transmit interrupt without a pending X-char but with | |
600 | * pending characters. | |
601 | * Locking: called with port lock held and IRQs disabled. | |
602 | * Returns: | |
603 | * false if we want to use PIO to transmit | |
604 | * true if we queued a DMA buffer | |
605 | */ | |
606 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
607 | { | |
ead76f32 | 608 | if (!uap->using_tx_dma) |
68b65f73 RK |
609 | return false; |
610 | ||
611 | /* | |
612 | * If we already have a TX buffer queued, but received a | |
613 | * TX interrupt, it will be because we've just sent an X-char. | |
614 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
615 | */ | |
616 | if (uap->dmatx.queued) { | |
617 | uap->dmacr |= UART011_TXDMAE; | |
618 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
619 | uap->im &= ~UART011_TXIM; | |
620 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
621 | return true; | |
622 | } | |
623 | ||
624 | /* | |
625 | * We don't have a TX buffer queued, so try to queue one. | |
25985edc | 626 | * If we successfully queued a buffer, mask the TX IRQ. |
68b65f73 RK |
627 | */ |
628 | if (pl011_dma_tx_refill(uap) > 0) { | |
629 | uap->im &= ~UART011_TXIM; | |
630 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
631 | return true; | |
632 | } | |
633 | return false; | |
634 | } | |
635 | ||
636 | /* | |
637 | * Stop the DMA transmit (eg, due to received XOFF). | |
638 | * Locking: called with port lock held and IRQs disabled. | |
639 | */ | |
640 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
641 | { | |
642 | if (uap->dmatx.queued) { | |
643 | uap->dmacr &= ~UART011_TXDMAE; | |
644 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
645 | } | |
646 | } | |
647 | ||
648 | /* | |
649 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
650 | * character queued for send, try to get that character out ASAP. | |
651 | * Locking: called with port lock held and IRQs disabled. | |
652 | * Returns: | |
653 | * false if we want the TX IRQ to be enabled | |
654 | * true if we have a buffer queued | |
655 | */ | |
656 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
657 | { | |
658 | u16 dmacr; | |
659 | ||
ead76f32 | 660 | if (!uap->using_tx_dma) |
68b65f73 RK |
661 | return false; |
662 | ||
663 | if (!uap->port.x_char) { | |
664 | /* no X-char, try to push chars out in DMA mode */ | |
665 | bool ret = true; | |
666 | ||
667 | if (!uap->dmatx.queued) { | |
668 | if (pl011_dma_tx_refill(uap) > 0) { | |
669 | uap->im &= ~UART011_TXIM; | |
734745ca DM |
670 | writew(uap->im, uap->port.membase + |
671 | UART011_IMSC); | |
672 | } else | |
68b65f73 | 673 | ret = false; |
68b65f73 RK |
674 | } else if (!(uap->dmacr & UART011_TXDMAE)) { |
675 | uap->dmacr |= UART011_TXDMAE; | |
676 | writew(uap->dmacr, | |
677 | uap->port.membase + UART011_DMACR); | |
678 | } | |
679 | return ret; | |
680 | } | |
681 | ||
682 | /* | |
683 | * We have an X-char to send. Disable DMA to prevent it loading | |
684 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
685 | */ | |
686 | dmacr = uap->dmacr; | |
687 | uap->dmacr &= ~UART011_TXDMAE; | |
688 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
689 | ||
690 | if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { | |
691 | /* | |
692 | * No space in the FIFO, so enable the transmit interrupt | |
693 | * so we know when there is space. Note that once we've | |
694 | * loaded the character, we should just re-enable DMA. | |
695 | */ | |
696 | return false; | |
697 | } | |
698 | ||
699 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
700 | uap->port.icount.tx++; | |
701 | uap->port.x_char = 0; | |
702 | ||
703 | /* Success - restore the DMA state */ | |
704 | uap->dmacr = dmacr; | |
705 | writew(dmacr, uap->port.membase + UART011_DMACR); | |
706 | ||
707 | return true; | |
708 | } | |
709 | ||
710 | /* | |
711 | * Flush the transmit buffer. | |
712 | * Locking: called with port lock held and IRQs disabled. | |
713 | */ | |
714 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
b83286bf FE |
715 | __releases(&uap->port.lock) |
716 | __acquires(&uap->port.lock) | |
68b65f73 | 717 | { |
a5820c24 DT |
718 | struct uart_amba_port *uap = |
719 | container_of(port, struct uart_amba_port, port); | |
68b65f73 | 720 | |
ead76f32 | 721 | if (!uap->using_tx_dma) |
68b65f73 RK |
722 | return; |
723 | ||
724 | /* Avoid deadlock with the DMA engine callback */ | |
725 | spin_unlock(&uap->port.lock); | |
726 | dmaengine_terminate_all(uap->dmatx.chan); | |
727 | spin_lock(&uap->port.lock); | |
728 | if (uap->dmatx.queued) { | |
729 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
730 | DMA_TO_DEVICE); | |
731 | uap->dmatx.queued = false; | |
732 | uap->dmacr &= ~UART011_TXDMAE; | |
733 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
734 | } | |
735 | } | |
736 | ||
ead76f32 LW |
737 | static void pl011_dma_rx_callback(void *data); |
738 | ||
739 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
740 | { | |
741 | struct dma_chan *rxchan = uap->dmarx.chan; | |
ead76f32 LW |
742 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
743 | struct dma_async_tx_descriptor *desc; | |
744 | struct pl011_sgbuf *sgbuf; | |
745 | ||
746 | if (!rxchan) | |
747 | return -EIO; | |
748 | ||
749 | /* Start the RX DMA job */ | |
750 | sgbuf = uap->dmarx.use_buf_b ? | |
751 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
16052827 | 752 | desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, |
a485df4b | 753 | DMA_DEV_TO_MEM, |
ead76f32 LW |
754 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
755 | /* | |
756 | * If the DMA engine is busy and cannot prepare a | |
757 | * channel, no big deal, the driver will fall back | |
758 | * to interrupt mode as a result of this error code. | |
759 | */ | |
760 | if (!desc) { | |
761 | uap->dmarx.running = false; | |
762 | dmaengine_terminate_all(rxchan); | |
763 | return -EBUSY; | |
764 | } | |
765 | ||
766 | /* Some data to go along to the callback */ | |
767 | desc->callback = pl011_dma_rx_callback; | |
768 | desc->callback_param = uap; | |
769 | dmarx->cookie = dmaengine_submit(desc); | |
770 | dma_async_issue_pending(rxchan); | |
771 | ||
772 | uap->dmacr |= UART011_RXDMAE; | |
773 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
774 | uap->dmarx.running = true; | |
775 | ||
776 | uap->im &= ~UART011_RXIM; | |
777 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
778 | ||
779 | return 0; | |
780 | } | |
781 | ||
782 | /* | |
783 | * This is called when either the DMA job is complete, or | |
784 | * the FIFO timeout interrupt occurred. This must be called | |
785 | * with the port spinlock uap->port.lock held. | |
786 | */ | |
787 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
788 | u32 pending, bool use_buf_b, | |
789 | bool readfifo) | |
790 | { | |
05c7cd39 | 791 | struct tty_port *port = &uap->port.state->port; |
ead76f32 LW |
792 | struct pl011_sgbuf *sgbuf = use_buf_b ? |
793 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
ead76f32 LW |
794 | int dma_count = 0; |
795 | u32 fifotaken = 0; /* only used for vdbg() */ | |
796 | ||
cb06ff10 CM |
797 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
798 | int dmataken = 0; | |
799 | ||
800 | if (uap->dmarx.poll_rate) { | |
801 | /* The data can be taken by polling */ | |
802 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
803 | /* Recalculate the pending size */ | |
804 | if (pending >= dmataken) | |
805 | pending -= dmataken; | |
806 | } | |
807 | ||
808 | /* Pick the remain data from the DMA */ | |
ead76f32 | 809 | if (pending) { |
ead76f32 LW |
810 | |
811 | /* | |
812 | * First take all chars in the DMA pipe, then look in the FIFO. | |
813 | * Note that tty_insert_flip_buf() tries to take as many chars | |
814 | * as it can. | |
815 | */ | |
cb06ff10 CM |
816 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, |
817 | pending); | |
ead76f32 LW |
818 | |
819 | uap->port.icount.rx += dma_count; | |
820 | if (dma_count < pending) | |
821 | dev_warn(uap->port.dev, | |
822 | "couldn't insert all characters (TTY is full?)\n"); | |
823 | } | |
824 | ||
cb06ff10 CM |
825 | /* Reset the last_residue for Rx DMA poll */ |
826 | if (uap->dmarx.poll_rate) | |
827 | dmarx->last_residue = sgbuf->sg.length; | |
828 | ||
ead76f32 LW |
829 | /* |
830 | * Only continue with trying to read the FIFO if all DMA chars have | |
831 | * been taken first. | |
832 | */ | |
833 | if (dma_count == pending && readfifo) { | |
834 | /* Clear any error flags */ | |
835 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
836 | uap->port.membase + UART011_ICR); | |
837 | ||
838 | /* | |
839 | * If we read all the DMA'd characters, and we had an | |
29772c4e LW |
840 | * incomplete buffer, that could be due to an rx error, or |
841 | * maybe we just timed out. Read any pending chars and check | |
842 | * the error status. | |
843 | * | |
844 | * Error conditions will only occur in the FIFO, these will | |
845 | * trigger an immediate interrupt and stop the DMA job, so we | |
846 | * will always find the error in the FIFO, never in the DMA | |
847 | * buffer. | |
ead76f32 | 848 | */ |
29772c4e | 849 | fifotaken = pl011_fifo_to_tty(uap); |
ead76f32 LW |
850 | } |
851 | ||
852 | spin_unlock(&uap->port.lock); | |
853 | dev_vdbg(uap->port.dev, | |
854 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
855 | dma_count, fifotaken); | |
2e124b4a | 856 | tty_flip_buffer_push(port); |
ead76f32 LW |
857 | spin_lock(&uap->port.lock); |
858 | } | |
859 | ||
860 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
861 | { | |
862 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
863 | struct dma_chan *rxchan = dmarx->chan; | |
864 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? | |
865 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
866 | size_t pending; | |
867 | struct dma_tx_state state; | |
868 | enum dma_status dmastat; | |
869 | ||
870 | /* | |
871 | * Pause the transfer so we can trust the current counter, | |
872 | * do this before we pause the PL011 block, else we may | |
873 | * overflow the FIFO. | |
874 | */ | |
875 | if (dmaengine_pause(rxchan)) | |
876 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
877 | dmastat = rxchan->device->device_tx_status(rxchan, | |
878 | dmarx->cookie, &state); | |
879 | if (dmastat != DMA_PAUSED) | |
880 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
881 | ||
882 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
883 | uap->dmacr &= ~UART011_RXDMAE; | |
884 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
885 | uap->dmarx.running = false; | |
886 | ||
887 | pending = sgbuf->sg.length - state.residue; | |
888 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
889 | /* Then we terminate the transfer - we now know our residue */ | |
890 | dmaengine_terminate_all(rxchan); | |
891 | ||
892 | /* | |
893 | * This will take the chars we have so far and insert | |
894 | * into the framework. | |
895 | */ | |
896 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
897 | ||
898 | /* Switch buffer & re-trigger DMA job */ | |
899 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
900 | if (pl011_dma_rx_trigger_dma(uap)) { | |
901 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
902 | "fall back to interrupt mode\n"); | |
903 | uap->im |= UART011_RXIM; | |
904 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
905 | } | |
906 | } | |
907 | ||
908 | static void pl011_dma_rx_callback(void *data) | |
909 | { | |
910 | struct uart_amba_port *uap = data; | |
911 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
6dc01aa6 | 912 | struct dma_chan *rxchan = dmarx->chan; |
ead76f32 | 913 | bool lastbuf = dmarx->use_buf_b; |
6dc01aa6 CM |
914 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? |
915 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
916 | size_t pending; | |
917 | struct dma_tx_state state; | |
ead76f32 LW |
918 | int ret; |
919 | ||
920 | /* | |
921 | * This completion interrupt occurs typically when the | |
922 | * RX buffer is totally stuffed but no timeout has yet | |
923 | * occurred. When that happens, we just want the RX | |
924 | * routine to flush out the secondary DMA buffer while | |
925 | * we immediately trigger the next DMA job. | |
926 | */ | |
927 | spin_lock_irq(&uap->port.lock); | |
6dc01aa6 CM |
928 | /* |
929 | * Rx data can be taken by the UART interrupts during | |
930 | * the DMA irq handler. So we check the residue here. | |
931 | */ | |
932 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
933 | pending = sgbuf->sg.length - state.residue; | |
934 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
935 | /* Then we terminate the transfer - we now know our residue */ | |
936 | dmaengine_terminate_all(rxchan); | |
937 | ||
ead76f32 LW |
938 | uap->dmarx.running = false; |
939 | dmarx->use_buf_b = !lastbuf; | |
940 | ret = pl011_dma_rx_trigger_dma(uap); | |
941 | ||
6dc01aa6 | 942 | pl011_dma_rx_chars(uap, pending, lastbuf, false); |
ead76f32 LW |
943 | spin_unlock_irq(&uap->port.lock); |
944 | /* | |
945 | * Do this check after we picked the DMA chars so we don't | |
946 | * get some IRQ immediately from RX. | |
947 | */ | |
948 | if (ret) { | |
949 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
950 | "fall back to interrupt mode\n"); | |
951 | uap->im |= UART011_RXIM; | |
952 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
953 | } | |
954 | } | |
955 | ||
956 | /* | |
957 | * Stop accepting received characters, when we're shutting down or | |
958 | * suspending this port. | |
959 | * Locking: called with port lock held and IRQs disabled. | |
960 | */ | |
961 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
962 | { | |
963 | /* FIXME. Just disable the DMA enable */ | |
964 | uap->dmacr &= ~UART011_RXDMAE; | |
965 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
966 | } | |
68b65f73 | 967 | |
cb06ff10 CM |
968 | /* |
969 | * Timer handler for Rx DMA polling. | |
970 | * Every polling, It checks the residue in the dma buffer and transfer | |
971 | * data to the tty. Also, last_residue is updated for the next polling. | |
972 | */ | |
973 | static void pl011_dma_rx_poll(unsigned long args) | |
974 | { | |
975 | struct uart_amba_port *uap = (struct uart_amba_port *)args; | |
976 | struct tty_port *port = &uap->port.state->port; | |
977 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
978 | struct dma_chan *rxchan = uap->dmarx.chan; | |
979 | unsigned long flags = 0; | |
980 | unsigned int dmataken = 0; | |
981 | unsigned int size = 0; | |
982 | struct pl011_sgbuf *sgbuf; | |
983 | int dma_count; | |
984 | struct dma_tx_state state; | |
985 | ||
986 | sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
987 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
988 | if (likely(state.residue < dmarx->last_residue)) { | |
989 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
990 | size = dmarx->last_residue - state.residue; | |
991 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, | |
992 | size); | |
993 | if (dma_count == size) | |
994 | dmarx->last_residue = state.residue; | |
995 | dmarx->last_jiffies = jiffies; | |
996 | } | |
997 | tty_flip_buffer_push(port); | |
998 | ||
999 | /* | |
1000 | * If no data is received in poll_timeout, the driver will fall back | |
1001 | * to interrupt mode. We will retrigger DMA at the first interrupt. | |
1002 | */ | |
1003 | if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) | |
1004 | > uap->dmarx.poll_timeout) { | |
1005 | ||
1006 | spin_lock_irqsave(&uap->port.lock, flags); | |
1007 | pl011_dma_rx_stop(uap); | |
c25a1ad7 GL |
1008 | uap->im |= UART011_RXIM; |
1009 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
cb06ff10 CM |
1010 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1011 | ||
1012 | uap->dmarx.running = false; | |
1013 | dmaengine_terminate_all(rxchan); | |
1014 | del_timer(&uap->dmarx.timer); | |
1015 | } else { | |
1016 | mod_timer(&uap->dmarx.timer, | |
1017 | jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1018 | } | |
1019 | } | |
1020 | ||
68b65f73 RK |
1021 | static void pl011_dma_startup(struct uart_amba_port *uap) |
1022 | { | |
ead76f32 LW |
1023 | int ret; |
1024 | ||
68b65f73 RK |
1025 | if (!uap->dmatx.chan) |
1026 | return; | |
1027 | ||
4c0be45b | 1028 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); |
68b65f73 RK |
1029 | if (!uap->dmatx.buf) { |
1030 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
1031 | uap->port.fifosize = uap->fifosize; | |
1032 | return; | |
1033 | } | |
1034 | ||
1035 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
1036 | ||
1037 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
1038 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
1039 | uap->using_tx_dma = true; |
1040 | ||
1041 | if (!uap->dmarx.chan) | |
1042 | goto skip_rx; | |
1043 | ||
1044 | /* Allocate and map DMA RX buffers */ | |
1045 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1046 | DMA_FROM_DEVICE); | |
1047 | if (ret) { | |
1048 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1049 | "RX buffer A", ret); | |
1050 | goto skip_rx; | |
1051 | } | |
68b65f73 | 1052 | |
ead76f32 LW |
1053 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
1054 | DMA_FROM_DEVICE); | |
1055 | if (ret) { | |
1056 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1057 | "RX buffer B", ret); | |
1058 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1059 | DMA_FROM_DEVICE); | |
1060 | goto skip_rx; | |
1061 | } | |
1062 | ||
1063 | uap->using_rx_dma = true; | |
68b65f73 | 1064 | |
ead76f32 | 1065 | skip_rx: |
68b65f73 RK |
1066 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
1067 | uap->dmacr |= UART011_DMAONERR; | |
1068 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
38d62436 RK |
1069 | |
1070 | /* | |
1071 | * ST Micro variants has some specific dma burst threshold | |
1072 | * compensation. Set this to 16 bytes, so burst will only | |
1073 | * be issued above/below 16 bytes. | |
1074 | */ | |
1075 | if (uap->vendor->dma_threshold) | |
1076 | writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, | |
1077 | uap->port.membase + ST_UART011_DMAWM); | |
ead76f32 LW |
1078 | |
1079 | if (uap->using_rx_dma) { | |
1080 | if (pl011_dma_rx_trigger_dma(uap)) | |
1081 | dev_dbg(uap->port.dev, "could not trigger initial " | |
1082 | "RX DMA job, fall back to interrupt mode\n"); | |
cb06ff10 CM |
1083 | if (uap->dmarx.poll_rate) { |
1084 | init_timer(&(uap->dmarx.timer)); | |
1085 | uap->dmarx.timer.function = pl011_dma_rx_poll; | |
1086 | uap->dmarx.timer.data = (unsigned long)uap; | |
1087 | mod_timer(&uap->dmarx.timer, | |
1088 | jiffies + | |
1089 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1090 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1091 | uap->dmarx.last_jiffies = jiffies; | |
1092 | } | |
ead76f32 | 1093 | } |
68b65f73 RK |
1094 | } |
1095 | ||
1096 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1097 | { | |
ead76f32 | 1098 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
1099 | return; |
1100 | ||
1101 | /* Disable RX and TX DMA */ | |
1102 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
1103 | barrier(); | |
1104 | ||
1105 | spin_lock_irq(&uap->port.lock); | |
1106 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
1107 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
1108 | spin_unlock_irq(&uap->port.lock); | |
1109 | ||
ead76f32 LW |
1110 | if (uap->using_tx_dma) { |
1111 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
1112 | dmaengine_terminate_all(uap->dmatx.chan); | |
1113 | if (uap->dmatx.queued) { | |
1114 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
1115 | DMA_TO_DEVICE); | |
1116 | uap->dmatx.queued = false; | |
1117 | } | |
1118 | ||
1119 | kfree(uap->dmatx.buf); | |
1120 | uap->using_tx_dma = false; | |
68b65f73 RK |
1121 | } |
1122 | ||
ead76f32 LW |
1123 | if (uap->using_rx_dma) { |
1124 | dmaengine_terminate_all(uap->dmarx.chan); | |
1125 | /* Clean up the RX DMA */ | |
1126 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); | |
1127 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); | |
cb06ff10 CM |
1128 | if (uap->dmarx.poll_rate) |
1129 | del_timer_sync(&uap->dmarx.timer); | |
ead76f32 LW |
1130 | uap->using_rx_dma = false; |
1131 | } | |
1132 | } | |
68b65f73 | 1133 | |
ead76f32 LW |
1134 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
1135 | { | |
1136 | return uap->using_rx_dma; | |
68b65f73 RK |
1137 | } |
1138 | ||
ead76f32 LW |
1139 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
1140 | { | |
1141 | return uap->using_rx_dma && uap->dmarx.running; | |
1142 | } | |
1143 | ||
68b65f73 RK |
1144 | #else |
1145 | /* Blank functions if the DMA engine is not available */ | |
aabdd290 | 1146 | static inline void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) |
68b65f73 RK |
1147 | { |
1148 | } | |
1149 | ||
1150 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
1151 | { | |
1152 | } | |
1153 | ||
1154 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
1155 | { | |
1156 | } | |
1157 | ||
1158 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1159 | { | |
1160 | } | |
1161 | ||
1162 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
1163 | { | |
1164 | return false; | |
1165 | } | |
1166 | ||
1167 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
1168 | { | |
1169 | } | |
1170 | ||
1171 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
1172 | { | |
1173 | return false; | |
1174 | } | |
1175 | ||
ead76f32 LW |
1176 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
1177 | { | |
1178 | } | |
1179 | ||
1180 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1181 | { | |
1182 | } | |
1183 | ||
1184 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
1185 | { | |
1186 | return -EIO; | |
1187 | } | |
1188 | ||
1189 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
1190 | { | |
1191 | return false; | |
1192 | } | |
1193 | ||
1194 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
1195 | { | |
1196 | return false; | |
1197 | } | |
1198 | ||
68b65f73 RK |
1199 | #define pl011_dma_flush_buffer NULL |
1200 | #endif | |
1201 | ||
b129a8cc | 1202 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 | 1203 | { |
a5820c24 DT |
1204 | struct uart_amba_port *uap = |
1205 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1206 | |
1207 | uap->im &= ~UART011_TXIM; | |
1208 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
68b65f73 | 1209 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
1210 | } |
1211 | ||
734745ca DM |
1212 | static bool pl011_tx_chars(struct uart_amba_port *uap); |
1213 | ||
1214 | /* Start TX with programmed I/O only (no DMA) */ | |
1215 | static void pl011_start_tx_pio(struct uart_amba_port *uap) | |
1216 | { | |
1217 | uap->im |= UART011_TXIM; | |
1218 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1219 | if (!uap->tx_irq_seen) | |
1220 | pl011_tx_chars(uap); | |
1221 | } | |
1222 | ||
b129a8cc | 1223 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 | 1224 | { |
a5820c24 DT |
1225 | struct uart_amba_port *uap = |
1226 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1227 | |
734745ca DM |
1228 | if (!pl011_dma_tx_start(uap)) |
1229 | pl011_start_tx_pio(uap); | |
1da177e4 LT |
1230 | } |
1231 | ||
1232 | static void pl011_stop_rx(struct uart_port *port) | |
1233 | { | |
a5820c24 DT |
1234 | struct uart_amba_port *uap = |
1235 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1236 | |
1237 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
1238 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
1239 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
ead76f32 LW |
1240 | |
1241 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1242 | } |
1243 | ||
1244 | static void pl011_enable_ms(struct uart_port *port) | |
1245 | { | |
a5820c24 DT |
1246 | struct uart_amba_port *uap = |
1247 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1248 | |
1249 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
1250 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1251 | } | |
1252 | ||
7d12e780 | 1253 | static void pl011_rx_chars(struct uart_amba_port *uap) |
b83286bf FE |
1254 | __releases(&uap->port.lock) |
1255 | __acquires(&uap->port.lock) | |
1da177e4 | 1256 | { |
29772c4e | 1257 | pl011_fifo_to_tty(uap); |
1da177e4 | 1258 | |
2389b272 | 1259 | spin_unlock(&uap->port.lock); |
2e124b4a | 1260 | tty_flip_buffer_push(&uap->port.state->port); |
ead76f32 LW |
1261 | /* |
1262 | * If we were temporarily out of DMA mode for a while, | |
1263 | * attempt to switch back to DMA mode again. | |
1264 | */ | |
1265 | if (pl011_dma_rx_available(uap)) { | |
1266 | if (pl011_dma_rx_trigger_dma(uap)) { | |
1267 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " | |
1268 | "fall back to interrupt mode again\n"); | |
1269 | uap->im |= UART011_RXIM; | |
30ae5859 | 1270 | writew(uap->im, uap->port.membase + UART011_IMSC); |
cb06ff10 | 1271 | } else { |
89fa28db | 1272 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1273 | /* Start Rx DMA poll */ |
1274 | if (uap->dmarx.poll_rate) { | |
1275 | uap->dmarx.last_jiffies = jiffies; | |
1276 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1277 | mod_timer(&uap->dmarx.timer, | |
1278 | jiffies + | |
1279 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1280 | } | |
89fa28db | 1281 | #endif |
cb06ff10 | 1282 | } |
ead76f32 | 1283 | } |
2389b272 | 1284 | spin_lock(&uap->port.lock); |
1da177e4 LT |
1285 | } |
1286 | ||
734745ca DM |
1287 | /* |
1288 | * Transmit a character | |
1289 | * There must be at least one free entry in the TX FIFO to accept the char. | |
1290 | * | |
1291 | * Returns true if the FIFO might have space in it afterwards; | |
1292 | * returns false if the FIFO definitely became full. | |
1293 | */ | |
1294 | static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c) | |
1295 | { | |
1296 | writew(c, uap->port.membase + UART01x_DR); | |
1297 | uap->port.icount.tx++; | |
1298 | ||
1299 | if (likely(uap->tx_irq_seen > 1)) | |
1300 | return true; | |
1301 | ||
1302 | return !(readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF); | |
1303 | } | |
1304 | ||
1305 | static bool pl011_tx_chars(struct uart_amba_port *uap) | |
1da177e4 | 1306 | { |
ebd2c8f6 | 1307 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
1308 | int count; |
1309 | ||
734745ca DM |
1310 | if (unlikely(uap->tx_irq_seen < 2)) |
1311 | /* | |
1312 | * Initial FIFO fill level unknown: we must check TXFF | |
1313 | * after each write, so just try to fill up the FIFO. | |
1314 | */ | |
1315 | count = uap->fifosize; | |
1316 | else /* tx_irq_seen >= 2 */ | |
1317 | /* | |
1318 | * FIFO initially at least half-empty, so we can simply | |
1319 | * write half the FIFO without polling TXFF. | |
1320 | ||
1321 | * Note: the *first* TX IRQ can still race with | |
1322 | * pl011_start_tx_pio(), which can result in the FIFO | |
1323 | * being fuller than expected in that case. | |
1324 | */ | |
1325 | count = uap->fifosize >> 1; | |
1326 | ||
1327 | /* | |
1328 | * If the FIFO is full we're guaranteed a TX IRQ at some later point, | |
1329 | * and can't transmit immediately in any case: | |
1330 | */ | |
1331 | if (unlikely(uap->tx_irq_seen < 2 && | |
1332 | readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)) | |
1333 | return false; | |
1334 | ||
1da177e4 | 1335 | if (uap->port.x_char) { |
734745ca | 1336 | pl011_tx_char(uap, uap->port.x_char); |
1da177e4 | 1337 | uap->port.x_char = 0; |
734745ca | 1338 | --count; |
1da177e4 LT |
1339 | } |
1340 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1341 | pl011_stop_tx(&uap->port); |
734745ca | 1342 | goto done; |
1da177e4 LT |
1343 | } |
1344 | ||
68b65f73 RK |
1345 | /* If we are using DMA mode, try to send some characters. */ |
1346 | if (pl011_dma_tx_irq(uap)) | |
734745ca | 1347 | goto done; |
68b65f73 | 1348 | |
734745ca | 1349 | while (count-- > 0 && pl011_tx_char(uap, xmit->buf[xmit->tail])) { |
1da177e4 | 1350 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1da177e4 LT |
1351 | if (uart_circ_empty(xmit)) |
1352 | break; | |
734745ca | 1353 | } |
1da177e4 LT |
1354 | |
1355 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1356 | uart_write_wakeup(&uap->port); | |
1357 | ||
734745ca | 1358 | if (uart_circ_empty(xmit)) { |
b129a8cc | 1359 | pl011_stop_tx(&uap->port); |
734745ca DM |
1360 | goto done; |
1361 | } | |
1362 | ||
1363 | if (unlikely(!uap->tx_irq_seen)) | |
1364 | schedule_delayed_work(&uap->tx_softirq_work, uap->port.timeout); | |
1365 | ||
1366 | done: | |
1367 | return false; | |
1da177e4 LT |
1368 | } |
1369 | ||
1370 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1371 | { | |
1372 | unsigned int status, delta; | |
1373 | ||
1374 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1375 | ||
1376 | delta = status ^ uap->old_status; | |
1377 | uap->old_status = status; | |
1378 | ||
1379 | if (!delta) | |
1380 | return; | |
1381 | ||
1382 | if (delta & UART01x_FR_DCD) | |
1383 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1384 | ||
1385 | if (delta & UART01x_FR_DSR) | |
1386 | uap->port.icount.dsr++; | |
1387 | ||
1388 | if (delta & UART01x_FR_CTS) | |
1389 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
1390 | ||
bdc04e31 | 1391 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1392 | } |
1393 | ||
734745ca DM |
1394 | static void pl011_tx_softirq(struct work_struct *work) |
1395 | { | |
1396 | struct delayed_work *dwork = to_delayed_work(work); | |
1397 | struct uart_amba_port *uap = | |
1398 | container_of(dwork, struct uart_amba_port, tx_softirq_work); | |
1399 | ||
1400 | spin_lock(&uap->port.lock); | |
1401 | while (pl011_tx_chars(uap)) ; | |
1402 | spin_unlock(&uap->port.lock); | |
1403 | } | |
1404 | ||
1405 | static void pl011_tx_irq_seen(struct uart_amba_port *uap) | |
1406 | { | |
1407 | if (likely(uap->tx_irq_seen > 1)) | |
1408 | return; | |
1409 | ||
1410 | uap->tx_irq_seen++; | |
1411 | if (uap->tx_irq_seen < 2) | |
1412 | /* first TX IRQ */ | |
1413 | cancel_delayed_work(&uap->tx_softirq_work); | |
1414 | } | |
1415 | ||
7d12e780 | 1416 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1417 | { |
1418 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1419 | unsigned long flags; |
1da177e4 LT |
1420 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
1421 | int handled = 0; | |
4fd0690b | 1422 | unsigned int dummy_read; |
1da177e4 | 1423 | |
963cc981 | 1424 | spin_lock_irqsave(&uap->port.lock, flags); |
1da177e4 LT |
1425 | status = readw(uap->port.membase + UART011_MIS); |
1426 | if (status) { | |
1427 | do { | |
4fd0690b R |
1428 | if (uap->vendor->cts_event_workaround) { |
1429 | /* workaround to make sure that all bits are unlocked.. */ | |
1430 | writew(0x00, uap->port.membase + UART011_ICR); | |
1431 | ||
1432 | /* | |
1433 | * WA: introduce 26ns(1 uart clk) delay before W1C; | |
1434 | * single apb access will incur 2 pclk(133.12Mhz) delay, | |
1435 | * so add 2 dummy reads | |
1436 | */ | |
1437 | dummy_read = readw(uap->port.membase + UART011_ICR); | |
1438 | dummy_read = readw(uap->port.membase + UART011_ICR); | |
1439 | } | |
1440 | ||
1da177e4 LT |
1441 | writew(status & ~(UART011_TXIS|UART011_RTIS| |
1442 | UART011_RXIS), | |
1443 | uap->port.membase + UART011_ICR); | |
1444 | ||
ead76f32 LW |
1445 | if (status & (UART011_RTIS|UART011_RXIS)) { |
1446 | if (pl011_dma_rx_running(uap)) | |
1447 | pl011_dma_rx_irq(uap); | |
1448 | else | |
1449 | pl011_rx_chars(uap); | |
1450 | } | |
1da177e4 LT |
1451 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1452 | UART011_CTSMIS|UART011_RIMIS)) | |
1453 | pl011_modem_status(uap); | |
734745ca DM |
1454 | if (status & UART011_TXIS) { |
1455 | pl011_tx_irq_seen(uap); | |
1da177e4 | 1456 | pl011_tx_chars(uap); |
734745ca | 1457 | } |
1da177e4 | 1458 | |
4fd0690b | 1459 | if (pass_counter-- == 0) |
1da177e4 LT |
1460 | break; |
1461 | ||
1462 | status = readw(uap->port.membase + UART011_MIS); | |
1463 | } while (status != 0); | |
1464 | handled = 1; | |
1465 | } | |
1466 | ||
963cc981 | 1467 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
1468 | |
1469 | return IRQ_RETVAL(handled); | |
1470 | } | |
1471 | ||
e643f87f | 1472 | static unsigned int pl011_tx_empty(struct uart_port *port) |
1da177e4 | 1473 | { |
a5820c24 DT |
1474 | struct uart_amba_port *uap = |
1475 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1476 | unsigned int status = readw(uap->port.membase + UART01x_FR); |
1477 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
1478 | } | |
1479 | ||
e643f87f | 1480 | static unsigned int pl011_get_mctrl(struct uart_port *port) |
1da177e4 | 1481 | { |
a5820c24 DT |
1482 | struct uart_amba_port *uap = |
1483 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1484 | unsigned int result = 0; |
1485 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1486 | ||
5159f407 | 1487 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
1488 | if (status & uartbit) \ |
1489 | result |= tiocmbit | |
1490 | ||
5159f407 JS |
1491 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
1492 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); | |
1493 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
1494 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
1495 | #undef TIOCMBIT | |
1da177e4 LT |
1496 | return result; |
1497 | } | |
1498 | ||
1499 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1500 | { | |
a5820c24 DT |
1501 | struct uart_amba_port *uap = |
1502 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1503 | unsigned int cr; |
1504 | ||
1505 | cr = readw(uap->port.membase + UART011_CR); | |
1506 | ||
5159f407 | 1507 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
1508 | if (mctrl & tiocmbit) \ |
1509 | cr |= uartbit; \ | |
1510 | else \ | |
1511 | cr &= ~uartbit | |
1512 | ||
5159f407 JS |
1513 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
1514 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
1515 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
1516 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
1517 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
1518 | |
1519 | if (uap->autorts) { | |
1520 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
1521 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
1522 | } | |
5159f407 | 1523 | #undef TIOCMBIT |
1da177e4 LT |
1524 | |
1525 | writew(cr, uap->port.membase + UART011_CR); | |
1526 | } | |
1527 | ||
1528 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1529 | { | |
a5820c24 DT |
1530 | struct uart_amba_port *uap = |
1531 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1532 | unsigned long flags; |
1533 | unsigned int lcr_h; | |
1534 | ||
1535 | spin_lock_irqsave(&uap->port.lock, flags); | |
ec489aa8 | 1536 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1537 | if (break_state == -1) |
1538 | lcr_h |= UART01x_LCRH_BRK; | |
1539 | else | |
1540 | lcr_h &= ~UART01x_LCRH_BRK; | |
ec489aa8 | 1541 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1542 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1543 | } | |
1544 | ||
84b5ae15 | 1545 | #ifdef CONFIG_CONSOLE_POLL |
5c8124a0 AV |
1546 | |
1547 | static void pl011_quiesce_irqs(struct uart_port *port) | |
1548 | { | |
a5820c24 DT |
1549 | struct uart_amba_port *uap = |
1550 | container_of(port, struct uart_amba_port, port); | |
5c8124a0 AV |
1551 | unsigned char __iomem *regs = uap->port.membase; |
1552 | ||
1553 | writew(readw(regs + UART011_MIS), regs + UART011_ICR); | |
1554 | /* | |
1555 | * There is no way to clear TXIM as this is "ready to transmit IRQ", so | |
1556 | * we simply mask it. start_tx() will unmask it. | |
1557 | * | |
1558 | * Note we can race with start_tx(), and if the race happens, the | |
1559 | * polling user might get another interrupt just after we clear it. | |
1560 | * But it should be OK and can happen even w/o the race, e.g. | |
1561 | * controller immediately got some new data and raised the IRQ. | |
1562 | * | |
1563 | * And whoever uses polling routines assumes that it manages the device | |
1564 | * (including tx queue), so we're also fine with start_tx()'s caller | |
1565 | * side. | |
1566 | */ | |
1567 | writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC); | |
1568 | } | |
1569 | ||
e643f87f | 1570 | static int pl011_get_poll_char(struct uart_port *port) |
84b5ae15 | 1571 | { |
a5820c24 DT |
1572 | struct uart_amba_port *uap = |
1573 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 JW |
1574 | unsigned int status; |
1575 | ||
5c8124a0 AV |
1576 | /* |
1577 | * The caller might need IRQs lowered, e.g. if used with KDB NMI | |
1578 | * debugger. | |
1579 | */ | |
1580 | pl011_quiesce_irqs(port); | |
1581 | ||
f5316b4a JW |
1582 | status = readw(uap->port.membase + UART01x_FR); |
1583 | if (status & UART01x_FR_RXFE) | |
1584 | return NO_POLL_CHAR; | |
84b5ae15 JW |
1585 | |
1586 | return readw(uap->port.membase + UART01x_DR); | |
1587 | } | |
1588 | ||
e643f87f | 1589 | static void pl011_put_poll_char(struct uart_port *port, |
84b5ae15 JW |
1590 | unsigned char ch) |
1591 | { | |
a5820c24 DT |
1592 | struct uart_amba_port *uap = |
1593 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 JW |
1594 | |
1595 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) | |
1596 | barrier(); | |
1597 | ||
1598 | writew(ch, uap->port.membase + UART01x_DR); | |
1599 | } | |
1600 | ||
1601 | #endif /* CONFIG_CONSOLE_POLL */ | |
1602 | ||
b3564c2c | 1603 | static int pl011_hwinit(struct uart_port *port) |
1da177e4 | 1604 | { |
a5820c24 DT |
1605 | struct uart_amba_port *uap = |
1606 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1607 | int retval; |
1608 | ||
78d80c5a | 1609 | /* Optionaly enable pins to be muxed in and configured */ |
2b996fc5 | 1610 | pinctrl_pm_select_default_state(port->dev); |
78d80c5a | 1611 | |
1da177e4 LT |
1612 | /* |
1613 | * Try to enable the clock producer. | |
1614 | */ | |
1c4c4394 | 1615 | retval = clk_prepare_enable(uap->clk); |
1da177e4 | 1616 | if (retval) |
7f6d942a | 1617 | return retval; |
1da177e4 LT |
1618 | |
1619 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1620 | ||
9b96fbac LW |
1621 | /* Clear pending error and receive interrupts */ |
1622 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS | | |
1623 | UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR); | |
1624 | ||
b3564c2c AV |
1625 | /* |
1626 | * Save interrupts enable mask, and enable RX interrupts in case if | |
1627 | * the interrupt is used for NMI entry. | |
1628 | */ | |
1629 | uap->im = readw(uap->port.membase + UART011_IMSC); | |
1630 | writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC); | |
1631 | ||
574de559 | 1632 | if (dev_get_platdata(uap->port.dev)) { |
b3564c2c AV |
1633 | struct amba_pl011_data *plat; |
1634 | ||
574de559 | 1635 | plat = dev_get_platdata(uap->port.dev); |
b3564c2c AV |
1636 | if (plat->init) |
1637 | plat->init(); | |
1638 | } | |
1639 | return 0; | |
b3564c2c AV |
1640 | } |
1641 | ||
b60f2f66 JM |
1642 | static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) |
1643 | { | |
1644 | writew(lcr_h, uap->port.membase + uap->lcrh_rx); | |
1645 | if (uap->lcrh_rx != uap->lcrh_tx) { | |
1646 | int i; | |
1647 | /* | |
1648 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1649 | * to get this delay write read only register 10 times | |
1650 | */ | |
1651 | for (i = 0; i < 10; ++i) | |
1652 | writew(0xff, uap->port.membase + UART011_MIS); | |
1653 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); | |
1654 | } | |
1655 | } | |
1656 | ||
b3564c2c AV |
1657 | static int pl011_startup(struct uart_port *port) |
1658 | { | |
a5820c24 DT |
1659 | struct uart_amba_port *uap = |
1660 | container_of(port, struct uart_amba_port, port); | |
734745ca | 1661 | unsigned int cr; |
b3564c2c AV |
1662 | int retval; |
1663 | ||
1664 | retval = pl011_hwinit(port); | |
1665 | if (retval) | |
1666 | goto clk_dis; | |
1667 | ||
1668 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1669 | ||
1da177e4 LT |
1670 | /* |
1671 | * Allocate the IRQ | |
1672 | */ | |
1673 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
1674 | if (retval) | |
1675 | goto clk_dis; | |
1676 | ||
c19f12b5 | 1677 | writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); |
1da177e4 | 1678 | |
734745ca | 1679 | spin_lock_irq(&uap->port.lock); |
570d2910 | 1680 | |
d8d8ffa4 SKS |
1681 | /* restore RTS and DTR */ |
1682 | cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); | |
1683 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
1da177e4 LT |
1684 | writew(cr, uap->port.membase + UART011_CR); |
1685 | ||
fe433907 JM |
1686 | spin_unlock_irq(&uap->port.lock); |
1687 | ||
1da177e4 LT |
1688 | /* |
1689 | * initialise the old status of the modem signals | |
1690 | */ | |
1691 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1692 | ||
68b65f73 RK |
1693 | /* Startup DMA */ |
1694 | pl011_dma_startup(uap); | |
1695 | ||
1da177e4 | 1696 | /* |
ead76f32 LW |
1697 | * Finally, enable interrupts, only timeouts when using DMA |
1698 | * if initial RX DMA job failed, start in interrupt mode | |
1699 | * as well. | |
1da177e4 LT |
1700 | */ |
1701 | spin_lock_irq(&uap->port.lock); | |
9b96fbac LW |
1702 | /* Clear out any spuriously appearing RX interrupts */ |
1703 | writew(UART011_RTIS | UART011_RXIS, | |
1704 | uap->port.membase + UART011_ICR); | |
ead76f32 LW |
1705 | uap->im = UART011_RTIM; |
1706 | if (!pl011_dma_rx_running(uap)) | |
1707 | uap->im |= UART011_RXIM; | |
1da177e4 LT |
1708 | writew(uap->im, uap->port.membase + UART011_IMSC); |
1709 | spin_unlock_irq(&uap->port.lock); | |
1710 | ||
1711 | return 0; | |
1712 | ||
1713 | clk_dis: | |
1c4c4394 | 1714 | clk_disable_unprepare(uap->clk); |
1da177e4 LT |
1715 | return retval; |
1716 | } | |
1717 | ||
ec489aa8 LW |
1718 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
1719 | unsigned int lcrh) | |
1720 | { | |
1721 | unsigned long val; | |
1722 | ||
1723 | val = readw(uap->port.membase + lcrh); | |
1724 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
1725 | writew(val, uap->port.membase + lcrh); | |
1726 | } | |
1727 | ||
1da177e4 LT |
1728 | static void pl011_shutdown(struct uart_port *port) |
1729 | { | |
a5820c24 DT |
1730 | struct uart_amba_port *uap = |
1731 | container_of(port, struct uart_amba_port, port); | |
d8d8ffa4 | 1732 | unsigned int cr; |
1da177e4 | 1733 | |
734745ca DM |
1734 | cancel_delayed_work_sync(&uap->tx_softirq_work); |
1735 | ||
1da177e4 LT |
1736 | /* |
1737 | * disable all interrupts | |
1738 | */ | |
1739 | spin_lock_irq(&uap->port.lock); | |
1740 | uap->im = 0; | |
1741 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
f2ee6dfa | 1742 | writew(0xffff & ~UART011_TXIS, uap->port.membase + UART011_ICR); |
1da177e4 LT |
1743 | spin_unlock_irq(&uap->port.lock); |
1744 | ||
68b65f73 RK |
1745 | pl011_dma_shutdown(uap); |
1746 | ||
1da177e4 LT |
1747 | /* |
1748 | * Free the interrupt | |
1749 | */ | |
1750 | free_irq(uap->port.irq, uap); | |
1751 | ||
1752 | /* | |
1753 | * disable the port | |
d8d8ffa4 SKS |
1754 | * disable the port. It should not disable RTS and DTR. |
1755 | * Also RTS and DTR state should be preserved to restore | |
1756 | * it during startup(). | |
1da177e4 | 1757 | */ |
3b43816f | 1758 | uap->autorts = false; |
fe433907 | 1759 | spin_lock_irq(&uap->port.lock); |
d8d8ffa4 SKS |
1760 | cr = readw(uap->port.membase + UART011_CR); |
1761 | uap->old_cr = cr; | |
1762 | cr &= UART011_CR_RTS | UART011_CR_DTR; | |
1763 | cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1764 | writew(cr, uap->port.membase + UART011_CR); | |
fe433907 | 1765 | spin_unlock_irq(&uap->port.lock); |
1da177e4 LT |
1766 | |
1767 | /* | |
1768 | * disable break condition and fifos | |
1769 | */ | |
ec489aa8 LW |
1770 | pl011_shutdown_channel(uap, uap->lcrh_rx); |
1771 | if (uap->lcrh_rx != uap->lcrh_tx) | |
1772 | pl011_shutdown_channel(uap, uap->lcrh_tx); | |
1da177e4 LT |
1773 | |
1774 | /* | |
1775 | * Shut down the clock producer | |
1776 | */ | |
1c4c4394 | 1777 | clk_disable_unprepare(uap->clk); |
78d80c5a | 1778 | /* Optionally let pins go into sleep states */ |
2b996fc5 | 1779 | pinctrl_pm_select_sleep_state(port->dev); |
c16d51a3 | 1780 | |
574de559 | 1781 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
1782 | struct amba_pl011_data *plat; |
1783 | ||
574de559 | 1784 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
1785 | if (plat->exit) |
1786 | plat->exit(); | |
1787 | } | |
1788 | ||
36f339d1 PH |
1789 | if (uap->port.ops->flush_buffer) |
1790 | uap->port.ops->flush_buffer(port); | |
1da177e4 LT |
1791 | } |
1792 | ||
1793 | static void | |
606d099c AC |
1794 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1795 | struct ktermios *old) | |
1da177e4 | 1796 | { |
a5820c24 DT |
1797 | struct uart_amba_port *uap = |
1798 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1799 | unsigned int lcr_h, old_cr; |
1800 | unsigned long flags; | |
c19f12b5 RK |
1801 | unsigned int baud, quot, clkdiv; |
1802 | ||
1803 | if (uap->vendor->oversampling) | |
1804 | clkdiv = 8; | |
1805 | else | |
1806 | clkdiv = 16; | |
1da177e4 LT |
1807 | |
1808 | /* | |
1809 | * Ask the core to calculate the divisor for us. | |
1810 | */ | |
ac3e3fb4 | 1811 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1812 | port->uartclk / clkdiv); |
89fa28db | 1813 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1814 | /* |
1815 | * Adjust RX DMA polling rate with baud rate if not specified. | |
1816 | */ | |
1817 | if (uap->dmarx.auto_poll_rate) | |
1818 | uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); | |
89fa28db | 1819 | #endif |
ac3e3fb4 LW |
1820 | |
1821 | if (baud > port->uartclk/16) | |
1822 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1823 | else | |
1824 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1825 | |
1826 | switch (termios->c_cflag & CSIZE) { | |
1827 | case CS5: | |
1828 | lcr_h = UART01x_LCRH_WLEN_5; | |
1829 | break; | |
1830 | case CS6: | |
1831 | lcr_h = UART01x_LCRH_WLEN_6; | |
1832 | break; | |
1833 | case CS7: | |
1834 | lcr_h = UART01x_LCRH_WLEN_7; | |
1835 | break; | |
1836 | default: // CS8 | |
1837 | lcr_h = UART01x_LCRH_WLEN_8; | |
1838 | break; | |
1839 | } | |
1840 | if (termios->c_cflag & CSTOPB) | |
1841 | lcr_h |= UART01x_LCRH_STP2; | |
1842 | if (termios->c_cflag & PARENB) { | |
1843 | lcr_h |= UART01x_LCRH_PEN; | |
1844 | if (!(termios->c_cflag & PARODD)) | |
1845 | lcr_h |= UART01x_LCRH_EPS; | |
1846 | } | |
ffca2b11 | 1847 | if (uap->fifosize > 1) |
1da177e4 LT |
1848 | lcr_h |= UART01x_LCRH_FEN; |
1849 | ||
1850 | spin_lock_irqsave(&port->lock, flags); | |
1851 | ||
1852 | /* | |
1853 | * Update the per-port timeout. | |
1854 | */ | |
1855 | uart_update_timeout(port, termios->c_cflag, baud); | |
1856 | ||
b63d4f0f | 1857 | port->read_status_mask = UART011_DR_OE | 255; |
1da177e4 | 1858 | if (termios->c_iflag & INPCK) |
b63d4f0f | 1859 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
ef8b9ddc | 1860 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
b63d4f0f | 1861 | port->read_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1862 | |
1863 | /* | |
1864 | * Characters to ignore | |
1865 | */ | |
1866 | port->ignore_status_mask = 0; | |
1867 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1868 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1869 | if (termios->c_iflag & IGNBRK) { |
b63d4f0f | 1870 | port->ignore_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1871 | /* |
1872 | * If we're ignoring parity and break indicators, | |
1873 | * ignore overruns too (for real raw support). | |
1874 | */ | |
1875 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1876 | port->ignore_status_mask |= UART011_DR_OE; |
1da177e4 LT |
1877 | } |
1878 | ||
1879 | /* | |
1880 | * Ignore all characters if CREAD is not set. | |
1881 | */ | |
1882 | if ((termios->c_cflag & CREAD) == 0) | |
b63d4f0f | 1883 | port->ignore_status_mask |= UART_DUMMY_DR_RX; |
1da177e4 LT |
1884 | |
1885 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1886 | pl011_enable_ms(port); | |
1887 | ||
1888 | /* first, disable everything */ | |
1889 | old_cr = readw(port->membase + UART011_CR); | |
1890 | writew(0, port->membase + UART011_CR); | |
1891 | ||
3b43816f RV |
1892 | if (termios->c_cflag & CRTSCTS) { |
1893 | if (old_cr & UART011_CR_RTS) | |
1894 | old_cr |= UART011_CR_RTSEN; | |
1895 | ||
1896 | old_cr |= UART011_CR_CTSEN; | |
1897 | uap->autorts = true; | |
1898 | } else { | |
1899 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1900 | uap->autorts = false; | |
1901 | } | |
1902 | ||
c19f12b5 RK |
1903 | if (uap->vendor->oversampling) { |
1904 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1905 | old_cr |= ST_UART011_CR_OVSFACT; |
1906 | else | |
1907 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1908 | } | |
1909 | ||
c5dd553b LW |
1910 | /* |
1911 | * Workaround for the ST Micro oversampling variants to | |
1912 | * increase the bitrate slightly, by lowering the divisor, | |
1913 | * to avoid delayed sampling of start bit at high speeds, | |
1914 | * else we see data corruption. | |
1915 | */ | |
1916 | if (uap->vendor->oversampling) { | |
1917 | if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) | |
1918 | quot -= 1; | |
1919 | else if ((baud > 3250000) && (quot > 2)) | |
1920 | quot -= 2; | |
1921 | } | |
1da177e4 LT |
1922 | /* Set baud rate */ |
1923 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
1924 | writew(quot >> 6, port->membase + UART011_IBRD); | |
1925 | ||
1926 | /* | |
1927 | * ----------v----------v----------v----------v----- | |
c5dd553b LW |
1928 | * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER |
1929 | * UART011_FBRD & UART011_IBRD. | |
1da177e4 LT |
1930 | * ----------^----------^----------^----------^----- |
1931 | */ | |
b60f2f66 | 1932 | pl011_write_lcr_h(uap, lcr_h); |
1da177e4 LT |
1933 | writew(old_cr, port->membase + UART011_CR); |
1934 | ||
1935 | spin_unlock_irqrestore(&port->lock, flags); | |
1936 | } | |
1937 | ||
1938 | static const char *pl011_type(struct uart_port *port) | |
1939 | { | |
a5820c24 DT |
1940 | struct uart_amba_port *uap = |
1941 | container_of(port, struct uart_amba_port, port); | |
e8a7ba86 | 1942 | return uap->port.type == PORT_AMBA ? uap->type : NULL; |
1da177e4 LT |
1943 | } |
1944 | ||
1945 | /* | |
1946 | * Release the memory region(s) being used by 'port' | |
1947 | */ | |
e643f87f | 1948 | static void pl011_release_port(struct uart_port *port) |
1da177e4 LT |
1949 | { |
1950 | release_mem_region(port->mapbase, SZ_4K); | |
1951 | } | |
1952 | ||
1953 | /* | |
1954 | * Request the memory region(s) being used by 'port' | |
1955 | */ | |
e643f87f | 1956 | static int pl011_request_port(struct uart_port *port) |
1da177e4 LT |
1957 | { |
1958 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
1959 | != NULL ? 0 : -EBUSY; | |
1960 | } | |
1961 | ||
1962 | /* | |
1963 | * Configure/autoconfigure the port. | |
1964 | */ | |
e643f87f | 1965 | static void pl011_config_port(struct uart_port *port, int flags) |
1da177e4 LT |
1966 | { |
1967 | if (flags & UART_CONFIG_TYPE) { | |
1968 | port->type = PORT_AMBA; | |
e643f87f | 1969 | pl011_request_port(port); |
1da177e4 LT |
1970 | } |
1971 | } | |
1972 | ||
1973 | /* | |
1974 | * verify the new serial_struct (for TIOCSSERIAL). | |
1975 | */ | |
e643f87f | 1976 | static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) |
1da177e4 LT |
1977 | { |
1978 | int ret = 0; | |
1979 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
1980 | ret = -EINVAL; | |
a62c4133 | 1981 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
1982 | ret = -EINVAL; |
1983 | if (ser->baud_base < 9600) | |
1984 | ret = -EINVAL; | |
1985 | return ret; | |
1986 | } | |
1987 | ||
1988 | static struct uart_ops amba_pl011_pops = { | |
e643f87f | 1989 | .tx_empty = pl011_tx_empty, |
1da177e4 | 1990 | .set_mctrl = pl011_set_mctrl, |
e643f87f | 1991 | .get_mctrl = pl011_get_mctrl, |
1da177e4 LT |
1992 | .stop_tx = pl011_stop_tx, |
1993 | .start_tx = pl011_start_tx, | |
1994 | .stop_rx = pl011_stop_rx, | |
1995 | .enable_ms = pl011_enable_ms, | |
1996 | .break_ctl = pl011_break_ctl, | |
1997 | .startup = pl011_startup, | |
1998 | .shutdown = pl011_shutdown, | |
68b65f73 | 1999 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
2000 | .set_termios = pl011_set_termios, |
2001 | .type = pl011_type, | |
e643f87f LW |
2002 | .release_port = pl011_release_port, |
2003 | .request_port = pl011_request_port, | |
2004 | .config_port = pl011_config_port, | |
2005 | .verify_port = pl011_verify_port, | |
84b5ae15 | 2006 | #ifdef CONFIG_CONSOLE_POLL |
b3564c2c | 2007 | .poll_init = pl011_hwinit, |
e643f87f LW |
2008 | .poll_get_char = pl011_get_poll_char, |
2009 | .poll_put_char = pl011_put_poll_char, | |
84b5ae15 | 2010 | #endif |
1da177e4 LT |
2011 | }; |
2012 | ||
2013 | static struct uart_amba_port *amba_ports[UART_NR]; | |
2014 | ||
2015 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
2016 | ||
d358788f | 2017 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 2018 | { |
a5820c24 DT |
2019 | struct uart_amba_port *uap = |
2020 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 2021 | |
d358788f RK |
2022 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
2023 | barrier(); | |
1da177e4 LT |
2024 | writew(ch, uap->port.membase + UART01x_DR); |
2025 | } | |
2026 | ||
2027 | static void | |
2028 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
2029 | { | |
2030 | struct uart_amba_port *uap = amba_ports[co->index]; | |
2031 | unsigned int status, old_cr, new_cr; | |
ef605fdb RV |
2032 | unsigned long flags; |
2033 | int locked = 1; | |
1da177e4 LT |
2034 | |
2035 | clk_enable(uap->clk); | |
2036 | ||
ef605fdb RV |
2037 | local_irq_save(flags); |
2038 | if (uap->port.sysrq) | |
2039 | locked = 0; | |
2040 | else if (oops_in_progress) | |
2041 | locked = spin_trylock(&uap->port.lock); | |
2042 | else | |
2043 | spin_lock(&uap->port.lock); | |
2044 | ||
1da177e4 LT |
2045 | /* |
2046 | * First save the CR then disable the interrupts | |
2047 | */ | |
2048 | old_cr = readw(uap->port.membase + UART011_CR); | |
2049 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
2050 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
2051 | writew(new_cr, uap->port.membase + UART011_CR); | |
2052 | ||
d358788f | 2053 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
2054 | |
2055 | /* | |
2056 | * Finally, wait for transmitter to become empty | |
2057 | * and restore the TCR | |
2058 | */ | |
2059 | do { | |
2060 | status = readw(uap->port.membase + UART01x_FR); | |
2061 | } while (status & UART01x_FR_BUSY); | |
2062 | writew(old_cr, uap->port.membase + UART011_CR); | |
2063 | ||
ef605fdb RV |
2064 | if (locked) |
2065 | spin_unlock(&uap->port.lock); | |
2066 | local_irq_restore(flags); | |
2067 | ||
1da177e4 LT |
2068 | clk_disable(uap->clk); |
2069 | } | |
2070 | ||
2071 | static void __init | |
2072 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
2073 | int *parity, int *bits) | |
2074 | { | |
2075 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
2076 | unsigned int lcr_h, ibrd, fbrd; | |
2077 | ||
ec489aa8 | 2078 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
2079 | |
2080 | *parity = 'n'; | |
2081 | if (lcr_h & UART01x_LCRH_PEN) { | |
2082 | if (lcr_h & UART01x_LCRH_EPS) | |
2083 | *parity = 'e'; | |
2084 | else | |
2085 | *parity = 'o'; | |
2086 | } | |
2087 | ||
2088 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
2089 | *bits = 7; | |
2090 | else | |
2091 | *bits = 8; | |
2092 | ||
2093 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
2094 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
2095 | ||
2096 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 2097 | |
c19f12b5 | 2098 | if (uap->vendor->oversampling) { |
ac3e3fb4 LW |
2099 | if (readw(uap->port.membase + UART011_CR) |
2100 | & ST_UART011_CR_OVSFACT) | |
2101 | *baud *= 2; | |
2102 | } | |
1da177e4 LT |
2103 | } |
2104 | } | |
2105 | ||
2106 | static int __init pl011_console_setup(struct console *co, char *options) | |
2107 | { | |
2108 | struct uart_amba_port *uap; | |
2109 | int baud = 38400; | |
2110 | int bits = 8; | |
2111 | int parity = 'n'; | |
2112 | int flow = 'n'; | |
4b4851c6 | 2113 | int ret; |
1da177e4 LT |
2114 | |
2115 | /* | |
2116 | * Check whether an invalid uart number has been specified, and | |
2117 | * if so, search for the first available port that does have | |
2118 | * console support. | |
2119 | */ | |
2120 | if (co->index >= UART_NR) | |
2121 | co->index = 0; | |
2122 | uap = amba_ports[co->index]; | |
d28122a5 RK |
2123 | if (!uap) |
2124 | return -ENODEV; | |
1da177e4 | 2125 | |
78d80c5a | 2126 | /* Allow pins to be muxed in and configured */ |
2b996fc5 | 2127 | pinctrl_pm_select_default_state(uap->port.dev); |
78d80c5a | 2128 | |
4b4851c6 RK |
2129 | ret = clk_prepare(uap->clk); |
2130 | if (ret) | |
2131 | return ret; | |
2132 | ||
574de559 | 2133 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
2134 | struct amba_pl011_data *plat; |
2135 | ||
574de559 | 2136 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
2137 | if (plat->init) |
2138 | plat->init(); | |
2139 | } | |
2140 | ||
1da177e4 LT |
2141 | uap->port.uartclk = clk_get_rate(uap->clk); |
2142 | ||
2143 | if (options) | |
2144 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2145 | else | |
2146 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
2147 | ||
2148 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
2149 | } | |
2150 | ||
2d93486c | 2151 | static struct uart_driver amba_reg; |
1da177e4 LT |
2152 | static struct console amba_console = { |
2153 | .name = "ttyAMA", | |
2154 | .write = pl011_console_write, | |
2155 | .device = uart_console_device, | |
2156 | .setup = pl011_console_setup, | |
2157 | .flags = CON_PRINTBUFFER, | |
2158 | .index = -1, | |
2159 | .data = &amba_reg, | |
2160 | }; | |
2161 | ||
2162 | #define AMBA_CONSOLE (&amba_console) | |
0d3c673e RH |
2163 | |
2164 | static void pl011_putc(struct uart_port *port, int c) | |
2165 | { | |
2166 | while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) | |
2167 | ; | |
2168 | writeb(c, port->membase + UART01x_DR); | |
2169 | while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) | |
2170 | ; | |
2171 | } | |
2172 | ||
2173 | static void pl011_early_write(struct console *con, const char *s, unsigned n) | |
2174 | { | |
2175 | struct earlycon_device *dev = con->data; | |
2176 | ||
2177 | uart_console_write(&dev->port, s, n, pl011_putc); | |
2178 | } | |
2179 | ||
2180 | static int __init pl011_early_console_setup(struct earlycon_device *device, | |
2181 | const char *opt) | |
2182 | { | |
2183 | if (!device->port.membase) | |
2184 | return -ENODEV; | |
2185 | ||
2186 | device->con->write = pl011_early_write; | |
2187 | return 0; | |
2188 | } | |
2189 | EARLYCON_DECLARE(pl011, pl011_early_console_setup); | |
45e0f0f5 | 2190 | OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); |
0d3c673e | 2191 | |
1da177e4 LT |
2192 | #else |
2193 | #define AMBA_CONSOLE NULL | |
2194 | #endif | |
2195 | ||
2196 | static struct uart_driver amba_reg = { | |
2197 | .owner = THIS_MODULE, | |
2198 | .driver_name = "ttyAMA", | |
2199 | .dev_name = "ttyAMA", | |
2200 | .major = SERIAL_AMBA_MAJOR, | |
2201 | .minor = SERIAL_AMBA_MINOR, | |
2202 | .nr = UART_NR, | |
2203 | .cons = AMBA_CONSOLE, | |
2204 | }; | |
2205 | ||
32614aad ML |
2206 | static int pl011_probe_dt_alias(int index, struct device *dev) |
2207 | { | |
2208 | struct device_node *np; | |
2209 | static bool seen_dev_with_alias = false; | |
2210 | static bool seen_dev_without_alias = false; | |
2211 | int ret = index; | |
2212 | ||
2213 | if (!IS_ENABLED(CONFIG_OF)) | |
2214 | return ret; | |
2215 | ||
2216 | np = dev->of_node; | |
2217 | if (!np) | |
2218 | return ret; | |
2219 | ||
2220 | ret = of_alias_get_id(np, "serial"); | |
2221 | if (IS_ERR_VALUE(ret)) { | |
2222 | seen_dev_without_alias = true; | |
2223 | ret = index; | |
2224 | } else { | |
2225 | seen_dev_with_alias = true; | |
2226 | if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { | |
2227 | dev_warn(dev, "requested serial port %d not available.\n", ret); | |
2228 | ret = index; | |
2229 | } | |
2230 | } | |
2231 | ||
2232 | if (seen_dev_with_alias && seen_dev_without_alias) | |
2233 | dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); | |
2234 | ||
2235 | return ret; | |
2236 | } | |
2237 | ||
aa25afad | 2238 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
1da177e4 LT |
2239 | { |
2240 | struct uart_amba_port *uap; | |
5926a295 | 2241 | struct vendor_data *vendor = id->data; |
1da177e4 LT |
2242 | void __iomem *base; |
2243 | int i, ret; | |
2244 | ||
2245 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
2246 | if (amba_ports[i] == NULL) | |
2247 | break; | |
2248 | ||
7f6d942a TB |
2249 | if (i == ARRAY_SIZE(amba_ports)) |
2250 | return -EBUSY; | |
1da177e4 | 2251 | |
de609582 LW |
2252 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), |
2253 | GFP_KERNEL); | |
7f6d942a TB |
2254 | if (uap == NULL) |
2255 | return -ENOMEM; | |
1da177e4 | 2256 | |
32614aad ML |
2257 | i = pl011_probe_dt_alias(i, &dev->dev); |
2258 | ||
de609582 LW |
2259 | base = devm_ioremap(&dev->dev, dev->res.start, |
2260 | resource_size(&dev->res)); | |
7f6d942a TB |
2261 | if (!base) |
2262 | return -ENOMEM; | |
1da177e4 | 2263 | |
de609582 | 2264 | uap->clk = devm_clk_get(&dev->dev, NULL); |
7f6d942a TB |
2265 | if (IS_ERR(uap->clk)) |
2266 | return PTR_ERR(uap->clk); | |
1da177e4 | 2267 | |
c19f12b5 | 2268 | uap->vendor = vendor; |
ec489aa8 LW |
2269 | uap->lcrh_rx = vendor->lcrh_rx; |
2270 | uap->lcrh_tx = vendor->lcrh_tx; | |
d8d8ffa4 | 2271 | uap->old_cr = 0; |
ea33640a | 2272 | uap->fifosize = vendor->get_fifosize(dev); |
1da177e4 LT |
2273 | uap->port.dev = &dev->dev; |
2274 | uap->port.mapbase = dev->res.start; | |
2275 | uap->port.membase = base; | |
2276 | uap->port.iotype = UPIO_MEM; | |
2277 | uap->port.irq = dev->irq[0]; | |
ffca2b11 | 2278 | uap->port.fifosize = uap->fifosize; |
1da177e4 LT |
2279 | uap->port.ops = &amba_pl011_pops; |
2280 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
2281 | uap->port.line = i; | |
734745ca | 2282 | INIT_DELAYED_WORK(&uap->tx_softirq_work, pl011_tx_softirq); |
787b0c1f | 2283 | pl011_dma_probe(&dev->dev, uap); |
1da177e4 | 2284 | |
c3d8b76f LW |
2285 | /* Ensure interrupts from this UART are masked and cleared */ |
2286 | writew(0, uap->port.membase + UART011_IMSC); | |
2287 | writew(0xffff, uap->port.membase + UART011_ICR); | |
2288 | ||
e8a7ba86 RK |
2289 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); |
2290 | ||
1da177e4 LT |
2291 | amba_ports[i] = uap; |
2292 | ||
2293 | amba_set_drvdata(dev, uap); | |
ef2889f7 TB |
2294 | |
2295 | if (!amba_reg.state) { | |
2296 | ret = uart_register_driver(&amba_reg); | |
2297 | if (ret < 0) { | |
2298 | pr_err("Failed to register AMBA-PL011 driver\n"); | |
2299 | return ret; | |
2300 | } | |
2301 | } | |
2302 | ||
1da177e4 LT |
2303 | ret = uart_add_one_port(&amba_reg, &uap->port); |
2304 | if (ret) { | |
1da177e4 | 2305 | amba_ports[i] = NULL; |
ef2889f7 | 2306 | uart_unregister_driver(&amba_reg); |
68b65f73 | 2307 | pl011_dma_remove(uap); |
1da177e4 | 2308 | } |
7f6d942a | 2309 | |
1da177e4 LT |
2310 | return ret; |
2311 | } | |
2312 | ||
2313 | static int pl011_remove(struct amba_device *dev) | |
2314 | { | |
2315 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1e7da053 | 2316 | bool busy = false; |
1da177e4 LT |
2317 | int i; |
2318 | ||
1da177e4 LT |
2319 | uart_remove_one_port(&amba_reg, &uap->port); |
2320 | ||
2321 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
2322 | if (amba_ports[i] == uap) | |
2323 | amba_ports[i] = NULL; | |
1e7da053 GL |
2324 | else if (amba_ports[i]) |
2325 | busy = true; | |
1da177e4 | 2326 | |
68b65f73 | 2327 | pl011_dma_remove(uap); |
1e7da053 GL |
2328 | if (!busy) |
2329 | uart_unregister_driver(&amba_reg); | |
1da177e4 LT |
2330 | return 0; |
2331 | } | |
2332 | ||
d0ce850d UH |
2333 | #ifdef CONFIG_PM_SLEEP |
2334 | static int pl011_suspend(struct device *dev) | |
b736b89f | 2335 | { |
d0ce850d | 2336 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2337 | |
2338 | if (!uap) | |
2339 | return -EINVAL; | |
2340 | ||
2341 | return uart_suspend_port(&amba_reg, &uap->port); | |
2342 | } | |
2343 | ||
d0ce850d | 2344 | static int pl011_resume(struct device *dev) |
b736b89f | 2345 | { |
d0ce850d | 2346 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2347 | |
2348 | if (!uap) | |
2349 | return -EINVAL; | |
2350 | ||
2351 | return uart_resume_port(&amba_reg, &uap->port); | |
2352 | } | |
2353 | #endif | |
2354 | ||
d0ce850d UH |
2355 | static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); |
2356 | ||
2c39c9e1 | 2357 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
2358 | { |
2359 | .id = 0x00041011, | |
2360 | .mask = 0x000fffff, | |
5926a295 AR |
2361 | .data = &vendor_arm, |
2362 | }, | |
2363 | { | |
2364 | .id = 0x00380802, | |
2365 | .mask = 0x00ffffff, | |
2366 | .data = &vendor_st, | |
1da177e4 LT |
2367 | }, |
2368 | { 0, 0 }, | |
2369 | }; | |
2370 | ||
60f7a33b DM |
2371 | MODULE_DEVICE_TABLE(amba, pl011_ids); |
2372 | ||
1da177e4 LT |
2373 | static struct amba_driver pl011_driver = { |
2374 | .drv = { | |
2375 | .name = "uart-pl011", | |
d0ce850d | 2376 | .pm = &pl011_dev_pm_ops, |
1da177e4 LT |
2377 | }, |
2378 | .id_table = pl011_ids, | |
2379 | .probe = pl011_probe, | |
2380 | .remove = pl011_remove, | |
2381 | }; | |
2382 | ||
2383 | static int __init pl011_init(void) | |
2384 | { | |
1da177e4 LT |
2385 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); |
2386 | ||
ef2889f7 | 2387 | return amba_driver_register(&pl011_driver); |
1da177e4 LT |
2388 | } |
2389 | ||
2390 | static void __exit pl011_exit(void) | |
2391 | { | |
2392 | amba_driver_unregister(&pl011_driver); | |
1da177e4 LT |
2393 | } |
2394 | ||
4dd9e742 AR |
2395 | /* |
2396 | * While this can be a module, if builtin it's most likely the console | |
2397 | * So let's leave module_exit but move module_init to an earlier place | |
2398 | */ | |
2399 | arch_initcall(pl011_init); | |
1da177e4 LT |
2400 | module_exit(pl011_exit); |
2401 | ||
2402 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
2403 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
2404 | MODULE_LICENSE("GPL"); |