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[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / atmel_serial.c
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1e6c9c28 1/*
7192f92c 2 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV		 3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
a6670615
CC		 8 * DMA support added by Chip Coldwell.
9 *
1e6c9c28
AV		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
1e6c9c28
AV		 25#include <linux/tty.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
28#include <linux/init.h>
29#include <linux/serial.h>
afefc415 30#include <linux/clk.h>
1e6c9c28
AV		 31#include <linux/console.h>
32#include <linux/sysrq.h>
33#include <linux/tty_flip.h>
afefc415 34#include <linux/platform_device.h>
5fbe46b6
NF		 35#include <linux/of.h>
36#include <linux/of_device.h>
354e57f3 37#include <linux/of_gpio.h>
a6670615 38#include <linux/dma-mapping.h>
6b997bab 39#include <linux/dmaengine.h>
93a3ddc2 40#include <linux/atmel_pdc.h>
fa3218d8 41#include <linux/atmel_serial.h>
e8faff73 42#include <linux/uaccess.h>
bcd2360c 43#include <linux/platform_data/atmel.h>
2e68c22f 44#include <linux/timer.h>
354e57f3 45#include <linux/gpio.h>
e0b0baad
RG		 46#include <linux/gpio/consumer.h>
47#include <linux/err.h>
ab5e4e41 48#include <linux/irq.h>
2c7af5ba 49#include <linux/suspend.h>
1e6c9c28
AV		 50
51#include <asm/io.h>
f7512e7c 52#include <asm/ioctls.h>
1e6c9c28 53
a6670615
CC		 54#define PDC_BUFFER_SIZE 512
55/* Revisit: We should calculate this based on the actual port settings */
56#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
57
b5199d46
CP		 58/* The minium number of data FIFOs should be able to contain */
59#define ATMEL_MIN_FIFO_SIZE 8
60/*
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
63 */
64#define ATMEL_RTS_HIGH_OFFSET 16
65#define ATMEL_RTS_LOW_OFFSET 20
66
749c4e60 67#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV		 68#define SUPPORT_SYSRQ
69#endif
70
71#include <linux/serial_core.h>
72
e0b0baad
RG		 73#include "serial_mctrl_gpio.h"
74
e8faff73
CS		 75static void atmel_start_rx(struct uart_port *port);
76static void atmel_stop_rx(struct uart_port *port);
77
749c4e60 78#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 79
80/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
82 * UART. */
7192f92c 83#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 84#define MINOR_START 154
7192f92c 85#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 86
87#else
88
89/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
7192f92c 91#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 92#define MINOR_START 64
7192f92c 93#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 94
95#endif
96
7192f92c 97#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 98
a6670615
CC		 99struct atmel_dma_buffer {
100 unsigned char *buf;
101 dma_addr_t dma_addr;
102 unsigned int dma_size;
103 unsigned int ofs;
104};
105
1ecc26bd
RB		 106struct atmel_uart_char {
107 u16 status;
108 u16 ch;
109};
110
637ba54f
LD		 111/*
112 * Be careful, the real size of the ring buffer is
113 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
114 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
115 * DMA mode.
116 */
1ecc26bd
RB		 117#define ATMEL_SERIAL_RINGSIZE 1024
118
9af92fbf
AB		 119/*
120 * at91: 6 USARTs and one DBGU port (SAM9260)
121 * avr32: 4
122 */
123#define ATMEL_MAX_UART 7
124
afefc415
AV		 125/*
126 * We wrap our port structure around the generic uart_port.
127 */
7192f92c 128struct atmel_uart_port {
afefc415
AV		 129 struct uart_port uart; /* uart */
130 struct clk *clk; /* uart clock */
f05596db
AS		 131 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
132 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 133 int break_active; /* break being received */
1ecc26bd 134
34df42f5 135 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 136 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 137 short pdc_rx_idx; /* current PDC RX buffer */
138 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
139
08f738be 140 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 141 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 142 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
143
08f738be 144 spinlock_t lock_tx; /* port lock */
34df42f5 145 spinlock_t lock_rx; /* port lock */
08f738be 146 struct dma_chan *chan_tx;
34df42f5 147 struct dma_chan *chan_rx;
08f738be 148 struct dma_async_tx_descriptor *desc_tx;
34df42f5 149 struct dma_async_tx_descriptor *desc_rx;
08f738be 150 dma_cookie_t cookie_tx;
34df42f5 151 dma_cookie_t cookie_rx;
08f738be 152 struct scatterlist sg_tx;
34df42f5 153 struct scatterlist sg_rx;
00e8e658
NF		 154 struct tasklet_struct tasklet_rx;
155 struct tasklet_struct tasklet_tx;
98f2082c 156 atomic_t tasklet_shutdown;
1ecc26bd 157 unsigned int irq_status_prev;
5f258b3e 158 unsigned int tx_len;
1ecc26bd
RB		 159
160 struct circ_buf rx_ring;
e8faff73 161
e0b0baad 162 struct mctrl_gpios *gpios;
e8faff73 163 unsigned int tx_done_mask;
b5199d46
CP		 164 u32 fifo_size;
165 u32 rts_high;
166 u32 rts_low;
ab5e4e41 167 bool ms_irq_enabled;
2958ccee 168 u32 rtor; /* address of receiver timeout register if it exists */
5bf5635a 169 bool has_frac_baudrate;
4b769371
NF		 170 bool has_hw_timer;
171 struct timer_list uart_timer;
2c7af5ba
BB		 172
173 bool suspended;
174 unsigned int pending;
175 unsigned int pending_status;
176 spinlock_t lock_suspended;
177
6a5f0e2f
AB		 178 struct {
179 u32 cr;
180 u32 mr;
181 u32 imr;
182 u32 brgr;
183 u32 rtor;
184 u32 ttgr;
185 u32 fmr;
186 u32 fimr;
187 } cache;
188
a930e528
ES		 189 int (*prepare_rx)(struct uart_port *port);
190 int (*prepare_tx)(struct uart_port *port);
191 void (*schedule_rx)(struct uart_port *port);
192 void (*schedule_tx)(struct uart_port *port);
193 void (*release_rx)(struct uart_port *port);
194 void (*release_tx)(struct uart_port *port);
afefc415
AV		 195};
196
7192f92c 197static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 198static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 199
1e6c9c28 200#ifdef SUPPORT_SYSRQ
7192f92c 201static struct console atmel_console;
1e6c9c28
AV		 202#endif
203
5fbe46b6
NF		 204#if defined(CONFIG_OF)
205static const struct of_device_id atmel_serial_dt_ids[] = {
206 { .compatible = "atmel,at91rm9200-usart" },
207 { .compatible = "atmel,at91sam9260-usart" },
208 { /* sentinel */ }
209};
5fbe46b6
NF		 210#endif
211
c811ab8c
HS		 212static inline struct atmel_uart_port *
213to_atmel_uart_port(struct uart_port *uart)
214{
215 return container_of(uart, struct atmel_uart_port, uart);
216}
217
4e7decda
CP		 218static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
219{
220 return __raw_readl(port->membase + reg);
221}
222
223static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
224{
225 __raw_writel(value, port->membase + reg);
226}
227
a6499435
CP		 228#ifdef CONFIG_AVR32
229
230/* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
231static inline u8 atmel_uart_read_char(struct uart_port *port)
232{
233 return __raw_readl(port->membase + ATMEL_US_RHR);
234}
235
236static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
b5199d46 237{
a6499435 238 __raw_writel(value, port->membase + ATMEL_US_THR);
b5199d46
CP		 239}
240
a6499435
CP		 241#else
242
243static inline u8 atmel_uart_read_char(struct uart_port *port)
b5199d46 244{
a6499435 245 return __raw_readb(port->membase + ATMEL_US_RHR);
b5199d46
CP		 246}
247
a6499435
CP		 248static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
249{
250 __raw_writeb(value, port->membase + ATMEL_US_THR);
251}
252
253#endif
254
a6670615 255#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 256static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 257{
c811ab8c 258 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 259
64e22ebe 260 return atmel_port->use_pdc_rx;
a6670615
CC		 261}
262
64e22ebe 263static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 264{
c811ab8c 265 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 266
64e22ebe 267 return atmel_port->use_pdc_tx;
a6670615
CC		 268}
269#else
64e22ebe 270static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 271{
272 return false;
273}
274
64e22ebe 275static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 276{
277 return false;
278}
279#endif
280
08f738be
ES		 281static bool atmel_use_dma_tx(struct uart_port *port)
282{
283 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
284
285 return atmel_port->use_dma_tx;
286}
287
34df42f5
ES		 288static bool atmel_use_dma_rx(struct uart_port *port)
289{
290 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
291
292 return atmel_port->use_dma_rx;
293}
294
5be605ac
AB		 295static bool atmel_use_fifo(struct uart_port *port)
296{
297 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
298
299 return atmel_port->fifo_size;
300}
301
98f2082c
NF		 302static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
303 struct tasklet_struct *t)
304{
305 if (!atomic_read(&atmel_port->tasklet_shutdown))
306 tasklet_schedule(t);
307}
308
e0b0baad
RG		 309static unsigned int atmel_get_lines_status(struct uart_port *port)
310{
311 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
312 unsigned int status, ret = 0;
313
4e7decda 314 status = atmel_uart_readl(port, ATMEL_US_CSR);
e0b0baad
RG		 315
316 mctrl_gpio_get(atmel_port->gpios, &ret);
317
318 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
319 UART_GPIO_CTS))) {
320 if (ret & TIOCM_CTS)
321 status &= ~ATMEL_US_CTS;
322 else
323 status |= ATMEL_US_CTS;
324 }
325
326 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
327 UART_GPIO_DSR))) {
328 if (ret & TIOCM_DSR)
329 status &= ~ATMEL_US_DSR;
330 else
331 status |= ATMEL_US_DSR;
332 }
333
334 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
335 UART_GPIO_RI))) {
336 if (ret & TIOCM_RI)
337 status &= ~ATMEL_US_RI;
338 else
339 status |= ATMEL_US_RI;
340 }
341
342 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
343 UART_GPIO_DCD))) {
344 if (ret & TIOCM_CD)
345 status &= ~ATMEL_US_DCD;
346 else
347 status |= ATMEL_US_DCD;
348 }
349
350 return status;
351}
352
e8faff73 353/* Enable or disable the rs485 support */
13bd3e6f
RRD		 354static int atmel_config_rs485(struct uart_port *port,
355 struct serial_rs485 *rs485conf)
e8faff73
CS		 356{
357 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
358 unsigned int mode;
e8faff73
CS		 359
360 /* Disable interrupts */
4e7decda 361 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 362
4e7decda 363 mode = atmel_uart_readl(port, ATMEL_US_MR);
e8faff73
CS		 364
365 /* Resetting serial mode to RS232 (0x0) */
366 mode &= ~ATMEL_US_USMODE;
367
13bd3e6f 368 port->rs485 = *rs485conf;
e8faff73
CS		 369
370 if (rs485conf->flags & SER_RS485_ENABLED) {
371 dev_dbg(port->dev, "Setting UART to RS485\n");
372 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
4e7decda
CP		 373 atmel_uart_writel(port, ATMEL_US_TTGR,
374 rs485conf->delay_rts_after_send);
e8faff73
CS		 375 mode |= ATMEL_US_USMODE_RS485;
376 } else {
377 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 378 if (atmel_use_pdc_tx(port))
e8faff73
CS		 379 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
380 ATMEL_US_TXBUFE;
381 else
382 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
383 }
4e7decda 384 atmel_uart_writel(port, ATMEL_US_MR, mode);
e8faff73
CS		 385
386 /* Enable interrupts */
4e7decda 387 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
e8faff73 388
13bd3e6f 389 return 0;
e8faff73
CS		 390}
391
1e6c9c28
AV		 392/*
393 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
394 */
7192f92c 395static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 396{
4e7decda
CP		 397 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
398 TIOCSER_TEMT :
399 0;
1e6c9c28
AV		 400}
401
402/*
403 * Set state of the modem control output lines
404 */
7192f92c 405static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 406{
407 unsigned int control = 0;
4e7decda 408 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
1cf6e8fc 409 unsigned int rts_paused, rts_ready;
e8faff73 410 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 411
1cf6e8fc
CP		 412 /* override mode to RS485 if needed, otherwise keep the current mode */
413 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 414 atmel_uart_writel(port, ATMEL_US_TTGR,
415 port->rs485.delay_rts_after_send);
1cf6e8fc
CP		 416 mode &= ~ATMEL_US_USMODE;
417 mode |= ATMEL_US_USMODE_RS485;
418 }
419
420 /* set the RTS line state according to the mode */
421 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
422 /* force RTS line to high level */
423 rts_paused = ATMEL_US_RTSEN;
424
425 /* give the control of the RTS line back to the hardware */
426 rts_ready = ATMEL_US_RTSDIS;
427 } else {
428 /* force RTS line to high level */
429 rts_paused = ATMEL_US_RTSDIS;
430
431 /* force RTS line to low level */
432 rts_ready = ATMEL_US_RTSEN;
433 }
434
1e6c9c28 435 if (mctrl & TIOCM_RTS)
1cf6e8fc 436 control |= rts_ready;
1e6c9c28 437 else
1cf6e8fc 438 control |= rts_paused;
1e6c9c28
AV		 439
440 if (mctrl & TIOCM_DTR)
7192f92c 441 control |= ATMEL_US_DTREN;
1e6c9c28 442 else
7192f92c 443 control |= ATMEL_US_DTRDIS;
1e6c9c28 444
4e7decda 445 atmel_uart_writel(port, ATMEL_US_CR, control);
afefc415 446
e0b0baad
RG		 447 mctrl_gpio_set(atmel_port->gpios, mctrl);
448
afefc415 449 /* Local loopback mode? */
1cf6e8fc 450 mode &= ~ATMEL_US_CHMODE;
afefc415 451 if (mctrl & TIOCM_LOOP)
7192f92c 452 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 453 else
7192f92c 454 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73 455
4e7decda 456 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28
AV		 457}
458
459/*
460 * Get state of the modem control input lines
461 */
7192f92c 462static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 463{
e0b0baad
RG		 464 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
465 unsigned int ret = 0, status;
1e6c9c28 466
4e7decda 467 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 468
469 /*
470 * The control signals are active low.
471 */
7192f92c 472 if (!(status & ATMEL_US_DCD))
1e6c9c28 473 ret |= TIOCM_CD;
7192f92c 474 if (!(status & ATMEL_US_CTS))
1e6c9c28 475 ret |= TIOCM_CTS;
7192f92c 476 if (!(status & ATMEL_US_DSR))
1e6c9c28 477 ret |= TIOCM_DSR;
7192f92c 478 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 479 ret |= TIOCM_RI;
480
e0b0baad 481 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 482}
483
484/*
485 * Stop transmitting.
486 */
7192f92c 487static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 488{
e8faff73
CS		 489 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
490
64e22ebe 491 if (atmel_use_pdc_tx(port)) {
a6670615 492 /* disable PDC transmit */
4e7decda 493 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
e8faff73 494 }
89d82324
RG		 495
496 /*
497 * Disable the transmitter.
498 * This is mandatory when DMA is used, otherwise the DMA buffer
499 * is fully transmitted.
500 */
501 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
502
e8faff73 503 /* Disable interrupts */
4e7decda 504 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 505
13bd3e6f
RRD		 506 if ((port->rs485.flags & SER_RS485_ENABLED) &&
507 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73 508 atmel_start_rx(port);
1e6c9c28
AV		 509}
510
511/*
512 * Start transmitting.
513 */
7192f92c 514static void atmel_start_tx(struct uart_port *port)
1e6c9c28 515{
e8faff73
CS		 516 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
517
0058f087
AB		 518 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
519 & ATMEL_PDC_TXTEN))
520 /* The transmitter is already running. Yes, we
521 really need this.*/
522 return;
a6670615 523
0058f087 524 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
13bd3e6f
RRD		 525 if ((port->rs485.flags & SER_RS485_ENABLED) &&
526 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73
CS		 527 atmel_stop_rx(port);
528
0058f087 529 if (atmel_use_pdc_tx(port))
a6670615 530 /* re-enable PDC transmit */
4e7decda 531 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
0058f087 532
e8faff73 533 /* Enable interrupts */
4e7decda 534 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
89d82324
RG		 535
536 /* re-enable the transmitter */
537 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
e8faff73
CS		 538}
539
540/*
541 * start receiving - port is in process of being opened.
542 */
543static void atmel_start_rx(struct uart_port *port)
544{
4e7decda
CP		 545 /* reset status and receiver */
546 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
e8faff73 547
4e7decda 548 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
57c36868 549
64e22ebe 550 if (atmel_use_pdc_rx(port)) {
e8faff73 551 /* enable PDC controller */
4e7decda
CP		 552 atmel_uart_writel(port, ATMEL_US_IER,
553 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
554 port->read_status_mask);
555 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
e8faff73 556 } else {
4e7decda 557 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
e8faff73 558 }
1e6c9c28
AV		 559}
560
561/*
562 * Stop receiving - port is in process of being closed.
563 */
7192f92c 564static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 565{
4e7decda 566 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
57c36868 567
64e22ebe 568 if (atmel_use_pdc_rx(port)) {
a6670615 569 /* disable PDC receive */
4e7decda
CP		 570 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
571 atmel_uart_writel(port, ATMEL_US_IDR,
572 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
573 port->read_status_mask);
e8faff73 574 } else {
4e7decda 575 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
e8faff73 576 }
1e6c9c28
AV		 577}
578
579/*
580 * Enable modem status interrupts
581 */
7192f92c 582static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 583{
ab5e4e41
RG		 584 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
585 uint32_t ier = 0;
586
587 /*
588 * Interrupt should not be enabled twice
589 */
590 if (atmel_port->ms_irq_enabled)
591 return;
592
593 atmel_port->ms_irq_enabled = true;
594
18dfef9c 595 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
ab5e4e41
RG		 596 ier |= ATMEL_US_CTSIC;
597
18dfef9c 598 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
ab5e4e41
RG		 599 ier |= ATMEL_US_DSRIC;
600
18dfef9c 601 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
ab5e4e41
RG		 602 ier |= ATMEL_US_RIIC;
603
18dfef9c 604 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
ab5e4e41
RG		 605 ier |= ATMEL_US_DCDIC;
606
4e7decda 607 atmel_uart_writel(port, ATMEL_US_IER, ier);
18dfef9c
UKK		 608
609 mctrl_gpio_enable_ms(atmel_port->gpios);
1e6c9c28
AV		 610}
611
35b675b9
RG		 612/*
613 * Disable modem status interrupts
614 */
615static void atmel_disable_ms(struct uart_port *port)
616{
617 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
618 uint32_t idr = 0;
619
620 /*
621 * Interrupt should not be disabled twice
622 */
623 if (!atmel_port->ms_irq_enabled)
624 return;
625
626 atmel_port->ms_irq_enabled = false;
627
18dfef9c
UKK		 628 mctrl_gpio_disable_ms(atmel_port->gpios);
629
630 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
35b675b9
RG		 631 idr |= ATMEL_US_CTSIC;
632
18dfef9c 633 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
35b675b9
RG		 634 idr |= ATMEL_US_DSRIC;
635
18dfef9c 636 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
35b675b9
RG		 637 idr |= ATMEL_US_RIIC;
638
18dfef9c 639 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
35b675b9
RG		 640 idr |= ATMEL_US_DCDIC;
641
4e7decda 642 atmel_uart_writel(port, ATMEL_US_IDR, idr);
35b675b9
RG		 643}
644
1e6c9c28
AV		 645/*
646 * Control the transmission of a break signal
647 */
7192f92c 648static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 649{
650 if (break_state != 0)
4e7decda
CP		 651 /* start break */
652 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
1e6c9c28 653 else
4e7decda
CP		 654 /* stop break */
655 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
1e6c9c28
AV		 656}
657
1ecc26bd
RB		 658/*
659 * Stores the incoming character in the ring buffer
660 */
661static void
662atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
663 unsigned int ch)
664{
c811ab8c 665 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 666 struct circ_buf *ring = &atmel_port->rx_ring;
667 struct atmel_uart_char *c;
668
669 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
670 /* Buffer overflow, ignore char */
671 return;
672
673 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
674 c->status = status;
675 c->ch = ch;
676
677 /* Make sure the character is stored before we update head. */
678 smp_wmb();
679
680 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
681}
682
a6670615
CC		 683/*
684 * Deal with parity, framing and overrun errors.
685 */
686static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
687{
688 /* clear error */
4e7decda 689 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
a6670615
CC		 690
691 if (status & ATMEL_US_RXBRK) {
692 /* ignore side-effect */
693 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
694 port->icount.brk++;
695 }
696 if (status & ATMEL_US_PARE)
697 port->icount.parity++;
698 if (status & ATMEL_US_FRAME)
699 port->icount.frame++;
700 if (status & ATMEL_US_OVRE)
701 port->icount.overrun++;
702}
703
1e6c9c28
AV		 704/*
705 * Characters received (called from interrupt handler)
706 */
7d12e780 707static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 708{
c811ab8c 709 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 710 unsigned int status, ch;
1e6c9c28 711
4e7decda 712 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 713 while (status & ATMEL_US_RXRDY) {
a6499435 714 ch = atmel_uart_read_char(port);
1e6c9c28 715
1e6c9c28
AV		 716 /*
717 * note that the error handling code is
718 * out of the main execution path
719 */
9e6077bd
HS		 720 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
721 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
722 || atmel_port->break_active)) {
1ecc26bd 723
b843aa21 724 /* clear error */
4e7decda 725 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1ecc26bd 726
9e6077bd
HS		 727 if (status & ATMEL_US_RXBRK
728 && !atmel_port->break_active) {
9e6077bd 729 atmel_port->break_active = 1;
4e7decda
CP		 730 atmel_uart_writel(port, ATMEL_US_IER,
731 ATMEL_US_RXBRK);
9e6077bd
HS		 732 } else {
733 /*
734 * This is either the end-of-break
735 * condition or we've received at
736 * least one character without RXBRK
737 * being set. In both cases, the next
738 * RXBRK will indicate start-of-break.
739 */
4e7decda
CP		 740 atmel_uart_writel(port, ATMEL_US_IDR,
741 ATMEL_US_RXBRK);
9e6077bd
HS		 742 status &= ~ATMEL_US_RXBRK;
743 atmel_port->break_active = 0;
afefc415 744 }
1e6c9c28
AV		 745 }
746
1ecc26bd 747 atmel_buffer_rx_char(port, status, ch);
4e7decda 748 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 749 }
750
98f2082c 751 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1e6c9c28
AV		 752}
753
754/*
1ecc26bd
RB		 755 * Transmit characters (called from tasklet with TXRDY interrupt
756 * disabled)
1e6c9c28 757 */
7192f92c 758static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 759{
ebd2c8f6 760 struct circ_buf *xmit = &port->state->xmit;
e8faff73 761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 762
4e7decda
CP		 763 if (port->x_char &&
764 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
a6499435 765 atmel_uart_write_char(port, port->x_char);
1e6c9c28
AV		 766 port->icount.tx++;
767 port->x_char = 0;
1e6c9c28 768 }
1ecc26bd 769 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 770 return;
1e6c9c28 771
4e7decda
CP		 772 while (atmel_uart_readl(port, ATMEL_US_CSR) &
773 atmel_port->tx_done_mask) {
a6499435 774 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
1e6c9c28
AV		 775 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
776 port->icount.tx++;
777 if (uart_circ_empty(xmit))
778 break;
779 }
780
781 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
782 uart_write_wakeup(port);
783
1ecc26bd 784 if (!uart_circ_empty(xmit))
e8faff73 785 /* Enable interrupts */
4e7decda
CP		 786 atmel_uart_writel(port, ATMEL_US_IER,
787 atmel_port->tx_done_mask);
1e6c9c28
AV		 788}
789
08f738be
ES		 790static void atmel_complete_tx_dma(void *arg)
791{
792 struct atmel_uart_port *atmel_port = arg;
793 struct uart_port *port = &atmel_port->uart;
794 struct circ_buf *xmit = &port->state->xmit;
795 struct dma_chan *chan = atmel_port->chan_tx;
796 unsigned long flags;
797
798 spin_lock_irqsave(&port->lock, flags);
799
800 if (chan)
801 dmaengine_terminate_all(chan);
5f258b3e 802 xmit->tail += atmel_port->tx_len;
08f738be
ES		 803 xmit->tail &= UART_XMIT_SIZE - 1;
804
5f258b3e 805 port->icount.tx += atmel_port->tx_len;
08f738be
ES		 806
807 spin_lock_irq(&atmel_port->lock_tx);
808 async_tx_ack(atmel_port->desc_tx);
809 atmel_port->cookie_tx = -EINVAL;
810 atmel_port->desc_tx = NULL;
811 spin_unlock_irq(&atmel_port->lock_tx);
812
813 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
814 uart_write_wakeup(port);
815
1842dc2e
CP		 816 /*
817 * xmit is a circular buffer so, if we have just send data from
818 * xmit->tail to the end of xmit->buf, now we have to transmit the
819 * remaining data from the beginning of xmit->buf to xmit->head.
820 */
08f738be 821 if (!uart_circ_empty(xmit))
98f2082c 822 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
b389f173
RG		 823 else if ((port->rs485.flags & SER_RS485_ENABLED) &&
824 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
825 /* DMA done, stop TX, start RX for RS485 */
826 atmel_start_rx(port);
827 }
08f738be
ES		 828
829 spin_unlock_irqrestore(&port->lock, flags);
830}
831
832static void atmel_release_tx_dma(struct uart_port *port)
833{
834 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
835 struct dma_chan *chan = atmel_port->chan_tx;
836
837 if (chan) {
838 dmaengine_terminate_all(chan);
839 dma_release_channel(chan);
840 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 841 DMA_TO_DEVICE);
08f738be
ES		 842 }
843
844 atmel_port->desc_tx = NULL;
845 atmel_port->chan_tx = NULL;
846 atmel_port->cookie_tx = -EINVAL;
847}
848
849/*
850 * Called from tasklet with TXRDY interrupt is disabled.
851 */
852static void atmel_tx_dma(struct uart_port *port)
853{
854 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
855 struct circ_buf *xmit = &port->state->xmit;
856 struct dma_chan *chan = atmel_port->chan_tx;
857 struct dma_async_tx_descriptor *desc;
5f258b3e
CP		 858 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
859 unsigned int tx_len, part1_len, part2_len, sg_len;
860 dma_addr_t phys_addr;
08f738be
ES		 861
862 /* Make sure we have an idle channel */
863 if (atmel_port->desc_tx != NULL)
864 return;
865
866 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
867 /*
868 * DMA is idle now.
869 * Port xmit buffer is already mapped,
870 * and it is one page... Just adjust
871 * offsets and lengths. Since it is a circular buffer,
872 * we have to transmit till the end, and then the rest.
873 * Take the port lock to get a
874 * consistent xmit buffer state.
875 */
5f258b3e
CP		 876 tx_len = CIRC_CNT_TO_END(xmit->head,
877 xmit->tail,
878 UART_XMIT_SIZE);
879
880 if (atmel_port->fifo_size) {
881 /* multi data mode */
882 part1_len = (tx_len & ~0x3); /* DWORD access */
883 part2_len = (tx_len & 0x3); /* BYTE access */
884 } else {
885 /* single data (legacy) mode */
886 part1_len = 0;
887 part2_len = tx_len; /* BYTE access only */
888 }
889
890 sg_init_table(sgl, 2);
891 sg_len = 0;
892 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
893 if (part1_len) {
894 sg = &sgl[sg_len++];
895 sg_dma_address(sg) = phys_addr;
896 sg_dma_len(sg) = part1_len;
897
898 phys_addr += part1_len;
899 }
900
901 if (part2_len) {
902 sg = &sgl[sg_len++];
903 sg_dma_address(sg) = phys_addr;
904 sg_dma_len(sg) = part2_len;
905 }
906
907 /*
908 * save tx_len so atmel_complete_tx_dma() will increase
909 * xmit->tail correctly
910 */
911 atmel_port->tx_len = tx_len;
08f738be
ES		 912
913 desc = dmaengine_prep_slave_sg(chan,
5f258b3e
CP		 914 sgl,
915 sg_len,
1842dc2e
CP		 916 DMA_MEM_TO_DEV,
917 DMA_PREP_INTERRUPT |
918 DMA_CTRL_ACK);
08f738be
ES		 919 if (!desc) {
920 dev_err(port->dev, "Failed to send via dma!\n");
921 return;
922 }
923
5f258b3e 924 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
08f738be
ES		 925
926 atmel_port->desc_tx = desc;
927 desc->callback = atmel_complete_tx_dma;
928 desc->callback_param = atmel_port;
929 atmel_port->cookie_tx = dmaengine_submit(desc);
08f738be
ES		 930 }
931
932 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
933 uart_write_wakeup(port);
934}
935
936static int atmel_prepare_tx_dma(struct uart_port *port)
937{
938 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
939 dma_cap_mask_t mask;
940 struct dma_slave_config config;
941 int ret, nent;
942
943 dma_cap_zero(mask);
944 dma_cap_set(DMA_SLAVE, mask);
945
946 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
947 if (atmel_port->chan_tx == NULL)
948 goto chan_err;
949 dev_info(port->dev, "using %s for tx DMA transfers\n",
950 dma_chan_name(atmel_port->chan_tx));
951
952 spin_lock_init(&atmel_port->lock_tx);
953 sg_init_table(&atmel_port->sg_tx, 1);
954 /* UART circular tx buffer is an aligned page. */
2c277054 955 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
08f738be
ES		 956 sg_set_page(&atmel_port->sg_tx,
957 virt_to_page(port->state->xmit.buf),
958 UART_XMIT_SIZE,
c8d1f022 959 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
08f738be
ES		 960 nent = dma_map_sg(port->dev,
961 &atmel_port->sg_tx,
962 1,
48479148 963 DMA_TO_DEVICE);
08f738be
ES		 964
965 if (!nent) {
966 dev_dbg(port->dev, "need to release resource of dma\n");
967 goto chan_err;
968 } else {
c8d1f022 969 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
08f738be
ES		 970 sg_dma_len(&atmel_port->sg_tx),
971 port->state->xmit.buf,
c8d1f022 972 &sg_dma_address(&atmel_port->sg_tx));
08f738be
ES		 973 }
974
975 /* Configure the slave DMA */
976 memset(&config, 0, sizeof(config));
977 config.direction = DMA_MEM_TO_DEV;
5f258b3e
CP		 978 config.dst_addr_width = (atmel_port->fifo_size) ?
979 DMA_SLAVE_BUSWIDTH_4_BYTES :
980 DMA_SLAVE_BUSWIDTH_1_BYTE;
08f738be 981 config.dst_addr = port->mapbase + ATMEL_US_THR;
a8d4e016 982 config.dst_maxburst = 1;
08f738be 983
5483c10e
MR		 984 ret = dmaengine_slave_config(atmel_port->chan_tx,
985 &config);
08f738be
ES		 986 if (ret) {
987 dev_err(port->dev, "DMA tx slave configuration failed\n");
988 goto chan_err;
989 }
990
991 return 0;
992
993chan_err:
994 dev_err(port->dev, "TX channel not available, switch to pio\n");
995 atmel_port->use_dma_tx = 0;
996 if (atmel_port->chan_tx)
997 atmel_release_tx_dma(port);
998 return -EINVAL;
999}
1000
34df42f5
ES		 1001static void atmel_complete_rx_dma(void *arg)
1002{
1003 struct uart_port *port = arg;
1004 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1005
98f2082c 1006 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1007}
1008
1009static void atmel_release_rx_dma(struct uart_port *port)
1010{
1011 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1012 struct dma_chan *chan = atmel_port->chan_rx;
1013
1014 if (chan) {
1015 dmaengine_terminate_all(chan);
1016 dma_release_channel(chan);
1017 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 1018 DMA_FROM_DEVICE);
34df42f5
ES		 1019 }
1020
1021 atmel_port->desc_rx = NULL;
1022 atmel_port->chan_rx = NULL;
1023 atmel_port->cookie_rx = -EINVAL;
1024}
1025
1026static void atmel_rx_from_dma(struct uart_port *port)
1027{
1028 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 1029 struct tty_port *tport = &port->state->port;
34df42f5
ES		 1030 struct circ_buf *ring = &atmel_port->rx_ring;
1031 struct dma_chan *chan = atmel_port->chan_rx;
1032 struct dma_tx_state state;
1033 enum dma_status dmastat;
66f37aaf 1034 size_t count;
34df42f5
ES		 1035
1036
1037 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1038 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5
ES		 1039 dmastat = dmaengine_tx_status(chan,
1040 atmel_port->cookie_rx,
1041 &state);
1042 /* Restart a new tasklet if DMA status is error */
1043 if (dmastat == DMA_ERROR) {
1044 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
4e7decda 1045 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
98f2082c 1046 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1047 return;
1048 }
34df42f5 1049
66f37aaf
CP		 1050 /* CPU claims ownership of RX DMA buffer */
1051 dma_sync_sg_for_cpu(port->dev,
1052 &atmel_port->sg_rx,
1053 1,
485819b5 1054 DMA_FROM_DEVICE);
66f37aaf
CP		 1055
1056 /*
1057 * ring->head points to the end of data already written by the DMA.
1058 * ring->tail points to the beginning of data to be read by the
1059 * framework.
1060 * The current transfer size should not be larger than the dma buffer
1061 * length.
1062 */
1063 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1064 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 1065 /*
66f37aaf
CP		 1066 * At this point ring->head may point to the first byte right after the
1067 * last byte of the dma buffer:
1068 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1069 *
1070 * However ring->tail must always points inside the dma buffer:
1071 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1072 *
1073 * Since we use a ring buffer, we have to handle the case
1074 * where head is lower than tail. In such a case, we first read from
1075 * tail to the end of the buffer then reset tail.
34df42f5 1076 */
66f37aaf
CP		 1077 if (ring->head < ring->tail) {
1078 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 1079
66f37aaf
CP		 1080 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1081 ring->tail = 0;
1082 port->icount.rx += count;
1083 }
34df42f5 1084
66f37aaf
CP		 1085 /* Finally we read data from tail to head */
1086 if (ring->tail < ring->head) {
1087 count = ring->head - ring->tail;
34df42f5 1088
66f37aaf
CP		 1089 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1090 /* Wrap ring->head if needed */
1091 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1092 ring->head = 0;
1093 ring->tail = ring->head;
34df42f5
ES		 1094 port->icount.rx += count;
1095 }
1096
66f37aaf
CP		 1097 /* USART retreives ownership of RX DMA buffer */
1098 dma_sync_sg_for_device(port->dev,
1099 &atmel_port->sg_rx,
1100 1,
485819b5 1101 DMA_FROM_DEVICE);
66f37aaf
CP		 1102
1103 /*
1104 * Drop the lock here since it might end up calling
1105 * uart_start(), which takes the lock.
1106 */
1107 spin_unlock(&port->lock);
1108 tty_flip_buffer_push(tport);
1109 spin_lock(&port->lock);
1110
4e7decda 1111 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
34df42f5
ES		 1112}
1113
1114static int atmel_prepare_rx_dma(struct uart_port *port)
1115{
1116 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1117 struct dma_async_tx_descriptor *desc;
1118 dma_cap_mask_t mask;
1119 struct dma_slave_config config;
1120 struct circ_buf *ring;
1121 int ret, nent;
1122
1123 ring = &atmel_port->rx_ring;
1124
1125 dma_cap_zero(mask);
1126 dma_cap_set(DMA_CYCLIC, mask);
1127
1128 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1129 if (atmel_port->chan_rx == NULL)
1130 goto chan_err;
1131 dev_info(port->dev, "using %s for rx DMA transfers\n",
1132 dma_chan_name(atmel_port->chan_rx));
1133
1134 spin_lock_init(&atmel_port->lock_rx);
1135 sg_init_table(&atmel_port->sg_rx, 1);
1136 /* UART circular rx buffer is an aligned page. */
2c277054 1137 BUG_ON(!PAGE_ALIGNED(ring->buf));
34df42f5 1138 sg_set_page(&atmel_port->sg_rx,
1842dc2e 1139 virt_to_page(ring->buf),
a510880f 1140 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
c8d1f022 1141 (unsigned long)ring->buf & ~PAGE_MASK);
1842dc2e
CP		 1142 nent = dma_map_sg(port->dev,
1143 &atmel_port->sg_rx,
1144 1,
1145 DMA_FROM_DEVICE);
34df42f5
ES		 1146
1147 if (!nent) {
1148 dev_dbg(port->dev, "need to release resource of dma\n");
1149 goto chan_err;
1150 } else {
c8d1f022 1151 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
34df42f5
ES		 1152 sg_dma_len(&atmel_port->sg_rx),
1153 ring->buf,
c8d1f022 1154 &sg_dma_address(&atmel_port->sg_rx));
34df42f5
ES		 1155 }
1156
1157 /* Configure the slave DMA */
1158 memset(&config, 0, sizeof(config));
1159 config.direction = DMA_DEV_TO_MEM;
1160 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1161 config.src_addr = port->mapbase + ATMEL_US_RHR;
a8d4e016 1162 config.src_maxburst = 1;
34df42f5 1163
5483c10e
MR		 1164 ret = dmaengine_slave_config(atmel_port->chan_rx,
1165 &config);
34df42f5
ES		 1166 if (ret) {
1167 dev_err(port->dev, "DMA rx slave configuration failed\n");
1168 goto chan_err;
1169 }
1170 /*
1171 * Prepare a cyclic dma transfer, assign 2 descriptors,
1172 * each one is half ring buffer size
1173 */
1174 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1842dc2e
CP		 1175 sg_dma_address(&atmel_port->sg_rx),
1176 sg_dma_len(&atmel_port->sg_rx),
1177 sg_dma_len(&atmel_port->sg_rx)/2,
1178 DMA_DEV_TO_MEM,
1179 DMA_PREP_INTERRUPT);
34df42f5
ES		 1180 desc->callback = atmel_complete_rx_dma;
1181 desc->callback_param = port;
1182 atmel_port->desc_rx = desc;
1183 atmel_port->cookie_rx = dmaengine_submit(desc);
1184
1185 return 0;
1186
1187chan_err:
1188 dev_err(port->dev, "RX channel not available, switch to pio\n");
1189 atmel_port->use_dma_rx = 0;
1190 if (atmel_port->chan_rx)
1191 atmel_release_rx_dma(port);
1192 return -EINVAL;
1193}
1194
2e68c22f
ES		 1195static void atmel_uart_timer_callback(unsigned long data)
1196{
1197 struct uart_port *port = (void *)data;
1198 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1199
98f2082c
NF		 1200 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1201 tasklet_schedule(&atmel_port->tasklet_rx);
1202 mod_timer(&atmel_port->uart_timer,
1203 jiffies + uart_poll_timeout(port));
1204 }
2e68c22f
ES		 1205}
1206
b843aa21
RB		 1207/*
1208 * receive interrupt handler.
1209 */
1210static void
1211atmel_handle_receive(struct uart_port *port, unsigned int pending)
1212{
c811ab8c 1213 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1214
64e22ebe 1215 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1216 /*
1217 * PDC receive. Just schedule the tasklet and let it
1218 * figure out the details.
1219 *
1220 * TODO: We're not handling error flags correctly at
1221 * the moment.
1222 */
1223 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
4e7decda
CP		 1224 atmel_uart_writel(port, ATMEL_US_IDR,
1225 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
98f2082c
NF		 1226 atmel_tasklet_schedule(atmel_port,
1227 &atmel_port->tasklet_rx);
a6670615
CC		 1228 }
1229
1230 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1231 ATMEL_US_FRAME | ATMEL_US_PARE))
1232 atmel_pdc_rxerr(port, pending);
1233 }
1234
34df42f5
ES		 1235 if (atmel_use_dma_rx(port)) {
1236 if (pending & ATMEL_US_TIMEOUT) {
4e7decda
CP		 1237 atmel_uart_writel(port, ATMEL_US_IDR,
1238 ATMEL_US_TIMEOUT);
98f2082c
NF		 1239 atmel_tasklet_schedule(atmel_port,
1240 &atmel_port->tasklet_rx);
34df42f5
ES		 1241 }
1242 }
1243
b843aa21
RB		 1244 /* Interrupt receive */
1245 if (pending & ATMEL_US_RXRDY)
1246 atmel_rx_chars(port);
1247 else if (pending & ATMEL_US_RXBRK) {
1248 /*
1249 * End of break detected. If it came along with a
1250 * character, atmel_rx_chars will handle it.
1251 */
4e7decda
CP		 1252 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1253 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
b843aa21
RB		 1254 atmel_port->break_active = 0;
1255 }
1256}
1257
1258/*
1ecc26bd 1259 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1260 */
1261static void
1262atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1263{
c811ab8c 1264 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1265
e8faff73
CS		 1266 if (pending & atmel_port->tx_done_mask) {
1267 /* Either PDC or interrupt transmission */
4e7decda
CP		 1268 atmel_uart_writel(port, ATMEL_US_IDR,
1269 atmel_port->tx_done_mask);
98f2082c 1270 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1ecc26bd 1271 }
b843aa21
RB		 1272}
1273
1274/*
1275 * status flags interrupt handler.
1276 */
1277static void
1278atmel_handle_status(struct uart_port *port, unsigned int pending,
1279 unsigned int status)
1280{
c811ab8c 1281 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
9205218e 1282 unsigned int status_change;
1ecc26bd 1283
b843aa21 1284 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd 1285 | ATMEL_US_CTSIC)) {
9205218e 1286 status_change = status ^ atmel_port->irq_status_prev;
d033e82d 1287 atmel_port->irq_status_prev = status;
9205218e
NF		 1288
1289 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1290 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1291 /* TODO: All reads to CSR will clear these interrupts! */
1292 if (status_change & ATMEL_US_RI)
1293 port->icount.rng++;
1294 if (status_change & ATMEL_US_DSR)
1295 port->icount.dsr++;
1296 if (status_change & ATMEL_US_DCD)
1297 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1298 if (status_change & ATMEL_US_CTS)
1299 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1300
1301 wake_up_interruptible(&port->state->port.delta_msr_wait);
1302 }
1ecc26bd 1303 }
b843aa21
RB		 1304}
1305
1e6c9c28
AV		 1306/*
1307 * Interrupt handler
1308 */
7d12e780 1309static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1310{
1311 struct uart_port *port = dev_id;
ab5e4e41 1312 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba 1313 unsigned int status, pending, mask, pass_counter = 0;
1e6c9c28 1314
2c7af5ba
BB		 1315 spin_lock(&atmel_port->lock_suspended);
1316
a6670615 1317 do {
e0b0baad 1318 status = atmel_get_lines_status(port);
4e7decda 1319 mask = atmel_uart_readl(port, ATMEL_US_IMR);
2c7af5ba 1320 pending = status & mask;
a6670615
CC		 1321 if (!pending)
1322 break;
1323
2c7af5ba
BB		 1324 if (atmel_port->suspended) {
1325 atmel_port->pending |= pending;
1326 atmel_port->pending_status = status;
4e7decda 1327 atmel_uart_writel(port, ATMEL_US_IDR, mask);
2c7af5ba
BB		 1328 pm_system_wakeup();
1329 break;
1330 }
1331
b843aa21
RB		 1332 atmel_handle_receive(port, pending);
1333 atmel_handle_status(port, pending, status);
1334 atmel_handle_transmit(port, pending);
a6670615 1335 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1336
2c7af5ba
BB		 1337 spin_unlock(&atmel_port->lock_suspended);
1338
0400b697 1339 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1340}
1e6c9c28 1341
a930e528
ES		 1342static void atmel_release_tx_pdc(struct uart_port *port)
1343{
1344 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1345 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1346
1347 dma_unmap_single(port->dev,
1348 pdc->dma_addr,
1349 pdc->dma_size,
1350 DMA_TO_DEVICE);
1351}
1352
a6670615
CC		 1353/*
1354 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1355 */
64e22ebe 1356static void atmel_tx_pdc(struct uart_port *port)
a6670615 1357{
c811ab8c 1358 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1359 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC		 1360 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1361 int count;
1362
ba0657ff 1363 /* nothing left to transmit? */
4e7decda 1364 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
ba0657ff
MT		 1365 return;
1366
a6670615
CC		 1367 xmit->tail += pdc->ofs;
1368 xmit->tail &= UART_XMIT_SIZE - 1;
1369
1370 port->icount.tx += pdc->ofs;
1371 pdc->ofs = 0;
1372
ba0657ff 1373 /* more to transmit - setup next transfer */
a6670615 1374
ba0657ff 1375 /* disable PDC transmit */
4e7decda 1376 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
ba0657ff 1377
1f14081d 1378 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC		 1379 dma_sync_single_for_device(port->dev,
1380 pdc->dma_addr,
1381 pdc->dma_size,
1382 DMA_TO_DEVICE);
1383
1384 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1385 pdc->ofs = count;
1386
4e7decda
CP		 1387 atmel_uart_writel(port, ATMEL_PDC_TPR,
1388 pdc->dma_addr + xmit->tail);
1389 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
e8faff73 1390 /* re-enable PDC transmit */
4e7decda 1391 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
e8faff73 1392 /* Enable interrupts */
4e7decda
CP		 1393 atmel_uart_writel(port, ATMEL_US_IER,
1394 atmel_port->tx_done_mask);
e8faff73 1395 } else {
13bd3e6f
RRD		 1396 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1397 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
e8faff73
CS		 1398 /* DMA done, stop TX, start RX for RS485 */
1399 atmel_start_rx(port);
1400 }
1e6c9c28 1401 }
a6670615
CC		 1402
1403 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1404 uart_write_wakeup(port);
1e6c9c28
AV		 1405}
1406
a930e528
ES		 1407static int atmel_prepare_tx_pdc(struct uart_port *port)
1408{
1409 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1410 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1411 struct circ_buf *xmit = &port->state->xmit;
1412
1413 pdc->buf = xmit->buf;
1414 pdc->dma_addr = dma_map_single(port->dev,
1415 pdc->buf,
1416 UART_XMIT_SIZE,
1417 DMA_TO_DEVICE);
1418 pdc->dma_size = UART_XMIT_SIZE;
1419 pdc->ofs = 0;
1420
1421 return 0;
1422}
1423
1ecc26bd
RB		 1424static void atmel_rx_from_ring(struct uart_port *port)
1425{
c811ab8c 1426 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1427 struct circ_buf *ring = &atmel_port->rx_ring;
1428 unsigned int flg;
1429 unsigned int status;
1430
1431 while (ring->head != ring->tail) {
1432 struct atmel_uart_char c;
1433
1434 /* Make sure c is loaded after head. */
1435 smp_rmb();
1436
1437 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1438
1439 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1440
1441 port->icount.rx++;
1442 status = c.status;
1443 flg = TTY_NORMAL;
1444
1445 /*
1446 * note that the error handling code is
1447 * out of the main execution path
1448 */
1449 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1450 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1451 if (status & ATMEL_US_RXBRK) {
1452 /* ignore side-effect */
1453 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1454
1455 port->icount.brk++;
1456 if (uart_handle_break(port))
1457 continue;
1458 }
1459 if (status & ATMEL_US_PARE)
1460 port->icount.parity++;
1461 if (status & ATMEL_US_FRAME)
1462 port->icount.frame++;
1463 if (status & ATMEL_US_OVRE)
1464 port->icount.overrun++;
1465
1466 status &= port->read_status_mask;
1467
1468 if (status & ATMEL_US_RXBRK)
1469 flg = TTY_BREAK;
1470 else if (status & ATMEL_US_PARE)
1471 flg = TTY_PARITY;
1472 else if (status & ATMEL_US_FRAME)
1473 flg = TTY_FRAME;
1474 }
1475
1476
1477 if (uart_handle_sysrq_char(port, c.ch))
1478 continue;
1479
1480 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1481 }
1482
1483 /*
1484 * Drop the lock here since it might end up calling
1485 * uart_start(), which takes the lock.
1486 */
1487 spin_unlock(&port->lock);
2e124b4a 1488 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1489 spin_lock(&port->lock);
1490}
1491
a930e528
ES		 1492static void atmel_release_rx_pdc(struct uart_port *port)
1493{
1494 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1495 int i;
1496
1497 for (i = 0; i < 2; i++) {
1498 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1499
1500 dma_unmap_single(port->dev,
1501 pdc->dma_addr,
1502 pdc->dma_size,
1503 DMA_FROM_DEVICE);
1504 kfree(pdc->buf);
1505 }
1506}
1507
64e22ebe 1508static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1509{
c811ab8c 1510 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1511 struct tty_port *tport = &port->state->port;
a6670615
CC		 1512 struct atmel_dma_buffer *pdc;
1513 int rx_idx = atmel_port->pdc_rx_idx;
1514 unsigned int head;
1515 unsigned int tail;
1516 unsigned int count;
1517
1518 do {
1519 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1520 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615
CC		 1521
1522 pdc = &atmel_port->pdc_rx[rx_idx];
4e7decda 1523 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
a6670615
CC		 1524 tail = pdc->ofs;
1525
1526 /* If the PDC has switched buffers, RPR won't contain
1527 * any address within the current buffer. Since head
1528 * is unsigned, we just need a one-way comparison to
1529 * find out.
1530 *
1531 * In this case, we just need to consume the entire
1532 * buffer and resubmit it for DMA. This will clear the
1533 * ENDRX bit as well, so that we can safely re-enable
1534 * all interrupts below.
1535 */
1536 head = min(head, pdc->dma_size);
1537
1538 if (likely(head != tail)) {
1539 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1540 pdc->dma_size, DMA_FROM_DEVICE);
1541
1542 /*
1543 * head will only wrap around when we recycle
1544 * the DMA buffer, and when that happens, we
1545 * explicitly set tail to 0. So head will
1546 * always be greater than tail.
1547 */
1548 count = head - tail;
1549
05c7cd39
JS		 1550 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1551 count);
a6670615
CC		 1552
1553 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1554 pdc->dma_size, DMA_FROM_DEVICE);
1555
1556 port->icount.rx += count;
1557 pdc->ofs = head;
1558 }
1559
1560 /*
1561 * If the current buffer is full, we need to check if
1562 * the next one contains any additional data.
1563 */
1564 if (head >= pdc->dma_size) {
1565 pdc->ofs = 0;
4e7decda
CP		 1566 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1567 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
a6670615
CC		 1568
1569 rx_idx = !rx_idx;
1570 atmel_port->pdc_rx_idx = rx_idx;
1571 }
1572 } while (head >= pdc->dma_size);
1573
1574 /*
1575 * Drop the lock here since it might end up calling
1576 * uart_start(), which takes the lock.
1577 */
1578 spin_unlock(&port->lock);
2e124b4a 1579 tty_flip_buffer_push(tport);
a6670615
CC		 1580 spin_lock(&port->lock);
1581
4e7decda
CP		 1582 atmel_uart_writel(port, ATMEL_US_IER,
1583 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
a6670615
CC		 1584}
1585
a930e528
ES		 1586static int atmel_prepare_rx_pdc(struct uart_port *port)
1587{
1588 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1589 int i;
1590
1591 for (i = 0; i < 2; i++) {
1592 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1593
1594 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1595 if (pdc->buf == NULL) {
1596 if (i != 0) {
1597 dma_unmap_single(port->dev,
1598 atmel_port->pdc_rx[0].dma_addr,
1599 PDC_BUFFER_SIZE,
1600 DMA_FROM_DEVICE);
1601 kfree(atmel_port->pdc_rx[0].buf);
1602 }
1603 atmel_port->use_pdc_rx = 0;
1604 return -ENOMEM;
1605 }
1606 pdc->dma_addr = dma_map_single(port->dev,
1607 pdc->buf,
1608 PDC_BUFFER_SIZE,
1609 DMA_FROM_DEVICE);
1610 pdc->dma_size = PDC_BUFFER_SIZE;
1611 pdc->ofs = 0;
1612 }
1613
1614 atmel_port->pdc_rx_idx = 0;
1615
4e7decda
CP		 1616 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1617 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
a930e528 1618
4e7decda
CP		 1619 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1620 atmel_port->pdc_rx[1].dma_addr);
1621 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
a930e528
ES		 1622
1623 return 0;
1624}
1625
1ecc26bd
RB		 1626/*
1627 * tasklet handling tty stuff outside the interrupt handler.
1628 */
00e8e658 1629static void atmel_tasklet_rx_func(unsigned long data)
1ecc26bd
RB		 1630{
1631 struct uart_port *port = (struct uart_port *)data;
c811ab8c 1632 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1633
1634 /* The interrupt handler does not take the lock */
1635 spin_lock(&port->lock);
a930e528 1636 atmel_port->schedule_rx(port);
00e8e658
NF		 1637 spin_unlock(&port->lock);
1638}
1ecc26bd 1639
00e8e658
NF		 1640static void atmel_tasklet_tx_func(unsigned long data)
1641{
1642 struct uart_port *port = (struct uart_port *)data;
1643 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1644
1645 /* The interrupt handler does not take the lock */
1646 spin_lock(&port->lock);
1647 atmel_port->schedule_tx(port);
1ecc26bd
RB		 1648 spin_unlock(&port->lock);
1649}
1650
4a1e8888 1651static void atmel_init_property(struct atmel_uart_port *atmel_port,
33d64c4f
ES		 1652 struct platform_device *pdev)
1653{
1654 struct device_node *np = pdev->dev.of_node;
574de559 1655 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1656
1657 if (np) {
1658 /* DMA/PDC usage specification */
490d5ce2
JL		 1659 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1660 if (of_property_read_bool(np, "dmas")) {
33d64c4f
ES		 1661 atmel_port->use_dma_rx = true;
1662 atmel_port->use_pdc_rx = false;
1663 } else {
1664 atmel_port->use_dma_rx = false;
1665 atmel_port->use_pdc_rx = true;
1666 }
1667 } else {
1668 atmel_port->use_dma_rx = false;
1669 atmel_port->use_pdc_rx = false;
1670 }
1671
490d5ce2
JL		 1672 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1673 if (of_property_read_bool(np, "dmas")) {
33d64c4f
ES		 1674 atmel_port->use_dma_tx = true;
1675 atmel_port->use_pdc_tx = false;
1676 } else {
1677 atmel_port->use_dma_tx = false;
1678 atmel_port->use_pdc_tx = true;
1679 }
1680 } else {
1681 atmel_port->use_dma_tx = false;
1682 atmel_port->use_pdc_tx = false;
1683 }
1684
1685 } else {
1686 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1687 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1688 atmel_port->use_dma_rx = false;
1689 atmel_port->use_dma_tx = false;
1690 }
1691
33d64c4f
ES		 1692}
1693
13bd3e6f 1694static void atmel_init_rs485(struct uart_port *port,
33d64c4f
ES		 1695 struct platform_device *pdev)
1696{
1697 struct device_node *np = pdev->dev.of_node;
574de559 1698 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1699
1700 if (np) {
77bdec6f 1701 struct serial_rs485 *rs485conf = &port->rs485;
33d64c4f
ES		 1702 u32 rs485_delay[2];
1703 /* rs485 properties */
1704 if (of_property_read_u32_array(np, "rs485-rts-delay",
1705 rs485_delay, 2) == 0) {
33d64c4f
ES		 1706 rs485conf->delay_rts_before_send = rs485_delay[0];
1707 rs485conf->delay_rts_after_send = rs485_delay[1];
1708 rs485conf->flags = 0;
77bdec6f 1709 }
33d64c4f
ES		 1710
1711 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1712 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1713
1714 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1715 NULL))
1716 rs485conf->flags |= SER_RS485_ENABLED;
33d64c4f 1717 } else {
13bd3e6f 1718 port->rs485 = pdata->rs485;
33d64c4f
ES		 1719 }
1720
1721}
1722
a930e528
ES		 1723static void atmel_set_ops(struct uart_port *port)
1724{
1725 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1726
34df42f5
ES		 1727 if (atmel_use_dma_rx(port)) {
1728 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1729 atmel_port->schedule_rx = &atmel_rx_from_dma;
1730 atmel_port->release_rx = &atmel_release_rx_dma;
1731 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1732 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1733 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1734 atmel_port->release_rx = &atmel_release_rx_pdc;
1735 } else {
1736 atmel_port->prepare_rx = NULL;
1737 atmel_port->schedule_rx = &atmel_rx_from_ring;
1738 atmel_port->release_rx = NULL;
1739 }
1740
08f738be
ES		 1741 if (atmel_use_dma_tx(port)) {
1742 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1743 atmel_port->schedule_tx = &atmel_tx_dma;
1744 atmel_port->release_tx = &atmel_release_tx_dma;
1745 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1746 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1747 atmel_port->schedule_tx = &atmel_tx_pdc;
1748 atmel_port->release_tx = &atmel_release_tx_pdc;
1749 } else {
1750 atmel_port->prepare_tx = NULL;
1751 atmel_port->schedule_tx = &atmel_tx_chars;
1752 atmel_port->release_tx = NULL;
1753 }
1754}
1755
055560b0
ES		 1756/*
1757 * Get ip name usart or uart
1758 */
892db58b 1759static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1760{
1761 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
4e7decda 1762 int name = atmel_uart_readl(port, ATMEL_US_NAME);
731d9cae 1763 u32 version;
1d673fb9 1764 u32 usart, dbgu_uart, new_uart;
4b769371
NF		 1765 /* ASCII decoding for IP version */
1766 usart = 0x55534152; /* USAR(T) */
1767 dbgu_uart = 0x44424755; /* DBGU */
1d673fb9 1768 new_uart = 0x55415254; /* UART */
055560b0 1769
5bf5635a
LD		 1770 /*
1771 * Only USART devices from at91sam9260 SOC implement fractional
2867af2d
RI		 1772 * baudrate. It is available for all asynchronous modes, with the
1773 * following restriction: the sampling clock's duty cycle is not
1774 * constant.
5bf5635a
LD		 1775 */
1776 atmel_port->has_frac_baudrate = false;
4b769371 1777 atmel_port->has_hw_timer = false;
055560b0 1778
2958ccee
LD		 1779 if (name == new_uart) {
1780 dev_dbg(port->dev, "Uart with hw timer");
4b769371 1781 atmel_port->has_hw_timer = true;
2958ccee
LD		 1782 atmel_port->rtor = ATMEL_UA_RTOR;
1783 } else if (name == usart) {
1784 dev_dbg(port->dev, "Usart\n");
5bf5635a 1785 atmel_port->has_frac_baudrate = true;
2958ccee
LD		 1786 atmel_port->has_hw_timer = true;
1787 atmel_port->rtor = ATMEL_US_RTOR;
4b769371
NF		 1788 } else if (name == dbgu_uart) {
1789 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
055560b0 1790 } else {
731d9cae 1791 /* fallback for older SoCs: use version field */
4e7decda 1792 version = atmel_uart_readl(port, ATMEL_US_VERSION);
731d9cae
NF		 1793 switch (version) {
1794 case 0x302:
1795 case 0x10213:
1796 dev_dbg(port->dev, "This version is usart\n");
5bf5635a 1797 atmel_port->has_frac_baudrate = true;
4b769371 1798 atmel_port->has_hw_timer = true;
2958ccee 1799 atmel_port->rtor = ATMEL_US_RTOR;
731d9cae
NF		 1800 break;
1801 case 0x203:
1802 case 0x10202:
1803 dev_dbg(port->dev, "This version is uart\n");
731d9cae
NF		 1804 break;
1805 default:
1806 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1807 }
055560b0 1808 }
055560b0
ES		 1809}
1810
1e6c9c28
AV		 1811/*
1812 * Perform initialization and enable port for reception
1813 */
7192f92c 1814static int atmel_startup(struct uart_port *port)
1e6c9c28 1815{
33d64c4f 1816 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1817 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1818 struct tty_struct *tty = port->state->port.tty;
1e6c9c28
AV		 1819 int retval;
1820
1821 /*
1822 * Ensure that no interrupts are enabled otherwise when
1823 * request_irq() is called we could get stuck trying to
1824 * handle an unexpected interrupt
1825 */
4e7decda 1826 atmel_uart_writel(port, ATMEL_US_IDR, -1);
ab5e4e41 1827 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1828
1829 /*
1830 * Allocate the IRQ
1831 */
2c7af5ba
BB		 1832 retval = request_irq(port->irq, atmel_interrupt,
1833 IRQF_SHARED | IRQF_COND_SUSPEND,
ae161068 1834 tty ? tty->name : "atmel_serial", port);
1e6c9c28 1835 if (retval) {
ddaa6037 1836 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1837 return retval;
1838 }
1839
98f2082c
NF		 1840 atomic_set(&atmel_port->tasklet_shutdown, 0);
1841 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1842 (unsigned long)port);
1843 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1844 (unsigned long)port);
1e125786 1845
a6670615
CC		 1846 /*
1847 * Initialize DMA (if necessary)
1848 */
33d64c4f 1849 atmel_init_property(atmel_port, pdev);
4d9628a1 1850 atmel_set_ops(port);
33d64c4f 1851
a930e528
ES		 1852 if (atmel_port->prepare_rx) {
1853 retval = atmel_port->prepare_rx(port);
1854 if (retval < 0)
1855 atmel_set_ops(port);
a6670615 1856 }
a6670615 1857
a930e528
ES		 1858 if (atmel_port->prepare_tx) {
1859 retval = atmel_port->prepare_tx(port);
1860 if (retval < 0)
1861 atmel_set_ops(port);
a6670615 1862 }
1e6c9c28 1863
b5199d46
CP		 1864 /*
1865 * Enable FIFO when available
1866 */
1867 if (atmel_port->fifo_size) {
1868 unsigned int txrdym = ATMEL_US_ONE_DATA;
1869 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1870 unsigned int fmr;
1871
1872 atmel_uart_writel(port, ATMEL_US_CR,
1873 ATMEL_US_FIFOEN |
1874 ATMEL_US_RXFCLR |
1875 ATMEL_US_TXFLCLR);
1876
5f258b3e
CP		 1877 if (atmel_use_dma_tx(port))
1878 txrdym = ATMEL_US_FOUR_DATA;
1879
b5199d46
CP		 1880 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1881 if (atmel_port->rts_high &&
1882 atmel_port->rts_low)
1883 fmr |= ATMEL_US_FRTSC |
1884 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1885 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1886
1887 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1888 }
1889
27c0c8e5 1890 /* Save current CSR for comparison in atmel_tasklet_func() */
e0b0baad 1891 atmel_port->irq_status_prev = atmel_get_lines_status(port);
27c0c8e5 1892
1e6c9c28
AV		 1893 /*
1894 * Finally, enable the serial port
1895 */
4e7decda 1896 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21 1897 /* enable xmit & rcvr */
4e7decda 1898 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 1899
8bc661bf
MR		 1900 setup_timer(&atmel_port->uart_timer,
1901 atmel_uart_timer_callback,
1902 (unsigned long)port);
1903
64e22ebe 1904 if (atmel_use_pdc_rx(port)) {
a6670615 1905 /* set UART timeout */
4b769371 1906 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1907 mod_timer(&atmel_port->uart_timer,
1908 jiffies + uart_poll_timeout(port));
1909 /* set USART timeout */
1910 } else {
2958ccee
LD		 1911 atmel_uart_writel(port, atmel_port->rtor,
1912 PDC_RX_TIMEOUT);
4e7decda 1913 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615 1914
4e7decda
CP		 1915 atmel_uart_writel(port, ATMEL_US_IER,
1916 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
2e68c22f 1917 }
a6670615 1918 /* enable PDC controller */
4e7decda 1919 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
34df42f5 1920 } else if (atmel_use_dma_rx(port)) {
2e68c22f 1921 /* set UART timeout */
4b769371 1922 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1923 mod_timer(&atmel_port->uart_timer,
1924 jiffies + uart_poll_timeout(port));
1925 /* set USART timeout */
1926 } else {
2958ccee
LD		 1927 atmel_uart_writel(port, atmel_port->rtor,
1928 PDC_RX_TIMEOUT);
4e7decda 1929 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5 1930
4e7decda
CP		 1931 atmel_uart_writel(port, ATMEL_US_IER,
1932 ATMEL_US_TIMEOUT);
2e68c22f 1933 }
a6670615
CC		 1934 } else {
1935 /* enable receive only */
4e7decda 1936 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
a6670615 1937 }
afefc415 1938
1e6c9c28
AV		 1939 return 0;
1940}
1941
479e9b94
PH		 1942/*
1943 * Flush any TX data submitted for DMA. Called when the TX circular
1944 * buffer is reset.
1945 */
1946static void atmel_flush_buffer(struct uart_port *port)
1947{
1948 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1949
1950 if (atmel_use_pdc_tx(port)) {
4e7decda 1951 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
479e9b94
PH		 1952 atmel_port->pdc_tx.ofs = 0;
1953 }
31ca2c63
RG		 1954 /*
1955 * in uart_flush_buffer(), the xmit circular buffer has just
1956 * been cleared, so we have to reset tx_len accordingly.
1957 */
1958 atmel_port->tx_len = 0;
479e9b94
PH		 1959}
1960
1e6c9c28
AV		 1961/*
1962 * Disable the port
1963 */
7192f92c 1964static void atmel_shutdown(struct uart_port *port)
1e6c9c28 1965{
c811ab8c 1966 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 1967
0ae9fdef
RG		 1968 /* Disable modem control lines interrupts */
1969 atmel_disable_ms(port);
1970
98f2082c
NF		 1971 /* Disable interrupts at device level */
1972 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1973
1974 /* Prevent spurious interrupts from scheduling the tasklet */
1975 atomic_inc(&atmel_port->tasklet_shutdown);
1976
8bc661bf
MR		 1977 /*
1978 * Prevent any tasklets being scheduled during
1979 * cleanup
1980 */
1981 del_timer_sync(&atmel_port->uart_timer);
1982
98f2082c
NF		 1983 /* Make sure that no interrupt is on the fly */
1984 synchronize_irq(port->irq);
1985
0cc7c6c7
MR		 1986 /*
1987 * Clear out any scheduled tasklets before
1988 * we destroy the buffers
1989 */
00e8e658
NF		 1990 tasklet_kill(&atmel_port->tasklet_rx);
1991 tasklet_kill(&atmel_port->tasklet_tx);
0cc7c6c7 1992
a6670615 1993 /*
0cc7c6c7 1994 * Ensure everything is stopped and
98f2082c 1995 * disable port and break condition.
a6670615
CC		 1996 */
1997 atmel_stop_rx(port);
1998 atmel_stop_tx(port);
1999
4e7decda 2000 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
0cc7c6c7 2001
a6670615
CC		 2002 /*
2003 * Shut-down the DMA.
2004 */
a930e528
ES		 2005 if (atmel_port->release_rx)
2006 atmel_port->release_rx(port);
2007 if (atmel_port->release_tx)
2008 atmel_port->release_tx(port);
a6670615 2009
bb7e73c5
MD		 2010 /*
2011 * Reset ring buffer pointers
2012 */
2013 atmel_port->rx_ring.head = 0;
2014 atmel_port->rx_ring.tail = 0;
2015
1e6c9c28 2016 /*
ab5e4e41 2017 * Free the interrupts
1e6c9c28
AV		 2018 */
2019 free_irq(port->irq, port);
ab5e4e41 2020
479e9b94 2021 atmel_flush_buffer(port);
9afd561a
HS		 2022}
2023
1e6c9c28
AV		 2024/*
2025 * Power / Clock management.
2026 */
b843aa21
RB		 2027static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2028 unsigned int oldstate)
1e6c9c28 2029{
c811ab8c 2030 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2031
1e6c9c28 2032 switch (state) {
b843aa21
RB		 2033 case 0:
2034 /*
2035 * Enable the peripheral clock for this serial port.
2036 * This is called on uart_open() or a resume event.
2037 */
91f8c2d8 2038 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 2039
2040 /* re-enable interrupts if we disabled some on suspend */
4e7decda 2041 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
b843aa21
RB		 2042 break;
2043 case 3:
f05596db 2044 /* Back up the interrupt mask and disable all interrupts */
4e7decda
CP		 2045 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2046 atmel_uart_writel(port, ATMEL_US_IDR, -1);
f05596db 2047
b843aa21
RB		 2048 /*
2049 * Disable the peripheral clock for this serial port.
2050 * This is called on uart_close() or a suspend event.
2051 */
91f8c2d8 2052 clk_disable_unprepare(atmel_port->clk);
b843aa21
RB		 2053 break;
2054 default:
ddaa6037 2055 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 2056 }
2057}
2058
2059/*
2060 * Change the port parameters
2061 */
b843aa21
RB		 2062static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2063 struct ktermios *old)
1e6c9c28 2064{
5bf5635a 2065 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 2066 unsigned long flags;
5bf5635a 2067 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
1cf6e8fc
CP		 2068
2069 /* save the current mode register */
4e7decda 2070 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
1e6c9c28 2071
1cf6e8fc
CP		 2072 /* reset the mode, clock divisor, parity, stop bits and data size */
2073 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2074 ATMEL_US_PAR | ATMEL_US_USMODE);
03abeac0 2075
b843aa21 2076 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 2077
2078 /* byte size */
2079 switch (termios->c_cflag & CSIZE) {
2080 case CS5:
7192f92c 2081 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 2082 break;
2083 case CS6:
7192f92c 2084 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 2085 break;
2086 case CS7:
7192f92c 2087 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 2088 break;
2089 default:
7192f92c 2090 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 2091 break;
2092 }
2093
2094 /* stop bits */
2095 if (termios->c_cflag & CSTOPB)
7192f92c 2096 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 2097
2098 /* parity */
2099 if (termios->c_cflag & PARENB) {
b843aa21
RB		 2100 /* Mark or Space parity */
2101 if (termios->c_cflag & CMSPAR) {
1e6c9c28 2102 if (termios->c_cflag & PARODD)
7192f92c 2103 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 2104 else
7192f92c 2105 mode |= ATMEL_US_PAR_SPACE;
b843aa21 2106 } else if (termios->c_cflag & PARODD)
7192f92c 2107 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 2108 else
7192f92c 2109 mode |= ATMEL_US_PAR_EVEN;
b843aa21 2110 } else
7192f92c 2111 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV		 2112
2113 spin_lock_irqsave(&port->lock, flags);
2114
7192f92c 2115 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 2116 if (termios->c_iflag & INPCK)
7192f92c 2117 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 2118 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 2119 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 2120
64e22ebe 2121 if (atmel_use_pdc_rx(port))
a6670615 2122 /* need to enable error interrupts */
4e7decda 2123 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
a6670615 2124
1e6c9c28
AV		 2125 /*
2126 * Characters to ignore
2127 */
2128 port->ignore_status_mask = 0;
2129 if (termios->c_iflag & IGNPAR)
7192f92c 2130 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 2131 if (termios->c_iflag & IGNBRK) {
7192f92c 2132 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2133 /*
2134 * If we're ignoring parity and break indicators,
2135 * ignore overruns too (for real raw support).
2136 */
2137 if (termios->c_iflag & IGNPAR)
7192f92c 2138 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2139 }
b843aa21 2140 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2141
2142 /* update the per-port timeout */
2143 uart_update_timeout(port, termios->c_cflag, baud);
2144
0ccad870
HS		 2145 /*
2146 * save/disable interrupts. The tty layer will ensure that the
2147 * transmitter is empty if requested by the caller, so there's
2148 * no need to wait for it here.
2149 */
4e7decda
CP		 2150 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2151 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1e6c9c28
AV		 2152
2153 /* disable receiver and transmitter */
4e7decda 2154 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28 2155
1cf6e8fc 2156 /* mode */
13bd3e6f 2157 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 2158 atmel_uart_writel(port, ATMEL_US_TTGR,
2159 port->rs485.delay_rts_after_send);
e8faff73 2160 mode |= ATMEL_US_USMODE_RS485;
1cf6e8fc
CP		 2161 } else if (termios->c_cflag & CRTSCTS) {
2162 /* RS232 with hardware handshake (RTS/CTS) */
9bcffe75
RG		 2163 if (atmel_use_fifo(port) &&
2164 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2165 /*
2166 * with ATMEL_US_USMODE_HWHS set, the controller will
2167 * be able to drive the RTS pin high/low when the RX
2168 * FIFO is above RXFTHRES/below RXFTHRES2.
2169 * It will also disable the transmitter when the CTS
2170 * pin is high.
2171 * This mode is not activated if CTS pin is a GPIO
2172 * because in this case, the transmitter is always
2173 * disabled (there must be an internal pull-up
2174 * responsible for this behaviour).
2175 * If the RTS pin is a GPIO, the controller won't be
2176 * able to drive it according to the FIFO thresholds,
2177 * but it will be handled by the driver.
2178 */
5be605ac 2179 mode |= ATMEL_US_USMODE_HWHS;
9bcffe75
RG		 2180 } else {
2181 /*
2182 * For platforms without FIFO, the flow control is
2183 * handled by the driver.
2184 */
2185 mode |= ATMEL_US_USMODE_NORMAL;
5be605ac 2186 }
1cf6e8fc
CP		 2187 } else {
2188 /* RS232 without hadware handshake */
2189 mode |= ATMEL_US_USMODE_NORMAL;
e8faff73
CS		 2190 }
2191
1cf6e8fc 2192 /* set the mode, clock divisor, parity, stop bits and data size */
4e7decda 2193 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28 2194
1cf6e8fc
CP		 2195 /*
2196 * when switching the mode, set the RTS line state according to the
2197 * new mode, otherwise keep the former state
2198 */
2199 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2200 unsigned int rts_state;
2201
2202 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2203 /* let the hardware control the RTS line */
2204 rts_state = ATMEL_US_RTSDIS;
2205 } else {
2206 /* force RTS line to low level */
2207 rts_state = ATMEL_US_RTSEN;
2208 }
2209
4e7decda 2210 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
1cf6e8fc
CP		 2211 }
2212
5bf5635a
LD		 2213 /*
2214 * Set the baud rate:
2215 * Fractional baudrate allows to setup output frequency more
2216 * accurately. This feature is enabled only when using normal mode.
2217 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2218 * Currently, OVER is always set to 0 so we get
36131cdf
AS		 2219 * baudrate = selected clock / (16 * (CD + FP / 8))
2220 * then
2221 * 8 CD + FP = selected clock / (2 * baudrate)
5bf5635a 2222 */
2867af2d 2223 if (atmel_port->has_frac_baudrate) {
36131cdf
AS		 2224 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2225 cd = div >> 3;
2226 fp = div & ATMEL_US_FP_MASK;
5bf5635a
LD		 2227 } else {
2228 cd = uart_get_divisor(port, baud);
2229 }
2230
2231 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2232 cd /= 8;
2233 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2234 }
2235 quot = cd | fp << ATMEL_US_FP_OFFSET;
2236
4e7decda
CP		 2237 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2238 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2239 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2240
2241 /* restore interrupts */
4e7decda 2242 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2243
2244 /* CTS flow-control and modem-status interrupts */
2245 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2246 atmel_enable_ms(port);
2247 else
2248 atmel_disable_ms(port);
1e6c9c28
AV		 2249
2250 spin_unlock_irqrestore(&port->lock, flags);
2251}
2252
732a84a0 2253static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
42bd7a4f 2254{
732a84a0 2255 if (termios->c_line == N_PPS) {
42bd7a4f 2256 port->flags |= UPF_HARDPPS_CD;
d41510ce 2257 spin_lock_irq(&port->lock);
42bd7a4f 2258 atmel_enable_ms(port);
d41510ce 2259 spin_unlock_irq(&port->lock);
42bd7a4f
VP		 2260 } else {
2261 port->flags &= ~UPF_HARDPPS_CD;
cab68f89
PH		 2262 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2263 spin_lock_irq(&port->lock);
2264 atmel_disable_ms(port);
2265 spin_unlock_irq(&port->lock);
2266 }
42bd7a4f
VP		 2267 }
2268}
2269
1e6c9c28
AV		 2270/*
2271 * Return string describing the specified port
2272 */
7192f92c 2273static const char *atmel_type(struct uart_port *port)
1e6c9c28 2274{
9ab4f88b 2275 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2276}
2277
2278/*
2279 * Release the memory region(s) being used by 'port'.
2280 */
7192f92c 2281static void atmel_release_port(struct uart_port *port)
1e6c9c28 2282{
afefc415
AV		 2283 struct platform_device *pdev = to_platform_device(port->dev);
2284 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2285
2286 release_mem_region(port->mapbase, size);
2287
2288 if (port->flags & UPF_IOREMAP) {
2289 iounmap(port->membase);
2290 port->membase = NULL;
2291 }
1e6c9c28
AV		 2292}
2293
2294/*
2295 * Request the memory region(s) being used by 'port'.
2296 */
7192f92c 2297static int atmel_request_port(struct uart_port *port)
1e6c9c28 2298{
afefc415
AV		 2299 struct platform_device *pdev = to_platform_device(port->dev);
2300 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2301
7192f92c 2302 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2303 return -EBUSY;
2304
2305 if (port->flags & UPF_IOREMAP) {
2306 port->membase = ioremap(port->mapbase, size);
2307 if (port->membase == NULL) {
2308 release_mem_region(port->mapbase, size);
2309 return -ENOMEM;
2310 }
2311 }
1e6c9c28 2312
afefc415 2313 return 0;
1e6c9c28
AV		 2314}
2315
2316/*
2317 * Configure/autoconfigure the port.
2318 */
7192f92c 2319static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2320{
2321 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2322 port->type = PORT_ATMEL;
7192f92c 2323 atmel_request_port(port);
1e6c9c28
AV		 2324 }
2325}
2326
2327/*
2328 * Verify the new serial_struct (for TIOCSSERIAL).
2329 */
7192f92c 2330static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2331{
2332 int ret = 0;
9ab4f88b 2333 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2334 ret = -EINVAL;
2335 if (port->irq != ser->irq)
2336 ret = -EINVAL;
2337 if (ser->io_type != SERIAL_IO_MEM)
2338 ret = -EINVAL;
2339 if (port->uartclk / 16 != ser->baud_base)
2340 ret = -EINVAL;
270c2ade 2341 if (port->mapbase != (unsigned long)ser->iomem_base)
1e6c9c28
AV		 2342 ret = -EINVAL;
2343 if (port->iobase != ser->port)
2344 ret = -EINVAL;
2345 if (ser->hub6 != 0)
2346 ret = -EINVAL;
2347 return ret;
2348}
2349
8fe2d541
AT		 2350#ifdef CONFIG_CONSOLE_POLL
2351static int atmel_poll_get_char(struct uart_port *port)
2352{
4e7decda 2353 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
8fe2d541
AT		 2354 cpu_relax();
2355
a6499435 2356 return atmel_uart_read_char(port);
8fe2d541
AT		 2357}
2358
2359static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2360{
4e7decda 2361 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
8fe2d541
AT		 2362 cpu_relax();
2363
a6499435 2364 atmel_uart_write_char(port, ch);
8fe2d541
AT		 2365}
2366#endif
2367
5c7dcdb6 2368static const struct uart_ops atmel_pops = {
7192f92c
HS		 2369 .tx_empty = atmel_tx_empty,
2370 .set_mctrl = atmel_set_mctrl,
2371 .get_mctrl = atmel_get_mctrl,
2372 .stop_tx = atmel_stop_tx,
2373 .start_tx = atmel_start_tx,
2374 .stop_rx = atmel_stop_rx,
2375 .enable_ms = atmel_enable_ms,
2376 .break_ctl = atmel_break_ctl,
2377 .startup = atmel_startup,
2378 .shutdown = atmel_shutdown,
9afd561a 2379 .flush_buffer = atmel_flush_buffer,
7192f92c 2380 .set_termios = atmel_set_termios,
42bd7a4f 2381 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2382 .type = atmel_type,
2383 .release_port = atmel_release_port,
2384 .request_port = atmel_request_port,
2385 .config_port = atmel_config_port,
2386 .verify_port = atmel_verify_port,
2387 .pm = atmel_serial_pm,
8fe2d541
AT		 2388#ifdef CONFIG_CONSOLE_POLL
2389 .poll_get_char = atmel_poll_get_char,
2390 .poll_put_char = atmel_poll_put_char,
2391#endif
1e6c9c28
AV		 2392};
2393
afefc415
AV		 2394/*
2395 * Configure the port from the platform device resource info.
2396 */
91f8c2d8 2397static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2398 struct platform_device *pdev)
1e6c9c28 2399{
91f8c2d8 2400 int ret;
7192f92c 2401 struct uart_port *port = &atmel_port->uart;
574de559 2402 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
afefc415 2403
4a1e8888
LZ		 2404 atmel_init_property(atmel_port, pdev);
2405 atmel_set_ops(port);
afefc415 2406
13bd3e6f 2407 atmel_init_rs485(port, pdev);
a930e528 2408
e8faff73
CS		 2409 port->iotype = UPIO_MEM;
2410 port->flags = UPF_BOOT_AUTOCONF;
2411 port->ops = &atmel_pops;
2412 port->fifosize = 1;
e8faff73 2413 port->dev = &pdev->dev;
afefc415
AV		 2414 port->mapbase = pdev->resource[0].start;
2415 port->irq = pdev->resource[1].start;
13bd3e6f 2416 port->rs485_config = atmel_config_rs485;
afefc415 2417
1ecc26bd
RB		 2418 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2419
5fbe46b6 2420 if (pdata && pdata->regs) {
75d35213 2421 /* Already mapped by setup code */
1acfc7ec 2422 port->membase = pdata->regs;
588edbf3 2423 } else {
afefc415
AV		 2424 port->flags |= UPF_IOREMAP;
2425 port->membase = NULL;
2426 }
1e6c9c28 2427
b843aa21
RB		 2428 /* for console, the clock could already be configured */
2429 if (!atmel_port->clk) {
7192f92c 2430 atmel_port->clk = clk_get(&pdev->dev, "usart");
91f8c2d8
BB		 2431 if (IS_ERR(atmel_port->clk)) {
2432 ret = PTR_ERR(atmel_port->clk);
2433 atmel_port->clk = NULL;
2434 return ret;
2435 }
2436 ret = clk_prepare_enable(atmel_port->clk);
2437 if (ret) {
2438 clk_put(atmel_port->clk);
2439 atmel_port->clk = NULL;
2440 return ret;
2441 }
7192f92c 2442 port->uartclk = clk_get_rate(atmel_port->clk);
91f8c2d8 2443 clk_disable_unprepare(atmel_port->clk);
06a7f058 2444 /* only enable clock when USART is in use */
afefc415 2445 }
a6670615 2446
e8faff73 2447 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
13bd3e6f 2448 if (port->rs485.flags & SER_RS485_ENABLED)
e8faff73 2449 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2450 else if (atmel_use_pdc_tx(port)) {
a6670615 2451 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2452 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2453 } else {
2454 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2455 }
91f8c2d8
BB		 2456
2457 return 0;
1e6c9c28
AV		 2458}
2459
69f6a27b
JCPV		 2460struct platform_device *atmel_default_console_device; /* the serial console device */
2461
749c4e60 2462#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 2463static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 2464{
4e7decda 2465 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
829dd811 2466 cpu_relax();
a6499435 2467 atmel_uart_write_char(port, ch);
d358788f 2468}
1e6c9c28
AV		 2469
2470/*
2471 * Interrupts are disabled on entering
2472 */
7192f92c 2473static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2474{
7192f92c 2475 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2476 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2477 unsigned int status, imr;
39d4c922 2478 unsigned int pdc_tx;
1e6c9c28
AV		 2479
2480 /*
b843aa21 2481 * First, save IMR and then disable interrupts
1e6c9c28 2482 */
4e7decda
CP		 2483 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2484 atmel_uart_writel(port, ATMEL_US_IDR,
2485 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2486
39d4c922 2487 /* Store PDC transmit status and disable it */
4e7decda
CP		 2488 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2489 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
39d4c922 2490
497e1e16
NF		 2491 /* Make sure that tx path is actually able to send characters */
2492 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2493
7192f92c 2494 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2495
2496 /*
b843aa21
RB		 2497 * Finally, wait for transmitter to become empty
2498 * and restore IMR
1e6c9c28
AV		 2499 */
2500 do {
4e7decda 2501 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 2502 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2503
2504 /* Restore PDC transmit status */
2505 if (pdc_tx)
4e7decda 2506 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
39d4c922 2507
b843aa21 2508 /* set interrupts back the way they were */
4e7decda 2509 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2510}
2511
2512/*
b843aa21
RB		 2513 * If the port was already initialised (eg, by a boot loader),
2514 * try to determine the current setup.
1e6c9c28 2515 */
b843aa21
RB		 2516static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2517 int *parity, int *bits)
1e6c9c28
AV		 2518{
2519 unsigned int mr, quot;
2520
1c0fd82f
HS		 2521 /*
2522 * If the baud rate generator isn't running, the port wasn't
2523 * initialized by the boot loader.
2524 */
4e7decda 2525 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
1c0fd82f
HS		 2526 if (!quot)
2527 return;
1e6c9c28 2528
4e7decda 2529 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
7192f92c 2530 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2531 *bits = 8;
2532 else
2533 *bits = 7;
2534
4e7decda 2535 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
7192f92c 2536 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2537 *parity = 'e';
7192f92c 2538 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2539 *parity = 'o';
2540
4d5e392c
HS		 2541 /*
2542 * The serial core only rounds down when matching this to a
2543 * supported baud rate. Make sure we don't end up slightly
2544 * lower than one of those, as it would make us fall through
2545 * to a much lower baud rate than we really want.
2546 */
4d5e392c 2547 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV		 2548}
2549
7192f92c 2550static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2551{
91f8c2d8 2552 int ret;
7192f92c 2553 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV		 2554 int baud = 115200;
2555 int bits = 8;
2556 int parity = 'n';
2557 int flow = 'n';
2558
b843aa21
RB		 2559 if (port->membase == NULL) {
2560 /* Port not initialized yet - delay setup */
afefc415 2561 return -ENODEV;
b843aa21 2562 }
1e6c9c28 2563
91f8c2d8
BB		 2564 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2565 if (ret)
2566 return ret;
06a7f058 2567
4e7decda
CP		 2568 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2569 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2570 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2571
2572 if (options)
2573 uart_parse_options(options, &baud, &parity, &bits, &flow);
2574 else
7192f92c 2575 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2576
2577 return uart_set_options(port, co, baud, parity, bits, flow);
2578}
2579
7192f92c 2580static struct uart_driver atmel_uart;
1e6c9c28 2581
7192f92c
HS		 2582static struct console atmel_console = {
2583 .name = ATMEL_DEVICENAME,
2584 .write = atmel_console_write,
1e6c9c28 2585 .device = uart_console_device,
7192f92c 2586 .setup = atmel_console_setup,
1e6c9c28
AV		 2587 .flags = CON_PRINTBUFFER,
2588 .index = -1,
7192f92c 2589 .data = &atmel_uart,
1e6c9c28
AV		 2590};
2591
06a7f058 2592#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2593
afefc415
AV		 2594/*
2595 * Early console initialization (before VM subsystem initialized).
2596 */
7192f92c 2597static int __init atmel_console_init(void)
1e6c9c28 2598{
91f8c2d8 2599 int ret;
73e2798b 2600 if (atmel_default_console_device) {
0d0a3cc1 2601 struct atmel_uart_data *pdata =
574de559 2602 dev_get_platdata(&atmel_default_console_device->dev);
efb8d21b 2603 int id = pdata->num;
b78cd169 2604 struct atmel_uart_port *atmel_port = &atmel_ports[id];
4cbf9f48 2605
b78cd169
JA		 2606 atmel_port->backup_imr = 0;
2607 atmel_port->uart.line = id;
0d0a3cc1 2608
4cbf9f48 2609 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
b78cd169 2610 ret = atmel_init_port(atmel_port, atmel_default_console_device);
91f8c2d8
BB		 2611 if (ret)
2612 return ret;
7192f92c 2613 register_console(&atmel_console);
afefc415 2614 }
1e6c9c28 2615
1e6c9c28
AV		 2616 return 0;
2617}
b843aa21 2618
7192f92c 2619console_initcall(atmel_console_init);
1e6c9c28 2620
afefc415
AV		 2621/*
2622 * Late console initialization.
2623 */
7192f92c 2624static int __init atmel_late_console_init(void)
afefc415 2625{
b843aa21
RB		 2626 if (atmel_default_console_device
2627 && !(atmel_console.flags & CON_ENABLED))
7192f92c 2628 register_console(&atmel_console);
afefc415
AV		 2629
2630 return 0;
2631}
b843aa21 2632
7192f92c 2633core_initcall(atmel_late_console_init);
afefc415 2634
dfa7f343
HS		 2635static inline bool atmel_is_console_port(struct uart_port *port)
2636{
2637 return port->cons && port->cons->index == port->line;
2638}
2639
1e6c9c28 2640#else
7192f92c 2641#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS		 2642
2643static inline bool atmel_is_console_port(struct uart_port *port)
2644{
2645 return false;
2646}
1e6c9c28
AV		 2647#endif
2648
7192f92c 2649static struct uart_driver atmel_uart = {
b843aa21
RB		 2650 .owner = THIS_MODULE,
2651 .driver_name = "atmel_serial",
2652 .dev_name = ATMEL_DEVICENAME,
2653 .major = SERIAL_ATMEL_MAJOR,
2654 .minor = MINOR_START,
2655 .nr = ATMEL_MAX_UART,
2656 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2657};
2658
afefc415 2659#ifdef CONFIG_PM
f826caa4
HS		 2660static bool atmel_serial_clk_will_stop(void)
2661{
2662#ifdef CONFIG_ARCH_AT91
2663 return at91_suspend_entering_slow_clock();
2664#else
2665 return false;
2666#endif
2667}
2668
b843aa21
RB		 2669static int atmel_serial_suspend(struct platform_device *pdev,
2670 pm_message_t state)
1e6c9c28 2671{
afefc415 2672 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2673 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2674
e1c609ef
HS		 2675 if (atmel_is_console_port(port) && console_suspend_enabled) {
2676 /* Drain the TX shifter */
4e7decda
CP		 2677 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2678 ATMEL_US_TXEMPTY))
e1c609ef
HS		 2679 cpu_relax();
2680 }
2681
6a5f0e2f
AB		 2682 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2683 /* Cache register values as we won't get a full shutdown/startup
2684 * cycle
2685 */
2686 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2687 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2688 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2689 atmel_port->cache.rtor = atmel_uart_readl(port,
2690 atmel_port->rtor);
2691 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2692 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2693 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2694 }
2695
f05596db
AS		 2696 /* we can not wake up if we're running on slow clock */
2697 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2c7af5ba
BB		 2698 if (atmel_serial_clk_will_stop()) {
2699 unsigned long flags;
2700
2701 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2702 atmel_port->suspended = true;
2703 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
f05596db 2704 device_set_wakeup_enable(&pdev->dev, 0);
2c7af5ba 2705 }
f05596db
AS		 2706
2707 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2708
afefc415
AV		 2709 return 0;
2710}
1e6c9c28 2711
7192f92c 2712static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV		 2713{
2714 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2715 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba
BB		 2716 unsigned long flags;
2717
6a5f0e2f
AB		 2718 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2719 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2720 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2721 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2722 atmel_uart_writel(port, atmel_port->rtor,
2723 atmel_port->cache.rtor);
2724 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2725
2726 if (atmel_port->fifo_size) {
2727 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2728 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2729 atmel_uart_writel(port, ATMEL_US_FMR,
2730 atmel_port->cache.fmr);
2731 atmel_uart_writel(port, ATMEL_US_FIER,
2732 atmel_port->cache.fimr);
2733 }
2734 atmel_start_rx(port);
2735 }
2736
2c7af5ba
BB		 2737 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2738 if (atmel_port->pending) {
2739 atmel_handle_receive(port, atmel_port->pending);
2740 atmel_handle_status(port, atmel_port->pending,
2741 atmel_port->pending_status);
2742 atmel_handle_transmit(port, atmel_port->pending);
2743 atmel_port->pending = 0;
2744 }
2745 atmel_port->suspended = false;
2746 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
1e6c9c28 2747
f05596db
AS		 2748 uart_resume_port(&atmel_uart, port);
2749 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2750
2751 return 0;
2752}
afefc415 2753#else
7192f92c
HS		 2754#define atmel_serial_suspend NULL
2755#define atmel_serial_resume NULL
afefc415 2756#endif
1e6c9c28 2757
b78cd169 2758static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
b5199d46
CP		 2759 struct platform_device *pdev)
2760{
b78cd169
JA		 2761 atmel_port->fifo_size = 0;
2762 atmel_port->rts_low = 0;
2763 atmel_port->rts_high = 0;
b5199d46
CP		 2764
2765 if (of_property_read_u32(pdev->dev.of_node,
2766 "atmel,fifo-size",
b78cd169 2767 &atmel_port->fifo_size))
b5199d46
CP		 2768 return;
2769
b78cd169 2770 if (!atmel_port->fifo_size)
b5199d46
CP		 2771 return;
2772
b78cd169
JA		 2773 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2774 atmel_port->fifo_size = 0;
b5199d46
CP		 2775 dev_err(&pdev->dev, "Invalid FIFO size\n");
2776 return;
2777 }
2778
2779 /*
2780 * 0 <= rts_low <= rts_high <= fifo_size
2781 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2782 * to flush their internal TX FIFO, commonly up to 16 data, before
2783 * actually stopping to send new data. So we try to set the RTS High
2784 * Threshold to a reasonably high value respecting this 16 data
2785 * empirical rule when possible.
2786 */
b78cd169
JA		 2787 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2788 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2789 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2790 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
b5199d46
CP		 2791
2792 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
b78cd169 2793 atmel_port->fifo_size);
b5199d46 2794 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
b78cd169 2795 atmel_port->rts_high);
b5199d46 2796 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
b78cd169 2797 atmel_port->rts_low);
b5199d46
CP		 2798}
2799
9671f099 2800static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2801{
b78cd169 2802 struct atmel_uart_port *atmel_port;
5fbe46b6 2803 struct device_node *np = pdev->dev.of_node;
574de559 2804 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1ecc26bd 2805 void *data;
4cbf9f48 2806 int ret = -ENODEV;
bd737f87 2807 bool rs485_enabled;
1e6c9c28 2808
9d09daf8 2809 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2810
5fbe46b6
NF		 2811 if (np)
2812 ret = of_alias_get_id(np, "serial");
2813 else
2814 if (pdata)
2815 ret = pdata->num;
4cbf9f48
NF		 2816
2817 if (ret < 0)
5fbe46b6 2818 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2819 * auto-enumerate it */
503bded9 2820 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2821
503bded9 2822 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2823 ret = -ENODEV;
2824 goto err;
2825 }
2826
503bded9 2827 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2828 /* port already in use */
2829 ret = -EBUSY;
2830 goto err;
2831 }
2832
b78cd169
JA		 2833 atmel_port = &atmel_ports[ret];
2834 atmel_port->backup_imr = 0;
2835 atmel_port->uart.line = ret;
2836 atmel_serial_probe_fifos(atmel_port, pdev);
e0b0baad 2837
98f2082c 2838 atomic_set(&atmel_port->tasklet_shutdown, 0);
b78cd169 2839 spin_lock_init(&atmel_port->lock_suspended);
2c7af5ba 2840
b78cd169 2841 ret = atmel_init_port(atmel_port, pdev);
91f8c2d8 2842 if (ret)
6fbb9bdf 2843 goto err_clear_bit;
1e6c9c28 2844
b78cd169
JA		 2845 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2846 if (IS_ERR(atmel_port->gpios)) {
2847 ret = PTR_ERR(atmel_port->gpios);
18dfef9c
UKK		 2848 goto err_clear_bit;
2849 }
2850
b78cd169 2851 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
a6670615 2852 ret = -ENOMEM;
6433471d
HS		 2853 data = kmalloc(sizeof(struct atmel_uart_char)
2854 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
a6670615
CC		 2855 if (!data)
2856 goto err_alloc_ring;
b78cd169 2857 atmel_port->rx_ring.buf = data;
a6670615 2858 }
1ecc26bd 2859
b78cd169 2860 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
bd737f87 2861
b78cd169 2862 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
dfa7f343
HS		 2863 if (ret)
2864 goto err_add_port;
2865
8da14b5f 2866#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
b78cd169 2867 if (atmel_is_console_port(&atmel_port->uart)
06a7f058
DB		 2868 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2869 /*
2870 * The serial core enabled the clock for us, so undo
91f8c2d8 2871 * the clk_prepare_enable() in atmel_console_setup()
06a7f058 2872 */
b78cd169 2873 clk_disable_unprepare(atmel_port->clk);
06a7f058 2874 }
8da14b5f 2875#endif
06a7f058 2876
dfa7f343 2877 device_init_wakeup(&pdev->dev, 1);
b78cd169 2878 platform_set_drvdata(pdev, atmel_port);
dfa7f343 2879
d4f64187
CP		 2880 /*
2881 * The peripheral clock has been disabled by atmel_init_port():
2882 * enable it before accessing I/O registers
2883 */
b78cd169 2884 clk_prepare_enable(atmel_port->clk);
d4f64187 2885
bd737f87 2886 if (rs485_enabled) {
b78cd169 2887 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
4e7decda 2888 ATMEL_US_USMODE_NORMAL);
b78cd169
JA		 2889 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2890 ATMEL_US_RTSEN);
5dfbd1d7
CS		 2891 }
2892
055560b0
ES		 2893 /*
2894 * Get port name of usart or uart
2895 */
b78cd169 2896 atmel_get_ip_name(&atmel_port->uart);
055560b0 2897
d4f64187
CP		 2898 /*
2899 * The peripheral clock can now safely be disabled till the port
2900 * is used
2901 */
b78cd169 2902 clk_disable_unprepare(atmel_port->clk);
d4f64187 2903
dfa7f343
HS		 2904 return 0;
2905
2906err_add_port:
b78cd169
JA		 2907 kfree(atmel_port->rx_ring.buf);
2908 atmel_port->rx_ring.buf = NULL;
1ecc26bd 2909err_alloc_ring:
b78cd169
JA		 2910 if (!atmel_is_console_port(&atmel_port->uart)) {
2911 clk_put(atmel_port->clk);
2912 atmel_port->clk = NULL;
afefc415 2913 }
6fbb9bdf 2914err_clear_bit:
b78cd169 2915 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
4cbf9f48 2916err:
afefc415
AV		 2917 return ret;
2918}
2919
f4a8ab04
RI		 2920/*
2921 * Even if the driver is not modular, it makes sense to be able to
2922 * unbind a device: there can be many bound devices, and there are
2923 * situations where dynamic binding and unbinding can be useful.
2924 *
2925 * For example, a connected device can require a specific firmware update
2926 * protocol that needs bitbanging on IO lines, but use the regular serial
2927 * port in the normal case.
2928 */
2929static int atmel_serial_remove(struct platform_device *pdev)
2930{
2931 struct uart_port *port = platform_get_drvdata(pdev);
2932 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2933 int ret = 0;
2934
00e8e658
NF		 2935 tasklet_kill(&atmel_port->tasklet_rx);
2936 tasklet_kill(&atmel_port->tasklet_tx);
f4a8ab04
RI		 2937
2938 device_init_wakeup(&pdev->dev, 0);
2939
2940 ret = uart_remove_one_port(&atmel_uart, port);
2941
2942 kfree(atmel_port->rx_ring.buf);
2943
2944 /* "port" is allocated statically, so we shouldn't free it */
2945
2946 clear_bit(port->line, atmel_ports_in_use);
2947
2948 clk_put(atmel_port->clk);
2949 atmel_port->clk = NULL;
2950
2951 return ret;
2952}
2953
7192f92c
HS		 2954static struct platform_driver atmel_serial_driver = {
2955 .probe = atmel_serial_probe,
f4a8ab04 2956 .remove = atmel_serial_remove,
7192f92c
HS		 2957 .suspend = atmel_serial_suspend,
2958 .resume = atmel_serial_resume,
afefc415 2959 .driver = {
c39dfebc
PG		 2960 .name = "atmel_usart",
2961 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
afefc415
AV		 2962 },
2963};
2964
7192f92c 2965static int __init atmel_serial_init(void)
afefc415
AV		 2966{
2967 int ret;
2968
7192f92c 2969 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 2970 if (ret)
2971 return ret;
2972
7192f92c 2973 ret = platform_driver_register(&atmel_serial_driver);
afefc415 2974 if (ret)
7192f92c 2975 uart_unregister_driver(&atmel_uart);
afefc415
AV		 2976
2977 return ret;
2978}
c39dfebc 2979device_initcall(atmel_serial_init);
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