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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for CLPS711x serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright 1999 ARM Limited | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
1da177e4 | 13 | */ |
1da177e4 LT |
14 | |
15 | #if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
16 | #define SUPPORT_SYSRQ | |
17 | #endif | |
18 | ||
19 | #include <linux/module.h> | |
1da177e4 | 20 | #include <linux/device.h> |
a1c25f2b | 21 | #include <linux/console.h> |
1da177e4 LT |
22 | #include <linux/serial_core.h> |
23 | #include <linux/serial.h> | |
c08f0153 | 24 | #include <linux/clk.h> |
bc000245 | 25 | #include <linux/io.h> |
a1c25f2b AS |
26 | #include <linux/tty.h> |
27 | #include <linux/tty_flip.h> | |
28 | #include <linux/ioport.h> | |
bc000245 | 29 | #include <linux/of.h> |
95113728 | 30 | #include <linux/platform_device.h> |
bc000245 | 31 | #include <linux/regmap.h> |
1da177e4 | 32 | |
bc000245 AS |
33 | #include <linux/mfd/syscon.h> |
34 | #include <linux/mfd/syscon/clps711x.h> | |
1da177e4 | 35 | |
62b0a1b3 AS |
36 | #include "serial_mctrl_gpio.h" |
37 | ||
bc000245 | 38 | #define UART_CLPS711X_DEVNAME "ttyCL" |
117d5d42 AS |
39 | #define UART_CLPS711X_NR 2 |
40 | #define UART_CLPS711X_MAJOR 204 | |
41 | #define UART_CLPS711X_MINOR 40 | |
95113728 | 42 | |
bc000245 AS |
43 | #define UARTDR_OFFSET (0x00) |
44 | #define UBRLCR_OFFSET (0x40) | |
45 | ||
46 | #define UARTDR_FRMERR (1 << 8) | |
47 | #define UARTDR_PARERR (1 << 9) | |
48 | #define UARTDR_OVERR (1 << 10) | |
49 | ||
50 | #define UBRLCR_BAUD_MASK ((1 << 12) - 1) | |
51 | #define UBRLCR_BREAK (1 << 12) | |
52 | #define UBRLCR_PRTEN (1 << 13) | |
53 | #define UBRLCR_EVENPRT (1 << 14) | |
54 | #define UBRLCR_XSTOP (1 << 15) | |
55 | #define UBRLCR_FIFOEN (1 << 16) | |
56 | #define UBRLCR_WRDLEN5 (0 << 17) | |
57 | #define UBRLCR_WRDLEN6 (1 << 17) | |
58 | #define UBRLCR_WRDLEN7 (2 << 17) | |
59 | #define UBRLCR_WRDLEN8 (3 << 17) | |
60 | #define UBRLCR_WRDLEN_MASK (3 << 17) | |
1da177e4 | 61 | |
117d5d42 | 62 | struct clps711x_port { |
bc000245 AS |
63 | struct uart_port port; |
64 | unsigned int tx_enabled; | |
65 | int rx_irq; | |
66 | struct regmap *syscon; | |
62b0a1b3 | 67 | struct mctrl_gpios *gpios; |
bc000245 AS |
68 | }; |
69 | ||
70 | static struct uart_driver clps711x_uart = { | |
71 | .owner = THIS_MODULE, | |
72 | .driver_name = UART_CLPS711X_DEVNAME, | |
73 | .dev_name = UART_CLPS711X_DEVNAME, | |
74 | .major = UART_CLPS711X_MAJOR, | |
75 | .minor = UART_CLPS711X_MINOR, | |
76 | .nr = UART_CLPS711X_NR, | |
117d5d42 AS |
77 | }; |
78 | ||
a1c25f2b | 79 | static void uart_clps711x_stop_tx(struct uart_port *port) |
1da177e4 | 80 | { |
3c7e9eb1 AS |
81 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
82 | ||
bc000245 AS |
83 | if (s->tx_enabled) { |
84 | disable_irq(port->irq); | |
85 | s->tx_enabled = 0; | |
1da177e4 LT |
86 | } |
87 | } | |
88 | ||
a1c25f2b | 89 | static void uart_clps711x_start_tx(struct uart_port *port) |
1da177e4 | 90 | { |
3c7e9eb1 AS |
91 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
92 | ||
bc000245 AS |
93 | if (!s->tx_enabled) { |
94 | s->tx_enabled = 1; | |
95 | enable_irq(port->irq); | |
1da177e4 LT |
96 | } |
97 | } | |
98 | ||
135cc790 | 99 | static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id) |
1da177e4 LT |
100 | { |
101 | struct uart_port *port = dev_id; | |
bc000245 AS |
102 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
103 | unsigned int status, flg; | |
bc000245 | 104 | u16 ch; |
1da177e4 | 105 | |
f27de95c | 106 | for (;;) { |
093a9e2a AS |
107 | u32 sysflg = 0; |
108 | ||
bc000245 AS |
109 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); |
110 | if (sysflg & SYSFLG_URXFE) | |
f27de95c | 111 | break; |
1da177e4 | 112 | |
093a9e2a | 113 | ch = readw(port->membase + UARTDR_OFFSET); |
f27de95c AS |
114 | status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR); |
115 | ch &= 0xff; | |
116 | ||
117 | port->icount.rx++; | |
1da177e4 LT |
118 | flg = TTY_NORMAL; |
119 | ||
f27de95c AS |
120 | if (unlikely(status)) { |
121 | if (status & UARTDR_PARERR) | |
2a9604b8 | 122 | port->icount.parity++; |
f27de95c | 123 | else if (status & UARTDR_FRMERR) |
2a9604b8 | 124 | port->icount.frame++; |
f27de95c | 125 | else if (status & UARTDR_OVERR) |
2a9604b8 | 126 | port->icount.overrun++; |
1da177e4 | 127 | |
f27de95c | 128 | status &= port->read_status_mask; |
1da177e4 | 129 | |
f27de95c | 130 | if (status & UARTDR_PARERR) |
2a9604b8 | 131 | flg = TTY_PARITY; |
f27de95c | 132 | else if (status & UARTDR_FRMERR) |
2a9604b8 | 133 | flg = TTY_FRAME; |
f27de95c AS |
134 | else if (status & UARTDR_OVERR) |
135 | flg = TTY_OVERRUN; | |
2a9604b8 | 136 | } |
1da177e4 | 137 | |
7d12e780 | 138 | if (uart_handle_sysrq_char(port, ch)) |
f27de95c | 139 | continue; |
1da177e4 | 140 | |
f27de95c AS |
141 | if (status & port->ignore_status_mask) |
142 | continue; | |
2a9604b8 | 143 | |
f27de95c | 144 | uart_insert_char(port, status, UARTDR_OVERR, ch, flg); |
1da177e4 | 145 | } |
f27de95c | 146 | |
2e124b4a | 147 | tty_flip_buffer_push(&port->state->port); |
f27de95c | 148 | |
2a9604b8 | 149 | return IRQ_HANDLED; |
1da177e4 LT |
150 | } |
151 | ||
135cc790 | 152 | static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id) |
1da177e4 LT |
153 | { |
154 | struct uart_port *port = dev_id; | |
3c7e9eb1 | 155 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
ebd2c8f6 | 156 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 LT |
157 | |
158 | if (port->x_char) { | |
093a9e2a | 159 | writew(port->x_char, port->membase + UARTDR_OFFSET); |
1da177e4 LT |
160 | port->icount.tx++; |
161 | port->x_char = 0; | |
162 | return IRQ_HANDLED; | |
163 | } | |
7a6fbc9a | 164 | |
3c7e9eb1 | 165 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { |
bc000245 AS |
166 | if (s->tx_enabled) { |
167 | disable_irq_nosync(port->irq); | |
168 | s->tx_enabled = 0; | |
169 | } | |
3c7e9eb1 AS |
170 | return IRQ_HANDLED; |
171 | } | |
1da177e4 | 172 | |
cf03a884 | 173 | while (!uart_circ_empty(xmit)) { |
093a9e2a AS |
174 | u32 sysflg = 0; |
175 | ||
176 | writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET); | |
1da177e4 LT |
177 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
178 | port->icount.tx++; | |
bc000245 AS |
179 | |
180 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); | |
181 | if (sysflg & SYSFLG_UTXFF) | |
1da177e4 | 182 | break; |
cf03a884 | 183 | } |
1da177e4 LT |
184 | |
185 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
186 | uart_write_wakeup(port); | |
187 | ||
1da177e4 LT |
188 | return IRQ_HANDLED; |
189 | } | |
190 | ||
a1c25f2b | 191 | static unsigned int uart_clps711x_tx_empty(struct uart_port *port) |
1da177e4 | 192 | { |
bc000245 | 193 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
093a9e2a | 194 | u32 sysflg = 0; |
bc000245 AS |
195 | |
196 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); | |
197 | ||
198 | return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT; | |
1da177e4 LT |
199 | } |
200 | ||
a1c25f2b | 201 | static unsigned int uart_clps711x_get_mctrl(struct uart_port *port) |
1da177e4 | 202 | { |
62b0a1b3 | 203 | unsigned int result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; |
bc000245 | 204 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
1da177e4 | 205 | |
62b0a1b3 | 206 | return mctrl_gpio_get(s->gpios, &result); |
1da177e4 LT |
207 | } |
208 | ||
a1c25f2b | 209 | static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1da177e4 | 210 | { |
62b0a1b3 AS |
211 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
212 | ||
213 | mctrl_gpio_set(s->gpios, mctrl); | |
1da177e4 LT |
214 | } |
215 | ||
a1c25f2b | 216 | static void uart_clps711x_break_ctl(struct uart_port *port, int break_state) |
1da177e4 | 217 | { |
1da177e4 LT |
218 | unsigned int ubrlcr; |
219 | ||
093a9e2a | 220 | ubrlcr = readl(port->membase + UBRLCR_OFFSET); |
ec335526 | 221 | if (break_state) |
1da177e4 LT |
222 | ubrlcr |= UBRLCR_BREAK; |
223 | else | |
224 | ubrlcr &= ~UBRLCR_BREAK; | |
093a9e2a | 225 | writel(ubrlcr, port->membase + UBRLCR_OFFSET); |
1da177e4 LT |
226 | } |
227 | ||
732a84a0 PH |
228 | static void uart_clps711x_set_ldisc(struct uart_port *port, |
229 | struct ktermios *termios) | |
71b9e8c6 AS |
230 | { |
231 | if (!port->line) { | |
232 | struct clps711x_port *s = dev_get_drvdata(port->dev); | |
233 | ||
234 | regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON1_SIREN, | |
732a84a0 | 235 | (termios->c_line == N_IRDA) ? SYSCON1_SIREN : 0); |
71b9e8c6 AS |
236 | } |
237 | } | |
238 | ||
a1c25f2b | 239 | static int uart_clps711x_startup(struct uart_port *port) |
1da177e4 | 240 | { |
3c7e9eb1 | 241 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
1da177e4 | 242 | |
f52ede2a | 243 | /* Disable break */ |
093a9e2a AS |
244 | writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK, |
245 | port->membase + UBRLCR_OFFSET); | |
f52ede2a AS |
246 | |
247 | /* Enable the port */ | |
bc000245 AS |
248 | return regmap_update_bits(s->syscon, SYSCON_OFFSET, |
249 | SYSCON_UARTEN, SYSCON_UARTEN); | |
1da177e4 LT |
250 | } |
251 | ||
a1c25f2b | 252 | static void uart_clps711x_shutdown(struct uart_port *port) |
1da177e4 | 253 | { |
bc000245 | 254 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
1da177e4 | 255 | |
f52ede2a | 256 | /* Disable the port */ |
bc000245 | 257 | regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0); |
1da177e4 LT |
258 | } |
259 | ||
a1c25f2b AS |
260 | static void uart_clps711x_set_termios(struct uart_port *port, |
261 | struct ktermios *termios, | |
262 | struct ktermios *old) | |
1da177e4 | 263 | { |
bc000245 AS |
264 | u32 ubrlcr; |
265 | unsigned int baud, quot; | |
1da177e4 | 266 | |
7ae75e94 AS |
267 | /* Mask termios capabilities we don't support */ |
268 | termios->c_cflag &= ~CMSPAR; | |
269 | termios->c_iflag &= ~(BRKINT | IGNBRK); | |
1da177e4 | 270 | |
c08f0153 AS |
271 | /* Ask the core to calculate the divisor for us */ |
272 | baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096, | |
273 | port->uartclk / 16); | |
1da177e4 LT |
274 | quot = uart_get_divisor(port, baud); |
275 | ||
276 | switch (termios->c_cflag & CSIZE) { | |
277 | case CS5: | |
278 | ubrlcr = UBRLCR_WRDLEN5; | |
279 | break; | |
280 | case CS6: | |
281 | ubrlcr = UBRLCR_WRDLEN6; | |
282 | break; | |
283 | case CS7: | |
284 | ubrlcr = UBRLCR_WRDLEN7; | |
285 | break; | |
a1c25f2b AS |
286 | case CS8: |
287 | default: | |
1da177e4 LT |
288 | ubrlcr = UBRLCR_WRDLEN8; |
289 | break; | |
290 | } | |
7ae75e94 | 291 | |
1da177e4 LT |
292 | if (termios->c_cflag & CSTOPB) |
293 | ubrlcr |= UBRLCR_XSTOP; | |
7ae75e94 | 294 | |
1da177e4 LT |
295 | if (termios->c_cflag & PARENB) { |
296 | ubrlcr |= UBRLCR_PRTEN; | |
297 | if (!(termios->c_cflag & PARODD)) | |
298 | ubrlcr |= UBRLCR_EVENPRT; | |
299 | } | |
cf03a884 AS |
300 | |
301 | /* Enable FIFO */ | |
302 | ubrlcr |= UBRLCR_FIFOEN; | |
1da177e4 | 303 | |
7ae75e94 | 304 | /* Set read status mask */ |
1da177e4 LT |
305 | port->read_status_mask = UARTDR_OVERR; |
306 | if (termios->c_iflag & INPCK) | |
307 | port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR; | |
308 | ||
7ae75e94 | 309 | /* Set status ignore mask */ |
1da177e4 | 310 | port->ignore_status_mask = 0; |
7ae75e94 AS |
311 | if (!(termios->c_cflag & CREAD)) |
312 | port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR | | |
313 | UARTDR_FRMERR; | |
1da177e4 | 314 | |
7ae75e94 | 315 | uart_update_timeout(port, termios->c_cflag, baud); |
1da177e4 | 316 | |
093a9e2a | 317 | writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET); |
1da177e4 LT |
318 | } |
319 | ||
a1c25f2b | 320 | static const char *uart_clps711x_type(struct uart_port *port) |
1da177e4 | 321 | { |
a1c25f2b | 322 | return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL; |
1da177e4 LT |
323 | } |
324 | ||
a1c25f2b | 325 | static void uart_clps711x_config_port(struct uart_port *port, int flags) |
1da177e4 LT |
326 | { |
327 | if (flags & UART_CONFIG_TYPE) | |
328 | port->type = PORT_CLPS711X; | |
329 | } | |
330 | ||
bc000245 | 331 | static void uart_clps711x_nop_void(struct uart_port *port) |
1da177e4 LT |
332 | { |
333 | } | |
334 | ||
bc000245 | 335 | static int uart_clps711x_nop_int(struct uart_port *port) |
1da177e4 LT |
336 | { |
337 | return 0; | |
338 | } | |
339 | ||
a1c25f2b AS |
340 | static const struct uart_ops uart_clps711x_ops = { |
341 | .tx_empty = uart_clps711x_tx_empty, | |
342 | .set_mctrl = uart_clps711x_set_mctrl, | |
343 | .get_mctrl = uart_clps711x_get_mctrl, | |
344 | .stop_tx = uart_clps711x_stop_tx, | |
345 | .start_tx = uart_clps711x_start_tx, | |
bc000245 | 346 | .stop_rx = uart_clps711x_nop_void, |
a1c25f2b | 347 | .break_ctl = uart_clps711x_break_ctl, |
71b9e8c6 | 348 | .set_ldisc = uart_clps711x_set_ldisc, |
a1c25f2b AS |
349 | .startup = uart_clps711x_startup, |
350 | .shutdown = uart_clps711x_shutdown, | |
351 | .set_termios = uart_clps711x_set_termios, | |
352 | .type = uart_clps711x_type, | |
353 | .config_port = uart_clps711x_config_port, | |
bc000245 AS |
354 | .release_port = uart_clps711x_nop_void, |
355 | .request_port = uart_clps711x_nop_int, | |
1da177e4 LT |
356 | }; |
357 | ||
1da177e4 | 358 | #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE |
117d5d42 | 359 | static void uart_clps711x_console_putchar(struct uart_port *port, int ch) |
d358788f | 360 | { |
bc000245 | 361 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
2f310b8e | 362 | u32 sysflg = 0; |
bc000245 | 363 | |
63e3ad32 | 364 | /* Wait for FIFO is not full */ |
2f310b8e | 365 | do { |
bc000245 | 366 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); |
2f310b8e | 367 | } while (sysflg & SYSFLG_UTXFF); |
117d5d42 | 368 | |
093a9e2a | 369 | writew(ch, port->membase + UARTDR_OFFSET); |
d358788f RK |
370 | } |
371 | ||
117d5d42 AS |
372 | static void uart_clps711x_console_write(struct console *co, const char *c, |
373 | unsigned n) | |
1da177e4 | 374 | { |
bc000245 AS |
375 | struct uart_port *port = clps711x_uart.state[co->index].uart_port; |
376 | struct clps711x_port *s = dev_get_drvdata(port->dev); | |
2f310b8e | 377 | u32 sysflg = 0; |
1da177e4 | 378 | |
117d5d42 | 379 | uart_console_write(port, c, n, uart_clps711x_console_putchar); |
1da177e4 | 380 | |
117d5d42 | 381 | /* Wait for transmitter to become empty */ |
2f310b8e | 382 | do { |
bc000245 | 383 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); |
2f310b8e | 384 | } while (sysflg & SYSFLG_UBUSY); |
1da177e4 LT |
385 | } |
386 | ||
bc000245 | 387 | static int uart_clps711x_console_setup(struct console *co, char *options) |
1da177e4 | 388 | { |
bc000245 AS |
389 | int baud = 38400, bits = 8, parity = 'n', flow = 'n'; |
390 | int ret, index = co->index; | |
391 | struct clps711x_port *s; | |
392 | struct uart_port *port; | |
bc000245 | 393 | unsigned int quot; |
093a9e2a | 394 | u32 ubrlcr; |
1da177e4 | 395 | |
bc000245 AS |
396 | if (index < 0 || index >= UART_CLPS711X_NR) |
397 | return -EINVAL; | |
1da177e4 | 398 | |
bc000245 AS |
399 | port = clps711x_uart.state[index].uart_port; |
400 | if (!port) | |
401 | return -ENODEV; | |
1da177e4 | 402 | |
bc000245 | 403 | s = dev_get_drvdata(port->dev); |
1da177e4 | 404 | |
bc000245 | 405 | if (!options) { |
093a9e2a AS |
406 | u32 syscon = 0; |
407 | ||
bc000245 AS |
408 | regmap_read(s->syscon, SYSCON_OFFSET, &syscon); |
409 | if (syscon & SYSCON_UARTEN) { | |
093a9e2a | 410 | ubrlcr = readl(port->membase + UBRLCR_OFFSET); |
1da177e4 | 411 | |
bc000245 AS |
412 | if (ubrlcr & UBRLCR_PRTEN) { |
413 | if (ubrlcr & UBRLCR_EVENPRT) | |
414 | parity = 'e'; | |
415 | else | |
416 | parity = 'o'; | |
417 | } | |
1da177e4 | 418 | |
bc000245 AS |
419 | if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7) |
420 | bits = 7; | |
421 | ||
422 | quot = ubrlcr & UBRLCR_BAUD_MASK; | |
423 | baud = port->uartclk / (16 * (quot + 1)); | |
424 | } | |
425 | } else | |
1da177e4 | 426 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
1da177e4 | 427 | |
bc000245 AS |
428 | ret = uart_set_options(port, co, baud, parity, bits, flow); |
429 | if (ret) | |
430 | return ret; | |
431 | ||
432 | return regmap_update_bits(s->syscon, SYSCON_OFFSET, | |
433 | SYSCON_UARTEN, SYSCON_UARTEN); | |
1da177e4 | 434 | } |
bc000245 AS |
435 | |
436 | static struct console clps711x_console = { | |
437 | .name = UART_CLPS711X_DEVNAME, | |
438 | .device = uart_console_device, | |
439 | .write = uart_clps711x_console_write, | |
440 | .setup = uart_clps711x_console_setup, | |
441 | .flags = CON_PRINTBUFFER, | |
442 | .index = -1, | |
443 | }; | |
1da177e4 LT |
444 | #endif |
445 | ||
9671f099 | 446 | static int uart_clps711x_probe(struct platform_device *pdev) |
1da177e4 | 447 | { |
bc000245 AS |
448 | struct device_node *np = pdev->dev.of_node; |
449 | int ret, index = np ? of_alias_get_id(np, "serial") : pdev->id; | |
117d5d42 | 450 | struct clps711x_port *s; |
bc000245 AS |
451 | struct resource *res; |
452 | struct clk *uart_clk; | |
8f5405c9 | 453 | int irq; |
1da177e4 | 454 | |
bc000245 AS |
455 | if (index < 0 || index >= UART_CLPS711X_NR) |
456 | return -EINVAL; | |
457 | ||
458 | s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); | |
459 | if (!s) | |
117d5d42 | 460 | return -ENOMEM; |
bc000245 AS |
461 | |
462 | uart_clk = devm_clk_get(&pdev->dev, NULL); | |
463 | if (IS_ERR(uart_clk)) | |
464 | return PTR_ERR(uart_clk); | |
465 | ||
466 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
467 | s->port.membase = devm_ioremap_resource(&pdev->dev, res); | |
468 | if (IS_ERR(s->port.membase)) | |
469 | return PTR_ERR(s->port.membase); | |
470 | ||
8f5405c9 GR |
471 | irq = platform_get_irq(pdev, 0); |
472 | if (irq < 0) | |
473 | return irq; | |
474 | s->port.irq = irq; | |
bc000245 AS |
475 | |
476 | s->rx_irq = platform_get_irq(pdev, 1); | |
8f5405c9 | 477 | if (s->rx_irq < 0) |
bc000245 AS |
478 | return s->rx_irq; |
479 | ||
480 | if (!np) { | |
481 | char syscon_name[9]; | |
482 | ||
483 | sprintf(syscon_name, "syscon.%i", index + 1); | |
484 | s->syscon = syscon_regmap_lookup_by_pdevname(syscon_name); | |
485 | if (IS_ERR(s->syscon)) | |
486 | return PTR_ERR(s->syscon); | |
bc000245 AS |
487 | } else { |
488 | s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon"); | |
489 | if (IS_ERR(s->syscon)) | |
490 | return PTR_ERR(s->syscon); | |
117d5d42 | 491 | } |
bc000245 AS |
492 | |
493 | s->port.line = index; | |
494 | s->port.dev = &pdev->dev; | |
495 | s->port.iotype = UPIO_MEM32; | |
496 | s->port.mapbase = res->start; | |
497 | s->port.type = PORT_CLPS711X; | |
498 | s->port.fifosize = 16; | |
499 | s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; | |
500 | s->port.uartclk = clk_get_rate(uart_clk); | |
501 | s->port.ops = &uart_clps711x_ops; | |
502 | ||
117d5d42 | 503 | platform_set_drvdata(pdev, s); |
1da177e4 | 504 | |
7d8c70d8 | 505 | s->gpios = mctrl_gpio_init_noauto(&pdev->dev, 0); |
f059a455 UKK |
506 | if (IS_ERR(s->gpios)) |
507 | return PTR_ERR(s->gpios); | |
62b0a1b3 | 508 | |
bc000245 AS |
509 | ret = uart_add_one_port(&clps711x_uart, &s->port); |
510 | if (ret) | |
511 | return ret; | |
c08f0153 | 512 | |
bc000245 AS |
513 | /* Disable port */ |
514 | if (!uart_console(&s->port)) | |
515 | regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0); | |
516 | ||
517 | s->tx_enabled = 1; | |
518 | ||
519 | ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0, | |
520 | dev_name(&pdev->dev), &s->port); | |
117d5d42 | 521 | if (ret) { |
bc000245 | 522 | uart_remove_one_port(&clps711x_uart, &s->port); |
43b829b3 | 523 | return ret; |
117d5d42 | 524 | } |
1da177e4 | 525 | |
bc000245 AS |
526 | ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0, |
527 | dev_name(&pdev->dev), &s->port); | |
528 | if (ret) | |
529 | uart_remove_one_port(&clps711x_uart, &s->port); | |
1da177e4 | 530 | |
bc000245 | 531 | return ret; |
1da177e4 LT |
532 | } |
533 | ||
ae8d8a14 | 534 | static int uart_clps711x_remove(struct platform_device *pdev) |
1da177e4 | 535 | { |
117d5d42 | 536 | struct clps711x_port *s = platform_get_drvdata(pdev); |
95113728 | 537 | |
bc000245 | 538 | return uart_remove_one_port(&clps711x_uart, &s->port); |
1da177e4 LT |
539 | } |
540 | ||
bc000245 | 541 | static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = { |
d305345c | 542 | { .compatible = "cirrus,ep7209-uart", }, |
bc000245 AS |
543 | { } |
544 | }; | |
545 | MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids); | |
546 | ||
547 | static struct platform_driver clps711x_uart_platform = { | |
95113728 | 548 | .driver = { |
bc000245 | 549 | .name = "clps711x-uart", |
bc000245 | 550 | .of_match_table = of_match_ptr(clps711x_uart_dt_ids), |
95113728 AS |
551 | }, |
552 | .probe = uart_clps711x_probe, | |
2d47b716 | 553 | .remove = uart_clps711x_remove, |
95113728 | 554 | }; |
95113728 AS |
555 | |
556 | static int __init uart_clps711x_init(void) | |
557 | { | |
bc000245 AS |
558 | int ret; |
559 | ||
560 | #ifdef CONFIG_SERIAL_CLPS711X_CONSOLE | |
561 | clps711x_uart.cons = &clps711x_console; | |
562 | clps711x_console.data = &clps711x_uart; | |
563 | #endif | |
564 | ||
565 | ret = uart_register_driver(&clps711x_uart); | |
566 | if (ret) | |
567 | return ret; | |
568 | ||
569 | return platform_driver_register(&clps711x_uart_platform); | |
95113728 AS |
570 | } |
571 | module_init(uart_clps711x_init); | |
572 | ||
573 | static void __exit uart_clps711x_exit(void) | |
574 | { | |
bc000245 AS |
575 | platform_driver_unregister(&clps711x_uart_platform); |
576 | uart_unregister_driver(&clps711x_uart); | |
95113728 AS |
577 | } |
578 | module_exit(uart_clps711x_exit); | |
1da177e4 LT |
579 | |
580 | MODULE_AUTHOR("Deep Blue Solutions Ltd"); | |
95113728 | 581 | MODULE_DESCRIPTION("CLPS711X serial driver"); |
1da177e4 | 582 | MODULE_LICENSE("GPL"); |