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77accbf5 | 1 | /* |
1da177e4 LT |
2 | * Serial port driver for the ETRAX 100LX chip |
3 | * | |
77accbf5 | 4 | * Copyright (C) 1998-2007 Axis Communications AB |
1da177e4 LT |
5 | * |
6 | * Many, many authors. Based once upon a time on serial.c for 16x50. | |
7 | * | |
1da177e4 LT |
8 | */ |
9 | ||
10 | static char *serial_version = "$Revision: 1.25 $"; | |
11 | ||
1da177e4 LT |
12 | #include <linux/types.h> |
13 | #include <linux/errno.h> | |
14 | #include <linux/signal.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/timer.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/tty.h> | |
19 | #include <linux/tty_flip.h> | |
20 | #include <linux/major.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/fcntl.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/init.h> | |
1da177e4 | 26 | #include <linux/kernel.h> |
f392ecfa | 27 | #include <linux/mutex.h> |
1977f032 | 28 | #include <linux/bitops.h> |
9e040a3e JN |
29 | #include <linux/seq_file.h> |
30 | #include <linux/delay.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/uaccess.h> | |
33 | #include <linux/io.h> | |
1da177e4 | 34 | |
1da177e4 | 35 | #include <asm/irq.h> |
77accbf5 | 36 | #include <asm/dma.h> |
1da177e4 | 37 | |
556dcee7 | 38 | #include <arch/svinto.h> |
b1a154db | 39 | #include <arch/system.h> |
1da177e4 LT |
40 | |
41 | /* non-arch dependent serial structures are in linux/serial.h */ | |
42 | #include <linux/serial.h> | |
43 | /* while we keep our own stuff (struct e100_serial) in a local .h file */ | |
77accbf5 | 44 | #include "crisv10.h" |
1da177e4 | 45 | #include <asm/fasttimer.h> |
556dcee7 | 46 | #include <arch/io_interface_mux.h> |
1da177e4 LT |
47 | |
48 | #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER | |
49 | #ifndef CONFIG_ETRAX_FAST_TIMER | |
50 | #error "Enable FAST_TIMER to use SERIAL_FAST_TIMER" | |
51 | #endif | |
52 | #endif | |
53 | ||
54 | #if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \ | |
55 | (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0) | |
56 | #error "RX_TIMEOUT_TICKS == 0 not allowed, use 1" | |
57 | #endif | |
58 | ||
59 | #if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G) | |
60 | #error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G" | |
61 | #endif | |
62 | ||
63 | /* | |
64 | * All of the compatibilty code so we can compile serial.c against | |
65 | * older kernels is hidden in serial_compat.h | |
66 | */ | |
67 | #if defined(LOCAL_HEADERS) | |
68 | #include "serial_compat.h" | |
69 | #endif | |
70 | ||
1da177e4 LT |
71 | struct tty_driver *serial_driver; |
72 | ||
1da177e4 LT |
73 | /* number of characters left in xmit buffer before we ask for more */ |
74 | #define WAKEUP_CHARS 256 | |
75 | ||
76 | //#define SERIAL_DEBUG_INTR | |
77 | //#define SERIAL_DEBUG_OPEN | |
78 | //#define SERIAL_DEBUG_FLOW | |
79 | //#define SERIAL_DEBUG_DATA | |
80 | //#define SERIAL_DEBUG_THROTTLE | |
81 | //#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */ | |
82 | //#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */ | |
83 | ||
84 | /* Enable this to use serial interrupts to handle when you | |
85 | expect the first received event on the serial port to | |
86 | be an error, break or similar. Used to be able to flash IRMA | |
87 | from eLinux */ | |
88 | #define SERIAL_HANDLE_EARLY_ERRORS | |
89 | ||
1da177e4 LT |
90 | /* Currently 16 descriptors x 128 bytes = 2048 bytes */ |
91 | #define SERIAL_DESCR_BUF_SIZE 256 | |
92 | ||
93 | #define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */ | |
94 | #define DEF_BAUD_BASE SERIAL_PRESCALE_BASE | |
95 | ||
96 | /* We don't want to load the system with massive fast timer interrupt | |
97 | * on high baudrates so limit it to 250 us (4kHz) */ | |
98 | #define MIN_FLUSH_TIME_USEC 250 | |
99 | ||
100 | /* Add an x here to log a lot of timer stuff */ | |
101 | #define TIMERD(x) | |
102 | /* Debug details of interrupt handling */ | |
103 | #define DINTR1(x) /* irq on/off, errors */ | |
104 | #define DINTR2(x) /* tx and rx */ | |
105 | /* Debug flip buffer stuff */ | |
106 | #define DFLIP(x) | |
107 | /* Debug flow control and overview of data flow */ | |
108 | #define DFLOW(x) | |
109 | #define DBAUD(x) | |
110 | #define DLOG_INT_TRIG(x) | |
111 | ||
112 | //#define DEBUG_LOG_INCLUDED | |
113 | #ifndef DEBUG_LOG_INCLUDED | |
114 | #define DEBUG_LOG(line, string, value) | |
115 | #else | |
116 | struct debug_log_info | |
117 | { | |
118 | unsigned long time; | |
119 | unsigned long timer_data; | |
120 | // int line; | |
121 | const char *string; | |
122 | int value; | |
123 | }; | |
124 | #define DEBUG_LOG_SIZE 4096 | |
125 | ||
126 | struct debug_log_info debug_log[DEBUG_LOG_SIZE]; | |
127 | int debug_log_pos = 0; | |
128 | ||
129 | #define DEBUG_LOG(_line, _string, _value) do { \ | |
130 | if ((_line) == SERIAL_DEBUG_LINE) {\ | |
131 | debug_log_func(_line, _string, _value); \ | |
132 | }\ | |
133 | }while(0) | |
134 | ||
135 | void debug_log_func(int line, const char *string, int value) | |
136 | { | |
137 | if (debug_log_pos < DEBUG_LOG_SIZE) { | |
138 | debug_log[debug_log_pos].time = jiffies; | |
139 | debug_log[debug_log_pos].timer_data = *R_TIMER_DATA; | |
140 | // debug_log[debug_log_pos].line = line; | |
141 | debug_log[debug_log_pos].string = string; | |
142 | debug_log[debug_log_pos].value = value; | |
143 | debug_log_pos++; | |
144 | } | |
145 | /*printk(string, value);*/ | |
146 | } | |
147 | #endif | |
148 | ||
149 | #ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS | |
150 | /* Default number of timer ticks before flushing rx fifo | |
151 | * When using "little data, low latency applications: use 0 | |
152 | * When using "much data applications (PPP)" use ~5 | |
153 | */ | |
154 | #define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5 | |
155 | #endif | |
156 | ||
157 | unsigned long timer_data_to_ns(unsigned long timer_data); | |
158 | ||
159 | static void change_speed(struct e100_serial *info); | |
160 | static void rs_throttle(struct tty_struct * tty); | |
161 | static void rs_wait_until_sent(struct tty_struct *tty, int timeout); | |
77accbf5 JN |
162 | static int rs_write(struct tty_struct *tty, |
163 | const unsigned char *buf, int count); | |
1da177e4 | 164 | #ifdef CONFIG_ETRAX_RS485 |
77accbf5 JN |
165 | static int e100_write_rs485(struct tty_struct *tty, |
166 | const unsigned char *buf, int count); | |
1da177e4 | 167 | #endif |
77accbf5 | 168 | static int get_lsr_info(struct e100_serial *info, unsigned int *value); |
1da177e4 LT |
169 | |
170 | ||
171 | #define DEF_BAUD 115200 /* 115.2 kbit/s */ | |
1da177e4 LT |
172 | #define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */ |
173 | /* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */ | |
174 | #define DEF_TX 0x80 /* or SERIAL_CTRL_B */ | |
175 | ||
176 | /* offsets from R_SERIALx_CTRL */ | |
177 | ||
178 | #define REG_DATA 0 | |
179 | #define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */ | |
180 | #define REG_TR_DATA 0 | |
181 | #define REG_STATUS 1 | |
182 | #define REG_TR_CTRL 1 | |
183 | #define REG_REC_CTRL 2 | |
184 | #define REG_BAUD 3 | |
185 | #define REG_XOFF 4 /* this is a 32 bit register */ | |
186 | ||
187 | /* The bitfields are the same for all serial ports */ | |
188 | #define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd) | |
189 | #define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail) | |
190 | #define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err) | |
191 | #define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err) | |
192 | #define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun) | |
193 | ||
194 | #define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK) | |
195 | ||
196 | /* Values for info->errorcode */ | |
197 | #define ERRCODE_SET_BREAK (TTY_BREAK) | |
198 | #define ERRCODE_INSERT 0x100 | |
199 | #define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK) | |
200 | ||
201 | #define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop; | |
202 | ||
203 | /* | |
204 | * General note regarding the use of IO_* macros in this file: | |
205 | * | |
206 | * We will use the bits defined for DMA channel 6 when using various | |
207 | * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are | |
208 | * the same for all channels (which of course they are). | |
209 | * | |
210 | * We will also use the bits defined for serial port 0 when writing commands | |
211 | * to the different ports, as these bits too are the same for all ports. | |
212 | */ | |
213 | ||
214 | ||
215 | /* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */ | |
216 | static const unsigned long e100_ser_int_mask = 0 | |
217 | #ifdef CONFIG_ETRAX_SERIAL_PORT0 | |
218 | | IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready) | |
219 | #endif | |
220 | #ifdef CONFIG_ETRAX_SERIAL_PORT1 | |
221 | | IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready) | |
222 | #endif | |
223 | #ifdef CONFIG_ETRAX_SERIAL_PORT2 | |
224 | | IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready) | |
225 | #endif | |
226 | #ifdef CONFIG_ETRAX_SERIAL_PORT3 | |
227 | | IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready) | |
228 | #endif | |
229 | ; | |
230 | unsigned long r_alt_ser_baudrate_shadow = 0; | |
231 | ||
232 | /* this is the data for the four serial ports in the etrax100 */ | |
233 | /* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */ | |
234 | /* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */ | |
235 | ||
236 | static struct e100_serial rs_table[] = { | |
237 | { .baud = DEF_BAUD, | |
d7283353 | 238 | .ioport = (unsigned char *)R_SERIAL0_CTRL, |
1da177e4 LT |
239 | .irq = 1U << 12, /* uses DMA 6 and 7 */ |
240 | .oclrintradr = R_DMA_CH6_CLR_INTR, | |
241 | .ofirstadr = R_DMA_CH6_FIRST, | |
242 | .ocmdadr = R_DMA_CH6_CMD, | |
243 | .ostatusadr = R_DMA_CH6_STATUS, | |
244 | .iclrintradr = R_DMA_CH7_CLR_INTR, | |
245 | .ifirstadr = R_DMA_CH7_FIRST, | |
246 | .icmdadr = R_DMA_CH7_CMD, | |
247 | .idescradr = R_DMA_CH7_DESCR, | |
1da177e4 LT |
248 | .rx_ctrl = DEF_RX, |
249 | .tx_ctrl = DEF_TX, | |
250 | .iseteop = 2, | |
77accbf5 JN |
251 | .dma_owner = dma_ser0, |
252 | .io_if = if_serial_0, | |
1da177e4 LT |
253 | #ifdef CONFIG_ETRAX_SERIAL_PORT0 |
254 | .enabled = 1, | |
255 | #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT | |
256 | .dma_out_enabled = 1, | |
77accbf5 JN |
257 | .dma_out_nbr = SER0_TX_DMA_NBR, |
258 | .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR, | |
9cfb5c05 | 259 | .dma_out_irq_flags = 0, |
77accbf5 | 260 | .dma_out_irq_description = "serial 0 dma tr", |
1da177e4 LT |
261 | #else |
262 | .dma_out_enabled = 0, | |
77accbf5 JN |
263 | .dma_out_nbr = UINT_MAX, |
264 | .dma_out_irq_nbr = 0, | |
265 | .dma_out_irq_flags = 0, | |
266 | .dma_out_irq_description = NULL, | |
1da177e4 LT |
267 | #endif |
268 | #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN | |
269 | .dma_in_enabled = 1, | |
77accbf5 JN |
270 | .dma_in_nbr = SER0_RX_DMA_NBR, |
271 | .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR, | |
9cfb5c05 | 272 | .dma_in_irq_flags = 0, |
77accbf5 | 273 | .dma_in_irq_description = "serial 0 dma rec", |
1da177e4 | 274 | #else |
77accbf5 JN |
275 | .dma_in_enabled = 0, |
276 | .dma_in_nbr = UINT_MAX, | |
277 | .dma_in_irq_nbr = 0, | |
278 | .dma_in_irq_flags = 0, | |
279 | .dma_in_irq_description = NULL, | |
1da177e4 LT |
280 | #endif |
281 | #else | |
282 | .enabled = 0, | |
77accbf5 | 283 | .io_if_description = NULL, |
1da177e4 LT |
284 | .dma_out_enabled = 0, |
285 | .dma_in_enabled = 0 | |
286 | #endif | |
287 | ||
288 | }, /* ttyS0 */ | |
1da177e4 | 289 | { .baud = DEF_BAUD, |
d7283353 | 290 | .ioport = (unsigned char *)R_SERIAL1_CTRL, |
1da177e4 LT |
291 | .irq = 1U << 16, /* uses DMA 8 and 9 */ |
292 | .oclrintradr = R_DMA_CH8_CLR_INTR, | |
293 | .ofirstadr = R_DMA_CH8_FIRST, | |
294 | .ocmdadr = R_DMA_CH8_CMD, | |
295 | .ostatusadr = R_DMA_CH8_STATUS, | |
296 | .iclrintradr = R_DMA_CH9_CLR_INTR, | |
297 | .ifirstadr = R_DMA_CH9_FIRST, | |
298 | .icmdadr = R_DMA_CH9_CMD, | |
299 | .idescradr = R_DMA_CH9_DESCR, | |
1da177e4 LT |
300 | .rx_ctrl = DEF_RX, |
301 | .tx_ctrl = DEF_TX, | |
302 | .iseteop = 3, | |
77accbf5 JN |
303 | .dma_owner = dma_ser1, |
304 | .io_if = if_serial_1, | |
1da177e4 LT |
305 | #ifdef CONFIG_ETRAX_SERIAL_PORT1 |
306 | .enabled = 1, | |
77accbf5 | 307 | .io_if_description = "ser1", |
1da177e4 LT |
308 | #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT |
309 | .dma_out_enabled = 1, | |
77accbf5 JN |
310 | .dma_out_nbr = SER1_TX_DMA_NBR, |
311 | .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR, | |
9cfb5c05 | 312 | .dma_out_irq_flags = 0, |
77accbf5 | 313 | .dma_out_irq_description = "serial 1 dma tr", |
1da177e4 LT |
314 | #else |
315 | .dma_out_enabled = 0, | |
77accbf5 JN |
316 | .dma_out_nbr = UINT_MAX, |
317 | .dma_out_irq_nbr = 0, | |
318 | .dma_out_irq_flags = 0, | |
319 | .dma_out_irq_description = NULL, | |
1da177e4 LT |
320 | #endif |
321 | #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN | |
322 | .dma_in_enabled = 1, | |
77accbf5 JN |
323 | .dma_in_nbr = SER1_RX_DMA_NBR, |
324 | .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR, | |
9cfb5c05 | 325 | .dma_in_irq_flags = 0, |
77accbf5 | 326 | .dma_in_irq_description = "serial 1 dma rec", |
1da177e4 | 327 | #else |
77accbf5 JN |
328 | .dma_in_enabled = 0, |
329 | .dma_in_enabled = 0, | |
330 | .dma_in_nbr = UINT_MAX, | |
331 | .dma_in_irq_nbr = 0, | |
332 | .dma_in_irq_flags = 0, | |
333 | .dma_in_irq_description = NULL, | |
1da177e4 LT |
334 | #endif |
335 | #else | |
336 | .enabled = 0, | |
77accbf5 JN |
337 | .io_if_description = NULL, |
338 | .dma_in_irq_nbr = 0, | |
1da177e4 LT |
339 | .dma_out_enabled = 0, |
340 | .dma_in_enabled = 0 | |
341 | #endif | |
342 | }, /* ttyS1 */ | |
343 | ||
344 | { .baud = DEF_BAUD, | |
d7283353 | 345 | .ioport = (unsigned char *)R_SERIAL2_CTRL, |
1da177e4 LT |
346 | .irq = 1U << 4, /* uses DMA 2 and 3 */ |
347 | .oclrintradr = R_DMA_CH2_CLR_INTR, | |
348 | .ofirstadr = R_DMA_CH2_FIRST, | |
349 | .ocmdadr = R_DMA_CH2_CMD, | |
350 | .ostatusadr = R_DMA_CH2_STATUS, | |
351 | .iclrintradr = R_DMA_CH3_CLR_INTR, | |
352 | .ifirstadr = R_DMA_CH3_FIRST, | |
353 | .icmdadr = R_DMA_CH3_CMD, | |
354 | .idescradr = R_DMA_CH3_DESCR, | |
1da177e4 LT |
355 | .rx_ctrl = DEF_RX, |
356 | .tx_ctrl = DEF_TX, | |
357 | .iseteop = 0, | |
77accbf5 JN |
358 | .dma_owner = dma_ser2, |
359 | .io_if = if_serial_2, | |
1da177e4 LT |
360 | #ifdef CONFIG_ETRAX_SERIAL_PORT2 |
361 | .enabled = 1, | |
77accbf5 | 362 | .io_if_description = "ser2", |
1da177e4 LT |
363 | #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT |
364 | .dma_out_enabled = 1, | |
77accbf5 JN |
365 | .dma_out_nbr = SER2_TX_DMA_NBR, |
366 | .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR, | |
9cfb5c05 | 367 | .dma_out_irq_flags = 0, |
77accbf5 | 368 | .dma_out_irq_description = "serial 2 dma tr", |
1da177e4 LT |
369 | #else |
370 | .dma_out_enabled = 0, | |
77accbf5 JN |
371 | .dma_out_nbr = UINT_MAX, |
372 | .dma_out_irq_nbr = 0, | |
373 | .dma_out_irq_flags = 0, | |
374 | .dma_out_irq_description = NULL, | |
1da177e4 LT |
375 | #endif |
376 | #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN | |
377 | .dma_in_enabled = 1, | |
77accbf5 JN |
378 | .dma_in_nbr = SER2_RX_DMA_NBR, |
379 | .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR, | |
9cfb5c05 | 380 | .dma_in_irq_flags = 0, |
77accbf5 | 381 | .dma_in_irq_description = "serial 2 dma rec", |
1da177e4 | 382 | #else |
77accbf5 JN |
383 | .dma_in_enabled = 0, |
384 | .dma_in_nbr = UINT_MAX, | |
385 | .dma_in_irq_nbr = 0, | |
386 | .dma_in_irq_flags = 0, | |
387 | .dma_in_irq_description = NULL, | |
1da177e4 LT |
388 | #endif |
389 | #else | |
390 | .enabled = 0, | |
77accbf5 | 391 | .io_if_description = NULL, |
1da177e4 LT |
392 | .dma_out_enabled = 0, |
393 | .dma_in_enabled = 0 | |
394 | #endif | |
395 | }, /* ttyS2 */ | |
396 | ||
397 | { .baud = DEF_BAUD, | |
d7283353 | 398 | .ioport = (unsigned char *)R_SERIAL3_CTRL, |
1da177e4 LT |
399 | .irq = 1U << 8, /* uses DMA 4 and 5 */ |
400 | .oclrintradr = R_DMA_CH4_CLR_INTR, | |
401 | .ofirstadr = R_DMA_CH4_FIRST, | |
402 | .ocmdadr = R_DMA_CH4_CMD, | |
403 | .ostatusadr = R_DMA_CH4_STATUS, | |
404 | .iclrintradr = R_DMA_CH5_CLR_INTR, | |
405 | .ifirstadr = R_DMA_CH5_FIRST, | |
406 | .icmdadr = R_DMA_CH5_CMD, | |
407 | .idescradr = R_DMA_CH5_DESCR, | |
1da177e4 LT |
408 | .rx_ctrl = DEF_RX, |
409 | .tx_ctrl = DEF_TX, | |
410 | .iseteop = 1, | |
77accbf5 JN |
411 | .dma_owner = dma_ser3, |
412 | .io_if = if_serial_3, | |
1da177e4 LT |
413 | #ifdef CONFIG_ETRAX_SERIAL_PORT3 |
414 | .enabled = 1, | |
77accbf5 | 415 | .io_if_description = "ser3", |
1da177e4 LT |
416 | #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT |
417 | .dma_out_enabled = 1, | |
77accbf5 JN |
418 | .dma_out_nbr = SER3_TX_DMA_NBR, |
419 | .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR, | |
9cfb5c05 | 420 | .dma_out_irq_flags = 0, |
77accbf5 | 421 | .dma_out_irq_description = "serial 3 dma tr", |
1da177e4 LT |
422 | #else |
423 | .dma_out_enabled = 0, | |
77accbf5 JN |
424 | .dma_out_nbr = UINT_MAX, |
425 | .dma_out_irq_nbr = 0, | |
426 | .dma_out_irq_flags = 0, | |
427 | .dma_out_irq_description = NULL, | |
1da177e4 LT |
428 | #endif |
429 | #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN | |
430 | .dma_in_enabled = 1, | |
77accbf5 JN |
431 | .dma_in_nbr = SER3_RX_DMA_NBR, |
432 | .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR, | |
9cfb5c05 | 433 | .dma_in_irq_flags = 0, |
77accbf5 | 434 | .dma_in_irq_description = "serial 3 dma rec", |
1da177e4 | 435 | #else |
77accbf5 JN |
436 | .dma_in_enabled = 0, |
437 | .dma_in_nbr = UINT_MAX, | |
438 | .dma_in_irq_nbr = 0, | |
439 | .dma_in_irq_flags = 0, | |
440 | .dma_in_irq_description = NULL | |
1da177e4 LT |
441 | #endif |
442 | #else | |
443 | .enabled = 0, | |
77accbf5 | 444 | .io_if_description = NULL, |
1da177e4 LT |
445 | .dma_out_enabled = 0, |
446 | .dma_in_enabled = 0 | |
447 | #endif | |
448 | } /* ttyS3 */ | |
1da177e4 LT |
449 | }; |
450 | ||
451 | ||
452 | #define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial)) | |
453 | ||
1da177e4 LT |
454 | #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER |
455 | static struct fast_timer fast_timers[NR_PORTS]; | |
456 | #endif | |
457 | ||
458 | #ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY | |
459 | #define PROCSTAT(x) x | |
460 | struct ser_statistics_type { | |
461 | int overrun_cnt; | |
462 | int early_errors_cnt; | |
463 | int ser_ints_ok_cnt; | |
464 | int errors_cnt; | |
465 | unsigned long int processing_flip; | |
466 | unsigned long processing_flip_still_room; | |
467 | unsigned long int timeout_flush_cnt; | |
468 | int rx_dma_ints; | |
469 | int tx_dma_ints; | |
470 | int rx_tot; | |
471 | int tx_tot; | |
472 | }; | |
473 | ||
474 | static struct ser_statistics_type ser_stat[NR_PORTS]; | |
475 | ||
476 | #else | |
477 | ||
478 | #define PROCSTAT(x) | |
479 | ||
480 | #endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */ | |
481 | ||
482 | /* RS-485 */ | |
483 | #if defined(CONFIG_ETRAX_RS485) | |
484 | #ifdef CONFIG_ETRAX_FAST_TIMER | |
485 | static struct fast_timer fast_timers_rs485[NR_PORTS]; | |
486 | #endif | |
487 | #if defined(CONFIG_ETRAX_RS485_ON_PA) | |
488 | static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT; | |
489 | #endif | |
490 | #if defined(CONFIG_ETRAX_RS485_ON_PORT_G) | |
491 | static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT; | |
492 | #endif | |
493 | #endif | |
494 | ||
495 | /* Info and macros needed for each ports extra control/status signals. */ | |
496 | #define E100_STRUCT_PORT(line, pinname) \ | |
497 | ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \ | |
498 | (R_PORT_PA_DATA): ( \ | |
499 | (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \ | |
500 | (R_PORT_PB_DATA):&dummy_ser[line])) | |
501 | ||
502 | #define E100_STRUCT_SHADOW(line, pinname) \ | |
503 | ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \ | |
504 | (&port_pa_data_shadow): ( \ | |
505 | (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \ | |
506 | (&port_pb_data_shadow):&dummy_ser[line])) | |
507 | #define E100_STRUCT_MASK(line, pinname) \ | |
508 | ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \ | |
509 | (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \ | |
510 | (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \ | |
511 | (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK)) | |
512 | ||
513 | #define DUMMY_DTR_MASK 1 | |
514 | #define DUMMY_RI_MASK 2 | |
515 | #define DUMMY_DSR_MASK 4 | |
516 | #define DUMMY_CD_MASK 8 | |
517 | static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF}; | |
518 | ||
519 | /* If not all status pins are used or disabled, use mixed mode */ | |
520 | #ifdef CONFIG_ETRAX_SERIAL_PORT0 | |
521 | ||
522 | #define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT) | |
523 | ||
524 | #if SER0_PA_BITSUM != -4 | |
525 | # if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1 | |
526 | # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED | |
527 | # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1 | |
528 | # endif | |
529 | # endif | |
530 | # if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1 | |
531 | # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED | |
532 | # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1 | |
533 | # endif | |
534 | # endif | |
535 | # if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1 | |
536 | # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED | |
537 | # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1 | |
538 | # endif | |
539 | # endif | |
540 | # if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1 | |
541 | # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED | |
542 | # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1 | |
543 | # endif | |
544 | # endif | |
545 | #endif | |
546 | ||
547 | #define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT) | |
548 | ||
549 | #if SER0_PB_BITSUM != -4 | |
550 | # if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1 | |
551 | # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED | |
552 | # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1 | |
553 | # endif | |
554 | # endif | |
555 | # if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1 | |
556 | # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED | |
557 | # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1 | |
558 | # endif | |
559 | # endif | |
560 | # if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1 | |
561 | # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED | |
562 | # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1 | |
563 | # endif | |
564 | # endif | |
565 | # if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1 | |
566 | # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED | |
567 | # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1 | |
568 | # endif | |
569 | # endif | |
570 | #endif | |
571 | ||
572 | #endif /* PORT0 */ | |
573 | ||
574 | ||
575 | #ifdef CONFIG_ETRAX_SERIAL_PORT1 | |
576 | ||
577 | #define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT) | |
578 | ||
579 | #if SER1_PA_BITSUM != -4 | |
580 | # if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1 | |
581 | # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED | |
582 | # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1 | |
583 | # endif | |
584 | # endif | |
585 | # if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1 | |
586 | # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED | |
587 | # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1 | |
588 | # endif | |
589 | # endif | |
590 | # if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1 | |
591 | # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED | |
592 | # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1 | |
593 | # endif | |
594 | # endif | |
595 | # if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1 | |
596 | # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED | |
597 | # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1 | |
598 | # endif | |
599 | # endif | |
600 | #endif | |
601 | ||
602 | #define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT) | |
603 | ||
604 | #if SER1_PB_BITSUM != -4 | |
605 | # if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1 | |
606 | # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED | |
607 | # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1 | |
608 | # endif | |
609 | # endif | |
610 | # if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1 | |
611 | # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED | |
612 | # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1 | |
613 | # endif | |
614 | # endif | |
615 | # if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1 | |
616 | # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED | |
617 | # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1 | |
618 | # endif | |
619 | # endif | |
620 | # if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1 | |
621 | # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED | |
622 | # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1 | |
623 | # endif | |
624 | # endif | |
625 | #endif | |
626 | ||
627 | #endif /* PORT1 */ | |
628 | ||
629 | #ifdef CONFIG_ETRAX_SERIAL_PORT2 | |
630 | ||
631 | #define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT) | |
632 | ||
633 | #if SER2_PA_BITSUM != -4 | |
634 | # if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1 | |
635 | # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED | |
636 | # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1 | |
637 | # endif | |
638 | # endif | |
639 | # if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1 | |
640 | # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED | |
641 | # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1 | |
642 | # endif | |
643 | # endif | |
644 | # if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1 | |
645 | # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED | |
646 | # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1 | |
647 | # endif | |
648 | # endif | |
649 | # if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1 | |
650 | # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED | |
651 | # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1 | |
652 | # endif | |
653 | # endif | |
654 | #endif | |
655 | ||
656 | #define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT) | |
657 | ||
658 | #if SER2_PB_BITSUM != -4 | |
659 | # if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1 | |
660 | # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED | |
661 | # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1 | |
662 | # endif | |
663 | # endif | |
664 | # if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1 | |
665 | # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED | |
666 | # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1 | |
667 | # endif | |
668 | # endif | |
669 | # if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1 | |
670 | # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED | |
671 | # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1 | |
672 | # endif | |
673 | # endif | |
674 | # if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1 | |
675 | # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED | |
676 | # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1 | |
677 | # endif | |
678 | # endif | |
679 | #endif | |
680 | ||
681 | #endif /* PORT2 */ | |
682 | ||
683 | #ifdef CONFIG_ETRAX_SERIAL_PORT3 | |
684 | ||
685 | #define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT) | |
686 | ||
687 | #if SER3_PA_BITSUM != -4 | |
688 | # if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1 | |
689 | # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED | |
690 | # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1 | |
691 | # endif | |
692 | # endif | |
693 | # if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1 | |
694 | # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED | |
695 | # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1 | |
696 | # endif | |
697 | # endif | |
698 | # if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1 | |
699 | # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED | |
700 | # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1 | |
701 | # endif | |
702 | # endif | |
703 | # if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1 | |
704 | # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED | |
705 | # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1 | |
706 | # endif | |
707 | # endif | |
708 | #endif | |
709 | ||
710 | #define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT) | |
711 | ||
712 | #if SER3_PB_BITSUM != -4 | |
713 | # if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1 | |
714 | # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED | |
715 | # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1 | |
716 | # endif | |
717 | # endif | |
718 | # if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1 | |
719 | # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED | |
720 | # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1 | |
721 | # endif | |
722 | # endif | |
723 | # if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1 | |
724 | # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED | |
725 | # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1 | |
726 | # endif | |
727 | # endif | |
728 | # if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1 | |
729 | # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED | |
730 | # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1 | |
731 | # endif | |
732 | # endif | |
733 | #endif | |
734 | ||
735 | #endif /* PORT3 */ | |
736 | ||
737 | ||
738 | #if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \ | |
739 | defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \ | |
740 | defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \ | |
741 | defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED) | |
742 | #define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED | |
743 | #endif | |
744 | ||
745 | #ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED | |
746 | /* The pins can be mixed on PA and PB */ | |
747 | #define CONTROL_PINS_PORT_NOT_USED(line) \ | |
748 | &dummy_ser[line], &dummy_ser[line], \ | |
749 | &dummy_ser[line], &dummy_ser[line], \ | |
750 | &dummy_ser[line], &dummy_ser[line], \ | |
751 | &dummy_ser[line], &dummy_ser[line], \ | |
752 | DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK | |
753 | ||
754 | ||
755 | struct control_pins | |
756 | { | |
757 | volatile unsigned char *dtr_port; | |
758 | unsigned char *dtr_shadow; | |
759 | volatile unsigned char *ri_port; | |
760 | unsigned char *ri_shadow; | |
761 | volatile unsigned char *dsr_port; | |
762 | unsigned char *dsr_shadow; | |
763 | volatile unsigned char *cd_port; | |
764 | unsigned char *cd_shadow; | |
765 | ||
766 | unsigned char dtr_mask; | |
767 | unsigned char ri_mask; | |
768 | unsigned char dsr_mask; | |
769 | unsigned char cd_mask; | |
770 | }; | |
771 | ||
772 | static const struct control_pins e100_modem_pins[NR_PORTS] = | |
773 | { | |
774 | /* Ser 0 */ | |
775 | { | |
776 | #ifdef CONFIG_ETRAX_SERIAL_PORT0 | |
777 | E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR), | |
778 | E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI), | |
779 | E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR), | |
780 | E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD), | |
781 | E100_STRUCT_MASK(0,DTR), | |
782 | E100_STRUCT_MASK(0,RI), | |
783 | E100_STRUCT_MASK(0,DSR), | |
784 | E100_STRUCT_MASK(0,CD) | |
785 | #else | |
786 | CONTROL_PINS_PORT_NOT_USED(0) | |
787 | #endif | |
788 | }, | |
789 | ||
790 | /* Ser 1 */ | |
791 | { | |
792 | #ifdef CONFIG_ETRAX_SERIAL_PORT1 | |
793 | E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR), | |
794 | E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI), | |
795 | E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR), | |
796 | E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD), | |
797 | E100_STRUCT_MASK(1,DTR), | |
798 | E100_STRUCT_MASK(1,RI), | |
799 | E100_STRUCT_MASK(1,DSR), | |
800 | E100_STRUCT_MASK(1,CD) | |
801 | #else | |
802 | CONTROL_PINS_PORT_NOT_USED(1) | |
803 | #endif | |
804 | }, | |
805 | ||
806 | /* Ser 2 */ | |
807 | { | |
808 | #ifdef CONFIG_ETRAX_SERIAL_PORT2 | |
809 | E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR), | |
810 | E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI), | |
811 | E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR), | |
812 | E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD), | |
813 | E100_STRUCT_MASK(2,DTR), | |
814 | E100_STRUCT_MASK(2,RI), | |
815 | E100_STRUCT_MASK(2,DSR), | |
816 | E100_STRUCT_MASK(2,CD) | |
817 | #else | |
818 | CONTROL_PINS_PORT_NOT_USED(2) | |
819 | #endif | |
820 | }, | |
821 | ||
822 | /* Ser 3 */ | |
823 | { | |
824 | #ifdef CONFIG_ETRAX_SERIAL_PORT3 | |
825 | E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR), | |
826 | E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI), | |
827 | E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR), | |
828 | E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD), | |
829 | E100_STRUCT_MASK(3,DTR), | |
830 | E100_STRUCT_MASK(3,RI), | |
831 | E100_STRUCT_MASK(3,DSR), | |
832 | E100_STRUCT_MASK(3,CD) | |
833 | #else | |
834 | CONTROL_PINS_PORT_NOT_USED(3) | |
835 | #endif | |
836 | } | |
837 | }; | |
838 | #else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */ | |
839 | ||
840 | /* All pins are on either PA or PB for each serial port */ | |
841 | #define CONTROL_PINS_PORT_NOT_USED(line) \ | |
842 | &dummy_ser[line], &dummy_ser[line], \ | |
843 | DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK | |
844 | ||
845 | ||
846 | struct control_pins | |
847 | { | |
848 | volatile unsigned char *port; | |
849 | unsigned char *shadow; | |
850 | ||
851 | unsigned char dtr_mask; | |
852 | unsigned char ri_mask; | |
853 | unsigned char dsr_mask; | |
854 | unsigned char cd_mask; | |
855 | }; | |
856 | ||
857 | #define dtr_port port | |
858 | #define dtr_shadow shadow | |
859 | #define ri_port port | |
860 | #define ri_shadow shadow | |
861 | #define dsr_port port | |
862 | #define dsr_shadow shadow | |
863 | #define cd_port port | |
864 | #define cd_shadow shadow | |
865 | ||
866 | static const struct control_pins e100_modem_pins[NR_PORTS] = | |
867 | { | |
868 | /* Ser 0 */ | |
869 | { | |
870 | #ifdef CONFIG_ETRAX_SERIAL_PORT0 | |
871 | E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR), | |
872 | E100_STRUCT_MASK(0,DTR), | |
873 | E100_STRUCT_MASK(0,RI), | |
874 | E100_STRUCT_MASK(0,DSR), | |
875 | E100_STRUCT_MASK(0,CD) | |
876 | #else | |
877 | CONTROL_PINS_PORT_NOT_USED(0) | |
878 | #endif | |
879 | }, | |
880 | ||
881 | /* Ser 1 */ | |
882 | { | |
883 | #ifdef CONFIG_ETRAX_SERIAL_PORT1 | |
884 | E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR), | |
885 | E100_STRUCT_MASK(1,DTR), | |
886 | E100_STRUCT_MASK(1,RI), | |
887 | E100_STRUCT_MASK(1,DSR), | |
888 | E100_STRUCT_MASK(1,CD) | |
889 | #else | |
890 | CONTROL_PINS_PORT_NOT_USED(1) | |
891 | #endif | |
892 | }, | |
893 | ||
894 | /* Ser 2 */ | |
895 | { | |
896 | #ifdef CONFIG_ETRAX_SERIAL_PORT2 | |
897 | E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR), | |
898 | E100_STRUCT_MASK(2,DTR), | |
899 | E100_STRUCT_MASK(2,RI), | |
900 | E100_STRUCT_MASK(2,DSR), | |
901 | E100_STRUCT_MASK(2,CD) | |
902 | #else | |
903 | CONTROL_PINS_PORT_NOT_USED(2) | |
904 | #endif | |
905 | }, | |
906 | ||
907 | /* Ser 3 */ | |
908 | { | |
909 | #ifdef CONFIG_ETRAX_SERIAL_PORT3 | |
910 | E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR), | |
911 | E100_STRUCT_MASK(3,DTR), | |
912 | E100_STRUCT_MASK(3,RI), | |
913 | E100_STRUCT_MASK(3,DSR), | |
914 | E100_STRUCT_MASK(3,CD) | |
915 | #else | |
916 | CONTROL_PINS_PORT_NOT_USED(3) | |
917 | #endif | |
918 | } | |
919 | }; | |
920 | #endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */ | |
921 | ||
922 | #define E100_RTS_MASK 0x20 | |
923 | #define E100_CTS_MASK 0x40 | |
924 | ||
925 | /* All serial port signals are active low: | |
926 | * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level | |
927 | * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level | |
928 | * | |
929 | * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip | |
930 | */ | |
931 | ||
932 | /* Output */ | |
933 | #define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK) | |
934 | /* Input */ | |
d7283353 | 935 | #define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK) |
1da177e4 LT |
936 | |
937 | /* These are typically PA or PB and 0 means 0V, 1 means 3.3V */ | |
938 | /* Is an output */ | |
939 | #define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask) | |
940 | ||
941 | /* Normally inputs */ | |
942 | #define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask) | |
943 | #define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask) | |
944 | ||
945 | /* Input */ | |
946 | #define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask) | |
947 | ||
1da177e4 LT |
948 | /* Calculate the chartime depending on baudrate, numbor of bits etc. */ |
949 | static void update_char_time(struct e100_serial * info) | |
950 | { | |
adc8d746 | 951 | tcflag_t cflags = info->port.tty->termios.c_cflag; |
1da177e4 LT |
952 | int bits; |
953 | ||
954 | /* calc. number of bits / data byte */ | |
955 | /* databits + startbit and 1 stopbit */ | |
956 | if ((cflags & CSIZE) == CS7) | |
957 | bits = 9; | |
958 | else | |
959 | bits = 10; | |
960 | ||
961 | if (cflags & CSTOPB) /* 2 stopbits ? */ | |
962 | bits++; | |
963 | ||
964 | if (cflags & PARENB) /* parity bit ? */ | |
965 | bits++; | |
966 | ||
967 | /* calc timeout */ | |
968 | info->char_time_usec = ((bits * 1000000) / info->baud) + 1; | |
969 | info->flush_time_usec = 4*info->char_time_usec; | |
970 | if (info->flush_time_usec < MIN_FLUSH_TIME_USEC) | |
971 | info->flush_time_usec = MIN_FLUSH_TIME_USEC; | |
972 | ||
973 | } | |
974 | ||
975 | /* | |
976 | * This function maps from the Bxxxx defines in asm/termbits.h into real | |
977 | * baud rates. | |
978 | */ | |
979 | ||
980 | static int | |
981 | cflag_to_baud(unsigned int cflag) | |
982 | { | |
983 | static int baud_table[] = { | |
984 | 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, | |
985 | 4800, 9600, 19200, 38400 }; | |
986 | ||
987 | static int ext_baud_table[] = { | |
988 | 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000, | |
989 | 0, 0, 0, 0, 0, 0, 0, 0 }; | |
990 | ||
991 | if (cflag & CBAUDEX) | |
992 | return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX]; | |
993 | else | |
994 | return baud_table[cflag & CBAUD]; | |
995 | } | |
996 | ||
997 | /* and this maps to an etrax100 hardware baud constant */ | |
998 | ||
999 | static unsigned char | |
1000 | cflag_to_etrax_baud(unsigned int cflag) | |
1001 | { | |
1002 | char retval; | |
1003 | ||
1004 | static char baud_table[] = { | |
1005 | -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 }; | |
1006 | ||
1007 | static char ext_baud_table[] = { | |
1008 | -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 }; | |
1009 | ||
1010 | if (cflag & CBAUDEX) | |
1011 | retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX]; | |
1012 | else | |
1013 | retval = baud_table[cflag & CBAUD]; | |
1014 | ||
1015 | if (retval < 0) { | |
1016 | printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag); | |
1017 | retval = 5; /* choose default 9600 instead */ | |
1018 | } | |
1019 | ||
1020 | return retval | (retval << 4); /* choose same for both TX and RX */ | |
1021 | } | |
1022 | ||
1023 | ||
1024 | /* Various static support functions */ | |
1025 | ||
1026 | /* Functions to set or clear DTR/RTS on the requested line */ | |
1027 | /* It is complicated by the fact that RTS is a serial port register, while | |
1028 | * DTR might not be implemented in the HW at all, and if it is, it can be on | |
1029 | * any general port. | |
1030 | */ | |
1031 | ||
1032 | ||
1033 | static inline void | |
1034 | e100_dtr(struct e100_serial *info, int set) | |
1035 | { | |
1da177e4 LT |
1036 | unsigned char mask = e100_modem_pins[info->line].dtr_mask; |
1037 | ||
1038 | #ifdef SERIAL_DEBUG_IO | |
1039 | printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask); | |
1040 | printk("ser%i shadow before 0x%02X get: %i\n", | |
1041 | info->line, *e100_modem_pins[info->line].dtr_shadow, | |
1042 | E100_DTR_GET(info)); | |
1043 | #endif | |
1044 | /* DTR is active low */ | |
1045 | { | |
1046 | unsigned long flags; | |
1047 | ||
77accbf5 | 1048 | local_irq_save(flags); |
1da177e4 LT |
1049 | *e100_modem_pins[info->line].dtr_shadow &= ~mask; |
1050 | *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask); | |
1051 | *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow; | |
77accbf5 | 1052 | local_irq_restore(flags); |
1da177e4 LT |
1053 | } |
1054 | ||
1055 | #ifdef SERIAL_DEBUG_IO | |
1056 | printk("ser%i shadow after 0x%02X get: %i\n", | |
1057 | info->line, *e100_modem_pins[info->line].dtr_shadow, | |
1058 | E100_DTR_GET(info)); | |
1059 | #endif | |
1da177e4 LT |
1060 | } |
1061 | ||
1062 | /* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive | |
1063 | * 0=0V , 1=3.3V | |
1064 | */ | |
1065 | static inline void | |
1066 | e100_rts(struct e100_serial *info, int set) | |
1067 | { | |
1da177e4 | 1068 | unsigned long flags; |
77accbf5 | 1069 | local_irq_save(flags); |
1da177e4 LT |
1070 | info->rx_ctrl &= ~E100_RTS_MASK; |
1071 | info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */ | |
d7283353 | 1072 | info->ioport[REG_REC_CTRL] = info->rx_ctrl; |
77accbf5 | 1073 | local_irq_restore(flags); |
1da177e4 LT |
1074 | #ifdef SERIAL_DEBUG_IO |
1075 | printk("ser%i rts %i\n", info->line, set); | |
1076 | #endif | |
1da177e4 LT |
1077 | } |
1078 | ||
1079 | ||
1080 | /* If this behaves as a modem, RI and CD is an output */ | |
1081 | static inline void | |
1082 | e100_ri_out(struct e100_serial *info, int set) | |
1083 | { | |
1da177e4 LT |
1084 | /* RI is active low */ |
1085 | { | |
1086 | unsigned char mask = e100_modem_pins[info->line].ri_mask; | |
1087 | unsigned long flags; | |
1088 | ||
77accbf5 | 1089 | local_irq_save(flags); |
1da177e4 LT |
1090 | *e100_modem_pins[info->line].ri_shadow &= ~mask; |
1091 | *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask); | |
1092 | *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow; | |
77accbf5 | 1093 | local_irq_restore(flags); |
1da177e4 | 1094 | } |
1da177e4 LT |
1095 | } |
1096 | static inline void | |
1097 | e100_cd_out(struct e100_serial *info, int set) | |
1098 | { | |
1da177e4 LT |
1099 | /* CD is active low */ |
1100 | { | |
1101 | unsigned char mask = e100_modem_pins[info->line].cd_mask; | |
1102 | unsigned long flags; | |
1103 | ||
77accbf5 | 1104 | local_irq_save(flags); |
1da177e4 LT |
1105 | *e100_modem_pins[info->line].cd_shadow &= ~mask; |
1106 | *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask); | |
1107 | *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow; | |
77accbf5 | 1108 | local_irq_restore(flags); |
1da177e4 | 1109 | } |
1da177e4 LT |
1110 | } |
1111 | ||
1112 | static inline void | |
1113 | e100_disable_rx(struct e100_serial *info) | |
1114 | { | |
1da177e4 | 1115 | /* disable the receiver */ |
d7283353 | 1116 | info->ioport[REG_REC_CTRL] = |
1da177e4 | 1117 | (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable)); |
1da177e4 LT |
1118 | } |
1119 | ||
1120 | static inline void | |
1121 | e100_enable_rx(struct e100_serial *info) | |
1122 | { | |
1da177e4 | 1123 | /* enable the receiver */ |
d7283353 | 1124 | info->ioport[REG_REC_CTRL] = |
1da177e4 | 1125 | (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable)); |
1da177e4 LT |
1126 | } |
1127 | ||
1128 | /* the rx DMA uses both the dma_descr and the dma_eop interrupts */ | |
1129 | ||
1130 | static inline void | |
1131 | e100_disable_rxdma_irq(struct e100_serial *info) | |
1132 | { | |
1133 | #ifdef SERIAL_DEBUG_INTR | |
1134 | printk("rxdma_irq(%d): 0\n",info->line); | |
1135 | #endif | |
1136 | DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line)); | |
1137 | *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3); | |
1138 | } | |
1139 | ||
1140 | static inline void | |
1141 | e100_enable_rxdma_irq(struct e100_serial *info) | |
1142 | { | |
1143 | #ifdef SERIAL_DEBUG_INTR | |
1144 | printk("rxdma_irq(%d): 1\n",info->line); | |
1145 | #endif | |
1146 | DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line)); | |
1147 | *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3); | |
1148 | } | |
1149 | ||
1150 | /* the tx DMA uses only dma_descr interrupt */ | |
1151 | ||
41c28ff1 | 1152 | static void e100_disable_txdma_irq(struct e100_serial *info) |
1da177e4 LT |
1153 | { |
1154 | #ifdef SERIAL_DEBUG_INTR | |
1155 | printk("txdma_irq(%d): 0\n",info->line); | |
1156 | #endif | |
1157 | DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line)); | |
1158 | *R_IRQ_MASK2_CLR = info->irq; | |
1159 | } | |
1160 | ||
41c28ff1 | 1161 | static void e100_enable_txdma_irq(struct e100_serial *info) |
1da177e4 LT |
1162 | { |
1163 | #ifdef SERIAL_DEBUG_INTR | |
1164 | printk("txdma_irq(%d): 1\n",info->line); | |
1165 | #endif | |
1166 | DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line)); | |
1167 | *R_IRQ_MASK2_SET = info->irq; | |
1168 | } | |
1169 | ||
41c28ff1 | 1170 | static void e100_disable_txdma_channel(struct e100_serial *info) |
1da177e4 LT |
1171 | { |
1172 | unsigned long flags; | |
1173 | ||
1174 | /* Disable output DMA channel for the serial port in question | |
025dfdaf | 1175 | * ( set to something other than serialX) |
1da177e4 | 1176 | */ |
77accbf5 | 1177 | local_irq_save(flags); |
1da177e4 LT |
1178 | DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line)); |
1179 | if (info->line == 0) { | |
1180 | if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) == | |
1181 | IO_STATE(R_GEN_CONFIG, dma6, serial0)) { | |
1182 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6); | |
1183 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused); | |
1184 | } | |
1185 | } else if (info->line == 1) { | |
1186 | if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) == | |
1187 | IO_STATE(R_GEN_CONFIG, dma8, serial1)) { | |
1188 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8); | |
1189 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb); | |
1190 | } | |
1191 | } else if (info->line == 2) { | |
1192 | if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) == | |
1193 | IO_STATE(R_GEN_CONFIG, dma2, serial2)) { | |
1194 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2); | |
1195 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0); | |
1196 | } | |
1197 | } else if (info->line == 3) { | |
1198 | if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) == | |
1199 | IO_STATE(R_GEN_CONFIG, dma4, serial3)) { | |
1200 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4); | |
1201 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1); | |
1202 | } | |
1203 | } | |
1204 | *R_GEN_CONFIG = genconfig_shadow; | |
77accbf5 | 1205 | local_irq_restore(flags); |
1da177e4 LT |
1206 | } |
1207 | ||
1208 | ||
41c28ff1 | 1209 | static void e100_enable_txdma_channel(struct e100_serial *info) |
1da177e4 LT |
1210 | { |
1211 | unsigned long flags; | |
1212 | ||
77accbf5 | 1213 | local_irq_save(flags); |
1da177e4 LT |
1214 | DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line)); |
1215 | /* Enable output DMA channel for the serial port in question */ | |
1216 | if (info->line == 0) { | |
1217 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6); | |
1218 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0); | |
1219 | } else if (info->line == 1) { | |
1220 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8); | |
1221 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1); | |
1222 | } else if (info->line == 2) { | |
1223 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2); | |
1224 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2); | |
1225 | } else if (info->line == 3) { | |
1226 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4); | |
1227 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3); | |
1228 | } | |
1229 | *R_GEN_CONFIG = genconfig_shadow; | |
77accbf5 | 1230 | local_irq_restore(flags); |
1da177e4 LT |
1231 | } |
1232 | ||
41c28ff1 | 1233 | static void e100_disable_rxdma_channel(struct e100_serial *info) |
1da177e4 LT |
1234 | { |
1235 | unsigned long flags; | |
1236 | ||
1237 | /* Disable input DMA channel for the serial port in question | |
025dfdaf | 1238 | * ( set to something other than serialX) |
1da177e4 | 1239 | */ |
77accbf5 | 1240 | local_irq_save(flags); |
1da177e4 LT |
1241 | if (info->line == 0) { |
1242 | if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) == | |
1243 | IO_STATE(R_GEN_CONFIG, dma7, serial0)) { | |
1244 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7); | |
1245 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused); | |
1246 | } | |
1247 | } else if (info->line == 1) { | |
1248 | if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) == | |
1249 | IO_STATE(R_GEN_CONFIG, dma9, serial1)) { | |
1250 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9); | |
1251 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb); | |
1252 | } | |
1253 | } else if (info->line == 2) { | |
1254 | if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) == | |
1255 | IO_STATE(R_GEN_CONFIG, dma3, serial2)) { | |
1256 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3); | |
1257 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0); | |
1258 | } | |
1259 | } else if (info->line == 3) { | |
1260 | if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) == | |
1261 | IO_STATE(R_GEN_CONFIG, dma5, serial3)) { | |
1262 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5); | |
1263 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1); | |
1264 | } | |
1265 | } | |
1266 | *R_GEN_CONFIG = genconfig_shadow; | |
77accbf5 | 1267 | local_irq_restore(flags); |
1da177e4 LT |
1268 | } |
1269 | ||
1270 | ||
41c28ff1 | 1271 | static void e100_enable_rxdma_channel(struct e100_serial *info) |
1da177e4 LT |
1272 | { |
1273 | unsigned long flags; | |
1274 | ||
77accbf5 | 1275 | local_irq_save(flags); |
1da177e4 LT |
1276 | /* Enable input DMA channel for the serial port in question */ |
1277 | if (info->line == 0) { | |
1278 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7); | |
1279 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0); | |
1280 | } else if (info->line == 1) { | |
1281 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9); | |
1282 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1); | |
1283 | } else if (info->line == 2) { | |
1284 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3); | |
1285 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2); | |
1286 | } else if (info->line == 3) { | |
1287 | genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5); | |
1288 | genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3); | |
1289 | } | |
1290 | *R_GEN_CONFIG = genconfig_shadow; | |
77accbf5 | 1291 | local_irq_restore(flags); |
1da177e4 LT |
1292 | } |
1293 | ||
1294 | #ifdef SERIAL_HANDLE_EARLY_ERRORS | |
1295 | /* in order to detect and fix errors on the first byte | |
1296 | we have to use the serial interrupts as well. */ | |
1297 | ||
1298 | static inline void | |
1299 | e100_disable_serial_data_irq(struct e100_serial *info) | |
1300 | { | |
1301 | #ifdef SERIAL_DEBUG_INTR | |
1302 | printk("ser_irq(%d): 0\n",info->line); | |
1303 | #endif | |
1304 | DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line)); | |
1305 | *R_IRQ_MASK1_CLR = (1U << (8+2*info->line)); | |
1306 | } | |
1307 | ||
1308 | static inline void | |
1309 | e100_enable_serial_data_irq(struct e100_serial *info) | |
1310 | { | |
1311 | #ifdef SERIAL_DEBUG_INTR | |
1312 | printk("ser_irq(%d): 1\n",info->line); | |
1313 | printk("**** %d = %d\n", | |
1314 | (8+2*info->line), | |
1315 | (1U << (8+2*info->line))); | |
1316 | #endif | |
1317 | DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line)); | |
1318 | *R_IRQ_MASK1_SET = (1U << (8+2*info->line)); | |
1319 | } | |
1320 | #endif | |
1321 | ||
1322 | static inline void | |
1323 | e100_disable_serial_tx_ready_irq(struct e100_serial *info) | |
1324 | { | |
1325 | #ifdef SERIAL_DEBUG_INTR | |
1326 | printk("ser_tx_irq(%d): 0\n",info->line); | |
1327 | #endif | |
1328 | DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line)); | |
1329 | *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line)); | |
1330 | } | |
1331 | ||
1332 | static inline void | |
1333 | e100_enable_serial_tx_ready_irq(struct e100_serial *info) | |
1334 | { | |
1335 | #ifdef SERIAL_DEBUG_INTR | |
1336 | printk("ser_tx_irq(%d): 1\n",info->line); | |
1337 | printk("**** %d = %d\n", | |
1338 | (8+1+2*info->line), | |
1339 | (1U << (8+1+2*info->line))); | |
1340 | #endif | |
1341 | DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line)); | |
1342 | *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line)); | |
1343 | } | |
1344 | ||
1345 | static inline void e100_enable_rx_irq(struct e100_serial *info) | |
1346 | { | |
1347 | if (info->uses_dma_in) | |
1348 | e100_enable_rxdma_irq(info); | |
1349 | else | |
1350 | e100_enable_serial_data_irq(info); | |
1351 | } | |
1352 | static inline void e100_disable_rx_irq(struct e100_serial *info) | |
1353 | { | |
1354 | if (info->uses_dma_in) | |
1355 | e100_disable_rxdma_irq(info); | |
1356 | else | |
1357 | e100_disable_serial_data_irq(info); | |
1358 | } | |
1359 | ||
1360 | #if defined(CONFIG_ETRAX_RS485) | |
1361 | /* Enable RS-485 mode on selected port. This is UGLY. */ | |
1362 | static int | |
6fd1af4c | 1363 | e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r) |
1da177e4 LT |
1364 | { |
1365 | struct e100_serial * info = (struct e100_serial *)tty->driver_data; | |
1366 | ||
1367 | #if defined(CONFIG_ETRAX_RS485_ON_PA) | |
1368 | *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit); | |
1369 | #endif | |
1370 | #if defined(CONFIG_ETRAX_RS485_ON_PORT_G) | |
1371 | REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, | |
1372 | rs485_port_g_bit, 1); | |
1373 | #endif | |
1374 | #if defined(CONFIG_ETRAX_RS485_LTC1387) | |
1375 | REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, | |
1376 | CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1); | |
1377 | REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, | |
1378 | CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1); | |
1379 | #endif | |
1380 | ||
c7213fc4 JN |
1381 | info->rs485 = *r; |
1382 | ||
1383 | /* Maximum delay before RTS equal to 1000 */ | |
1384 | if (info->rs485.delay_rts_before_send >= 1000) | |
1da177e4 | 1385 | info->rs485.delay_rts_before_send = 1000; |
c7213fc4 | 1386 | |
1da177e4 LT |
1387 | /* printk("rts: on send = %i, after = %i, enabled = %i", |
1388 | info->rs485.rts_on_send, | |
1389 | info->rs485.rts_after_sent, | |
1390 | info->rs485.enabled | |
1391 | ); | |
1392 | */ | |
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | static int | |
77accbf5 | 1397 | e100_write_rs485(struct tty_struct *tty, |
1da177e4 LT |
1398 | const unsigned char *buf, int count) |
1399 | { | |
1400 | struct e100_serial * info = (struct e100_serial *)tty->driver_data; | |
6fd1af4c | 1401 | int old_value = (info->rs485.flags) & SER_RS485_ENABLED; |
1da177e4 LT |
1402 | |
1403 | /* rs485 is always implicitly enabled if we're using the ioctl() | |
6fd1af4c | 1404 | * but it doesn't have to be set in the serial_rs485 |
1da177e4 LT |
1405 | * (to be backward compatible with old apps) |
1406 | * So we store, set and restore it. | |
1407 | */ | |
6fd1af4c | 1408 | info->rs485.flags |= SER_RS485_ENABLED; |
1da177e4 | 1409 | /* rs_write now deals with RS485 if enabled */ |
77accbf5 | 1410 | count = rs_write(tty, buf, count); |
6fd1af4c CS |
1411 | if (!old_value) |
1412 | info->rs485.flags &= ~(SER_RS485_ENABLED); | |
1da177e4 LT |
1413 | return count; |
1414 | } | |
1415 | ||
1416 | #ifdef CONFIG_ETRAX_FAST_TIMER | |
1417 | /* Timer function to toggle RTS when using FAST_TIMER */ | |
1418 | static void rs485_toggle_rts_timer_function(unsigned long data) | |
1419 | { | |
1420 | struct e100_serial *info = (struct e100_serial *)data; | |
1421 | ||
1422 | fast_timers_rs485[info->line].function = NULL; | |
6fd1af4c | 1423 | e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND)); |
1da177e4 LT |
1424 | #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER) |
1425 | e100_enable_rx(info); | |
1426 | e100_enable_rx_irq(info); | |
1427 | #endif | |
1428 | } | |
1429 | #endif | |
1430 | #endif /* CONFIG_ETRAX_RS485 */ | |
1431 | ||
1432 | /* | |
1433 | * ------------------------------------------------------------ | |
1434 | * rs_stop() and rs_start() | |
1435 | * | |
1436 | * This routines are called before setting or resetting tty->stopped. | |
1437 | * They enable or disable transmitter using the XOFF registers, as necessary. | |
1438 | * ------------------------------------------------------------ | |
1439 | */ | |
1440 | ||
1441 | static void | |
1442 | rs_stop(struct tty_struct *tty) | |
1443 | { | |
1444 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
1445 | if (info) { | |
1446 | unsigned long flags; | |
1447 | unsigned long xoff; | |
1448 | ||
77accbf5 | 1449 | local_irq_save(flags); |
1da177e4 LT |
1450 | DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n", |
1451 | CIRC_CNT(info->xmit.head, | |
1452 | info->xmit.tail,SERIAL_XMIT_SIZE))); | |
1453 | ||
a88487c7 TI |
1454 | xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, |
1455 | STOP_CHAR(info->port.tty)); | |
1da177e4 | 1456 | xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop); |
adc8d746 | 1457 | if (tty->termios.c_iflag & IXON ) { |
1da177e4 LT |
1458 | xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable); |
1459 | } | |
1460 | ||
d7283353 | 1461 | *((unsigned long *)&info->ioport[REG_XOFF]) = xoff; |
77accbf5 | 1462 | local_irq_restore(flags); |
1da177e4 LT |
1463 | } |
1464 | } | |
1465 | ||
1466 | static void | |
1467 | rs_start(struct tty_struct *tty) | |
1468 | { | |
1469 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
1470 | if (info) { | |
1471 | unsigned long flags; | |
1472 | unsigned long xoff; | |
1473 | ||
77accbf5 | 1474 | local_irq_save(flags); |
1da177e4 LT |
1475 | DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n", |
1476 | CIRC_CNT(info->xmit.head, | |
1477 | info->xmit.tail,SERIAL_XMIT_SIZE))); | |
1478 | xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty)); | |
1479 | xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable); | |
adc8d746 | 1480 | if (tty->termios.c_iflag & IXON ) { |
1da177e4 LT |
1481 | xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable); |
1482 | } | |
1483 | ||
d7283353 | 1484 | *((unsigned long *)&info->ioport[REG_XOFF]) = xoff; |
1da177e4 LT |
1485 | if (!info->uses_dma_out && |
1486 | info->xmit.head != info->xmit.tail && info->xmit.buf) | |
1487 | e100_enable_serial_tx_ready_irq(info); | |
1488 | ||
77accbf5 | 1489 | local_irq_restore(flags); |
1da177e4 LT |
1490 | } |
1491 | } | |
1492 | ||
1493 | /* | |
1494 | * ---------------------------------------------------------------------- | |
1495 | * | |
1496 | * Here starts the interrupt handling routines. All of the following | |
1497 | * subroutines are declared as inline and are folded into | |
1498 | * rs_interrupt(). They were separated out for readability's sake. | |
1499 | * | |
1500 | * Note: rs_interrupt() is a "fast" interrupt, which means that it | |
1501 | * runs with interrupts turned off. People who may want to modify | |
1502 | * rs_interrupt() should try to keep the interrupt handler as fast as | |
1503 | * possible. After you are done making modifications, it is not a bad | |
1504 | * idea to do: | |
1505 | * | |
1506 | * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c | |
1507 | * | |
1508 | * and look at the resulting assemble code in serial.s. | |
1509 | * | |
1510 | * - Ted Ts'o (tytso@mit.edu), 7-Mar-93 | |
1511 | * ----------------------------------------------------------------------- | |
1512 | */ | |
1513 | ||
1514 | /* | |
1515 | * This routine is used by the interrupt handler to schedule | |
1516 | * processing in the software interrupt portion of the driver. | |
1517 | */ | |
41c28ff1 | 1518 | static void rs_sched_event(struct e100_serial *info, int event) |
1da177e4 LT |
1519 | { |
1520 | if (info->event & (1 << event)) | |
1521 | return; | |
1522 | info->event |= 1 << event; | |
1523 | schedule_work(&info->work); | |
1524 | } | |
1525 | ||
1526 | /* The output DMA channel is free - use it to send as many chars as possible | |
1527 | * NOTES: | |
1528 | * We don't pay attention to info->x_char, which means if the TTY wants to | |
1529 | * use XON/XOFF it will set info->x_char but we won't send any X char! | |
1530 | * | |
1531 | * To implement this, we'd just start a DMA send of 1 byte pointing at a | |
1532 | * buffer containing the X char, and skip updating xmit. We'd also have to | |
1533 | * check if the last sent char was the X char when we enter this function | |
1534 | * the next time, to avoid updating xmit with the sent X value. | |
1535 | */ | |
1536 | ||
1537 | static void | |
1538 | transmit_chars_dma(struct e100_serial *info) | |
1539 | { | |
1540 | unsigned int c, sentl; | |
1541 | struct etrax_dma_descr *descr; | |
1542 | ||
1da177e4 LT |
1543 | /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */ |
1544 | *info->oclrintradr = | |
1545 | IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) | | |
1546 | IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); | |
1547 | ||
1548 | #ifdef SERIAL_DEBUG_INTR | |
1549 | if (info->line == SERIAL_DEBUG_LINE) | |
1550 | printk("tc\n"); | |
1551 | #endif | |
1552 | if (!info->tr_running) { | |
1553 | /* weirdo... we shouldn't get here! */ | |
1554 | printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n"); | |
1555 | return; | |
1556 | } | |
1557 | ||
1558 | descr = &info->tr_descr; | |
1559 | ||
1560 | /* first get the amount of bytes sent during the last DMA transfer, | |
1561 | and update xmit accordingly */ | |
1562 | ||
1563 | /* if the stop bit was not set, all data has been sent */ | |
1564 | if (!(descr->status & d_stop)) { | |
1565 | sentl = descr->sw_len; | |
1566 | } else | |
1567 | /* otherwise we find the amount of data sent here */ | |
1568 | sentl = descr->hw_len; | |
1569 | ||
1570 | DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl)); | |
1571 | ||
1572 | /* update stats */ | |
1573 | info->icount.tx += sentl; | |
1574 | ||
1575 | /* update xmit buffer */ | |
1576 | info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1); | |
1577 | ||
1578 | /* if there is only a few chars left in the buf, wake up the blocked | |
1579 | write if any */ | |
1580 | if (CIRC_CNT(info->xmit.head, | |
1581 | info->xmit.tail, | |
1582 | SERIAL_XMIT_SIZE) < WAKEUP_CHARS) | |
1583 | rs_sched_event(info, RS_EVENT_WRITE_WAKEUP); | |
1584 | ||
1585 | /* find out the largest amount of consecutive bytes we want to send now */ | |
1586 | ||
1587 | c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); | |
1588 | ||
1589 | /* Don't send all in one DMA transfer - divide it so we wake up | |
1590 | * application before all is sent | |
1591 | */ | |
1592 | ||
1593 | if (c >= 4*WAKEUP_CHARS) | |
1594 | c = c/2; | |
1595 | ||
1596 | if (c <= 0) { | |
1597 | /* our job here is done, don't schedule any new DMA transfer */ | |
1598 | info->tr_running = 0; | |
1599 | ||
1600 | #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER) | |
6fd1af4c | 1601 | if (info->rs485.flags & SER_RS485_ENABLED) { |
1da177e4 LT |
1602 | /* Set a short timer to toggle RTS */ |
1603 | start_one_shot_timer(&fast_timers_rs485[info->line], | |
1604 | rs485_toggle_rts_timer_function, | |
1605 | (unsigned long)info, | |
1606 | info->char_time_usec*2, | |
1607 | "RS-485"); | |
1608 | } | |
1609 | #endif /* RS485 */ | |
1610 | return; | |
1611 | } | |
1612 | ||
1613 | /* ok we can schedule a dma send of c chars starting at info->xmit.tail */ | |
1614 | /* set up the descriptor correctly for output */ | |
1615 | DFLOW(DEBUG_LOG(info->line, "TX %i\n", c)); | |
1616 | descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */ | |
1617 | descr->sw_len = c; | |
1618 | descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail); | |
1619 | descr->status = 0; | |
1620 | ||
1621 | *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */ | |
1622 | *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start); | |
1623 | ||
1624 | /* DMA is now running (hopefully) */ | |
1625 | } /* transmit_chars_dma */ | |
1626 | ||
1627 | static void | |
1628 | start_transmit(struct e100_serial *info) | |
1629 | { | |
1630 | #if 0 | |
1631 | if (info->line == SERIAL_DEBUG_LINE) | |
1632 | printk("x\n"); | |
1633 | #endif | |
1634 | ||
1635 | info->tr_descr.sw_len = 0; | |
1636 | info->tr_descr.hw_len = 0; | |
1637 | info->tr_descr.status = 0; | |
1638 | info->tr_running = 1; | |
1639 | if (info->uses_dma_out) | |
1640 | transmit_chars_dma(info); | |
1641 | else | |
1642 | e100_enable_serial_tx_ready_irq(info); | |
1643 | } /* start_transmit */ | |
1644 | ||
1645 | #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER | |
1646 | static int serial_fast_timer_started = 0; | |
1647 | static int serial_fast_timer_expired = 0; | |
1648 | static void flush_timeout_function(unsigned long data); | |
1649 | #define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\ | |
1650 | unsigned long timer_flags; \ | |
77accbf5 | 1651 | local_irq_save(timer_flags); \ |
1da177e4 LT |
1652 | if (fast_timers[info->line].function == NULL) { \ |
1653 | serial_fast_timer_started++; \ | |
1654 | TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \ | |
1655 | TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \ | |
1656 | start_one_shot_timer(&fast_timers[info->line], \ | |
1657 | flush_timeout_function, \ | |
1658 | (unsigned long)info, \ | |
1659 | (usec), \ | |
1660 | string); \ | |
1661 | } \ | |
1662 | else { \ | |
1663 | TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \ | |
1664 | } \ | |
77accbf5 | 1665 | local_irq_restore(timer_flags); \ |
1da177e4 LT |
1666 | } |
1667 | #define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec) | |
1668 | ||
1669 | #else | |
1670 | #define START_FLUSH_FAST_TIMER_TIME(info, string, usec) | |
1671 | #define START_FLUSH_FAST_TIMER(info, string) | |
1672 | #endif | |
1673 | ||
1674 | static struct etrax_recv_buffer * | |
1675 | alloc_recv_buffer(unsigned int size) | |
1676 | { | |
1677 | struct etrax_recv_buffer *buffer; | |
1678 | ||
1679 | if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC))) | |
1680 | return NULL; | |
1681 | ||
1682 | buffer->next = NULL; | |
1683 | buffer->length = 0; | |
1684 | buffer->error = TTY_NORMAL; | |
1685 | ||
1686 | return buffer; | |
1687 | } | |
1688 | ||
1689 | static void | |
1690 | append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer) | |
1691 | { | |
1692 | unsigned long flags; | |
1693 | ||
77accbf5 | 1694 | local_irq_save(flags); |
1da177e4 LT |
1695 | |
1696 | if (!info->first_recv_buffer) | |
1697 | info->first_recv_buffer = buffer; | |
1698 | else | |
1699 | info->last_recv_buffer->next = buffer; | |
1700 | ||
1701 | info->last_recv_buffer = buffer; | |
1702 | ||
1703 | info->recv_cnt += buffer->length; | |
1704 | if (info->recv_cnt > info->max_recv_cnt) | |
1705 | info->max_recv_cnt = info->recv_cnt; | |
1706 | ||
77accbf5 | 1707 | local_irq_restore(flags); |
1da177e4 LT |
1708 | } |
1709 | ||
1710 | static int | |
1711 | add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag) | |
1712 | { | |
1713 | struct etrax_recv_buffer *buffer; | |
1714 | if (info->uses_dma_in) { | |
1715 | if (!(buffer = alloc_recv_buffer(4))) | |
1716 | return 0; | |
1717 | ||
1718 | buffer->length = 1; | |
1719 | buffer->error = flag; | |
1720 | buffer->buffer[0] = data; | |
1721 | ||
1722 | append_recv_buffer(info, buffer); | |
1723 | ||
1724 | info->icount.rx++; | |
1725 | } else { | |
92a19f9c | 1726 | tty_insert_flip_char(&info->port, data, flag); |
1da177e4 LT |
1727 | info->icount.rx++; |
1728 | } | |
1729 | ||
1730 | return 1; | |
1731 | } | |
1732 | ||
41c28ff1 AB |
1733 | static unsigned int handle_descr_data(struct e100_serial *info, |
1734 | struct etrax_dma_descr *descr, | |
1735 | unsigned int recvl) | |
1da177e4 LT |
1736 | { |
1737 | struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer; | |
1738 | ||
1739 | if (info->recv_cnt + recvl > 65536) { | |
3d43b7d5 | 1740 | printk(KERN_WARNING |
71cc2c21 | 1741 | "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl); |
1da177e4 LT |
1742 | return 0; |
1743 | } | |
1744 | ||
1745 | buffer->length = recvl; | |
1746 | ||
1747 | if (info->errorcode == ERRCODE_SET_BREAK) | |
1748 | buffer->error = TTY_BREAK; | |
1749 | info->errorcode = 0; | |
1750 | ||
1751 | append_recv_buffer(info, buffer); | |
1752 | ||
1753 | if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE))) | |
71cc2c21 | 1754 | panic("%s: Failed to allocate memory for receive buffer!\n", __func__); |
1da177e4 LT |
1755 | |
1756 | descr->buf = virt_to_phys(buffer->buffer); | |
1757 | ||
1758 | return recvl; | |
1759 | } | |
1760 | ||
41c28ff1 | 1761 | static unsigned int handle_all_descr_data(struct e100_serial *info) |
1da177e4 LT |
1762 | { |
1763 | struct etrax_dma_descr *descr; | |
1764 | unsigned int recvl; | |
1765 | unsigned int ret = 0; | |
1766 | ||
1767 | while (1) | |
1768 | { | |
1769 | descr = &info->rec_descr[info->cur_rec_descr]; | |
1770 | ||
1771 | if (descr == phys_to_virt(*info->idescradr)) | |
1772 | break; | |
1773 | ||
1774 | if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS) | |
1775 | info->cur_rec_descr = 0; | |
1776 | ||
1777 | /* find out how many bytes were read */ | |
1778 | ||
1779 | /* if the eop bit was not set, all data has been received */ | |
1780 | if (!(descr->status & d_eop)) { | |
1781 | recvl = descr->sw_len; | |
1782 | } else { | |
1783 | /* otherwise we find the amount of data received here */ | |
1784 | recvl = descr->hw_len; | |
1785 | } | |
1786 | ||
1787 | /* Reset the status information */ | |
1788 | descr->status = 0; | |
1789 | ||
1790 | DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl); | |
a88487c7 | 1791 | if (info->port.tty->stopped) { |
1da177e4 LT |
1792 | unsigned char *buf = phys_to_virt(descr->buf); |
1793 | DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]); | |
1794 | DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]); | |
1795 | DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]); | |
1796 | } | |
1797 | ); | |
1798 | ||
1799 | /* update stats */ | |
1800 | info->icount.rx += recvl; | |
1801 | ||
1802 | ret += handle_descr_data(info, descr, recvl); | |
1803 | } | |
1804 | ||
1805 | return ret; | |
1806 | } | |
1807 | ||
41c28ff1 | 1808 | static void receive_chars_dma(struct e100_serial *info) |
1da177e4 LT |
1809 | { |
1810 | struct tty_struct *tty; | |
1811 | unsigned char rstat; | |
1812 | ||
1da177e4 LT |
1813 | /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */ |
1814 | *info->iclrintradr = | |
1815 | IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) | | |
1816 | IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); | |
1817 | ||
a88487c7 | 1818 | tty = info->port.tty; |
1da177e4 LT |
1819 | if (!tty) /* Something wrong... */ |
1820 | return; | |
1821 | ||
1822 | #ifdef SERIAL_HANDLE_EARLY_ERRORS | |
1823 | if (info->uses_dma_in) | |
1824 | e100_enable_serial_data_irq(info); | |
1825 | #endif | |
1826 | ||
1827 | if (info->errorcode == ERRCODE_INSERT_BREAK) | |
1828 | add_char_and_flag(info, '\0', TTY_BREAK); | |
1829 | ||
1830 | handle_all_descr_data(info); | |
1831 | ||
1832 | /* Read the status register to detect errors */ | |
d7283353 | 1833 | rstat = info->ioport[REG_STATUS]; |
1da177e4 LT |
1834 | if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) { |
1835 | DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat)); | |
1836 | } | |
1837 | ||
1838 | if (rstat & SER_ERROR_MASK) { | |
1839 | /* If we got an error, we must reset it by reading the | |
1840 | * data_in field | |
1841 | */ | |
d7283353 | 1842 | unsigned char data = info->ioport[REG_DATA]; |
1da177e4 LT |
1843 | |
1844 | PROCSTAT(ser_stat[info->line].errors_cnt++); | |
1845 | DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n", | |
1846 | ((rstat & SER_ERROR_MASK) << 8) | data); | |
1847 | ||
1848 | if (rstat & SER_PAR_ERR_MASK) | |
1849 | add_char_and_flag(info, data, TTY_PARITY); | |
1850 | else if (rstat & SER_OVERRUN_MASK) | |
1851 | add_char_and_flag(info, data, TTY_OVERRUN); | |
1852 | else if (rstat & SER_FRAMING_ERR_MASK) | |
1853 | add_char_and_flag(info, data, TTY_FRAME); | |
1854 | } | |
1855 | ||
1856 | START_FLUSH_FAST_TIMER(info, "receive_chars"); | |
1857 | ||
1858 | /* Restart the receiving DMA */ | |
1859 | *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart); | |
1860 | } | |
1861 | ||
41c28ff1 | 1862 | static int start_recv_dma(struct e100_serial *info) |
1da177e4 LT |
1863 | { |
1864 | struct etrax_dma_descr *descr = info->rec_descr; | |
1865 | struct etrax_recv_buffer *buffer; | |
1866 | int i; | |
1867 | ||
1868 | /* Set up the receiving descriptors */ | |
1869 | for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) { | |
1870 | if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE))) | |
71cc2c21 | 1871 | panic("%s: Failed to allocate memory for receive buffer!\n", __func__); |
1da177e4 LT |
1872 | |
1873 | descr[i].ctrl = d_int; | |
1874 | descr[i].buf = virt_to_phys(buffer->buffer); | |
1875 | descr[i].sw_len = SERIAL_DESCR_BUF_SIZE; | |
1876 | descr[i].hw_len = 0; | |
1877 | descr[i].status = 0; | |
1878 | descr[i].next = virt_to_phys(&descr[i+1]); | |
1879 | } | |
1880 | ||
1881 | /* Link the last descriptor to the first */ | |
1882 | descr[i-1].next = virt_to_phys(&descr[0]); | |
1883 | ||
1884 | /* Start with the first descriptor in the list */ | |
1885 | info->cur_rec_descr = 0; | |
1886 | ||
1887 | /* Start the DMA */ | |
1888 | *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]); | |
1889 | *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start); | |
1890 | ||
1891 | /* Input DMA should be running now */ | |
1892 | return 1; | |
1893 | } | |
1894 | ||
1895 | static void | |
1896 | start_receive(struct e100_serial *info) | |
1897 | { | |
1da177e4 LT |
1898 | if (info->uses_dma_in) { |
1899 | /* reset the input dma channel to be sure it works */ | |
1900 | ||
1901 | *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); | |
1902 | while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) == | |
1903 | IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset)); | |
1904 | ||
1905 | start_recv_dma(info); | |
1906 | } | |
1907 | } | |
1908 | ||
1909 | ||
1da177e4 LT |
1910 | /* the bits in the MASK2 register are laid out like this: |
1911 | DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR | |
1912 | where I is the input channel and O is the output channel for the port. | |
1913 | info->irq is the bit number for the DMAO_DESCR so to check the others we | |
1914 | shift info->irq to the left. | |
1915 | */ | |
1916 | ||
1917 | /* dma output channel interrupt handler | |
1918 | this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or | |
1919 | DMA8(ser1) when they have finished a descriptor with the intr flag set. | |
1920 | */ | |
1921 | ||
1922 | static irqreturn_t | |
7d12e780 | 1923 | tr_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1924 | { |
1925 | struct e100_serial *info; | |
1926 | unsigned long ireg; | |
1927 | int i; | |
1928 | int handled = 0; | |
1929 | ||
1da177e4 LT |
1930 | /* find out the line that caused this irq and get it from rs_table */ |
1931 | ||
1932 | ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */ | |
1933 | ||
1934 | for (i = 0; i < NR_PORTS; i++) { | |
1935 | info = rs_table + i; | |
1936 | if (!info->enabled || !info->uses_dma_out) | |
1937 | continue; | |
1938 | /* check for dma_descr (don't need to check for dma_eop in output dma for serial */ | |
1939 | if (ireg & info->irq) { | |
1940 | handled = 1; | |
1941 | /* we can send a new dma bunch. make it so. */ | |
1942 | DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i)); | |
1943 | /* Read jiffies_usec first, | |
1944 | * we want this time to be as late as possible | |
1945 | */ | |
1946 | PROCSTAT(ser_stat[info->line].tx_dma_ints++); | |
1947 | info->last_tx_active_usec = GET_JIFFIES_USEC(); | |
1948 | info->last_tx_active = jiffies; | |
1949 | transmit_chars_dma(info); | |
1950 | } | |
1951 | ||
1952 | /* FIXME: here we should really check for a change in the | |
1953 | status lines and if so call status_handle(info) */ | |
1954 | } | |
1955 | return IRQ_RETVAL(handled); | |
1956 | } /* tr_interrupt */ | |
1957 | ||
1958 | /* dma input channel interrupt handler */ | |
1959 | ||
1960 | static irqreturn_t | |
7d12e780 | 1961 | rec_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1962 | { |
1963 | struct e100_serial *info; | |
1964 | unsigned long ireg; | |
1965 | int i; | |
1966 | int handled = 0; | |
1967 | ||
1da177e4 LT |
1968 | /* find out the line that caused this irq and get it from rs_table */ |
1969 | ||
1970 | ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */ | |
1971 | ||
1972 | for (i = 0; i < NR_PORTS; i++) { | |
1973 | info = rs_table + i; | |
1974 | if (!info->enabled || !info->uses_dma_in) | |
1975 | continue; | |
1976 | /* check for both dma_eop and dma_descr for the input dma channel */ | |
1977 | if (ireg & ((info->irq << 2) | (info->irq << 3))) { | |
1978 | handled = 1; | |
1979 | /* we have received something */ | |
1980 | receive_chars_dma(info); | |
1981 | } | |
1982 | ||
1983 | /* FIXME: here we should really check for a change in the | |
1984 | status lines and if so call status_handle(info) */ | |
1985 | } | |
1986 | return IRQ_RETVAL(handled); | |
1987 | } /* rec_interrupt */ | |
1988 | ||
41c28ff1 | 1989 | static int force_eop_if_needed(struct e100_serial *info) |
1da177e4 LT |
1990 | { |
1991 | /* We check data_avail bit to determine if data has | |
1992 | * arrived since last time | |
1993 | */ | |
d7283353 | 1994 | unsigned char rstat = info->ioport[REG_STATUS]; |
1da177e4 LT |
1995 | |
1996 | /* error or datavail? */ | |
1997 | if (rstat & SER_ERROR_MASK) { | |
1998 | /* Some error has occurred. If there has been valid data, an | |
1999 | * EOP interrupt will be made automatically. If no data, the | |
2000 | * normal ser_interrupt should be enabled and handle it. | |
2001 | * So do nothing! | |
2002 | */ | |
2003 | DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n", | |
2004 | rstat | (info->line << 8)); | |
2005 | return 0; | |
2006 | } | |
2007 | ||
2008 | if (rstat & SER_DATA_AVAIL_MASK) { | |
2009 | /* Ok data, no error, count it */ | |
2010 | TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n", | |
2011 | rstat | (info->line << 8))); | |
2012 | /* Read data to clear status flags */ | |
d7283353 | 2013 | (void)info->ioport[REG_DATA]; |
1da177e4 LT |
2014 | |
2015 | info->forced_eop = 0; | |
2016 | START_FLUSH_FAST_TIMER(info, "magic"); | |
2017 | return 0; | |
2018 | } | |
2019 | ||
2020 | /* hit the timeout, force an EOP for the input | |
2021 | * dma channel if we haven't already | |
2022 | */ | |
2023 | if (!info->forced_eop) { | |
2024 | info->forced_eop = 1; | |
2025 | PROCSTAT(ser_stat[info->line].timeout_flush_cnt++); | |
2026 | TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line)); | |
2027 | FORCE_EOP(info); | |
2028 | } | |
2029 | ||
2030 | return 1; | |
2031 | } | |
2032 | ||
41c28ff1 | 2033 | static void flush_to_flip_buffer(struct e100_serial *info) |
1da177e4 | 2034 | { |
1da177e4 | 2035 | struct etrax_recv_buffer *buffer; |
1da177e4 | 2036 | unsigned long flags; |
1da177e4 | 2037 | |
77accbf5 | 2038 | local_irq_save(flags); |
1da177e4 | 2039 | |
2090ab05 | 2040 | while ((buffer = info->first_recv_buffer) != NULL) { |
1da177e4 LT |
2041 | unsigned int count = buffer->length; |
2042 | ||
05c7cd39 | 2043 | tty_insert_flip_string(&info->port, buffer->buffer, count); |
1da177e4 | 2044 | info->recv_cnt -= count; |
1da177e4 LT |
2045 | |
2046 | if (count == buffer->length) { | |
2047 | info->first_recv_buffer = buffer->next; | |
2048 | kfree(buffer); | |
2049 | } else { | |
2050 | buffer->length -= count; | |
2051 | memmove(buffer->buffer, buffer->buffer + count, buffer->length); | |
2052 | buffer->error = TTY_NORMAL; | |
2053 | } | |
2054 | } | |
2055 | ||
2056 | if (!info->first_recv_buffer) | |
2057 | info->last_recv_buffer = NULL; | |
2058 | ||
77accbf5 | 2059 | local_irq_restore(flags); |
1da177e4 | 2060 | |
77accbf5 | 2061 | /* This includes a check for low-latency */ |
2e124b4a | 2062 | tty_flip_buffer_push(&info->port); |
1da177e4 LT |
2063 | } |
2064 | ||
41c28ff1 | 2065 | static void check_flush_timeout(struct e100_serial *info) |
1da177e4 LT |
2066 | { |
2067 | /* Flip what we've got (if we can) */ | |
2068 | flush_to_flip_buffer(info); | |
2069 | ||
2070 | /* We might need to flip later, but not to fast | |
2071 | * since the system is busy processing input... */ | |
2072 | if (info->first_recv_buffer) | |
2073 | START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000); | |
2074 | ||
2075 | /* Force eop last, since data might have come while we're processing | |
2076 | * and if we started the slow timer above, we won't start a fast | |
2077 | * below. | |
2078 | */ | |
2079 | force_eop_if_needed(info); | |
2080 | } | |
2081 | ||
2082 | #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER | |
2083 | static void flush_timeout_function(unsigned long data) | |
2084 | { | |
2085 | struct e100_serial *info = (struct e100_serial *)data; | |
2086 | ||
2087 | fast_timers[info->line].function = NULL; | |
2088 | serial_fast_timer_expired++; | |
8faaaead | 2089 | TIMERD(DEBUG_LOG(info->line, "flush_timeout %i ", info->line)); |
1da177e4 LT |
2090 | TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired)); |
2091 | check_flush_timeout(info); | |
2092 | } | |
2093 | ||
2094 | #else | |
2095 | ||
2096 | /* dma fifo/buffer timeout handler | |
2097 | forces an end-of-packet for the dma input channel if no chars | |
2098 | have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s. | |
2099 | */ | |
2100 | ||
2101 | static struct timer_list flush_timer; | |
2102 | ||
2103 | static void | |
2104 | timed_flush_handler(unsigned long ptr) | |
2105 | { | |
2106 | struct e100_serial *info; | |
2107 | int i; | |
2108 | ||
1da177e4 LT |
2109 | for (i = 0; i < NR_PORTS; i++) { |
2110 | info = rs_table + i; | |
2111 | if (info->uses_dma_in) | |
2112 | check_flush_timeout(info); | |
2113 | } | |
2114 | ||
2115 | /* restart flush timer */ | |
2116 | mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS); | |
2117 | } | |
2118 | #endif | |
2119 | ||
2120 | #ifdef SERIAL_HANDLE_EARLY_ERRORS | |
2121 | ||
2122 | /* If there is an error (ie break) when the DMA is running and | |
2123 | * there are no bytes in the fifo the DMA is stopped and we get no | |
2124 | * eop interrupt. Thus we have to monitor the first bytes on a DMA | |
2125 | * transfer, and if it is without error we can turn the serial | |
2126 | * interrupts off. | |
2127 | */ | |
2128 | ||
2129 | /* | |
2130 | BREAK handling on ETRAX 100: | |
2131 | ETRAX will generate interrupt although there is no stop bit between the | |
2132 | characters. | |
2133 | ||
2134 | Depending on how long the break sequence is, the end of the breaksequence | |
2135 | will look differently: | |
2136 | | indicates start/end of a character. | |
2137 | ||
2138 | B= Break character (0x00) with framing error. | |
2139 | E= Error byte with parity error received after B characters. | |
2140 | F= "Faked" valid byte received immediately after B characters. | |
2141 | V= Valid byte | |
2142 | ||
2143 | 1. | |
2144 | B BL ___________________________ V | |
2145 | .._|__________|__________| |valid data | | |
2146 | ||
2147 | Multiple frame errors with data == 0x00 (B), | |
2148 | the timing matches up "perfectly" so no extra ending char is detected. | |
2149 | The RXD pin is 1 in the last interrupt, in that case | |
2150 | we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really | |
2151 | know if another byte will come and this really is case 2. below | |
2152 | (e.g F=0xFF or 0xFE) | |
2153 | If RXD pin is 0 we can expect another character (see 2. below). | |
2154 | ||
2155 | ||
2156 | 2. | |
2157 | ||
2158 | B B E or F__________________..__ V | |
2159 | .._|__________|__________|______ | |valid data | |
2160 | "valid" or | |
2161 | parity error | |
2162 | ||
2163 | Multiple frame errors with data == 0x00 (B), | |
2164 | but the part of the break trigs is interpreted as a start bit (and possibly | |
2165 | some 0 bits followed by a number of 1 bits and a stop bit). | |
2166 | Depending on parity settings etc. this last character can be either | |
2167 | a fake "valid" char (F) or have a parity error (E). | |
2168 | ||
2169 | If the character is valid it will be put in the buffer, | |
2170 | we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt | |
2171 | will set the flags so the tty will handle it, | |
2172 | if it's an error byte it will not be put in the buffer | |
2173 | and we set info->errorcode = ERRCODE_INSERT_BREAK. | |
2174 | ||
2175 | To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp | |
2176 | of the last faulty char (B) and compares it with the current time: | |
2177 | If the time elapsed time is less then 2*char_time_usec we will assume | |
2178 | it's a faked F char and not a Valid char and set | |
2179 | info->errorcode = ERRCODE_SET_BREAK. | |
2180 | ||
2181 | Flaws in the above solution: | |
2182 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
2183 | We use the timer to distinguish a F character from a V character, | |
2184 | if a V character is to close after the break we might make the wrong decision. | |
2185 | ||
2186 | TODO: The break will be delayed until an F or V character is received. | |
2187 | ||
2188 | */ | |
2189 | ||
12aad550 | 2190 | static void handle_ser_rx_interrupt_no_dma(struct e100_serial *info) |
1da177e4 LT |
2191 | { |
2192 | unsigned long data_read; | |
77accbf5 | 2193 | |
1da177e4 | 2194 | /* Read data and status at the same time */ |
d7283353 | 2195 | data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]); |
1da177e4 LT |
2196 | more_data: |
2197 | if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) { | |
2198 | DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0)); | |
2199 | } | |
2200 | DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read))); | |
2201 | ||
2202 | if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) | | |
2203 | IO_MASK(R_SERIAL0_READ, par_err) | | |
2204 | IO_MASK(R_SERIAL0_READ, overrun) )) { | |
2205 | /* An error */ | |
2206 | info->last_rx_active_usec = GET_JIFFIES_USEC(); | |
2207 | info->last_rx_active = jiffies; | |
2208 | DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read)); | |
2209 | DLOG_INT_TRIG( | |
2210 | if (!log_int_trig1_pos) { | |
2211 | log_int_trig1_pos = log_int_pos; | |
2212 | log_int(rdpc(), 0, 0); | |
2213 | } | |
2214 | ); | |
2215 | ||
2216 | ||
2217 | if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) && | |
2218 | (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) { | |
2219 | /* Most likely a break, but we get interrupts over and | |
2220 | * over again. | |
2221 | */ | |
2222 | ||
2223 | if (!info->break_detected_cnt) { | |
2224 | DEBUG_LOG(info->line, "#BRK start\n", 0); | |
2225 | } | |
2226 | if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) { | |
2227 | /* The RX pin is high now, so the break | |
2228 | * must be over, but.... | |
2229 | * we can't really know if we will get another | |
2230 | * last byte ending the break or not. | |
2231 | * And we don't know if the byte (if any) will | |
2232 | * have an error or look valid. | |
2233 | */ | |
2234 | DEBUG_LOG(info->line, "# BL BRK\n", 0); | |
2235 | info->errorcode = ERRCODE_INSERT_BREAK; | |
2236 | } | |
2237 | info->break_detected_cnt++; | |
2238 | } else { | |
2239 | /* The error does not look like a break, but could be | |
2240 | * the end of one | |
2241 | */ | |
2242 | if (info->break_detected_cnt) { | |
2243 | DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt); | |
2244 | info->errorcode = ERRCODE_INSERT_BREAK; | |
2245 | } else { | |
77accbf5 JN |
2246 | unsigned char data = IO_EXTRACT(R_SERIAL0_READ, |
2247 | data_in, data_read); | |
2248 | char flag = TTY_NORMAL; | |
1da177e4 | 2249 | if (info->errorcode == ERRCODE_INSERT_BREAK) { |
92a19f9c | 2250 | tty_insert_flip_char(&info->port, 0, flag); |
1da177e4 LT |
2251 | info->icount.rx++; |
2252 | } | |
1da177e4 LT |
2253 | |
2254 | if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) { | |
2255 | info->icount.parity++; | |
77accbf5 | 2256 | flag = TTY_PARITY; |
1da177e4 LT |
2257 | } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) { |
2258 | info->icount.overrun++; | |
77accbf5 | 2259 | flag = TTY_OVERRUN; |
1da177e4 LT |
2260 | } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) { |
2261 | info->icount.frame++; | |
77accbf5 | 2262 | flag = TTY_FRAME; |
1da177e4 | 2263 | } |
92a19f9c | 2264 | tty_insert_flip_char(&info->port, data, flag); |
1da177e4 LT |
2265 | info->errorcode = 0; |
2266 | } | |
2267 | info->break_detected_cnt = 0; | |
2268 | } | |
2269 | } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) { | |
2270 | /* No error */ | |
2271 | DLOG_INT_TRIG( | |
2272 | if (!log_int_trig1_pos) { | |
2273 | if (log_int_pos >= log_int_size) { | |
2274 | log_int_pos = 0; | |
2275 | } | |
2276 | log_int_trig0_pos = log_int_pos; | |
2277 | log_int(rdpc(), 0, 0); | |
2278 | } | |
2279 | ); | |
92a19f9c | 2280 | tty_insert_flip_char(&info->port, |
77accbf5 JN |
2281 | IO_EXTRACT(R_SERIAL0_READ, data_in, data_read), |
2282 | TTY_NORMAL); | |
1da177e4 LT |
2283 | } else { |
2284 | DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read); | |
2285 | } | |
2286 | ||
2287 | ||
1da177e4 | 2288 | info->icount.rx++; |
d7283353 | 2289 | data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]); |
1da177e4 LT |
2290 | if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) { |
2291 | DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)); | |
2292 | goto more_data; | |
2293 | } | |
2294 | ||
2e124b4a | 2295 | tty_flip_buffer_push(&info->port); |
1da177e4 LT |
2296 | } |
2297 | ||
12aad550 | 2298 | static void handle_ser_rx_interrupt(struct e100_serial *info) |
1da177e4 LT |
2299 | { |
2300 | unsigned char rstat; | |
2301 | ||
2302 | #ifdef SERIAL_DEBUG_INTR | |
2303 | printk("Interrupt from serport %d\n", i); | |
2304 | #endif | |
2305 | /* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */ | |
2306 | if (!info->uses_dma_in) { | |
12aad550 JS |
2307 | handle_ser_rx_interrupt_no_dma(info); |
2308 | return; | |
1da177e4 LT |
2309 | } |
2310 | /* DMA is used */ | |
d7283353 | 2311 | rstat = info->ioport[REG_STATUS]; |
1da177e4 LT |
2312 | if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) { |
2313 | DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0)); | |
2314 | } | |
2315 | ||
2316 | if (rstat & SER_ERROR_MASK) { | |
2317 | unsigned char data; | |
2318 | ||
2319 | info->last_rx_active_usec = GET_JIFFIES_USEC(); | |
2320 | info->last_rx_active = jiffies; | |
2321 | /* If we got an error, we must reset it by reading the | |
2322 | * data_in field | |
2323 | */ | |
d7283353 | 2324 | data = info->ioport[REG_DATA]; |
1da177e4 LT |
2325 | DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data)); |
2326 | DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat)); | |
2327 | if (!data && (rstat & SER_FRAMING_ERR_MASK)) { | |
2328 | /* Most likely a break, but we get interrupts over and | |
2329 | * over again. | |
2330 | */ | |
2331 | ||
2332 | if (!info->break_detected_cnt) { | |
2333 | DEBUG_LOG(info->line, "#BRK start\n", 0); | |
2334 | } | |
2335 | if (rstat & SER_RXD_MASK) { | |
2336 | /* The RX pin is high now, so the break | |
2337 | * must be over, but.... | |
2338 | * we can't really know if we will get another | |
2339 | * last byte ending the break or not. | |
2340 | * And we don't know if the byte (if any) will | |
2341 | * have an error or look valid. | |
2342 | */ | |
2343 | DEBUG_LOG(info->line, "# BL BRK\n", 0); | |
2344 | info->errorcode = ERRCODE_INSERT_BREAK; | |
2345 | } | |
2346 | info->break_detected_cnt++; | |
2347 | } else { | |
2348 | /* The error does not look like a break, but could be | |
2349 | * the end of one | |
2350 | */ | |
2351 | if (info->break_detected_cnt) { | |
2352 | DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt); | |
2353 | info->errorcode = ERRCODE_INSERT_BREAK; | |
2354 | } else { | |
2355 | if (info->errorcode == ERRCODE_INSERT_BREAK) { | |
2356 | info->icount.brk++; | |
2357 | add_char_and_flag(info, '\0', TTY_BREAK); | |
2358 | } | |
2359 | ||
2360 | if (rstat & SER_PAR_ERR_MASK) { | |
2361 | info->icount.parity++; | |
2362 | add_char_and_flag(info, data, TTY_PARITY); | |
2363 | } else if (rstat & SER_OVERRUN_MASK) { | |
2364 | info->icount.overrun++; | |
2365 | add_char_and_flag(info, data, TTY_OVERRUN); | |
2366 | } else if (rstat & SER_FRAMING_ERR_MASK) { | |
2367 | info->icount.frame++; | |
2368 | add_char_and_flag(info, data, TTY_FRAME); | |
2369 | } | |
2370 | ||
2371 | info->errorcode = 0; | |
2372 | } | |
2373 | info->break_detected_cnt = 0; | |
2374 | DEBUG_LOG(info->line, "#iERR s d %04X\n", | |
2375 | ((rstat & SER_ERROR_MASK) << 8) | data); | |
2376 | } | |
2377 | PROCSTAT(ser_stat[info->line].early_errors_cnt++); | |
2378 | } else { /* It was a valid byte, now let the DMA do the rest */ | |
2379 | unsigned long curr_time_u = GET_JIFFIES_USEC(); | |
2380 | unsigned long curr_time = jiffies; | |
2381 | ||
2382 | if (info->break_detected_cnt) { | |
2383 | /* Detect if this character is a new valid char or the | |
2384 | * last char in a break sequence: If LSBits are 0 and | |
2385 | * MSBits are high AND the time is close to the | |
2386 | * previous interrupt we should discard it. | |
2387 | */ | |
2388 | long elapsed_usec = | |
2389 | (curr_time - info->last_rx_active) * (1000000/HZ) + | |
2390 | curr_time_u - info->last_rx_active_usec; | |
2391 | if (elapsed_usec < 2*info->char_time_usec) { | |
2392 | DEBUG_LOG(info->line, "FBRK %i\n", info->line); | |
2393 | /* Report as BREAK (error) and let | |
2394 | * receive_chars_dma() handle it | |
2395 | */ | |
2396 | info->errorcode = ERRCODE_SET_BREAK; | |
2397 | } else { | |
2398 | DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line); | |
2399 | } | |
2400 | DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt); | |
2401 | } | |
2402 | ||
2403 | #ifdef SERIAL_DEBUG_INTR | |
2404 | printk("** OK, disabling ser_interrupts\n"); | |
2405 | #endif | |
2406 | e100_disable_serial_data_irq(info); | |
2407 | DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line)); | |
2408 | info->break_detected_cnt = 0; | |
2409 | ||
2410 | PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++); | |
2411 | } | |
2412 | /* Restarting the DMA never hurts */ | |
2413 | *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart); | |
2414 | START_FLUSH_FAST_TIMER(info, "ser_int"); | |
1da177e4 LT |
2415 | } /* handle_ser_rx_interrupt */ |
2416 | ||
41c28ff1 | 2417 | static void handle_ser_tx_interrupt(struct e100_serial *info) |
1da177e4 LT |
2418 | { |
2419 | unsigned long flags; | |
2420 | ||
2421 | if (info->x_char) { | |
2422 | unsigned char rstat; | |
2423 | DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char)); | |
77accbf5 | 2424 | local_irq_save(flags); |
d7283353 | 2425 | rstat = info->ioport[REG_STATUS]; |
1da177e4 LT |
2426 | DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat)); |
2427 | ||
d7283353 | 2428 | info->ioport[REG_TR_DATA] = info->x_char; |
1da177e4 LT |
2429 | info->icount.tx++; |
2430 | info->x_char = 0; | |
2431 | /* We must enable since it is disabled in ser_interrupt */ | |
2432 | e100_enable_serial_tx_ready_irq(info); | |
77accbf5 | 2433 | local_irq_restore(flags); |
1da177e4 LT |
2434 | return; |
2435 | } | |
2436 | if (info->uses_dma_out) { | |
2437 | unsigned char rstat; | |
2438 | int i; | |
2439 | /* We only use normal tx interrupt when sending x_char */ | |
2440 | DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0)); | |
77accbf5 | 2441 | local_irq_save(flags); |
d7283353 | 2442 | rstat = info->ioport[REG_STATUS]; |
1da177e4 LT |
2443 | DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat)); |
2444 | e100_disable_serial_tx_ready_irq(info); | |
a88487c7 TI |
2445 | if (info->port.tty->stopped) |
2446 | rs_stop(info->port.tty); | |
1da177e4 LT |
2447 | /* Enable the DMA channel and tell it to continue */ |
2448 | e100_enable_txdma_channel(info); | |
2449 | /* Wait 12 cycles before doing the DMA command */ | |
2450 | for(i = 6; i > 0; i--) | |
2451 | nop(); | |
2452 | ||
2453 | *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue); | |
77accbf5 | 2454 | local_irq_restore(flags); |
1da177e4 LT |
2455 | return; |
2456 | } | |
2457 | /* Normal char-by-char interrupt */ | |
2458 | if (info->xmit.head == info->xmit.tail | |
ee797069 | 2459 | || info->port.tty->stopped) { |
a88487c7 TI |
2460 | DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n", |
2461 | info->port.tty->stopped)); | |
1da177e4 LT |
2462 | e100_disable_serial_tx_ready_irq(info); |
2463 | info->tr_running = 0; | |
2464 | return; | |
2465 | } | |
2466 | DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail])); | |
2467 | /* Send a byte, rs485 timing is critical so turn of ints */ | |
77accbf5 | 2468 | local_irq_save(flags); |
d7283353 | 2469 | info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail]; |
1da177e4 LT |
2470 | info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1); |
2471 | info->icount.tx++; | |
2472 | if (info->xmit.head == info->xmit.tail) { | |
2473 | #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER) | |
6fd1af4c | 2474 | if (info->rs485.flags & SER_RS485_ENABLED) { |
1da177e4 LT |
2475 | /* Set a short timer to toggle RTS */ |
2476 | start_one_shot_timer(&fast_timers_rs485[info->line], | |
2477 | rs485_toggle_rts_timer_function, | |
2478 | (unsigned long)info, | |
2479 | info->char_time_usec*2, | |
2480 | "RS-485"); | |
2481 | } | |
2482 | #endif /* RS485 */ | |
2483 | info->last_tx_active_usec = GET_JIFFIES_USEC(); | |
2484 | info->last_tx_active = jiffies; | |
2485 | e100_disable_serial_tx_ready_irq(info); | |
2486 | info->tr_running = 0; | |
2487 | DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0)); | |
2488 | } else { | |
2489 | /* We must enable since it is disabled in ser_interrupt */ | |
2490 | e100_enable_serial_tx_ready_irq(info); | |
2491 | } | |
77accbf5 | 2492 | local_irq_restore(flags); |
1da177e4 LT |
2493 | |
2494 | if (CIRC_CNT(info->xmit.head, | |
2495 | info->xmit.tail, | |
2496 | SERIAL_XMIT_SIZE) < WAKEUP_CHARS) | |
2497 | rs_sched_event(info, RS_EVENT_WRITE_WAKEUP); | |
2498 | ||
2499 | } /* handle_ser_tx_interrupt */ | |
2500 | ||
2501 | /* result of time measurements: | |
2502 | * RX duration 54-60 us when doing something, otherwise 6-9 us | |
2503 | * ser_int duration: just sending: 8-15 us normally, up to 73 us | |
2504 | */ | |
2505 | static irqreturn_t | |
7d12e780 | 2506 | ser_interrupt(int irq, void *dev_id) |
1da177e4 LT |
2507 | { |
2508 | static volatile int tx_started = 0; | |
2509 | struct e100_serial *info; | |
2510 | int i; | |
2511 | unsigned long flags; | |
2512 | unsigned long irq_mask1_rd; | |
2513 | unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */ | |
2514 | int handled = 0; | |
2515 | static volatile unsigned long reentered_ready_mask = 0; | |
2516 | ||
77accbf5 | 2517 | local_irq_save(flags); |
1da177e4 LT |
2518 | irq_mask1_rd = *R_IRQ_MASK1_RD; |
2519 | /* First handle all rx interrupts with ints disabled */ | |
2520 | info = rs_table; | |
2521 | irq_mask1_rd &= e100_ser_int_mask; | |
2522 | for (i = 0; i < NR_PORTS; i++) { | |
2523 | /* Which line caused the data irq? */ | |
2524 | if (irq_mask1_rd & data_mask) { | |
2525 | handled = 1; | |
2526 | handle_ser_rx_interrupt(info); | |
2527 | } | |
2528 | info += 1; | |
2529 | data_mask <<= 2; | |
2530 | } | |
2531 | /* Handle tx interrupts with interrupts enabled so we | |
2532 | * can take care of new data interrupts while transmitting | |
2533 | * We protect the tx part with the tx_started flag. | |
2534 | * We disable the tr_ready interrupts we are about to handle and | |
2535 | * unblock the serial interrupt so new serial interrupts may come. | |
2536 | * | |
2537 | * If we get a new interrupt: | |
2538 | * - it migth be due to synchronous serial ports. | |
2539 | * - serial irq will be blocked by general irq handler. | |
2540 | * - async data will be handled above (sync will be ignored). | |
2541 | * - tx_started flag will prevent us from trying to send again and | |
2542 | * we will exit fast - no need to unblock serial irq. | |
2543 | * - Next (sync) serial interrupt handler will be runned with | |
2544 | * disabled interrupt due to restore_flags() at end of function, | |
2545 | * so sync handler will not be preempted or reentered. | |
2546 | */ | |
2547 | if (!tx_started) { | |
2548 | unsigned long ready_mask; | |
2549 | unsigned long | |
2550 | tx_started = 1; | |
2551 | /* Only the tr_ready interrupts left */ | |
2552 | irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) | | |
2553 | IO_MASK(R_IRQ_MASK1_RD, ser1_ready) | | |
2554 | IO_MASK(R_IRQ_MASK1_RD, ser2_ready) | | |
2555 | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)); | |
2556 | while (irq_mask1_rd) { | |
2557 | /* Disable those we are about to handle */ | |
2558 | *R_IRQ_MASK1_CLR = irq_mask1_rd; | |
2559 | /* Unblock the serial interrupt */ | |
2560 | *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set); | |
2561 | ||
77accbf5 | 2562 | local_irq_enable(); |
1da177e4 LT |
2563 | ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */ |
2564 | info = rs_table; | |
2565 | for (i = 0; i < NR_PORTS; i++) { | |
2566 | /* Which line caused the ready irq? */ | |
2567 | if (irq_mask1_rd & ready_mask) { | |
2568 | handled = 1; | |
2569 | handle_ser_tx_interrupt(info); | |
2570 | } | |
2571 | info += 1; | |
2572 | ready_mask <<= 2; | |
2573 | } | |
2574 | /* handle_ser_tx_interrupt enables tr_ready interrupts */ | |
77accbf5 | 2575 | local_irq_disable(); |
1da177e4 LT |
2576 | /* Handle reentered TX interrupt */ |
2577 | irq_mask1_rd = reentered_ready_mask; | |
2578 | } | |
77accbf5 | 2579 | local_irq_disable(); |
1da177e4 LT |
2580 | tx_started = 0; |
2581 | } else { | |
2582 | unsigned long ready_mask; | |
2583 | ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) | | |
2584 | IO_MASK(R_IRQ_MASK1_RD, ser1_ready) | | |
2585 | IO_MASK(R_IRQ_MASK1_RD, ser2_ready) | | |
2586 | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)); | |
2587 | if (ready_mask) { | |
2588 | reentered_ready_mask |= ready_mask; | |
2589 | /* Disable those we are about to handle */ | |
2590 | *R_IRQ_MASK1_CLR = ready_mask; | |
2591 | DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask)); | |
2592 | } | |
2593 | } | |
2594 | ||
77accbf5 | 2595 | local_irq_restore(flags); |
1da177e4 LT |
2596 | return IRQ_RETVAL(handled); |
2597 | } /* ser_interrupt */ | |
2598 | #endif | |
2599 | ||
2600 | /* | |
2601 | * ------------------------------------------------------------------- | |
2602 | * Here ends the serial interrupt routines. | |
2603 | * ------------------------------------------------------------------- | |
2604 | */ | |
2605 | ||
2606 | /* | |
2607 | * This routine is used to handle the "bottom half" processing for the | |
2608 | * serial driver, known also the "software interrupt" processing. | |
2609 | * This processing is done at the kernel interrupt level, after the | |
2610 | * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This | |
2611 | * is where time-consuming activities which can not be done in the | |
2612 | * interrupt driver proper are done; the interrupt driver schedules | |
2613 | * them using rs_sched_event(), and they get done here. | |
2614 | */ | |
2615 | static void | |
77accbf5 | 2616 | do_softint(struct work_struct *work) |
1da177e4 | 2617 | { |
77accbf5 | 2618 | struct e100_serial *info; |
1da177e4 LT |
2619 | struct tty_struct *tty; |
2620 | ||
77accbf5 JN |
2621 | info = container_of(work, struct e100_serial, work); |
2622 | ||
a88487c7 | 2623 | tty = info->port.tty; |
1da177e4 LT |
2624 | if (!tty) |
2625 | return; | |
2626 | ||
b963a844 JS |
2627 | if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event)) |
2628 | tty_wakeup(tty); | |
1da177e4 LT |
2629 | } |
2630 | ||
2631 | static int | |
2632 | startup(struct e100_serial * info) | |
2633 | { | |
2634 | unsigned long flags; | |
2635 | unsigned long xmit_page; | |
2636 | int i; | |
2637 | ||
2638 | xmit_page = get_zeroed_page(GFP_KERNEL); | |
2639 | if (!xmit_page) | |
2640 | return -ENOMEM; | |
2641 | ||
77accbf5 | 2642 | local_irq_save(flags); |
1da177e4 LT |
2643 | |
2644 | /* if it was already initialized, skip this */ | |
2645 | ||
b1d984cf | 2646 | if (info->port.flags & ASYNC_INITIALIZED) { |
77accbf5 | 2647 | local_irq_restore(flags); |
1da177e4 LT |
2648 | free_page(xmit_page); |
2649 | return 0; | |
2650 | } | |
2651 | ||
2652 | if (info->xmit.buf) | |
2653 | free_page(xmit_page); | |
2654 | else | |
2655 | info->xmit.buf = (unsigned char *) xmit_page; | |
2656 | ||
2657 | #ifdef SERIAL_DEBUG_OPEN | |
2658 | printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf); | |
2659 | #endif | |
2660 | ||
1da177e4 LT |
2661 | /* |
2662 | * Clear the FIFO buffers and disable them | |
2663 | * (they will be reenabled in change_speed()) | |
2664 | */ | |
2665 | ||
2666 | /* | |
2667 | * Reset the DMA channels and make sure their interrupts are cleared | |
2668 | */ | |
2669 | ||
2670 | if (info->dma_in_enabled) { | |
2671 | info->uses_dma_in = 1; | |
2672 | e100_enable_rxdma_channel(info); | |
2673 | ||
2674 | *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); | |
2675 | ||
2676 | /* Wait until reset cycle is complete */ | |
2677 | while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) == | |
2678 | IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset)); | |
2679 | ||
2680 | /* Make sure the irqs are cleared */ | |
2681 | *info->iclrintradr = | |
2682 | IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) | | |
2683 | IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); | |
2684 | } else { | |
2685 | e100_disable_rxdma_channel(info); | |
2686 | } | |
2687 | ||
2688 | if (info->dma_out_enabled) { | |
2689 | info->uses_dma_out = 1; | |
2690 | e100_enable_txdma_channel(info); | |
2691 | *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); | |
2692 | ||
2693 | while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) == | |
2694 | IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset)); | |
2695 | ||
2696 | /* Make sure the irqs are cleared */ | |
2697 | *info->oclrintradr = | |
2698 | IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) | | |
2699 | IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); | |
2700 | } else { | |
2701 | e100_disable_txdma_channel(info); | |
2702 | } | |
2703 | ||
a88487c7 TI |
2704 | if (info->port.tty) |
2705 | clear_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
1da177e4 LT |
2706 | |
2707 | info->xmit.head = info->xmit.tail = 0; | |
2708 | info->first_recv_buffer = info->last_recv_buffer = NULL; | |
2709 | info->recv_cnt = info->max_recv_cnt = 0; | |
2710 | ||
2711 | for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) | |
2712 | info->rec_descr[i].buf = 0; | |
2713 | ||
2714 | /* | |
2715 | * and set the speed and other flags of the serial port | |
2716 | * this will start the rx/tx as well | |
2717 | */ | |
2718 | #ifdef SERIAL_HANDLE_EARLY_ERRORS | |
2719 | e100_enable_serial_data_irq(info); | |
2720 | #endif | |
2721 | change_speed(info); | |
2722 | ||
2723 | /* dummy read to reset any serial errors */ | |
2724 | ||
d7283353 | 2725 | (void)info->ioport[REG_DATA]; |
1da177e4 LT |
2726 | |
2727 | /* enable the interrupts */ | |
2728 | if (info->uses_dma_out) | |
2729 | e100_enable_txdma_irq(info); | |
2730 | ||
2731 | e100_enable_rx_irq(info); | |
2732 | ||
2733 | info->tr_running = 0; /* to be sure we don't lock up the transmitter */ | |
2734 | ||
2735 | /* setup the dma input descriptor and start dma */ | |
2736 | ||
2737 | start_receive(info); | |
2738 | ||
2739 | /* for safety, make sure the descriptors last result is 0 bytes written */ | |
2740 | ||
2741 | info->tr_descr.sw_len = 0; | |
2742 | info->tr_descr.hw_len = 0; | |
2743 | info->tr_descr.status = 0; | |
2744 | ||
2745 | /* enable RTS/DTR last */ | |
2746 | ||
2747 | e100_rts(info, 1); | |
2748 | e100_dtr(info, 1); | |
2749 | ||
b1d984cf | 2750 | info->port.flags |= ASYNC_INITIALIZED; |
1da177e4 | 2751 | |
77accbf5 | 2752 | local_irq_restore(flags); |
1da177e4 LT |
2753 | return 0; |
2754 | } | |
2755 | ||
2756 | /* | |
2757 | * This routine will shutdown a serial port; interrupts are disabled, and | |
2758 | * DTR is dropped if the hangup on close termio flag is on. | |
2759 | */ | |
2760 | static void | |
2761 | shutdown(struct e100_serial * info) | |
2762 | { | |
2763 | unsigned long flags; | |
2764 | struct etrax_dma_descr *descr = info->rec_descr; | |
2765 | struct etrax_recv_buffer *buffer; | |
2766 | int i; | |
2767 | ||
1da177e4 LT |
2768 | /* shut down the transmitter and receiver */ |
2769 | DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line)); | |
2770 | e100_disable_rx(info); | |
d7283353 | 2771 | info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40); |
1da177e4 LT |
2772 | |
2773 | /* disable interrupts, reset dma channels */ | |
2774 | if (info->uses_dma_in) { | |
2775 | e100_disable_rxdma_irq(info); | |
2776 | *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); | |
2777 | info->uses_dma_in = 0; | |
2778 | } else { | |
2779 | e100_disable_serial_data_irq(info); | |
2780 | } | |
2781 | ||
2782 | if (info->uses_dma_out) { | |
2783 | e100_disable_txdma_irq(info); | |
2784 | info->tr_running = 0; | |
2785 | *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); | |
2786 | info->uses_dma_out = 0; | |
2787 | } else { | |
2788 | e100_disable_serial_tx_ready_irq(info); | |
2789 | info->tr_running = 0; | |
2790 | } | |
2791 | ||
b1d984cf | 2792 | if (!(info->port.flags & ASYNC_INITIALIZED)) |
1da177e4 LT |
2793 | return; |
2794 | ||
2795 | #ifdef SERIAL_DEBUG_OPEN | |
2796 | printk("Shutting down serial port %d (irq %d)....\n", info->line, | |
2797 | info->irq); | |
2798 | #endif | |
2799 | ||
77accbf5 | 2800 | local_irq_save(flags); |
1da177e4 LT |
2801 | |
2802 | if (info->xmit.buf) { | |
2803 | free_page((unsigned long)info->xmit.buf); | |
2804 | info->xmit.buf = NULL; | |
2805 | } | |
2806 | ||
2807 | for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) | |
2808 | if (descr[i].buf) { | |
2809 | buffer = phys_to_virt(descr[i].buf) - sizeof *buffer; | |
2810 | kfree(buffer); | |
2811 | descr[i].buf = 0; | |
2812 | } | |
2813 | ||
adc8d746 | 2814 | if (!info->port.tty || (info->port.tty->termios.c_cflag & HUPCL)) { |
1da177e4 LT |
2815 | /* hang up DTR and RTS if HUPCL is enabled */ |
2816 | e100_dtr(info, 0); | |
2817 | e100_rts(info, 0); /* could check CRTSCTS before doing this */ | |
2818 | } | |
2819 | ||
a88487c7 TI |
2820 | if (info->port.tty) |
2821 | set_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
1da177e4 | 2822 | |
b1d984cf | 2823 | info->port.flags &= ~ASYNC_INITIALIZED; |
77accbf5 | 2824 | local_irq_restore(flags); |
1da177e4 LT |
2825 | } |
2826 | ||
2827 | ||
2828 | /* change baud rate and other assorted parameters */ | |
2829 | ||
2830 | static void | |
2831 | change_speed(struct e100_serial *info) | |
2832 | { | |
2833 | unsigned int cflag; | |
2834 | unsigned long xoff; | |
2835 | unsigned long flags; | |
2836 | /* first some safety checks */ | |
2837 | ||
adc8d746 | 2838 | if (!info->port.tty) |
1da177e4 | 2839 | return; |
d7283353 | 2840 | if (!info->ioport) |
1da177e4 LT |
2841 | return; |
2842 | ||
adc8d746 | 2843 | cflag = info->port.tty->termios.c_cflag; |
1da177e4 LT |
2844 | |
2845 | /* possibly, the tx/rx should be disabled first to do this safely */ | |
2846 | ||
2847 | /* change baud-rate and write it to the hardware */ | |
b1d984cf | 2848 | if ((info->port.flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) { |
1da177e4 LT |
2849 | /* Special baudrate */ |
2850 | u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */ | |
2851 | unsigned long alt_source = | |
2852 | IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) | | |
2853 | IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal); | |
2854 | /* R_ALT_SER_BAUDRATE selects the source */ | |
2855 | DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n", | |
2856 | (unsigned long)info->baud_base, info->custom_divisor)); | |
2857 | if (info->baud_base == SERIAL_PRESCALE_BASE) { | |
2858 | /* 0, 2-65535 (0=65536) */ | |
2859 | u16 divisor = info->custom_divisor; | |
2860 | /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */ | |
2861 | /* baudrate is 3.125MHz/custom_divisor */ | |
2862 | alt_source = | |
2863 | IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) | | |
2864 | IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale); | |
2865 | alt_source = 0x11; | |
2866 | DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor)); | |
2867 | *R_SERIAL_PRESCALE = divisor; | |
2868 | info->baud = SERIAL_PRESCALE_BASE/divisor; | |
2869 | } | |
2870 | #ifdef CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED | |
2871 | else if ((info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8 && | |
2872 | info->custom_divisor == 1) || | |
2873 | (info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ && | |
2874 | info->custom_divisor == 8)) { | |
2875 | /* ext_clk selected */ | |
2876 | alt_source = | |
2877 | IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) | | |
2878 | IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern); | |
2879 | DBAUD(printk("using external baudrate: %lu\n", CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8)); | |
2880 | info->baud = CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8; | |
2881 | } | |
1da177e4 LT |
2882 | #endif |
2883 | else | |
2884 | { | |
2885 | /* Bad baudbase, we don't support using timer0 | |
2886 | * for baudrate. | |
2887 | */ | |
2888 | printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n", | |
2889 | (unsigned long)info->baud_base, info->custom_divisor); | |
2890 | } | |
2891 | r_alt_ser_baudrate_shadow &= ~mask; | |
2892 | r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8)); | |
2893 | *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow; | |
2894 | } else { | |
2895 | /* Normal baudrate */ | |
2896 | /* Make sure we use normal baudrate */ | |
2897 | u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */ | |
2898 | unsigned long alt_source = | |
2899 | IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) | | |
2900 | IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal); | |
2901 | r_alt_ser_baudrate_shadow &= ~mask; | |
2902 | r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8)); | |
1da177e4 | 2903 | *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow; |
1da177e4 LT |
2904 | |
2905 | info->baud = cflag_to_baud(cflag); | |
d7283353 | 2906 | info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag); |
1da177e4 LT |
2907 | } |
2908 | ||
1da177e4 | 2909 | /* start with default settings and then fill in changes */ |
77accbf5 | 2910 | local_irq_save(flags); |
1da177e4 LT |
2911 | /* 8 bit, no/even parity */ |
2912 | info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) | | |
2913 | IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) | | |
2914 | IO_MASK(R_SERIAL0_REC_CTRL, rec_par)); | |
2915 | ||
2916 | /* 8 bit, no/even parity, 1 stop bit, no cts */ | |
2917 | info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) | | |
2918 | IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) | | |
2919 | IO_MASK(R_SERIAL0_TR_CTRL, tr_par) | | |
2920 | IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) | | |
2921 | IO_MASK(R_SERIAL0_TR_CTRL, auto_cts)); | |
2922 | ||
2923 | if ((cflag & CSIZE) == CS7) { | |
2924 | /* set 7 bit mode */ | |
2925 | info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit); | |
2926 | info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit); | |
2927 | } | |
2928 | ||
2929 | if (cflag & CSTOPB) { | |
2930 | /* set 2 stop bit mode */ | |
2931 | info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits); | |
2932 | } | |
2933 | ||
2934 | if (cflag & PARENB) { | |
2935 | /* enable parity */ | |
2936 | info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); | |
2937 | info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); | |
2938 | } | |
2939 | ||
2940 | if (cflag & CMSPAR) { | |
2941 | /* enable stick parity, PARODD mean Mark which matches ETRAX */ | |
2942 | info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick); | |
2943 | info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick); | |
2944 | } | |
2945 | if (cflag & PARODD) { | |
2946 | /* set odd parity (or Mark if CMSPAR) */ | |
2947 | info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd); | |
2948 | info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd); | |
2949 | } | |
2950 | ||
2951 | if (cflag & CRTSCTS) { | |
2952 | /* enable automatic CTS handling */ | |
2953 | DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0)); | |
2954 | info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active); | |
2955 | } | |
2956 | ||
2957 | /* make sure the tx and rx are enabled */ | |
2958 | ||
2959 | info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable); | |
2960 | info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable); | |
2961 | ||
2962 | /* actually write the control regs to the hardware */ | |
2963 | ||
d7283353 AC |
2964 | info->ioport[REG_TR_CTRL] = info->tx_ctrl; |
2965 | info->ioport[REG_REC_CTRL] = info->rx_ctrl; | |
a88487c7 | 2966 | xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty)); |
1da177e4 | 2967 | xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable); |
adc8d746 | 2968 | if (info->port.tty->termios.c_iflag & IXON ) { |
a88487c7 TI |
2969 | DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n", |
2970 | STOP_CHAR(info->port.tty))); | |
1da177e4 LT |
2971 | xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable); |
2972 | } | |
2973 | ||
d7283353 | 2974 | *((unsigned long *)&info->ioport[REG_XOFF]) = xoff; |
77accbf5 | 2975 | local_irq_restore(flags); |
1da177e4 LT |
2976 | |
2977 | update_char_time(info); | |
2978 | ||
2979 | } /* change_speed */ | |
2980 | ||
2981 | /* start transmitting chars NOW */ | |
2982 | ||
2983 | static void | |
2984 | rs_flush_chars(struct tty_struct *tty) | |
2985 | { | |
2986 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
2987 | unsigned long flags; | |
2988 | ||
2989 | if (info->tr_running || | |
2990 | info->xmit.head == info->xmit.tail || | |
2991 | tty->stopped || | |
1da177e4 LT |
2992 | !info->xmit.buf) |
2993 | return; | |
2994 | ||
2995 | #ifdef SERIAL_DEBUG_FLOW | |
2996 | printk("rs_flush_chars\n"); | |
2997 | #endif | |
2998 | ||
2999 | /* this protection might not exactly be necessary here */ | |
3000 | ||
77accbf5 | 3001 | local_irq_save(flags); |
1da177e4 | 3002 | start_transmit(info); |
77accbf5 | 3003 | local_irq_restore(flags); |
1da177e4 LT |
3004 | } |
3005 | ||
77accbf5 | 3006 | static int rs_raw_write(struct tty_struct *tty, |
41c28ff1 | 3007 | const unsigned char *buf, int count) |
1da177e4 LT |
3008 | { |
3009 | int c, ret = 0; | |
3010 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
3011 | unsigned long flags; | |
3012 | ||
3013 | /* first some sanity checks */ | |
3014 | ||
f938f378 | 3015 | if (!info->xmit.buf) |
1da177e4 LT |
3016 | return 0; |
3017 | ||
3018 | #ifdef SERIAL_DEBUG_DATA | |
3019 | if (info->line == SERIAL_DEBUG_LINE) | |
3020 | printk("rs_raw_write (%d), status %d\n", | |
d7283353 | 3021 | count, info->ioport[REG_STATUS]); |
1da177e4 LT |
3022 | #endif |
3023 | ||
77accbf5 | 3024 | local_save_flags(flags); |
1da177e4 LT |
3025 | DFLOW(DEBUG_LOG(info->line, "write count %i ", count)); |
3026 | DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty))); | |
3027 | ||
3028 | ||
77accbf5 JN |
3029 | /* The local_irq_disable/restore_flags pairs below are needed |
3030 | * because the DMA interrupt handler moves the info->xmit values. | |
3031 | * the memcpy needs to be in the critical region unfortunately, | |
3032 | * because we need to read xmit values, memcpy, write xmit values | |
3033 | * in one atomic operation... this could perhaps be avoided by | |
3034 | * more clever design. | |
1da177e4 | 3035 | */ |
77accbf5 | 3036 | local_irq_disable(); |
1da177e4 LT |
3037 | while (count) { |
3038 | c = CIRC_SPACE_TO_END(info->xmit.head, | |
3039 | info->xmit.tail, | |
3040 | SERIAL_XMIT_SIZE); | |
3041 | ||
3042 | if (count < c) | |
3043 | c = count; | |
3044 | if (c <= 0) | |
3045 | break; | |
3046 | ||
3047 | memcpy(info->xmit.buf + info->xmit.head, buf, c); | |
3048 | info->xmit.head = (info->xmit.head + c) & | |
3049 | (SERIAL_XMIT_SIZE-1); | |
3050 | buf += c; | |
3051 | count -= c; | |
3052 | ret += c; | |
3053 | } | |
77accbf5 | 3054 | local_irq_restore(flags); |
1da177e4 LT |
3055 | |
3056 | /* enable transmitter if not running, unless the tty is stopped | |
3057 | * this does not need IRQ protection since if tr_running == 0 | |
3058 | * the IRQ's are not running anyway for this port. | |
3059 | */ | |
3060 | DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret)); | |
3061 | ||
3062 | if (info->xmit.head != info->xmit.tail && | |
3063 | !tty->stopped && | |
1da177e4 LT |
3064 | !info->tr_running) { |
3065 | start_transmit(info); | |
3066 | } | |
3067 | ||
3068 | return ret; | |
3069 | } /* raw_raw_write() */ | |
3070 | ||
3071 | static int | |
77accbf5 | 3072 | rs_write(struct tty_struct *tty, |
1da177e4 LT |
3073 | const unsigned char *buf, int count) |
3074 | { | |
3075 | #if defined(CONFIG_ETRAX_RS485) | |
3076 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
3077 | ||
6fd1af4c | 3078 | if (info->rs485.flags & SER_RS485_ENABLED) |
1da177e4 LT |
3079 | { |
3080 | /* If we are in RS-485 mode, we need to toggle RTS and disable | |
3081 | * the receiver before initiating a DMA transfer | |
3082 | */ | |
3083 | #ifdef CONFIG_ETRAX_FAST_TIMER | |
3084 | /* Abort any started timer */ | |
3085 | fast_timers_rs485[info->line].function = NULL; | |
3086 | del_fast_timer(&fast_timers_rs485[info->line]); | |
3087 | #endif | |
6fd1af4c | 3088 | e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND)); |
1da177e4 LT |
3089 | #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER) |
3090 | e100_disable_rx(info); | |
3091 | e100_enable_rx_irq(info); | |
3092 | #endif | |
93f3350c CS |
3093 | if (info->rs485.delay_rts_before_send > 0) |
3094 | msleep(info->rs485.delay_rts_before_send); | |
1da177e4 LT |
3095 | } |
3096 | #endif /* CONFIG_ETRAX_RS485 */ | |
3097 | ||
77accbf5 | 3098 | count = rs_raw_write(tty, buf, count); |
1da177e4 LT |
3099 | |
3100 | #if defined(CONFIG_ETRAX_RS485) | |
6fd1af4c | 3101 | if (info->rs485.flags & SER_RS485_ENABLED) |
1da177e4 LT |
3102 | { |
3103 | unsigned int val; | |
3104 | /* If we are in RS-485 mode the following has to be done: | |
3105 | * wait until DMA is ready | |
3106 | * wait on transmit shift register | |
3107 | * toggle RTS | |
3108 | * enable the receiver | |
3109 | */ | |
3110 | ||
3111 | /* Sleep until all sent */ | |
3112 | tty_wait_until_sent(tty, 0); | |
3113 | #ifdef CONFIG_ETRAX_FAST_TIMER | |
3114 | /* Now sleep a little more so that shift register is empty */ | |
3115 | schedule_usleep(info->char_time_usec * 2); | |
3116 | #endif | |
3117 | /* wait on transmit shift register */ | |
3118 | do{ | |
3119 | get_lsr_info(info, &val); | |
3120 | }while (!(val & TIOCSER_TEMT)); | |
3121 | ||
6fd1af4c | 3122 | e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND)); |
1da177e4 LT |
3123 | |
3124 | #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER) | |
3125 | e100_enable_rx(info); | |
3126 | e100_enable_rxdma_irq(info); | |
3127 | #endif | |
3128 | } | |
3129 | #endif /* CONFIG_ETRAX_RS485 */ | |
3130 | ||
3131 | return count; | |
3132 | } /* rs_write */ | |
3133 | ||
3134 | ||
3135 | /* how much space is available in the xmit buffer? */ | |
3136 | ||
3137 | static int | |
3138 | rs_write_room(struct tty_struct *tty) | |
3139 | { | |
3140 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
3141 | ||
3142 | return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); | |
3143 | } | |
3144 | ||
3145 | /* How many chars are in the xmit buffer? | |
3146 | * This does not include any chars in the transmitter FIFO. | |
3147 | * Use wait_until_sent for waiting for FIFO drain. | |
3148 | */ | |
3149 | ||
3150 | static int | |
3151 | rs_chars_in_buffer(struct tty_struct *tty) | |
3152 | { | |
3153 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
3154 | ||
3155 | return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); | |
3156 | } | |
3157 | ||
3158 | /* discard everything in the xmit buffer */ | |
3159 | ||
3160 | static void | |
3161 | rs_flush_buffer(struct tty_struct *tty) | |
3162 | { | |
3163 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
3164 | unsigned long flags; | |
3165 | ||
77accbf5 | 3166 | local_irq_save(flags); |
1da177e4 | 3167 | info->xmit.head = info->xmit.tail = 0; |
77accbf5 | 3168 | local_irq_restore(flags); |
1da177e4 | 3169 | |
b963a844 | 3170 | tty_wakeup(tty); |
1da177e4 LT |
3171 | } |
3172 | ||
3173 | /* | |
3174 | * This function is used to send a high-priority XON/XOFF character to | |
3175 | * the device | |
3176 | * | |
3177 | * Since we use DMA we don't check for info->x_char in transmit_chars_dma(), | |
3178 | * but we do it in handle_ser_tx_interrupt(). | |
3179 | * We disable DMA channel and enable tx ready interrupt and write the | |
3180 | * character when possible. | |
3181 | */ | |
3182 | static void rs_send_xchar(struct tty_struct *tty, char ch) | |
3183 | { | |
3184 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
3185 | unsigned long flags; | |
77accbf5 | 3186 | local_irq_save(flags); |
1da177e4 LT |
3187 | if (info->uses_dma_out) { |
3188 | /* Put the DMA on hold and disable the channel */ | |
3189 | *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold); | |
3190 | while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) != | |
3191 | IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold)); | |
3192 | e100_disable_txdma_channel(info); | |
3193 | } | |
3194 | ||
3195 | /* Must make sure transmitter is not stopped before we can transmit */ | |
3196 | if (tty->stopped) | |
3197 | rs_start(tty); | |
3198 | ||
3199 | /* Enable manual transmit interrupt and send from there */ | |
3200 | DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch)); | |
3201 | info->x_char = ch; | |
3202 | e100_enable_serial_tx_ready_irq(info); | |
77accbf5 | 3203 | local_irq_restore(flags); |
1da177e4 LT |
3204 | } |
3205 | ||
3206 | /* | |
3207 | * ------------------------------------------------------------ | |
3208 | * rs_throttle() | |
3209 | * | |
3210 | * This routine is called by the upper-layer tty layer to signal that | |
3211 | * incoming characters should be throttled. | |
3212 | * ------------------------------------------------------------ | |
3213 | */ | |
3214 | static void | |
3215 | rs_throttle(struct tty_struct * tty) | |
3216 | { | |
3217 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
3218 | #ifdef SERIAL_DEBUG_THROTTLE | |
3219 | char buf[64]; | |
3220 | ||
3221 | printk("throttle %s: %lu....\n", tty_name(tty, buf), | |
3222 | (unsigned long)tty->ldisc.chars_in_buffer(tty)); | |
3223 | #endif | |
3224 | DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty))); | |
3225 | ||
3226 | /* Do RTS before XOFF since XOFF might take some time */ | |
adc8d746 | 3227 | if (tty->termios.c_cflag & CRTSCTS) { |
1da177e4 LT |
3228 | /* Turn off RTS line */ |
3229 | e100_rts(info, 0); | |
3230 | } | |
3231 | if (I_IXOFF(tty)) | |
3232 | rs_send_xchar(tty, STOP_CHAR(tty)); | |
3233 | ||
3234 | } | |
3235 | ||
3236 | static void | |
3237 | rs_unthrottle(struct tty_struct * tty) | |
3238 | { | |
3239 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
3240 | #ifdef SERIAL_DEBUG_THROTTLE | |
3241 | char buf[64]; | |
3242 | ||
3243 | printk("unthrottle %s: %lu....\n", tty_name(tty, buf), | |
3244 | (unsigned long)tty->ldisc.chars_in_buffer(tty)); | |
3245 | #endif | |
3246 | DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty))); | |
3247 | DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count)); | |
3248 | /* Do RTS before XOFF since XOFF might take some time */ | |
adc8d746 | 3249 | if (tty->termios.c_cflag & CRTSCTS) { |
1da177e4 LT |
3250 | /* Assert RTS line */ |
3251 | e100_rts(info, 1); | |
3252 | } | |
3253 | ||
3254 | if (I_IXOFF(tty)) { | |
3255 | if (info->x_char) | |
3256 | info->x_char = 0; | |
3257 | else | |
3258 | rs_send_xchar(tty, START_CHAR(tty)); | |
3259 | } | |
3260 | ||
3261 | } | |
3262 | ||
3263 | /* | |
3264 | * ------------------------------------------------------------ | |
3265 | * rs_ioctl() and friends | |
3266 | * ------------------------------------------------------------ | |
3267 | */ | |
3268 | ||
3269 | static int | |
3270 | get_serial_info(struct e100_serial * info, | |
3271 | struct serial_struct * retinfo) | |
3272 | { | |
3273 | struct serial_struct tmp; | |
3274 | ||
3275 | /* this is all probably wrong, there are a lot of fields | |
3276 | * here that we don't have in e100_serial and maybe we | |
3277 | * should set them to something else than 0. | |
3278 | */ | |
3279 | ||
3280 | if (!retinfo) | |
3281 | return -EFAULT; | |
3282 | memset(&tmp, 0, sizeof(tmp)); | |
3283 | tmp.type = info->type; | |
3284 | tmp.line = info->line; | |
d7283353 | 3285 | tmp.port = (int)info->ioport; |
1da177e4 | 3286 | tmp.irq = info->irq; |
b1d984cf | 3287 | tmp.flags = info->port.flags; |
1da177e4 | 3288 | tmp.baud_base = info->baud_base; |
892c7cfc JS |
3289 | tmp.close_delay = info->port.close_delay; |
3290 | tmp.closing_wait = info->port.closing_wait; | |
1da177e4 LT |
3291 | tmp.custom_divisor = info->custom_divisor; |
3292 | if (copy_to_user(retinfo, &tmp, sizeof(*retinfo))) | |
3293 | return -EFAULT; | |
3294 | return 0; | |
3295 | } | |
3296 | ||
3297 | static int | |
3298 | set_serial_info(struct e100_serial *info, | |
3299 | struct serial_struct *new_info) | |
3300 | { | |
3301 | struct serial_struct new_serial; | |
3302 | struct e100_serial old_info; | |
3303 | int retval = 0; | |
3304 | ||
3305 | if (copy_from_user(&new_serial, new_info, sizeof(new_serial))) | |
3306 | return -EFAULT; | |
3307 | ||
3308 | old_info = *info; | |
3309 | ||
3310 | if (!capable(CAP_SYS_ADMIN)) { | |
3311 | if ((new_serial.type != info->type) || | |
892c7cfc | 3312 | (new_serial.close_delay != info->port.close_delay) || |
1da177e4 | 3313 | ((new_serial.flags & ~ASYNC_USR_MASK) != |
b1d984cf | 3314 | (info->port.flags & ~ASYNC_USR_MASK))) |
1da177e4 | 3315 | return -EPERM; |
b1d984cf | 3316 | info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) | |
1da177e4 LT |
3317 | (new_serial.flags & ASYNC_USR_MASK)); |
3318 | goto check_and_exit; | |
3319 | } | |
3320 | ||
b12d8dc2 | 3321 | if (info->port.count > 1) |
1da177e4 LT |
3322 | return -EBUSY; |
3323 | ||
3324 | /* | |
3325 | * OK, past this point, all the error checking has been done. | |
3326 | * At this point, we start making changes..... | |
3327 | */ | |
3328 | ||
3329 | info->baud_base = new_serial.baud_base; | |
b1d984cf | 3330 | info->port.flags = ((info->port.flags & ~ASYNC_FLAGS) | |
1da177e4 LT |
3331 | (new_serial.flags & ASYNC_FLAGS)); |
3332 | info->custom_divisor = new_serial.custom_divisor; | |
3333 | info->type = new_serial.type; | |
892c7cfc JS |
3334 | info->port.close_delay = new_serial.close_delay; |
3335 | info->port.closing_wait = new_serial.closing_wait; | |
b1d984cf | 3336 | info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; |
1da177e4 LT |
3337 | |
3338 | check_and_exit: | |
b1d984cf | 3339 | if (info->port.flags & ASYNC_INITIALIZED) { |
1da177e4 LT |
3340 | change_speed(info); |
3341 | } else | |
3342 | retval = startup(info); | |
3343 | return retval; | |
3344 | } | |
3345 | ||
3346 | /* | |
3347 | * get_lsr_info - get line status register info | |
3348 | * | |
3349 | * Purpose: Let user call ioctl() to get info when the UART physically | |
3350 | * is emptied. On bus types like RS485, the transmitter must | |
3351 | * release the bus after transmitting. This must be done when | |
3352 | * the transmit shift register is empty, not be done when the | |
3353 | * transmit holding register is empty. This functionality | |
3354 | * allows an RS485 driver to be written in user space. | |
3355 | */ | |
3356 | static int | |
3357 | get_lsr_info(struct e100_serial * info, unsigned int *value) | |
3358 | { | |
3359 | unsigned int result = TIOCSER_TEMT; | |
1da177e4 LT |
3360 | unsigned long curr_time = jiffies; |
3361 | unsigned long curr_time_usec = GET_JIFFIES_USEC(); | |
3362 | unsigned long elapsed_usec = | |
3363 | (curr_time - info->last_tx_active) * 1000000/HZ + | |
3364 | curr_time_usec - info->last_tx_active_usec; | |
3365 | ||
3366 | if (info->xmit.head != info->xmit.tail || | |
3367 | elapsed_usec < 2*info->char_time_usec) { | |
3368 | result = 0; | |
3369 | } | |
1da177e4 LT |
3370 | |
3371 | if (copy_to_user(value, &result, sizeof(int))) | |
3372 | return -EFAULT; | |
3373 | return 0; | |
3374 | } | |
3375 | ||
3376 | #ifdef SERIAL_DEBUG_IO | |
3377 | struct state_str | |
3378 | { | |
3379 | int state; | |
3380 | const char *str; | |
3381 | }; | |
3382 | ||
3383 | const struct state_str control_state_str[] = { | |
3384 | {TIOCM_DTR, "DTR" }, | |
3385 | {TIOCM_RTS, "RTS"}, | |
3386 | {TIOCM_ST, "ST?" }, | |
3387 | {TIOCM_SR, "SR?" }, | |
3388 | {TIOCM_CTS, "CTS" }, | |
3389 | {TIOCM_CD, "CD" }, | |
3390 | {TIOCM_RI, "RI" }, | |
3391 | {TIOCM_DSR, "DSR" }, | |
3392 | {0, NULL } | |
3393 | }; | |
3394 | ||
3395 | char *get_control_state_str(int MLines, char *s) | |
3396 | { | |
3397 | int i = 0; | |
3398 | ||
3399 | s[0]='\0'; | |
3400 | while (control_state_str[i].str != NULL) { | |
3401 | if (MLines & control_state_str[i].state) { | |
3402 | if (s[0] != '\0') { | |
3403 | strcat(s, ", "); | |
3404 | } | |
3405 | strcat(s, control_state_str[i].str); | |
3406 | } | |
3407 | i++; | |
3408 | } | |
3409 | return s; | |
3410 | } | |
3411 | #endif | |
3412 | ||
d7283353 | 3413 | static int |
77accbf5 JN |
3414 | rs_break(struct tty_struct *tty, int break_state) |
3415 | { | |
3416 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
3417 | unsigned long flags; | |
3418 | ||
d7283353 AC |
3419 | if (!info->ioport) |
3420 | return -EIO; | |
77accbf5 JN |
3421 | |
3422 | local_irq_save(flags); | |
3423 | if (break_state == -1) { | |
3424 | /* Go to manual mode and set the txd pin to 0 */ | |
3425 | /* Clear bit 7 (txd) and 6 (tr_enable) */ | |
3426 | info->tx_ctrl &= 0x3F; | |
3427 | } else { | |
3428 | /* Set bit 7 (txd) and 6 (tr_enable) */ | |
3429 | info->tx_ctrl |= (0x80 | 0x40); | |
3430 | } | |
d7283353 | 3431 | info->ioport[REG_TR_CTRL] = info->tx_ctrl; |
77accbf5 | 3432 | local_irq_restore(flags); |
d7283353 | 3433 | return 0; |
77accbf5 JN |
3434 | } |
3435 | ||
1da177e4 | 3436 | static int |
20b9d177 | 3437 | rs_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear) |
1da177e4 | 3438 | { |
77accbf5 | 3439 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; |
978e595f | 3440 | unsigned long flags; |
1da177e4 | 3441 | |
978e595f | 3442 | local_irq_save(flags); |
032c17e8 | 3443 | |
77accbf5 JN |
3444 | if (clear & TIOCM_RTS) |
3445 | e100_rts(info, 0); | |
3446 | if (clear & TIOCM_DTR) | |
3447 | e100_dtr(info, 0); | |
3448 | /* Handle FEMALE behaviour */ | |
3449 | if (clear & TIOCM_RI) | |
3450 | e100_ri_out(info, 0); | |
3451 | if (clear & TIOCM_CD) | |
3452 | e100_cd_out(info, 0); | |
3453 | ||
3454 | if (set & TIOCM_RTS) | |
3455 | e100_rts(info, 1); | |
3456 | if (set & TIOCM_DTR) | |
3457 | e100_dtr(info, 1); | |
3458 | /* Handle FEMALE behaviour */ | |
3459 | if (set & TIOCM_RI) | |
3460 | e100_ri_out(info, 1); | |
3461 | if (set & TIOCM_CD) | |
3462 | e100_cd_out(info, 1); | |
032c17e8 | 3463 | |
978e595f | 3464 | local_irq_restore(flags); |
77accbf5 JN |
3465 | return 0; |
3466 | } | |
3467 | ||
3468 | static int | |
60b33c13 | 3469 | rs_tiocmget(struct tty_struct *tty) |
77accbf5 JN |
3470 | { |
3471 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
3472 | unsigned int result; | |
978e595f AC |
3473 | unsigned long flags; |
3474 | ||
3475 | local_irq_save(flags); | |
1da177e4 LT |
3476 | |
3477 | result = | |
3478 | (!E100_RTS_GET(info) ? TIOCM_RTS : 0) | |
3479 | | (!E100_DTR_GET(info) ? TIOCM_DTR : 0) | |
3480 | | (!E100_RI_GET(info) ? TIOCM_RNG : 0) | |
3481 | | (!E100_DSR_GET(info) ? TIOCM_DSR : 0) | |
3482 | | (!E100_CD_GET(info) ? TIOCM_CAR : 0) | |
3483 | | (!E100_CTS_GET(info) ? TIOCM_CTS : 0); | |
3484 | ||
978e595f | 3485 | local_irq_restore(flags); |
032c17e8 | 3486 | |
1da177e4 | 3487 | #ifdef SERIAL_DEBUG_IO |
77accbf5 JN |
3488 | printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n", |
3489 | info->line, result, result); | |
1da177e4 LT |
3490 | { |
3491 | char s[100]; | |
3492 | ||
3493 | get_control_state_str(result, s); | |
77accbf5 | 3494 | printk(KERN_DEBUG "state: %s\n", s); |
1da177e4 LT |
3495 | } |
3496 | #endif | |
77accbf5 | 3497 | return result; |
1da177e4 | 3498 | |
1da177e4 LT |
3499 | } |
3500 | ||
3501 | ||
1da177e4 | 3502 | static int |
6caa76b7 | 3503 | rs_ioctl(struct tty_struct *tty, |
1da177e4 LT |
3504 | unsigned int cmd, unsigned long arg) |
3505 | { | |
3506 | struct e100_serial * info = (struct e100_serial *)tty->driver_data; | |
3507 | ||
3508 | if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && | |
3509 | (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) && | |
3510 | (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) { | |
3511 | if (tty->flags & (1 << TTY_IO_ERROR)) | |
3512 | return -EIO; | |
3513 | } | |
3514 | ||
3515 | switch (cmd) { | |
77accbf5 JN |
3516 | case TIOCGSERIAL: |
3517 | return get_serial_info(info, | |
3518 | (struct serial_struct *) arg); | |
3519 | case TIOCSSERIAL: | |
3520 | return set_serial_info(info, | |
3521 | (struct serial_struct *) arg); | |
3522 | case TIOCSERGETLSR: /* Get line status register */ | |
3523 | return get_lsr_info(info, (unsigned int *) arg); | |
3524 | ||
3525 | case TIOCSERGSTRUCT: | |
3526 | if (copy_to_user((struct e100_serial *) arg, | |
3527 | info, sizeof(struct e100_serial))) | |
3528 | return -EFAULT; | |
3529 | return 0; | |
1da177e4 LT |
3530 | |
3531 | #if defined(CONFIG_ETRAX_RS485) | |
77accbf5 JN |
3532 | case TIOCSERSETRS485: |
3533 | { | |
6fd1af4c CS |
3534 | /* In this ioctl we still use the old structure |
3535 | * rs485_control for backward compatibility | |
3536 | * (if we use serial_rs485, then old user-level code | |
3537 | * wouldn't work anymore...). | |
3538 | * The use of this ioctl is deprecated: use TIOCSRS485 | |
3539 | * instead.*/ | |
77accbf5 | 3540 | struct rs485_control rs485ctrl; |
6fd1af4c CS |
3541 | struct serial_rs485 rs485data; |
3542 | printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n"); | |
77accbf5 JN |
3543 | if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg, |
3544 | sizeof(rs485ctrl))) | |
3545 | return -EFAULT; | |
1da177e4 | 3546 | |
6fd1af4c CS |
3547 | rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send; |
3548 | rs485data.flags = 0; | |
c7213fc4 | 3549 | |
6fd1af4c CS |
3550 | if (rs485ctrl.enabled) |
3551 | rs485data.flags |= SER_RS485_ENABLED; | |
3552 | else | |
3553 | rs485data.flags &= ~(SER_RS485_ENABLED); | |
3554 | ||
3555 | if (rs485ctrl.rts_on_send) | |
3556 | rs485data.flags |= SER_RS485_RTS_ON_SEND; | |
3557 | else | |
3558 | rs485data.flags &= ~(SER_RS485_RTS_ON_SEND); | |
3559 | ||
3560 | if (rs485ctrl.rts_after_sent) | |
3561 | rs485data.flags |= SER_RS485_RTS_AFTER_SEND; | |
3562 | else | |
3563 | rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND); | |
3564 | ||
3565 | return e100_enable_rs485(tty, &rs485data); | |
77accbf5 | 3566 | } |
1da177e4 | 3567 | |
6fd1af4c CS |
3568 | case TIOCSRS485: |
3569 | { | |
3570 | /* This is the new version of TIOCSRS485, with new | |
3571 | * data structure serial_rs485 */ | |
3572 | struct serial_rs485 rs485data; | |
3573 | if (copy_from_user(&rs485data, (struct rs485_control *)arg, | |
3574 | sizeof(rs485data))) | |
3575 | return -EFAULT; | |
3576 | ||
3577 | return e100_enable_rs485(tty, &rs485data); | |
3578 | } | |
3579 | ||
f1d23ed8 CS |
3580 | case TIOCGRS485: |
3581 | { | |
3582 | struct serial_rs485 *rs485data = | |
3583 | &(((struct e100_serial *)tty->driver_data)->rs485); | |
3584 | /* This is the ioctl to get RS485 data from user-space */ | |
3585 | if (copy_to_user((struct serial_rs485 *) arg, | |
3586 | rs485data, | |
94479c01 | 3587 | sizeof(struct serial_rs485))) |
f1d23ed8 CS |
3588 | return -EFAULT; |
3589 | break; | |
3590 | } | |
6fd1af4c | 3591 | |
77accbf5 JN |
3592 | case TIOCSERWRRS485: |
3593 | { | |
3594 | struct rs485_write rs485wr; | |
3595 | if (copy_from_user(&rs485wr, (struct rs485_write *)arg, | |
3596 | sizeof(rs485wr))) | |
3597 | return -EFAULT; | |
1da177e4 | 3598 | |
77accbf5 JN |
3599 | return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size); |
3600 | } | |
1da177e4 LT |
3601 | #endif |
3602 | ||
77accbf5 JN |
3603 | default: |
3604 | return -ENOIOCTLCMD; | |
1da177e4 LT |
3605 | } |
3606 | return 0; | |
3607 | } | |
3608 | ||
3609 | static void | |
606d099c | 3610 | rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
1da177e4 LT |
3611 | { |
3612 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
3613 | ||
1da177e4 LT |
3614 | change_speed(info); |
3615 | ||
3616 | /* Handle turning off CRTSCTS */ | |
3617 | if ((old_termios->c_cflag & CRTSCTS) && | |
ee797069 | 3618 | !(tty->termios.c_cflag & CRTSCTS)) |
1da177e4 | 3619 | rs_start(tty); |
1da177e4 LT |
3620 | |
3621 | } | |
3622 | ||
1da177e4 LT |
3623 | /* |
3624 | * ------------------------------------------------------------ | |
3625 | * rs_close() | |
3626 | * | |
3627 | * This routine is called when the serial port gets closed. First, we | |
3628 | * wait for the last remaining data to be sent. Then, we unlink its | |
3629 | * S structure from the interrupt chain if necessary, and we free | |
3630 | * that IRQ if nothing is left in the chain. | |
3631 | * ------------------------------------------------------------ | |
3632 | */ | |
3633 | static void | |
3634 | rs_close(struct tty_struct *tty, struct file * filp) | |
3635 | { | |
3636 | struct e100_serial * info = (struct e100_serial *)tty->driver_data; | |
3637 | unsigned long flags; | |
3638 | ||
3639 | if (!info) | |
3640 | return; | |
3641 | ||
3642 | /* interrupts are disabled for this entire function */ | |
3643 | ||
77accbf5 | 3644 | local_irq_save(flags); |
1da177e4 LT |
3645 | |
3646 | if (tty_hung_up_p(filp)) { | |
77accbf5 | 3647 | local_irq_restore(flags); |
1da177e4 LT |
3648 | return; |
3649 | } | |
3650 | ||
3651 | #ifdef SERIAL_DEBUG_OPEN | |
3652 | printk("[%d] rs_close ttyS%d, count = %d\n", current->pid, | |
3653 | info->line, info->count); | |
3654 | #endif | |
b12d8dc2 | 3655 | if ((tty->count == 1) && (info->port.count != 1)) { |
1da177e4 LT |
3656 | /* |
3657 | * Uh, oh. tty->count is 1, which means that the tty | |
3658 | * structure will be freed. Info->count should always | |
3659 | * be one in these conditions. If it's greater than | |
3660 | * one, we've got real problems, since it means the | |
3661 | * serial port won't be shutdown. | |
3662 | */ | |
3d43b7d5 | 3663 | printk(KERN_ERR |
1da177e4 | 3664 | "rs_close: bad serial port count; tty->count is 1, " |
b12d8dc2 JS |
3665 | "info->count is %d\n", info->port.count); |
3666 | info->port.count = 1; | |
1da177e4 | 3667 | } |
b12d8dc2 | 3668 | if (--info->port.count < 0) { |
3d43b7d5 | 3669 | printk(KERN_ERR "rs_close: bad serial port count for ttyS%d: %d\n", |
b12d8dc2 JS |
3670 | info->line, info->port.count); |
3671 | info->port.count = 0; | |
1da177e4 | 3672 | } |
b12d8dc2 | 3673 | if (info->port.count) { |
77accbf5 | 3674 | local_irq_restore(flags); |
1da177e4 LT |
3675 | return; |
3676 | } | |
b1d984cf | 3677 | info->port.flags |= ASYNC_CLOSING; |
1da177e4 LT |
3678 | /* |
3679 | * Save the termios structure, since this port may have | |
3680 | * separate termios for callout and dialin. | |
3681 | */ | |
b1d984cf | 3682 | if (info->port.flags & ASYNC_NORMAL_ACTIVE) |
adc8d746 | 3683 | info->normal_termios = tty->termios; |
1da177e4 LT |
3684 | /* |
3685 | * Now we wait for the transmit buffer to clear; and we notify | |
3686 | * the line discipline to only process XON/XOFF characters. | |
3687 | */ | |
3688 | tty->closing = 1; | |
892c7cfc JS |
3689 | if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) |
3690 | tty_wait_until_sent(tty, info->port.closing_wait); | |
1da177e4 LT |
3691 | /* |
3692 | * At this point we stop accepting input. To do this, we | |
3693 | * disable the serial receiver and the DMA receive interrupt. | |
3694 | */ | |
3695 | #ifdef SERIAL_HANDLE_EARLY_ERRORS | |
3696 | e100_disable_serial_data_irq(info); | |
3697 | #endif | |
3698 | ||
1da177e4 LT |
3699 | e100_disable_rx(info); |
3700 | e100_disable_rx_irq(info); | |
3701 | ||
b1d984cf | 3702 | if (info->port.flags & ASYNC_INITIALIZED) { |
1da177e4 LT |
3703 | /* |
3704 | * Before we drop DTR, make sure the UART transmitter | |
3705 | * has completely drained; this is especially | |
3706 | * important as we have a transmit FIFO! | |
3707 | */ | |
3708 | rs_wait_until_sent(tty, HZ); | |
3709 | } | |
1da177e4 LT |
3710 | |
3711 | shutdown(info); | |
978e595f | 3712 | rs_flush_buffer(tty); |
454aa389 | 3713 | tty_ldisc_flush(tty); |
1da177e4 LT |
3714 | tty->closing = 0; |
3715 | info->event = 0; | |
a88487c7 | 3716 | info->port.tty = NULL; |
b12d8dc2 | 3717 | if (info->port.blocked_open) { |
892c7cfc JS |
3718 | if (info->port.close_delay) |
3719 | schedule_timeout_interruptible(info->port.close_delay); | |
4aeaeb0c | 3720 | wake_up_interruptible(&info->port.open_wait); |
1da177e4 | 3721 | } |
b1d984cf | 3722 | info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING); |
4aeaeb0c | 3723 | wake_up_interruptible(&info->port.close_wait); |
77accbf5 | 3724 | local_irq_restore(flags); |
1da177e4 LT |
3725 | |
3726 | /* port closed */ | |
3727 | ||
3728 | #if defined(CONFIG_ETRAX_RS485) | |
6fd1af4c CS |
3729 | if (info->rs485.flags & SER_RS485_ENABLED) { |
3730 | info->rs485.flags &= ~(SER_RS485_ENABLED); | |
1da177e4 LT |
3731 | #if defined(CONFIG_ETRAX_RS485_ON_PA) |
3732 | *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit); | |
3733 | #endif | |
3734 | #if defined(CONFIG_ETRAX_RS485_ON_PORT_G) | |
3735 | REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, | |
3736 | rs485_port_g_bit, 0); | |
3737 | #endif | |
3738 | #if defined(CONFIG_ETRAX_RS485_LTC1387) | |
3739 | REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, | |
3740 | CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 0); | |
3741 | REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow, | |
3742 | CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 0); | |
3743 | #endif | |
3744 | } | |
3745 | #endif | |
77accbf5 JN |
3746 | |
3747 | /* | |
3748 | * Release any allocated DMA irq's. | |
3749 | */ | |
3750 | if (info->dma_in_enabled) { | |
3751 | free_irq(info->dma_in_irq_nbr, info); | |
3752 | cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description); | |
3753 | info->uses_dma_in = 0; | |
3754 | #ifdef SERIAL_DEBUG_OPEN | |
3755 | printk(KERN_DEBUG "DMA irq '%s' freed\n", | |
3756 | info->dma_in_irq_description); | |
3757 | #endif | |
3758 | } | |
3759 | if (info->dma_out_enabled) { | |
3760 | free_irq(info->dma_out_irq_nbr, info); | |
3761 | cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description); | |
3762 | info->uses_dma_out = 0; | |
3763 | #ifdef SERIAL_DEBUG_OPEN | |
3764 | printk(KERN_DEBUG "DMA irq '%s' freed\n", | |
3765 | info->dma_out_irq_description); | |
3766 | #endif | |
3767 | } | |
1da177e4 LT |
3768 | } |
3769 | ||
3770 | /* | |
3771 | * rs_wait_until_sent() --- wait until the transmitter is empty | |
3772 | */ | |
3773 | static void rs_wait_until_sent(struct tty_struct *tty, int timeout) | |
3774 | { | |
3775 | unsigned long orig_jiffies; | |
3776 | struct e100_serial *info = (struct e100_serial *)tty->driver_data; | |
3777 | unsigned long curr_time = jiffies; | |
3778 | unsigned long curr_time_usec = GET_JIFFIES_USEC(); | |
3779 | long elapsed_usec = | |
3780 | (curr_time - info->last_tx_active) * (1000000/HZ) + | |
3781 | curr_time_usec - info->last_tx_active_usec; | |
3782 | ||
3783 | /* | |
3784 | * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO | |
3785 | * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k) | |
3786 | */ | |
3787 | orig_jiffies = jiffies; | |
3788 | while (info->xmit.head != info->xmit.tail || /* More in send queue */ | |
3789 | (*info->ostatusadr & 0x007f) || /* more in FIFO */ | |
3790 | (elapsed_usec < 2*info->char_time_usec)) { | |
3c76bc5b | 3791 | schedule_timeout_interruptible(1); |
1da177e4 LT |
3792 | if (signal_pending(current)) |
3793 | break; | |
3794 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
3795 | break; | |
3796 | curr_time = jiffies; | |
3797 | curr_time_usec = GET_JIFFIES_USEC(); | |
3798 | elapsed_usec = | |
3799 | (curr_time - info->last_tx_active) * (1000000/HZ) + | |
3800 | curr_time_usec - info->last_tx_active_usec; | |
3801 | } | |
3802 | set_current_state(TASK_RUNNING); | |
3803 | } | |
3804 | ||
3805 | /* | |
3806 | * rs_hangup() --- called by tty_hangup() when a hangup is signaled. | |
3807 | */ | |
3808 | void | |
3809 | rs_hangup(struct tty_struct *tty) | |
3810 | { | |
3811 | struct e100_serial * info = (struct e100_serial *)tty->driver_data; | |
3812 | ||
3813 | rs_flush_buffer(tty); | |
3814 | shutdown(info); | |
3815 | info->event = 0; | |
b12d8dc2 | 3816 | info->port.count = 0; |
b1d984cf | 3817 | info->port.flags &= ~ASYNC_NORMAL_ACTIVE; |
a88487c7 | 3818 | info->port.tty = NULL; |
4aeaeb0c | 3819 | wake_up_interruptible(&info->port.open_wait); |
1da177e4 LT |
3820 | } |
3821 | ||
3822 | /* | |
3823 | * ------------------------------------------------------------ | |
3824 | * rs_open() and friends | |
3825 | * ------------------------------------------------------------ | |
3826 | */ | |
3827 | static int | |
3828 | block_til_ready(struct tty_struct *tty, struct file * filp, | |
3829 | struct e100_serial *info) | |
3830 | { | |
3831 | DECLARE_WAITQUEUE(wait, current); | |
3832 | unsigned long flags; | |
3833 | int retval; | |
3834 | int do_clocal = 0, extra_count = 0; | |
3835 | ||
3836 | /* | |
3837 | * If the device is in the middle of being closed, then block | |
3838 | * until it's done, and then try again. | |
3839 | */ | |
3840 | if (tty_hung_up_p(filp) || | |
b1d984cf | 3841 | (info->port.flags & ASYNC_CLOSING)) { |
4aeaeb0c | 3842 | wait_event_interruptible_tty(tty, info->port.close_wait, |
b1d984cf | 3843 | !(info->port.flags & ASYNC_CLOSING)); |
1da177e4 | 3844 | #ifdef SERIAL_DO_RESTART |
b1d984cf | 3845 | if (info->port.flags & ASYNC_HUP_NOTIFY) |
1da177e4 LT |
3846 | return -EAGAIN; |
3847 | else | |
3848 | return -ERESTARTSYS; | |
3849 | #else | |
3850 | return -EAGAIN; | |
3851 | #endif | |
3852 | } | |
3853 | ||
3854 | /* | |
3855 | * If non-blocking mode is set, or the port is not enabled, | |
3856 | * then make the check up front and then exit. | |
3857 | */ | |
3858 | if ((filp->f_flags & O_NONBLOCK) || | |
3859 | (tty->flags & (1 << TTY_IO_ERROR))) { | |
b1d984cf | 3860 | info->port.flags |= ASYNC_NORMAL_ACTIVE; |
1da177e4 LT |
3861 | return 0; |
3862 | } | |
3863 | ||
adc8d746 | 3864 | if (tty->termios.c_cflag & CLOCAL) { |
1da177e4 LT |
3865 | do_clocal = 1; |
3866 | } | |
3867 | ||
3868 | /* | |
3869 | * Block waiting for the carrier detect and the line to become | |
3870 | * free (i.e., not in use by the callout). While we are in | |
b12d8dc2 | 3871 | * this loop, info->port.count is dropped by one, so that |
1da177e4 LT |
3872 | * rs_close() knows when to free things. We restore it upon |
3873 | * exit, either normal or abnormal. | |
3874 | */ | |
3875 | retval = 0; | |
4aeaeb0c | 3876 | add_wait_queue(&info->port.open_wait, &wait); |
1da177e4 LT |
3877 | #ifdef SERIAL_DEBUG_OPEN |
3878 | printk("block_til_ready before block: ttyS%d, count = %d\n", | |
b12d8dc2 | 3879 | info->line, info->port.count); |
1da177e4 | 3880 | #endif |
77accbf5 | 3881 | local_irq_save(flags); |
1da177e4 LT |
3882 | if (!tty_hung_up_p(filp)) { |
3883 | extra_count++; | |
b12d8dc2 | 3884 | info->port.count--; |
1da177e4 | 3885 | } |
77accbf5 | 3886 | local_irq_restore(flags); |
b12d8dc2 | 3887 | info->port.blocked_open++; |
1da177e4 | 3888 | while (1) { |
77accbf5 | 3889 | local_irq_save(flags); |
1da177e4 LT |
3890 | /* assert RTS and DTR */ |
3891 | e100_rts(info, 1); | |
3892 | e100_dtr(info, 1); | |
77accbf5 | 3893 | local_irq_restore(flags); |
1da177e4 LT |
3894 | set_current_state(TASK_INTERRUPTIBLE); |
3895 | if (tty_hung_up_p(filp) || | |
b1d984cf | 3896 | !(info->port.flags & ASYNC_INITIALIZED)) { |
1da177e4 | 3897 | #ifdef SERIAL_DO_RESTART |
b1d984cf | 3898 | if (info->port.flags & ASYNC_HUP_NOTIFY) |
1da177e4 LT |
3899 | retval = -EAGAIN; |
3900 | else | |
3901 | retval = -ERESTARTSYS; | |
3902 | #else | |
3903 | retval = -EAGAIN; | |
3904 | #endif | |
3905 | break; | |
3906 | } | |
b1d984cf | 3907 | if (!(info->port.flags & ASYNC_CLOSING) && do_clocal) |
1da177e4 LT |
3908 | /* && (do_clocal || DCD_IS_ASSERTED) */ |
3909 | break; | |
3910 | if (signal_pending(current)) { | |
3911 | retval = -ERESTARTSYS; | |
3912 | break; | |
3913 | } | |
3914 | #ifdef SERIAL_DEBUG_OPEN | |
3915 | printk("block_til_ready blocking: ttyS%d, count = %d\n", | |
b12d8dc2 | 3916 | info->line, info->port.count); |
1da177e4 | 3917 | #endif |
89c8d91e | 3918 | tty_unlock(tty); |
1da177e4 | 3919 | schedule(); |
89c8d91e | 3920 | tty_lock(tty); |
1da177e4 LT |
3921 | } |
3922 | set_current_state(TASK_RUNNING); | |
4aeaeb0c | 3923 | remove_wait_queue(&info->port.open_wait, &wait); |
1da177e4 | 3924 | if (extra_count) |
b12d8dc2 JS |
3925 | info->port.count++; |
3926 | info->port.blocked_open--; | |
1da177e4 LT |
3927 | #ifdef SERIAL_DEBUG_OPEN |
3928 | printk("block_til_ready after blocking: ttyS%d, count = %d\n", | |
b12d8dc2 | 3929 | info->line, info->port.count); |
1da177e4 LT |
3930 | #endif |
3931 | if (retval) | |
3932 | return retval; | |
b1d984cf | 3933 | info->port.flags |= ASYNC_NORMAL_ACTIVE; |
1da177e4 LT |
3934 | return 0; |
3935 | } | |
3936 | ||
77accbf5 JN |
3937 | static void |
3938 | deinit_port(struct e100_serial *info) | |
3939 | { | |
3940 | if (info->dma_out_enabled) { | |
3941 | cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description); | |
3942 | free_irq(info->dma_out_irq_nbr, info); | |
3943 | } | |
3944 | if (info->dma_in_enabled) { | |
3945 | cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description); | |
3946 | free_irq(info->dma_in_irq_nbr, info); | |
3947 | } | |
3948 | } | |
3949 | ||
1da177e4 LT |
3950 | /* |
3951 | * This routine is called whenever a serial port is opened. | |
3952 | * It performs the serial-specific initialization for the tty structure. | |
3953 | */ | |
3954 | static int | |
3955 | rs_open(struct tty_struct *tty, struct file * filp) | |
3956 | { | |
3957 | struct e100_serial *info; | |
410235fd | 3958 | int retval; |
77accbf5 | 3959 | int allocated_resources = 0; |
1da177e4 | 3960 | |
410235fd | 3961 | info = rs_table + tty->index; |
1da177e4 LT |
3962 | if (!info->enabled) |
3963 | return -ENODEV; | |
3964 | ||
3965 | #ifdef SERIAL_DEBUG_OPEN | |
3966 | printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name, | |
b12d8dc2 | 3967 | info->port.count); |
1da177e4 LT |
3968 | #endif |
3969 | ||
b12d8dc2 | 3970 | info->port.count++; |
1da177e4 | 3971 | tty->driver_data = info; |
a88487c7 | 3972 | info->port.tty = tty; |
1da177e4 | 3973 | |
b1d984cf | 3974 | info->port.low_latency = !!(info->port.flags & ASYNC_LOW_LATENCY); |
1da177e4 | 3975 | |
1da177e4 LT |
3976 | /* |
3977 | * If the port is in the middle of closing, bail out now | |
3978 | */ | |
3979 | if (tty_hung_up_p(filp) || | |
b1d984cf | 3980 | (info->port.flags & ASYNC_CLOSING)) { |
4aeaeb0c | 3981 | wait_event_interruptible_tty(tty, info->port.close_wait, |
b1d984cf | 3982 | !(info->port.flags & ASYNC_CLOSING)); |
1da177e4 | 3983 | #ifdef SERIAL_DO_RESTART |
b1d984cf | 3984 | return ((info->port.flags & ASYNC_HUP_NOTIFY) ? |
1da177e4 LT |
3985 | -EAGAIN : -ERESTARTSYS); |
3986 | #else | |
3987 | return -EAGAIN; | |
3988 | #endif | |
3989 | } | |
3990 | ||
77accbf5 JN |
3991 | /* |
3992 | * If DMA is enabled try to allocate the irq's. | |
3993 | */ | |
b12d8dc2 | 3994 | if (info->port.count == 1) { |
77accbf5 JN |
3995 | allocated_resources = 1; |
3996 | if (info->dma_in_enabled) { | |
3997 | if (request_irq(info->dma_in_irq_nbr, | |
3998 | rec_interrupt, | |
3999 | info->dma_in_irq_flags, | |
4000 | info->dma_in_irq_description, | |
4001 | info)) { | |
4002 | printk(KERN_WARNING "DMA irq '%s' busy; " | |
4003 | "falling back to non-DMA mode\n", | |
4004 | info->dma_in_irq_description); | |
4005 | /* Make sure we never try to use DMA in */ | |
4006 | /* for the port again. */ | |
4007 | info->dma_in_enabled = 0; | |
4008 | } else if (cris_request_dma(info->dma_in_nbr, | |
4009 | info->dma_in_irq_description, | |
4010 | DMA_VERBOSE_ON_ERROR, | |
4011 | info->dma_owner)) { | |
4012 | free_irq(info->dma_in_irq_nbr, info); | |
4013 | printk(KERN_WARNING "DMA '%s' busy; " | |
4014 | "falling back to non-DMA mode\n", | |
4015 | info->dma_in_irq_description); | |
4016 | /* Make sure we never try to use DMA in */ | |
4017 | /* for the port again. */ | |
4018 | info->dma_in_enabled = 0; | |
4019 | } | |
4020 | #ifdef SERIAL_DEBUG_OPEN | |
4021 | else | |
4022 | printk(KERN_DEBUG "DMA irq '%s' allocated\n", | |
4023 | info->dma_in_irq_description); | |
4024 | #endif | |
4025 | } | |
4026 | if (info->dma_out_enabled) { | |
4027 | if (request_irq(info->dma_out_irq_nbr, | |
4028 | tr_interrupt, | |
4029 | info->dma_out_irq_flags, | |
4030 | info->dma_out_irq_description, | |
4031 | info)) { | |
4032 | printk(KERN_WARNING "DMA irq '%s' busy; " | |
4033 | "falling back to non-DMA mode\n", | |
4034 | info->dma_out_irq_description); | |
4035 | /* Make sure we never try to use DMA out */ | |
4036 | /* for the port again. */ | |
4037 | info->dma_out_enabled = 0; | |
4038 | } else if (cris_request_dma(info->dma_out_nbr, | |
4039 | info->dma_out_irq_description, | |
4040 | DMA_VERBOSE_ON_ERROR, | |
4041 | info->dma_owner)) { | |
4042 | free_irq(info->dma_out_irq_nbr, info); | |
4043 | printk(KERN_WARNING "DMA '%s' busy; " | |
4044 | "falling back to non-DMA mode\n", | |
4045 | info->dma_out_irq_description); | |
4046 | /* Make sure we never try to use DMA out */ | |
4047 | /* for the port again. */ | |
4048 | info->dma_out_enabled = 0; | |
4049 | } | |
4050 | #ifdef SERIAL_DEBUG_OPEN | |
4051 | else | |
4052 | printk(KERN_DEBUG "DMA irq '%s' allocated\n", | |
4053 | info->dma_out_irq_description); | |
4054 | #endif | |
4055 | } | |
4056 | } | |
4057 | ||
1da177e4 LT |
4058 | /* |
4059 | * Start up the serial port | |
4060 | */ | |
4061 | ||
4062 | retval = startup(info); | |
77accbf5 JN |
4063 | if (retval) { |
4064 | if (allocated_resources) | |
4065 | deinit_port(info); | |
4066 | ||
b12d8dc2 | 4067 | /* FIXME Decrease count info->port.count here too? */ |
1da177e4 | 4068 | return retval; |
77accbf5 JN |
4069 | } |
4070 | ||
1da177e4 LT |
4071 | |
4072 | retval = block_til_ready(tty, filp, info); | |
4073 | if (retval) { | |
4074 | #ifdef SERIAL_DEBUG_OPEN | |
4075 | printk("rs_open returning after block_til_ready with %d\n", | |
4076 | retval); | |
4077 | #endif | |
77accbf5 JN |
4078 | if (allocated_resources) |
4079 | deinit_port(info); | |
4080 | ||
1da177e4 LT |
4081 | return retval; |
4082 | } | |
4083 | ||
b12d8dc2 | 4084 | if ((info->port.count == 1) && (info->port.flags & ASYNC_SPLIT_TERMIOS)) { |
adc8d746 | 4085 | tty->termios = info->normal_termios; |
1da177e4 LT |
4086 | change_speed(info); |
4087 | } | |
4088 | ||
4089 | #ifdef SERIAL_DEBUG_OPEN | |
4090 | printk("rs_open ttyS%d successful...\n", info->line); | |
4091 | #endif | |
4092 | DLOG_INT_TRIG( log_int_pos = 0); | |
4093 | ||
4094 | DFLIP( if (info->line == SERIAL_DEBUG_LINE) { | |
4095 | info->icount.rx = 0; | |
4096 | } ); | |
4097 | ||
4098 | return 0; | |
4099 | } | |
4100 | ||
9e040a3e | 4101 | #ifdef CONFIG_PROC_FS |
1da177e4 LT |
4102 | /* |
4103 | * /proc fs routines.... | |
4104 | */ | |
4105 | ||
9e040a3e | 4106 | static void seq_line_info(struct seq_file *m, struct e100_serial *info) |
1da177e4 | 4107 | { |
1da177e4 LT |
4108 | unsigned long tmp; |
4109 | ||
9e040a3e JN |
4110 | seq_printf(m, "%d: uart:E100 port:%lX irq:%d", |
4111 | info->line, (unsigned long)info->ioport, info->irq); | |
1da177e4 | 4112 | |
d7283353 | 4113 | if (!info->ioport || (info->type == PORT_UNKNOWN)) { |
9e040a3e JN |
4114 | seq_printf(m, "\n"); |
4115 | return; | |
1da177e4 LT |
4116 | } |
4117 | ||
9e040a3e JN |
4118 | seq_printf(m, " baud:%d", info->baud); |
4119 | seq_printf(m, " tx:%lu rx:%lu", | |
1da177e4 LT |
4120 | (unsigned long)info->icount.tx, |
4121 | (unsigned long)info->icount.rx); | |
4122 | tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE); | |
9e040a3e JN |
4123 | if (tmp) |
4124 | seq_printf(m, " tx_pend:%lu/%lu", | |
4125 | (unsigned long)tmp, | |
4126 | (unsigned long)SERIAL_XMIT_SIZE); | |
1da177e4 | 4127 | |
9e040a3e JN |
4128 | seq_printf(m, " rx_pend:%lu/%lu", |
4129 | (unsigned long)info->recv_cnt, | |
4130 | (unsigned long)info->max_recv_cnt); | |
1da177e4 LT |
4131 | |
4132 | #if 1 | |
a88487c7 | 4133 | if (info->port.tty) { |
a88487c7 | 4134 | if (info->port.tty->stopped) |
9e040a3e JN |
4135 | seq_printf(m, " stopped:%i", |
4136 | (int)info->port.tty->stopped); | |
1da177e4 LT |
4137 | } |
4138 | ||
4139 | { | |
d7283353 | 4140 | unsigned char rstat = info->ioport[REG_STATUS]; |
9e040a3e JN |
4141 | if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect)) |
4142 | seq_printf(m, " xoff_detect:1"); | |
1da177e4 LT |
4143 | } |
4144 | ||
4145 | #endif | |
4146 | ||
1da177e4 | 4147 | if (info->icount.frame) |
9e040a3e | 4148 | seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame); |
1da177e4 LT |
4149 | |
4150 | if (info->icount.parity) | |
9e040a3e | 4151 | seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity); |
1da177e4 LT |
4152 | |
4153 | if (info->icount.brk) | |
9e040a3e | 4154 | seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk); |
1da177e4 LT |
4155 | |
4156 | if (info->icount.overrun) | |
9e040a3e | 4157 | seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun); |
1da177e4 LT |
4158 | |
4159 | /* | |
4160 | * Last thing is the RS-232 status lines | |
4161 | */ | |
9e040a3e JN |
4162 | if (!E100_RTS_GET(info)) |
4163 | seq_puts(m, "|RTS"); | |
4164 | if (!E100_CTS_GET(info)) | |
4165 | seq_puts(m, "|CTS"); | |
4166 | if (!E100_DTR_GET(info)) | |
4167 | seq_puts(m, "|DTR"); | |
4168 | if (!E100_DSR_GET(info)) | |
4169 | seq_puts(m, "|DSR"); | |
4170 | if (!E100_CD_GET(info)) | |
4171 | seq_puts(m, "|CD"); | |
4172 | if (!E100_RI_GET(info)) | |
4173 | seq_puts(m, "|RI"); | |
4174 | seq_puts(m, "\n"); | |
1da177e4 LT |
4175 | } |
4176 | ||
9e040a3e JN |
4177 | |
4178 | static int crisv10_proc_show(struct seq_file *m, void *v) | |
1da177e4 | 4179 | { |
9e040a3e | 4180 | int i; |
1da177e4 | 4181 | |
9e040a3e JN |
4182 | seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version); |
4183 | ||
4184 | for (i = 0; i < NR_PORTS; i++) { | |
1da177e4 LT |
4185 | if (!rs_table[i].enabled) |
4186 | continue; | |
9e040a3e | 4187 | seq_line_info(m, &rs_table[i]); |
1da177e4 LT |
4188 | } |
4189 | #ifdef DEBUG_LOG_INCLUDED | |
4190 | for (i = 0; i < debug_log_pos; i++) { | |
9e040a3e JN |
4191 | seq_printf(m, "%-4i %lu.%lu ", |
4192 | i, debug_log[i].time, | |
4193 | timer_data_to_ns(debug_log[i].timer_data)); | |
4194 | seq_printf(m, debug_log[i].string, debug_log[i].value); | |
1da177e4 | 4195 | } |
9e040a3e | 4196 | seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE); |
1da177e4 LT |
4197 | debug_log_pos = 0; |
4198 | #endif | |
9e040a3e JN |
4199 | return 0; |
4200 | } | |
1da177e4 | 4201 | |
9e040a3e JN |
4202 | static int crisv10_proc_open(struct inode *inode, struct file *file) |
4203 | { | |
4204 | return single_open(file, crisv10_proc_show, NULL); | |
1da177e4 LT |
4205 | } |
4206 | ||
9e040a3e JN |
4207 | static const struct file_operations crisv10_proc_fops = { |
4208 | .owner = THIS_MODULE, | |
4209 | .open = crisv10_proc_open, | |
4210 | .read = seq_read, | |
4211 | .llseek = seq_lseek, | |
4212 | .release = single_release, | |
4213 | }; | |
4214 | #endif | |
4215 | ||
4216 | ||
1da177e4 LT |
4217 | /* Finally, routines used to initialize the serial driver. */ |
4218 | ||
9e040a3e | 4219 | static void show_serial_version(void) |
1da177e4 LT |
4220 | { |
4221 | printk(KERN_INFO | |
9e040a3e JN |
4222 | "ETRAX 100LX serial-driver %s, " |
4223 | "(c) 2000-2004 Axis Communications AB\r\n", | |
1da177e4 LT |
4224 | &serial_version[11]); /* "$Revision: x.yy" */ |
4225 | } | |
4226 | ||
4227 | /* rs_init inits the driver at boot (using the module_init chain) */ | |
4228 | ||
b68e31d0 | 4229 | static const struct tty_operations rs_ops = { |
1da177e4 LT |
4230 | .open = rs_open, |
4231 | .close = rs_close, | |
4232 | .write = rs_write, | |
4233 | .flush_chars = rs_flush_chars, | |
4234 | .write_room = rs_write_room, | |
4235 | .chars_in_buffer = rs_chars_in_buffer, | |
4236 | .flush_buffer = rs_flush_buffer, | |
4237 | .ioctl = rs_ioctl, | |
4238 | .throttle = rs_throttle, | |
4239 | .unthrottle = rs_unthrottle, | |
4240 | .set_termios = rs_set_termios, | |
4241 | .stop = rs_stop, | |
4242 | .start = rs_start, | |
4243 | .hangup = rs_hangup, | |
4244 | .break_ctl = rs_break, | |
4245 | .send_xchar = rs_send_xchar, | |
4246 | .wait_until_sent = rs_wait_until_sent, | |
77accbf5 | 4247 | .tiocmget = rs_tiocmget, |
9e040a3e JN |
4248 | .tiocmset = rs_tiocmset, |
4249 | #ifdef CONFIG_PROC_FS | |
4250 | .proc_fops = &crisv10_proc_fops, | |
4251 | #endif | |
1da177e4 LT |
4252 | }; |
4253 | ||
9e040a3e | 4254 | static int __init rs_init(void) |
1da177e4 LT |
4255 | { |
4256 | int i; | |
4257 | struct e100_serial *info; | |
4258 | struct tty_driver *driver = alloc_tty_driver(NR_PORTS); | |
4259 | ||
4260 | if (!driver) | |
4261 | return -ENOMEM; | |
4262 | ||
4263 | show_serial_version(); | |
4264 | ||
4265 | /* Setup the timed flush handler system */ | |
4266 | ||
4267 | #if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER) | |
77accbf5 JN |
4268 | setup_timer(&flush_timer, timed_flush_handler, 0); |
4269 | mod_timer(&flush_timer, jiffies + 5); | |
4270 | #endif | |
4271 | ||
4272 | #if defined(CONFIG_ETRAX_RS485) | |
4273 | #if defined(CONFIG_ETRAX_RS485_ON_PA) | |
2f7861de | 4274 | if (cris_io_interface_allocate_pins(if_serial_0, 'a', rs485_pa_bit, |
77accbf5 | 4275 | rs485_pa_bit)) { |
3d43b7d5 | 4276 | printk(KERN_ERR "ETRAX100LX serial: Could not allocate " |
77accbf5 | 4277 | "RS485 pin\n"); |
41ca7322 | 4278 | put_tty_driver(driver); |
77accbf5 JN |
4279 | return -EBUSY; |
4280 | } | |
4281 | #endif | |
4282 | #if defined(CONFIG_ETRAX_RS485_ON_PORT_G) | |
2f7861de | 4283 | if (cris_io_interface_allocate_pins(if_serial_0, 'g', rs485_pa_bit, |
77accbf5 | 4284 | rs485_port_g_bit)) { |
3d43b7d5 | 4285 | printk(KERN_ERR "ETRAX100LX serial: Could not allocate " |
77accbf5 | 4286 | "RS485 pin\n"); |
41ca7322 | 4287 | put_tty_driver(driver); |
77accbf5 JN |
4288 | return -EBUSY; |
4289 | } | |
4290 | #endif | |
1da177e4 LT |
4291 | #endif |
4292 | ||
4293 | /* Initialize the tty_driver structure */ | |
4294 | ||
4295 | driver->driver_name = "serial"; | |
4296 | driver->name = "ttyS"; | |
4297 | driver->major = TTY_MAJOR; | |
4298 | driver->minor_start = 64; | |
4299 | driver->type = TTY_DRIVER_TYPE_SERIAL; | |
4300 | driver->subtype = SERIAL_TYPE_NORMAL; | |
4301 | driver->init_termios = tty_std_termios; | |
4302 | driver->init_termios.c_cflag = | |
4303 | B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */ | |
606d099c AC |
4304 | driver->init_termios.c_ispeed = 115200; |
4305 | driver->init_termios.c_ospeed = 115200; | |
c4d6ebeb | 4306 | driver->flags = TTY_DRIVER_REAL_RAW; |
1da177e4 LT |
4307 | |
4308 | tty_set_operations(driver, &rs_ops); | |
4309 | serial_driver = driver; | |
1da177e4 | 4310 | |
b19e2ca7 | 4311 | /* do some initializing for the separate ports */ |
1da177e4 | 4312 | for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) { |
77accbf5 JN |
4313 | if (info->enabled) { |
4314 | if (cris_request_io_interface(info->io_if, | |
4315 | info->io_if_description)) { | |
3d43b7d5 | 4316 | printk(KERN_ERR "ETRAX100LX async serial: " |
77accbf5 JN |
4317 | "Could not allocate IO pins for " |
4318 | "%s, port %d\n", | |
4319 | info->io_if_description, i); | |
4320 | info->enabled = 0; | |
4321 | } | |
4322 | } | |
953756e2 | 4323 | tty_port_init(&info->port); |
1da177e4 LT |
4324 | info->uses_dma_in = 0; |
4325 | info->uses_dma_out = 0; | |
4326 | info->line = i; | |
a88487c7 | 4327 | info->port.tty = NULL; |
1da177e4 LT |
4328 | info->type = PORT_ETRAX; |
4329 | info->tr_running = 0; | |
4330 | info->forced_eop = 0; | |
4331 | info->baud_base = DEF_BAUD_BASE; | |
4332 | info->custom_divisor = 0; | |
1da177e4 LT |
4333 | info->x_char = 0; |
4334 | info->event = 0; | |
1da177e4 | 4335 | info->normal_termios = driver->init_termios; |
1da177e4 LT |
4336 | info->xmit.buf = NULL; |
4337 | info->xmit.tail = info->xmit.head = 0; | |
4338 | info->first_recv_buffer = info->last_recv_buffer = NULL; | |
4339 | info->recv_cnt = info->max_recv_cnt = 0; | |
4340 | info->last_tx_active_usec = 0; | |
4341 | info->last_tx_active = 0; | |
4342 | ||
4343 | #if defined(CONFIG_ETRAX_RS485) | |
4344 | /* Set sane defaults */ | |
6fd1af4c CS |
4345 | info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND); |
4346 | info->rs485.flags |= SER_RS485_RTS_AFTER_SEND; | |
1da177e4 | 4347 | info->rs485.delay_rts_before_send = 0; |
6fd1af4c | 4348 | info->rs485.flags &= ~(SER_RS485_ENABLED); |
1da177e4 | 4349 | #endif |
77accbf5 | 4350 | INIT_WORK(&info->work, do_softint); |
1da177e4 LT |
4351 | |
4352 | if (info->enabled) { | |
078dee2d KV |
4353 | printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n", |
4354 | serial_driver->name, info->line, info->ioport); | |
1da177e4 | 4355 | } |
b19e2ca7 | 4356 | tty_port_link_device(&info->port, driver, i); |
1da177e4 | 4357 | } |
b19e2ca7 JS |
4358 | |
4359 | if (tty_register_driver(driver)) | |
4360 | panic("Couldn't register serial driver\n"); | |
4361 | ||
1da177e4 LT |
4362 | #ifdef CONFIG_ETRAX_FAST_TIMER |
4363 | #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER | |
4364 | memset(fast_timers, 0, sizeof(fast_timers)); | |
4365 | #endif | |
4366 | #ifdef CONFIG_ETRAX_RS485 | |
4367 | memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485)); | |
4368 | #endif | |
4369 | fast_timer_init(); | |
4370 | #endif | |
4371 | ||
77accbf5 | 4372 | #ifndef CONFIG_ETRAX_KGDB |
1da177e4 LT |
4373 | /* Not needed in simulator. May only complicate stuff. */ |
4374 | /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */ | |
4375 | ||
77accbf5 | 4376 | if (request_irq(SERIAL_IRQ_NBR, ser_interrupt, |
9cfb5c05 | 4377 | IRQF_SHARED, "serial ", driver)) |
71cc2c21 | 4378 | panic("%s: Failed to request irq8", __func__); |
1da177e4 | 4379 | |
1da177e4 | 4380 | #endif |
77accbf5 | 4381 | |
1da177e4 LT |
4382 | return 0; |
4383 | } | |
4384 | ||
4385 | /* this makes sure that rs_init is called during kernel boot */ | |
4386 | ||
4387 | module_init(rs_init); |