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Merge tag 'mmc-v4.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / crisv10.c
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
77accbf5 2/*
1da177e4
LT		 3 * Serial port driver for the ETRAX 100LX chip
4 *
77accbf5 5 * Copyright (C) 1998-2007 Axis Communications AB
1da177e4
LT		 6 *
7 * Many, many authors. Based once upon a time on serial.c for 16x50.
8 *
1da177e4
LT		 9 */
10
11static char *serial_version = "$Revision: 1.25 $";
12
1da177e4
LT		 13#include <linux/types.h>
14#include <linux/errno.h>
15#include <linux/signal.h>
174cd4b1 16#include <linux/sched/signal.h>
1da177e4
LT		 17#include <linux/timer.h>
18#include <linux/interrupt.h>
19#include <linux/tty.h>
20#include <linux/tty_flip.h>
21#include <linux/major.h>
22#include <linux/string.h>
23#include <linux/fcntl.h>
24#include <linux/mm.h>
25#include <linux/slab.h>
26#include <linux/init.h>
1da177e4 27#include <linux/kernel.h>
f392ecfa 28#include <linux/mutex.h>
1977f032 29#include <linux/bitops.h>
9e040a3e
JN		 30#include <linux/seq_file.h>
31#include <linux/delay.h>
9e040a3e
JN		 32#include <linux/uaccess.h>
33#include <linux/io.h>
1da177e4 34
1da177e4 35#include <asm/irq.h>
77accbf5 36#include <asm/dma.h>
1da177e4 37
556dcee7 38#include <arch/svinto.h>
b1a154db 39#include <arch/system.h>
1da177e4
LT		 40
41/* non-arch dependent serial structures are in linux/serial.h */
42#include <linux/serial.h>
43/* while we keep our own stuff (struct e100_serial) in a local .h file */
77accbf5 44#include "crisv10.h"
1da177e4 45#include <asm/fasttimer.h>
556dcee7 46#include <arch/io_interface_mux.h>
1da177e4
LT		 47
48#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
49#ifndef CONFIG_ETRAX_FAST_TIMER
50#error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
51#endif
52#endif
53
54#if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
55 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
56#error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
57#endif
58
1da177e4
LT		 59/*
60 * All of the compatibilty code so we can compile serial.c against
61 * older kernels is hidden in serial_compat.h
62 */
63#if defined(LOCAL_HEADERS)
64#include "serial_compat.h"
65#endif
66
1da177e4
LT		 67struct tty_driver *serial_driver;
68
1da177e4
LT		 69/* number of characters left in xmit buffer before we ask for more */
70#define WAKEUP_CHARS 256
71
72//#define SERIAL_DEBUG_INTR
73//#define SERIAL_DEBUG_OPEN
74//#define SERIAL_DEBUG_FLOW
75//#define SERIAL_DEBUG_DATA
76//#define SERIAL_DEBUG_THROTTLE
77//#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
78//#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
79
80/* Enable this to use serial interrupts to handle when you
81 expect the first received event on the serial port to
82 be an error, break or similar. Used to be able to flash IRMA
83 from eLinux */
84#define SERIAL_HANDLE_EARLY_ERRORS
85
1da177e4
LT		 86/* Currently 16 descriptors x 128 bytes = 2048 bytes */
87#define SERIAL_DESCR_BUF_SIZE 256
88
89#define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
90#define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
91
92/* We don't want to load the system with massive fast timer interrupt
93 * on high baudrates so limit it to 250 us (4kHz) */
94#define MIN_FLUSH_TIME_USEC 250
95
96/* Add an x here to log a lot of timer stuff */
97#define TIMERD(x)
98/* Debug details of interrupt handling */
99#define DINTR1(x) /* irq on/off, errors */
100#define DINTR2(x) /* tx and rx */
101/* Debug flip buffer stuff */
102#define DFLIP(x)
103/* Debug flow control and overview of data flow */
104#define DFLOW(x)
105#define DBAUD(x)
106#define DLOG_INT_TRIG(x)
107
108//#define DEBUG_LOG_INCLUDED
109#ifndef DEBUG_LOG_INCLUDED
110#define DEBUG_LOG(line, string, value)
111#else
112struct debug_log_info
113{
114 unsigned long time;
115 unsigned long timer_data;
116// int line;
117 const char *string;
118 int value;
119};
120#define DEBUG_LOG_SIZE 4096
121
122struct debug_log_info debug_log[DEBUG_LOG_SIZE];
123int debug_log_pos = 0;
124
125#define DEBUG_LOG(_line, _string, _value) do { \
126 if ((_line) == SERIAL_DEBUG_LINE) {\
127 debug_log_func(_line, _string, _value); \
128 }\
129}while(0)
130
131void debug_log_func(int line, const char *string, int value)
132{
133 if (debug_log_pos < DEBUG_LOG_SIZE) {
134 debug_log[debug_log_pos].time = jiffies;
135 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
136// debug_log[debug_log_pos].line = line;
137 debug_log[debug_log_pos].string = string;
138 debug_log[debug_log_pos].value = value;
139 debug_log_pos++;
140 }
141 /*printk(string, value);*/
142}
143#endif
144
145#ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
146/* Default number of timer ticks before flushing rx fifo
147 * When using "little data, low latency applications: use 0
148 * When using "much data applications (PPP)" use ~5
149 */
150#define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
151#endif
152
153unsigned long timer_data_to_ns(unsigned long timer_data);
154
155static void change_speed(struct e100_serial *info);
156static void rs_throttle(struct tty_struct * tty);
157static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
77accbf5
JN		 158static int rs_write(struct tty_struct *tty,
159 const unsigned char *buf, int count);
1da177e4 160#ifdef CONFIG_ETRAX_RS485
77accbf5
JN		 161static int e100_write_rs485(struct tty_struct *tty,
162 const unsigned char *buf, int count);
1da177e4 163#endif
77accbf5 164static int get_lsr_info(struct e100_serial *info, unsigned int *value);
1da177e4
LT		 165
166
167#define DEF_BAUD 115200 /* 115.2 kbit/s */
1da177e4
LT		 168#define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
169/* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
170#define DEF_TX 0x80 /* or SERIAL_CTRL_B */
171
172/* offsets from R_SERIALx_CTRL */
173
174#define REG_DATA 0
175#define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
176#define REG_TR_DATA 0
177#define REG_STATUS 1
178#define REG_TR_CTRL 1
179#define REG_REC_CTRL 2
180#define REG_BAUD 3
181#define REG_XOFF 4 /* this is a 32 bit register */
182
183/* The bitfields are the same for all serial ports */
184#define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
185#define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
186#define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
187#define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
188#define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
189
190#define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
191
192/* Values for info->errorcode */
193#define ERRCODE_SET_BREAK (TTY_BREAK)
194#define ERRCODE_INSERT 0x100
195#define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
196
197#define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
198
199/*
200 * General note regarding the use of IO_* macros in this file:
201 *
202 * We will use the bits defined for DMA channel 6 when using various
203 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
204 * the same for all channels (which of course they are).
205 *
206 * We will also use the bits defined for serial port 0 when writing commands
207 * to the different ports, as these bits too are the same for all ports.
208 */
209
210
211/* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
212static const unsigned long e100_ser_int_mask = 0
213#ifdef CONFIG_ETRAX_SERIAL_PORT0
214| IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
215#endif
216#ifdef CONFIG_ETRAX_SERIAL_PORT1
217| IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
218#endif
219#ifdef CONFIG_ETRAX_SERIAL_PORT2
220| IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
221#endif
222#ifdef CONFIG_ETRAX_SERIAL_PORT3
223| IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
224#endif
225;
226unsigned long r_alt_ser_baudrate_shadow = 0;
227
228/* this is the data for the four serial ports in the etrax100 */
229/* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
230/* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
231
232static struct e100_serial rs_table[] = {
233 { .baud = DEF_BAUD,
d7283353 234 .ioport = (unsigned char *)R_SERIAL0_CTRL,
1da177e4
LT		 235 .irq = 1U << 12, /* uses DMA 6 and 7 */
236 .oclrintradr = R_DMA_CH6_CLR_INTR,
237 .ofirstadr = R_DMA_CH6_FIRST,
238 .ocmdadr = R_DMA_CH6_CMD,
239 .ostatusadr = R_DMA_CH6_STATUS,
240 .iclrintradr = R_DMA_CH7_CLR_INTR,
241 .ifirstadr = R_DMA_CH7_FIRST,
242 .icmdadr = R_DMA_CH7_CMD,
243 .idescradr = R_DMA_CH7_DESCR,
1da177e4
LT		 244 .rx_ctrl = DEF_RX,
245 .tx_ctrl = DEF_TX,
246 .iseteop = 2,
77accbf5
JN		 247 .dma_owner = dma_ser0,
248 .io_if = if_serial_0,
1da177e4
LT		 249#ifdef CONFIG_ETRAX_SERIAL_PORT0
250 .enabled = 1,
251#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
252 .dma_out_enabled = 1,
77accbf5
JN		 253 .dma_out_nbr = SER0_TX_DMA_NBR,
254 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
9cfb5c05 255 .dma_out_irq_flags = 0,
77accbf5 256 .dma_out_irq_description = "serial 0 dma tr",
1da177e4
LT		 257#else
258 .dma_out_enabled = 0,
77accbf5
JN		 259 .dma_out_nbr = UINT_MAX,
260 .dma_out_irq_nbr = 0,
261 .dma_out_irq_flags = 0,
262 .dma_out_irq_description = NULL,
1da177e4
LT		 263#endif
264#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
265 .dma_in_enabled = 1,
77accbf5
JN		 266 .dma_in_nbr = SER0_RX_DMA_NBR,
267 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
9cfb5c05 268 .dma_in_irq_flags = 0,
77accbf5 269 .dma_in_irq_description = "serial 0 dma rec",
1da177e4 270#else
77accbf5
JN		 271 .dma_in_enabled = 0,
272 .dma_in_nbr = UINT_MAX,
273 .dma_in_irq_nbr = 0,
274 .dma_in_irq_flags = 0,
275 .dma_in_irq_description = NULL,
1da177e4
LT		 276#endif
277#else
278 .enabled = 0,
77accbf5 279 .io_if_description = NULL,
1da177e4
LT		 280 .dma_out_enabled = 0,
281 .dma_in_enabled = 0
282#endif
283
284}, /* ttyS0 */
1da177e4 285 { .baud = DEF_BAUD,
d7283353 286 .ioport = (unsigned char *)R_SERIAL1_CTRL,
1da177e4
LT		 287 .irq = 1U << 16, /* uses DMA 8 and 9 */
288 .oclrintradr = R_DMA_CH8_CLR_INTR,
289 .ofirstadr = R_DMA_CH8_FIRST,
290 .ocmdadr = R_DMA_CH8_CMD,
291 .ostatusadr = R_DMA_CH8_STATUS,
292 .iclrintradr = R_DMA_CH9_CLR_INTR,
293 .ifirstadr = R_DMA_CH9_FIRST,
294 .icmdadr = R_DMA_CH9_CMD,
295 .idescradr = R_DMA_CH9_DESCR,
1da177e4
LT		 296 .rx_ctrl = DEF_RX,
297 .tx_ctrl = DEF_TX,
298 .iseteop = 3,
77accbf5
JN		 299 .dma_owner = dma_ser1,
300 .io_if = if_serial_1,
1da177e4
LT		 301#ifdef CONFIG_ETRAX_SERIAL_PORT1
302 .enabled = 1,
77accbf5 303 .io_if_description = "ser1",
1da177e4
LT		 304#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
305 .dma_out_enabled = 1,
77accbf5
JN		 306 .dma_out_nbr = SER1_TX_DMA_NBR,
307 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
9cfb5c05 308 .dma_out_irq_flags = 0,
77accbf5 309 .dma_out_irq_description = "serial 1 dma tr",
1da177e4
LT		 310#else
311 .dma_out_enabled = 0,
77accbf5
JN		 312 .dma_out_nbr = UINT_MAX,
313 .dma_out_irq_nbr = 0,
314 .dma_out_irq_flags = 0,
315 .dma_out_irq_description = NULL,
1da177e4
LT		 316#endif
317#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
318 .dma_in_enabled = 1,
77accbf5
JN		 319 .dma_in_nbr = SER1_RX_DMA_NBR,
320 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
9cfb5c05 321 .dma_in_irq_flags = 0,
77accbf5 322 .dma_in_irq_description = "serial 1 dma rec",
1da177e4 323#else
77accbf5
JN		 324 .dma_in_enabled = 0,
325 .dma_in_enabled = 0,
326 .dma_in_nbr = UINT_MAX,
327 .dma_in_irq_nbr = 0,
328 .dma_in_irq_flags = 0,
329 .dma_in_irq_description = NULL,
1da177e4
LT		 330#endif
331#else
332 .enabled = 0,
77accbf5
JN		 333 .io_if_description = NULL,
334 .dma_in_irq_nbr = 0,
1da177e4
LT		 335 .dma_out_enabled = 0,
336 .dma_in_enabled = 0
337#endif
338}, /* ttyS1 */
339
340 { .baud = DEF_BAUD,
d7283353 341 .ioport = (unsigned char *)R_SERIAL2_CTRL,
1da177e4
LT		 342 .irq = 1U << 4, /* uses DMA 2 and 3 */
343 .oclrintradr = R_DMA_CH2_CLR_INTR,
344 .ofirstadr = R_DMA_CH2_FIRST,
345 .ocmdadr = R_DMA_CH2_CMD,
346 .ostatusadr = R_DMA_CH2_STATUS,
347 .iclrintradr = R_DMA_CH3_CLR_INTR,
348 .ifirstadr = R_DMA_CH3_FIRST,
349 .icmdadr = R_DMA_CH3_CMD,
350 .idescradr = R_DMA_CH3_DESCR,
1da177e4
LT		 351 .rx_ctrl = DEF_RX,
352 .tx_ctrl = DEF_TX,
353 .iseteop = 0,
77accbf5
JN		 354 .dma_owner = dma_ser2,
355 .io_if = if_serial_2,
1da177e4
LT		 356#ifdef CONFIG_ETRAX_SERIAL_PORT2
357 .enabled = 1,
77accbf5 358 .io_if_description = "ser2",
1da177e4
LT		 359#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
360 .dma_out_enabled = 1,
77accbf5
JN		 361 .dma_out_nbr = SER2_TX_DMA_NBR,
362 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
9cfb5c05 363 .dma_out_irq_flags = 0,
77accbf5 364 .dma_out_irq_description = "serial 2 dma tr",
1da177e4
LT		 365#else
366 .dma_out_enabled = 0,
77accbf5
JN		 367 .dma_out_nbr = UINT_MAX,
368 .dma_out_irq_nbr = 0,
369 .dma_out_irq_flags = 0,
370 .dma_out_irq_description = NULL,
1da177e4
LT		 371#endif
372#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
373 .dma_in_enabled = 1,
77accbf5
JN		 374 .dma_in_nbr = SER2_RX_DMA_NBR,
375 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
9cfb5c05 376 .dma_in_irq_flags = 0,
77accbf5 377 .dma_in_irq_description = "serial 2 dma rec",
1da177e4 378#else
77accbf5
JN		 379 .dma_in_enabled = 0,
380 .dma_in_nbr = UINT_MAX,
381 .dma_in_irq_nbr = 0,
382 .dma_in_irq_flags = 0,
383 .dma_in_irq_description = NULL,
1da177e4
LT		 384#endif
385#else
386 .enabled = 0,
77accbf5 387 .io_if_description = NULL,
1da177e4
LT		 388 .dma_out_enabled = 0,
389 .dma_in_enabled = 0
390#endif
391 }, /* ttyS2 */
392
393 { .baud = DEF_BAUD,
d7283353 394 .ioport = (unsigned char *)R_SERIAL3_CTRL,
1da177e4
LT		 395 .irq = 1U << 8, /* uses DMA 4 and 5 */
396 .oclrintradr = R_DMA_CH4_CLR_INTR,
397 .ofirstadr = R_DMA_CH4_FIRST,
398 .ocmdadr = R_DMA_CH4_CMD,
399 .ostatusadr = R_DMA_CH4_STATUS,
400 .iclrintradr = R_DMA_CH5_CLR_INTR,
401 .ifirstadr = R_DMA_CH5_FIRST,
402 .icmdadr = R_DMA_CH5_CMD,
403 .idescradr = R_DMA_CH5_DESCR,
1da177e4
LT		 404 .rx_ctrl = DEF_RX,
405 .tx_ctrl = DEF_TX,
406 .iseteop = 1,
77accbf5
JN		 407 .dma_owner = dma_ser3,
408 .io_if = if_serial_3,
1da177e4
LT		 409#ifdef CONFIG_ETRAX_SERIAL_PORT3
410 .enabled = 1,
77accbf5 411 .io_if_description = "ser3",
1da177e4
LT		 412#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
413 .dma_out_enabled = 1,
77accbf5
JN		 414 .dma_out_nbr = SER3_TX_DMA_NBR,
415 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
9cfb5c05 416 .dma_out_irq_flags = 0,
77accbf5 417 .dma_out_irq_description = "serial 3 dma tr",
1da177e4
LT		 418#else
419 .dma_out_enabled = 0,
77accbf5
JN		 420 .dma_out_nbr = UINT_MAX,
421 .dma_out_irq_nbr = 0,
422 .dma_out_irq_flags = 0,
423 .dma_out_irq_description = NULL,
1da177e4
LT		 424#endif
425#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
426 .dma_in_enabled = 1,
77accbf5
JN		 427 .dma_in_nbr = SER3_RX_DMA_NBR,
428 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
9cfb5c05 429 .dma_in_irq_flags = 0,
77accbf5 430 .dma_in_irq_description = "serial 3 dma rec",
1da177e4 431#else
77accbf5
JN		 432 .dma_in_enabled = 0,
433 .dma_in_nbr = UINT_MAX,
434 .dma_in_irq_nbr = 0,
435 .dma_in_irq_flags = 0,
436 .dma_in_irq_description = NULL
1da177e4
LT		 437#endif
438#else
439 .enabled = 0,
77accbf5 440 .io_if_description = NULL,
1da177e4
LT		 441 .dma_out_enabled = 0,
442 .dma_in_enabled = 0
443#endif
444 } /* ttyS3 */
1da177e4
LT		 445};
446
447
448#define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
449
1da177e4
LT		 450#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
451static struct fast_timer fast_timers[NR_PORTS];
452#endif
453
1da177e4
LT		 454/* RS-485 */
455#if defined(CONFIG_ETRAX_RS485)
456#ifdef CONFIG_ETRAX_FAST_TIMER
457static struct fast_timer fast_timers_rs485[NR_PORTS];
458#endif
459#if defined(CONFIG_ETRAX_RS485_ON_PA)
460static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
461#endif
1da177e4
LT		 462#endif
463
464/* Info and macros needed for each ports extra control/status signals. */
465#define E100_STRUCT_PORT(line, pinname) \
466 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
467 (R_PORT_PA_DATA): ( \
468 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
469 (R_PORT_PB_DATA):&dummy_ser[line]))
470
471#define E100_STRUCT_SHADOW(line, pinname) \
472 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
473 (&port_pa_data_shadow): ( \
474 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
475 (&port_pb_data_shadow):&dummy_ser[line]))
476#define E100_STRUCT_MASK(line, pinname) \
477 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
478 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
479 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
480 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
481
482#define DUMMY_DTR_MASK 1
483#define DUMMY_RI_MASK 2
484#define DUMMY_DSR_MASK 4
485#define DUMMY_CD_MASK 8
486static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
487
488/* If not all status pins are used or disabled, use mixed mode */
489#ifdef CONFIG_ETRAX_SERIAL_PORT0
490
491#define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
492
493#if SER0_PA_BITSUM != -4
494# if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
495# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
496# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
497# endif
498# endif
499# if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
500# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
501# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
502# endif
503# endif
504# if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
505# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
506# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
507# endif
508# endif
509# if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
510# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
511# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
512# endif
513# endif
514#endif
515
516#define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
517
518#if SER0_PB_BITSUM != -4
519# if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
520# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
521# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
522# endif
523# endif
524# if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
525# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
526# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
527# endif
528# endif
529# if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
530# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
531# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
532# endif
533# endif
534# if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
535# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
536# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
537# endif
538# endif
539#endif
540
541#endif /* PORT0 */
542
543
544#ifdef CONFIG_ETRAX_SERIAL_PORT1
545
546#define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
547
548#if SER1_PA_BITSUM != -4
549# if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
550# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
551# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
552# endif
553# endif
554# if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
555# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
556# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
557# endif
558# endif
559# if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
560# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
561# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
562# endif
563# endif
564# if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
565# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
566# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
567# endif
568# endif
569#endif
570
571#define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
572
573#if SER1_PB_BITSUM != -4
574# if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
575# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
576# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
577# endif
578# endif
579# if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
580# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
581# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
582# endif
583# endif
584# if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
585# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
586# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
587# endif
588# endif
589# if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
590# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
591# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
592# endif
593# endif
594#endif
595
596#endif /* PORT1 */
597
598#ifdef CONFIG_ETRAX_SERIAL_PORT2
599
600#define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
601
602#if SER2_PA_BITSUM != -4
603# if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
604# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
605# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
606# endif
607# endif
608# if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
609# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
610# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
611# endif
612# endif
613# if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
614# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
615# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
616# endif
617# endif
618# if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
619# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
620# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
621# endif
622# endif
623#endif
624
625#define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
626
627#if SER2_PB_BITSUM != -4
628# if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
629# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
630# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
631# endif
632# endif
633# if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
634# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
635# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
636# endif
637# endif
638# if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
639# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
640# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
641# endif
642# endif
643# if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
644# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
645# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
646# endif
647# endif
648#endif
649
650#endif /* PORT2 */
651
652#ifdef CONFIG_ETRAX_SERIAL_PORT3
653
654#define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
655
656#if SER3_PA_BITSUM != -4
657# if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
658# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
659# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
660# endif
661# endif
662# if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
663# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
664# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
665# endif
666# endif
667# if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
668# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
669# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
670# endif
671# endif
672# if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
673# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
674# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
675# endif
676# endif
677#endif
678
679#define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
680
681#if SER3_PB_BITSUM != -4
682# if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
683# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
684# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
685# endif
686# endif
687# if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
688# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
689# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
690# endif
691# endif
692# if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
693# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
694# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
695# endif
696# endif
697# if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
698# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
699# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
700# endif
701# endif
702#endif
703
704#endif /* PORT3 */
705
706
707#if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
708 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
709 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
710 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
74a76089 711#define ETRAX_SERX_DTR_RI_DSR_CD_MIXED
1da177e4
LT		 712#endif
713
74a76089 714#ifdef ETRAX_SERX_DTR_RI_DSR_CD_MIXED
1da177e4
LT		 715/* The pins can be mixed on PA and PB */
716#define CONTROL_PINS_PORT_NOT_USED(line) \
717 &dummy_ser[line], &dummy_ser[line], \
718 &dummy_ser[line], &dummy_ser[line], \
719 &dummy_ser[line], &dummy_ser[line], \
720 &dummy_ser[line], &dummy_ser[line], \
721 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
722
723
724struct control_pins
725{
726 volatile unsigned char *dtr_port;
727 unsigned char *dtr_shadow;
728 volatile unsigned char *ri_port;
729 unsigned char *ri_shadow;
730 volatile unsigned char *dsr_port;
731 unsigned char *dsr_shadow;
732 volatile unsigned char *cd_port;
733 unsigned char *cd_shadow;
734
735 unsigned char dtr_mask;
736 unsigned char ri_mask;
737 unsigned char dsr_mask;
738 unsigned char cd_mask;
739};
740
741static const struct control_pins e100_modem_pins[NR_PORTS] =
742{
743 /* Ser 0 */
744 {
745#ifdef CONFIG_ETRAX_SERIAL_PORT0
746 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
747 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
748 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
749 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
750 E100_STRUCT_MASK(0,DTR),
751 E100_STRUCT_MASK(0,RI),
752 E100_STRUCT_MASK(0,DSR),
753 E100_STRUCT_MASK(0,CD)
754#else
755 CONTROL_PINS_PORT_NOT_USED(0)
756#endif
757 },
758
759 /* Ser 1 */
760 {
761#ifdef CONFIG_ETRAX_SERIAL_PORT1
762 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
763 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
764 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
765 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
766 E100_STRUCT_MASK(1,DTR),
767 E100_STRUCT_MASK(1,RI),
768 E100_STRUCT_MASK(1,DSR),
769 E100_STRUCT_MASK(1,CD)
770#else
771 CONTROL_PINS_PORT_NOT_USED(1)
772#endif
773 },
774
775 /* Ser 2 */
776 {
777#ifdef CONFIG_ETRAX_SERIAL_PORT2
778 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
779 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
780 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
781 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
782 E100_STRUCT_MASK(2,DTR),
783 E100_STRUCT_MASK(2,RI),
784 E100_STRUCT_MASK(2,DSR),
785 E100_STRUCT_MASK(2,CD)
786#else
787 CONTROL_PINS_PORT_NOT_USED(2)
788#endif
789 },
790
791 /* Ser 3 */
792 {
793#ifdef CONFIG_ETRAX_SERIAL_PORT3
794 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
795 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
796 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
797 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
798 E100_STRUCT_MASK(3,DTR),
799 E100_STRUCT_MASK(3,RI),
800 E100_STRUCT_MASK(3,DSR),
801 E100_STRUCT_MASK(3,CD)
802#else
803 CONTROL_PINS_PORT_NOT_USED(3)
804#endif
805 }
806};
74a76089 807#else /* ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
1da177e4
LT		 808
809/* All pins are on either PA or PB for each serial port */
810#define CONTROL_PINS_PORT_NOT_USED(line) \
811 &dummy_ser[line], &dummy_ser[line], \
812 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
813
814
815struct control_pins
816{
817 volatile unsigned char *port;
818 unsigned char *shadow;
819
820 unsigned char dtr_mask;
821 unsigned char ri_mask;
822 unsigned char dsr_mask;
823 unsigned char cd_mask;
824};
825
826#define dtr_port port
827#define dtr_shadow shadow
828#define ri_port port
829#define ri_shadow shadow
830#define dsr_port port
831#define dsr_shadow shadow
832#define cd_port port
833#define cd_shadow shadow
834
835static const struct control_pins e100_modem_pins[NR_PORTS] =
836{
837 /* Ser 0 */
838 {
839#ifdef CONFIG_ETRAX_SERIAL_PORT0
840 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
841 E100_STRUCT_MASK(0,DTR),
842 E100_STRUCT_MASK(0,RI),
843 E100_STRUCT_MASK(0,DSR),
844 E100_STRUCT_MASK(0,CD)
845#else
846 CONTROL_PINS_PORT_NOT_USED(0)
847#endif
848 },
849
850 /* Ser 1 */
851 {
852#ifdef CONFIG_ETRAX_SERIAL_PORT1
853 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
854 E100_STRUCT_MASK(1,DTR),
855 E100_STRUCT_MASK(1,RI),
856 E100_STRUCT_MASK(1,DSR),
857 E100_STRUCT_MASK(1,CD)
858#else
859 CONTROL_PINS_PORT_NOT_USED(1)
860#endif
861 },
862
863 /* Ser 2 */
864 {
865#ifdef CONFIG_ETRAX_SERIAL_PORT2
866 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
867 E100_STRUCT_MASK(2,DTR),
868 E100_STRUCT_MASK(2,RI),
869 E100_STRUCT_MASK(2,DSR),
870 E100_STRUCT_MASK(2,CD)
871#else
872 CONTROL_PINS_PORT_NOT_USED(2)
873#endif
874 },
875
876 /* Ser 3 */
877 {
878#ifdef CONFIG_ETRAX_SERIAL_PORT3
879 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
880 E100_STRUCT_MASK(3,DTR),
881 E100_STRUCT_MASK(3,RI),
882 E100_STRUCT_MASK(3,DSR),
883 E100_STRUCT_MASK(3,CD)
884#else
885 CONTROL_PINS_PORT_NOT_USED(3)
886#endif
887 }
888};
74a76089 889#endif /* !ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
1da177e4
LT		 890
891#define E100_RTS_MASK 0x20
892#define E100_CTS_MASK 0x40
893
894/* All serial port signals are active low:
895 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
896 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
897 *
898 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
899 */
900
901/* Output */
902#define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
903/* Input */
d7283353 904#define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
1da177e4
LT		 905
906/* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
907/* Is an output */
908#define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
909
910/* Normally inputs */
911#define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
912#define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
913
914/* Input */
915#define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
916
1da177e4
LT		 917/* Calculate the chartime depending on baudrate, numbor of bits etc. */
918static void update_char_time(struct e100_serial * info)
919{
adc8d746 920 tcflag_t cflags = info->port.tty->termios.c_cflag;
1da177e4
LT		 921 int bits;
922
923 /* calc. number of bits / data byte */
924 /* databits + startbit and 1 stopbit */
925 if ((cflags & CSIZE) == CS7)
926 bits = 9;
927 else
928 bits = 10;
929
930 if (cflags & CSTOPB) /* 2 stopbits ? */
931 bits++;
932
933 if (cflags & PARENB) /* parity bit ? */
934 bits++;
935
936 /* calc timeout */
937 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
938 info->flush_time_usec = 4*info->char_time_usec;
939 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
940 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
941
942}
943
944/*
945 * This function maps from the Bxxxx defines in asm/termbits.h into real
946 * baud rates.
947 */
948
949static int
950cflag_to_baud(unsigned int cflag)
951{
952 static int baud_table[] = {
953 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
954 4800, 9600, 19200, 38400 };
955
956 static int ext_baud_table[] = {
957 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
958 0, 0, 0, 0, 0, 0, 0, 0 };
959
960 if (cflag & CBAUDEX)
961 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
962 else
963 return baud_table[cflag & CBAUD];
964}
965
966/* and this maps to an etrax100 hardware baud constant */
967
968static unsigned char
969cflag_to_etrax_baud(unsigned int cflag)
970{
971 char retval;
972
973 static char baud_table[] = {
974 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
975
976 static char ext_baud_table[] = {
977 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
978
979 if (cflag & CBAUDEX)
980 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
981 else
982 retval = baud_table[cflag & CBAUD];
983
984 if (retval < 0) {
985 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
986 retval = 5; /* choose default 9600 instead */
987 }
988
989 return retval | (retval << 4); /* choose same for both TX and RX */
990}
991
992
993/* Various static support functions */
994
995/* Functions to set or clear DTR/RTS on the requested line */
996/* It is complicated by the fact that RTS is a serial port register, while
997 * DTR might not be implemented in the HW at all, and if it is, it can be on
998 * any general port.
999 */
1000
1001
1002static inline void
1003e100_dtr(struct e100_serial *info, int set)
1004{
1da177e4
LT		 1005 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1006
1007#ifdef SERIAL_DEBUG_IO
1008 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1009 printk("ser%i shadow before 0x%02X get: %i\n",
1010 info->line, *e100_modem_pins[info->line].dtr_shadow,
1011 E100_DTR_GET(info));
1012#endif
1013 /* DTR is active low */
1014 {
1015 unsigned long flags;
1016
77accbf5 1017 local_irq_save(flags);
1da177e4
LT		 1018 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1019 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1020 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
77accbf5 1021 local_irq_restore(flags);
1da177e4
LT		 1022 }
1023
1024#ifdef SERIAL_DEBUG_IO
1025 printk("ser%i shadow after 0x%02X get: %i\n",
1026 info->line, *e100_modem_pins[info->line].dtr_shadow,
1027 E100_DTR_GET(info));
1028#endif
1da177e4
LT		 1029}
1030
1031/* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1032 * 0=0V , 1=3.3V
1033 */
1034static inline void
1035e100_rts(struct e100_serial *info, int set)
1036{
1da177e4 1037 unsigned long flags;
77accbf5 1038 local_irq_save(flags);
1da177e4
LT		 1039 info->rx_ctrl &= ~E100_RTS_MASK;
1040 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
d7283353 1041 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
77accbf5 1042 local_irq_restore(flags);
1da177e4
LT		 1043#ifdef SERIAL_DEBUG_IO
1044 printk("ser%i rts %i\n", info->line, set);
1045#endif
1da177e4
LT		 1046}
1047
1048
1049/* If this behaves as a modem, RI and CD is an output */
1050static inline void
1051e100_ri_out(struct e100_serial *info, int set)
1052{
1da177e4
LT		 1053 /* RI is active low */
1054 {
1055 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1056 unsigned long flags;
1057
77accbf5 1058 local_irq_save(flags);
1da177e4
LT		 1059 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1060 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1061 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
77accbf5 1062 local_irq_restore(flags);
1da177e4 1063 }
1da177e4
LT		 1064}
1065static inline void
1066e100_cd_out(struct e100_serial *info, int set)
1067{
1da177e4
LT		 1068 /* CD is active low */
1069 {
1070 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1071 unsigned long flags;
1072
77accbf5 1073 local_irq_save(flags);
1da177e4
LT		 1074 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1075 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1076 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
77accbf5 1077 local_irq_restore(flags);
1da177e4 1078 }
1da177e4
LT		 1079}
1080
1081static inline void
1082e100_disable_rx(struct e100_serial *info)
1083{
1da177e4 1084 /* disable the receiver */
d7283353 1085 info->ioport[REG_REC_CTRL] =
1da177e4 1086 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1da177e4
LT		 1087}
1088
1089static inline void
1090e100_enable_rx(struct e100_serial *info)
1091{
1da177e4 1092 /* enable the receiver */
d7283353 1093 info->ioport[REG_REC_CTRL] =
1da177e4 1094 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1da177e4
LT		 1095}
1096
1097/* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1098
1099static inline void
1100e100_disable_rxdma_irq(struct e100_serial *info)
1101{
1102#ifdef SERIAL_DEBUG_INTR
1103 printk("rxdma_irq(%d): 0\n",info->line);
1104#endif
1105 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1106 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1107}
1108
1109static inline void
1110e100_enable_rxdma_irq(struct e100_serial *info)
1111{
1112#ifdef SERIAL_DEBUG_INTR
1113 printk("rxdma_irq(%d): 1\n",info->line);
1114#endif
1115 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1116 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1117}
1118
1119/* the tx DMA uses only dma_descr interrupt */
1120
41c28ff1 1121static void e100_disable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1122{
1123#ifdef SERIAL_DEBUG_INTR
1124 printk("txdma_irq(%d): 0\n",info->line);
1125#endif
1126 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1127 *R_IRQ_MASK2_CLR = info->irq;
1128}
1129
41c28ff1 1130static void e100_enable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1131{
1132#ifdef SERIAL_DEBUG_INTR
1133 printk("txdma_irq(%d): 1\n",info->line);
1134#endif
1135 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1136 *R_IRQ_MASK2_SET = info->irq;
1137}
1138
41c28ff1 1139static void e100_disable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1140{
1141 unsigned long flags;
1142
1143 /* Disable output DMA channel for the serial port in question
025dfdaf 1144 * ( set to something other than serialX)
1da177e4 1145 */
77accbf5 1146 local_irq_save(flags);
1da177e4
LT		 1147 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1148 if (info->line == 0) {
1149 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1150 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1151 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1152 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1153 }
1154 } else if (info->line == 1) {
1155 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1156 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1157 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1158 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1159 }
1160 } else if (info->line == 2) {
1161 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1162 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1163 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1164 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1165 }
1166 } else if (info->line == 3) {
1167 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1168 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1169 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1170 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1171 }
1172 }
1173 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1174 local_irq_restore(flags);
1da177e4
LT		 1175}
1176
1177
41c28ff1 1178static void e100_enable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1179{
1180 unsigned long flags;
1181
77accbf5 1182 local_irq_save(flags);
1da177e4
LT		 1183 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1184 /* Enable output DMA channel for the serial port in question */
1185 if (info->line == 0) {
1186 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1187 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1188 } else if (info->line == 1) {
1189 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1190 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1191 } else if (info->line == 2) {
1192 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1193 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1194 } else if (info->line == 3) {
1195 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1196 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1197 }
1198 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1199 local_irq_restore(flags);
1da177e4
LT		 1200}
1201
41c28ff1 1202static void e100_disable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1203{
1204 unsigned long flags;
1205
1206 /* Disable input DMA channel for the serial port in question
025dfdaf 1207 * ( set to something other than serialX)
1da177e4 1208 */
77accbf5 1209 local_irq_save(flags);
1da177e4
LT		 1210 if (info->line == 0) {
1211 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1212 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1213 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1214 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1215 }
1216 } else if (info->line == 1) {
1217 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1218 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1219 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1220 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1221 }
1222 } else if (info->line == 2) {
1223 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1224 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1225 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1226 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1227 }
1228 } else if (info->line == 3) {
1229 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1230 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1231 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1232 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1233 }
1234 }
1235 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1236 local_irq_restore(flags);
1da177e4
LT		 1237}
1238
1239
41c28ff1 1240static void e100_enable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1241{
1242 unsigned long flags;
1243
77accbf5 1244 local_irq_save(flags);
1da177e4
LT		 1245 /* Enable input DMA channel for the serial port in question */
1246 if (info->line == 0) {
1247 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1248 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1249 } else if (info->line == 1) {
1250 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1251 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1252 } else if (info->line == 2) {
1253 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1254 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1255 } else if (info->line == 3) {
1256 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1257 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1258 }
1259 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1260 local_irq_restore(flags);
1da177e4
LT		 1261}
1262
1263#ifdef SERIAL_HANDLE_EARLY_ERRORS
1264/* in order to detect and fix errors on the first byte
1265 we have to use the serial interrupts as well. */
1266
1267static inline void
1268e100_disable_serial_data_irq(struct e100_serial *info)
1269{
1270#ifdef SERIAL_DEBUG_INTR
1271 printk("ser_irq(%d): 0\n",info->line);
1272#endif
1273 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1274 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1275}
1276
1277static inline void
1278e100_enable_serial_data_irq(struct e100_serial *info)
1279{
1280#ifdef SERIAL_DEBUG_INTR
1281 printk("ser_irq(%d): 1\n",info->line);
1282 printk("**** %d = %d\n",
1283 (8+2*info->line),
1284 (1U << (8+2*info->line)));
1285#endif
1286 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1287 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1288}
1289#endif
1290
1291static inline void
1292e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1293{
1294#ifdef SERIAL_DEBUG_INTR
1295 printk("ser_tx_irq(%d): 0\n",info->line);
1296#endif
1297 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1298 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1299}
1300
1301static inline void
1302e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1303{
1304#ifdef SERIAL_DEBUG_INTR
1305 printk("ser_tx_irq(%d): 1\n",info->line);
1306 printk("**** %d = %d\n",
1307 (8+1+2*info->line),
1308 (1U << (8+1+2*info->line)));
1309#endif
1310 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1311 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1312}
1313
1314static inline void e100_enable_rx_irq(struct e100_serial *info)
1315{
1316 if (info->uses_dma_in)
1317 e100_enable_rxdma_irq(info);
1318 else
1319 e100_enable_serial_data_irq(info);
1320}
1321static inline void e100_disable_rx_irq(struct e100_serial *info)
1322{
1323 if (info->uses_dma_in)
1324 e100_disable_rxdma_irq(info);
1325 else
1326 e100_disable_serial_data_irq(info);
1327}
1328
1329#if defined(CONFIG_ETRAX_RS485)
1330/* Enable RS-485 mode on selected port. This is UGLY. */
1331static int
6fd1af4c 1332e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1da177e4
LT		 1333{
1334 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1335
1336#if defined(CONFIG_ETRAX_RS485_ON_PA)
1337 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1338#endif
1da177e4 1339
c7213fc4
JN		 1340 info->rs485 = *r;
1341
1342 /* Maximum delay before RTS equal to 1000 */
1343 if (info->rs485.delay_rts_before_send >= 1000)
1da177e4 1344 info->rs485.delay_rts_before_send = 1000;
c7213fc4 1345
1da177e4
LT		 1346/* printk("rts: on send = %i, after = %i, enabled = %i",
1347 info->rs485.rts_on_send,
1348 info->rs485.rts_after_sent,
1349 info->rs485.enabled
1350 );
1351*/
1352 return 0;
1353}
1354
1355static int
77accbf5 1356e100_write_rs485(struct tty_struct *tty,
1da177e4
LT		 1357 const unsigned char *buf, int count)
1358{
1359 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
6fd1af4c 1360 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1da177e4
LT		 1361
1362 /* rs485 is always implicitly enabled if we're using the ioctl()
6fd1af4c 1363 * but it doesn't have to be set in the serial_rs485
1da177e4
LT		 1364 * (to be backward compatible with old apps)
1365 * So we store, set and restore it.
1366 */
6fd1af4c 1367 info->rs485.flags |= SER_RS485_ENABLED;
1da177e4 1368 /* rs_write now deals with RS485 if enabled */
77accbf5 1369 count = rs_write(tty, buf, count);
6fd1af4c
CS		 1370 if (!old_value)
1371 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4
LT		 1372 return count;
1373}
1374
1375#ifdef CONFIG_ETRAX_FAST_TIMER
1376/* Timer function to toggle RTS when using FAST_TIMER */
1377static void rs485_toggle_rts_timer_function(unsigned long data)
1378{
1379 struct e100_serial *info = (struct e100_serial *)data;
1380
1381 fast_timers_rs485[info->line].function = NULL;
6fd1af4c 1382 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1da177e4
LT		 1383#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1384 e100_enable_rx(info);
1385 e100_enable_rx_irq(info);
1386#endif
1387}
1388#endif
1389#endif /* CONFIG_ETRAX_RS485 */
1390
1391/*
1392 * ------------------------------------------------------------
1393 * rs_stop() and rs_start()
1394 *
1395 * This routines are called before setting or resetting tty->stopped.
1396 * They enable or disable transmitter using the XOFF registers, as necessary.
1397 * ------------------------------------------------------------
1398 */
1399
1400static void
1401rs_stop(struct tty_struct *tty)
1402{
1403 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1404 if (info) {
1405 unsigned long flags;
1406 unsigned long xoff;
1407
77accbf5 1408 local_irq_save(flags);
1da177e4
LT		 1409 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1410 CIRC_CNT(info->xmit.head,
1411 info->xmit.tail,SERIAL_XMIT_SIZE)));
1412
a88487c7
TI		 1413 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1414 STOP_CHAR(info->port.tty));
1da177e4 1415 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
9db276f8 1416 if (I_IXON(tty))
1da177e4 1417 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1da177e4 1418
d7283353 1419 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
77accbf5 1420 local_irq_restore(flags);
1da177e4
LT		 1421 }
1422}
1423
1424static void
1425rs_start(struct tty_struct *tty)
1426{
1427 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1428 if (info) {
1429 unsigned long flags;
1430 unsigned long xoff;
1431
77accbf5 1432 local_irq_save(flags);
1da177e4
LT		 1433 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1434 CIRC_CNT(info->xmit.head,
1435 info->xmit.tail,SERIAL_XMIT_SIZE)));
1436 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1437 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
9db276f8 1438 if (I_IXON(tty))
1da177e4 1439 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1da177e4 1440
d7283353 1441 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1da177e4
LT		 1442 if (!info->uses_dma_out &&
1443 info->xmit.head != info->xmit.tail && info->xmit.buf)
1444 e100_enable_serial_tx_ready_irq(info);
1445
77accbf5 1446 local_irq_restore(flags);
1da177e4
LT		 1447 }
1448}
1449
1450/*
1451 * ----------------------------------------------------------------------
1452 *
1453 * Here starts the interrupt handling routines. All of the following
1454 * subroutines are declared as inline and are folded into
1455 * rs_interrupt(). They were separated out for readability's sake.
1456 *
1457 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1458 * runs with interrupts turned off. People who may want to modify
1459 * rs_interrupt() should try to keep the interrupt handler as fast as
1460 * possible. After you are done making modifications, it is not a bad
1461 * idea to do:
1462 *
1463 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1464 *
1465 * and look at the resulting assemble code in serial.s.
1466 *
1467 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1468 * -----------------------------------------------------------------------
1469 */
1470
1471/*
1472 * This routine is used by the interrupt handler to schedule
1473 * processing in the software interrupt portion of the driver.
1474 */
41c28ff1 1475static void rs_sched_event(struct e100_serial *info, int event)
1da177e4
LT		 1476{
1477 if (info->event & (1 << event))
1478 return;
1479 info->event |= 1 << event;
1480 schedule_work(&info->work);
1481}
1482
1483/* The output DMA channel is free - use it to send as many chars as possible
1484 * NOTES:
1485 * We don't pay attention to info->x_char, which means if the TTY wants to
1486 * use XON/XOFF it will set info->x_char but we won't send any X char!
1487 *
1488 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1489 * buffer containing the X char, and skip updating xmit. We'd also have to
1490 * check if the last sent char was the X char when we enter this function
1491 * the next time, to avoid updating xmit with the sent X value.
1492 */
1493
1494static void
1495transmit_chars_dma(struct e100_serial *info)
1496{
1497 unsigned int c, sentl;
1498 struct etrax_dma_descr *descr;
1499
1da177e4
LT		 1500 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1501 *info->oclrintradr =
1502 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1503 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1504
1505#ifdef SERIAL_DEBUG_INTR
1506 if (info->line == SERIAL_DEBUG_LINE)
1507 printk("tc\n");
1508#endif
1509 if (!info->tr_running) {
1510 /* weirdo... we shouldn't get here! */
1511 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1512 return;
1513 }
1514
1515 descr = &info->tr_descr;
1516
1517 /* first get the amount of bytes sent during the last DMA transfer,
1518 and update xmit accordingly */
1519
1520 /* if the stop bit was not set, all data has been sent */
1521 if (!(descr->status & d_stop)) {
1522 sentl = descr->sw_len;
1523 } else
1524 /* otherwise we find the amount of data sent here */
1525 sentl = descr->hw_len;
1526
1527 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1528
1529 /* update stats */
1530 info->icount.tx += sentl;
1531
1532 /* update xmit buffer */
1533 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1534
1535 /* if there is only a few chars left in the buf, wake up the blocked
1536 write if any */
1537 if (CIRC_CNT(info->xmit.head,
1538 info->xmit.tail,
1539 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1540 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1541
1542 /* find out the largest amount of consecutive bytes we want to send now */
1543
1544 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1545
1546 /* Don't send all in one DMA transfer - divide it so we wake up
1547 * application before all is sent
1548 */
1549
1550 if (c >= 4*WAKEUP_CHARS)
1551 c = c/2;
1552
1553 if (c <= 0) {
1554 /* our job here is done, don't schedule any new DMA transfer */
1555 info->tr_running = 0;
1556
1557#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
6fd1af4c 1558 if (info->rs485.flags & SER_RS485_ENABLED) {
1da177e4
LT		 1559 /* Set a short timer to toggle RTS */
1560 start_one_shot_timer(&fast_timers_rs485[info->line],
1561 rs485_toggle_rts_timer_function,
1562 (unsigned long)info,
1563 info->char_time_usec*2,
1564 "RS-485");
1565 }
1566#endif /* RS485 */
1567 return;
1568 }
1569
1570 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1571 /* set up the descriptor correctly for output */
1572 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1573 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1574 descr->sw_len = c;
1575 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1576 descr->status = 0;
1577
1578 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1579 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1580
1581 /* DMA is now running (hopefully) */
1582} /* transmit_chars_dma */
1583
1584static void
1585start_transmit(struct e100_serial *info)
1586{
1587#if 0
1588 if (info->line == SERIAL_DEBUG_LINE)
1589 printk("x\n");
1590#endif
1591
1592 info->tr_descr.sw_len = 0;
1593 info->tr_descr.hw_len = 0;
1594 info->tr_descr.status = 0;
1595 info->tr_running = 1;
1596 if (info->uses_dma_out)
1597 transmit_chars_dma(info);
1598 else
1599 e100_enable_serial_tx_ready_irq(info);
1600} /* start_transmit */
1601
1602#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1603static int serial_fast_timer_started = 0;
1604static int serial_fast_timer_expired = 0;
1605static void flush_timeout_function(unsigned long data);
1606#define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1607 unsigned long timer_flags; \
77accbf5 1608 local_irq_save(timer_flags); \
1da177e4
LT		 1609 if (fast_timers[info->line].function == NULL) { \
1610 serial_fast_timer_started++; \
1611 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1612 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1613 start_one_shot_timer(&fast_timers[info->line], \
1614 flush_timeout_function, \
1615 (unsigned long)info, \
1616 (usec), \
1617 string); \
1618 } \
1619 else { \
1620 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1621 } \
77accbf5 1622 local_irq_restore(timer_flags); \
1da177e4
LT		 1623}
1624#define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1625
1626#else
1627#define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1628#define START_FLUSH_FAST_TIMER(info, string)
1629#endif
1630
1631static struct etrax_recv_buffer *
1632alloc_recv_buffer(unsigned int size)
1633{
1634 struct etrax_recv_buffer *buffer;
1635
9ff46047
GKH		 1636 buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC);
1637 if (!buffer)
1da177e4
LT		 1638 return NULL;
1639
1640 buffer->next = NULL;
1641 buffer->length = 0;
1642 buffer->error = TTY_NORMAL;
1643
1644 return buffer;
1645}
1646
1647static void
1648append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1649{
1650 unsigned long flags;
1651
77accbf5 1652 local_irq_save(flags);
1da177e4
LT		 1653
1654 if (!info->first_recv_buffer)
1655 info->first_recv_buffer = buffer;
1656 else
1657 info->last_recv_buffer->next = buffer;
1658
1659 info->last_recv_buffer = buffer;
1660
1661 info->recv_cnt += buffer->length;
1662 if (info->recv_cnt > info->max_recv_cnt)
1663 info->max_recv_cnt = info->recv_cnt;
1664
77accbf5 1665 local_irq_restore(flags);
1da177e4
LT		 1666}
1667
1668static int
1669add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1670{
1671 struct etrax_recv_buffer *buffer;
1672 if (info->uses_dma_in) {
9ff46047
GKH		 1673 buffer = alloc_recv_buffer(4);
1674 if (!buffer)
1da177e4
LT		 1675 return 0;
1676
1677 buffer->length = 1;
1678 buffer->error = flag;
1679 buffer->buffer[0] = data;
1680
1681 append_recv_buffer(info, buffer);
1682
1683 info->icount.rx++;
1684 } else {
92a19f9c 1685 tty_insert_flip_char(&info->port, data, flag);
1da177e4
LT		 1686 info->icount.rx++;
1687 }
1688
1689 return 1;
1690}
1691
41c28ff1
AB		 1692static unsigned int handle_descr_data(struct e100_serial *info,
1693 struct etrax_dma_descr *descr,
1694 unsigned int recvl)
1da177e4
LT		 1695{
1696 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1697
1698 if (info->recv_cnt + recvl > 65536) {
3d43b7d5 1699 printk(KERN_WARNING
71cc2c21 1700 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1da177e4
LT		 1701 return 0;
1702 }
1703
1704 buffer->length = recvl;
1705
1706 if (info->errorcode == ERRCODE_SET_BREAK)
1707 buffer->error = TTY_BREAK;
1708 info->errorcode = 0;
1709
1710 append_recv_buffer(info, buffer);
1711
9ff46047
GKH		 1712 buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE);
1713 if (!buffer)
71cc2c21 1714 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1da177e4
LT		 1715
1716 descr->buf = virt_to_phys(buffer->buffer);
1717
1718 return recvl;
1719}
1720
41c28ff1 1721static unsigned int handle_all_descr_data(struct e100_serial *info)
1da177e4
LT		 1722{
1723 struct etrax_dma_descr *descr;
1724 unsigned int recvl;
1725 unsigned int ret = 0;
1726
1727 while (1)
1728 {
1729 descr = &info->rec_descr[info->cur_rec_descr];
1730
1731 if (descr == phys_to_virt(*info->idescradr))
1732 break;
1733
1734 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1735 info->cur_rec_descr = 0;
1736
1737 /* find out how many bytes were read */
1738
1739 /* if the eop bit was not set, all data has been received */
1740 if (!(descr->status & d_eop)) {
1741 recvl = descr->sw_len;
1742 } else {
1743 /* otherwise we find the amount of data received here */
1744 recvl = descr->hw_len;
1745 }
1746
1747 /* Reset the status information */
1748 descr->status = 0;
1749
1750 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
a88487c7 1751 if (info->port.tty->stopped) {
1da177e4
LT		 1752 unsigned char *buf = phys_to_virt(descr->buf);
1753 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1754 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1755 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1756 }
1757 );
1758
1759 /* update stats */
1760 info->icount.rx += recvl;
1761
1762 ret += handle_descr_data(info, descr, recvl);
1763 }
1764
1765 return ret;
1766}
1767
41c28ff1 1768static void receive_chars_dma(struct e100_serial *info)
1da177e4
LT		 1769{
1770 struct tty_struct *tty;
1771 unsigned char rstat;
1772
1da177e4
LT		 1773 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1774 *info->iclrintradr =
1775 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1776 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1777
a88487c7 1778 tty = info->port.tty;
1da177e4
LT		 1779 if (!tty) /* Something wrong... */
1780 return;
1781
1782#ifdef SERIAL_HANDLE_EARLY_ERRORS
1783 if (info->uses_dma_in)
1784 e100_enable_serial_data_irq(info);
1785#endif
1786
1787 if (info->errorcode == ERRCODE_INSERT_BREAK)
1788 add_char_and_flag(info, '\0', TTY_BREAK);
1789
1790 handle_all_descr_data(info);
1791
1792 /* Read the status register to detect errors */
d7283353 1793 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 1794 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1795 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1796 }
1797
1798 if (rstat & SER_ERROR_MASK) {
1799 /* If we got an error, we must reset it by reading the
1800 * data_in field
1801 */
d7283353 1802 unsigned char data = info->ioport[REG_DATA];
1da177e4 1803
1da177e4
LT		 1804 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1805 ((rstat & SER_ERROR_MASK) << 8) | data);
1806
1807 if (rstat & SER_PAR_ERR_MASK)
1808 add_char_and_flag(info, data, TTY_PARITY);
1809 else if (rstat & SER_OVERRUN_MASK)
1810 add_char_and_flag(info, data, TTY_OVERRUN);
1811 else if (rstat & SER_FRAMING_ERR_MASK)
1812 add_char_and_flag(info, data, TTY_FRAME);
1813 }
1814
1815 START_FLUSH_FAST_TIMER(info, "receive_chars");
1816
1817 /* Restart the receiving DMA */
1818 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1819}
1820
41c28ff1 1821static int start_recv_dma(struct e100_serial *info)
1da177e4
LT		 1822{
1823 struct etrax_dma_descr *descr = info->rec_descr;
1824 struct etrax_recv_buffer *buffer;
1825 int i;
1826
1827 /* Set up the receiving descriptors */
1828 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
9ff46047
GKH		 1829 buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE);
1830 if (!buffer)
71cc2c21 1831 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1da177e4
LT		 1832
1833 descr[i].ctrl = d_int;
1834 descr[i].buf = virt_to_phys(buffer->buffer);
1835 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1836 descr[i].hw_len = 0;
1837 descr[i].status = 0;
1838 descr[i].next = virt_to_phys(&descr[i+1]);
1839 }
1840
1841 /* Link the last descriptor to the first */
1842 descr[i-1].next = virt_to_phys(&descr[0]);
1843
1844 /* Start with the first descriptor in the list */
1845 info->cur_rec_descr = 0;
1846
1847 /* Start the DMA */
1848 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1849 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1850
1851 /* Input DMA should be running now */
1852 return 1;
1853}
1854
1855static void
1856start_receive(struct e100_serial *info)
1857{
1da177e4
LT		 1858 if (info->uses_dma_in) {
1859 /* reset the input dma channel to be sure it works */
1860
1861 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1862 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1863 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1864
1865 start_recv_dma(info);
1866 }
1867}
1868
1869
1da177e4
LT		 1870/* the bits in the MASK2 register are laid out like this:
1871 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1872 where I is the input channel and O is the output channel for the port.
1873 info->irq is the bit number for the DMAO_DESCR so to check the others we
1874 shift info->irq to the left.
1875*/
1876
1877/* dma output channel interrupt handler
1878 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1879 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1880*/
1881
1882static irqreturn_t
7d12e780 1883tr_interrupt(int irq, void *dev_id)
1da177e4
LT		 1884{
1885 struct e100_serial *info;
1886 unsigned long ireg;
1887 int i;
1888 int handled = 0;
1889
1da177e4
LT		 1890 /* find out the line that caused this irq and get it from rs_table */
1891
1892 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
1893
1894 for (i = 0; i < NR_PORTS; i++) {
1895 info = rs_table + i;
1896 if (!info->enabled || !info->uses_dma_out)
1897 continue;
1898 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
1899 if (ireg & info->irq) {
1900 handled = 1;
1901 /* we can send a new dma bunch. make it so. */
1902 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
1903 /* Read jiffies_usec first,
1904 * we want this time to be as late as possible
1905 */
1da177e4
LT		 1906 info->last_tx_active_usec = GET_JIFFIES_USEC();
1907 info->last_tx_active = jiffies;
1908 transmit_chars_dma(info);
1909 }
1910
1911 /* FIXME: here we should really check for a change in the
1912 status lines and if so call status_handle(info) */
1913 }
1914 return IRQ_RETVAL(handled);
1915} /* tr_interrupt */
1916
1917/* dma input channel interrupt handler */
1918
1919static irqreturn_t
7d12e780 1920rec_interrupt(int irq, void *dev_id)
1da177e4
LT		 1921{
1922 struct e100_serial *info;
1923 unsigned long ireg;
1924 int i;
1925 int handled = 0;
1926
1da177e4
LT		 1927 /* find out the line that caused this irq and get it from rs_table */
1928
1929 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
1930
1931 for (i = 0; i < NR_PORTS; i++) {
1932 info = rs_table + i;
1933 if (!info->enabled || !info->uses_dma_in)
1934 continue;
1935 /* check for both dma_eop and dma_descr for the input dma channel */
1936 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
1937 handled = 1;
1938 /* we have received something */
1939 receive_chars_dma(info);
1940 }
1941
1942 /* FIXME: here we should really check for a change in the
1943 status lines and if so call status_handle(info) */
1944 }
1945 return IRQ_RETVAL(handled);
1946} /* rec_interrupt */
1947
41c28ff1 1948static int force_eop_if_needed(struct e100_serial *info)
1da177e4
LT		 1949{
1950 /* We check data_avail bit to determine if data has
1951 * arrived since last time
1952 */
d7283353 1953 unsigned char rstat = info->ioport[REG_STATUS];
1da177e4
LT		 1954
1955 /* error or datavail? */
1956 if (rstat & SER_ERROR_MASK) {
1957 /* Some error has occurred. If there has been valid data, an
1958 * EOP interrupt will be made automatically. If no data, the
1959 * normal ser_interrupt should be enabled and handle it.
1960 * So do nothing!
1961 */
1962 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
1963 rstat | (info->line << 8));
1964 return 0;
1965 }
1966
1967 if (rstat & SER_DATA_AVAIL_MASK) {
1968 /* Ok data, no error, count it */
1969 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
1970 rstat | (info->line << 8)));
1971 /* Read data to clear status flags */
d7283353 1972 (void)info->ioport[REG_DATA];
1da177e4
LT		 1973
1974 info->forced_eop = 0;
1975 START_FLUSH_FAST_TIMER(info, "magic");
1976 return 0;
1977 }
1978
1979 /* hit the timeout, force an EOP for the input
1980 * dma channel if we haven't already
1981 */
1982 if (!info->forced_eop) {
1983 info->forced_eop = 1;
1da177e4
LT		 1984 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
1985 FORCE_EOP(info);
1986 }
1987
1988 return 1;
1989}
1990
41c28ff1 1991static void flush_to_flip_buffer(struct e100_serial *info)
1da177e4 1992{
1da177e4 1993 struct etrax_recv_buffer *buffer;
1da177e4 1994 unsigned long flags;
1da177e4 1995
77accbf5 1996 local_irq_save(flags);
1da177e4 1997
2090ab05 1998 while ((buffer = info->first_recv_buffer) != NULL) {
1da177e4
LT		 1999 unsigned int count = buffer->length;
2000
05c7cd39 2001 tty_insert_flip_string(&info->port, buffer->buffer, count);
1da177e4 2002 info->recv_cnt -= count;
1da177e4
LT		 2003
2004 if (count == buffer->length) {
2005 info->first_recv_buffer = buffer->next;
2006 kfree(buffer);
2007 } else {
2008 buffer->length -= count;
2009 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2010 buffer->error = TTY_NORMAL;
2011 }
2012 }
2013
2014 if (!info->first_recv_buffer)
2015 info->last_recv_buffer = NULL;
2016
77accbf5 2017 local_irq_restore(flags);
1da177e4 2018
77accbf5 2019 /* This includes a check for low-latency */
2e124b4a 2020 tty_flip_buffer_push(&info->port);
1da177e4
LT		 2021}
2022
41c28ff1 2023static void check_flush_timeout(struct e100_serial *info)
1da177e4
LT		 2024{
2025 /* Flip what we've got (if we can) */
2026 flush_to_flip_buffer(info);
2027
2028 /* We might need to flip later, but not to fast
2029 * since the system is busy processing input... */
2030 if (info->first_recv_buffer)
2031 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2032
2033 /* Force eop last, since data might have come while we're processing
2034 * and if we started the slow timer above, we won't start a fast
2035 * below.
2036 */
2037 force_eop_if_needed(info);
2038}
2039
2040#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2041static void flush_timeout_function(unsigned long data)
2042{
2043 struct e100_serial *info = (struct e100_serial *)data;
2044
2045 fast_timers[info->line].function = NULL;
2046 serial_fast_timer_expired++;
8faaaead 2047 TIMERD(DEBUG_LOG(info->line, "flush_timeout %i ", info->line));
1da177e4
LT		 2048 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2049 check_flush_timeout(info);
2050}
2051
2052#else
2053
2054/* dma fifo/buffer timeout handler
2055 forces an end-of-packet for the dma input channel if no chars
2056 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2057*/
2058
2059static struct timer_list flush_timer;
2060
2061static void
e99e88a9 2062timed_flush_handler(struct timer_list *unused)
1da177e4
LT		 2063{
2064 struct e100_serial *info;
2065 int i;
2066
1da177e4
LT		 2067 for (i = 0; i < NR_PORTS; i++) {
2068 info = rs_table + i;
2069 if (info->uses_dma_in)
2070 check_flush_timeout(info);
2071 }
2072
2073 /* restart flush timer */
2074 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2075}
2076#endif
2077
2078#ifdef SERIAL_HANDLE_EARLY_ERRORS
2079
2080/* If there is an error (ie break) when the DMA is running and
2081 * there are no bytes in the fifo the DMA is stopped and we get no
2082 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2083 * transfer, and if it is without error we can turn the serial
2084 * interrupts off.
2085 */
2086
2087/*
2088BREAK handling on ETRAX 100:
2089ETRAX will generate interrupt although there is no stop bit between the
2090characters.
2091
2092Depending on how long the break sequence is, the end of the breaksequence
2093will look differently:
2094| indicates start/end of a character.
2095
2096B= Break character (0x00) with framing error.
2097E= Error byte with parity error received after B characters.
2098F= "Faked" valid byte received immediately after B characters.
2099V= Valid byte
2100
21011.
2102 B BL ___________________________ V
2103.._|__________|__________| |valid data |
2104
2105Multiple frame errors with data == 0x00 (B),
2106the timing matches up "perfectly" so no extra ending char is detected.
2107The RXD pin is 1 in the last interrupt, in that case
2108we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2109know if another byte will come and this really is case 2. below
2110(e.g F=0xFF or 0xFE)
2111If RXD pin is 0 we can expect another character (see 2. below).
2112
2113
21142.
2115
2116 B B E or F__________________..__ V
2117.._|__________|__________|______ | |valid data
2118 "valid" or
2119 parity error
2120
2121Multiple frame errors with data == 0x00 (B),
2122but the part of the break trigs is interpreted as a start bit (and possibly
2123some 0 bits followed by a number of 1 bits and a stop bit).
2124Depending on parity settings etc. this last character can be either
2125a fake "valid" char (F) or have a parity error (E).
2126
2127If the character is valid it will be put in the buffer,
2128we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2129will set the flags so the tty will handle it,
2130if it's an error byte it will not be put in the buffer
2131and we set info->errorcode = ERRCODE_INSERT_BREAK.
2132
2133To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2134of the last faulty char (B) and compares it with the current time:
2135If the time elapsed time is less then 2*char_time_usec we will assume
2136it's a faked F char and not a Valid char and set
2137info->errorcode = ERRCODE_SET_BREAK.
2138
2139Flaws in the above solution:
2140~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2141We use the timer to distinguish a F character from a V character,
2142if a V character is to close after the break we might make the wrong decision.
2143
2144TODO: The break will be delayed until an F or V character is received.
2145
2146*/
2147
12aad550 2148static void handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
1da177e4
LT		 2149{
2150 unsigned long data_read;
77accbf5 2151
1da177e4 2152 /* Read data and status at the same time */
d7283353 2153 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
1da177e4
LT		 2154more_data:
2155 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2156 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2157 }
2158 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2159
2160 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2161 IO_MASK(R_SERIAL0_READ, par_err) |
2162 IO_MASK(R_SERIAL0_READ, overrun) )) {
2163 /* An error */
2164 info->last_rx_active_usec = GET_JIFFIES_USEC();
2165 info->last_rx_active = jiffies;
2166 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2167 DLOG_INT_TRIG(
2168 if (!log_int_trig1_pos) {
2169 log_int_trig1_pos = log_int_pos;
2170 log_int(rdpc(), 0, 0);
2171 }
2172 );
2173
2174
2175 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2176 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2177 /* Most likely a break, but we get interrupts over and
2178 * over again.
2179 */
2180
2181 if (!info->break_detected_cnt) {
2182 DEBUG_LOG(info->line, "#BRK start\n", 0);
2183 }
2184 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2185 /* The RX pin is high now, so the break
2186 * must be over, but....
2187 * we can't really know if we will get another
2188 * last byte ending the break or not.
2189 * And we don't know if the byte (if any) will
2190 * have an error or look valid.
2191 */
2192 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2193 info->errorcode = ERRCODE_INSERT_BREAK;
2194 }
2195 info->break_detected_cnt++;
2196 } else {
2197 /* The error does not look like a break, but could be
2198 * the end of one
2199 */
2200 if (info->break_detected_cnt) {
2201 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2202 info->errorcode = ERRCODE_INSERT_BREAK;
2203 } else {
77accbf5
JN		 2204 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2205 data_in, data_read);
2206 char flag = TTY_NORMAL;
1da177e4 2207 if (info->errorcode == ERRCODE_INSERT_BREAK) {
92a19f9c 2208 tty_insert_flip_char(&info->port, 0, flag);
1da177e4
LT		 2209 info->icount.rx++;
2210 }
1da177e4
LT		 2211
2212 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2213 info->icount.parity++;
77accbf5 2214 flag = TTY_PARITY;
1da177e4
LT		 2215 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2216 info->icount.overrun++;
77accbf5 2217 flag = TTY_OVERRUN;
1da177e4
LT		 2218 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2219 info->icount.frame++;
77accbf5 2220 flag = TTY_FRAME;
1da177e4 2221 }
92a19f9c 2222 tty_insert_flip_char(&info->port, data, flag);
1da177e4
LT		 2223 info->errorcode = 0;
2224 }
2225 info->break_detected_cnt = 0;
2226 }
2227 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2228 /* No error */
2229 DLOG_INT_TRIG(
2230 if (!log_int_trig1_pos) {
2231 if (log_int_pos >= log_int_size) {
2232 log_int_pos = 0;
2233 }
2234 log_int_trig0_pos = log_int_pos;
2235 log_int(rdpc(), 0, 0);
2236 }
2237 );
92a19f9c 2238 tty_insert_flip_char(&info->port,
77accbf5
JN		 2239 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2240 TTY_NORMAL);
1da177e4
LT		 2241 } else {
2242 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2243 }
2244
2245
1da177e4 2246 info->icount.rx++;
d7283353 2247 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
1da177e4
LT		 2248 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2249 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2250 goto more_data;
2251 }
2252
2e124b4a 2253 tty_flip_buffer_push(&info->port);
1da177e4
LT		 2254}
2255
12aad550 2256static void handle_ser_rx_interrupt(struct e100_serial *info)
1da177e4
LT		 2257{
2258 unsigned char rstat;
2259
2260#ifdef SERIAL_DEBUG_INTR
2261 printk("Interrupt from serport %d\n", i);
2262#endif
2263/* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2264 if (!info->uses_dma_in) {
12aad550
JS		 2265 handle_ser_rx_interrupt_no_dma(info);
2266 return;
1da177e4
LT		 2267 }
2268 /* DMA is used */
d7283353 2269 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2270 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2271 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2272 }
2273
2274 if (rstat & SER_ERROR_MASK) {
2275 unsigned char data;
2276
2277 info->last_rx_active_usec = GET_JIFFIES_USEC();
2278 info->last_rx_active = jiffies;
2279 /* If we got an error, we must reset it by reading the
2280 * data_in field
2281 */
d7283353 2282 data = info->ioport[REG_DATA];
1da177e4
LT		 2283 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2284 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2285 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2286 /* Most likely a break, but we get interrupts over and
2287 * over again.
2288 */
2289
2290 if (!info->break_detected_cnt) {
2291 DEBUG_LOG(info->line, "#BRK start\n", 0);
2292 }
2293 if (rstat & SER_RXD_MASK) {
2294 /* The RX pin is high now, so the break
2295 * must be over, but....
2296 * we can't really know if we will get another
2297 * last byte ending the break or not.
2298 * And we don't know if the byte (if any) will
2299 * have an error or look valid.
2300 */
2301 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2302 info->errorcode = ERRCODE_INSERT_BREAK;
2303 }
2304 info->break_detected_cnt++;
2305 } else {
2306 /* The error does not look like a break, but could be
2307 * the end of one
2308 */
2309 if (info->break_detected_cnt) {
2310 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2311 info->errorcode = ERRCODE_INSERT_BREAK;
2312 } else {
2313 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2314 info->icount.brk++;
2315 add_char_and_flag(info, '\0', TTY_BREAK);
2316 }
2317
2318 if (rstat & SER_PAR_ERR_MASK) {
2319 info->icount.parity++;
2320 add_char_and_flag(info, data, TTY_PARITY);
2321 } else if (rstat & SER_OVERRUN_MASK) {
2322 info->icount.overrun++;
2323 add_char_and_flag(info, data, TTY_OVERRUN);
2324 } else if (rstat & SER_FRAMING_ERR_MASK) {
2325 info->icount.frame++;
2326 add_char_and_flag(info, data, TTY_FRAME);
2327 }
2328
2329 info->errorcode = 0;
2330 }
2331 info->break_detected_cnt = 0;
2332 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2333 ((rstat & SER_ERROR_MASK) << 8) | data);
2334 }
1da177e4
LT		 2335 } else { /* It was a valid byte, now let the DMA do the rest */
2336 unsigned long curr_time_u = GET_JIFFIES_USEC();
2337 unsigned long curr_time = jiffies;
2338
2339 if (info->break_detected_cnt) {
2340 /* Detect if this character is a new valid char or the
2341 * last char in a break sequence: If LSBits are 0 and
2342 * MSBits are high AND the time is close to the
2343 * previous interrupt we should discard it.
2344 */
2345 long elapsed_usec =
2346 (curr_time - info->last_rx_active) * (1000000/HZ) +
2347 curr_time_u - info->last_rx_active_usec;
2348 if (elapsed_usec < 2*info->char_time_usec) {
2349 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2350 /* Report as BREAK (error) and let
2351 * receive_chars_dma() handle it
2352 */
2353 info->errorcode = ERRCODE_SET_BREAK;
2354 } else {
2355 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2356 }
2357 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2358 }
2359
2360#ifdef SERIAL_DEBUG_INTR
2361 printk("** OK, disabling ser_interrupts\n");
2362#endif
2363 e100_disable_serial_data_irq(info);
2364 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2365 info->break_detected_cnt = 0;
2366
1da177e4
LT		 2367 }
2368 /* Restarting the DMA never hurts */
2369 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2370 START_FLUSH_FAST_TIMER(info, "ser_int");
1da177e4
LT		 2371} /* handle_ser_rx_interrupt */
2372
41c28ff1 2373static void handle_ser_tx_interrupt(struct e100_serial *info)
1da177e4
LT		 2374{
2375 unsigned long flags;
2376
2377 if (info->x_char) {
2378 unsigned char rstat;
2379 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
77accbf5 2380 local_irq_save(flags);
d7283353 2381 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2382 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2383
d7283353 2384 info->ioport[REG_TR_DATA] = info->x_char;
1da177e4
LT		 2385 info->icount.tx++;
2386 info->x_char = 0;
2387 /* We must enable since it is disabled in ser_interrupt */
2388 e100_enable_serial_tx_ready_irq(info);
77accbf5 2389 local_irq_restore(flags);
1da177e4
LT		 2390 return;
2391 }
2392 if (info->uses_dma_out) {
2393 unsigned char rstat;
2394 int i;
2395 /* We only use normal tx interrupt when sending x_char */
2396 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
77accbf5 2397 local_irq_save(flags);
d7283353 2398 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2399 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2400 e100_disable_serial_tx_ready_irq(info);
a88487c7
TI		 2401 if (info->port.tty->stopped)
2402 rs_stop(info->port.tty);
1da177e4
LT		 2403 /* Enable the DMA channel and tell it to continue */
2404 e100_enable_txdma_channel(info);
2405 /* Wait 12 cycles before doing the DMA command */
2406 for(i = 6; i > 0; i--)
2407 nop();
2408
2409 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
77accbf5 2410 local_irq_restore(flags);
1da177e4
LT		 2411 return;
2412 }
2413 /* Normal char-by-char interrupt */
2414 if (info->xmit.head == info->xmit.tail
ee797069 2415 || info->port.tty->stopped) {
a88487c7
TI		 2416 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2417 info->port.tty->stopped));
1da177e4
LT		 2418 e100_disable_serial_tx_ready_irq(info);
2419 info->tr_running = 0;
2420 return;
2421 }
2422 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2423 /* Send a byte, rs485 timing is critical so turn of ints */
77accbf5 2424 local_irq_save(flags);
d7283353 2425 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
1da177e4
LT		 2426 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2427 info->icount.tx++;
2428 if (info->xmit.head == info->xmit.tail) {
2429#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
6fd1af4c 2430 if (info->rs485.flags & SER_RS485_ENABLED) {
1da177e4
LT		 2431 /* Set a short timer to toggle RTS */
2432 start_one_shot_timer(&fast_timers_rs485[info->line],
2433 rs485_toggle_rts_timer_function,
2434 (unsigned long)info,
2435 info->char_time_usec*2,
2436 "RS-485");
2437 }
2438#endif /* RS485 */
2439 info->last_tx_active_usec = GET_JIFFIES_USEC();
2440 info->last_tx_active = jiffies;
2441 e100_disable_serial_tx_ready_irq(info);
2442 info->tr_running = 0;
2443 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2444 } else {
2445 /* We must enable since it is disabled in ser_interrupt */
2446 e100_enable_serial_tx_ready_irq(info);
2447 }
77accbf5 2448 local_irq_restore(flags);
1da177e4
LT		 2449
2450 if (CIRC_CNT(info->xmit.head,
2451 info->xmit.tail,
2452 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2453 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2454
2455} /* handle_ser_tx_interrupt */
2456
2457/* result of time measurements:
2458 * RX duration 54-60 us when doing something, otherwise 6-9 us
2459 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2460 */
2461static irqreturn_t
7d12e780 2462ser_interrupt(int irq, void *dev_id)
1da177e4
LT		 2463{
2464 static volatile int tx_started = 0;
2465 struct e100_serial *info;
2466 int i;
2467 unsigned long flags;
2468 unsigned long irq_mask1_rd;
2469 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2470 int handled = 0;
2471 static volatile unsigned long reentered_ready_mask = 0;
2472
77accbf5 2473 local_irq_save(flags);
1da177e4
LT		 2474 irq_mask1_rd = *R_IRQ_MASK1_RD;
2475 /* First handle all rx interrupts with ints disabled */
2476 info = rs_table;
2477 irq_mask1_rd &= e100_ser_int_mask;
2478 for (i = 0; i < NR_PORTS; i++) {
2479 /* Which line caused the data irq? */
2480 if (irq_mask1_rd & data_mask) {
2481 handled = 1;
2482 handle_ser_rx_interrupt(info);
2483 }
2484 info += 1;
2485 data_mask <<= 2;
2486 }
2487 /* Handle tx interrupts with interrupts enabled so we
2488 * can take care of new data interrupts while transmitting
2489 * We protect the tx part with the tx_started flag.
2490 * We disable the tr_ready interrupts we are about to handle and
2491 * unblock the serial interrupt so new serial interrupts may come.
2492 *
2493 * If we get a new interrupt:
2494 * - it migth be due to synchronous serial ports.
2495 * - serial irq will be blocked by general irq handler.
2496 * - async data will be handled above (sync will be ignored).
2497 * - tx_started flag will prevent us from trying to send again and
2498 * we will exit fast - no need to unblock serial irq.
2499 * - Next (sync) serial interrupt handler will be runned with
2500 * disabled interrupt due to restore_flags() at end of function,
2501 * so sync handler will not be preempted or reentered.
2502 */
2503 if (!tx_started) {
2504 unsigned long ready_mask;
2505 unsigned long
2506 tx_started = 1;
2507 /* Only the tr_ready interrupts left */
2508 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2509 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2510 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2511 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2512 while (irq_mask1_rd) {
2513 /* Disable those we are about to handle */
2514 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2515 /* Unblock the serial interrupt */
2516 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2517
77accbf5 2518 local_irq_enable();
1da177e4
LT		 2519 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2520 info = rs_table;
2521 for (i = 0; i < NR_PORTS; i++) {
2522 /* Which line caused the ready irq? */
2523 if (irq_mask1_rd & ready_mask) {
2524 handled = 1;
2525 handle_ser_tx_interrupt(info);
2526 }
2527 info += 1;
2528 ready_mask <<= 2;
2529 }
2530 /* handle_ser_tx_interrupt enables tr_ready interrupts */
77accbf5 2531 local_irq_disable();
1da177e4
LT		 2532 /* Handle reentered TX interrupt */
2533 irq_mask1_rd = reentered_ready_mask;
2534 }
77accbf5 2535 local_irq_disable();
1da177e4
LT		 2536 tx_started = 0;
2537 } else {
2538 unsigned long ready_mask;
2539 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2540 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2541 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2542 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2543 if (ready_mask) {
2544 reentered_ready_mask |= ready_mask;
2545 /* Disable those we are about to handle */
2546 *R_IRQ_MASK1_CLR = ready_mask;
2547 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2548 }
2549 }
2550
77accbf5 2551 local_irq_restore(flags);
1da177e4
LT		 2552 return IRQ_RETVAL(handled);
2553} /* ser_interrupt */
2554#endif
2555
2556/*
2557 * -------------------------------------------------------------------
2558 * Here ends the serial interrupt routines.
2559 * -------------------------------------------------------------------
2560 */
2561
2562/*
2563 * This routine is used to handle the "bottom half" processing for the
2564 * serial driver, known also the "software interrupt" processing.
2565 * This processing is done at the kernel interrupt level, after the
2566 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2567 * is where time-consuming activities which can not be done in the
2568 * interrupt driver proper are done; the interrupt driver schedules
2569 * them using rs_sched_event(), and they get done here.
2570 */
2571static void
77accbf5 2572do_softint(struct work_struct *work)
1da177e4 2573{
77accbf5 2574 struct e100_serial *info;
1da177e4
LT		 2575 struct tty_struct *tty;
2576
77accbf5
JN		 2577 info = container_of(work, struct e100_serial, work);
2578
a88487c7 2579 tty = info->port.tty;
1da177e4
LT		 2580 if (!tty)
2581 return;
2582
b963a844
JS		 2583 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2584 tty_wakeup(tty);
1da177e4
LT		 2585}
2586
2587static int
2588startup(struct e100_serial * info)
2589{
2590 unsigned long flags;
2591 unsigned long xmit_page;
2592 int i;
2593
2594 xmit_page = get_zeroed_page(GFP_KERNEL);
2595 if (!xmit_page)
2596 return -ENOMEM;
2597
77accbf5 2598 local_irq_save(flags);
1da177e4
LT		 2599
2600 /* if it was already initialized, skip this */
2601
d41861ca 2602 if (tty_port_initialized(&info->port)) {
77accbf5 2603 local_irq_restore(flags);
1da177e4
LT		 2604 free_page(xmit_page);
2605 return 0;
2606 }
2607
2608 if (info->xmit.buf)
2609 free_page(xmit_page);
2610 else
2611 info->xmit.buf = (unsigned char *) xmit_page;
2612
2613#ifdef SERIAL_DEBUG_OPEN
2614 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2615#endif
2616
1da177e4
LT		 2617 /*
2618 * Clear the FIFO buffers and disable them
2619 * (they will be reenabled in change_speed())
2620 */
2621
2622 /*
2623 * Reset the DMA channels and make sure their interrupts are cleared
2624 */
2625
2626 if (info->dma_in_enabled) {
2627 info->uses_dma_in = 1;
2628 e100_enable_rxdma_channel(info);
2629
2630 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2631
2632 /* Wait until reset cycle is complete */
2633 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2634 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2635
2636 /* Make sure the irqs are cleared */
2637 *info->iclrintradr =
2638 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2639 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2640 } else {
2641 e100_disable_rxdma_channel(info);
2642 }
2643
2644 if (info->dma_out_enabled) {
2645 info->uses_dma_out = 1;
2646 e100_enable_txdma_channel(info);
2647 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2648
2649 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2650 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2651
2652 /* Make sure the irqs are cleared */
2653 *info->oclrintradr =
2654 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2655 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2656 } else {
2657 e100_disable_txdma_channel(info);
2658 }
2659
a88487c7
TI		 2660 if (info->port.tty)
2661 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 2662
2663 info->xmit.head = info->xmit.tail = 0;
2664 info->first_recv_buffer = info->last_recv_buffer = NULL;
2665 info->recv_cnt = info->max_recv_cnt = 0;
2666
2667 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2668 info->rec_descr[i].buf = 0;
2669
2670 /*
2671 * and set the speed and other flags of the serial port
2672 * this will start the rx/tx as well
2673 */
2674#ifdef SERIAL_HANDLE_EARLY_ERRORS
2675 e100_enable_serial_data_irq(info);
2676#endif
2677 change_speed(info);
2678
2679 /* dummy read to reset any serial errors */
2680
d7283353 2681 (void)info->ioport[REG_DATA];
1da177e4
LT		 2682
2683 /* enable the interrupts */
2684 if (info->uses_dma_out)
2685 e100_enable_txdma_irq(info);
2686
2687 e100_enable_rx_irq(info);
2688
2689 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2690
2691 /* setup the dma input descriptor and start dma */
2692
2693 start_receive(info);
2694
2695 /* for safety, make sure the descriptors last result is 0 bytes written */
2696
2697 info->tr_descr.sw_len = 0;
2698 info->tr_descr.hw_len = 0;
2699 info->tr_descr.status = 0;
2700
2701 /* enable RTS/DTR last */
2702
2703 e100_rts(info, 1);
2704 e100_dtr(info, 1);
2705
d41861ca 2706 tty_port_set_initialized(&info->port, 1);
1da177e4 2707
77accbf5 2708 local_irq_restore(flags);
1da177e4
LT		 2709 return 0;
2710}
2711
2712/*
2713 * This routine will shutdown a serial port; interrupts are disabled, and
2714 * DTR is dropped if the hangup on close termio flag is on.
2715 */
2716static void
2717shutdown(struct e100_serial * info)
2718{
2719 unsigned long flags;
2720 struct etrax_dma_descr *descr = info->rec_descr;
2721 struct etrax_recv_buffer *buffer;
2722 int i;
2723
1da177e4
LT		 2724 /* shut down the transmitter and receiver */
2725 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2726 e100_disable_rx(info);
d7283353 2727 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
1da177e4
LT		 2728
2729 /* disable interrupts, reset dma channels */
2730 if (info->uses_dma_in) {
2731 e100_disable_rxdma_irq(info);
2732 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2733 info->uses_dma_in = 0;
2734 } else {
2735 e100_disable_serial_data_irq(info);
2736 }
2737
2738 if (info->uses_dma_out) {
2739 e100_disable_txdma_irq(info);
2740 info->tr_running = 0;
2741 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2742 info->uses_dma_out = 0;
2743 } else {
2744 e100_disable_serial_tx_ready_irq(info);
2745 info->tr_running = 0;
2746 }
2747
d41861ca 2748 if (!tty_port_initialized(&info->port))
1da177e4
LT		 2749 return;
2750
2751#ifdef SERIAL_DEBUG_OPEN
2752 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2753 info->irq);
2754#endif
2755
77accbf5 2756 local_irq_save(flags);
1da177e4
LT		 2757
2758 if (info->xmit.buf) {
2759 free_page((unsigned long)info->xmit.buf);
2760 info->xmit.buf = NULL;
2761 }
2762
2763 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2764 if (descr[i].buf) {
2765 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2766 kfree(buffer);
2767 descr[i].buf = 0;
2768 }
2769
adc8d746 2770 if (!info->port.tty || (info->port.tty->termios.c_cflag & HUPCL)) {
1da177e4
LT		 2771 /* hang up DTR and RTS if HUPCL is enabled */
2772 e100_dtr(info, 0);
2773 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2774 }
2775
a88487c7
TI		 2776 if (info->port.tty)
2777 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 2778
d41861ca 2779 tty_port_set_initialized(&info->port, 0);
77accbf5 2780 local_irq_restore(flags);
1da177e4
LT		 2781}
2782
2783
2784/* change baud rate and other assorted parameters */
2785
2786static void
2787change_speed(struct e100_serial *info)
2788{
2789 unsigned int cflag;
2790 unsigned long xoff;
2791 unsigned long flags;
2792 /* first some safety checks */
2793
adc8d746 2794 if (!info->port.tty)
1da177e4 2795 return;
d7283353 2796 if (!info->ioport)
1da177e4
LT		 2797 return;
2798
adc8d746 2799 cflag = info->port.tty->termios.c_cflag;
1da177e4
LT		 2800
2801 /* possibly, the tx/rx should be disabled first to do this safely */
2802
2803 /* change baud-rate and write it to the hardware */
b1d984cf 2804 if ((info->port.flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
1da177e4
LT		 2805 /* Special baudrate */
2806 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2807 unsigned long alt_source =
2808 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2809 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2810 /* R_ALT_SER_BAUDRATE selects the source */
2811 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2812 (unsigned long)info->baud_base, info->custom_divisor));
2813 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2814 /* 0, 2-65535 (0=65536) */
2815 u16 divisor = info->custom_divisor;
2816 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2817 /* baudrate is 3.125MHz/custom_divisor */
2818 alt_source =
2819 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2820 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2821 alt_source = 0x11;
2822 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2823 *R_SERIAL_PRESCALE = divisor;
2824 info->baud = SERIAL_PRESCALE_BASE/divisor;
2825 }
1da177e4
LT		 2826 else
2827 {
2828 /* Bad baudbase, we don't support using timer0
2829 * for baudrate.
2830 */
2831 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
2832 (unsigned long)info->baud_base, info->custom_divisor);
2833 }
2834 r_alt_ser_baudrate_shadow &= ~mask;
2835 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
2836 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
2837 } else {
2838 /* Normal baudrate */
2839 /* Make sure we use normal baudrate */
2840 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2841 unsigned long alt_source =
2842 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2843 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2844 r_alt_ser_baudrate_shadow &= ~mask;
2845 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
1da177e4 2846 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
1da177e4
LT		 2847
2848 info->baud = cflag_to_baud(cflag);
d7283353 2849 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
1da177e4
LT		 2850 }
2851
1da177e4 2852 /* start with default settings and then fill in changes */
77accbf5 2853 local_irq_save(flags);
1da177e4
LT		 2854 /* 8 bit, no/even parity */
2855 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
2856 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
2857 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
2858
2859 /* 8 bit, no/even parity, 1 stop bit, no cts */
2860 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
2861 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
2862 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
2863 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
2864 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
2865
2866 if ((cflag & CSIZE) == CS7) {
2867 /* set 7 bit mode */
2868 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
2869 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
2870 }
2871
2872 if (cflag & CSTOPB) {
2873 /* set 2 stop bit mode */
2874 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
2875 }
2876
2877 if (cflag & PARENB) {
2878 /* enable parity */
2879 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
2880 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
2881 }
2882
2883 if (cflag & CMSPAR) {
2884 /* enable stick parity, PARODD mean Mark which matches ETRAX */
2885 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
2886 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
2887 }
2888 if (cflag & PARODD) {
2889 /* set odd parity (or Mark if CMSPAR) */
2890 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
2891 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
2892 }
2893
2894 if (cflag & CRTSCTS) {
2895 /* enable automatic CTS handling */
2896 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
2897 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
2898 }
2899
2900 /* make sure the tx and rx are enabled */
2901
2902 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
2903 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
2904
2905 /* actually write the control regs to the hardware */
2906
d7283353
AC		 2907 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
2908 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
a88487c7 2909 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
1da177e4 2910 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
adc8d746 2911 if (info->port.tty->termios.c_iflag & IXON ) {
a88487c7
TI		 2912 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
2913 STOP_CHAR(info->port.tty)));
1da177e4
LT		 2914 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
2915 }
2916
d7283353 2917 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
77accbf5 2918 local_irq_restore(flags);
1da177e4
LT		 2919
2920 update_char_time(info);
2921
2922} /* change_speed */
2923
2924/* start transmitting chars NOW */
2925
2926static void
2927rs_flush_chars(struct tty_struct *tty)
2928{
2929 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
2930 unsigned long flags;
2931
2932 if (info->tr_running ||
2933 info->xmit.head == info->xmit.tail ||
2934 tty->stopped ||
1da177e4
LT		 2935 !info->xmit.buf)
2936 return;
2937
2938#ifdef SERIAL_DEBUG_FLOW
2939 printk("rs_flush_chars\n");
2940#endif
2941
2942 /* this protection might not exactly be necessary here */
2943
77accbf5 2944 local_irq_save(flags);
1da177e4 2945 start_transmit(info);
77accbf5 2946 local_irq_restore(flags);
1da177e4
LT		 2947}
2948
77accbf5 2949static int rs_raw_write(struct tty_struct *tty,
41c28ff1 2950 const unsigned char *buf, int count)
1da177e4
LT		 2951{
2952 int c, ret = 0;
2953 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
2954 unsigned long flags;
2955
2956 /* first some sanity checks */
2957
f938f378 2958 if (!info->xmit.buf)
1da177e4
LT		 2959 return 0;
2960
2961#ifdef SERIAL_DEBUG_DATA
2962 if (info->line == SERIAL_DEBUG_LINE)
2963 printk("rs_raw_write (%d), status %d\n",
d7283353 2964 count, info->ioport[REG_STATUS]);
1da177e4
LT		 2965#endif
2966
77accbf5 2967 local_save_flags(flags);
1da177e4 2968 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
fdfb719e 2969 DFLOW(DEBUG_LOG(info->line, "ldisc\n"));
1da177e4
LT		 2970
2971
77accbf5
JN		 2972 /* The local_irq_disable/restore_flags pairs below are needed
2973 * because the DMA interrupt handler moves the info->xmit values.
2974 * the memcpy needs to be in the critical region unfortunately,
2975 * because we need to read xmit values, memcpy, write xmit values
2976 * in one atomic operation... this could perhaps be avoided by
2977 * more clever design.
1da177e4 2978 */
77accbf5 2979 local_irq_disable();
1da177e4
LT		 2980 while (count) {
2981 c = CIRC_SPACE_TO_END(info->xmit.head,
2982 info->xmit.tail,
2983 SERIAL_XMIT_SIZE);
2984
2985 if (count < c)
2986 c = count;
2987 if (c <= 0)
2988 break;
2989
2990 memcpy(info->xmit.buf + info->xmit.head, buf, c);
2991 info->xmit.head = (info->xmit.head + c) &
2992 (SERIAL_XMIT_SIZE-1);
2993 buf += c;
2994 count -= c;
2995 ret += c;
2996 }
77accbf5 2997 local_irq_restore(flags);
1da177e4
LT		 2998
2999 /* enable transmitter if not running, unless the tty is stopped
3000 * this does not need IRQ protection since if tr_running == 0
3001 * the IRQ's are not running anyway for this port.
3002 */
3003 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3004
3005 if (info->xmit.head != info->xmit.tail &&
3006 !tty->stopped &&
1da177e4
LT		 3007 !info->tr_running) {
3008 start_transmit(info);
3009 }
3010
3011 return ret;
3012} /* raw_raw_write() */
3013
3014static int
77accbf5 3015rs_write(struct tty_struct *tty,
1da177e4
LT		 3016 const unsigned char *buf, int count)
3017{
3018#if defined(CONFIG_ETRAX_RS485)
3019 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3020
6fd1af4c 3021 if (info->rs485.flags & SER_RS485_ENABLED)
1da177e4
LT		 3022 {
3023 /* If we are in RS-485 mode, we need to toggle RTS and disable
3024 * the receiver before initiating a DMA transfer
3025 */
3026#ifdef CONFIG_ETRAX_FAST_TIMER
3027 /* Abort any started timer */
3028 fast_timers_rs485[info->line].function = NULL;
3029 del_fast_timer(&fast_timers_rs485[info->line]);
3030#endif
6fd1af4c 3031 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
1da177e4
LT		 3032#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3033 e100_disable_rx(info);
3034 e100_enable_rx_irq(info);
3035#endif
93f3350c
CS		 3036 if (info->rs485.delay_rts_before_send > 0)
3037 msleep(info->rs485.delay_rts_before_send);
1da177e4
LT		 3038 }
3039#endif /* CONFIG_ETRAX_RS485 */
3040
77accbf5 3041 count = rs_raw_write(tty, buf, count);
1da177e4
LT		 3042
3043#if defined(CONFIG_ETRAX_RS485)
6fd1af4c 3044 if (info->rs485.flags & SER_RS485_ENABLED)
1da177e4
LT		 3045 {
3046 unsigned int val;
3047 /* If we are in RS-485 mode the following has to be done:
3048 * wait until DMA is ready
3049 * wait on transmit shift register
3050 * toggle RTS
3051 * enable the receiver
3052 */
3053
3054 /* Sleep until all sent */
3055 tty_wait_until_sent(tty, 0);
3056#ifdef CONFIG_ETRAX_FAST_TIMER
3057 /* Now sleep a little more so that shift register is empty */
3058 schedule_usleep(info->char_time_usec * 2);
3059#endif
3060 /* wait on transmit shift register */
3061 do{
3062 get_lsr_info(info, &val);
3063 }while (!(val & TIOCSER_TEMT));
3064
6fd1af4c 3065 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1da177e4
LT		 3066
3067#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3068 e100_enable_rx(info);
3069 e100_enable_rxdma_irq(info);
3070#endif
3071 }
3072#endif /* CONFIG_ETRAX_RS485 */
3073
3074 return count;
3075} /* rs_write */
3076
3077
3078/* how much space is available in the xmit buffer? */
3079
3080static int
3081rs_write_room(struct tty_struct *tty)
3082{
3083 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3084
3085 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3086}
3087
3088/* How many chars are in the xmit buffer?
3089 * This does not include any chars in the transmitter FIFO.
3090 * Use wait_until_sent for waiting for FIFO drain.
3091 */
3092
3093static int
3094rs_chars_in_buffer(struct tty_struct *tty)
3095{
3096 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3097
3098 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3099}
3100
3101/* discard everything in the xmit buffer */
3102
3103static void
3104rs_flush_buffer(struct tty_struct *tty)
3105{
3106 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3107 unsigned long flags;
3108
77accbf5 3109 local_irq_save(flags);
1da177e4 3110 info->xmit.head = info->xmit.tail = 0;
77accbf5 3111 local_irq_restore(flags);
1da177e4 3112
b963a844 3113 tty_wakeup(tty);
1da177e4
LT		 3114}
3115
3116/*
3117 * This function is used to send a high-priority XON/XOFF character to
3118 * the device
3119 *
3120 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3121 * but we do it in handle_ser_tx_interrupt().
3122 * We disable DMA channel and enable tx ready interrupt and write the
3123 * character when possible.
3124 */
3125static void rs_send_xchar(struct tty_struct *tty, char ch)
3126{
3127 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3128 unsigned long flags;
77accbf5 3129 local_irq_save(flags);
1da177e4
LT		 3130 if (info->uses_dma_out) {
3131 /* Put the DMA on hold and disable the channel */
3132 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3133 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3134 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3135 e100_disable_txdma_channel(info);
3136 }
3137
3138 /* Must make sure transmitter is not stopped before we can transmit */
3139 if (tty->stopped)
3140 rs_start(tty);
3141
3142 /* Enable manual transmit interrupt and send from there */
3143 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3144 info->x_char = ch;
3145 e100_enable_serial_tx_ready_irq(info);
77accbf5 3146 local_irq_restore(flags);
1da177e4
LT		 3147}
3148
3149/*
3150 * ------------------------------------------------------------
3151 * rs_throttle()
3152 *
3153 * This routine is called by the upper-layer tty layer to signal that
3154 * incoming characters should be throttled.
3155 * ------------------------------------------------------------
3156 */
3157static void
3158rs_throttle(struct tty_struct * tty)
3159{
3160 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3161#ifdef SERIAL_DEBUG_THROTTLE
fdfb719e 3162 printk("throttle %s ....\n", tty_name(tty));
1da177e4 3163#endif
fdfb719e 3164 DFLOW(DEBUG_LOG(info->line,"rs_throttle\n"));
1da177e4
LT		 3165
3166 /* Do RTS before XOFF since XOFF might take some time */
9db276f8 3167 if (C_CRTSCTS(tty)) {
1da177e4
LT		 3168 /* Turn off RTS line */
3169 e100_rts(info, 0);
3170 }
3171 if (I_IXOFF(tty))
3172 rs_send_xchar(tty, STOP_CHAR(tty));
3173
3174}
3175
3176static void
3177rs_unthrottle(struct tty_struct * tty)
3178{
3179 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3180#ifdef SERIAL_DEBUG_THROTTLE
fdfb719e 3181 printk("unthrottle %s ....\n", tty_name(tty));
1da177e4 3182#endif
fdfb719e 3183 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc\n"));
1da177e4
LT		 3184 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3185 /* Do RTS before XOFF since XOFF might take some time */
9db276f8 3186 if (C_CRTSCTS(tty)) {
1da177e4
LT		 3187 /* Assert RTS line */
3188 e100_rts(info, 1);
3189 }
3190
3191 if (I_IXOFF(tty)) {
3192 if (info->x_char)
3193 info->x_char = 0;
3194 else
3195 rs_send_xchar(tty, START_CHAR(tty));
3196 }
3197
3198}
3199
3200/*
3201 * ------------------------------------------------------------
3202 * rs_ioctl() and friends
3203 * ------------------------------------------------------------
3204 */
3205
3206static int
3207get_serial_info(struct e100_serial * info,
3208 struct serial_struct * retinfo)
3209{
3210 struct serial_struct tmp;
3211
3212 /* this is all probably wrong, there are a lot of fields
3213 * here that we don't have in e100_serial and maybe we
3214 * should set them to something else than 0.
3215 */
3216
1da177e4
LT		 3217 memset(&tmp, 0, sizeof(tmp));
3218 tmp.type = info->type;
3219 tmp.line = info->line;
d7283353 3220 tmp.port = (int)info->ioport;
1da177e4 3221 tmp.irq = info->irq;
b1d984cf 3222 tmp.flags = info->port.flags;
1da177e4 3223 tmp.baud_base = info->baud_base;
892c7cfc
JS		 3224 tmp.close_delay = info->port.close_delay;
3225 tmp.closing_wait = info->port.closing_wait;
1da177e4
LT		 3226 tmp.custom_divisor = info->custom_divisor;
3227 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3228 return -EFAULT;
3229 return 0;
3230}
3231
3232static int
3233set_serial_info(struct e100_serial *info,
3234 struct serial_struct *new_info)
3235{
3236 struct serial_struct new_serial;
3237 struct e100_serial old_info;
3238 int retval = 0;
3239
3240 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3241 return -EFAULT;
3242
3243 old_info = *info;
3244
3245 if (!capable(CAP_SYS_ADMIN)) {
3246 if ((new_serial.type != info->type) ||
892c7cfc 3247 (new_serial.close_delay != info->port.close_delay) ||
1da177e4 3248 ((new_serial.flags & ~ASYNC_USR_MASK) !=
b1d984cf 3249 (info->port.flags & ~ASYNC_USR_MASK)))
1da177e4 3250 return -EPERM;
b1d984cf 3251 info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
1da177e4
LT		 3252 (new_serial.flags & ASYNC_USR_MASK));
3253 goto check_and_exit;
3254 }
3255
b12d8dc2 3256 if (info->port.count > 1)
1da177e4
LT		 3257 return -EBUSY;
3258
3259 /*
3260 * OK, past this point, all the error checking has been done.
3261 * At this point, we start making changes.....
3262 */
3263
3264 info->baud_base = new_serial.baud_base;
b1d984cf 3265 info->port.flags = ((info->port.flags & ~ASYNC_FLAGS) |
1da177e4
LT		 3266 (new_serial.flags & ASYNC_FLAGS));
3267 info->custom_divisor = new_serial.custom_divisor;
3268 info->type = new_serial.type;
892c7cfc
JS		 3269 info->port.close_delay = new_serial.close_delay;
3270 info->port.closing_wait = new_serial.closing_wait;
b1d984cf 3271 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 3272
3273 check_and_exit:
d41861ca 3274 if (tty_port_initialized(&info->port))
1da177e4 3275 change_speed(info);
d41861ca 3276 else
1da177e4
LT		 3277 retval = startup(info);
3278 return retval;
3279}
3280
3281/*
3282 * get_lsr_info - get line status register info
3283 *
3284 * Purpose: Let user call ioctl() to get info when the UART physically
3285 * is emptied. On bus types like RS485, the transmitter must
3286 * release the bus after transmitting. This must be done when
3287 * the transmit shift register is empty, not be done when the
3288 * transmit holding register is empty. This functionality
3289 * allows an RS485 driver to be written in user space.
3290 */
3291static int
3292get_lsr_info(struct e100_serial * info, unsigned int *value)
3293{
3294 unsigned int result = TIOCSER_TEMT;
1da177e4
LT		 3295 unsigned long curr_time = jiffies;
3296 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3297 unsigned long elapsed_usec =
3298 (curr_time - info->last_tx_active) * 1000000/HZ +
3299 curr_time_usec - info->last_tx_active_usec;
3300
3301 if (info->xmit.head != info->xmit.tail ||
3302 elapsed_usec < 2*info->char_time_usec) {
3303 result = 0;
3304 }
1da177e4
LT		 3305
3306 if (copy_to_user(value, &result, sizeof(int)))
3307 return -EFAULT;
3308 return 0;
3309}
3310
3311#ifdef SERIAL_DEBUG_IO
3312struct state_str
3313{
3314 int state;
3315 const char *str;
3316};
3317
3318const struct state_str control_state_str[] = {
3319 {TIOCM_DTR, "DTR" },
3320 {TIOCM_RTS, "RTS"},
3321 {TIOCM_ST, "ST?" },
3322 {TIOCM_SR, "SR?" },
3323 {TIOCM_CTS, "CTS" },
3324 {TIOCM_CD, "CD" },
3325 {TIOCM_RI, "RI" },
3326 {TIOCM_DSR, "DSR" },
3327 {0, NULL }
3328};
3329
3330char *get_control_state_str(int MLines, char *s)
3331{
3332 int i = 0;
3333
3334 s[0]='\0';
3335 while (control_state_str[i].str != NULL) {
3336 if (MLines & control_state_str[i].state) {
3337 if (s[0] != '\0') {
3338 strcat(s, ", ");
3339 }
3340 strcat(s, control_state_str[i].str);
3341 }
3342 i++;
3343 }
3344 return s;
3345}
3346#endif
3347
d7283353 3348static int
77accbf5
JN		 3349rs_break(struct tty_struct *tty, int break_state)
3350{
3351 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3352 unsigned long flags;
3353
d7283353
AC		 3354 if (!info->ioport)
3355 return -EIO;
77accbf5
JN		 3356
3357 local_irq_save(flags);
3358 if (break_state == -1) {
3359 /* Go to manual mode and set the txd pin to 0 */
3360 /* Clear bit 7 (txd) and 6 (tr_enable) */
3361 info->tx_ctrl &= 0x3F;
3362 } else {
3363 /* Set bit 7 (txd) and 6 (tr_enable) */
3364 info->tx_ctrl |= (0x80 | 0x40);
3365 }
d7283353 3366 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
77accbf5 3367 local_irq_restore(flags);
d7283353 3368 return 0;
77accbf5
JN		 3369}
3370
1da177e4 3371static int
20b9d177 3372rs_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)
1da177e4 3373{
77accbf5 3374 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
978e595f 3375 unsigned long flags;
1da177e4 3376
978e595f 3377 local_irq_save(flags);
032c17e8 3378
77accbf5
JN		 3379 if (clear & TIOCM_RTS)
3380 e100_rts(info, 0);
3381 if (clear & TIOCM_DTR)
3382 e100_dtr(info, 0);
3383 /* Handle FEMALE behaviour */
3384 if (clear & TIOCM_RI)
3385 e100_ri_out(info, 0);
3386 if (clear & TIOCM_CD)
3387 e100_cd_out(info, 0);
3388
3389 if (set & TIOCM_RTS)
3390 e100_rts(info, 1);
3391 if (set & TIOCM_DTR)
3392 e100_dtr(info, 1);
3393 /* Handle FEMALE behaviour */
3394 if (set & TIOCM_RI)
3395 e100_ri_out(info, 1);
3396 if (set & TIOCM_CD)
3397 e100_cd_out(info, 1);
032c17e8 3398
978e595f 3399 local_irq_restore(flags);
77accbf5
JN		 3400 return 0;
3401}
3402
3403static int
60b33c13 3404rs_tiocmget(struct tty_struct *tty)
77accbf5
JN		 3405{
3406 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3407 unsigned int result;
978e595f
AC		 3408 unsigned long flags;
3409
3410 local_irq_save(flags);
1da177e4
LT		 3411
3412 result =
3413 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3414 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3415 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3416 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3417 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3418 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3419
978e595f 3420 local_irq_restore(flags);
032c17e8 3421
1da177e4 3422#ifdef SERIAL_DEBUG_IO
77accbf5
JN		 3423 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3424 info->line, result, result);
1da177e4
LT		 3425 {
3426 char s[100];
3427
3428 get_control_state_str(result, s);
77accbf5 3429 printk(KERN_DEBUG "state: %s\n", s);
1da177e4
LT		 3430 }
3431#endif
77accbf5 3432 return result;
1da177e4 3433
1da177e4
LT		 3434}
3435
3436
1da177e4 3437static int
6caa76b7 3438rs_ioctl(struct tty_struct *tty,
1da177e4
LT		 3439 unsigned int cmd, unsigned long arg)
3440{
3441 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3442
3443 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3444 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3445 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
18900ca6 3446 if (tty_io_error(tty))
1da177e4
LT		 3447 return -EIO;
3448 }
3449
3450 switch (cmd) {
77accbf5
JN		 3451 case TIOCGSERIAL:
3452 return get_serial_info(info,
3453 (struct serial_struct *) arg);
3454 case TIOCSSERIAL:
3455 return set_serial_info(info,
3456 (struct serial_struct *) arg);
3457 case TIOCSERGETLSR: /* Get line status register */
3458 return get_lsr_info(info, (unsigned int *) arg);
3459
3460 case TIOCSERGSTRUCT:
3461 if (copy_to_user((struct e100_serial *) arg,
3462 info, sizeof(struct e100_serial)))
3463 return -EFAULT;
3464 return 0;
1da177e4
LT		 3465
3466#if defined(CONFIG_ETRAX_RS485)
77accbf5
JN		 3467 case TIOCSERSETRS485:
3468 {
6fd1af4c
CS		 3469 /* In this ioctl we still use the old structure
3470 * rs485_control for backward compatibility
3471 * (if we use serial_rs485, then old user-level code
3472 * wouldn't work anymore...).
3473 * The use of this ioctl is deprecated: use TIOCSRS485
3474 * instead.*/
77accbf5 3475 struct rs485_control rs485ctrl;
6fd1af4c
CS		 3476 struct serial_rs485 rs485data;
3477 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
77accbf5
JN		 3478 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3479 sizeof(rs485ctrl)))
3480 return -EFAULT;
1da177e4 3481
6fd1af4c
CS		 3482 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3483 rs485data.flags = 0;
c7213fc4 3484
6fd1af4c
CS		 3485 if (rs485ctrl.enabled)
3486 rs485data.flags |= SER_RS485_ENABLED;
3487 else
3488 rs485data.flags &= ~(SER_RS485_ENABLED);
3489
3490 if (rs485ctrl.rts_on_send)
3491 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3492 else
3493 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3494
3495 if (rs485ctrl.rts_after_sent)
3496 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3497 else
3498 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3499
3500 return e100_enable_rs485(tty, &rs485data);
77accbf5 3501 }
1da177e4 3502
6fd1af4c
CS		 3503 case TIOCSRS485:
3504 {
3505 /* This is the new version of TIOCSRS485, with new
3506 * data structure serial_rs485 */
3507 struct serial_rs485 rs485data;
3508 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3509 sizeof(rs485data)))
3510 return -EFAULT;
3511
3512 return e100_enable_rs485(tty, &rs485data);
3513 }
3514
f1d23ed8
CS		 3515 case TIOCGRS485:
3516 {
3517 struct serial_rs485 *rs485data =
3518 &(((struct e100_serial *)tty->driver_data)->rs485);
3519 /* This is the ioctl to get RS485 data from user-space */
3520 if (copy_to_user((struct serial_rs485 *) arg,
3521 rs485data,
94479c01 3522 sizeof(struct serial_rs485)))
f1d23ed8
CS		 3523 return -EFAULT;
3524 break;
3525 }
6fd1af4c 3526
77accbf5
JN		 3527 case TIOCSERWRRS485:
3528 {
3529 struct rs485_write rs485wr;
3530 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3531 sizeof(rs485wr)))
3532 return -EFAULT;
1da177e4 3533
77accbf5
JN		 3534 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3535 }
1da177e4
LT		 3536#endif
3537
77accbf5
JN		 3538 default:
3539 return -ENOIOCTLCMD;
1da177e4
LT		 3540 }
3541 return 0;
3542}
3543
3544static void
606d099c 3545rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 3546{
3547 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3548
1da177e4
LT		 3549 change_speed(info);
3550
3551 /* Handle turning off CRTSCTS */
9db276f8 3552 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
1da177e4 3553 rs_start(tty);
1da177e4
LT		 3554
3555}
3556
1da177e4
LT		 3557/*
3558 * ------------------------------------------------------------
3559 * rs_close()
3560 *
3561 * This routine is called when the serial port gets closed. First, we
3562 * wait for the last remaining data to be sent. Then, we unlink its
3563 * S structure from the interrupt chain if necessary, and we free
3564 * that IRQ if nothing is left in the chain.
3565 * ------------------------------------------------------------
3566 */
3567static void
3568rs_close(struct tty_struct *tty, struct file * filp)
3569{
3570 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3571 unsigned long flags;
3572
3573 if (!info)
3574 return;
3575
3576 /* interrupts are disabled for this entire function */
3577
77accbf5 3578 local_irq_save(flags);
1da177e4
LT		 3579
3580 if (tty_hung_up_p(filp)) {
77accbf5 3581 local_irq_restore(flags);
1da177e4
LT		 3582 return;
3583 }
3584
3585#ifdef SERIAL_DEBUG_OPEN
3586 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3587 info->line, info->count);
3588#endif
b12d8dc2 3589 if ((tty->count == 1) && (info->port.count != 1)) {
1da177e4
LT		 3590 /*
3591 * Uh, oh. tty->count is 1, which means that the tty
3592 * structure will be freed. Info->count should always
3593 * be one in these conditions. If it's greater than
3594 * one, we've got real problems, since it means the
3595 * serial port won't be shutdown.
3596 */
3d43b7d5 3597 printk(KERN_ERR
1da177e4 3598 "rs_close: bad serial port count; tty->count is 1, "
b12d8dc2
JS		 3599 "info->count is %d\n", info->port.count);
3600 info->port.count = 1;
1da177e4 3601 }
b12d8dc2 3602 if (--info->port.count < 0) {
3d43b7d5 3603 printk(KERN_ERR "rs_close: bad serial port count for ttyS%d: %d\n",
b12d8dc2
JS		 3604 info->line, info->port.count);
3605 info->port.count = 0;
1da177e4 3606 }
b12d8dc2 3607 if (info->port.count) {
77accbf5 3608 local_irq_restore(flags);
1da177e4
LT		 3609 return;
3610 }
1da177e4
LT		 3611 /*
3612 * Now we wait for the transmit buffer to clear; and we notify
3613 * the line discipline to only process XON/XOFF characters.
3614 */
3615 tty->closing = 1;
892c7cfc
JS		 3616 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE)
3617 tty_wait_until_sent(tty, info->port.closing_wait);
1da177e4
LT		 3618 /*
3619 * At this point we stop accepting input. To do this, we
3620 * disable the serial receiver and the DMA receive interrupt.
3621 */
3622#ifdef SERIAL_HANDLE_EARLY_ERRORS
3623 e100_disable_serial_data_irq(info);
3624#endif
3625
1da177e4
LT		 3626 e100_disable_rx(info);
3627 e100_disable_rx_irq(info);
3628
d41861ca 3629 if (tty_port_initialized(&info->port)) {
1da177e4
LT		 3630 /*
3631 * Before we drop DTR, make sure the UART transmitter
3632 * has completely drained; this is especially
3633 * important as we have a transmit FIFO!
3634 */
3635 rs_wait_until_sent(tty, HZ);
3636 }
1da177e4
LT		 3637
3638 shutdown(info);
978e595f 3639 rs_flush_buffer(tty);
454aa389 3640 tty_ldisc_flush(tty);
1da177e4
LT		 3641 tty->closing = 0;
3642 info->event = 0;
a88487c7 3643 info->port.tty = NULL;
b12d8dc2 3644 if (info->port.blocked_open) {
892c7cfc
JS		 3645 if (info->port.close_delay)
3646 schedule_timeout_interruptible(info->port.close_delay);
4aeaeb0c 3647 wake_up_interruptible(&info->port.open_wait);
1da177e4 3648 }
77accbf5 3649 local_irq_restore(flags);
807c8d81 3650 tty_port_set_active(&info->port, 0);
1da177e4
LT		 3651
3652 /* port closed */
3653
3654#if defined(CONFIG_ETRAX_RS485)
6fd1af4c
CS		 3655 if (info->rs485.flags & SER_RS485_ENABLED) {
3656 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4
LT		 3657#if defined(CONFIG_ETRAX_RS485_ON_PA)
3658 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
1da177e4
LT		 3659#endif
3660 }
3661#endif
77accbf5
JN		 3662
3663 /*
3664 * Release any allocated DMA irq's.
3665 */
3666 if (info->dma_in_enabled) {
3667 free_irq(info->dma_in_irq_nbr, info);
3668 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3669 info->uses_dma_in = 0;
3670#ifdef SERIAL_DEBUG_OPEN
3671 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3672 info->dma_in_irq_description);
3673#endif
3674 }
3675 if (info->dma_out_enabled) {
3676 free_irq(info->dma_out_irq_nbr, info);
3677 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3678 info->uses_dma_out = 0;
3679#ifdef SERIAL_DEBUG_OPEN
3680 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3681 info->dma_out_irq_description);
3682#endif
3683 }
1da177e4
LT		 3684}
3685
3686/*
3687 * rs_wait_until_sent() --- wait until the transmitter is empty
3688 */
3689static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3690{
3691 unsigned long orig_jiffies;
3692 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3693 unsigned long curr_time = jiffies;
3694 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3695 long elapsed_usec =
3696 (curr_time - info->last_tx_active) * (1000000/HZ) +
3697 curr_time_usec - info->last_tx_active_usec;
3698
3699 /*
3700 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3701 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3702 */
3703 orig_jiffies = jiffies;
3704 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3705 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3706 (elapsed_usec < 2*info->char_time_usec)) {
3c76bc5b 3707 schedule_timeout_interruptible(1);
1da177e4
LT		 3708 if (signal_pending(current))
3709 break;
3710 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3711 break;
3712 curr_time = jiffies;
3713 curr_time_usec = GET_JIFFIES_USEC();
3714 elapsed_usec =
3715 (curr_time - info->last_tx_active) * (1000000/HZ) +
3716 curr_time_usec - info->last_tx_active_usec;
3717 }
3718 set_current_state(TASK_RUNNING);
3719}
3720
3721/*
3722 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3723 */
3724void
3725rs_hangup(struct tty_struct *tty)
3726{
3727 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3728
3729 rs_flush_buffer(tty);
3730 shutdown(info);
3731 info->event = 0;
b12d8dc2 3732 info->port.count = 0;
807c8d81 3733 tty_port_set_active(&info->port, 0);
a88487c7 3734 info->port.tty = NULL;
4aeaeb0c 3735 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 3736}
3737
3738/*
3739 * ------------------------------------------------------------
3740 * rs_open() and friends
3741 * ------------------------------------------------------------
3742 */
3743static int
3744block_til_ready(struct tty_struct *tty, struct file * filp,
3745 struct e100_serial *info)
3746{
3747 DECLARE_WAITQUEUE(wait, current);
3748 unsigned long flags;
3749 int retval;
e359a4e3 3750 int do_clocal = 0;
1da177e4 3751
1da177e4
LT		 3752 /*
3753 * If non-blocking mode is set, or the port is not enabled,
3754 * then make the check up front and then exit.
3755 */
18900ca6 3756 if ((filp->f_flags & O_NONBLOCK) || tty_io_error(tty)) {
807c8d81 3757 tty_port_set_active(&info->port, 1);
1da177e4
LT		 3758 return 0;
3759 }
3760
9db276f8
PH		 3761 if (C_CLOCAL(tty))
3762 do_clocal = 1;
1da177e4
LT		 3763
3764 /*
3765 * Block waiting for the carrier detect and the line to become
3766 * free (i.e., not in use by the callout). While we are in
b12d8dc2 3767 * this loop, info->port.count is dropped by one, so that
1da177e4
LT		 3768 * rs_close() knows when to free things. We restore it upon
3769 * exit, either normal or abnormal.
3770 */
3771 retval = 0;
4aeaeb0c 3772 add_wait_queue(&info->port.open_wait, &wait);
1da177e4
LT		 3773#ifdef SERIAL_DEBUG_OPEN
3774 printk("block_til_ready before block: ttyS%d, count = %d\n",
b12d8dc2 3775 info->line, info->port.count);
1da177e4 3776#endif
77accbf5 3777 local_irq_save(flags);
e359a4e3 3778 info->port.count--;
77accbf5 3779 local_irq_restore(flags);
b12d8dc2 3780 info->port.blocked_open++;
1da177e4 3781 while (1) {
77accbf5 3782 local_irq_save(flags);
1da177e4
LT		 3783 /* assert RTS and DTR */
3784 e100_rts(info, 1);
3785 e100_dtr(info, 1);
77accbf5 3786 local_irq_restore(flags);
1da177e4 3787 set_current_state(TASK_INTERRUPTIBLE);
d41861ca 3788 if (tty_hung_up_p(filp) || !tty_port_initialized(&info->port)) {
1da177e4 3789#ifdef SERIAL_DO_RESTART
b1d984cf 3790 if (info->port.flags & ASYNC_HUP_NOTIFY)
1da177e4
LT		 3791 retval = -EAGAIN;
3792 else
3793 retval = -ERESTARTSYS;
3794#else
3795 retval = -EAGAIN;
3796#endif
3797 break;
3798 }
fef062cb 3799 if (do_clocal)
1da177e4
LT		 3800 /* && (do_clocal || DCD_IS_ASSERTED) */
3801 break;
3802 if (signal_pending(current)) {
3803 retval = -ERESTARTSYS;
3804 break;
3805 }
3806#ifdef SERIAL_DEBUG_OPEN
3807 printk("block_til_ready blocking: ttyS%d, count = %d\n",
b12d8dc2 3808 info->line, info->port.count);
1da177e4 3809#endif
89c8d91e 3810 tty_unlock(tty);
1da177e4 3811 schedule();
89c8d91e 3812 tty_lock(tty);
1da177e4
LT		 3813 }
3814 set_current_state(TASK_RUNNING);
4aeaeb0c 3815 remove_wait_queue(&info->port.open_wait, &wait);
e359a4e3 3816 if (!tty_hung_up_p(filp))
b12d8dc2
JS		 3817 info->port.count++;
3818 info->port.blocked_open--;
1da177e4
LT		 3819#ifdef SERIAL_DEBUG_OPEN
3820 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
b12d8dc2 3821 info->line, info->port.count);
1da177e4
LT		 3822#endif
3823 if (retval)
3824 return retval;
807c8d81 3825 tty_port_set_active(&info->port, 1);
1da177e4
LT		 3826 return 0;
3827}
3828
77accbf5
JN		 3829static void
3830deinit_port(struct e100_serial *info)
3831{
3832 if (info->dma_out_enabled) {
3833 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3834 free_irq(info->dma_out_irq_nbr, info);
3835 }
3836 if (info->dma_in_enabled) {
3837 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3838 free_irq(info->dma_in_irq_nbr, info);
3839 }
3840}
3841
1da177e4
LT		 3842/*
3843 * This routine is called whenever a serial port is opened.
3844 * It performs the serial-specific initialization for the tty structure.
3845 */
3846static int
3847rs_open(struct tty_struct *tty, struct file * filp)
3848{
3849 struct e100_serial *info;
410235fd 3850 int retval;
77accbf5 3851 int allocated_resources = 0;
1da177e4 3852
410235fd 3853 info = rs_table + tty->index;
1da177e4
LT		 3854 if (!info->enabled)
3855 return -ENODEV;
3856
3857#ifdef SERIAL_DEBUG_OPEN
3858 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
b12d8dc2 3859 info->port.count);
1da177e4
LT		 3860#endif
3861
b12d8dc2 3862 info->port.count++;
1da177e4 3863 tty->driver_data = info;
a88487c7 3864 info->port.tty = tty;
1da177e4 3865
b1d984cf 3866 info->port.low_latency = !!(info->port.flags & ASYNC_LOW_LATENCY);
1da177e4 3867
77accbf5
JN		 3868 /*
3869 * If DMA is enabled try to allocate the irq's.
3870 */
b12d8dc2 3871 if (info->port.count == 1) {
77accbf5
JN		 3872 allocated_resources = 1;
3873 if (info->dma_in_enabled) {
3874 if (request_irq(info->dma_in_irq_nbr,
3875 rec_interrupt,
3876 info->dma_in_irq_flags,
3877 info->dma_in_irq_description,
3878 info)) {
3879 printk(KERN_WARNING "DMA irq '%s' busy; "
3880 "falling back to non-DMA mode\n",
3881 info->dma_in_irq_description);
3882 /* Make sure we never try to use DMA in */
3883 /* for the port again. */
3884 info->dma_in_enabled = 0;
3885 } else if (cris_request_dma(info->dma_in_nbr,
3886 info->dma_in_irq_description,
3887 DMA_VERBOSE_ON_ERROR,
3888 info->dma_owner)) {
3889 free_irq(info->dma_in_irq_nbr, info);
3890 printk(KERN_WARNING "DMA '%s' busy; "
3891 "falling back to non-DMA mode\n",
3892 info->dma_in_irq_description);
3893 /* Make sure we never try to use DMA in */
3894 /* for the port again. */
3895 info->dma_in_enabled = 0;
3896 }
3897#ifdef SERIAL_DEBUG_OPEN
3898 else
3899 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
3900 info->dma_in_irq_description);
3901#endif
3902 }
3903 if (info->dma_out_enabled) {
3904 if (request_irq(info->dma_out_irq_nbr,
3905 tr_interrupt,
3906 info->dma_out_irq_flags,
3907 info->dma_out_irq_description,
3908 info)) {
3909 printk(KERN_WARNING "DMA irq '%s' busy; "
3910 "falling back to non-DMA mode\n",
3911 info->dma_out_irq_description);
3912 /* Make sure we never try to use DMA out */
3913 /* for the port again. */
3914 info->dma_out_enabled = 0;
3915 } else if (cris_request_dma(info->dma_out_nbr,
3916 info->dma_out_irq_description,
3917 DMA_VERBOSE_ON_ERROR,
3918 info->dma_owner)) {
3919 free_irq(info->dma_out_irq_nbr, info);
3920 printk(KERN_WARNING "DMA '%s' busy; "
3921 "falling back to non-DMA mode\n",
3922 info->dma_out_irq_description);
3923 /* Make sure we never try to use DMA out */
3924 /* for the port again. */
3925 info->dma_out_enabled = 0;
3926 }
3927#ifdef SERIAL_DEBUG_OPEN
3928 else
3929 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
3930 info->dma_out_irq_description);
3931#endif
3932 }
3933 }
3934
1da177e4
LT		 3935 /*
3936 * Start up the serial port
3937 */
3938
3939 retval = startup(info);
77accbf5
JN		 3940 if (retval) {
3941 if (allocated_resources)
3942 deinit_port(info);
3943
b12d8dc2 3944 /* FIXME Decrease count info->port.count here too? */
1da177e4 3945 return retval;
77accbf5
JN		 3946 }
3947
1da177e4
LT		 3948
3949 retval = block_til_ready(tty, filp, info);
3950 if (retval) {
3951#ifdef SERIAL_DEBUG_OPEN
3952 printk("rs_open returning after block_til_ready with %d\n",
3953 retval);
3954#endif
77accbf5
JN		 3955 if (allocated_resources)
3956 deinit_port(info);
3957
1da177e4
LT		 3958 return retval;
3959 }
3960
1da177e4
LT		 3961#ifdef SERIAL_DEBUG_OPEN
3962 printk("rs_open ttyS%d successful...\n", info->line);
3963#endif
3964 DLOG_INT_TRIG( log_int_pos = 0);
3965
3966 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
3967 info->icount.rx = 0;
3968 } );
3969
3970 return 0;
3971}
3972
9e040a3e 3973#ifdef CONFIG_PROC_FS
1da177e4
LT		 3974/*
3975 * /proc fs routines....
3976 */
3977
9e040a3e 3978static void seq_line_info(struct seq_file *m, struct e100_serial *info)
1da177e4 3979{
1da177e4
LT		 3980 unsigned long tmp;
3981
9e040a3e
JN		 3982 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
3983 info->line, (unsigned long)info->ioport, info->irq);
1da177e4 3984
d7283353 3985 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
9e040a3e
JN		 3986 seq_printf(m, "\n");
3987 return;
1da177e4
LT		 3988 }
3989
9e040a3e
JN		 3990 seq_printf(m, " baud:%d", info->baud);
3991 seq_printf(m, " tx:%lu rx:%lu",
1da177e4
LT		 3992 (unsigned long)info->icount.tx,
3993 (unsigned long)info->icount.rx);
3994 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
9e040a3e
JN		 3995 if (tmp)
3996 seq_printf(m, " tx_pend:%lu/%lu",
3997 (unsigned long)tmp,
3998 (unsigned long)SERIAL_XMIT_SIZE);
1da177e4 3999
9e040a3e
JN		 4000 seq_printf(m, " rx_pend:%lu/%lu",
4001 (unsigned long)info->recv_cnt,
4002 (unsigned long)info->max_recv_cnt);
1da177e4
LT		 4003
4004#if 1
a88487c7 4005 if (info->port.tty) {
a88487c7 4006 if (info->port.tty->stopped)
9e040a3e
JN		 4007 seq_printf(m, " stopped:%i",
4008 (int)info->port.tty->stopped);
1da177e4
LT		 4009 }
4010
4011 {
d7283353 4012 unsigned char rstat = info->ioport[REG_STATUS];
9e040a3e
JN		 4013 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4014 seq_printf(m, " xoff_detect:1");
1da177e4
LT		 4015 }
4016
4017#endif
4018
1da177e4 4019 if (info->icount.frame)
9e040a3e 4020 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
1da177e4
LT		 4021
4022 if (info->icount.parity)
9e040a3e 4023 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
1da177e4
LT		 4024
4025 if (info->icount.brk)
9e040a3e 4026 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
1da177e4
LT		 4027
4028 if (info->icount.overrun)
9e040a3e 4029 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
1da177e4
LT		 4030
4031 /*
4032 * Last thing is the RS-232 status lines
4033 */
9e040a3e
JN		 4034 if (!E100_RTS_GET(info))
4035 seq_puts(m, "|RTS");
4036 if (!E100_CTS_GET(info))
4037 seq_puts(m, "|CTS");
4038 if (!E100_DTR_GET(info))
4039 seq_puts(m, "|DTR");
4040 if (!E100_DSR_GET(info))
4041 seq_puts(m, "|DSR");
4042 if (!E100_CD_GET(info))
4043 seq_puts(m, "|CD");
4044 if (!E100_RI_GET(info))
4045 seq_puts(m, "|RI");
4046 seq_puts(m, "\n");
1da177e4
LT		 4047}
4048
9e040a3e
JN		 4049
4050static int crisv10_proc_show(struct seq_file *m, void *v)
1da177e4 4051{
9e040a3e 4052 int i;
1da177e4 4053
9e040a3e
JN		 4054 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4055
4056 for (i = 0; i < NR_PORTS; i++) {
1da177e4
LT		 4057 if (!rs_table[i].enabled)
4058 continue;
9e040a3e 4059 seq_line_info(m, &rs_table[i]);
1da177e4
LT		 4060 }
4061#ifdef DEBUG_LOG_INCLUDED
4062 for (i = 0; i < debug_log_pos; i++) {
9e040a3e
JN		 4063 seq_printf(m, "%-4i %lu.%lu ",
4064 i, debug_log[i].time,
4065 timer_data_to_ns(debug_log[i].timer_data));
4066 seq_printf(m, debug_log[i].string, debug_log[i].value);
1da177e4 4067 }
9e040a3e 4068 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
1da177e4
LT		 4069 debug_log_pos = 0;
4070#endif
9e040a3e
JN		 4071 return 0;
4072}
1da177e4 4073
9e040a3e
JN		 4074static int crisv10_proc_open(struct inode *inode, struct file *file)
4075{
4076 return single_open(file, crisv10_proc_show, NULL);
1da177e4
LT		 4077}
4078
9e040a3e
JN		 4079static const struct file_operations crisv10_proc_fops = {
4080 .owner = THIS_MODULE,
4081 .open = crisv10_proc_open,
4082 .read = seq_read,
4083 .llseek = seq_lseek,
4084 .release = single_release,
4085};
4086#endif
4087
4088
1da177e4
LT		 4089/* Finally, routines used to initialize the serial driver. */
4090
9e040a3e 4091static void show_serial_version(void)
1da177e4
LT		 4092{
4093 printk(KERN_INFO
9e040a3e
JN		 4094 "ETRAX 100LX serial-driver %s, "
4095 "(c) 2000-2004 Axis Communications AB\r\n",
1da177e4
LT		 4096 &serial_version[11]); /* "$Revision: x.yy" */
4097}
4098
146b4d5b 4099/* rs_init inits the driver at boot (using the initcall chain) */
1da177e4 4100
b68e31d0 4101static const struct tty_operations rs_ops = {
1da177e4
LT		 4102 .open = rs_open,
4103 .close = rs_close,
4104 .write = rs_write,
4105 .flush_chars = rs_flush_chars,
4106 .write_room = rs_write_room,
4107 .chars_in_buffer = rs_chars_in_buffer,
4108 .flush_buffer = rs_flush_buffer,
4109 .ioctl = rs_ioctl,
4110 .throttle = rs_throttle,
4111 .unthrottle = rs_unthrottle,
4112 .set_termios = rs_set_termios,
4113 .stop = rs_stop,
4114 .start = rs_start,
4115 .hangup = rs_hangup,
4116 .break_ctl = rs_break,
4117 .send_xchar = rs_send_xchar,
4118 .wait_until_sent = rs_wait_until_sent,
77accbf5 4119 .tiocmget = rs_tiocmget,
9e040a3e
JN		 4120 .tiocmset = rs_tiocmset,
4121#ifdef CONFIG_PROC_FS
4122 .proc_fops = &crisv10_proc_fops,
4123#endif
1da177e4
LT		 4124};
4125
9e040a3e 4126static int __init rs_init(void)
1da177e4
LT		 4127{
4128 int i;
4129 struct e100_serial *info;
4130 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4131
4132 if (!driver)
4133 return -ENOMEM;
4134
4135 show_serial_version();
4136
4137 /* Setup the timed flush handler system */
4138
4139#if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
e99e88a9 4140 timer_setup(&flush_timer, timed_flush_handler, 0);
77accbf5
JN		 4141 mod_timer(&flush_timer, jiffies + 5);
4142#endif
4143
4144#if defined(CONFIG_ETRAX_RS485)
4145#if defined(CONFIG_ETRAX_RS485_ON_PA)
2f7861de 4146 if (cris_io_interface_allocate_pins(if_serial_0, 'a', rs485_pa_bit,
77accbf5 4147 rs485_pa_bit)) {
3d43b7d5 4148 printk(KERN_ERR "ETRAX100LX serial: Could not allocate "
77accbf5 4149 "RS485 pin\n");
41ca7322 4150 put_tty_driver(driver);
77accbf5
JN		 4151 return -EBUSY;
4152 }
4153#endif
1da177e4
LT		 4154#endif
4155
4156 /* Initialize the tty_driver structure */
4157
4158 driver->driver_name = "serial";
4159 driver->name = "ttyS";
4160 driver->major = TTY_MAJOR;
4161 driver->minor_start = 64;
4162 driver->type = TTY_DRIVER_TYPE_SERIAL;
4163 driver->subtype = SERIAL_TYPE_NORMAL;
4164 driver->init_termios = tty_std_termios;
4165 driver->init_termios.c_cflag =
4166 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
606d099c
AC		 4167 driver->init_termios.c_ispeed = 115200;
4168 driver->init_termios.c_ospeed = 115200;
c4d6ebeb 4169 driver->flags = TTY_DRIVER_REAL_RAW;
1da177e4
LT		 4170
4171 tty_set_operations(driver, &rs_ops);
4172 serial_driver = driver;
1da177e4 4173
b19e2ca7 4174 /* do some initializing for the separate ports */
1da177e4 4175 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
77accbf5
JN		 4176 if (info->enabled) {
4177 if (cris_request_io_interface(info->io_if,
4178 info->io_if_description)) {
3d43b7d5 4179 printk(KERN_ERR "ETRAX100LX async serial: "
77accbf5
JN		 4180 "Could not allocate IO pins for "
4181 "%s, port %d\n",
4182 info->io_if_description, i);
4183 info->enabled = 0;
4184 }
4185 }
953756e2 4186 tty_port_init(&info->port);
1da177e4
LT		 4187 info->uses_dma_in = 0;
4188 info->uses_dma_out = 0;
4189 info->line = i;
a88487c7 4190 info->port.tty = NULL;
1da177e4
LT		 4191 info->type = PORT_ETRAX;
4192 info->tr_running = 0;
4193 info->forced_eop = 0;
4194 info->baud_base = DEF_BAUD_BASE;
4195 info->custom_divisor = 0;
1da177e4
LT		 4196 info->x_char = 0;
4197 info->event = 0;
1da177e4
LT		 4198 info->xmit.buf = NULL;
4199 info->xmit.tail = info->xmit.head = 0;
4200 info->first_recv_buffer = info->last_recv_buffer = NULL;
4201 info->recv_cnt = info->max_recv_cnt = 0;
4202 info->last_tx_active_usec = 0;
4203 info->last_tx_active = 0;
4204
4205#if defined(CONFIG_ETRAX_RS485)
4206 /* Set sane defaults */
6fd1af4c
CS		 4207 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4208 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
1da177e4 4209 info->rs485.delay_rts_before_send = 0;
6fd1af4c 4210 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4 4211#endif
77accbf5 4212 INIT_WORK(&info->work, do_softint);
1da177e4
LT		 4213
4214 if (info->enabled) {
078dee2d
KV		 4215 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n",
4216 serial_driver->name, info->line, info->ioport);
1da177e4 4217 }
b19e2ca7 4218 tty_port_link_device(&info->port, driver, i);
1da177e4 4219 }
b19e2ca7
JS		 4220
4221 if (tty_register_driver(driver))
4222 panic("Couldn't register serial driver\n");
4223
1da177e4
LT		 4224#ifdef CONFIG_ETRAX_FAST_TIMER
4225#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4226 memset(fast_timers, 0, sizeof(fast_timers));
4227#endif
4228#ifdef CONFIG_ETRAX_RS485
4229 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4230#endif
4231 fast_timer_init();
4232#endif
4233
77accbf5 4234#ifndef CONFIG_ETRAX_KGDB
1da177e4
LT		 4235 /* Not needed in simulator. May only complicate stuff. */
4236 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4237
77accbf5 4238 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
9cfb5c05 4239 IRQF_SHARED, "serial ", driver))
71cc2c21 4240 panic("%s: Failed to request irq8", __func__);
1da177e4 4241
1da177e4 4242#endif
77accbf5 4243
1da177e4
LT		 4244 return 0;
4245}
4246
4247/* this makes sure that rs_init is called during kernel boot */
146b4d5b 4248device_initcall(rs_init);
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