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crisv10: use *_wait from tty_port
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77accbf5 1/*
1da177e4
LT		 2 * Serial port driver for the ETRAX 100LX chip
3 *
77accbf5 4 * Copyright (C) 1998-2007 Axis Communications AB
1da177e4
LT		 5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
1da177e4
LT		 8 */
9
10static char *serial_version = "$Revision: 1.25 $";
11
1da177e4
LT		 12#include <linux/types.h>
13#include <linux/errno.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/timer.h>
17#include <linux/interrupt.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/major.h>
21#include <linux/string.h>
22#include <linux/fcntl.h>
23#include <linux/mm.h>
24#include <linux/slab.h>
25#include <linux/init.h>
1da177e4 26#include <linux/kernel.h>
f392ecfa 27#include <linux/mutex.h>
1977f032 28#include <linux/bitops.h>
9e040a3e
JN		 29#include <linux/seq_file.h>
30#include <linux/delay.h>
31#include <linux/module.h>
32#include <linux/uaccess.h>
33#include <linux/io.h>
1da177e4 34
1da177e4 35#include <asm/irq.h>
77accbf5 36#include <asm/dma.h>
1da177e4 37
556dcee7 38#include <arch/svinto.h>
b1a154db 39#include <arch/system.h>
1da177e4
LT		 40
41/* non-arch dependent serial structures are in linux/serial.h */
42#include <linux/serial.h>
43/* while we keep our own stuff (struct e100_serial) in a local .h file */
77accbf5 44#include "crisv10.h"
1da177e4 45#include <asm/fasttimer.h>
556dcee7 46#include <arch/io_interface_mux.h>
1da177e4
LT		 47
48#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
49#ifndef CONFIG_ETRAX_FAST_TIMER
50#error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
51#endif
52#endif
53
54#if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
55 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
56#error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
57#endif
58
59#if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
60#error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
61#endif
62
63/*
64 * All of the compatibilty code so we can compile serial.c against
65 * older kernels is hidden in serial_compat.h
66 */
67#if defined(LOCAL_HEADERS)
68#include "serial_compat.h"
69#endif
70
1da177e4
LT		 71struct tty_driver *serial_driver;
72
1da177e4
LT		 73/* number of characters left in xmit buffer before we ask for more */
74#define WAKEUP_CHARS 256
75
76//#define SERIAL_DEBUG_INTR
77//#define SERIAL_DEBUG_OPEN
78//#define SERIAL_DEBUG_FLOW
79//#define SERIAL_DEBUG_DATA
80//#define SERIAL_DEBUG_THROTTLE
81//#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
82//#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
83
84/* Enable this to use serial interrupts to handle when you
85 expect the first received event on the serial port to
86 be an error, break or similar. Used to be able to flash IRMA
87 from eLinux */
88#define SERIAL_HANDLE_EARLY_ERRORS
89
1da177e4
LT		 90/* Currently 16 descriptors x 128 bytes = 2048 bytes */
91#define SERIAL_DESCR_BUF_SIZE 256
92
93#define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
94#define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
95
96/* We don't want to load the system with massive fast timer interrupt
97 * on high baudrates so limit it to 250 us (4kHz) */
98#define MIN_FLUSH_TIME_USEC 250
99
100/* Add an x here to log a lot of timer stuff */
101#define TIMERD(x)
102/* Debug details of interrupt handling */
103#define DINTR1(x) /* irq on/off, errors */
104#define DINTR2(x) /* tx and rx */
105/* Debug flip buffer stuff */
106#define DFLIP(x)
107/* Debug flow control and overview of data flow */
108#define DFLOW(x)
109#define DBAUD(x)
110#define DLOG_INT_TRIG(x)
111
112//#define DEBUG_LOG_INCLUDED
113#ifndef DEBUG_LOG_INCLUDED
114#define DEBUG_LOG(line, string, value)
115#else
116struct debug_log_info
117{
118 unsigned long time;
119 unsigned long timer_data;
120// int line;
121 const char *string;
122 int value;
123};
124#define DEBUG_LOG_SIZE 4096
125
126struct debug_log_info debug_log[DEBUG_LOG_SIZE];
127int debug_log_pos = 0;
128
129#define DEBUG_LOG(_line, _string, _value) do { \
130 if ((_line) == SERIAL_DEBUG_LINE) {\
131 debug_log_func(_line, _string, _value); \
132 }\
133}while(0)
134
135void debug_log_func(int line, const char *string, int value)
136{
137 if (debug_log_pos < DEBUG_LOG_SIZE) {
138 debug_log[debug_log_pos].time = jiffies;
139 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
140// debug_log[debug_log_pos].line = line;
141 debug_log[debug_log_pos].string = string;
142 debug_log[debug_log_pos].value = value;
143 debug_log_pos++;
144 }
145 /*printk(string, value);*/
146}
147#endif
148
149#ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
150/* Default number of timer ticks before flushing rx fifo
151 * When using "little data, low latency applications: use 0
152 * When using "much data applications (PPP)" use ~5
153 */
154#define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
155#endif
156
157unsigned long timer_data_to_ns(unsigned long timer_data);
158
159static void change_speed(struct e100_serial *info);
160static void rs_throttle(struct tty_struct * tty);
161static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
77accbf5
JN		 162static int rs_write(struct tty_struct *tty,
163 const unsigned char *buf, int count);
1da177e4 164#ifdef CONFIG_ETRAX_RS485
77accbf5
JN		 165static int e100_write_rs485(struct tty_struct *tty,
166 const unsigned char *buf, int count);
1da177e4 167#endif
77accbf5 168static int get_lsr_info(struct e100_serial *info, unsigned int *value);
1da177e4
LT		 169
170
171#define DEF_BAUD 115200 /* 115.2 kbit/s */
1da177e4
LT		 172#define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
173/* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
174#define DEF_TX 0x80 /* or SERIAL_CTRL_B */
175
176/* offsets from R_SERIALx_CTRL */
177
178#define REG_DATA 0
179#define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
180#define REG_TR_DATA 0
181#define REG_STATUS 1
182#define REG_TR_CTRL 1
183#define REG_REC_CTRL 2
184#define REG_BAUD 3
185#define REG_XOFF 4 /* this is a 32 bit register */
186
187/* The bitfields are the same for all serial ports */
188#define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
189#define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
190#define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
191#define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
192#define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
193
194#define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
195
196/* Values for info->errorcode */
197#define ERRCODE_SET_BREAK (TTY_BREAK)
198#define ERRCODE_INSERT 0x100
199#define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
200
201#define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
202
203/*
204 * General note regarding the use of IO_* macros in this file:
205 *
206 * We will use the bits defined for DMA channel 6 when using various
207 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
208 * the same for all channels (which of course they are).
209 *
210 * We will also use the bits defined for serial port 0 when writing commands
211 * to the different ports, as these bits too are the same for all ports.
212 */
213
214
215/* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
216static const unsigned long e100_ser_int_mask = 0
217#ifdef CONFIG_ETRAX_SERIAL_PORT0
218| IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
219#endif
220#ifdef CONFIG_ETRAX_SERIAL_PORT1
221| IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
222#endif
223#ifdef CONFIG_ETRAX_SERIAL_PORT2
224| IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
225#endif
226#ifdef CONFIG_ETRAX_SERIAL_PORT3
227| IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
228#endif
229;
230unsigned long r_alt_ser_baudrate_shadow = 0;
231
232/* this is the data for the four serial ports in the etrax100 */
233/* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
234/* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
235
236static struct e100_serial rs_table[] = {
237 { .baud = DEF_BAUD,
d7283353 238 .ioport = (unsigned char *)R_SERIAL0_CTRL,
1da177e4
LT		 239 .irq = 1U << 12, /* uses DMA 6 and 7 */
240 .oclrintradr = R_DMA_CH6_CLR_INTR,
241 .ofirstadr = R_DMA_CH6_FIRST,
242 .ocmdadr = R_DMA_CH6_CMD,
243 .ostatusadr = R_DMA_CH6_STATUS,
244 .iclrintradr = R_DMA_CH7_CLR_INTR,
245 .ifirstadr = R_DMA_CH7_FIRST,
246 .icmdadr = R_DMA_CH7_CMD,
247 .idescradr = R_DMA_CH7_DESCR,
1da177e4
LT		 248 .rx_ctrl = DEF_RX,
249 .tx_ctrl = DEF_TX,
250 .iseteop = 2,
77accbf5
JN		 251 .dma_owner = dma_ser0,
252 .io_if = if_serial_0,
1da177e4
LT		 253#ifdef CONFIG_ETRAX_SERIAL_PORT0
254 .enabled = 1,
255#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
256 .dma_out_enabled = 1,
77accbf5
JN		 257 .dma_out_nbr = SER0_TX_DMA_NBR,
258 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
9cfb5c05 259 .dma_out_irq_flags = 0,
77accbf5 260 .dma_out_irq_description = "serial 0 dma tr",
1da177e4
LT		 261#else
262 .dma_out_enabled = 0,
77accbf5
JN		 263 .dma_out_nbr = UINT_MAX,
264 .dma_out_irq_nbr = 0,
265 .dma_out_irq_flags = 0,
266 .dma_out_irq_description = NULL,
1da177e4
LT		 267#endif
268#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
269 .dma_in_enabled = 1,
77accbf5
JN		 270 .dma_in_nbr = SER0_RX_DMA_NBR,
271 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
9cfb5c05 272 .dma_in_irq_flags = 0,
77accbf5 273 .dma_in_irq_description = "serial 0 dma rec",
1da177e4 274#else
77accbf5
JN		 275 .dma_in_enabled = 0,
276 .dma_in_nbr = UINT_MAX,
277 .dma_in_irq_nbr = 0,
278 .dma_in_irq_flags = 0,
279 .dma_in_irq_description = NULL,
1da177e4
LT		 280#endif
281#else
282 .enabled = 0,
77accbf5 283 .io_if_description = NULL,
1da177e4
LT		 284 .dma_out_enabled = 0,
285 .dma_in_enabled = 0
286#endif
287
288}, /* ttyS0 */
289#ifndef CONFIG_SVINTO_SIM
290 { .baud = DEF_BAUD,
d7283353 291 .ioport = (unsigned char *)R_SERIAL1_CTRL,
1da177e4
LT		 292 .irq = 1U << 16, /* uses DMA 8 and 9 */
293 .oclrintradr = R_DMA_CH8_CLR_INTR,
294 .ofirstadr = R_DMA_CH8_FIRST,
295 .ocmdadr = R_DMA_CH8_CMD,
296 .ostatusadr = R_DMA_CH8_STATUS,
297 .iclrintradr = R_DMA_CH9_CLR_INTR,
298 .ifirstadr = R_DMA_CH9_FIRST,
299 .icmdadr = R_DMA_CH9_CMD,
300 .idescradr = R_DMA_CH9_DESCR,
1da177e4
LT		 301 .rx_ctrl = DEF_RX,
302 .tx_ctrl = DEF_TX,
303 .iseteop = 3,
77accbf5
JN		 304 .dma_owner = dma_ser1,
305 .io_if = if_serial_1,
1da177e4
LT		 306#ifdef CONFIG_ETRAX_SERIAL_PORT1
307 .enabled = 1,
77accbf5 308 .io_if_description = "ser1",
1da177e4
LT		 309#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
310 .dma_out_enabled = 1,
77accbf5
JN		 311 .dma_out_nbr = SER1_TX_DMA_NBR,
312 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
9cfb5c05 313 .dma_out_irq_flags = 0,
77accbf5 314 .dma_out_irq_description = "serial 1 dma tr",
1da177e4
LT		 315#else
316 .dma_out_enabled = 0,
77accbf5
JN		 317 .dma_out_nbr = UINT_MAX,
318 .dma_out_irq_nbr = 0,
319 .dma_out_irq_flags = 0,
320 .dma_out_irq_description = NULL,
1da177e4
LT		 321#endif
322#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
323 .dma_in_enabled = 1,
77accbf5
JN		 324 .dma_in_nbr = SER1_RX_DMA_NBR,
325 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
9cfb5c05 326 .dma_in_irq_flags = 0,
77accbf5 327 .dma_in_irq_description = "serial 1 dma rec",
1da177e4 328#else
77accbf5
JN		 329 .dma_in_enabled = 0,
330 .dma_in_enabled = 0,
331 .dma_in_nbr = UINT_MAX,
332 .dma_in_irq_nbr = 0,
333 .dma_in_irq_flags = 0,
334 .dma_in_irq_description = NULL,
1da177e4
LT		 335#endif
336#else
337 .enabled = 0,
77accbf5
JN		 338 .io_if_description = NULL,
339 .dma_in_irq_nbr = 0,
1da177e4
LT		 340 .dma_out_enabled = 0,
341 .dma_in_enabled = 0
342#endif
343}, /* ttyS1 */
344
345 { .baud = DEF_BAUD,
d7283353 346 .ioport = (unsigned char *)R_SERIAL2_CTRL,
1da177e4
LT		 347 .irq = 1U << 4, /* uses DMA 2 and 3 */
348 .oclrintradr = R_DMA_CH2_CLR_INTR,
349 .ofirstadr = R_DMA_CH2_FIRST,
350 .ocmdadr = R_DMA_CH2_CMD,
351 .ostatusadr = R_DMA_CH2_STATUS,
352 .iclrintradr = R_DMA_CH3_CLR_INTR,
353 .ifirstadr = R_DMA_CH3_FIRST,
354 .icmdadr = R_DMA_CH3_CMD,
355 .idescradr = R_DMA_CH3_DESCR,
1da177e4
LT		 356 .rx_ctrl = DEF_RX,
357 .tx_ctrl = DEF_TX,
358 .iseteop = 0,
77accbf5
JN		 359 .dma_owner = dma_ser2,
360 .io_if = if_serial_2,
1da177e4
LT		 361#ifdef CONFIG_ETRAX_SERIAL_PORT2
362 .enabled = 1,
77accbf5 363 .io_if_description = "ser2",
1da177e4
LT		 364#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
365 .dma_out_enabled = 1,
77accbf5
JN		 366 .dma_out_nbr = SER2_TX_DMA_NBR,
367 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
9cfb5c05 368 .dma_out_irq_flags = 0,
77accbf5 369 .dma_out_irq_description = "serial 2 dma tr",
1da177e4
LT		 370#else
371 .dma_out_enabled = 0,
77accbf5
JN		 372 .dma_out_nbr = UINT_MAX,
373 .dma_out_irq_nbr = 0,
374 .dma_out_irq_flags = 0,
375 .dma_out_irq_description = NULL,
1da177e4
LT		 376#endif
377#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
378 .dma_in_enabled = 1,
77accbf5
JN		 379 .dma_in_nbr = SER2_RX_DMA_NBR,
380 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
9cfb5c05 381 .dma_in_irq_flags = 0,
77accbf5 382 .dma_in_irq_description = "serial 2 dma rec",
1da177e4 383#else
77accbf5
JN		 384 .dma_in_enabled = 0,
385 .dma_in_nbr = UINT_MAX,
386 .dma_in_irq_nbr = 0,
387 .dma_in_irq_flags = 0,
388 .dma_in_irq_description = NULL,
1da177e4
LT		 389#endif
390#else
391 .enabled = 0,
77accbf5 392 .io_if_description = NULL,
1da177e4
LT		 393 .dma_out_enabled = 0,
394 .dma_in_enabled = 0
395#endif
396 }, /* ttyS2 */
397
398 { .baud = DEF_BAUD,
d7283353 399 .ioport = (unsigned char *)R_SERIAL3_CTRL,
1da177e4
LT		 400 .irq = 1U << 8, /* uses DMA 4 and 5 */
401 .oclrintradr = R_DMA_CH4_CLR_INTR,
402 .ofirstadr = R_DMA_CH4_FIRST,
403 .ocmdadr = R_DMA_CH4_CMD,
404 .ostatusadr = R_DMA_CH4_STATUS,
405 .iclrintradr = R_DMA_CH5_CLR_INTR,
406 .ifirstadr = R_DMA_CH5_FIRST,
407 .icmdadr = R_DMA_CH5_CMD,
408 .idescradr = R_DMA_CH5_DESCR,
1da177e4
LT		 409 .rx_ctrl = DEF_RX,
410 .tx_ctrl = DEF_TX,
411 .iseteop = 1,
77accbf5
JN		 412 .dma_owner = dma_ser3,
413 .io_if = if_serial_3,
1da177e4
LT		 414#ifdef CONFIG_ETRAX_SERIAL_PORT3
415 .enabled = 1,
77accbf5 416 .io_if_description = "ser3",
1da177e4
LT		 417#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
418 .dma_out_enabled = 1,
77accbf5
JN		 419 .dma_out_nbr = SER3_TX_DMA_NBR,
420 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
9cfb5c05 421 .dma_out_irq_flags = 0,
77accbf5 422 .dma_out_irq_description = "serial 3 dma tr",
1da177e4
LT		 423#else
424 .dma_out_enabled = 0,
77accbf5
JN		 425 .dma_out_nbr = UINT_MAX,
426 .dma_out_irq_nbr = 0,
427 .dma_out_irq_flags = 0,
428 .dma_out_irq_description = NULL,
1da177e4
LT		 429#endif
430#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
431 .dma_in_enabled = 1,
77accbf5
JN		 432 .dma_in_nbr = SER3_RX_DMA_NBR,
433 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
9cfb5c05 434 .dma_in_irq_flags = 0,
77accbf5 435 .dma_in_irq_description = "serial 3 dma rec",
1da177e4 436#else
77accbf5
JN		 437 .dma_in_enabled = 0,
438 .dma_in_nbr = UINT_MAX,
439 .dma_in_irq_nbr = 0,
440 .dma_in_irq_flags = 0,
441 .dma_in_irq_description = NULL
1da177e4
LT		 442#endif
443#else
444 .enabled = 0,
77accbf5 445 .io_if_description = NULL,
1da177e4
LT		 446 .dma_out_enabled = 0,
447 .dma_in_enabled = 0
448#endif
449 } /* ttyS3 */
450#endif
451};
452
453
454#define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
455
1da177e4
LT		 456#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
457static struct fast_timer fast_timers[NR_PORTS];
458#endif
459
460#ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
461#define PROCSTAT(x) x
462struct ser_statistics_type {
463 int overrun_cnt;
464 int early_errors_cnt;
465 int ser_ints_ok_cnt;
466 int errors_cnt;
467 unsigned long int processing_flip;
468 unsigned long processing_flip_still_room;
469 unsigned long int timeout_flush_cnt;
470 int rx_dma_ints;
471 int tx_dma_ints;
472 int rx_tot;
473 int tx_tot;
474};
475
476static struct ser_statistics_type ser_stat[NR_PORTS];
477
478#else
479
480#define PROCSTAT(x)
481
482#endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
483
484/* RS-485 */
485#if defined(CONFIG_ETRAX_RS485)
486#ifdef CONFIG_ETRAX_FAST_TIMER
487static struct fast_timer fast_timers_rs485[NR_PORTS];
488#endif
489#if defined(CONFIG_ETRAX_RS485_ON_PA)
490static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
491#endif
492#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
493static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
494#endif
495#endif
496
497/* Info and macros needed for each ports extra control/status signals. */
498#define E100_STRUCT_PORT(line, pinname) \
499 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
500 (R_PORT_PA_DATA): ( \
501 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
502 (R_PORT_PB_DATA):&dummy_ser[line]))
503
504#define E100_STRUCT_SHADOW(line, pinname) \
505 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
506 (&port_pa_data_shadow): ( \
507 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
508 (&port_pb_data_shadow):&dummy_ser[line]))
509#define E100_STRUCT_MASK(line, pinname) \
510 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
511 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
512 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
513 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
514
515#define DUMMY_DTR_MASK 1
516#define DUMMY_RI_MASK 2
517#define DUMMY_DSR_MASK 4
518#define DUMMY_CD_MASK 8
519static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
520
521/* If not all status pins are used or disabled, use mixed mode */
522#ifdef CONFIG_ETRAX_SERIAL_PORT0
523
524#define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
525
526#if SER0_PA_BITSUM != -4
527# if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
528# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
529# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
530# endif
531# endif
532# if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
533# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
534# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
535# endif
536# endif
537# if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
538# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
539# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
540# endif
541# endif
542# if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
543# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
544# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
545# endif
546# endif
547#endif
548
549#define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
550
551#if SER0_PB_BITSUM != -4
552# if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
553# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
554# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
555# endif
556# endif
557# if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
558# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
559# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
560# endif
561# endif
562# if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
563# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
564# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
565# endif
566# endif
567# if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
568# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
569# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
570# endif
571# endif
572#endif
573
574#endif /* PORT0 */
575
576
577#ifdef CONFIG_ETRAX_SERIAL_PORT1
578
579#define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
580
581#if SER1_PA_BITSUM != -4
582# if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
583# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
584# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
585# endif
586# endif
587# if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
588# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
589# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
590# endif
591# endif
592# if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
593# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
594# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
595# endif
596# endif
597# if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
598# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
599# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
600# endif
601# endif
602#endif
603
604#define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
605
606#if SER1_PB_BITSUM != -4
607# if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
608# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
609# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
610# endif
611# endif
612# if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
613# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
614# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
615# endif
616# endif
617# if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
618# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
619# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
620# endif
621# endif
622# if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
623# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
624# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
625# endif
626# endif
627#endif
628
629#endif /* PORT1 */
630
631#ifdef CONFIG_ETRAX_SERIAL_PORT2
632
633#define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
634
635#if SER2_PA_BITSUM != -4
636# if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
637# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
638# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
639# endif
640# endif
641# if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
642# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
643# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
644# endif
645# endif
646# if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
647# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
648# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
649# endif
650# endif
651# if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
652# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
653# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
654# endif
655# endif
656#endif
657
658#define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
659
660#if SER2_PB_BITSUM != -4
661# if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
662# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
663# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
664# endif
665# endif
666# if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
667# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
668# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
669# endif
670# endif
671# if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
672# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
673# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
674# endif
675# endif
676# if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
677# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
678# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
679# endif
680# endif
681#endif
682
683#endif /* PORT2 */
684
685#ifdef CONFIG_ETRAX_SERIAL_PORT3
686
687#define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
688
689#if SER3_PA_BITSUM != -4
690# if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
691# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
692# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
693# endif
694# endif
695# if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
696# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
697# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
698# endif
699# endif
700# if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
701# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
702# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
703# endif
704# endif
705# if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
706# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
707# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
708# endif
709# endif
710#endif
711
712#define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
713
714#if SER3_PB_BITSUM != -4
715# if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
716# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
717# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
718# endif
719# endif
720# if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
721# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
722# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
723# endif
724# endif
725# if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
726# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
727# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
728# endif
729# endif
730# if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
731# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
732# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
733# endif
734# endif
735#endif
736
737#endif /* PORT3 */
738
739
740#if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
741 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
742 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
743 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
744#define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
745#endif
746
747#ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
748/* The pins can be mixed on PA and PB */
749#define CONTROL_PINS_PORT_NOT_USED(line) \
750 &dummy_ser[line], &dummy_ser[line], \
751 &dummy_ser[line], &dummy_ser[line], \
752 &dummy_ser[line], &dummy_ser[line], \
753 &dummy_ser[line], &dummy_ser[line], \
754 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
755
756
757struct control_pins
758{
759 volatile unsigned char *dtr_port;
760 unsigned char *dtr_shadow;
761 volatile unsigned char *ri_port;
762 unsigned char *ri_shadow;
763 volatile unsigned char *dsr_port;
764 unsigned char *dsr_shadow;
765 volatile unsigned char *cd_port;
766 unsigned char *cd_shadow;
767
768 unsigned char dtr_mask;
769 unsigned char ri_mask;
770 unsigned char dsr_mask;
771 unsigned char cd_mask;
772};
773
774static const struct control_pins e100_modem_pins[NR_PORTS] =
775{
776 /* Ser 0 */
777 {
778#ifdef CONFIG_ETRAX_SERIAL_PORT0
779 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
780 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
781 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
782 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
783 E100_STRUCT_MASK(0,DTR),
784 E100_STRUCT_MASK(0,RI),
785 E100_STRUCT_MASK(0,DSR),
786 E100_STRUCT_MASK(0,CD)
787#else
788 CONTROL_PINS_PORT_NOT_USED(0)
789#endif
790 },
791
792 /* Ser 1 */
793 {
794#ifdef CONFIG_ETRAX_SERIAL_PORT1
795 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
796 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
797 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
798 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
799 E100_STRUCT_MASK(1,DTR),
800 E100_STRUCT_MASK(1,RI),
801 E100_STRUCT_MASK(1,DSR),
802 E100_STRUCT_MASK(1,CD)
803#else
804 CONTROL_PINS_PORT_NOT_USED(1)
805#endif
806 },
807
808 /* Ser 2 */
809 {
810#ifdef CONFIG_ETRAX_SERIAL_PORT2
811 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
812 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
813 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
814 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
815 E100_STRUCT_MASK(2,DTR),
816 E100_STRUCT_MASK(2,RI),
817 E100_STRUCT_MASK(2,DSR),
818 E100_STRUCT_MASK(2,CD)
819#else
820 CONTROL_PINS_PORT_NOT_USED(2)
821#endif
822 },
823
824 /* Ser 3 */
825 {
826#ifdef CONFIG_ETRAX_SERIAL_PORT3
827 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
828 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
829 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
830 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
831 E100_STRUCT_MASK(3,DTR),
832 E100_STRUCT_MASK(3,RI),
833 E100_STRUCT_MASK(3,DSR),
834 E100_STRUCT_MASK(3,CD)
835#else
836 CONTROL_PINS_PORT_NOT_USED(3)
837#endif
838 }
839};
840#else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
841
842/* All pins are on either PA or PB for each serial port */
843#define CONTROL_PINS_PORT_NOT_USED(line) \
844 &dummy_ser[line], &dummy_ser[line], \
845 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
846
847
848struct control_pins
849{
850 volatile unsigned char *port;
851 unsigned char *shadow;
852
853 unsigned char dtr_mask;
854 unsigned char ri_mask;
855 unsigned char dsr_mask;
856 unsigned char cd_mask;
857};
858
859#define dtr_port port
860#define dtr_shadow shadow
861#define ri_port port
862#define ri_shadow shadow
863#define dsr_port port
864#define dsr_shadow shadow
865#define cd_port port
866#define cd_shadow shadow
867
868static const struct control_pins e100_modem_pins[NR_PORTS] =
869{
870 /* Ser 0 */
871 {
872#ifdef CONFIG_ETRAX_SERIAL_PORT0
873 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
874 E100_STRUCT_MASK(0,DTR),
875 E100_STRUCT_MASK(0,RI),
876 E100_STRUCT_MASK(0,DSR),
877 E100_STRUCT_MASK(0,CD)
878#else
879 CONTROL_PINS_PORT_NOT_USED(0)
880#endif
881 },
882
883 /* Ser 1 */
884 {
885#ifdef CONFIG_ETRAX_SERIAL_PORT1
886 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
887 E100_STRUCT_MASK(1,DTR),
888 E100_STRUCT_MASK(1,RI),
889 E100_STRUCT_MASK(1,DSR),
890 E100_STRUCT_MASK(1,CD)
891#else
892 CONTROL_PINS_PORT_NOT_USED(1)
893#endif
894 },
895
896 /* Ser 2 */
897 {
898#ifdef CONFIG_ETRAX_SERIAL_PORT2
899 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
900 E100_STRUCT_MASK(2,DTR),
901 E100_STRUCT_MASK(2,RI),
902 E100_STRUCT_MASK(2,DSR),
903 E100_STRUCT_MASK(2,CD)
904#else
905 CONTROL_PINS_PORT_NOT_USED(2)
906#endif
907 },
908
909 /* Ser 3 */
910 {
911#ifdef CONFIG_ETRAX_SERIAL_PORT3
912 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
913 E100_STRUCT_MASK(3,DTR),
914 E100_STRUCT_MASK(3,RI),
915 E100_STRUCT_MASK(3,DSR),
916 E100_STRUCT_MASK(3,CD)
917#else
918 CONTROL_PINS_PORT_NOT_USED(3)
919#endif
920 }
921};
922#endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
923
924#define E100_RTS_MASK 0x20
925#define E100_CTS_MASK 0x40
926
927/* All serial port signals are active low:
928 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
929 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
930 *
931 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
932 */
933
934/* Output */
935#define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
936/* Input */
d7283353 937#define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
1da177e4
LT		 938
939/* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
940/* Is an output */
941#define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
942
943/* Normally inputs */
944#define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
945#define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
946
947/* Input */
948#define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
949
1da177e4
LT		 950/* Calculate the chartime depending on baudrate, numbor of bits etc. */
951static void update_char_time(struct e100_serial * info)
952{
adc8d746 953 tcflag_t cflags = info->port.tty->termios.c_cflag;
1da177e4
LT		 954 int bits;
955
956 /* calc. number of bits / data byte */
957 /* databits + startbit and 1 stopbit */
958 if ((cflags & CSIZE) == CS7)
959 bits = 9;
960 else
961 bits = 10;
962
963 if (cflags & CSTOPB) /* 2 stopbits ? */
964 bits++;
965
966 if (cflags & PARENB) /* parity bit ? */
967 bits++;
968
969 /* calc timeout */
970 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
971 info->flush_time_usec = 4*info->char_time_usec;
972 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
973 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
974
975}
976
977/*
978 * This function maps from the Bxxxx defines in asm/termbits.h into real
979 * baud rates.
980 */
981
982static int
983cflag_to_baud(unsigned int cflag)
984{
985 static int baud_table[] = {
986 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
987 4800, 9600, 19200, 38400 };
988
989 static int ext_baud_table[] = {
990 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
991 0, 0, 0, 0, 0, 0, 0, 0 };
992
993 if (cflag & CBAUDEX)
994 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
995 else
996 return baud_table[cflag & CBAUD];
997}
998
999/* and this maps to an etrax100 hardware baud constant */
1000
1001static unsigned char
1002cflag_to_etrax_baud(unsigned int cflag)
1003{
1004 char retval;
1005
1006 static char baud_table[] = {
1007 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
1008
1009 static char ext_baud_table[] = {
1010 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
1011
1012 if (cflag & CBAUDEX)
1013 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1014 else
1015 retval = baud_table[cflag & CBAUD];
1016
1017 if (retval < 0) {
1018 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
1019 retval = 5; /* choose default 9600 instead */
1020 }
1021
1022 return retval | (retval << 4); /* choose same for both TX and RX */
1023}
1024
1025
1026/* Various static support functions */
1027
1028/* Functions to set or clear DTR/RTS on the requested line */
1029/* It is complicated by the fact that RTS is a serial port register, while
1030 * DTR might not be implemented in the HW at all, and if it is, it can be on
1031 * any general port.
1032 */
1033
1034
1035static inline void
1036e100_dtr(struct e100_serial *info, int set)
1037{
1038#ifndef CONFIG_SVINTO_SIM
1039 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1040
1041#ifdef SERIAL_DEBUG_IO
1042 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1043 printk("ser%i shadow before 0x%02X get: %i\n",
1044 info->line, *e100_modem_pins[info->line].dtr_shadow,
1045 E100_DTR_GET(info));
1046#endif
1047 /* DTR is active low */
1048 {
1049 unsigned long flags;
1050
77accbf5 1051 local_irq_save(flags);
1da177e4
LT		 1052 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1053 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1054 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
77accbf5 1055 local_irq_restore(flags);
1da177e4
LT		 1056 }
1057
1058#ifdef SERIAL_DEBUG_IO
1059 printk("ser%i shadow after 0x%02X get: %i\n",
1060 info->line, *e100_modem_pins[info->line].dtr_shadow,
1061 E100_DTR_GET(info));
1062#endif
1063#endif
1064}
1065
1066/* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1067 * 0=0V , 1=3.3V
1068 */
1069static inline void
1070e100_rts(struct e100_serial *info, int set)
1071{
1072#ifndef CONFIG_SVINTO_SIM
1073 unsigned long flags;
77accbf5 1074 local_irq_save(flags);
1da177e4
LT		 1075 info->rx_ctrl &= ~E100_RTS_MASK;
1076 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
d7283353 1077 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
77accbf5 1078 local_irq_restore(flags);
1da177e4
LT		 1079#ifdef SERIAL_DEBUG_IO
1080 printk("ser%i rts %i\n", info->line, set);
1081#endif
1082#endif
1083}
1084
1085
1086/* If this behaves as a modem, RI and CD is an output */
1087static inline void
1088e100_ri_out(struct e100_serial *info, int set)
1089{
1090#ifndef CONFIG_SVINTO_SIM
1091 /* RI is active low */
1092 {
1093 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1094 unsigned long flags;
1095
77accbf5 1096 local_irq_save(flags);
1da177e4
LT		 1097 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1098 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1099 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
77accbf5 1100 local_irq_restore(flags);
1da177e4
LT		 1101 }
1102#endif
1103}
1104static inline void
1105e100_cd_out(struct e100_serial *info, int set)
1106{
1107#ifndef CONFIG_SVINTO_SIM
1108 /* CD is active low */
1109 {
1110 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1111 unsigned long flags;
1112
77accbf5 1113 local_irq_save(flags);
1da177e4
LT		 1114 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1115 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1116 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
77accbf5 1117 local_irq_restore(flags);
1da177e4
LT		 1118 }
1119#endif
1120}
1121
1122static inline void
1123e100_disable_rx(struct e100_serial *info)
1124{
1125#ifndef CONFIG_SVINTO_SIM
1126 /* disable the receiver */
d7283353 1127 info->ioport[REG_REC_CTRL] =
1da177e4
LT		 1128 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1129#endif
1130}
1131
1132static inline void
1133e100_enable_rx(struct e100_serial *info)
1134{
1135#ifndef CONFIG_SVINTO_SIM
1136 /* enable the receiver */
d7283353 1137 info->ioport[REG_REC_CTRL] =
1da177e4
LT		 1138 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1139#endif
1140}
1141
1142/* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1143
1144static inline void
1145e100_disable_rxdma_irq(struct e100_serial *info)
1146{
1147#ifdef SERIAL_DEBUG_INTR
1148 printk("rxdma_irq(%d): 0\n",info->line);
1149#endif
1150 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1151 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1152}
1153
1154static inline void
1155e100_enable_rxdma_irq(struct e100_serial *info)
1156{
1157#ifdef SERIAL_DEBUG_INTR
1158 printk("rxdma_irq(%d): 1\n",info->line);
1159#endif
1160 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1161 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1162}
1163
1164/* the tx DMA uses only dma_descr interrupt */
1165
41c28ff1 1166static void e100_disable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1167{
1168#ifdef SERIAL_DEBUG_INTR
1169 printk("txdma_irq(%d): 0\n",info->line);
1170#endif
1171 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1172 *R_IRQ_MASK2_CLR = info->irq;
1173}
1174
41c28ff1 1175static void e100_enable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1176{
1177#ifdef SERIAL_DEBUG_INTR
1178 printk("txdma_irq(%d): 1\n",info->line);
1179#endif
1180 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1181 *R_IRQ_MASK2_SET = info->irq;
1182}
1183
41c28ff1 1184static void e100_disable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1185{
1186 unsigned long flags;
1187
1188 /* Disable output DMA channel for the serial port in question
025dfdaf 1189 * ( set to something other than serialX)
1da177e4 1190 */
77accbf5 1191 local_irq_save(flags);
1da177e4
LT		 1192 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1193 if (info->line == 0) {
1194 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1195 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1196 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1197 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1198 }
1199 } else if (info->line == 1) {
1200 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1201 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1202 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1203 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1204 }
1205 } else if (info->line == 2) {
1206 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1207 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1208 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1209 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1210 }
1211 } else if (info->line == 3) {
1212 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1213 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1214 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1215 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1216 }
1217 }
1218 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1219 local_irq_restore(flags);
1da177e4
LT		 1220}
1221
1222
41c28ff1 1223static void e100_enable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1224{
1225 unsigned long flags;
1226
77accbf5 1227 local_irq_save(flags);
1da177e4
LT		 1228 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1229 /* Enable output DMA channel for the serial port in question */
1230 if (info->line == 0) {
1231 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1232 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1233 } else if (info->line == 1) {
1234 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1235 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1236 } else if (info->line == 2) {
1237 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1238 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1239 } else if (info->line == 3) {
1240 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1241 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1242 }
1243 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1244 local_irq_restore(flags);
1da177e4
LT		 1245}
1246
41c28ff1 1247static void e100_disable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1248{
1249 unsigned long flags;
1250
1251 /* Disable input DMA channel for the serial port in question
025dfdaf 1252 * ( set to something other than serialX)
1da177e4 1253 */
77accbf5 1254 local_irq_save(flags);
1da177e4
LT		 1255 if (info->line == 0) {
1256 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1257 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1258 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1259 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1260 }
1261 } else if (info->line == 1) {
1262 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1263 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1264 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1265 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1266 }
1267 } else if (info->line == 2) {
1268 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1269 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1270 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1271 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1272 }
1273 } else if (info->line == 3) {
1274 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1275 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1276 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1277 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1278 }
1279 }
1280 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1281 local_irq_restore(flags);
1da177e4
LT		 1282}
1283
1284
41c28ff1 1285static void e100_enable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1286{
1287 unsigned long flags;
1288
77accbf5 1289 local_irq_save(flags);
1da177e4
LT		 1290 /* Enable input DMA channel for the serial port in question */
1291 if (info->line == 0) {
1292 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1293 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1294 } else if (info->line == 1) {
1295 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1296 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1297 } else if (info->line == 2) {
1298 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1299 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1300 } else if (info->line == 3) {
1301 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1302 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1303 }
1304 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1305 local_irq_restore(flags);
1da177e4
LT		 1306}
1307
1308#ifdef SERIAL_HANDLE_EARLY_ERRORS
1309/* in order to detect and fix errors on the first byte
1310 we have to use the serial interrupts as well. */
1311
1312static inline void
1313e100_disable_serial_data_irq(struct e100_serial *info)
1314{
1315#ifdef SERIAL_DEBUG_INTR
1316 printk("ser_irq(%d): 0\n",info->line);
1317#endif
1318 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1319 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1320}
1321
1322static inline void
1323e100_enable_serial_data_irq(struct e100_serial *info)
1324{
1325#ifdef SERIAL_DEBUG_INTR
1326 printk("ser_irq(%d): 1\n",info->line);
1327 printk("**** %d = %d\n",
1328 (8+2*info->line),
1329 (1U << (8+2*info->line)));
1330#endif
1331 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1332 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1333}
1334#endif
1335
1336static inline void
1337e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1338{
1339#ifdef SERIAL_DEBUG_INTR
1340 printk("ser_tx_irq(%d): 0\n",info->line);
1341#endif
1342 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1343 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1344}
1345
1346static inline void
1347e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1348{
1349#ifdef SERIAL_DEBUG_INTR
1350 printk("ser_tx_irq(%d): 1\n",info->line);
1351 printk("**** %d = %d\n",
1352 (8+1+2*info->line),
1353 (1U << (8+1+2*info->line)));
1354#endif
1355 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1356 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1357}
1358
1359static inline void e100_enable_rx_irq(struct e100_serial *info)
1360{
1361 if (info->uses_dma_in)
1362 e100_enable_rxdma_irq(info);
1363 else
1364 e100_enable_serial_data_irq(info);
1365}
1366static inline void e100_disable_rx_irq(struct e100_serial *info)
1367{
1368 if (info->uses_dma_in)
1369 e100_disable_rxdma_irq(info);
1370 else
1371 e100_disable_serial_data_irq(info);
1372}
1373
1374#if defined(CONFIG_ETRAX_RS485)
1375/* Enable RS-485 mode on selected port. This is UGLY. */
1376static int
6fd1af4c 1377e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1da177e4
LT		 1378{
1379 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1380
1381#if defined(CONFIG_ETRAX_RS485_ON_PA)
1382 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1383#endif
1384#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
1385 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1386 rs485_port_g_bit, 1);
1387#endif
1388#if defined(CONFIG_ETRAX_RS485_LTC1387)
1389 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1390 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1);
1391 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1392 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
1393#endif
1394
c7213fc4
JN		 1395 info->rs485 = *r;
1396
1397 /* Maximum delay before RTS equal to 1000 */
1398 if (info->rs485.delay_rts_before_send >= 1000)
1da177e4 1399 info->rs485.delay_rts_before_send = 1000;
c7213fc4 1400
1da177e4
LT		 1401/* printk("rts: on send = %i, after = %i, enabled = %i",
1402 info->rs485.rts_on_send,
1403 info->rs485.rts_after_sent,
1404 info->rs485.enabled
1405 );
1406*/
1407 return 0;
1408}
1409
1410static int
77accbf5 1411e100_write_rs485(struct tty_struct *tty,
1da177e4
LT		 1412 const unsigned char *buf, int count)
1413{
1414 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
6fd1af4c 1415 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1da177e4
LT		 1416
1417 /* rs485 is always implicitly enabled if we're using the ioctl()
6fd1af4c 1418 * but it doesn't have to be set in the serial_rs485
1da177e4
LT		 1419 * (to be backward compatible with old apps)
1420 * So we store, set and restore it.
1421 */
6fd1af4c 1422 info->rs485.flags |= SER_RS485_ENABLED;
1da177e4 1423 /* rs_write now deals with RS485 if enabled */
77accbf5 1424 count = rs_write(tty, buf, count);
6fd1af4c
CS		 1425 if (!old_value)
1426 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4
LT		 1427 return count;
1428}
1429
1430#ifdef CONFIG_ETRAX_FAST_TIMER
1431/* Timer function to toggle RTS when using FAST_TIMER */
1432static void rs485_toggle_rts_timer_function(unsigned long data)
1433{
1434 struct e100_serial *info = (struct e100_serial *)data;
1435
1436 fast_timers_rs485[info->line].function = NULL;
6fd1af4c 1437 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1da177e4
LT		 1438#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1439 e100_enable_rx(info);
1440 e100_enable_rx_irq(info);
1441#endif
1442}
1443#endif
1444#endif /* CONFIG_ETRAX_RS485 */
1445
1446/*
1447 * ------------------------------------------------------------
1448 * rs_stop() and rs_start()
1449 *
1450 * This routines are called before setting or resetting tty->stopped.
1451 * They enable or disable transmitter using the XOFF registers, as necessary.
1452 * ------------------------------------------------------------
1453 */
1454
1455static void
1456rs_stop(struct tty_struct *tty)
1457{
1458 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1459 if (info) {
1460 unsigned long flags;
1461 unsigned long xoff;
1462
77accbf5 1463 local_irq_save(flags);
1da177e4
LT		 1464 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1465 CIRC_CNT(info->xmit.head,
1466 info->xmit.tail,SERIAL_XMIT_SIZE)));
1467
a88487c7
TI		 1468 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1469 STOP_CHAR(info->port.tty));
1da177e4 1470 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
adc8d746 1471 if (tty->termios.c_iflag & IXON ) {
1da177e4
LT		 1472 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1473 }
1474
d7283353 1475 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
77accbf5 1476 local_irq_restore(flags);
1da177e4
LT		 1477 }
1478}
1479
1480static void
1481rs_start(struct tty_struct *tty)
1482{
1483 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1484 if (info) {
1485 unsigned long flags;
1486 unsigned long xoff;
1487
77accbf5 1488 local_irq_save(flags);
1da177e4
LT		 1489 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1490 CIRC_CNT(info->xmit.head,
1491 info->xmit.tail,SERIAL_XMIT_SIZE)));
1492 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1493 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
adc8d746 1494 if (tty->termios.c_iflag & IXON ) {
1da177e4
LT		 1495 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1496 }
1497
d7283353 1498 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1da177e4
LT		 1499 if (!info->uses_dma_out &&
1500 info->xmit.head != info->xmit.tail && info->xmit.buf)
1501 e100_enable_serial_tx_ready_irq(info);
1502
77accbf5 1503 local_irq_restore(flags);
1da177e4
LT		 1504 }
1505}
1506
1507/*
1508 * ----------------------------------------------------------------------
1509 *
1510 * Here starts the interrupt handling routines. All of the following
1511 * subroutines are declared as inline and are folded into
1512 * rs_interrupt(). They were separated out for readability's sake.
1513 *
1514 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1515 * runs with interrupts turned off. People who may want to modify
1516 * rs_interrupt() should try to keep the interrupt handler as fast as
1517 * possible. After you are done making modifications, it is not a bad
1518 * idea to do:
1519 *
1520 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1521 *
1522 * and look at the resulting assemble code in serial.s.
1523 *
1524 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1525 * -----------------------------------------------------------------------
1526 */
1527
1528/*
1529 * This routine is used by the interrupt handler to schedule
1530 * processing in the software interrupt portion of the driver.
1531 */
41c28ff1 1532static void rs_sched_event(struct e100_serial *info, int event)
1da177e4
LT		 1533{
1534 if (info->event & (1 << event))
1535 return;
1536 info->event |= 1 << event;
1537 schedule_work(&info->work);
1538}
1539
1540/* The output DMA channel is free - use it to send as many chars as possible
1541 * NOTES:
1542 * We don't pay attention to info->x_char, which means if the TTY wants to
1543 * use XON/XOFF it will set info->x_char but we won't send any X char!
1544 *
1545 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1546 * buffer containing the X char, and skip updating xmit. We'd also have to
1547 * check if the last sent char was the X char when we enter this function
1548 * the next time, to avoid updating xmit with the sent X value.
1549 */
1550
1551static void
1552transmit_chars_dma(struct e100_serial *info)
1553{
1554 unsigned int c, sentl;
1555 struct etrax_dma_descr *descr;
1556
1557#ifdef CONFIG_SVINTO_SIM
1558 /* This will output too little if tail is not 0 always since
1559 * we don't reloop to send the other part. Anyway this SHOULD be a
1560 * no-op - transmit_chars_dma would never really be called during sim
1561 * since rs_write does not write into the xmit buffer then.
1562 */
1563 if (info->xmit.tail)
1564 printk("Error in serial.c:transmit_chars-dma(), tail!=0\n");
1565 if (info->xmit.head != info->xmit.tail) {
1566 SIMCOUT(info->xmit.buf + info->xmit.tail,
1567 CIRC_CNT(info->xmit.head,
1568 info->xmit.tail,
1569 SERIAL_XMIT_SIZE));
1570 info->xmit.head = info->xmit.tail; /* move back head */
1571 info->tr_running = 0;
1572 }
1573 return;
1574#endif
1575 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1576 *info->oclrintradr =
1577 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1578 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1579
1580#ifdef SERIAL_DEBUG_INTR
1581 if (info->line == SERIAL_DEBUG_LINE)
1582 printk("tc\n");
1583#endif
1584 if (!info->tr_running) {
1585 /* weirdo... we shouldn't get here! */
1586 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1587 return;
1588 }
1589
1590 descr = &info->tr_descr;
1591
1592 /* first get the amount of bytes sent during the last DMA transfer,
1593 and update xmit accordingly */
1594
1595 /* if the stop bit was not set, all data has been sent */
1596 if (!(descr->status & d_stop)) {
1597 sentl = descr->sw_len;
1598 } else
1599 /* otherwise we find the amount of data sent here */
1600 sentl = descr->hw_len;
1601
1602 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1603
1604 /* update stats */
1605 info->icount.tx += sentl;
1606
1607 /* update xmit buffer */
1608 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1609
1610 /* if there is only a few chars left in the buf, wake up the blocked
1611 write if any */
1612 if (CIRC_CNT(info->xmit.head,
1613 info->xmit.tail,
1614 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1615 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1616
1617 /* find out the largest amount of consecutive bytes we want to send now */
1618
1619 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1620
1621 /* Don't send all in one DMA transfer - divide it so we wake up
1622 * application before all is sent
1623 */
1624
1625 if (c >= 4*WAKEUP_CHARS)
1626 c = c/2;
1627
1628 if (c <= 0) {
1629 /* our job here is done, don't schedule any new DMA transfer */
1630 info->tr_running = 0;
1631
1632#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
6fd1af4c 1633 if (info->rs485.flags & SER_RS485_ENABLED) {
1da177e4
LT		 1634 /* Set a short timer to toggle RTS */
1635 start_one_shot_timer(&fast_timers_rs485[info->line],
1636 rs485_toggle_rts_timer_function,
1637 (unsigned long)info,
1638 info->char_time_usec*2,
1639 "RS-485");
1640 }
1641#endif /* RS485 */
1642 return;
1643 }
1644
1645 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1646 /* set up the descriptor correctly for output */
1647 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1648 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1649 descr->sw_len = c;
1650 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1651 descr->status = 0;
1652
1653 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1654 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1655
1656 /* DMA is now running (hopefully) */
1657} /* transmit_chars_dma */
1658
1659static void
1660start_transmit(struct e100_serial *info)
1661{
1662#if 0
1663 if (info->line == SERIAL_DEBUG_LINE)
1664 printk("x\n");
1665#endif
1666
1667 info->tr_descr.sw_len = 0;
1668 info->tr_descr.hw_len = 0;
1669 info->tr_descr.status = 0;
1670 info->tr_running = 1;
1671 if (info->uses_dma_out)
1672 transmit_chars_dma(info);
1673 else
1674 e100_enable_serial_tx_ready_irq(info);
1675} /* start_transmit */
1676
1677#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1678static int serial_fast_timer_started = 0;
1679static int serial_fast_timer_expired = 0;
1680static void flush_timeout_function(unsigned long data);
1681#define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1682 unsigned long timer_flags; \
77accbf5 1683 local_irq_save(timer_flags); \
1da177e4
LT		 1684 if (fast_timers[info->line].function == NULL) { \
1685 serial_fast_timer_started++; \
1686 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1687 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1688 start_one_shot_timer(&fast_timers[info->line], \
1689 flush_timeout_function, \
1690 (unsigned long)info, \
1691 (usec), \
1692 string); \
1693 } \
1694 else { \
1695 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1696 } \
77accbf5 1697 local_irq_restore(timer_flags); \
1da177e4
LT		 1698}
1699#define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1700
1701#else
1702#define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1703#define START_FLUSH_FAST_TIMER(info, string)
1704#endif
1705
1706static struct etrax_recv_buffer *
1707alloc_recv_buffer(unsigned int size)
1708{
1709 struct etrax_recv_buffer *buffer;
1710
1711 if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
1712 return NULL;
1713
1714 buffer->next = NULL;
1715 buffer->length = 0;
1716 buffer->error = TTY_NORMAL;
1717
1718 return buffer;
1719}
1720
1721static void
1722append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1723{
1724 unsigned long flags;
1725
77accbf5 1726 local_irq_save(flags);
1da177e4
LT		 1727
1728 if (!info->first_recv_buffer)
1729 info->first_recv_buffer = buffer;
1730 else
1731 info->last_recv_buffer->next = buffer;
1732
1733 info->last_recv_buffer = buffer;
1734
1735 info->recv_cnt += buffer->length;
1736 if (info->recv_cnt > info->max_recv_cnt)
1737 info->max_recv_cnt = info->recv_cnt;
1738
77accbf5 1739 local_irq_restore(flags);
1da177e4
LT		 1740}
1741
1742static int
1743add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1744{
1745 struct etrax_recv_buffer *buffer;
1746 if (info->uses_dma_in) {
1747 if (!(buffer = alloc_recv_buffer(4)))
1748 return 0;
1749
1750 buffer->length = 1;
1751 buffer->error = flag;
1752 buffer->buffer[0] = data;
1753
1754 append_recv_buffer(info, buffer);
1755
1756 info->icount.rx++;
1757 } else {
92a19f9c 1758 tty_insert_flip_char(&info->port, data, flag);
1da177e4
LT		 1759 info->icount.rx++;
1760 }
1761
1762 return 1;
1763}
1764
41c28ff1
AB		 1765static unsigned int handle_descr_data(struct e100_serial *info,
1766 struct etrax_dma_descr *descr,
1767 unsigned int recvl)
1da177e4
LT		 1768{
1769 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1770
1771 if (info->recv_cnt + recvl > 65536) {
3d43b7d5 1772 printk(KERN_WARNING
71cc2c21 1773 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1da177e4
LT		 1774 return 0;
1775 }
1776
1777 buffer->length = recvl;
1778
1779 if (info->errorcode == ERRCODE_SET_BREAK)
1780 buffer->error = TTY_BREAK;
1781 info->errorcode = 0;
1782
1783 append_recv_buffer(info, buffer);
1784
1785 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
71cc2c21 1786 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1da177e4
LT		 1787
1788 descr->buf = virt_to_phys(buffer->buffer);
1789
1790 return recvl;
1791}
1792
41c28ff1 1793static unsigned int handle_all_descr_data(struct e100_serial *info)
1da177e4
LT		 1794{
1795 struct etrax_dma_descr *descr;
1796 unsigned int recvl;
1797 unsigned int ret = 0;
1798
1799 while (1)
1800 {
1801 descr = &info->rec_descr[info->cur_rec_descr];
1802
1803 if (descr == phys_to_virt(*info->idescradr))
1804 break;
1805
1806 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1807 info->cur_rec_descr = 0;
1808
1809 /* find out how many bytes were read */
1810
1811 /* if the eop bit was not set, all data has been received */
1812 if (!(descr->status & d_eop)) {
1813 recvl = descr->sw_len;
1814 } else {
1815 /* otherwise we find the amount of data received here */
1816 recvl = descr->hw_len;
1817 }
1818
1819 /* Reset the status information */
1820 descr->status = 0;
1821
1822 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
a88487c7 1823 if (info->port.tty->stopped) {
1da177e4
LT		 1824 unsigned char *buf = phys_to_virt(descr->buf);
1825 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1826 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1827 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1828 }
1829 );
1830
1831 /* update stats */
1832 info->icount.rx += recvl;
1833
1834 ret += handle_descr_data(info, descr, recvl);
1835 }
1836
1837 return ret;
1838}
1839
41c28ff1 1840static void receive_chars_dma(struct e100_serial *info)
1da177e4
LT		 1841{
1842 struct tty_struct *tty;
1843 unsigned char rstat;
1844
1845#ifdef CONFIG_SVINTO_SIM
1846 /* No receive in the simulator. Will probably be when the rest of
1847 * the serial interface works, and this piece will just be removed.
1848 */
1849 return;
1850#endif
1851
1852 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1853 *info->iclrintradr =
1854 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1855 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1856
a88487c7 1857 tty = info->port.tty;
1da177e4
LT		 1858 if (!tty) /* Something wrong... */
1859 return;
1860
1861#ifdef SERIAL_HANDLE_EARLY_ERRORS
1862 if (info->uses_dma_in)
1863 e100_enable_serial_data_irq(info);
1864#endif
1865
1866 if (info->errorcode == ERRCODE_INSERT_BREAK)
1867 add_char_and_flag(info, '\0', TTY_BREAK);
1868
1869 handle_all_descr_data(info);
1870
1871 /* Read the status register to detect errors */
d7283353 1872 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 1873 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1874 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1875 }
1876
1877 if (rstat & SER_ERROR_MASK) {
1878 /* If we got an error, we must reset it by reading the
1879 * data_in field
1880 */
d7283353 1881 unsigned char data = info->ioport[REG_DATA];
1da177e4
LT		 1882
1883 PROCSTAT(ser_stat[info->line].errors_cnt++);
1884 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1885 ((rstat & SER_ERROR_MASK) << 8) | data);
1886
1887 if (rstat & SER_PAR_ERR_MASK)
1888 add_char_and_flag(info, data, TTY_PARITY);
1889 else if (rstat & SER_OVERRUN_MASK)
1890 add_char_and_flag(info, data, TTY_OVERRUN);
1891 else if (rstat & SER_FRAMING_ERR_MASK)
1892 add_char_and_flag(info, data, TTY_FRAME);
1893 }
1894
1895 START_FLUSH_FAST_TIMER(info, "receive_chars");
1896
1897 /* Restart the receiving DMA */
1898 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1899}
1900
41c28ff1 1901static int start_recv_dma(struct e100_serial *info)
1da177e4
LT		 1902{
1903 struct etrax_dma_descr *descr = info->rec_descr;
1904 struct etrax_recv_buffer *buffer;
1905 int i;
1906
1907 /* Set up the receiving descriptors */
1908 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1909 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
71cc2c21 1910 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1da177e4
LT		 1911
1912 descr[i].ctrl = d_int;
1913 descr[i].buf = virt_to_phys(buffer->buffer);
1914 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1915 descr[i].hw_len = 0;
1916 descr[i].status = 0;
1917 descr[i].next = virt_to_phys(&descr[i+1]);
1918 }
1919
1920 /* Link the last descriptor to the first */
1921 descr[i-1].next = virt_to_phys(&descr[0]);
1922
1923 /* Start with the first descriptor in the list */
1924 info->cur_rec_descr = 0;
1925
1926 /* Start the DMA */
1927 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1928 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1929
1930 /* Input DMA should be running now */
1931 return 1;
1932}
1933
1934static void
1935start_receive(struct e100_serial *info)
1936{
1937#ifdef CONFIG_SVINTO_SIM
1938 /* No receive in the simulator. Will probably be when the rest of
1939 * the serial interface works, and this piece will just be removed.
1940 */
1941 return;
1942#endif
1da177e4
LT		 1943 if (info->uses_dma_in) {
1944 /* reset the input dma channel to be sure it works */
1945
1946 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1947 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1948 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1949
1950 start_recv_dma(info);
1951 }
1952}
1953
1954
1da177e4
LT		 1955/* the bits in the MASK2 register are laid out like this:
1956 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1957 where I is the input channel and O is the output channel for the port.
1958 info->irq is the bit number for the DMAO_DESCR so to check the others we
1959 shift info->irq to the left.
1960*/
1961
1962/* dma output channel interrupt handler
1963 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1964 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1965*/
1966
1967static irqreturn_t
7d12e780 1968tr_interrupt(int irq, void *dev_id)
1da177e4
LT		 1969{
1970 struct e100_serial *info;
1971 unsigned long ireg;
1972 int i;
1973 int handled = 0;
1974
1975#ifdef CONFIG_SVINTO_SIM
1976 /* No receive in the simulator. Will probably be when the rest of
1977 * the serial interface works, and this piece will just be removed.
1978 */
1979 {
1980 const char *s = "What? tr_interrupt in simulator??\n";
1981 SIMCOUT(s,strlen(s));
1982 }
1983 return IRQ_HANDLED;
1984#endif
1985
1986 /* find out the line that caused this irq and get it from rs_table */
1987
1988 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
1989
1990 for (i = 0; i < NR_PORTS; i++) {
1991 info = rs_table + i;
1992 if (!info->enabled || !info->uses_dma_out)
1993 continue;
1994 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
1995 if (ireg & info->irq) {
1996 handled = 1;
1997 /* we can send a new dma bunch. make it so. */
1998 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
1999 /* Read jiffies_usec first,
2000 * we want this time to be as late as possible
2001 */
2002 PROCSTAT(ser_stat[info->line].tx_dma_ints++);
2003 info->last_tx_active_usec = GET_JIFFIES_USEC();
2004 info->last_tx_active = jiffies;
2005 transmit_chars_dma(info);
2006 }
2007
2008 /* FIXME: here we should really check for a change in the
2009 status lines and if so call status_handle(info) */
2010 }
2011 return IRQ_RETVAL(handled);
2012} /* tr_interrupt */
2013
2014/* dma input channel interrupt handler */
2015
2016static irqreturn_t
7d12e780 2017rec_interrupt(int irq, void *dev_id)
1da177e4
LT		 2018{
2019 struct e100_serial *info;
2020 unsigned long ireg;
2021 int i;
2022 int handled = 0;
2023
2024#ifdef CONFIG_SVINTO_SIM
2025 /* No receive in the simulator. Will probably be when the rest of
2026 * the serial interface works, and this piece will just be removed.
2027 */
2028 {
2029 const char *s = "What? rec_interrupt in simulator??\n";
2030 SIMCOUT(s,strlen(s));
2031 }
2032 return IRQ_HANDLED;
2033#endif
2034
2035 /* find out the line that caused this irq and get it from rs_table */
2036
2037 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2038
2039 for (i = 0; i < NR_PORTS; i++) {
2040 info = rs_table + i;
2041 if (!info->enabled || !info->uses_dma_in)
2042 continue;
2043 /* check for both dma_eop and dma_descr for the input dma channel */
2044 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
2045 handled = 1;
2046 /* we have received something */
2047 receive_chars_dma(info);
2048 }
2049
2050 /* FIXME: here we should really check for a change in the
2051 status lines and if so call status_handle(info) */
2052 }
2053 return IRQ_RETVAL(handled);
2054} /* rec_interrupt */
2055
41c28ff1 2056static int force_eop_if_needed(struct e100_serial *info)
1da177e4
LT		 2057{
2058 /* We check data_avail bit to determine if data has
2059 * arrived since last time
2060 */
d7283353 2061 unsigned char rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2062
2063 /* error or datavail? */
2064 if (rstat & SER_ERROR_MASK) {
2065 /* Some error has occurred. If there has been valid data, an
2066 * EOP interrupt will be made automatically. If no data, the
2067 * normal ser_interrupt should be enabled and handle it.
2068 * So do nothing!
2069 */
2070 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
2071 rstat | (info->line << 8));
2072 return 0;
2073 }
2074
2075 if (rstat & SER_DATA_AVAIL_MASK) {
2076 /* Ok data, no error, count it */
2077 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
2078 rstat | (info->line << 8)));
2079 /* Read data to clear status flags */
d7283353 2080 (void)info->ioport[REG_DATA];
1da177e4
LT		 2081
2082 info->forced_eop = 0;
2083 START_FLUSH_FAST_TIMER(info, "magic");
2084 return 0;
2085 }
2086
2087 /* hit the timeout, force an EOP for the input
2088 * dma channel if we haven't already
2089 */
2090 if (!info->forced_eop) {
2091 info->forced_eop = 1;
2092 PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
2093 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
2094 FORCE_EOP(info);
2095 }
2096
2097 return 1;
2098}
2099
41c28ff1 2100static void flush_to_flip_buffer(struct e100_serial *info)
1da177e4 2101{
1da177e4 2102 struct etrax_recv_buffer *buffer;
1da177e4 2103 unsigned long flags;
1da177e4 2104
77accbf5 2105 local_irq_save(flags);
1da177e4 2106
2090ab05 2107 while ((buffer = info->first_recv_buffer) != NULL) {
1da177e4
LT		 2108 unsigned int count = buffer->length;
2109
05c7cd39 2110 tty_insert_flip_string(&info->port, buffer->buffer, count);
1da177e4 2111 info->recv_cnt -= count;
1da177e4
LT		 2112
2113 if (count == buffer->length) {
2114 info->first_recv_buffer = buffer->next;
2115 kfree(buffer);
2116 } else {
2117 buffer->length -= count;
2118 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2119 buffer->error = TTY_NORMAL;
2120 }
2121 }
2122
2123 if (!info->first_recv_buffer)
2124 info->last_recv_buffer = NULL;
2125
77accbf5 2126 local_irq_restore(flags);
1da177e4 2127
77accbf5 2128 /* This includes a check for low-latency */
2e124b4a 2129 tty_flip_buffer_push(&info->port);
1da177e4
LT		 2130}
2131
41c28ff1 2132static void check_flush_timeout(struct e100_serial *info)
1da177e4
LT		 2133{
2134 /* Flip what we've got (if we can) */
2135 flush_to_flip_buffer(info);
2136
2137 /* We might need to flip later, but not to fast
2138 * since the system is busy processing input... */
2139 if (info->first_recv_buffer)
2140 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2141
2142 /* Force eop last, since data might have come while we're processing
2143 * and if we started the slow timer above, we won't start a fast
2144 * below.
2145 */
2146 force_eop_if_needed(info);
2147}
2148
2149#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2150static void flush_timeout_function(unsigned long data)
2151{
2152 struct e100_serial *info = (struct e100_serial *)data;
2153
2154 fast_timers[info->line].function = NULL;
2155 serial_fast_timer_expired++;
2156 TIMERD(DEBUG_LOG(info->line, "flush_timout %i ", info->line));
2157 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2158 check_flush_timeout(info);
2159}
2160
2161#else
2162
2163/* dma fifo/buffer timeout handler
2164 forces an end-of-packet for the dma input channel if no chars
2165 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2166*/
2167
2168static struct timer_list flush_timer;
2169
2170static void
2171timed_flush_handler(unsigned long ptr)
2172{
2173 struct e100_serial *info;
2174 int i;
2175
2176#ifdef CONFIG_SVINTO_SIM
2177 return;
2178#endif
2179
2180 for (i = 0; i < NR_PORTS; i++) {
2181 info = rs_table + i;
2182 if (info->uses_dma_in)
2183 check_flush_timeout(info);
2184 }
2185
2186 /* restart flush timer */
2187 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2188}
2189#endif
2190
2191#ifdef SERIAL_HANDLE_EARLY_ERRORS
2192
2193/* If there is an error (ie break) when the DMA is running and
2194 * there are no bytes in the fifo the DMA is stopped and we get no
2195 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2196 * transfer, and if it is without error we can turn the serial
2197 * interrupts off.
2198 */
2199
2200/*
2201BREAK handling on ETRAX 100:
2202ETRAX will generate interrupt although there is no stop bit between the
2203characters.
2204
2205Depending on how long the break sequence is, the end of the breaksequence
2206will look differently:
2207| indicates start/end of a character.
2208
2209B= Break character (0x00) with framing error.
2210E= Error byte with parity error received after B characters.
2211F= "Faked" valid byte received immediately after B characters.
2212V= Valid byte
2213
22141.
2215 B BL ___________________________ V
2216.._|__________|__________| |valid data |
2217
2218Multiple frame errors with data == 0x00 (B),
2219the timing matches up "perfectly" so no extra ending char is detected.
2220The RXD pin is 1 in the last interrupt, in that case
2221we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2222know if another byte will come and this really is case 2. below
2223(e.g F=0xFF or 0xFE)
2224If RXD pin is 0 we can expect another character (see 2. below).
2225
2226
22272.
2228
2229 B B E or F__________________..__ V
2230.._|__________|__________|______ | |valid data
2231 "valid" or
2232 parity error
2233
2234Multiple frame errors with data == 0x00 (B),
2235but the part of the break trigs is interpreted as a start bit (and possibly
2236some 0 bits followed by a number of 1 bits and a stop bit).
2237Depending on parity settings etc. this last character can be either
2238a fake "valid" char (F) or have a parity error (E).
2239
2240If the character is valid it will be put in the buffer,
2241we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2242will set the flags so the tty will handle it,
2243if it's an error byte it will not be put in the buffer
2244and we set info->errorcode = ERRCODE_INSERT_BREAK.
2245
2246To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2247of the last faulty char (B) and compares it with the current time:
2248If the time elapsed time is less then 2*char_time_usec we will assume
2249it's a faked F char and not a Valid char and set
2250info->errorcode = ERRCODE_SET_BREAK.
2251
2252Flaws in the above solution:
2253~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2254We use the timer to distinguish a F character from a V character,
2255if a V character is to close after the break we might make the wrong decision.
2256
2257TODO: The break will be delayed until an F or V character is received.
2258
2259*/
2260
12aad550 2261static void handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
1da177e4
LT		 2262{
2263 unsigned long data_read;
77accbf5 2264
1da177e4 2265 /* Read data and status at the same time */
d7283353 2266 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
1da177e4
LT		 2267more_data:
2268 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2269 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2270 }
2271 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2272
2273 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2274 IO_MASK(R_SERIAL0_READ, par_err) |
2275 IO_MASK(R_SERIAL0_READ, overrun) )) {
2276 /* An error */
2277 info->last_rx_active_usec = GET_JIFFIES_USEC();
2278 info->last_rx_active = jiffies;
2279 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2280 DLOG_INT_TRIG(
2281 if (!log_int_trig1_pos) {
2282 log_int_trig1_pos = log_int_pos;
2283 log_int(rdpc(), 0, 0);
2284 }
2285 );
2286
2287
2288 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2289 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2290 /* Most likely a break, but we get interrupts over and
2291 * over again.
2292 */
2293
2294 if (!info->break_detected_cnt) {
2295 DEBUG_LOG(info->line, "#BRK start\n", 0);
2296 }
2297 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2298 /* The RX pin is high now, so the break
2299 * must be over, but....
2300 * we can't really know if we will get another
2301 * last byte ending the break or not.
2302 * And we don't know if the byte (if any) will
2303 * have an error or look valid.
2304 */
2305 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2306 info->errorcode = ERRCODE_INSERT_BREAK;
2307 }
2308 info->break_detected_cnt++;
2309 } else {
2310 /* The error does not look like a break, but could be
2311 * the end of one
2312 */
2313 if (info->break_detected_cnt) {
2314 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2315 info->errorcode = ERRCODE_INSERT_BREAK;
2316 } else {
77accbf5
JN		 2317 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2318 data_in, data_read);
2319 char flag = TTY_NORMAL;
1da177e4 2320 if (info->errorcode == ERRCODE_INSERT_BREAK) {
92a19f9c 2321 tty_insert_flip_char(&info->port, 0, flag);
1da177e4
LT		 2322 info->icount.rx++;
2323 }
1da177e4
LT		 2324
2325 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2326 info->icount.parity++;
77accbf5 2327 flag = TTY_PARITY;
1da177e4
LT		 2328 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2329 info->icount.overrun++;
77accbf5 2330 flag = TTY_OVERRUN;
1da177e4
LT		 2331 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2332 info->icount.frame++;
77accbf5 2333 flag = TTY_FRAME;
1da177e4 2334 }
92a19f9c 2335 tty_insert_flip_char(&info->port, data, flag);
1da177e4
LT		 2336 info->errorcode = 0;
2337 }
2338 info->break_detected_cnt = 0;
2339 }
2340 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2341 /* No error */
2342 DLOG_INT_TRIG(
2343 if (!log_int_trig1_pos) {
2344 if (log_int_pos >= log_int_size) {
2345 log_int_pos = 0;
2346 }
2347 log_int_trig0_pos = log_int_pos;
2348 log_int(rdpc(), 0, 0);
2349 }
2350 );
92a19f9c 2351 tty_insert_flip_char(&info->port,
77accbf5
JN		 2352 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2353 TTY_NORMAL);
1da177e4
LT		 2354 } else {
2355 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2356 }
2357
2358
1da177e4 2359 info->icount.rx++;
d7283353 2360 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
1da177e4
LT		 2361 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2362 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2363 goto more_data;
2364 }
2365
2e124b4a 2366 tty_flip_buffer_push(&info->port);
1da177e4
LT		 2367}
2368
12aad550 2369static void handle_ser_rx_interrupt(struct e100_serial *info)
1da177e4
LT		 2370{
2371 unsigned char rstat;
2372
2373#ifdef SERIAL_DEBUG_INTR
2374 printk("Interrupt from serport %d\n", i);
2375#endif
2376/* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2377 if (!info->uses_dma_in) {
12aad550
JS		 2378 handle_ser_rx_interrupt_no_dma(info);
2379 return;
1da177e4
LT		 2380 }
2381 /* DMA is used */
d7283353 2382 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2383 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2384 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2385 }
2386
2387 if (rstat & SER_ERROR_MASK) {
2388 unsigned char data;
2389
2390 info->last_rx_active_usec = GET_JIFFIES_USEC();
2391 info->last_rx_active = jiffies;
2392 /* If we got an error, we must reset it by reading the
2393 * data_in field
2394 */
d7283353 2395 data = info->ioport[REG_DATA];
1da177e4
LT		 2396 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2397 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2398 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2399 /* Most likely a break, but we get interrupts over and
2400 * over again.
2401 */
2402
2403 if (!info->break_detected_cnt) {
2404 DEBUG_LOG(info->line, "#BRK start\n", 0);
2405 }
2406 if (rstat & SER_RXD_MASK) {
2407 /* The RX pin is high now, so the break
2408 * must be over, but....
2409 * we can't really know if we will get another
2410 * last byte ending the break or not.
2411 * And we don't know if the byte (if any) will
2412 * have an error or look valid.
2413 */
2414 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2415 info->errorcode = ERRCODE_INSERT_BREAK;
2416 }
2417 info->break_detected_cnt++;
2418 } else {
2419 /* The error does not look like a break, but could be
2420 * the end of one
2421 */
2422 if (info->break_detected_cnt) {
2423 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2424 info->errorcode = ERRCODE_INSERT_BREAK;
2425 } else {
2426 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2427 info->icount.brk++;
2428 add_char_and_flag(info, '\0', TTY_BREAK);
2429 }
2430
2431 if (rstat & SER_PAR_ERR_MASK) {
2432 info->icount.parity++;
2433 add_char_and_flag(info, data, TTY_PARITY);
2434 } else if (rstat & SER_OVERRUN_MASK) {
2435 info->icount.overrun++;
2436 add_char_and_flag(info, data, TTY_OVERRUN);
2437 } else if (rstat & SER_FRAMING_ERR_MASK) {
2438 info->icount.frame++;
2439 add_char_and_flag(info, data, TTY_FRAME);
2440 }
2441
2442 info->errorcode = 0;
2443 }
2444 info->break_detected_cnt = 0;
2445 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2446 ((rstat & SER_ERROR_MASK) << 8) | data);
2447 }
2448 PROCSTAT(ser_stat[info->line].early_errors_cnt++);
2449 } else { /* It was a valid byte, now let the DMA do the rest */
2450 unsigned long curr_time_u = GET_JIFFIES_USEC();
2451 unsigned long curr_time = jiffies;
2452
2453 if (info->break_detected_cnt) {
2454 /* Detect if this character is a new valid char or the
2455 * last char in a break sequence: If LSBits are 0 and
2456 * MSBits are high AND the time is close to the
2457 * previous interrupt we should discard it.
2458 */
2459 long elapsed_usec =
2460 (curr_time - info->last_rx_active) * (1000000/HZ) +
2461 curr_time_u - info->last_rx_active_usec;
2462 if (elapsed_usec < 2*info->char_time_usec) {
2463 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2464 /* Report as BREAK (error) and let
2465 * receive_chars_dma() handle it
2466 */
2467 info->errorcode = ERRCODE_SET_BREAK;
2468 } else {
2469 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2470 }
2471 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2472 }
2473
2474#ifdef SERIAL_DEBUG_INTR
2475 printk("** OK, disabling ser_interrupts\n");
2476#endif
2477 e100_disable_serial_data_irq(info);
2478 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2479 info->break_detected_cnt = 0;
2480
2481 PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++);
2482 }
2483 /* Restarting the DMA never hurts */
2484 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2485 START_FLUSH_FAST_TIMER(info, "ser_int");
1da177e4
LT		 2486} /* handle_ser_rx_interrupt */
2487
41c28ff1 2488static void handle_ser_tx_interrupt(struct e100_serial *info)
1da177e4
LT		 2489{
2490 unsigned long flags;
2491
2492 if (info->x_char) {
2493 unsigned char rstat;
2494 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
77accbf5 2495 local_irq_save(flags);
d7283353 2496 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2497 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2498
d7283353 2499 info->ioport[REG_TR_DATA] = info->x_char;
1da177e4
LT		 2500 info->icount.tx++;
2501 info->x_char = 0;
2502 /* We must enable since it is disabled in ser_interrupt */
2503 e100_enable_serial_tx_ready_irq(info);
77accbf5 2504 local_irq_restore(flags);
1da177e4
LT		 2505 return;
2506 }
2507 if (info->uses_dma_out) {
2508 unsigned char rstat;
2509 int i;
2510 /* We only use normal tx interrupt when sending x_char */
2511 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
77accbf5 2512 local_irq_save(flags);
d7283353 2513 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2514 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2515 e100_disable_serial_tx_ready_irq(info);
a88487c7
TI		 2516 if (info->port.tty->stopped)
2517 rs_stop(info->port.tty);
1da177e4
LT		 2518 /* Enable the DMA channel and tell it to continue */
2519 e100_enable_txdma_channel(info);
2520 /* Wait 12 cycles before doing the DMA command */
2521 for(i = 6; i > 0; i--)
2522 nop();
2523
2524 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
77accbf5 2525 local_irq_restore(flags);
1da177e4
LT		 2526 return;
2527 }
2528 /* Normal char-by-char interrupt */
2529 if (info->xmit.head == info->xmit.tail
ee797069 2530 || info->port.tty->stopped) {
a88487c7
TI		 2531 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2532 info->port.tty->stopped));
1da177e4
LT		 2533 e100_disable_serial_tx_ready_irq(info);
2534 info->tr_running = 0;
2535 return;
2536 }
2537 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2538 /* Send a byte, rs485 timing is critical so turn of ints */
77accbf5 2539 local_irq_save(flags);
d7283353 2540 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
1da177e4
LT		 2541 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2542 info->icount.tx++;
2543 if (info->xmit.head == info->xmit.tail) {
2544#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
6fd1af4c 2545 if (info->rs485.flags & SER_RS485_ENABLED) {
1da177e4
LT		 2546 /* Set a short timer to toggle RTS */
2547 start_one_shot_timer(&fast_timers_rs485[info->line],
2548 rs485_toggle_rts_timer_function,
2549 (unsigned long)info,
2550 info->char_time_usec*2,
2551 "RS-485");
2552 }
2553#endif /* RS485 */
2554 info->last_tx_active_usec = GET_JIFFIES_USEC();
2555 info->last_tx_active = jiffies;
2556 e100_disable_serial_tx_ready_irq(info);
2557 info->tr_running = 0;
2558 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2559 } else {
2560 /* We must enable since it is disabled in ser_interrupt */
2561 e100_enable_serial_tx_ready_irq(info);
2562 }
77accbf5 2563 local_irq_restore(flags);
1da177e4
LT		 2564
2565 if (CIRC_CNT(info->xmit.head,
2566 info->xmit.tail,
2567 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2568 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2569
2570} /* handle_ser_tx_interrupt */
2571
2572/* result of time measurements:
2573 * RX duration 54-60 us when doing something, otherwise 6-9 us
2574 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2575 */
2576static irqreturn_t
7d12e780 2577ser_interrupt(int irq, void *dev_id)
1da177e4
LT		 2578{
2579 static volatile int tx_started = 0;
2580 struct e100_serial *info;
2581 int i;
2582 unsigned long flags;
2583 unsigned long irq_mask1_rd;
2584 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2585 int handled = 0;
2586 static volatile unsigned long reentered_ready_mask = 0;
2587
77accbf5 2588 local_irq_save(flags);
1da177e4
LT		 2589 irq_mask1_rd = *R_IRQ_MASK1_RD;
2590 /* First handle all rx interrupts with ints disabled */
2591 info = rs_table;
2592 irq_mask1_rd &= e100_ser_int_mask;
2593 for (i = 0; i < NR_PORTS; i++) {
2594 /* Which line caused the data irq? */
2595 if (irq_mask1_rd & data_mask) {
2596 handled = 1;
2597 handle_ser_rx_interrupt(info);
2598 }
2599 info += 1;
2600 data_mask <<= 2;
2601 }
2602 /* Handle tx interrupts with interrupts enabled so we
2603 * can take care of new data interrupts while transmitting
2604 * We protect the tx part with the tx_started flag.
2605 * We disable the tr_ready interrupts we are about to handle and
2606 * unblock the serial interrupt so new serial interrupts may come.
2607 *
2608 * If we get a new interrupt:
2609 * - it migth be due to synchronous serial ports.
2610 * - serial irq will be blocked by general irq handler.
2611 * - async data will be handled above (sync will be ignored).
2612 * - tx_started flag will prevent us from trying to send again and
2613 * we will exit fast - no need to unblock serial irq.
2614 * - Next (sync) serial interrupt handler will be runned with
2615 * disabled interrupt due to restore_flags() at end of function,
2616 * so sync handler will not be preempted or reentered.
2617 */
2618 if (!tx_started) {
2619 unsigned long ready_mask;
2620 unsigned long
2621 tx_started = 1;
2622 /* Only the tr_ready interrupts left */
2623 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2624 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2625 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2626 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2627 while (irq_mask1_rd) {
2628 /* Disable those we are about to handle */
2629 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2630 /* Unblock the serial interrupt */
2631 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2632
77accbf5 2633 local_irq_enable();
1da177e4
LT		 2634 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2635 info = rs_table;
2636 for (i = 0; i < NR_PORTS; i++) {
2637 /* Which line caused the ready irq? */
2638 if (irq_mask1_rd & ready_mask) {
2639 handled = 1;
2640 handle_ser_tx_interrupt(info);
2641 }
2642 info += 1;
2643 ready_mask <<= 2;
2644 }
2645 /* handle_ser_tx_interrupt enables tr_ready interrupts */
77accbf5 2646 local_irq_disable();
1da177e4
LT		 2647 /* Handle reentered TX interrupt */
2648 irq_mask1_rd = reentered_ready_mask;
2649 }
77accbf5 2650 local_irq_disable();
1da177e4
LT		 2651 tx_started = 0;
2652 } else {
2653 unsigned long ready_mask;
2654 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2655 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2656 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2657 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2658 if (ready_mask) {
2659 reentered_ready_mask |= ready_mask;
2660 /* Disable those we are about to handle */
2661 *R_IRQ_MASK1_CLR = ready_mask;
2662 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2663 }
2664 }
2665
77accbf5 2666 local_irq_restore(flags);
1da177e4
LT		 2667 return IRQ_RETVAL(handled);
2668} /* ser_interrupt */
2669#endif
2670
2671/*
2672 * -------------------------------------------------------------------
2673 * Here ends the serial interrupt routines.
2674 * -------------------------------------------------------------------
2675 */
2676
2677/*
2678 * This routine is used to handle the "bottom half" processing for the
2679 * serial driver, known also the "software interrupt" processing.
2680 * This processing is done at the kernel interrupt level, after the
2681 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2682 * is where time-consuming activities which can not be done in the
2683 * interrupt driver proper are done; the interrupt driver schedules
2684 * them using rs_sched_event(), and they get done here.
2685 */
2686static void
77accbf5 2687do_softint(struct work_struct *work)
1da177e4 2688{
77accbf5 2689 struct e100_serial *info;
1da177e4
LT		 2690 struct tty_struct *tty;
2691
77accbf5
JN		 2692 info = container_of(work, struct e100_serial, work);
2693
a88487c7 2694 tty = info->port.tty;
1da177e4
LT		 2695 if (!tty)
2696 return;
2697
b963a844
JS		 2698 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2699 tty_wakeup(tty);
1da177e4
LT		 2700}
2701
2702static int
2703startup(struct e100_serial * info)
2704{
2705 unsigned long flags;
2706 unsigned long xmit_page;
2707 int i;
2708
2709 xmit_page = get_zeroed_page(GFP_KERNEL);
2710 if (!xmit_page)
2711 return -ENOMEM;
2712
77accbf5 2713 local_irq_save(flags);
1da177e4
LT		 2714
2715 /* if it was already initialized, skip this */
2716
b1d984cf 2717 if (info->port.flags & ASYNC_INITIALIZED) {
77accbf5 2718 local_irq_restore(flags);
1da177e4
LT		 2719 free_page(xmit_page);
2720 return 0;
2721 }
2722
2723 if (info->xmit.buf)
2724 free_page(xmit_page);
2725 else
2726 info->xmit.buf = (unsigned char *) xmit_page;
2727
2728#ifdef SERIAL_DEBUG_OPEN
2729 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2730#endif
2731
2732#ifdef CONFIG_SVINTO_SIM
2733 /* Bits and pieces collected from below. Better to have them
2734 in one ifdef:ed clause than to mix in a lot of ifdefs,
2735 right? */
a88487c7
TI		 2736 if (info->port.tty)
2737 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 2738
2739 info->xmit.head = info->xmit.tail = 0;
2740 info->first_recv_buffer = info->last_recv_buffer = NULL;
2741 info->recv_cnt = info->max_recv_cnt = 0;
2742
2743 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2744 info->rec_descr[i].buf = NULL;
2745
2746 /* No real action in the simulator, but may set info important
2747 to ioctl. */
2748 change_speed(info);
2749#else
2750
2751 /*
2752 * Clear the FIFO buffers and disable them
2753 * (they will be reenabled in change_speed())
2754 */
2755
2756 /*
2757 * Reset the DMA channels and make sure their interrupts are cleared
2758 */
2759
2760 if (info->dma_in_enabled) {
2761 info->uses_dma_in = 1;
2762 e100_enable_rxdma_channel(info);
2763
2764 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2765
2766 /* Wait until reset cycle is complete */
2767 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2768 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2769
2770 /* Make sure the irqs are cleared */
2771 *info->iclrintradr =
2772 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2773 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2774 } else {
2775 e100_disable_rxdma_channel(info);
2776 }
2777
2778 if (info->dma_out_enabled) {
2779 info->uses_dma_out = 1;
2780 e100_enable_txdma_channel(info);
2781 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2782
2783 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2784 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2785
2786 /* Make sure the irqs are cleared */
2787 *info->oclrintradr =
2788 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2789 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2790 } else {
2791 e100_disable_txdma_channel(info);
2792 }
2793
a88487c7
TI		 2794 if (info->port.tty)
2795 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 2796
2797 info->xmit.head = info->xmit.tail = 0;
2798 info->first_recv_buffer = info->last_recv_buffer = NULL;
2799 info->recv_cnt = info->max_recv_cnt = 0;
2800
2801 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2802 info->rec_descr[i].buf = 0;
2803
2804 /*
2805 * and set the speed and other flags of the serial port
2806 * this will start the rx/tx as well
2807 */
2808#ifdef SERIAL_HANDLE_EARLY_ERRORS
2809 e100_enable_serial_data_irq(info);
2810#endif
2811 change_speed(info);
2812
2813 /* dummy read to reset any serial errors */
2814
d7283353 2815 (void)info->ioport[REG_DATA];
1da177e4
LT		 2816
2817 /* enable the interrupts */
2818 if (info->uses_dma_out)
2819 e100_enable_txdma_irq(info);
2820
2821 e100_enable_rx_irq(info);
2822
2823 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2824
2825 /* setup the dma input descriptor and start dma */
2826
2827 start_receive(info);
2828
2829 /* for safety, make sure the descriptors last result is 0 bytes written */
2830
2831 info->tr_descr.sw_len = 0;
2832 info->tr_descr.hw_len = 0;
2833 info->tr_descr.status = 0;
2834
2835 /* enable RTS/DTR last */
2836
2837 e100_rts(info, 1);
2838 e100_dtr(info, 1);
2839
2840#endif /* CONFIG_SVINTO_SIM */
2841
b1d984cf 2842 info->port.flags |= ASYNC_INITIALIZED;
1da177e4 2843
77accbf5 2844 local_irq_restore(flags);
1da177e4
LT		 2845 return 0;
2846}
2847
2848/*
2849 * This routine will shutdown a serial port; interrupts are disabled, and
2850 * DTR is dropped if the hangup on close termio flag is on.
2851 */
2852static void
2853shutdown(struct e100_serial * info)
2854{
2855 unsigned long flags;
2856 struct etrax_dma_descr *descr = info->rec_descr;
2857 struct etrax_recv_buffer *buffer;
2858 int i;
2859
2860#ifndef CONFIG_SVINTO_SIM
2861 /* shut down the transmitter and receiver */
2862 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2863 e100_disable_rx(info);
d7283353 2864 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
1da177e4
LT		 2865
2866 /* disable interrupts, reset dma channels */
2867 if (info->uses_dma_in) {
2868 e100_disable_rxdma_irq(info);
2869 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2870 info->uses_dma_in = 0;
2871 } else {
2872 e100_disable_serial_data_irq(info);
2873 }
2874
2875 if (info->uses_dma_out) {
2876 e100_disable_txdma_irq(info);
2877 info->tr_running = 0;
2878 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2879 info->uses_dma_out = 0;
2880 } else {
2881 e100_disable_serial_tx_ready_irq(info);
2882 info->tr_running = 0;
2883 }
2884
2885#endif /* CONFIG_SVINTO_SIM */
2886
b1d984cf 2887 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 2888 return;
2889
2890#ifdef SERIAL_DEBUG_OPEN
2891 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2892 info->irq);
2893#endif
2894
77accbf5 2895 local_irq_save(flags);
1da177e4
LT		 2896
2897 if (info->xmit.buf) {
2898 free_page((unsigned long)info->xmit.buf);
2899 info->xmit.buf = NULL;
2900 }
2901
2902 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2903 if (descr[i].buf) {
2904 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2905 kfree(buffer);
2906 descr[i].buf = 0;
2907 }
2908
adc8d746 2909 if (!info->port.tty || (info->port.tty->termios.c_cflag & HUPCL)) {
1da177e4
LT		 2910 /* hang up DTR and RTS if HUPCL is enabled */
2911 e100_dtr(info, 0);
2912 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2913 }
2914
a88487c7
TI		 2915 if (info->port.tty)
2916 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 2917
b1d984cf 2918 info->port.flags &= ~ASYNC_INITIALIZED;
77accbf5 2919 local_irq_restore(flags);
1da177e4
LT		 2920}
2921
2922
2923/* change baud rate and other assorted parameters */
2924
2925static void
2926change_speed(struct e100_serial *info)
2927{
2928 unsigned int cflag;
2929 unsigned long xoff;
2930 unsigned long flags;
2931 /* first some safety checks */
2932
adc8d746 2933 if (!info->port.tty)
1da177e4 2934 return;
d7283353 2935 if (!info->ioport)
1da177e4
LT		 2936 return;
2937
adc8d746 2938 cflag = info->port.tty->termios.c_cflag;
1da177e4
LT		 2939
2940 /* possibly, the tx/rx should be disabled first to do this safely */
2941
2942 /* change baud-rate and write it to the hardware */
b1d984cf 2943 if ((info->port.flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
1da177e4
LT		 2944 /* Special baudrate */
2945 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2946 unsigned long alt_source =
2947 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2948 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2949 /* R_ALT_SER_BAUDRATE selects the source */
2950 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2951 (unsigned long)info->baud_base, info->custom_divisor));
2952 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2953 /* 0, 2-65535 (0=65536) */
2954 u16 divisor = info->custom_divisor;
2955 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2956 /* baudrate is 3.125MHz/custom_divisor */
2957 alt_source =
2958 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2959 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2960 alt_source = 0x11;
2961 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2962 *R_SERIAL_PRESCALE = divisor;
2963 info->baud = SERIAL_PRESCALE_BASE/divisor;
2964 }
2965#ifdef CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED
2966 else if ((info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8 &&
2967 info->custom_divisor == 1) ||
2968 (info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ &&
2969 info->custom_divisor == 8)) {
2970 /* ext_clk selected */
2971 alt_source =
2972 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) |
2973 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern);
2974 DBAUD(printk("using external baudrate: %lu\n", CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8));
2975 info->baud = CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8;
2976 }
1da177e4
LT		 2977#endif
2978 else
2979 {
2980 /* Bad baudbase, we don't support using timer0
2981 * for baudrate.
2982 */
2983 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
2984 (unsigned long)info->baud_base, info->custom_divisor);
2985 }
2986 r_alt_ser_baudrate_shadow &= ~mask;
2987 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
2988 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
2989 } else {
2990 /* Normal baudrate */
2991 /* Make sure we use normal baudrate */
2992 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2993 unsigned long alt_source =
2994 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2995 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2996 r_alt_ser_baudrate_shadow &= ~mask;
2997 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
2998#ifndef CONFIG_SVINTO_SIM
2999 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3000#endif /* CONFIG_SVINTO_SIM */
3001
3002 info->baud = cflag_to_baud(cflag);
3003#ifndef CONFIG_SVINTO_SIM
d7283353 3004 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
1da177e4
LT		 3005#endif /* CONFIG_SVINTO_SIM */
3006 }
3007
3008#ifndef CONFIG_SVINTO_SIM
3009 /* start with default settings and then fill in changes */
77accbf5 3010 local_irq_save(flags);
1da177e4
LT		 3011 /* 8 bit, no/even parity */
3012 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
3013 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
3014 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
3015
3016 /* 8 bit, no/even parity, 1 stop bit, no cts */
3017 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
3018 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
3019 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
3020 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
3021 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
3022
3023 if ((cflag & CSIZE) == CS7) {
3024 /* set 7 bit mode */
3025 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
3026 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
3027 }
3028
3029 if (cflag & CSTOPB) {
3030 /* set 2 stop bit mode */
3031 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
3032 }
3033
3034 if (cflag & PARENB) {
3035 /* enable parity */
3036 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
3037 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
3038 }
3039
3040 if (cflag & CMSPAR) {
3041 /* enable stick parity, PARODD mean Mark which matches ETRAX */
3042 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
3043 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
3044 }
3045 if (cflag & PARODD) {
3046 /* set odd parity (or Mark if CMSPAR) */
3047 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
3048 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
3049 }
3050
3051 if (cflag & CRTSCTS) {
3052 /* enable automatic CTS handling */
3053 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
3054 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
3055 }
3056
3057 /* make sure the tx and rx are enabled */
3058
3059 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
3060 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
3061
3062 /* actually write the control regs to the hardware */
3063
d7283353
AC		 3064 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3065 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
a88487c7 3066 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
1da177e4 3067 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
adc8d746 3068 if (info->port.tty->termios.c_iflag & IXON ) {
a88487c7
TI		 3069 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
3070 STOP_CHAR(info->port.tty)));
1da177e4
LT		 3071 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
3072 }
3073
d7283353 3074 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
77accbf5 3075 local_irq_restore(flags);
1da177e4
LT		 3076#endif /* !CONFIG_SVINTO_SIM */
3077
3078 update_char_time(info);
3079
3080} /* change_speed */
3081
3082/* start transmitting chars NOW */
3083
3084static void
3085rs_flush_chars(struct tty_struct *tty)
3086{
3087 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3088 unsigned long flags;
3089
3090 if (info->tr_running ||
3091 info->xmit.head == info->xmit.tail ||
3092 tty->stopped ||
1da177e4
LT		 3093 !info->xmit.buf)
3094 return;
3095
3096#ifdef SERIAL_DEBUG_FLOW
3097 printk("rs_flush_chars\n");
3098#endif
3099
3100 /* this protection might not exactly be necessary here */
3101
77accbf5 3102 local_irq_save(flags);
1da177e4 3103 start_transmit(info);
77accbf5 3104 local_irq_restore(flags);
1da177e4
LT		 3105}
3106
77accbf5 3107static int rs_raw_write(struct tty_struct *tty,
41c28ff1 3108 const unsigned char *buf, int count)
1da177e4
LT		 3109{
3110 int c, ret = 0;
3111 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3112 unsigned long flags;
3113
3114 /* first some sanity checks */
3115
f938f378 3116 if (!info->xmit.buf)
1da177e4
LT		 3117 return 0;
3118
3119#ifdef SERIAL_DEBUG_DATA
3120 if (info->line == SERIAL_DEBUG_LINE)
3121 printk("rs_raw_write (%d), status %d\n",
d7283353 3122 count, info->ioport[REG_STATUS]);
1da177e4
LT		 3123#endif
3124
3125#ifdef CONFIG_SVINTO_SIM
3126 /* Really simple. The output is here and now. */
3127 SIMCOUT(buf, count);
3128 return count;
3129#endif
77accbf5 3130 local_save_flags(flags);
1da177e4
LT		 3131 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
3132 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
3133
3134
77accbf5
JN		 3135 /* The local_irq_disable/restore_flags pairs below are needed
3136 * because the DMA interrupt handler moves the info->xmit values.
3137 * the memcpy needs to be in the critical region unfortunately,
3138 * because we need to read xmit values, memcpy, write xmit values
3139 * in one atomic operation... this could perhaps be avoided by
3140 * more clever design.
1da177e4 3141 */
77accbf5 3142 local_irq_disable();
1da177e4
LT		 3143 while (count) {
3144 c = CIRC_SPACE_TO_END(info->xmit.head,
3145 info->xmit.tail,
3146 SERIAL_XMIT_SIZE);
3147
3148 if (count < c)
3149 c = count;
3150 if (c <= 0)
3151 break;
3152
3153 memcpy(info->xmit.buf + info->xmit.head, buf, c);
3154 info->xmit.head = (info->xmit.head + c) &
3155 (SERIAL_XMIT_SIZE-1);
3156 buf += c;
3157 count -= c;
3158 ret += c;
3159 }
77accbf5 3160 local_irq_restore(flags);
1da177e4
LT		 3161
3162 /* enable transmitter if not running, unless the tty is stopped
3163 * this does not need IRQ protection since if tr_running == 0
3164 * the IRQ's are not running anyway for this port.
3165 */
3166 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3167
3168 if (info->xmit.head != info->xmit.tail &&
3169 !tty->stopped &&
1da177e4
LT		 3170 !info->tr_running) {
3171 start_transmit(info);
3172 }
3173
3174 return ret;
3175} /* raw_raw_write() */
3176
3177static int
77accbf5 3178rs_write(struct tty_struct *tty,
1da177e4
LT		 3179 const unsigned char *buf, int count)
3180{
3181#if defined(CONFIG_ETRAX_RS485)
3182 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3183
6fd1af4c 3184 if (info->rs485.flags & SER_RS485_ENABLED)
1da177e4
LT		 3185 {
3186 /* If we are in RS-485 mode, we need to toggle RTS and disable
3187 * the receiver before initiating a DMA transfer
3188 */
3189#ifdef CONFIG_ETRAX_FAST_TIMER
3190 /* Abort any started timer */
3191 fast_timers_rs485[info->line].function = NULL;
3192 del_fast_timer(&fast_timers_rs485[info->line]);
3193#endif
6fd1af4c 3194 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
1da177e4
LT		 3195#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3196 e100_disable_rx(info);
3197 e100_enable_rx_irq(info);
3198#endif
93f3350c
CS		 3199 if (info->rs485.delay_rts_before_send > 0)
3200 msleep(info->rs485.delay_rts_before_send);
1da177e4
LT		 3201 }
3202#endif /* CONFIG_ETRAX_RS485 */
3203
77accbf5 3204 count = rs_raw_write(tty, buf, count);
1da177e4
LT		 3205
3206#if defined(CONFIG_ETRAX_RS485)
6fd1af4c 3207 if (info->rs485.flags & SER_RS485_ENABLED)
1da177e4
LT		 3208 {
3209 unsigned int val;
3210 /* If we are in RS-485 mode the following has to be done:
3211 * wait until DMA is ready
3212 * wait on transmit shift register
3213 * toggle RTS
3214 * enable the receiver
3215 */
3216
3217 /* Sleep until all sent */
3218 tty_wait_until_sent(tty, 0);
3219#ifdef CONFIG_ETRAX_FAST_TIMER
3220 /* Now sleep a little more so that shift register is empty */
3221 schedule_usleep(info->char_time_usec * 2);
3222#endif
3223 /* wait on transmit shift register */
3224 do{
3225 get_lsr_info(info, &val);
3226 }while (!(val & TIOCSER_TEMT));
3227
6fd1af4c 3228 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1da177e4
LT		 3229
3230#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3231 e100_enable_rx(info);
3232 e100_enable_rxdma_irq(info);
3233#endif
3234 }
3235#endif /* CONFIG_ETRAX_RS485 */
3236
3237 return count;
3238} /* rs_write */
3239
3240
3241/* how much space is available in the xmit buffer? */
3242
3243static int
3244rs_write_room(struct tty_struct *tty)
3245{
3246 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3247
3248 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3249}
3250
3251/* How many chars are in the xmit buffer?
3252 * This does not include any chars in the transmitter FIFO.
3253 * Use wait_until_sent for waiting for FIFO drain.
3254 */
3255
3256static int
3257rs_chars_in_buffer(struct tty_struct *tty)
3258{
3259 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3260
3261 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3262}
3263
3264/* discard everything in the xmit buffer */
3265
3266static void
3267rs_flush_buffer(struct tty_struct *tty)
3268{
3269 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3270 unsigned long flags;
3271
77accbf5 3272 local_irq_save(flags);
1da177e4 3273 info->xmit.head = info->xmit.tail = 0;
77accbf5 3274 local_irq_restore(flags);
1da177e4 3275
b963a844 3276 tty_wakeup(tty);
1da177e4
LT		 3277}
3278
3279/*
3280 * This function is used to send a high-priority XON/XOFF character to
3281 * the device
3282 *
3283 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3284 * but we do it in handle_ser_tx_interrupt().
3285 * We disable DMA channel and enable tx ready interrupt and write the
3286 * character when possible.
3287 */
3288static void rs_send_xchar(struct tty_struct *tty, char ch)
3289{
3290 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3291 unsigned long flags;
77accbf5 3292 local_irq_save(flags);
1da177e4
LT		 3293 if (info->uses_dma_out) {
3294 /* Put the DMA on hold and disable the channel */
3295 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3296 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3297 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3298 e100_disable_txdma_channel(info);
3299 }
3300
3301 /* Must make sure transmitter is not stopped before we can transmit */
3302 if (tty->stopped)
3303 rs_start(tty);
3304
3305 /* Enable manual transmit interrupt and send from there */
3306 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3307 info->x_char = ch;
3308 e100_enable_serial_tx_ready_irq(info);
77accbf5 3309 local_irq_restore(flags);
1da177e4
LT		 3310}
3311
3312/*
3313 * ------------------------------------------------------------
3314 * rs_throttle()
3315 *
3316 * This routine is called by the upper-layer tty layer to signal that
3317 * incoming characters should be throttled.
3318 * ------------------------------------------------------------
3319 */
3320static void
3321rs_throttle(struct tty_struct * tty)
3322{
3323 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3324#ifdef SERIAL_DEBUG_THROTTLE
3325 char buf[64];
3326
3327 printk("throttle %s: %lu....\n", tty_name(tty, buf),
3328 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3329#endif
3330 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3331
3332 /* Do RTS before XOFF since XOFF might take some time */
adc8d746 3333 if (tty->termios.c_cflag & CRTSCTS) {
1da177e4
LT		 3334 /* Turn off RTS line */
3335 e100_rts(info, 0);
3336 }
3337 if (I_IXOFF(tty))
3338 rs_send_xchar(tty, STOP_CHAR(tty));
3339
3340}
3341
3342static void
3343rs_unthrottle(struct tty_struct * tty)
3344{
3345 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3346#ifdef SERIAL_DEBUG_THROTTLE
3347 char buf[64];
3348
3349 printk("unthrottle %s: %lu....\n", tty_name(tty, buf),
3350 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3351#endif
3352 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3353 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3354 /* Do RTS before XOFF since XOFF might take some time */
adc8d746 3355 if (tty->termios.c_cflag & CRTSCTS) {
1da177e4
LT		 3356 /* Assert RTS line */
3357 e100_rts(info, 1);
3358 }
3359
3360 if (I_IXOFF(tty)) {
3361 if (info->x_char)
3362 info->x_char = 0;
3363 else
3364 rs_send_xchar(tty, START_CHAR(tty));
3365 }
3366
3367}
3368
3369/*
3370 * ------------------------------------------------------------
3371 * rs_ioctl() and friends
3372 * ------------------------------------------------------------
3373 */
3374
3375static int
3376get_serial_info(struct e100_serial * info,
3377 struct serial_struct * retinfo)
3378{
3379 struct serial_struct tmp;
3380
3381 /* this is all probably wrong, there are a lot of fields
3382 * here that we don't have in e100_serial and maybe we
3383 * should set them to something else than 0.
3384 */
3385
3386 if (!retinfo)
3387 return -EFAULT;
3388 memset(&tmp, 0, sizeof(tmp));
3389 tmp.type = info->type;
3390 tmp.line = info->line;
d7283353 3391 tmp.port = (int)info->ioport;
1da177e4 3392 tmp.irq = info->irq;
b1d984cf 3393 tmp.flags = info->port.flags;
1da177e4 3394 tmp.baud_base = info->baud_base;
892c7cfc
JS		 3395 tmp.close_delay = info->port.close_delay;
3396 tmp.closing_wait = info->port.closing_wait;
1da177e4
LT		 3397 tmp.custom_divisor = info->custom_divisor;
3398 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3399 return -EFAULT;
3400 return 0;
3401}
3402
3403static int
3404set_serial_info(struct e100_serial *info,
3405 struct serial_struct *new_info)
3406{
3407 struct serial_struct new_serial;
3408 struct e100_serial old_info;
3409 int retval = 0;
3410
3411 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3412 return -EFAULT;
3413
3414 old_info = *info;
3415
3416 if (!capable(CAP_SYS_ADMIN)) {
3417 if ((new_serial.type != info->type) ||
892c7cfc 3418 (new_serial.close_delay != info->port.close_delay) ||
1da177e4 3419 ((new_serial.flags & ~ASYNC_USR_MASK) !=
b1d984cf 3420 (info->port.flags & ~ASYNC_USR_MASK)))
1da177e4 3421 return -EPERM;
b1d984cf 3422 info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
1da177e4
LT		 3423 (new_serial.flags & ASYNC_USR_MASK));
3424 goto check_and_exit;
3425 }
3426
3427 if (info->count > 1)
3428 return -EBUSY;
3429
3430 /*
3431 * OK, past this point, all the error checking has been done.
3432 * At this point, we start making changes.....
3433 */
3434
3435 info->baud_base = new_serial.baud_base;
b1d984cf 3436 info->port.flags = ((info->port.flags & ~ASYNC_FLAGS) |
1da177e4
LT		 3437 (new_serial.flags & ASYNC_FLAGS));
3438 info->custom_divisor = new_serial.custom_divisor;
3439 info->type = new_serial.type;
892c7cfc
JS		 3440 info->port.close_delay = new_serial.close_delay;
3441 info->port.closing_wait = new_serial.closing_wait;
b1d984cf 3442 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 3443
3444 check_and_exit:
b1d984cf 3445 if (info->port.flags & ASYNC_INITIALIZED) {
1da177e4
LT		 3446 change_speed(info);
3447 } else
3448 retval = startup(info);
3449 return retval;
3450}
3451
3452/*
3453 * get_lsr_info - get line status register info
3454 *
3455 * Purpose: Let user call ioctl() to get info when the UART physically
3456 * is emptied. On bus types like RS485, the transmitter must
3457 * release the bus after transmitting. This must be done when
3458 * the transmit shift register is empty, not be done when the
3459 * transmit holding register is empty. This functionality
3460 * allows an RS485 driver to be written in user space.
3461 */
3462static int
3463get_lsr_info(struct e100_serial * info, unsigned int *value)
3464{
3465 unsigned int result = TIOCSER_TEMT;
3466#ifndef CONFIG_SVINTO_SIM
3467 unsigned long curr_time = jiffies;
3468 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3469 unsigned long elapsed_usec =
3470 (curr_time - info->last_tx_active) * 1000000/HZ +
3471 curr_time_usec - info->last_tx_active_usec;
3472
3473 if (info->xmit.head != info->xmit.tail ||
3474 elapsed_usec < 2*info->char_time_usec) {
3475 result = 0;
3476 }
3477#endif
3478
3479 if (copy_to_user(value, &result, sizeof(int)))
3480 return -EFAULT;
3481 return 0;
3482}
3483
3484#ifdef SERIAL_DEBUG_IO
3485struct state_str
3486{
3487 int state;
3488 const char *str;
3489};
3490
3491const struct state_str control_state_str[] = {
3492 {TIOCM_DTR, "DTR" },
3493 {TIOCM_RTS, "RTS"},
3494 {TIOCM_ST, "ST?" },
3495 {TIOCM_SR, "SR?" },
3496 {TIOCM_CTS, "CTS" },
3497 {TIOCM_CD, "CD" },
3498 {TIOCM_RI, "RI" },
3499 {TIOCM_DSR, "DSR" },
3500 {0, NULL }
3501};
3502
3503char *get_control_state_str(int MLines, char *s)
3504{
3505 int i = 0;
3506
3507 s[0]='\0';
3508 while (control_state_str[i].str != NULL) {
3509 if (MLines & control_state_str[i].state) {
3510 if (s[0] != '\0') {
3511 strcat(s, ", ");
3512 }
3513 strcat(s, control_state_str[i].str);
3514 }
3515 i++;
3516 }
3517 return s;
3518}
3519#endif
3520
d7283353 3521static int
77accbf5
JN		 3522rs_break(struct tty_struct *tty, int break_state)
3523{
3524 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3525 unsigned long flags;
3526
d7283353
AC		 3527 if (!info->ioport)
3528 return -EIO;
77accbf5
JN		 3529
3530 local_irq_save(flags);
3531 if (break_state == -1) {
3532 /* Go to manual mode and set the txd pin to 0 */
3533 /* Clear bit 7 (txd) and 6 (tr_enable) */
3534 info->tx_ctrl &= 0x3F;
3535 } else {
3536 /* Set bit 7 (txd) and 6 (tr_enable) */
3537 info->tx_ctrl |= (0x80 | 0x40);
3538 }
d7283353 3539 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
77accbf5 3540 local_irq_restore(flags);
d7283353 3541 return 0;
77accbf5
JN		 3542}
3543
1da177e4 3544static int
20b9d177 3545rs_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)
1da177e4 3546{
77accbf5 3547 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
978e595f 3548 unsigned long flags;
1da177e4 3549
978e595f 3550 local_irq_save(flags);
032c17e8 3551
77accbf5
JN		 3552 if (clear & TIOCM_RTS)
3553 e100_rts(info, 0);
3554 if (clear & TIOCM_DTR)
3555 e100_dtr(info, 0);
3556 /* Handle FEMALE behaviour */
3557 if (clear & TIOCM_RI)
3558 e100_ri_out(info, 0);
3559 if (clear & TIOCM_CD)
3560 e100_cd_out(info, 0);
3561
3562 if (set & TIOCM_RTS)
3563 e100_rts(info, 1);
3564 if (set & TIOCM_DTR)
3565 e100_dtr(info, 1);
3566 /* Handle FEMALE behaviour */
3567 if (set & TIOCM_RI)
3568 e100_ri_out(info, 1);
3569 if (set & TIOCM_CD)
3570 e100_cd_out(info, 1);
032c17e8 3571
978e595f 3572 local_irq_restore(flags);
77accbf5
JN		 3573 return 0;
3574}
3575
3576static int
60b33c13 3577rs_tiocmget(struct tty_struct *tty)
77accbf5
JN		 3578{
3579 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3580 unsigned int result;
978e595f
AC		 3581 unsigned long flags;
3582
3583 local_irq_save(flags);
1da177e4
LT		 3584
3585 result =
3586 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3587 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3588 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3589 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3590 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3591 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3592
978e595f 3593 local_irq_restore(flags);
032c17e8 3594
1da177e4 3595#ifdef SERIAL_DEBUG_IO
77accbf5
JN		 3596 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3597 info->line, result, result);
1da177e4
LT		 3598 {
3599 char s[100];
3600
3601 get_control_state_str(result, s);
77accbf5 3602 printk(KERN_DEBUG "state: %s\n", s);
1da177e4
LT		 3603 }
3604#endif
77accbf5 3605 return result;
1da177e4 3606
1da177e4
LT		 3607}
3608
3609
1da177e4 3610static int
6caa76b7 3611rs_ioctl(struct tty_struct *tty,
1da177e4
LT		 3612 unsigned int cmd, unsigned long arg)
3613{
3614 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3615
3616 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3617 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3618 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3619 if (tty->flags & (1 << TTY_IO_ERROR))
3620 return -EIO;
3621 }
3622
3623 switch (cmd) {
77accbf5
JN		 3624 case TIOCGSERIAL:
3625 return get_serial_info(info,
3626 (struct serial_struct *) arg);
3627 case TIOCSSERIAL:
3628 return set_serial_info(info,
3629 (struct serial_struct *) arg);
3630 case TIOCSERGETLSR: /* Get line status register */
3631 return get_lsr_info(info, (unsigned int *) arg);
3632
3633 case TIOCSERGSTRUCT:
3634 if (copy_to_user((struct e100_serial *) arg,
3635 info, sizeof(struct e100_serial)))
3636 return -EFAULT;
3637 return 0;
1da177e4
LT		 3638
3639#if defined(CONFIG_ETRAX_RS485)
77accbf5
JN		 3640 case TIOCSERSETRS485:
3641 {
6fd1af4c
CS		 3642 /* In this ioctl we still use the old structure
3643 * rs485_control for backward compatibility
3644 * (if we use serial_rs485, then old user-level code
3645 * wouldn't work anymore...).
3646 * The use of this ioctl is deprecated: use TIOCSRS485
3647 * instead.*/
77accbf5 3648 struct rs485_control rs485ctrl;
6fd1af4c
CS		 3649 struct serial_rs485 rs485data;
3650 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
77accbf5
JN		 3651 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3652 sizeof(rs485ctrl)))
3653 return -EFAULT;
1da177e4 3654
6fd1af4c
CS		 3655 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3656 rs485data.flags = 0;
c7213fc4 3657
6fd1af4c
CS		 3658 if (rs485ctrl.enabled)
3659 rs485data.flags |= SER_RS485_ENABLED;
3660 else
3661 rs485data.flags &= ~(SER_RS485_ENABLED);
3662
3663 if (rs485ctrl.rts_on_send)
3664 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3665 else
3666 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3667
3668 if (rs485ctrl.rts_after_sent)
3669 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3670 else
3671 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3672
3673 return e100_enable_rs485(tty, &rs485data);
77accbf5 3674 }
1da177e4 3675
6fd1af4c
CS		 3676 case TIOCSRS485:
3677 {
3678 /* This is the new version of TIOCSRS485, with new
3679 * data structure serial_rs485 */
3680 struct serial_rs485 rs485data;
3681 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3682 sizeof(rs485data)))
3683 return -EFAULT;
3684
3685 return e100_enable_rs485(tty, &rs485data);
3686 }
3687
f1d23ed8
CS		 3688 case TIOCGRS485:
3689 {
3690 struct serial_rs485 *rs485data =
3691 &(((struct e100_serial *)tty->driver_data)->rs485);
3692 /* This is the ioctl to get RS485 data from user-space */
3693 if (copy_to_user((struct serial_rs485 *) arg,
3694 rs485data,
94479c01 3695 sizeof(struct serial_rs485)))
f1d23ed8
CS		 3696 return -EFAULT;
3697 break;
3698 }
6fd1af4c 3699
77accbf5
JN		 3700 case TIOCSERWRRS485:
3701 {
3702 struct rs485_write rs485wr;
3703 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3704 sizeof(rs485wr)))
3705 return -EFAULT;
1da177e4 3706
77accbf5
JN		 3707 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3708 }
1da177e4
LT		 3709#endif
3710
77accbf5
JN		 3711 default:
3712 return -ENOIOCTLCMD;
1da177e4
LT		 3713 }
3714 return 0;
3715}
3716
3717static void
606d099c 3718rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 3719{
3720 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3721
1da177e4
LT		 3722 change_speed(info);
3723
3724 /* Handle turning off CRTSCTS */
3725 if ((old_termios->c_cflag & CRTSCTS) &&
ee797069 3726 !(tty->termios.c_cflag & CRTSCTS))
1da177e4 3727 rs_start(tty);
1da177e4
LT		 3728
3729}
3730
1da177e4
LT		 3731/*
3732 * ------------------------------------------------------------
3733 * rs_close()
3734 *
3735 * This routine is called when the serial port gets closed. First, we
3736 * wait for the last remaining data to be sent. Then, we unlink its
3737 * S structure from the interrupt chain if necessary, and we free
3738 * that IRQ if nothing is left in the chain.
3739 * ------------------------------------------------------------
3740 */
3741static void
3742rs_close(struct tty_struct *tty, struct file * filp)
3743{
3744 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3745 unsigned long flags;
3746
3747 if (!info)
3748 return;
3749
3750 /* interrupts are disabled for this entire function */
3751
77accbf5 3752 local_irq_save(flags);
1da177e4
LT		 3753
3754 if (tty_hung_up_p(filp)) {
77accbf5 3755 local_irq_restore(flags);
1da177e4
LT		 3756 return;
3757 }
3758
3759#ifdef SERIAL_DEBUG_OPEN
3760 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3761 info->line, info->count);
3762#endif
3763 if ((tty->count == 1) && (info->count != 1)) {
3764 /*
3765 * Uh, oh. tty->count is 1, which means that the tty
3766 * structure will be freed. Info->count should always
3767 * be one in these conditions. If it's greater than
3768 * one, we've got real problems, since it means the
3769 * serial port won't be shutdown.
3770 */
3d43b7d5 3771 printk(KERN_ERR
1da177e4
LT		 3772 "rs_close: bad serial port count; tty->count is 1, "
3773 "info->count is %d\n", info->count);
3774 info->count = 1;
3775 }
3776 if (--info->count < 0) {
3d43b7d5 3777 printk(KERN_ERR "rs_close: bad serial port count for ttyS%d: %d\n",
1da177e4
LT		 3778 info->line, info->count);
3779 info->count = 0;
3780 }
3781 if (info->count) {
77accbf5 3782 local_irq_restore(flags);
1da177e4
LT		 3783 return;
3784 }
b1d984cf 3785 info->port.flags |= ASYNC_CLOSING;
1da177e4
LT		 3786 /*
3787 * Save the termios structure, since this port may have
3788 * separate termios for callout and dialin.
3789 */
b1d984cf 3790 if (info->port.flags & ASYNC_NORMAL_ACTIVE)
adc8d746 3791 info->normal_termios = tty->termios;
1da177e4
LT		 3792 /*
3793 * Now we wait for the transmit buffer to clear; and we notify
3794 * the line discipline to only process XON/XOFF characters.
3795 */
3796 tty->closing = 1;
892c7cfc
JS		 3797 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE)
3798 tty_wait_until_sent(tty, info->port.closing_wait);
1da177e4
LT		 3799 /*
3800 * At this point we stop accepting input. To do this, we
3801 * disable the serial receiver and the DMA receive interrupt.
3802 */
3803#ifdef SERIAL_HANDLE_EARLY_ERRORS
3804 e100_disable_serial_data_irq(info);
3805#endif
3806
3807#ifndef CONFIG_SVINTO_SIM
3808 e100_disable_rx(info);
3809 e100_disable_rx_irq(info);
3810
b1d984cf 3811 if (info->port.flags & ASYNC_INITIALIZED) {
1da177e4
LT		 3812 /*
3813 * Before we drop DTR, make sure the UART transmitter
3814 * has completely drained; this is especially
3815 * important as we have a transmit FIFO!
3816 */
3817 rs_wait_until_sent(tty, HZ);
3818 }
3819#endif
3820
3821 shutdown(info);
978e595f 3822 rs_flush_buffer(tty);
454aa389 3823 tty_ldisc_flush(tty);
1da177e4
LT		 3824 tty->closing = 0;
3825 info->event = 0;
a88487c7 3826 info->port.tty = NULL;
1da177e4 3827 if (info->blocked_open) {
892c7cfc
JS		 3828 if (info->port.close_delay)
3829 schedule_timeout_interruptible(info->port.close_delay);
4aeaeb0c 3830 wake_up_interruptible(&info->port.open_wait);
1da177e4 3831 }
b1d984cf 3832 info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
4aeaeb0c 3833 wake_up_interruptible(&info->port.close_wait);
77accbf5 3834 local_irq_restore(flags);
1da177e4
LT		 3835
3836 /* port closed */
3837
3838#if defined(CONFIG_ETRAX_RS485)
6fd1af4c
CS		 3839 if (info->rs485.flags & SER_RS485_ENABLED) {
3840 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4
LT		 3841#if defined(CONFIG_ETRAX_RS485_ON_PA)
3842 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3843#endif
3844#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
3845 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3846 rs485_port_g_bit, 0);
3847#endif
3848#if defined(CONFIG_ETRAX_RS485_LTC1387)
3849 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3850 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 0);
3851 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3852 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 0);
3853#endif
3854 }
3855#endif
77accbf5
JN		 3856
3857 /*
3858 * Release any allocated DMA irq's.
3859 */
3860 if (info->dma_in_enabled) {
3861 free_irq(info->dma_in_irq_nbr, info);
3862 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3863 info->uses_dma_in = 0;
3864#ifdef SERIAL_DEBUG_OPEN
3865 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3866 info->dma_in_irq_description);
3867#endif
3868 }
3869 if (info->dma_out_enabled) {
3870 free_irq(info->dma_out_irq_nbr, info);
3871 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3872 info->uses_dma_out = 0;
3873#ifdef SERIAL_DEBUG_OPEN
3874 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3875 info->dma_out_irq_description);
3876#endif
3877 }
1da177e4
LT		 3878}
3879
3880/*
3881 * rs_wait_until_sent() --- wait until the transmitter is empty
3882 */
3883static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3884{
3885 unsigned long orig_jiffies;
3886 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3887 unsigned long curr_time = jiffies;
3888 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3889 long elapsed_usec =
3890 (curr_time - info->last_tx_active) * (1000000/HZ) +
3891 curr_time_usec - info->last_tx_active_usec;
3892
3893 /*
3894 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3895 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3896 */
3897 orig_jiffies = jiffies;
3898 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3899 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3900 (elapsed_usec < 2*info->char_time_usec)) {
3c76bc5b 3901 schedule_timeout_interruptible(1);
1da177e4
LT		 3902 if (signal_pending(current))
3903 break;
3904 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3905 break;
3906 curr_time = jiffies;
3907 curr_time_usec = GET_JIFFIES_USEC();
3908 elapsed_usec =
3909 (curr_time - info->last_tx_active) * (1000000/HZ) +
3910 curr_time_usec - info->last_tx_active_usec;
3911 }
3912 set_current_state(TASK_RUNNING);
3913}
3914
3915/*
3916 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3917 */
3918void
3919rs_hangup(struct tty_struct *tty)
3920{
3921 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3922
3923 rs_flush_buffer(tty);
3924 shutdown(info);
3925 info->event = 0;
3926 info->count = 0;
b1d984cf 3927 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
a88487c7 3928 info->port.tty = NULL;
4aeaeb0c 3929 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 3930}
3931
3932/*
3933 * ------------------------------------------------------------
3934 * rs_open() and friends
3935 * ------------------------------------------------------------
3936 */
3937static int
3938block_til_ready(struct tty_struct *tty, struct file * filp,
3939 struct e100_serial *info)
3940{
3941 DECLARE_WAITQUEUE(wait, current);
3942 unsigned long flags;
3943 int retval;
3944 int do_clocal = 0, extra_count = 0;
3945
3946 /*
3947 * If the device is in the middle of being closed, then block
3948 * until it's done, and then try again.
3949 */
3950 if (tty_hung_up_p(filp) ||
b1d984cf 3951 (info->port.flags & ASYNC_CLOSING)) {
4aeaeb0c 3952 wait_event_interruptible_tty(tty, info->port.close_wait,
b1d984cf 3953 !(info->port.flags & ASYNC_CLOSING));
1da177e4 3954#ifdef SERIAL_DO_RESTART
b1d984cf 3955 if (info->port.flags & ASYNC_HUP_NOTIFY)
1da177e4
LT		 3956 return -EAGAIN;
3957 else
3958 return -ERESTARTSYS;
3959#else
3960 return -EAGAIN;
3961#endif
3962 }
3963
3964 /*
3965 * If non-blocking mode is set, or the port is not enabled,
3966 * then make the check up front and then exit.
3967 */
3968 if ((filp->f_flags & O_NONBLOCK) ||
3969 (tty->flags & (1 << TTY_IO_ERROR))) {
b1d984cf 3970 info->port.flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 3971 return 0;
3972 }
3973
adc8d746 3974 if (tty->termios.c_cflag & CLOCAL) {
1da177e4
LT		 3975 do_clocal = 1;
3976 }
3977
3978 /*
3979 * Block waiting for the carrier detect and the line to become
3980 * free (i.e., not in use by the callout). While we are in
3981 * this loop, info->count is dropped by one, so that
3982 * rs_close() knows when to free things. We restore it upon
3983 * exit, either normal or abnormal.
3984 */
3985 retval = 0;
4aeaeb0c 3986 add_wait_queue(&info->port.open_wait, &wait);
1da177e4
LT		 3987#ifdef SERIAL_DEBUG_OPEN
3988 printk("block_til_ready before block: ttyS%d, count = %d\n",
3989 info->line, info->count);
3990#endif
77accbf5 3991 local_irq_save(flags);
1da177e4
LT		 3992 if (!tty_hung_up_p(filp)) {
3993 extra_count++;
3994 info->count--;
3995 }
77accbf5 3996 local_irq_restore(flags);
1da177e4
LT		 3997 info->blocked_open++;
3998 while (1) {
77accbf5 3999 local_irq_save(flags);
1da177e4
LT		 4000 /* assert RTS and DTR */
4001 e100_rts(info, 1);
4002 e100_dtr(info, 1);
77accbf5 4003 local_irq_restore(flags);
1da177e4
LT		 4004 set_current_state(TASK_INTERRUPTIBLE);
4005 if (tty_hung_up_p(filp) ||
b1d984cf 4006 !(info->port.flags & ASYNC_INITIALIZED)) {
1da177e4 4007#ifdef SERIAL_DO_RESTART
b1d984cf 4008 if (info->port.flags & ASYNC_HUP_NOTIFY)
1da177e4
LT		 4009 retval = -EAGAIN;
4010 else
4011 retval = -ERESTARTSYS;
4012#else
4013 retval = -EAGAIN;
4014#endif
4015 break;
4016 }
b1d984cf 4017 if (!(info->port.flags & ASYNC_CLOSING) && do_clocal)
1da177e4
LT		 4018 /* && (do_clocal || DCD_IS_ASSERTED) */
4019 break;
4020 if (signal_pending(current)) {
4021 retval = -ERESTARTSYS;
4022 break;
4023 }
4024#ifdef SERIAL_DEBUG_OPEN
4025 printk("block_til_ready blocking: ttyS%d, count = %d\n",
4026 info->line, info->count);
4027#endif
89c8d91e 4028 tty_unlock(tty);
1da177e4 4029 schedule();
89c8d91e 4030 tty_lock(tty);
1da177e4
LT		 4031 }
4032 set_current_state(TASK_RUNNING);
4aeaeb0c 4033 remove_wait_queue(&info->port.open_wait, &wait);
1da177e4
LT		 4034 if (extra_count)
4035 info->count++;
4036 info->blocked_open--;
4037#ifdef SERIAL_DEBUG_OPEN
4038 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
4039 info->line, info->count);
4040#endif
4041 if (retval)
4042 return retval;
b1d984cf 4043 info->port.flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 4044 return 0;
4045}
4046
77accbf5
JN		 4047static void
4048deinit_port(struct e100_serial *info)
4049{
4050 if (info->dma_out_enabled) {
4051 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
4052 free_irq(info->dma_out_irq_nbr, info);
4053 }
4054 if (info->dma_in_enabled) {
4055 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
4056 free_irq(info->dma_in_irq_nbr, info);
4057 }
4058}
4059
1da177e4
LT		 4060/*
4061 * This routine is called whenever a serial port is opened.
4062 * It performs the serial-specific initialization for the tty structure.
4063 */
4064static int
4065rs_open(struct tty_struct *tty, struct file * filp)
4066{
4067 struct e100_serial *info;
410235fd 4068 int retval;
77accbf5 4069 int allocated_resources = 0;
1da177e4 4070
410235fd 4071 info = rs_table + tty->index;
1da177e4
LT		 4072 if (!info->enabled)
4073 return -ENODEV;
4074
4075#ifdef SERIAL_DEBUG_OPEN
4076 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
4077 info->count);
4078#endif
4079
4080 info->count++;
4081 tty->driver_data = info;
a88487c7 4082 info->port.tty = tty;
1da177e4 4083
b1d984cf 4084 info->port.low_latency = !!(info->port.flags & ASYNC_LOW_LATENCY);
1da177e4 4085
1da177e4
LT		 4086 /*
4087 * If the port is in the middle of closing, bail out now
4088 */
4089 if (tty_hung_up_p(filp) ||
b1d984cf 4090 (info->port.flags & ASYNC_CLOSING)) {
4aeaeb0c 4091 wait_event_interruptible_tty(tty, info->port.close_wait,
b1d984cf 4092 !(info->port.flags & ASYNC_CLOSING));
1da177e4 4093#ifdef SERIAL_DO_RESTART
b1d984cf 4094 return ((info->port.flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 4095 -EAGAIN : -ERESTARTSYS);
4096#else
4097 return -EAGAIN;
4098#endif
4099 }
4100
77accbf5
JN		 4101 /*
4102 * If DMA is enabled try to allocate the irq's.
4103 */
4104 if (info->count == 1) {
4105 allocated_resources = 1;
4106 if (info->dma_in_enabled) {
4107 if (request_irq(info->dma_in_irq_nbr,
4108 rec_interrupt,
4109 info->dma_in_irq_flags,
4110 info->dma_in_irq_description,
4111 info)) {
4112 printk(KERN_WARNING "DMA irq '%s' busy; "
4113 "falling back to non-DMA mode\n",
4114 info->dma_in_irq_description);
4115 /* Make sure we never try to use DMA in */
4116 /* for the port again. */
4117 info->dma_in_enabled = 0;
4118 } else if (cris_request_dma(info->dma_in_nbr,
4119 info->dma_in_irq_description,
4120 DMA_VERBOSE_ON_ERROR,
4121 info->dma_owner)) {
4122 free_irq(info->dma_in_irq_nbr, info);
4123 printk(KERN_WARNING "DMA '%s' busy; "
4124 "falling back to non-DMA mode\n",
4125 info->dma_in_irq_description);
4126 /* Make sure we never try to use DMA in */
4127 /* for the port again. */
4128 info->dma_in_enabled = 0;
4129 }
4130#ifdef SERIAL_DEBUG_OPEN
4131 else
4132 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4133 info->dma_in_irq_description);
4134#endif
4135 }
4136 if (info->dma_out_enabled) {
4137 if (request_irq(info->dma_out_irq_nbr,
4138 tr_interrupt,
4139 info->dma_out_irq_flags,
4140 info->dma_out_irq_description,
4141 info)) {
4142 printk(KERN_WARNING "DMA irq '%s' busy; "
4143 "falling back to non-DMA mode\n",
4144 info->dma_out_irq_description);
4145 /* Make sure we never try to use DMA out */
4146 /* for the port again. */
4147 info->dma_out_enabled = 0;
4148 } else if (cris_request_dma(info->dma_out_nbr,
4149 info->dma_out_irq_description,
4150 DMA_VERBOSE_ON_ERROR,
4151 info->dma_owner)) {
4152 free_irq(info->dma_out_irq_nbr, info);
4153 printk(KERN_WARNING "DMA '%s' busy; "
4154 "falling back to non-DMA mode\n",
4155 info->dma_out_irq_description);
4156 /* Make sure we never try to use DMA out */
4157 /* for the port again. */
4158 info->dma_out_enabled = 0;
4159 }
4160#ifdef SERIAL_DEBUG_OPEN
4161 else
4162 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4163 info->dma_out_irq_description);
4164#endif
4165 }
4166 }
4167
1da177e4
LT		 4168 /*
4169 * Start up the serial port
4170 */
4171
4172 retval = startup(info);
77accbf5
JN		 4173 if (retval) {
4174 if (allocated_resources)
4175 deinit_port(info);
4176
4177 /* FIXME Decrease count info->count here too? */
1da177e4 4178 return retval;
77accbf5
JN		 4179 }
4180
1da177e4
LT		 4181
4182 retval = block_til_ready(tty, filp, info);
4183 if (retval) {
4184#ifdef SERIAL_DEBUG_OPEN
4185 printk("rs_open returning after block_til_ready with %d\n",
4186 retval);
4187#endif
77accbf5
JN		 4188 if (allocated_resources)
4189 deinit_port(info);
4190
1da177e4
LT		 4191 return retval;
4192 }
4193
b1d984cf 4194 if ((info->count == 1) && (info->port.flags & ASYNC_SPLIT_TERMIOS)) {
adc8d746 4195 tty->termios = info->normal_termios;
1da177e4
LT		 4196 change_speed(info);
4197 }
4198
4199#ifdef SERIAL_DEBUG_OPEN
4200 printk("rs_open ttyS%d successful...\n", info->line);
4201#endif
4202 DLOG_INT_TRIG( log_int_pos = 0);
4203
4204 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
4205 info->icount.rx = 0;
4206 } );
4207
4208 return 0;
4209}
4210
9e040a3e 4211#ifdef CONFIG_PROC_FS
1da177e4
LT		 4212/*
4213 * /proc fs routines....
4214 */
4215
9e040a3e 4216static void seq_line_info(struct seq_file *m, struct e100_serial *info)
1da177e4 4217{
1da177e4
LT		 4218 unsigned long tmp;
4219
9e040a3e
JN		 4220 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
4221 info->line, (unsigned long)info->ioport, info->irq);
1da177e4 4222
d7283353 4223 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
9e040a3e
JN		 4224 seq_printf(m, "\n");
4225 return;
1da177e4
LT		 4226 }
4227
9e040a3e
JN		 4228 seq_printf(m, " baud:%d", info->baud);
4229 seq_printf(m, " tx:%lu rx:%lu",
1da177e4
LT		 4230 (unsigned long)info->icount.tx,
4231 (unsigned long)info->icount.rx);
4232 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
9e040a3e
JN		 4233 if (tmp)
4234 seq_printf(m, " tx_pend:%lu/%lu",
4235 (unsigned long)tmp,
4236 (unsigned long)SERIAL_XMIT_SIZE);
1da177e4 4237
9e040a3e
JN		 4238 seq_printf(m, " rx_pend:%lu/%lu",
4239 (unsigned long)info->recv_cnt,
4240 (unsigned long)info->max_recv_cnt);
1da177e4
LT		 4241
4242#if 1
a88487c7 4243 if (info->port.tty) {
a88487c7 4244 if (info->port.tty->stopped)
9e040a3e
JN		 4245 seq_printf(m, " stopped:%i",
4246 (int)info->port.tty->stopped);
1da177e4
LT		 4247 }
4248
4249 {
d7283353 4250 unsigned char rstat = info->ioport[REG_STATUS];
9e040a3e
JN		 4251 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4252 seq_printf(m, " xoff_detect:1");
1da177e4
LT		 4253 }
4254
4255#endif
4256
1da177e4 4257 if (info->icount.frame)
9e040a3e 4258 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
1da177e4
LT		 4259
4260 if (info->icount.parity)
9e040a3e 4261 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
1da177e4
LT		 4262
4263 if (info->icount.brk)
9e040a3e 4264 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
1da177e4
LT		 4265
4266 if (info->icount.overrun)
9e040a3e 4267 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
1da177e4
LT		 4268
4269 /*
4270 * Last thing is the RS-232 status lines
4271 */
9e040a3e
JN		 4272 if (!E100_RTS_GET(info))
4273 seq_puts(m, "|RTS");
4274 if (!E100_CTS_GET(info))
4275 seq_puts(m, "|CTS");
4276 if (!E100_DTR_GET(info))
4277 seq_puts(m, "|DTR");
4278 if (!E100_DSR_GET(info))
4279 seq_puts(m, "|DSR");
4280 if (!E100_CD_GET(info))
4281 seq_puts(m, "|CD");
4282 if (!E100_RI_GET(info))
4283 seq_puts(m, "|RI");
4284 seq_puts(m, "\n");
1da177e4
LT		 4285}
4286
9e040a3e
JN		 4287
4288static int crisv10_proc_show(struct seq_file *m, void *v)
1da177e4 4289{
9e040a3e 4290 int i;
1da177e4 4291
9e040a3e
JN		 4292 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4293
4294 for (i = 0; i < NR_PORTS; i++) {
1da177e4
LT		 4295 if (!rs_table[i].enabled)
4296 continue;
9e040a3e 4297 seq_line_info(m, &rs_table[i]);
1da177e4
LT		 4298 }
4299#ifdef DEBUG_LOG_INCLUDED
4300 for (i = 0; i < debug_log_pos; i++) {
9e040a3e
JN		 4301 seq_printf(m, "%-4i %lu.%lu ",
4302 i, debug_log[i].time,
4303 timer_data_to_ns(debug_log[i].timer_data));
4304 seq_printf(m, debug_log[i].string, debug_log[i].value);
1da177e4 4305 }
9e040a3e 4306 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
1da177e4
LT		 4307 debug_log_pos = 0;
4308#endif
9e040a3e
JN		 4309 return 0;
4310}
1da177e4 4311
9e040a3e
JN		 4312static int crisv10_proc_open(struct inode *inode, struct file *file)
4313{
4314 return single_open(file, crisv10_proc_show, NULL);
1da177e4
LT		 4315}
4316
9e040a3e
JN		 4317static const struct file_operations crisv10_proc_fops = {
4318 .owner = THIS_MODULE,
4319 .open = crisv10_proc_open,
4320 .read = seq_read,
4321 .llseek = seq_lseek,
4322 .release = single_release,
4323};
4324#endif
4325
4326
1da177e4
LT		 4327/* Finally, routines used to initialize the serial driver. */
4328
9e040a3e 4329static void show_serial_version(void)
1da177e4
LT		 4330{
4331 printk(KERN_INFO
9e040a3e
JN		 4332 "ETRAX 100LX serial-driver %s, "
4333 "(c) 2000-2004 Axis Communications AB\r\n",
1da177e4
LT		 4334 &serial_version[11]); /* "$Revision: x.yy" */
4335}
4336
4337/* rs_init inits the driver at boot (using the module_init chain) */
4338
b68e31d0 4339static const struct tty_operations rs_ops = {
1da177e4
LT		 4340 .open = rs_open,
4341 .close = rs_close,
4342 .write = rs_write,
4343 .flush_chars = rs_flush_chars,
4344 .write_room = rs_write_room,
4345 .chars_in_buffer = rs_chars_in_buffer,
4346 .flush_buffer = rs_flush_buffer,
4347 .ioctl = rs_ioctl,
4348 .throttle = rs_throttle,
4349 .unthrottle = rs_unthrottle,
4350 .set_termios = rs_set_termios,
4351 .stop = rs_stop,
4352 .start = rs_start,
4353 .hangup = rs_hangup,
4354 .break_ctl = rs_break,
4355 .send_xchar = rs_send_xchar,
4356 .wait_until_sent = rs_wait_until_sent,
77accbf5 4357 .tiocmget = rs_tiocmget,
9e040a3e
JN		 4358 .tiocmset = rs_tiocmset,
4359#ifdef CONFIG_PROC_FS
4360 .proc_fops = &crisv10_proc_fops,
4361#endif
1da177e4
LT		 4362};
4363
9e040a3e 4364static int __init rs_init(void)
1da177e4
LT		 4365{
4366 int i;
4367 struct e100_serial *info;
4368 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4369
4370 if (!driver)
4371 return -ENOMEM;
4372
4373 show_serial_version();
4374
4375 /* Setup the timed flush handler system */
4376
4377#if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
77accbf5
JN		 4378 setup_timer(&flush_timer, timed_flush_handler, 0);
4379 mod_timer(&flush_timer, jiffies + 5);
4380#endif
4381
4382#if defined(CONFIG_ETRAX_RS485)
4383#if defined(CONFIG_ETRAX_RS485_ON_PA)
2f7861de 4384 if (cris_io_interface_allocate_pins(if_serial_0, 'a', rs485_pa_bit,
77accbf5 4385 rs485_pa_bit)) {
3d43b7d5 4386 printk(KERN_ERR "ETRAX100LX serial: Could not allocate "
77accbf5 4387 "RS485 pin\n");
41ca7322 4388 put_tty_driver(driver);
77accbf5
JN		 4389 return -EBUSY;
4390 }
4391#endif
4392#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
2f7861de 4393 if (cris_io_interface_allocate_pins(if_serial_0, 'g', rs485_pa_bit,
77accbf5 4394 rs485_port_g_bit)) {
3d43b7d5 4395 printk(KERN_ERR "ETRAX100LX serial: Could not allocate "
77accbf5 4396 "RS485 pin\n");
41ca7322 4397 put_tty_driver(driver);
77accbf5
JN		 4398 return -EBUSY;
4399 }
4400#endif
1da177e4
LT		 4401#endif
4402
4403 /* Initialize the tty_driver structure */
4404
4405 driver->driver_name = "serial";
4406 driver->name = "ttyS";
4407 driver->major = TTY_MAJOR;
4408 driver->minor_start = 64;
4409 driver->type = TTY_DRIVER_TYPE_SERIAL;
4410 driver->subtype = SERIAL_TYPE_NORMAL;
4411 driver->init_termios = tty_std_termios;
4412 driver->init_termios.c_cflag =
4413 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
606d099c
AC		 4414 driver->init_termios.c_ispeed = 115200;
4415 driver->init_termios.c_ospeed = 115200;
c4d6ebeb 4416 driver->flags = TTY_DRIVER_REAL_RAW;
1da177e4
LT		 4417
4418 tty_set_operations(driver, &rs_ops);
4419 serial_driver = driver;
1da177e4 4420
b19e2ca7 4421 /* do some initializing for the separate ports */
1da177e4 4422 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
77accbf5
JN		 4423 if (info->enabled) {
4424 if (cris_request_io_interface(info->io_if,
4425 info->io_if_description)) {
3d43b7d5 4426 printk(KERN_ERR "ETRAX100LX async serial: "
77accbf5
JN		 4427 "Could not allocate IO pins for "
4428 "%s, port %d\n",
4429 info->io_if_description, i);
4430 info->enabled = 0;
4431 }
4432 }
953756e2 4433 tty_port_init(&info->port);
1da177e4
LT		 4434 info->uses_dma_in = 0;
4435 info->uses_dma_out = 0;
4436 info->line = i;
a88487c7 4437 info->port.tty = NULL;
1da177e4
LT		 4438 info->type = PORT_ETRAX;
4439 info->tr_running = 0;
4440 info->forced_eop = 0;
4441 info->baud_base = DEF_BAUD_BASE;
4442 info->custom_divisor = 0;
1da177e4
LT		 4443 info->x_char = 0;
4444 info->event = 0;
4445 info->count = 0;
4446 info->blocked_open = 0;
4447 info->normal_termios = driver->init_termios;
1da177e4
LT		 4448 info->xmit.buf = NULL;
4449 info->xmit.tail = info->xmit.head = 0;
4450 info->first_recv_buffer = info->last_recv_buffer = NULL;
4451 info->recv_cnt = info->max_recv_cnt = 0;
4452 info->last_tx_active_usec = 0;
4453 info->last_tx_active = 0;
4454
4455#if defined(CONFIG_ETRAX_RS485)
4456 /* Set sane defaults */
6fd1af4c
CS		 4457 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4458 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
1da177e4 4459 info->rs485.delay_rts_before_send = 0;
6fd1af4c 4460 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4 4461#endif
77accbf5 4462 INIT_WORK(&info->work, do_softint);
1da177e4
LT		 4463
4464 if (info->enabled) {
078dee2d
KV		 4465 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n",
4466 serial_driver->name, info->line, info->ioport);
1da177e4 4467 }
b19e2ca7 4468 tty_port_link_device(&info->port, driver, i);
1da177e4 4469 }
b19e2ca7
JS		 4470
4471 if (tty_register_driver(driver))
4472 panic("Couldn't register serial driver\n");
4473
1da177e4
LT		 4474#ifdef CONFIG_ETRAX_FAST_TIMER
4475#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4476 memset(fast_timers, 0, sizeof(fast_timers));
4477#endif
4478#ifdef CONFIG_ETRAX_RS485
4479 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4480#endif
4481 fast_timer_init();
4482#endif
4483
4484#ifndef CONFIG_SVINTO_SIM
77accbf5 4485#ifndef CONFIG_ETRAX_KGDB
1da177e4
LT		 4486 /* Not needed in simulator. May only complicate stuff. */
4487 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4488
77accbf5 4489 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
9cfb5c05 4490 IRQF_SHARED, "serial ", driver))
71cc2c21 4491 panic("%s: Failed to request irq8", __func__);
1da177e4 4492
1da177e4
LT		 4493#endif
4494#endif /* CONFIG_SVINTO_SIM */
77accbf5 4495
1da177e4
LT		 4496 return 0;
4497}
4498
4499/* this makes sure that rs_init is called during kernel boot */
4500
4501module_init(rs_init);
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