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Merge tag 'linux-kselftest-4.13-rc6-fixes' of git://git.kernel.org/pub/scm/linux...
[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / fsl_lpuart.c
CommitLineData
c9e2e946
JL		 1/*
2 * Freescale lpuart serial port driver
3 *
380c966c 4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
c9e2e946
JL		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
f1cd8c87
YY		 16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/dmaengine.h>
20#include <linux/dmapool.h>
c9e2e946
JL		 21#include <linux/io.h>
22#include <linux/irq.h>
f1cd8c87 23#include <linux/module.h>
c9e2e946
JL		 24#include <linux/of.h>
25#include <linux/of_device.h>
f1cd8c87 26#include <linux/of_dma.h>
c9e2e946 27#include <linux/serial_core.h>
f1cd8c87 28#include <linux/slab.h>
c9e2e946
JL		 29#include <linux/tty_flip.h>
30
31/* All registers are 8-bit width */
32#define UARTBDH 0x00
33#define UARTBDL 0x01
34#define UARTCR1 0x02
35#define UARTCR2 0x03
36#define UARTSR1 0x04
37#define UARTCR3 0x06
38#define UARTDR 0x07
39#define UARTCR4 0x0a
40#define UARTCR5 0x0b
41#define UARTMODEM 0x0d
42#define UARTPFIFO 0x10
43#define UARTCFIFO 0x11
44#define UARTSFIFO 0x12
45#define UARTTWFIFO 0x13
46#define UARTTCFIFO 0x14
47#define UARTRWFIFO 0x15
48
49#define UARTBDH_LBKDIE 0x80
50#define UARTBDH_RXEDGIE 0x40
51#define UARTBDH_SBR_MASK 0x1f
52
53#define UARTCR1_LOOPS 0x80
54#define UARTCR1_RSRC 0x20
55#define UARTCR1_M 0x10
56#define UARTCR1_WAKE 0x08
57#define UARTCR1_ILT 0x04
58#define UARTCR1_PE 0x02
59#define UARTCR1_PT 0x01
60
61#define UARTCR2_TIE 0x80
62#define UARTCR2_TCIE 0x40
63#define UARTCR2_RIE 0x20
64#define UARTCR2_ILIE 0x10
65#define UARTCR2_TE 0x08
66#define UARTCR2_RE 0x04
67#define UARTCR2_RWU 0x02
68#define UARTCR2_SBK 0x01
69
70#define UARTSR1_TDRE 0x80
71#define UARTSR1_TC 0x40
72#define UARTSR1_RDRF 0x20
73#define UARTSR1_IDLE 0x10
74#define UARTSR1_OR 0x08
75#define UARTSR1_NF 0x04
76#define UARTSR1_FE 0x02
77#define UARTSR1_PE 0x01
78
79#define UARTCR3_R8 0x80
80#define UARTCR3_T8 0x40
81#define UARTCR3_TXDIR 0x20
82#define UARTCR3_TXINV 0x10
83#define UARTCR3_ORIE 0x08
84#define UARTCR3_NEIE 0x04
85#define UARTCR3_FEIE 0x02
86#define UARTCR3_PEIE 0x01
87
88#define UARTCR4_MAEN1 0x80
89#define UARTCR4_MAEN2 0x40
90#define UARTCR4_M10 0x20
91#define UARTCR4_BRFA_MASK 0x1f
92#define UARTCR4_BRFA_OFF 0
93
94#define UARTCR5_TDMAS 0x80
95#define UARTCR5_RDMAS 0x20
96
97#define UARTMODEM_RXRTSE 0x08
98#define UARTMODEM_TXRTSPOL 0x04
99#define UARTMODEM_TXRTSE 0x02
100#define UARTMODEM_TXCTSE 0x01
101
102#define UARTPFIFO_TXFE 0x80
103#define UARTPFIFO_FIFOSIZE_MASK 0x7
104#define UARTPFIFO_TXSIZE_OFF 4
105#define UARTPFIFO_RXFE 0x08
106#define UARTPFIFO_RXSIZE_OFF 0
107
108#define UARTCFIFO_TXFLUSH 0x80
109#define UARTCFIFO_RXFLUSH 0x40
110#define UARTCFIFO_RXOFE 0x04
111#define UARTCFIFO_TXOFE 0x02
112#define UARTCFIFO_RXUFE 0x01
113
114#define UARTSFIFO_TXEMPT 0x80
115#define UARTSFIFO_RXEMPT 0x40
116#define UARTSFIFO_RXOF 0x04
117#define UARTSFIFO_TXOF 0x02
118#define UARTSFIFO_RXUF 0x01
119
380c966c
JL		 120/* 32-bit register defination */
121#define UARTBAUD 0x00
122#define UARTSTAT 0x04
123#define UARTCTRL 0x08
124#define UARTDATA 0x0C
125#define UARTMATCH 0x10
126#define UARTMODIR 0x14
127#define UARTFIFO 0x18
128#define UARTWATER 0x1c
129
130#define UARTBAUD_MAEN1 0x80000000
131#define UARTBAUD_MAEN2 0x40000000
132#define UARTBAUD_M10 0x20000000
133#define UARTBAUD_TDMAE 0x00800000
134#define UARTBAUD_RDMAE 0x00200000
135#define UARTBAUD_MATCFG 0x00400000
136#define UARTBAUD_BOTHEDGE 0x00020000
137#define UARTBAUD_RESYNCDIS 0x00010000
138#define UARTBAUD_LBKDIE 0x00008000
139#define UARTBAUD_RXEDGIE 0x00004000
140#define UARTBAUD_SBNS 0x00002000
141#define UARTBAUD_SBR 0x00000000
142#define UARTBAUD_SBR_MASK 0x1fff
a6d7514b
DA		 143#define UARTBAUD_OSR_MASK 0x1f
144#define UARTBAUD_OSR_SHIFT 24
380c966c
JL		 145
146#define UARTSTAT_LBKDIF 0x80000000
147#define UARTSTAT_RXEDGIF 0x40000000
148#define UARTSTAT_MSBF 0x20000000
149#define UARTSTAT_RXINV 0x10000000
150#define UARTSTAT_RWUID 0x08000000
151#define UARTSTAT_BRK13 0x04000000
152#define UARTSTAT_LBKDE 0x02000000
153#define UARTSTAT_RAF 0x01000000
154#define UARTSTAT_TDRE 0x00800000
155#define UARTSTAT_TC 0x00400000
156#define UARTSTAT_RDRF 0x00200000
157#define UARTSTAT_IDLE 0x00100000
158#define UARTSTAT_OR 0x00080000
159#define UARTSTAT_NF 0x00040000
160#define UARTSTAT_FE 0x00020000
161#define UARTSTAT_PE 0x00010000
162#define UARTSTAT_MA1F 0x00008000
163#define UARTSTAT_M21F 0x00004000
164
165#define UARTCTRL_R8T9 0x80000000
166#define UARTCTRL_R9T8 0x40000000
167#define UARTCTRL_TXDIR 0x20000000
168#define UARTCTRL_TXINV 0x10000000
169#define UARTCTRL_ORIE 0x08000000
170#define UARTCTRL_NEIE 0x04000000
171#define UARTCTRL_FEIE 0x02000000
172#define UARTCTRL_PEIE 0x01000000
173#define UARTCTRL_TIE 0x00800000
174#define UARTCTRL_TCIE 0x00400000
175#define UARTCTRL_RIE 0x00200000
176#define UARTCTRL_ILIE 0x00100000
177#define UARTCTRL_TE 0x00080000
178#define UARTCTRL_RE 0x00040000
179#define UARTCTRL_RWU 0x00020000
180#define UARTCTRL_SBK 0x00010000
181#define UARTCTRL_MA1IE 0x00008000
182#define UARTCTRL_MA2IE 0x00004000
183#define UARTCTRL_IDLECFG 0x00000100
184#define UARTCTRL_LOOPS 0x00000080
185#define UARTCTRL_DOZEEN 0x00000040
186#define UARTCTRL_RSRC 0x00000020
187#define UARTCTRL_M 0x00000010
188#define UARTCTRL_WAKE 0x00000008
189#define UARTCTRL_ILT 0x00000004
190#define UARTCTRL_PE 0x00000002
191#define UARTCTRL_PT 0x00000001
192
193#define UARTDATA_NOISY 0x00008000
194#define UARTDATA_PARITYE 0x00004000
195#define UARTDATA_FRETSC 0x00002000
196#define UARTDATA_RXEMPT 0x00001000
197#define UARTDATA_IDLINE 0x00000800
198#define UARTDATA_MASK 0x3ff
199
200#define UARTMODIR_IREN 0x00020000
201#define UARTMODIR_TXCTSSRC 0x00000020
202#define UARTMODIR_TXCTSC 0x00000010
203#define UARTMODIR_RXRTSE 0x00000008
204#define UARTMODIR_TXRTSPOL 0x00000004
205#define UARTMODIR_TXRTSE 0x00000002
206#define UARTMODIR_TXCTSE 0x00000001
207
208#define UARTFIFO_TXEMPT 0x00800000
209#define UARTFIFO_RXEMPT 0x00400000
210#define UARTFIFO_TXOF 0x00020000
211#define UARTFIFO_RXUF 0x00010000
212#define UARTFIFO_TXFLUSH 0x00008000
213#define UARTFIFO_RXFLUSH 0x00004000
214#define UARTFIFO_TXOFE 0x00000200
215#define UARTFIFO_RXUFE 0x00000100
216#define UARTFIFO_TXFE 0x00000080
217#define UARTFIFO_FIFOSIZE_MASK 0x7
218#define UARTFIFO_TXSIZE_OFF 4
219#define UARTFIFO_RXFE 0x00000008
220#define UARTFIFO_RXSIZE_OFF 0
221
222#define UARTWATER_COUNT_MASK 0xff
223#define UARTWATER_TXCNT_OFF 8
224#define UARTWATER_RXCNT_OFF 24
225#define UARTWATER_WATER_MASK 0xff
226#define UARTWATER_TXWATER_OFF 0
227#define UARTWATER_RXWATER_OFF 16
228
5887ad43
BD		 229/* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
230#define DMA_RX_TIMEOUT (10)
f1cd8c87 231
c9e2e946
JL		 232#define DRIVER_NAME "fsl-lpuart"
233#define DEV_NAME "ttyLP"
234#define UART_NR 6
235
24b1e5f0
DA		 236/* IMX lpuart has four extra unused regs located at the beginning */
237#define IMX_REG_OFF 0x10
238
c9e2e946
JL		 239struct lpuart_port {
240 struct uart_port port;
241 struct clk *clk;
242 unsigned int txfifo_size;
243 unsigned int rxfifo_size;
f1cd8c87 244
4a818c43
SA		 245 bool lpuart_dma_tx_use;
246 bool lpuart_dma_rx_use;
f1cd8c87
YY		 247 struct dma_chan *dma_tx_chan;
248 struct dma_chan *dma_rx_chan;
249 struct dma_async_tx_descriptor *dma_tx_desc;
250 struct dma_async_tx_descriptor *dma_rx_desc;
f1cd8c87
YY		 251 dma_cookie_t dma_tx_cookie;
252 dma_cookie_t dma_rx_cookie;
f1cd8c87
YY		 253 unsigned int dma_tx_bytes;
254 unsigned int dma_rx_bytes;
6250cc30 255 bool dma_tx_in_progress;
f1cd8c87
YY		 256 unsigned int dma_rx_timeout;
257 struct timer_list lpuart_timer;
6250cc30 258 struct scatterlist rx_sgl, tx_sgl[2];
5887ad43
BD		 259 struct circ_buf rx_ring;
260 int rx_dma_rng_buf_len;
6250cc30
BD		 261 unsigned int dma_tx_nents;
262 wait_queue_head_t dma_wait;
c9e2e946
JL		 263};
264
0d6fce90
DA		 265struct lpuart_soc_data {
266 char iotype;
24b1e5f0 267 u8 reg_off;
0d6fce90
DA		 268};
269
270static const struct lpuart_soc_data vf_data = {
271 .iotype = UPIO_MEM,
272};
273
274static const struct lpuart_soc_data ls_data = {
275 .iotype = UPIO_MEM32BE,
276};
277
24b1e5f0
DA		 278static struct lpuart_soc_data imx_data = {
279 .iotype = UPIO_MEM32,
280 .reg_off = IMX_REG_OFF,
281};
282
ed0bb232 283static const struct of_device_id lpuart_dt_ids[] = {
0d6fce90
DA		 284 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
285 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, },
24b1e5f0 286 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx_data, },
c9e2e946
JL		 287 { /* sentinel */ }
288};
289MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
290
f1cd8c87
YY		 291/* Forward declare this for the dma callbacks*/
292static void lpuart_dma_tx_complete(void *arg);
f1cd8c87 293
f98e1fcd
DA		 294static inline u32 lpuart32_read(struct uart_port *port, u32 off)
295{
296 switch (port->iotype) {
297 case UPIO_MEM32:
298 return readl(port->membase + off);
299 case UPIO_MEM32BE:
300 return ioread32be(port->membase + off);
301 default:
302 return 0;
303 }
380c966c
JL		 304}
305
a0204f25 306static inline void lpuart32_write(struct uart_port *port, u32 val,
f98e1fcd
DA		 307 u32 off)
308{
309 switch (port->iotype) {
310 case UPIO_MEM32:
311 writel(val, port->membase + off);
312 break;
313 case UPIO_MEM32BE:
314 iowrite32be(val, port->membase + off);
315 break;
316 }
380c966c
JL		 317}
318
c9e2e946
JL		 319static void lpuart_stop_tx(struct uart_port *port)
320{
321 unsigned char temp;
322
323 temp = readb(port->membase + UARTCR2);
324 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
325 writeb(temp, port->membase + UARTCR2);
326}
327
380c966c
JL		 328static void lpuart32_stop_tx(struct uart_port *port)
329{
330 unsigned long temp;
331
a0204f25 332 temp = lpuart32_read(port, UARTCTRL);
380c966c 333 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
a0204f25 334 lpuart32_write(port, temp, UARTCTRL);
380c966c
JL		 335}
336
c9e2e946
JL		 337static void lpuart_stop_rx(struct uart_port *port)
338{
339 unsigned char temp;
340
341 temp = readb(port->membase + UARTCR2);
342 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
343}
344
380c966c
JL		 345static void lpuart32_stop_rx(struct uart_port *port)
346{
347 unsigned long temp;
348
a0204f25
DA		 349 temp = lpuart32_read(port, UARTCTRL);
350 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
380c966c
JL		 351}
352
6250cc30 353static void lpuart_dma_tx(struct lpuart_port *sport)
f1cd8c87
YY		 354{
355 struct circ_buf *xmit = &sport->port.state->xmit;
6250cc30
BD		 356 struct scatterlist *sgl = sport->tx_sgl;
357 struct device *dev = sport->port.dev;
358 int ret;
f1cd8c87 359
6250cc30
BD		 360 if (sport->dma_tx_in_progress)
361 return;
f1cd8c87 362
6250cc30 363 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
f1cd8c87 364
d704b2d3 365 if (xmit->tail < xmit->head || xmit->head == 0) {
6250cc30
BD		 366 sport->dma_tx_nents = 1;
367 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
368 } else {
369 sport->dma_tx_nents = 2;
370 sg_init_table(sgl, 2);
371 sg_set_buf(sgl, xmit->buf + xmit->tail,
372 UART_XMIT_SIZE - xmit->tail);
373 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
374 }
f1cd8c87 375
6250cc30
BD		 376 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
377 if (!ret) {
378 dev_err(dev, "DMA mapping error for TX.\n");
379 return;
380 }
f1cd8c87 381
6250cc30
BD		 382 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
383 sport->dma_tx_nents,
f1cd8c87 384 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
f1cd8c87 385 if (!sport->dma_tx_desc) {
6250cc30
BD		 386 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
387 dev_err(dev, "Cannot prepare TX slave DMA!\n");
388 return;
f1cd8c87
YY		 389 }
390
391 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
392 sport->dma_tx_desc->callback_param = sport;
6250cc30 393 sport->dma_tx_in_progress = true;
f1cd8c87
YY		 394 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
395 dma_async_issue_pending(sport->dma_tx_chan);
f1cd8c87
YY		 396}
397
398static void lpuart_dma_tx_complete(void *arg)
399{
400 struct lpuart_port *sport = arg;
6250cc30 401 struct scatterlist *sgl = &sport->tx_sgl[0];
f1cd8c87
YY		 402 struct circ_buf *xmit = &sport->port.state->xmit;
403 unsigned long flags;
404
f1cd8c87
YY		 405 spin_lock_irqsave(&sport->port.lock, flags);
406
6250cc30
BD		 407 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
408
f1cd8c87 409 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
6250cc30
BD		 410
411 sport->port.icount.tx += sport->dma_tx_bytes;
412 sport->dma_tx_in_progress = false;
413 spin_unlock_irqrestore(&sport->port.lock, flags);
f1cd8c87
YY		 414
415 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
416 uart_write_wakeup(&sport->port);
417
6250cc30
BD		 418 if (waitqueue_active(&sport->dma_wait)) {
419 wake_up(&sport->dma_wait);
420 return;
421 }
422
423 spin_lock_irqsave(&sport->port.lock, flags);
424
425 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
426 lpuart_dma_tx(sport);
f1cd8c87
YY		 427
428 spin_unlock_irqrestore(&sport->port.lock, flags);
429}
430
6250cc30
BD		 431static int lpuart_dma_tx_request(struct uart_port *port)
432{
433 struct lpuart_port *sport = container_of(port,
434 struct lpuart_port, port);
435 struct dma_slave_config dma_tx_sconfig = {};
436 int ret;
437
438 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
439 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
440 dma_tx_sconfig.dst_maxburst = 1;
441 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
442 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
443
444 if (ret) {
445 dev_err(sport->port.dev,
446 "DMA slave config failed, err = %d\n", ret);
447 return ret;
448 }
449
450 return 0;
451}
452
bfc2e07f
SA		 453static void lpuart_flush_buffer(struct uart_port *port)
454{
455 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
6250cc30 456
bfc2e07f 457 if (sport->lpuart_dma_tx_use) {
6250cc30
BD		 458 if (sport->dma_tx_in_progress) {
459 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
460 sport->dma_tx_nents, DMA_TO_DEVICE);
461 sport->dma_tx_in_progress = false;
462 }
bfc2e07f 463 dmaengine_terminate_all(sport->dma_tx_chan);
bfc2e07f
SA		 464 }
465}
466
2a41bc2a
NR		 467#if defined(CONFIG_CONSOLE_POLL)
468
469static int lpuart_poll_init(struct uart_port *port)
470{
471 struct lpuart_port *sport = container_of(port,
472 struct lpuart_port, port);
473 unsigned long flags;
474 unsigned char temp;
475
476 sport->port.fifosize = 0;
477
478 spin_lock_irqsave(&sport->port.lock, flags);
479 /* Disable Rx & Tx */
480 writeb(0, sport->port.membase + UARTCR2);
481
482 temp = readb(sport->port.membase + UARTPFIFO);
483 /* Enable Rx and Tx FIFO */
484 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
485 sport->port.membase + UARTPFIFO);
486
487 /* flush Tx and Rx FIFO */
488 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
489 sport->port.membase + UARTCFIFO);
490
491 /* explicitly clear RDRF */
492 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
493 readb(sport->port.membase + UARTDR);
494 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
495 }
496
497 writeb(0, sport->port.membase + UARTTWFIFO);
498 writeb(1, sport->port.membase + UARTRWFIFO);
499
500 /* Enable Rx and Tx */
501 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
502 spin_unlock_irqrestore(&sport->port.lock, flags);
503
504 return 0;
505}
506
507static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
508{
2a41bc2a
NR		 509 /* drain */
510 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
511 barrier();
512
513 writeb(c, port->membase + UARTDR);
514}
515
516static int lpuart_poll_get_char(struct uart_port *port)
517{
518 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
519 return NO_POLL_CHAR;
520
521 return readb(port->membase + UARTDR);
522}
523
524#endif
525
c9e2e946
JL		 526static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
527{
528 struct circ_buf *xmit = &sport->port.state->xmit;
529
530 while (!uart_circ_empty(xmit) &&
531 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
532 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
533 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
534 sport->port.icount.tx++;
535 }
536
537 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
538 uart_write_wakeup(&sport->port);
539
540 if (uart_circ_empty(xmit))
541 lpuart_stop_tx(&sport->port);
542}
543
380c966c
JL		 544static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
545{
546 struct circ_buf *xmit = &sport->port.state->xmit;
547 unsigned long txcnt;
548
a0204f25 549 txcnt = lpuart32_read(&sport->port, UARTWATER);
380c966c
JL		 550 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
551 txcnt &= UARTWATER_COUNT_MASK;
552 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
a0204f25 553 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
380c966c
JL		 554 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
555 sport->port.icount.tx++;
a0204f25 556 txcnt = lpuart32_read(&sport->port, UARTWATER);
380c966c
JL		 557 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
558 txcnt &= UARTWATER_COUNT_MASK;
559 }
560
561 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
562 uart_write_wakeup(&sport->port);
563
564 if (uart_circ_empty(xmit))
565 lpuart32_stop_tx(&sport->port);
566}
567
c9e2e946
JL		 568static void lpuart_start_tx(struct uart_port *port)
569{
f1cd8c87
YY		 570 struct lpuart_port *sport = container_of(port,
571 struct lpuart_port, port);
572 struct circ_buf *xmit = &sport->port.state->xmit;
c9e2e946
JL		 573 unsigned char temp;
574
575 temp = readb(port->membase + UARTCR2);
576 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
577
4a818c43 578 if (sport->lpuart_dma_tx_use) {
6250cc30
BD		 579 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
580 lpuart_dma_tx(sport);
f1cd8c87
YY		 581 } else {
582 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
583 lpuart_transmit_buffer(sport);
584 }
c9e2e946
JL		 585}
586
380c966c
JL		 587static void lpuart32_start_tx(struct uart_port *port)
588{
589 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
590 unsigned long temp;
591
a0204f25
DA		 592 temp = lpuart32_read(port, UARTCTRL);
593 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
380c966c 594
a0204f25 595 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
380c966c
JL		 596 lpuart32_transmit_buffer(sport);
597}
598
6250cc30
BD		 599/* return TIOCSER_TEMT when transmitter is not busy */
600static unsigned int lpuart_tx_empty(struct uart_port *port)
601{
602 struct lpuart_port *sport = container_of(port,
603 struct lpuart_port, port);
604 unsigned char sr1 = readb(port->membase + UARTSR1);
605 unsigned char sfifo = readb(port->membase + UARTSFIFO);
606
607 if (sport->dma_tx_in_progress)
608 return 0;
609
610 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
611 return TIOCSER_TEMT;
612
613 return 0;
614}
615
616static unsigned int lpuart32_tx_empty(struct uart_port *port)
617{
a0204f25 618 return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ?
6250cc30
BD		 619 TIOCSER_TEMT : 0;
620}
621
3ee5447e
FE		 622static bool lpuart_is_32(struct lpuart_port *sport)
623{
624 return sport->port.iotype == UPIO_MEM32 ||
625 sport->port.iotype == UPIO_MEM32BE;
626}
627
c9e2e946
JL		 628static irqreturn_t lpuart_txint(int irq, void *dev_id)
629{
630 struct lpuart_port *sport = dev_id;
631 struct circ_buf *xmit = &sport->port.state->xmit;
632 unsigned long flags;
633
634 spin_lock_irqsave(&sport->port.lock, flags);
635 if (sport->port.x_char) {
3ee5447e 636 if (lpuart_is_32(sport))
a0204f25 637 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
380c966c
JL		 638 else
639 writeb(sport->port.x_char, sport->port.membase + UARTDR);
c9e2e946
JL		 640 goto out;
641 }
642
643 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
3ee5447e 644 if (lpuart_is_32(sport))
380c966c
JL		 645 lpuart32_stop_tx(&sport->port);
646 else
647 lpuart_stop_tx(&sport->port);
c9e2e946
JL		 648 goto out;
649 }
650
3ee5447e 651 if (lpuart_is_32(sport))
380c966c
JL		 652 lpuart32_transmit_buffer(sport);
653 else
654 lpuart_transmit_buffer(sport);
c9e2e946
JL		 655
656 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
657 uart_write_wakeup(&sport->port);
658
659out:
660 spin_unlock_irqrestore(&sport->port.lock, flags);
661 return IRQ_HANDLED;
662}
663
664static irqreturn_t lpuart_rxint(int irq, void *dev_id)
665{
666 struct lpuart_port *sport = dev_id;
667 unsigned int flg, ignored = 0;
668 struct tty_port *port = &sport->port.state->port;
669 unsigned long flags;
670 unsigned char rx, sr;
671
672 spin_lock_irqsave(&sport->port.lock, flags);
673
674 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
675 flg = TTY_NORMAL;
676 sport->port.icount.rx++;
677 /*
678 * to clear the FE, OR, NF, FE, PE flags,
679 * read SR1 then read DR
680 */
681 sr = readb(sport->port.membase + UARTSR1);
682 rx = readb(sport->port.membase + UARTDR);
683
684 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
685 continue;
686
687 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
688 if (sr & UARTSR1_PE)
689 sport->port.icount.parity++;
690 else if (sr & UARTSR1_FE)
691 sport->port.icount.frame++;
692
693 if (sr & UARTSR1_OR)
694 sport->port.icount.overrun++;
695
696 if (sr & sport->port.ignore_status_mask) {
697 if (++ignored > 100)
698 goto out;
699 continue;
700 }
701
702 sr &= sport->port.read_status_mask;
703
704 if (sr & UARTSR1_PE)
705 flg = TTY_PARITY;
706 else if (sr & UARTSR1_FE)
707 flg = TTY_FRAME;
708
709 if (sr & UARTSR1_OR)
710 flg = TTY_OVERRUN;
711
712#ifdef SUPPORT_SYSRQ
713 sport->port.sysrq = 0;
714#endif
715 }
716
717 tty_insert_flip_char(port, rx, flg);
718 }
719
720out:
721 spin_unlock_irqrestore(&sport->port.lock, flags);
722
723 tty_flip_buffer_push(port);
724 return IRQ_HANDLED;
725}
726
380c966c
JL		 727static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
728{
729 struct lpuart_port *sport = dev_id;
730 unsigned int flg, ignored = 0;
731 struct tty_port *port = &sport->port.state->port;
732 unsigned long flags;
733 unsigned long rx, sr;
734
735 spin_lock_irqsave(&sport->port.lock, flags);
736
a0204f25 737 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
380c966c
JL		 738 flg = TTY_NORMAL;
739 sport->port.icount.rx++;
740 /*
741 * to clear the FE, OR, NF, FE, PE flags,
742 * read STAT then read DATA reg
743 */
a0204f25
DA		 744 sr = lpuart32_read(&sport->port, UARTSTAT);
745 rx = lpuart32_read(&sport->port, UARTDATA);
380c966c
JL		 746 rx &= 0x3ff;
747
748 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
749 continue;
750
751 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
752 if (sr & UARTSTAT_PE)
753 sport->port.icount.parity++;
754 else if (sr & UARTSTAT_FE)
755 sport->port.icount.frame++;
756
757 if (sr & UARTSTAT_OR)
758 sport->port.icount.overrun++;
759
760 if (sr & sport->port.ignore_status_mask) {
761 if (++ignored > 100)
762 goto out;
763 continue;
764 }
765
766 sr &= sport->port.read_status_mask;
767
768 if (sr & UARTSTAT_PE)
769 flg = TTY_PARITY;
770 else if (sr & UARTSTAT_FE)
771 flg = TTY_FRAME;
772
773 if (sr & UARTSTAT_OR)
774 flg = TTY_OVERRUN;
775
776#ifdef SUPPORT_SYSRQ
777 sport->port.sysrq = 0;
778#endif
779 }
780
781 tty_insert_flip_char(port, rx, flg);
782 }
783
784out:
785 spin_unlock_irqrestore(&sport->port.lock, flags);
786
787 tty_flip_buffer_push(port);
788 return IRQ_HANDLED;
789}
790
c9e2e946
JL		 791static irqreturn_t lpuart_int(int irq, void *dev_id)
792{
793 struct lpuart_port *sport = dev_id;
5887ad43 794 unsigned char sts;
c9e2e946
JL		 795
796 sts = readb(sport->port.membase + UARTSR1);
797
5887ad43
BD		 798 if (sts & UARTSR1_RDRF)
799 lpuart_rxint(irq, dev_id);
800
6250cc30
BD		 801 if (sts & UARTSR1_TDRE)
802 lpuart_txint(irq, dev_id);
c9e2e946
JL		 803
804 return IRQ_HANDLED;
805}
806
380c966c
JL		 807static irqreturn_t lpuart32_int(int irq, void *dev_id)
808{
809 struct lpuart_port *sport = dev_id;
810 unsigned long sts, rxcount;
811
a0204f25
DA		 812 sts = lpuart32_read(&sport->port, UARTSTAT);
813 rxcount = lpuart32_read(&sport->port, UARTWATER);
380c966c
JL		 814 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
815
816 if (sts & UARTSTAT_RDRF || rxcount > 0)
817 lpuart32_rxint(irq, dev_id);
818
819 if ((sts & UARTSTAT_TDRE) &&
a0204f25 820 !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE))
380c966c
JL		 821 lpuart_txint(irq, dev_id);
822
a0204f25 823 lpuart32_write(&sport->port, sts, UARTSTAT);
380c966c
JL		 824 return IRQ_HANDLED;
825}
826
5887ad43
BD		 827static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
828{
829 struct tty_port *port = &sport->port.state->port;
830 struct dma_tx_state state;
831 enum dma_status dmastat;
832 struct circ_buf *ring = &sport->rx_ring;
833 unsigned long flags;
834 int count = 0;
835 unsigned char sr;
836
837 sr = readb(sport->port.membase + UARTSR1);
838
839 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
840 /* Read DR to clear the error flags */
841 readb(sport->port.membase + UARTDR);
842
843 if (sr & UARTSR1_PE)
844 sport->port.icount.parity++;
845 else if (sr & UARTSR1_FE)
846 sport->port.icount.frame++;
847 }
848
849 async_tx_ack(sport->dma_rx_desc);
850
851 spin_lock_irqsave(&sport->port.lock, flags);
852
853 dmastat = dmaengine_tx_status(sport->dma_rx_chan,
854 sport->dma_rx_cookie,
855 &state);
856
857 if (dmastat == DMA_ERROR) {
858 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
859 spin_unlock_irqrestore(&sport->port.lock, flags);
860 return;
861 }
862
863 /* CPU claims ownership of RX DMA buffer */
864 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
865
866 /*
867 * ring->head points to the end of data already written by the DMA.
868 * ring->tail points to the beginning of data to be read by the
869 * framework.
870 * The current transfer size should not be larger than the dma buffer
871 * length.
872 */
873 ring->head = sport->rx_sgl.length - state.residue;
874 BUG_ON(ring->head > sport->rx_sgl.length);
875 /*
876 * At this point ring->head may point to the first byte right after the
877 * last byte of the dma buffer:
878 * 0 <= ring->head <= sport->rx_sgl.length
879 *
880 * However ring->tail must always points inside the dma buffer:
881 * 0 <= ring->tail <= sport->rx_sgl.length - 1
882 *
883 * Since we use a ring buffer, we have to handle the case
884 * where head is lower than tail. In such a case, we first read from
885 * tail to the end of the buffer then reset tail.
886 */
887 if (ring->head < ring->tail) {
888 count = sport->rx_sgl.length - ring->tail;
889
890 tty_insert_flip_string(port, ring->buf + ring->tail, count);
891 ring->tail = 0;
892 sport->port.icount.rx += count;
893 }
894
895 /* Finally we read data from tail to head */
896 if (ring->tail < ring->head) {
897 count = ring->head - ring->tail;
898 tty_insert_flip_string(port, ring->buf + ring->tail, count);
899 /* Wrap ring->head if needed */
900 if (ring->head >= sport->rx_sgl.length)
901 ring->head = 0;
902 ring->tail = ring->head;
903 sport->port.icount.rx += count;
904 }
905
906 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
907 DMA_FROM_DEVICE);
908
909 spin_unlock_irqrestore(&sport->port.lock, flags);
910
911 tty_flip_buffer_push(port);
912 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
913}
914
915static void lpuart_dma_rx_complete(void *arg)
916{
917 struct lpuart_port *sport = arg;
918
919 lpuart_copy_rx_to_tty(sport);
920}
921
922static void lpuart_timer_func(unsigned long data)
923{
924 struct lpuart_port *sport = (struct lpuart_port *)data;
925
926 lpuart_copy_rx_to_tty(sport);
927}
928
929static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
930{
931 struct dma_slave_config dma_rx_sconfig = {};
932 struct circ_buf *ring = &sport->rx_ring;
933 int ret, nent;
934 int bits, baud;
935 struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port);
936 struct ktermios *termios = &tty->termios;
937
938 baud = tty_get_baud_rate(tty);
939
940 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
941 if (termios->c_cflag & PARENB)
942 bits++;
943
944 /*
945 * Calculate length of one DMA buffer size to keep latency below
946 * 10ms at any baud rate.
947 */
948 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
949 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
950 if (sport->rx_dma_rng_buf_len < 16)
951 sport->rx_dma_rng_buf_len = 16;
952
33ddca08 953 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
5887ad43
BD		 954 if (!ring->buf) {
955 dev_err(sport->port.dev, "Ring buf alloc failed\n");
956 return -ENOMEM;
957 }
958
959 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
960 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
961 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
962
963 if (!nent) {
964 dev_err(sport->port.dev, "DMA Rx mapping error\n");
965 return -EINVAL;
966 }
967
968 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
969 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
970 dma_rx_sconfig.src_maxburst = 1;
971 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
972 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
973
974 if (ret < 0) {
975 dev_err(sport->port.dev,
976 "DMA Rx slave config failed, err = %d\n", ret);
977 return ret;
978 }
979
980 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
981 sg_dma_address(&sport->rx_sgl),
982 sport->rx_sgl.length,
983 sport->rx_sgl.length / 2,
984 DMA_DEV_TO_MEM,
985 DMA_PREP_INTERRUPT);
986 if (!sport->dma_rx_desc) {
987 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
988 return -EFAULT;
989 }
990
991 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
992 sport->dma_rx_desc->callback_param = sport;
993 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
994 dma_async_issue_pending(sport->dma_rx_chan);
995
996 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
997 sport->port.membase + UARTCR5);
998
999 return 0;
1000}
1001
5887ad43
BD		 1002static void lpuart_dma_rx_free(struct uart_port *port)
1003{
1004 struct lpuart_port *sport = container_of(port,
1005 struct lpuart_port, port);
1006
1007 if (sport->dma_rx_chan)
1008 dmaengine_terminate_all(sport->dma_rx_chan);
1009
1010 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1011 kfree(sport->rx_ring.buf);
1012 sport->rx_ring.tail = 0;
1013 sport->rx_ring.head = 0;
1014 sport->dma_rx_desc = NULL;
1015 sport->dma_rx_cookie = -EINVAL;
1016}
1017
03895cf4
BD		 1018static int lpuart_config_rs485(struct uart_port *port,
1019 struct serial_rs485 *rs485)
1020{
1021 struct lpuart_port *sport = container_of(port,
1022 struct lpuart_port, port);
1023
1024 u8 modem = readb(sport->port.membase + UARTMODEM) &
1025 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1026 writeb(modem, sport->port.membase + UARTMODEM);
1027
1028 if (rs485->flags & SER_RS485_ENABLED) {
1029 /* Enable auto RS-485 RTS mode */
1030 modem |= UARTMODEM_TXRTSE;
1031
1032 /*
1033 * RTS needs to be logic HIGH either during transer _or_ after
1034 * transfer, other variants are not supported by the hardware.
1035 */
1036
1037 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1038 SER_RS485_RTS_AFTER_SEND)))
1039 rs485->flags |= SER_RS485_RTS_ON_SEND;
1040
1041 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1042 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1043 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1044
1045 /*
1046 * The hardware defaults to RTS logic HIGH while transfer.
1047 * Switch polarity in case RTS shall be logic HIGH
1048 * after transfer.
1049 * Note: UART is assumed to be active high.
1050 */
1051 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1052 modem &= ~UARTMODEM_TXRTSPOL;
1053 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1054 modem |= UARTMODEM_TXRTSPOL;
1055 }
1056
1057 /* Store the new configuration */
1058 sport->port.rs485 = *rs485;
1059
1060 writeb(modem, sport->port.membase + UARTMODEM);
1061 return 0;
1062}
1063
c9e2e946
JL		 1064static unsigned int lpuart_get_mctrl(struct uart_port *port)
1065{
1066 unsigned int temp = 0;
1067 unsigned char reg;
1068
1069 reg = readb(port->membase + UARTMODEM);
1070 if (reg & UARTMODEM_TXCTSE)
1071 temp |= TIOCM_CTS;
1072
1073 if (reg & UARTMODEM_RXRTSE)
1074 temp |= TIOCM_RTS;
1075
1076 return temp;
1077}
1078
380c966c
JL		 1079static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1080{
1081 unsigned int temp = 0;
1082 unsigned long reg;
1083
a0204f25 1084 reg = lpuart32_read(port, UARTMODIR);
380c966c
JL		 1085 if (reg & UARTMODIR_TXCTSE)
1086 temp |= TIOCM_CTS;
1087
1088 if (reg & UARTMODIR_RXRTSE)
1089 temp |= TIOCM_RTS;
1090
1091 return temp;
1092}
1093
c9e2e946
JL		 1094static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1095{
1096 unsigned char temp;
03895cf4
BD		 1097 struct lpuart_port *sport = container_of(port,
1098 struct lpuart_port, port);
c9e2e946 1099
03895cf4
BD		 1100 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1101 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1102 temp = readb(sport->port.membase + UARTMODEM) &
c9e2e946
JL		 1103 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1104
03895cf4
BD		 1105 if (mctrl & TIOCM_RTS)
1106 temp |= UARTMODEM_RXRTSE;
c9e2e946 1107
03895cf4
BD		 1108 if (mctrl & TIOCM_CTS)
1109 temp |= UARTMODEM_TXCTSE;
c9e2e946 1110
03895cf4
BD		 1111 writeb(temp, port->membase + UARTMODEM);
1112 }
c9e2e946
JL		 1113}
1114
380c966c
JL		 1115static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1116{
1117 unsigned long temp;
1118
a0204f25 1119 temp = lpuart32_read(port, UARTMODIR) &
380c966c
JL		 1120 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1121
1122 if (mctrl & TIOCM_RTS)
1123 temp |= UARTMODIR_RXRTSE;
1124
1125 if (mctrl & TIOCM_CTS)
1126 temp |= UARTMODIR_TXCTSE;
1127
a0204f25 1128 lpuart32_write(port, temp, UARTMODIR);
380c966c
JL		 1129}
1130
c9e2e946
JL		 1131static void lpuart_break_ctl(struct uart_port *port, int break_state)
1132{
1133 unsigned char temp;
1134
1135 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1136
1137 if (break_state != 0)
1138 temp |= UARTCR2_SBK;
1139
1140 writeb(temp, port->membase + UARTCR2);
1141}
1142
380c966c
JL		 1143static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1144{
1145 unsigned long temp;
1146
a0204f25 1147 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
380c966c
JL		 1148
1149 if (break_state != 0)
1150 temp |= UARTCTRL_SBK;
1151
a0204f25 1152 lpuart32_write(port, temp, UARTCTRL);
380c966c
JL		 1153}
1154
c9e2e946
JL		 1155static void lpuart_setup_watermark(struct lpuart_port *sport)
1156{
1157 unsigned char val, cr2;
bc764b8f 1158 unsigned char cr2_saved;
c9e2e946
JL		 1159
1160 cr2 = readb(sport->port.membase + UARTCR2);
bc764b8f 1161 cr2_saved = cr2;
c9e2e946
JL		 1162 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1163 UARTCR2_RIE | UARTCR2_RE);
1164 writeb(cr2, sport->port.membase + UARTCR2);
1165
c9e2e946 1166 val = readb(sport->port.membase + UARTPFIFO);
c9e2e946
JL		 1167 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1168 sport->port.membase + UARTPFIFO);
1169
1170 /* flush Tx and Rx FIFO */
1171 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1172 sport->port.membase + UARTCFIFO);
1173
d68827c6
SA		 1174 /* explicitly clear RDRF */
1175 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1176 readb(sport->port.membase + UARTDR);
1177 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1178 }
1179
f1cd8c87 1180 writeb(0, sport->port.membase + UARTTWFIFO);
c9e2e946 1181 writeb(1, sport->port.membase + UARTRWFIFO);
bc764b8f
SG		 1182
1183 /* Restore cr2 */
1184 writeb(cr2_saved, sport->port.membase + UARTCR2);
c9e2e946
JL		 1185}
1186
380c966c
JL		 1187static void lpuart32_setup_watermark(struct lpuart_port *sport)
1188{
1189 unsigned long val, ctrl;
1190 unsigned long ctrl_saved;
1191
a0204f25 1192 ctrl = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1193 ctrl_saved = ctrl;
1194 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1195 UARTCTRL_RIE | UARTCTRL_RE);
a0204f25 1196 lpuart32_write(&sport->port, ctrl, UARTCTRL);
380c966c
JL		 1197
1198 /* enable FIFO mode */
a0204f25 1199 val = lpuart32_read(&sport->port, UARTFIFO);
380c966c
JL		 1200 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1201 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
a0204f25 1202 lpuart32_write(&sport->port, val, UARTFIFO);
380c966c
JL		 1203
1204 /* set the watermark */
1205 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
a0204f25 1206 lpuart32_write(&sport->port, val, UARTWATER);
380c966c
JL		 1207
1208 /* Restore cr2 */
a0204f25 1209 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
380c966c
JL		 1210}
1211
5887ad43 1212static void rx_dma_timer_init(struct lpuart_port *sport)
f1cd8c87 1213{
5887ad43
BD		 1214 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1215 (unsigned long)sport);
1216 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1217 add_timer(&sport->lpuart_timer);
f1cd8c87
YY		 1218}
1219
c9e2e946
JL		 1220static int lpuart_startup(struct uart_port *port)
1221{
1222 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1223 int ret;
1224 unsigned long flags;
1225 unsigned char temp;
1226
ed9891bf
SA		 1227 /* determine FIFO size and enable FIFO mode */
1228 temp = readb(sport->port.membase + UARTPFIFO);
1229
1230 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1231 UARTPFIFO_FIFOSIZE_MASK) + 1);
1232
4e8f2459
SA		 1233 sport->port.fifosize = sport->txfifo_size;
1234
ed9891bf
SA		 1235 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1236 UARTPFIFO_FIFOSIZE_MASK) + 1);
1237
c9e2e946
JL		 1238 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1239 DRIVER_NAME, sport);
1240 if (ret)
1241 return ret;
1242
1243 spin_lock_irqsave(&sport->port.lock, flags);
1244
1245 lpuart_setup_watermark(sport);
1246
1247 temp = readb(sport->port.membase + UARTCR2);
1248 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1249 writeb(temp, sport->port.membase + UARTCR2);
1250
5887ad43
BD		 1251 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1252 /* set Rx DMA timeout */
1253 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1254 if (!sport->dma_rx_timeout)
1255 sport->dma_rx_timeout = 1;
1256
1257 sport->lpuart_dma_rx_use = true;
1258 rx_dma_timer_init(sport);
1259 } else {
1260 sport->lpuart_dma_rx_use = false;
1261 }
1262
1263 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
6250cc30 1264 init_waitqueue_head(&sport->dma_wait);
5887ad43
BD		 1265 sport->lpuart_dma_tx_use = true;
1266 temp = readb(port->membase + UARTCR5);
1267 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1268 } else {
1269 sport->lpuart_dma_tx_use = false;
1270 }
1271
c9e2e946 1272 spin_unlock_irqrestore(&sport->port.lock, flags);
5887ad43 1273
c9e2e946
JL		 1274 return 0;
1275}
1276
380c966c
JL		 1277static int lpuart32_startup(struct uart_port *port)
1278{
1279 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1280 int ret;
1281 unsigned long flags;
1282 unsigned long temp;
1283
1284 /* determine FIFO size */
a0204f25 1285 temp = lpuart32_read(&sport->port, UARTFIFO);
380c966c
JL		 1286
1287 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1288 UARTFIFO_FIFOSIZE_MASK) - 1);
1289
1290 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1291 UARTFIFO_FIFOSIZE_MASK) - 1);
1292
1293 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1294 DRIVER_NAME, sport);
1295 if (ret)
1296 return ret;
1297
1298 spin_lock_irqsave(&sport->port.lock, flags);
1299
1300 lpuart32_setup_watermark(sport);
1301
a0204f25 1302 temp = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1303 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1304 temp |= UARTCTRL_ILIE;
a0204f25 1305 lpuart32_write(&sport->port, temp, UARTCTRL);
380c966c
JL		 1306
1307 spin_unlock_irqrestore(&sport->port.lock, flags);
1308 return 0;
1309}
1310
c9e2e946
JL		 1311static void lpuart_shutdown(struct uart_port *port)
1312{
1313 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1314 unsigned char temp;
1315 unsigned long flags;
1316
1317 spin_lock_irqsave(&port->lock, flags);
1318
1319 /* disable Rx/Tx and interrupts */
1320 temp = readb(port->membase + UARTCR2);
1321 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1322 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1323 writeb(temp, port->membase + UARTCR2);
1324
1325 spin_unlock_irqrestore(&port->lock, flags);
1326
1327 devm_free_irq(port->dev, port->irq, sport);
f1cd8c87 1328
4a818c43 1329 if (sport->lpuart_dma_rx_use) {
4a8588a1 1330 del_timer_sync(&sport->lpuart_timer);
5887ad43 1331 lpuart_dma_rx_free(&sport->port);
f1cd8c87 1332 }
4a818c43 1333
6250cc30
BD		 1334 if (sport->lpuart_dma_tx_use) {
1335 if (wait_event_interruptible(sport->dma_wait,
1336 !sport->dma_tx_in_progress) != false) {
1337 sport->dma_tx_in_progress = false;
1338 dmaengine_terminate_all(sport->dma_tx_chan);
1339 }
1340
1341 lpuart_stop_tx(port);
1342 }
c9e2e946
JL		 1343}
1344
380c966c
JL		 1345static void lpuart32_shutdown(struct uart_port *port)
1346{
1347 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1348 unsigned long temp;
1349 unsigned long flags;
1350
1351 spin_lock_irqsave(&port->lock, flags);
1352
1353 /* disable Rx/Tx and interrupts */
a0204f25 1354 temp = lpuart32_read(port, UARTCTRL);
380c966c
JL		 1355 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1356 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
a0204f25 1357 lpuart32_write(port, temp, UARTCTRL);
380c966c
JL		 1358
1359 spin_unlock_irqrestore(&port->lock, flags);
1360
1361 devm_free_irq(port->dev, port->irq, sport);
1362}
1363
c9e2e946
JL		 1364static void
1365lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1366 struct ktermios *old)
1367{
1368 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1369 unsigned long flags;
aa9e7d78 1370 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
c9e2e946
JL		 1371 unsigned int baud;
1372 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1373 unsigned int sbr, brfa;
1374
1375 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1376 old_cr2 = readb(sport->port.membase + UARTCR2);
aa9e7d78 1377 cr3 = readb(sport->port.membase + UARTCR3);
c9e2e946
JL		 1378 cr4 = readb(sport->port.membase + UARTCR4);
1379 bdh = readb(sport->port.membase + UARTBDH);
1380 modem = readb(sport->port.membase + UARTMODEM);
1381 /*
1382 * only support CS8 and CS7, and for CS7 must enable PE.
1383 * supported mode:
1384 * - (7,e/o,1)
1385 * - (8,n,1)
1386 * - (8,m/s,1)
1387 * - (8,e/o,1)
1388 */
1389 while ((termios->c_cflag & CSIZE) != CS8 &&
1390 (termios->c_cflag & CSIZE) != CS7) {
1391 termios->c_cflag &= ~CSIZE;
1392 termios->c_cflag |= old_csize;
1393 old_csize = CS8;
1394 }
1395
1396 if ((termios->c_cflag & CSIZE) == CS8 ||
1397 (termios->c_cflag & CSIZE) == CS7)
1398 cr1 = old_cr1 & ~UARTCR1_M;
1399
1400 if (termios->c_cflag & CMSPAR) {
1401 if ((termios->c_cflag & CSIZE) != CS8) {
1402 termios->c_cflag &= ~CSIZE;
1403 termios->c_cflag |= CS8;
1404 }
1405 cr1 |= UARTCR1_M;
1406 }
1407
03895cf4
BD		 1408 /*
1409 * When auto RS-485 RTS mode is enabled,
1410 * hardware flow control need to be disabled.
1411 */
1412 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1413 termios->c_cflag &= ~CRTSCTS;
1414
c9e2e946
JL		 1415 if (termios->c_cflag & CRTSCTS) {
1416 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1417 } else {
1418 termios->c_cflag &= ~CRTSCTS;
1419 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1420 }
1421
1422 if (termios->c_cflag & CSTOPB)
1423 termios->c_cflag &= ~CSTOPB;
1424
1425 /* parity must be enabled when CS7 to match 8-bits format */
1426 if ((termios->c_cflag & CSIZE) == CS7)
1427 termios->c_cflag |= PARENB;
1428
1429 if ((termios->c_cflag & PARENB)) {
1430 if (termios->c_cflag & CMSPAR) {
1431 cr1 &= ~UARTCR1_PE;
aa9e7d78
BD		 1432 if (termios->c_cflag & PARODD)
1433 cr3 |= UARTCR3_T8;
1434 else
1435 cr3 &= ~UARTCR3_T8;
c9e2e946
JL		 1436 } else {
1437 cr1 |= UARTCR1_PE;
1438 if ((termios->c_cflag & CSIZE) == CS8)
1439 cr1 |= UARTCR1_M;
1440 if (termios->c_cflag & PARODD)
1441 cr1 |= UARTCR1_PT;
1442 else
1443 cr1 &= ~UARTCR1_PT;
1444 }
1445 }
1446
1447 /* ask the core to calculate the divisor */
1448 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1449
54a44d54
NY		 1450 /*
1451 * Need to update the Ring buffer length according to the selected
1452 * baud rate and restart Rx DMA path.
1453 *
1454 * Since timer function acqures sport->port.lock, need to stop before
1455 * acquring same lock because otherwise del_timer_sync() can deadlock.
1456 */
1457 if (old && sport->lpuart_dma_rx_use) {
1458 del_timer_sync(&sport->lpuart_timer);
1459 lpuart_dma_rx_free(&sport->port);
1460 }
1461
c9e2e946
JL		 1462 spin_lock_irqsave(&sport->port.lock, flags);
1463
1464 sport->port.read_status_mask = 0;
1465 if (termios->c_iflag & INPCK)
1466 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
ef8b9ddc 1467 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
c9e2e946
JL		 1468 sport->port.read_status_mask |= UARTSR1_FE;
1469
1470 /* characters to ignore */
1471 sport->port.ignore_status_mask = 0;
1472 if (termios->c_iflag & IGNPAR)
1473 sport->port.ignore_status_mask |= UARTSR1_PE;
1474 if (termios->c_iflag & IGNBRK) {
1475 sport->port.ignore_status_mask |= UARTSR1_FE;
1476 /*
1477 * if we're ignoring parity and break indicators,
1478 * ignore overruns too (for real raw support).
1479 */
1480 if (termios->c_iflag & IGNPAR)
1481 sport->port.ignore_status_mask |= UARTSR1_OR;
1482 }
1483
1484 /* update the per-port timeout */
1485 uart_update_timeout(port, termios->c_cflag, baud);
1486
1487 /* wait transmit engin complete */
1488 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1489 barrier();
1490
1491 /* disable transmit and receive */
1492 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1493 sport->port.membase + UARTCR2);
1494
1495 sbr = sport->port.uartclk / (16 * baud);
1496 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1497 bdh &= ~UARTBDH_SBR_MASK;
1498 bdh |= (sbr >> 8) & 0x1F;
1499 cr4 &= ~UARTCR4_BRFA_MASK;
1500 brfa &= UARTCR4_BRFA_MASK;
1501 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1502 writeb(bdh, sport->port.membase + UARTBDH);
1503 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
aa9e7d78 1504 writeb(cr3, sport->port.membase + UARTCR3);
c9e2e946
JL		 1505 writeb(cr1, sport->port.membase + UARTCR1);
1506 writeb(modem, sport->port.membase + UARTMODEM);
1507
1508 /* restore control register */
1509 writeb(old_cr2, sport->port.membase + UARTCR2);
1510
54a44d54
NY		 1511 if (old && sport->lpuart_dma_rx_use) {
1512 if (!lpuart_start_rx_dma(sport))
5887ad43 1513 rx_dma_timer_init(sport);
54a44d54 1514 else
5887ad43 1515 sport->lpuart_dma_rx_use = false;
5887ad43
BD		 1516 }
1517
c9e2e946
JL		 1518 spin_unlock_irqrestore(&sport->port.lock, flags);
1519}
1520
a6d7514b
DA		 1521static void
1522lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate)
1523{
1524 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1525 u32 clk = sport->port.uartclk;
1526
1527 /*
1528 * The idea is to use the best OSR (over-sampling rate) possible.
1529 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1530 * Loop to find the best OSR value possible, one that generates minimum
1531 * baud_diff iterate through the rest of the supported values of OSR.
1532 *
1533 * Calculation Formula:
1534 * Baud Rate = baud clock / ((OSR+1) × SBR)
1535 */
1536 baud_diff = baudrate;
1537 osr = 0;
1538 sbr = 0;
1539
1540 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1541 /* calculate the temporary sbr value */
1542 tmp_sbr = (clk / (baudrate * tmp_osr));
1543 if (tmp_sbr == 0)
1544 tmp_sbr = 1;
1545
1546 /*
1547 * calculate the baud rate difference based on the temporary
1548 * osr and sbr values
1549 */
1550 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1551
1552 /* select best values between sbr and sbr+1 */
1553 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1554 if (tmp_diff > (baudrate - tmp)) {
1555 tmp_diff = baudrate - tmp;
1556 tmp_sbr++;
1557 }
1558
1559 if (tmp_diff <= baud_diff) {
1560 baud_diff = tmp_diff;
1561 osr = tmp_osr;
1562 sbr = tmp_sbr;
1563
1564 if (!baud_diff)
1565 break;
1566 }
1567 }
1568
1569 /* handle buadrate outside acceptable rate */
1570 if (baud_diff > ((baudrate / 100) * 3))
1571 dev_warn(sport->port.dev,
1572 "unacceptable baud rate difference of more than 3%%\n");
1573
1574 tmp = lpuart32_read(&sport->port, UARTBAUD);
1575
1576 if ((osr > 3) && (osr < 8))
1577 tmp |= UARTBAUD_BOTHEDGE;
1578
1579 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
1580 tmp |= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT);
1581
1582 tmp &= ~UARTBAUD_SBR_MASK;
1583 tmp |= sbr & UARTBAUD_SBR_MASK;
1584
1585 tmp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1586
1587 lpuart32_write(&sport->port, tmp, UARTBAUD);
1588}
1589
380c966c
JL		 1590static void
1591lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1592 struct ktermios *old)
1593{
1594 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1595 unsigned long flags;
1596 unsigned long ctrl, old_ctrl, bd, modem;
1597 unsigned int baud;
1598 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
380c966c 1599
a0204f25
DA		 1600 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
1601 bd = lpuart32_read(&sport->port, UARTBAUD);
1602 modem = lpuart32_read(&sport->port, UARTMODIR);
380c966c
JL		 1603 /*
1604 * only support CS8 and CS7, and for CS7 must enable PE.
1605 * supported mode:
1606 * - (7,e/o,1)
1607 * - (8,n,1)
1608 * - (8,m/s,1)
1609 * - (8,e/o,1)
1610 */
1611 while ((termios->c_cflag & CSIZE) != CS8 &&
1612 (termios->c_cflag & CSIZE) != CS7) {
1613 termios->c_cflag &= ~CSIZE;
1614 termios->c_cflag |= old_csize;
1615 old_csize = CS8;
1616 }
1617
1618 if ((termios->c_cflag & CSIZE) == CS8 ||
1619 (termios->c_cflag & CSIZE) == CS7)
1620 ctrl = old_ctrl & ~UARTCTRL_M;
1621
1622 if (termios->c_cflag & CMSPAR) {
1623 if ((termios->c_cflag & CSIZE) != CS8) {
1624 termios->c_cflag &= ~CSIZE;
1625 termios->c_cflag |= CS8;
1626 }
1627 ctrl |= UARTCTRL_M;
1628 }
1629
1630 if (termios->c_cflag & CRTSCTS) {
1631 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1632 } else {
1633 termios->c_cflag &= ~CRTSCTS;
1634 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1635 }
1636
1637 if (termios->c_cflag & CSTOPB)
1638 termios->c_cflag &= ~CSTOPB;
1639
1640 /* parity must be enabled when CS7 to match 8-bits format */
1641 if ((termios->c_cflag & CSIZE) == CS7)
1642 termios->c_cflag |= PARENB;
1643
1644 if ((termios->c_cflag & PARENB)) {
1645 if (termios->c_cflag & CMSPAR) {
1646 ctrl &= ~UARTCTRL_PE;
1647 ctrl |= UARTCTRL_M;
1648 } else {
1649 ctrl |= UARTCR1_PE;
1650 if ((termios->c_cflag & CSIZE) == CS8)
1651 ctrl |= UARTCTRL_M;
1652 if (termios->c_cflag & PARODD)
1653 ctrl |= UARTCTRL_PT;
1654 else
1655 ctrl &= ~UARTCTRL_PT;
1656 }
1657 }
1658
1659 /* ask the core to calculate the divisor */
1660 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1661
1662 spin_lock_irqsave(&sport->port.lock, flags);
1663
1664 sport->port.read_status_mask = 0;
1665 if (termios->c_iflag & INPCK)
1666 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1667 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1668 sport->port.read_status_mask |= UARTSTAT_FE;
1669
1670 /* characters to ignore */
1671 sport->port.ignore_status_mask = 0;
1672 if (termios->c_iflag & IGNPAR)
1673 sport->port.ignore_status_mask |= UARTSTAT_PE;
1674 if (termios->c_iflag & IGNBRK) {
1675 sport->port.ignore_status_mask |= UARTSTAT_FE;
1676 /*
1677 * if we're ignoring parity and break indicators,
1678 * ignore overruns too (for real raw support).
1679 */
1680 if (termios->c_iflag & IGNPAR)
1681 sport->port.ignore_status_mask |= UARTSTAT_OR;
1682 }
1683
1684 /* update the per-port timeout */
1685 uart_update_timeout(port, termios->c_cflag, baud);
1686
1687 /* wait transmit engin complete */
a0204f25 1688 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
380c966c
JL		 1689 barrier();
1690
1691 /* disable transmit and receive */
a0204f25
DA		 1692 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1693 UARTCTRL);
380c966c 1694
a6d7514b 1695 lpuart32_serial_setbrg(sport, baud);
a0204f25
DA		 1696 lpuart32_write(&sport->port, modem, UARTMODIR);
1697 lpuart32_write(&sport->port, ctrl, UARTCTRL);
380c966c
JL		 1698 /* restore control register */
1699
1700 spin_unlock_irqrestore(&sport->port.lock, flags);
1701}
1702
c9e2e946
JL		 1703static const char *lpuart_type(struct uart_port *port)
1704{
1705 return "FSL_LPUART";
1706}
1707
1708static void lpuart_release_port(struct uart_port *port)
1709{
1710 /* nothing to do */
1711}
1712
1713static int lpuart_request_port(struct uart_port *port)
1714{
1715 return 0;
1716}
1717
1718/* configure/autoconfigure the port */
1719static void lpuart_config_port(struct uart_port *port, int flags)
1720{
1721 if (flags & UART_CONFIG_TYPE)
1722 port->type = PORT_LPUART;
1723}
1724
1725static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1726{
1727 int ret = 0;
1728
1729 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1730 ret = -EINVAL;
1731 if (port->irq != ser->irq)
1732 ret = -EINVAL;
1733 if (ser->io_type != UPIO_MEM)
1734 ret = -EINVAL;
1735 if (port->uartclk / 16 != ser->baud_base)
1736 ret = -EINVAL;
1737 if (port->iobase != ser->port)
1738 ret = -EINVAL;
1739 if (ser->hub6 != 0)
1740 ret = -EINVAL;
1741 return ret;
1742}
1743
069a47e5 1744static const struct uart_ops lpuart_pops = {
c9e2e946
JL		 1745 .tx_empty = lpuart_tx_empty,
1746 .set_mctrl = lpuart_set_mctrl,
1747 .get_mctrl = lpuart_get_mctrl,
1748 .stop_tx = lpuart_stop_tx,
1749 .start_tx = lpuart_start_tx,
1750 .stop_rx = lpuart_stop_rx,
c9e2e946
JL		 1751 .break_ctl = lpuart_break_ctl,
1752 .startup = lpuart_startup,
1753 .shutdown = lpuart_shutdown,
1754 .set_termios = lpuart_set_termios,
1755 .type = lpuart_type,
1756 .request_port = lpuart_request_port,
1757 .release_port = lpuart_release_port,
1758 .config_port = lpuart_config_port,
1759 .verify_port = lpuart_verify_port,
bfc2e07f 1760 .flush_buffer = lpuart_flush_buffer,
2a41bc2a
NR		 1761#if defined(CONFIG_CONSOLE_POLL)
1762 .poll_init = lpuart_poll_init,
1763 .poll_get_char = lpuart_poll_get_char,
1764 .poll_put_char = lpuart_poll_put_char,
1765#endif
c9e2e946
JL		 1766};
1767
069a47e5 1768static const struct uart_ops lpuart32_pops = {
380c966c
JL		 1769 .tx_empty = lpuart32_tx_empty,
1770 .set_mctrl = lpuart32_set_mctrl,
1771 .get_mctrl = lpuart32_get_mctrl,
1772 .stop_tx = lpuart32_stop_tx,
1773 .start_tx = lpuart32_start_tx,
1774 .stop_rx = lpuart32_stop_rx,
1775 .break_ctl = lpuart32_break_ctl,
1776 .startup = lpuart32_startup,
1777 .shutdown = lpuart32_shutdown,
1778 .set_termios = lpuart32_set_termios,
1779 .type = lpuart_type,
1780 .request_port = lpuart_request_port,
1781 .release_port = lpuart_release_port,
1782 .config_port = lpuart_config_port,
1783 .verify_port = lpuart_verify_port,
bfc2e07f 1784 .flush_buffer = lpuart_flush_buffer,
380c966c
JL		 1785};
1786
c9e2e946
JL		 1787static struct lpuart_port *lpuart_ports[UART_NR];
1788
1789#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1790static void lpuart_console_putchar(struct uart_port *port, int ch)
1791{
1792 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1793 barrier();
1794
1795 writeb(ch, port->membase + UARTDR);
1796}
1797
380c966c
JL		 1798static void lpuart32_console_putchar(struct uart_port *port, int ch)
1799{
a0204f25 1800 while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE))
380c966c
JL		 1801 barrier();
1802
a0204f25 1803 lpuart32_write(port, ch, UARTDATA);
380c966c
JL		 1804}
1805
c9e2e946
JL		 1806static void
1807lpuart_console_write(struct console *co, const char *s, unsigned int count)
1808{
1809 struct lpuart_port *sport = lpuart_ports[co->index];
1810 unsigned char old_cr2, cr2;
abf1e0a9
SA		 1811 unsigned long flags;
1812 int locked = 1;
1813
1814 if (sport->port.sysrq || oops_in_progress)
1815 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1816 else
1817 spin_lock_irqsave(&sport->port.lock, flags);
c9e2e946
JL		 1818
1819 /* first save CR2 and then disable interrupts */
1820 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1821 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1822 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1823 writeb(cr2, sport->port.membase + UARTCR2);
1824
1825 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1826
1827 /* wait for transmitter finish complete and restore CR2 */
1828 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1829 barrier();
1830
1831 writeb(old_cr2, sport->port.membase + UARTCR2);
abf1e0a9
SA		 1832
1833 if (locked)
1834 spin_unlock_irqrestore(&sport->port.lock, flags);
c9e2e946
JL		 1835}
1836
380c966c
JL		 1837static void
1838lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1839{
1840 struct lpuart_port *sport = lpuart_ports[co->index];
1841 unsigned long old_cr, cr;
abf1e0a9
SA		 1842 unsigned long flags;
1843 int locked = 1;
1844
1845 if (sport->port.sysrq || oops_in_progress)
1846 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1847 else
1848 spin_lock_irqsave(&sport->port.lock, flags);
380c966c
JL		 1849
1850 /* first save CR2 and then disable interrupts */
a0204f25 1851 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1852 cr |= (UARTCTRL_TE | UARTCTRL_RE);
1853 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
a0204f25 1854 lpuart32_write(&sport->port, cr, UARTCTRL);
380c966c
JL		 1855
1856 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1857
1858 /* wait for transmitter finish complete and restore CR2 */
a0204f25 1859 while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC))
380c966c
JL		 1860 barrier();
1861
a0204f25 1862 lpuart32_write(&sport->port, old_cr, UARTCTRL);
abf1e0a9
SA		 1863
1864 if (locked)
1865 spin_unlock_irqrestore(&sport->port.lock, flags);
380c966c
JL		 1866}
1867
c9e2e946
JL		 1868/*
1869 * if the port was already initialised (eg, by a boot loader),
1870 * try to determine the current setup.
1871 */
1872static void __init
1873lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1874 int *parity, int *bits)
1875{
1876 unsigned char cr, bdh, bdl, brfa;
1877 unsigned int sbr, uartclk, baud_raw;
1878
1879 cr = readb(sport->port.membase + UARTCR2);
1880 cr &= UARTCR2_TE | UARTCR2_RE;
1881 if (!cr)
1882 return;
1883
1884 /* ok, the port was enabled */
1885
1886 cr = readb(sport->port.membase + UARTCR1);
1887
1888 *parity = 'n';
1889 if (cr & UARTCR1_PE) {
1890 if (cr & UARTCR1_PT)
1891 *parity = 'o';
1892 else
1893 *parity = 'e';
1894 }
1895
1896 if (cr & UARTCR1_M)
1897 *bits = 9;
1898 else
1899 *bits = 8;
1900
1901 bdh = readb(sport->port.membase + UARTBDH);
1902 bdh &= UARTBDH_SBR_MASK;
1903 bdl = readb(sport->port.membase + UARTBDL);
1904 sbr = bdh;
1905 sbr <<= 8;
1906 sbr |= bdl;
1907 brfa = readb(sport->port.membase + UARTCR4);
1908 brfa &= UARTCR4_BRFA_MASK;
1909
1910 uartclk = clk_get_rate(sport->clk);
1911 /*
1912 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1913 */
1914 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1915
1916 if (*baud != baud_raw)
1917 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1918 "from %d to %d\n", baud_raw, *baud);
1919}
1920
380c966c
JL		 1921static void __init
1922lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1923 int *parity, int *bits)
1924{
1925 unsigned long cr, bd;
1926 unsigned int sbr, uartclk, baud_raw;
1927
a0204f25 1928 cr = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1929 cr &= UARTCTRL_TE | UARTCTRL_RE;
1930 if (!cr)
1931 return;
1932
1933 /* ok, the port was enabled */
1934
a0204f25 1935 cr = lpuart32_read(&sport->port, UARTCTRL);
380c966c
JL		 1936
1937 *parity = 'n';
1938 if (cr & UARTCTRL_PE) {
1939 if (cr & UARTCTRL_PT)
1940 *parity = 'o';
1941 else
1942 *parity = 'e';
1943 }
1944
1945 if (cr & UARTCTRL_M)
1946 *bits = 9;
1947 else
1948 *bits = 8;
1949
a0204f25 1950 bd = lpuart32_read(&sport->port, UARTBAUD);
380c966c
JL		 1951 bd &= UARTBAUD_SBR_MASK;
1952 sbr = bd;
1953 uartclk = clk_get_rate(sport->clk);
1954 /*
1955 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1956 */
1957 baud_raw = uartclk / (16 * sbr);
1958
1959 if (*baud != baud_raw)
1960 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1961 "from %d to %d\n", baud_raw, *baud);
1962}
1963
c9e2e946
JL		 1964static int __init lpuart_console_setup(struct console *co, char *options)
1965{
1966 struct lpuart_port *sport;
1967 int baud = 115200;
1968 int bits = 8;
1969 int parity = 'n';
1970 int flow = 'n';
1971
1972 /*
1973 * check whether an invalid uart number has been specified, and
1974 * if so, search for the first available port that does have
1975 * console support.
1976 */
1977 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1978 co->index = 0;
1979
1980 sport = lpuart_ports[co->index];
1981 if (sport == NULL)
1982 return -ENODEV;
1983
1984 if (options)
1985 uart_parse_options(options, &baud, &parity, &bits, &flow);
1986 else
3ee5447e 1987 if (lpuart_is_32(sport))
380c966c
JL		 1988 lpuart32_console_get_options(sport, &baud, &parity, &bits);
1989 else
1990 lpuart_console_get_options(sport, &baud, &parity, &bits);
c9e2e946 1991
3ee5447e 1992 if (lpuart_is_32(sport))
380c966c
JL		 1993 lpuart32_setup_watermark(sport);
1994 else
1995 lpuart_setup_watermark(sport);
c9e2e946
JL		 1996
1997 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1998}
1999
2000static struct uart_driver lpuart_reg;
2001static struct console lpuart_console = {
2002 .name = DEV_NAME,
2003 .write = lpuart_console_write,
2004 .device = uart_console_device,
2005 .setup = lpuart_console_setup,
2006 .flags = CON_PRINTBUFFER,
2007 .index = -1,
2008 .data = &lpuart_reg,
2009};
2010
380c966c
JL		 2011static struct console lpuart32_console = {
2012 .name = DEV_NAME,
2013 .write = lpuart32_console_write,
2014 .device = uart_console_device,
2015 .setup = lpuart_console_setup,
2016 .flags = CON_PRINTBUFFER,
2017 .index = -1,
2018 .data = &lpuart_reg,
2019};
2020
1d59b382
SA		 2021static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2022{
2023 struct earlycon_device *dev = con->data;
2024
2025 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2026}
2027
2028static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2029{
2030 struct earlycon_device *dev = con->data;
2031
2032 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2033}
2034
2035static int __init lpuart_early_console_setup(struct earlycon_device *device,
2036 const char *opt)
2037{
2038 if (!device->port.membase)
2039 return -ENODEV;
2040
2041 device->con->write = lpuart_early_write;
2042 return 0;
2043}
2044
2045static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2046 const char *opt)
2047{
2048 if (!device->port.membase)
2049 return -ENODEV;
2050
f98e1fcd 2051 device->port.iotype = UPIO_MEM32BE;
1d59b382
SA		 2052 device->con->write = lpuart32_early_write;
2053 return 0;
2054}
2055
97d6f353
DA		 2056static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2057 const char *opt)
2058{
2059 if (!device->port.membase)
2060 return -ENODEV;
2061
2062 device->port.iotype = UPIO_MEM32;
2063 device->port.membase += IMX_REG_OFF;
2064 device->con->write = lpuart32_early_write;
2065
2066 return 0;
2067}
1d59b382
SA		 2068OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2069OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
97d6f353 2070OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
1d59b382
SA		 2071EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2072EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2073
c9e2e946 2074#define LPUART_CONSOLE (&lpuart_console)
380c966c 2075#define LPUART32_CONSOLE (&lpuart32_console)
c9e2e946
JL		 2076#else
2077#define LPUART_CONSOLE NULL
380c966c 2078#define LPUART32_CONSOLE NULL
c9e2e946
JL		 2079#endif
2080
2081static struct uart_driver lpuart_reg = {
2082 .owner = THIS_MODULE,
2083 .driver_name = DRIVER_NAME,
2084 .dev_name = DEV_NAME,
2085 .nr = ARRAY_SIZE(lpuart_ports),
2086 .cons = LPUART_CONSOLE,
2087};
2088
2089static int lpuart_probe(struct platform_device *pdev)
2090{
0d6fce90
DA		 2091 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2092 &pdev->dev);
2093 const struct lpuart_soc_data *sdata = of_id->data;
c9e2e946
JL		 2094 struct device_node *np = pdev->dev.of_node;
2095 struct lpuart_port *sport;
2096 struct resource *res;
2097 int ret;
2098
2099 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2100 if (!sport)
2101 return -ENOMEM;
2102
2103 pdev->dev.coherent_dma_mask = 0;
2104
2105 ret = of_alias_get_id(np, "serial");
2106 if (ret < 0) {
2107 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2108 return ret;
2109 }
2110 sport->port.line = ret;
4ae612a3 2111 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c9e2e946
JL		 2112 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2113 if (IS_ERR(sport->port.membase))
2114 return PTR_ERR(sport->port.membase);
2115
24b1e5f0 2116 sport->port.membase += sdata->reg_off;
4ae612a3 2117 sport->port.mapbase = res->start;
c9e2e946
JL		 2118 sport->port.dev = &pdev->dev;
2119 sport->port.type = PORT_LPUART;
394a9e2c
JS		 2120 ret = platform_get_irq(pdev, 0);
2121 if (ret < 0) {
2122 dev_err(&pdev->dev, "cannot obtain irq\n");
2123 return ret;
2124 }
2125 sport->port.irq = ret;
0d6fce90 2126 sport->port.iotype = sdata->iotype;
3ee5447e 2127 if (lpuart_is_32(sport))
380c966c
JL		 2128 sport->port.ops = &lpuart32_pops;
2129 else
2130 sport->port.ops = &lpuart_pops;
c9e2e946
JL		 2131 sport->port.flags = UPF_BOOT_AUTOCONF;
2132
03895cf4
BD		 2133 sport->port.rs485_config = lpuart_config_rs485;
2134
c9e2e946
JL		 2135 sport->clk = devm_clk_get(&pdev->dev, "ipg");
2136 if (IS_ERR(sport->clk)) {
2137 ret = PTR_ERR(sport->clk);
2138 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
2139 return ret;
2140 }
2141
2142 ret = clk_prepare_enable(sport->clk);
2143 if (ret) {
2144 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
2145 return ret;
2146 }
2147
2148 sport->port.uartclk = clk_get_rate(sport->clk);
2149
2150 lpuart_ports[sport->port.line] = sport;
2151
2152 platform_set_drvdata(pdev, &sport->port);
2153
3ee5447e 2154 if (lpuart_is_32(sport))
380c966c
JL		 2155 lpuart_reg.cons = LPUART32_CONSOLE;
2156 else
2157 lpuart_reg.cons = LPUART_CONSOLE;
2158
c9e2e946
JL		 2159 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2160 if (ret) {
2161 clk_disable_unprepare(sport->clk);
2162 return ret;
2163 }
2164
4a818c43
SA		 2165 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2166 if (!sport->dma_tx_chan)
2167 dev_info(sport->port.dev, "DMA tx channel request failed, "
2168 "operating without tx DMA\n");
2169
2170 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2171 if (!sport->dma_rx_chan)
2172 dev_info(sport->port.dev, "DMA rx channel request failed, "
2173 "operating without rx DMA\n");
2174
03895cf4
BD		 2175 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) {
2176 sport->port.rs485.flags |= SER_RS485_ENABLED;
2177 sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND;
2178 writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM);
2179 }
2180
c9e2e946
JL		 2181 return 0;
2182}
2183
2184static int lpuart_remove(struct platform_device *pdev)
2185{
2186 struct lpuart_port *sport = platform_get_drvdata(pdev);
2187
2188 uart_remove_one_port(&lpuart_reg, &sport->port);
2189
2190 clk_disable_unprepare(sport->clk);
2191
4a818c43
SA		 2192 if (sport->dma_tx_chan)
2193 dma_release_channel(sport->dma_tx_chan);
2194
2195 if (sport->dma_rx_chan)
2196 dma_release_channel(sport->dma_rx_chan);
2197
c9e2e946
JL		 2198 return 0;
2199}
2200
2201#ifdef CONFIG_PM_SLEEP
2202static int lpuart_suspend(struct device *dev)
2203{
2204 struct lpuart_port *sport = dev_get_drvdata(dev);
2fe605df
YY		 2205 unsigned long temp;
2206
3ee5447e 2207 if (lpuart_is_32(sport)) {
2fe605df 2208 /* disable Rx/Tx and interrupts */
a0204f25 2209 temp = lpuart32_read(&sport->port, UARTCTRL);
2fe605df 2210 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
a0204f25 2211 lpuart32_write(&sport->port, temp, UARTCTRL);
2fe605df
YY		 2212 } else {
2213 /* disable Rx/Tx and interrupts */
2214 temp = readb(sport->port.membase + UARTCR2);
2215 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2216 writeb(temp, sport->port.membase + UARTCR2);
2217 }
c9e2e946
JL		 2218
2219 uart_suspend_port(&lpuart_reg, &sport->port);
c05efd69
BD		 2220
2221 if (sport->lpuart_dma_rx_use) {
2222 /*
2223 * EDMA driver during suspend will forcefully release any
2224 * non-idle DMA channels. If port wakeup is enabled or if port
2225 * is console port or 'no_console_suspend' is set the Rx DMA
2226 * cannot resume as as expected, hence gracefully release the
2227 * Rx DMA path before suspend and start Rx DMA path on resume.
2228 */
2229 if (sport->port.irq_wake) {
2230 del_timer_sync(&sport->lpuart_timer);
2231 lpuart_dma_rx_free(&sport->port);
2232 }
2233
2234 /* Disable Rx DMA to use UART port as wakeup source */
2235 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS,
2236 sport->port.membase + UARTCR5);
2237 }
2238
2239 if (sport->lpuart_dma_tx_use) {
2240 sport->dma_tx_in_progress = false;
2241 dmaengine_terminate_all(sport->dma_tx_chan);
2242 }
2243
d6b0d2f2
SA		 2244 if (sport->port.suspended && !sport->port.irq_wake)
2245 clk_disable_unprepare(sport->clk);
c9e2e946
JL		 2246
2247 return 0;
2248}
2249
2250static int lpuart_resume(struct device *dev)
2251{
2252 struct lpuart_port *sport = dev_get_drvdata(dev);
08de1014
JL		 2253 unsigned long temp;
2254
d6b0d2f2
SA		 2255 if (sport->port.suspended && !sport->port.irq_wake)
2256 clk_prepare_enable(sport->clk);
2257
3ee5447e 2258 if (lpuart_is_32(sport)) {
08de1014 2259 lpuart32_setup_watermark(sport);
a0204f25 2260 temp = lpuart32_read(&sport->port, UARTCTRL);
08de1014
JL		 2261 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
2262 UARTCTRL_TE | UARTCTRL_ILIE);
a0204f25 2263 lpuart32_write(&sport->port, temp, UARTCTRL);
08de1014
JL		 2264 } else {
2265 lpuart_setup_watermark(sport);
2266 temp = readb(sport->port.membase + UARTCR2);
2267 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
2268 writeb(temp, sport->port.membase + UARTCR2);
2269 }
c9e2e946 2270
c05efd69
BD		 2271 if (sport->lpuart_dma_rx_use) {
2272 if (sport->port.irq_wake) {
54a44d54 2273 if (!lpuart_start_rx_dma(sport))
c05efd69 2274 rx_dma_timer_init(sport);
54a44d54 2275 else
c05efd69 2276 sport->lpuart_dma_rx_use = false;
c05efd69
BD		 2277 }
2278 }
2279
2280 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2281 init_waitqueue_head(&sport->dma_wait);
2282 sport->lpuart_dma_tx_use = true;
2283 writeb(readb(sport->port.membase + UARTCR5) |
2284 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2285 } else {
2286 sport->lpuart_dma_tx_use = false;
2287 }
2288
c9e2e946
JL		 2289 uart_resume_port(&lpuart_reg, &sport->port);
2290
2291 return 0;
2292}
2293#endif
2294
2295static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2296
2297static struct platform_driver lpuart_driver = {
2298 .probe = lpuart_probe,
2299 .remove = lpuart_remove,
2300 .driver = {
2301 .name = "fsl-lpuart",
c9e2e946
JL		 2302 .of_match_table = lpuart_dt_ids,
2303 .pm = &lpuart_pm_ops,
2304 },
2305};
2306
2307static int __init lpuart_serial_init(void)
2308{
144c29ed 2309 int ret = uart_register_driver(&lpuart_reg);
c9e2e946 2310
c9e2e946
JL		 2311 if (ret)
2312 return ret;
2313
2314 ret = platform_driver_register(&lpuart_driver);
2315 if (ret)
2316 uart_unregister_driver(&lpuart_reg);
2317
39c34b09 2318 return ret;
c9e2e946
JL		 2319}
2320
2321static void __exit lpuart_serial_exit(void)
2322{
2323 platform_driver_unregister(&lpuart_driver);
2324 uart_unregister_driver(&lpuart_reg);
2325}
2326
2327module_init(lpuart_serial_init);
2328module_exit(lpuart_serial_exit);
2329
2330MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2331MODULE_LICENSE("GPL v2");
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