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serial: fsl_lpuart: avoid new transfer while DMA is running
[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / fsl_lpuart.c
CommitLineData
c9e2e946
JL		 1/*
2 * Freescale lpuart serial port driver
3 *
380c966c 4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
c9e2e946
JL		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
f1cd8c87
YY		 16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/dmaengine.h>
20#include <linux/dmapool.h>
c9e2e946
JL		 21#include <linux/io.h>
22#include <linux/irq.h>
f1cd8c87 23#include <linux/module.h>
c9e2e946
JL		 24#include <linux/of.h>
25#include <linux/of_device.h>
f1cd8c87 26#include <linux/of_dma.h>
c9e2e946 27#include <linux/serial_core.h>
f1cd8c87 28#include <linux/slab.h>
c9e2e946
JL		 29#include <linux/tty_flip.h>
30
31/* All registers are 8-bit width */
32#define UARTBDH 0x00
33#define UARTBDL 0x01
34#define UARTCR1 0x02
35#define UARTCR2 0x03
36#define UARTSR1 0x04
37#define UARTCR3 0x06
38#define UARTDR 0x07
39#define UARTCR4 0x0a
40#define UARTCR5 0x0b
41#define UARTMODEM 0x0d
42#define UARTPFIFO 0x10
43#define UARTCFIFO 0x11
44#define UARTSFIFO 0x12
45#define UARTTWFIFO 0x13
46#define UARTTCFIFO 0x14
47#define UARTRWFIFO 0x15
48
49#define UARTBDH_LBKDIE 0x80
50#define UARTBDH_RXEDGIE 0x40
51#define UARTBDH_SBR_MASK 0x1f
52
53#define UARTCR1_LOOPS 0x80
54#define UARTCR1_RSRC 0x20
55#define UARTCR1_M 0x10
56#define UARTCR1_WAKE 0x08
57#define UARTCR1_ILT 0x04
58#define UARTCR1_PE 0x02
59#define UARTCR1_PT 0x01
60
61#define UARTCR2_TIE 0x80
62#define UARTCR2_TCIE 0x40
63#define UARTCR2_RIE 0x20
64#define UARTCR2_ILIE 0x10
65#define UARTCR2_TE 0x08
66#define UARTCR2_RE 0x04
67#define UARTCR2_RWU 0x02
68#define UARTCR2_SBK 0x01
69
70#define UARTSR1_TDRE 0x80
71#define UARTSR1_TC 0x40
72#define UARTSR1_RDRF 0x20
73#define UARTSR1_IDLE 0x10
74#define UARTSR1_OR 0x08
75#define UARTSR1_NF 0x04
76#define UARTSR1_FE 0x02
77#define UARTSR1_PE 0x01
78
79#define UARTCR3_R8 0x80
80#define UARTCR3_T8 0x40
81#define UARTCR3_TXDIR 0x20
82#define UARTCR3_TXINV 0x10
83#define UARTCR3_ORIE 0x08
84#define UARTCR3_NEIE 0x04
85#define UARTCR3_FEIE 0x02
86#define UARTCR3_PEIE 0x01
87
88#define UARTCR4_MAEN1 0x80
89#define UARTCR4_MAEN2 0x40
90#define UARTCR4_M10 0x20
91#define UARTCR4_BRFA_MASK 0x1f
92#define UARTCR4_BRFA_OFF 0
93
94#define UARTCR5_TDMAS 0x80
95#define UARTCR5_RDMAS 0x20
96
97#define UARTMODEM_RXRTSE 0x08
98#define UARTMODEM_TXRTSPOL 0x04
99#define UARTMODEM_TXRTSE 0x02
100#define UARTMODEM_TXCTSE 0x01
101
102#define UARTPFIFO_TXFE 0x80
103#define UARTPFIFO_FIFOSIZE_MASK 0x7
104#define UARTPFIFO_TXSIZE_OFF 4
105#define UARTPFIFO_RXFE 0x08
106#define UARTPFIFO_RXSIZE_OFF 0
107
108#define UARTCFIFO_TXFLUSH 0x80
109#define UARTCFIFO_RXFLUSH 0x40
110#define UARTCFIFO_RXOFE 0x04
111#define UARTCFIFO_TXOFE 0x02
112#define UARTCFIFO_RXUFE 0x01
113
114#define UARTSFIFO_TXEMPT 0x80
115#define UARTSFIFO_RXEMPT 0x40
116#define UARTSFIFO_RXOF 0x04
117#define UARTSFIFO_TXOF 0x02
118#define UARTSFIFO_RXUF 0x01
119
380c966c
JL		 120/* 32-bit register defination */
121#define UARTBAUD 0x00
122#define UARTSTAT 0x04
123#define UARTCTRL 0x08
124#define UARTDATA 0x0C
125#define UARTMATCH 0x10
126#define UARTMODIR 0x14
127#define UARTFIFO 0x18
128#define UARTWATER 0x1c
129
130#define UARTBAUD_MAEN1 0x80000000
131#define UARTBAUD_MAEN2 0x40000000
132#define UARTBAUD_M10 0x20000000
133#define UARTBAUD_TDMAE 0x00800000
134#define UARTBAUD_RDMAE 0x00200000
135#define UARTBAUD_MATCFG 0x00400000
136#define UARTBAUD_BOTHEDGE 0x00020000
137#define UARTBAUD_RESYNCDIS 0x00010000
138#define UARTBAUD_LBKDIE 0x00008000
139#define UARTBAUD_RXEDGIE 0x00004000
140#define UARTBAUD_SBNS 0x00002000
141#define UARTBAUD_SBR 0x00000000
142#define UARTBAUD_SBR_MASK 0x1fff
143
144#define UARTSTAT_LBKDIF 0x80000000
145#define UARTSTAT_RXEDGIF 0x40000000
146#define UARTSTAT_MSBF 0x20000000
147#define UARTSTAT_RXINV 0x10000000
148#define UARTSTAT_RWUID 0x08000000
149#define UARTSTAT_BRK13 0x04000000
150#define UARTSTAT_LBKDE 0x02000000
151#define UARTSTAT_RAF 0x01000000
152#define UARTSTAT_TDRE 0x00800000
153#define UARTSTAT_TC 0x00400000
154#define UARTSTAT_RDRF 0x00200000
155#define UARTSTAT_IDLE 0x00100000
156#define UARTSTAT_OR 0x00080000
157#define UARTSTAT_NF 0x00040000
158#define UARTSTAT_FE 0x00020000
159#define UARTSTAT_PE 0x00010000
160#define UARTSTAT_MA1F 0x00008000
161#define UARTSTAT_M21F 0x00004000
162
163#define UARTCTRL_R8T9 0x80000000
164#define UARTCTRL_R9T8 0x40000000
165#define UARTCTRL_TXDIR 0x20000000
166#define UARTCTRL_TXINV 0x10000000
167#define UARTCTRL_ORIE 0x08000000
168#define UARTCTRL_NEIE 0x04000000
169#define UARTCTRL_FEIE 0x02000000
170#define UARTCTRL_PEIE 0x01000000
171#define UARTCTRL_TIE 0x00800000
172#define UARTCTRL_TCIE 0x00400000
173#define UARTCTRL_RIE 0x00200000
174#define UARTCTRL_ILIE 0x00100000
175#define UARTCTRL_TE 0x00080000
176#define UARTCTRL_RE 0x00040000
177#define UARTCTRL_RWU 0x00020000
178#define UARTCTRL_SBK 0x00010000
179#define UARTCTRL_MA1IE 0x00008000
180#define UARTCTRL_MA2IE 0x00004000
181#define UARTCTRL_IDLECFG 0x00000100
182#define UARTCTRL_LOOPS 0x00000080
183#define UARTCTRL_DOZEEN 0x00000040
184#define UARTCTRL_RSRC 0x00000020
185#define UARTCTRL_M 0x00000010
186#define UARTCTRL_WAKE 0x00000008
187#define UARTCTRL_ILT 0x00000004
188#define UARTCTRL_PE 0x00000002
189#define UARTCTRL_PT 0x00000001
190
191#define UARTDATA_NOISY 0x00008000
192#define UARTDATA_PARITYE 0x00004000
193#define UARTDATA_FRETSC 0x00002000
194#define UARTDATA_RXEMPT 0x00001000
195#define UARTDATA_IDLINE 0x00000800
196#define UARTDATA_MASK 0x3ff
197
198#define UARTMODIR_IREN 0x00020000
199#define UARTMODIR_TXCTSSRC 0x00000020
200#define UARTMODIR_TXCTSC 0x00000010
201#define UARTMODIR_RXRTSE 0x00000008
202#define UARTMODIR_TXRTSPOL 0x00000004
203#define UARTMODIR_TXRTSE 0x00000002
204#define UARTMODIR_TXCTSE 0x00000001
205
206#define UARTFIFO_TXEMPT 0x00800000
207#define UARTFIFO_RXEMPT 0x00400000
208#define UARTFIFO_TXOF 0x00020000
209#define UARTFIFO_RXUF 0x00010000
210#define UARTFIFO_TXFLUSH 0x00008000
211#define UARTFIFO_RXFLUSH 0x00004000
212#define UARTFIFO_TXOFE 0x00000200
213#define UARTFIFO_RXUFE 0x00000100
214#define UARTFIFO_TXFE 0x00000080
215#define UARTFIFO_FIFOSIZE_MASK 0x7
216#define UARTFIFO_TXSIZE_OFF 4
217#define UARTFIFO_RXFE 0x00000008
218#define UARTFIFO_RXSIZE_OFF 0
219
220#define UARTWATER_COUNT_MASK 0xff
221#define UARTWATER_TXCNT_OFF 8
222#define UARTWATER_RXCNT_OFF 24
223#define UARTWATER_WATER_MASK 0xff
224#define UARTWATER_TXWATER_OFF 0
225#define UARTWATER_RXWATER_OFF 16
226
f1cd8c87
YY		 227#define FSL_UART_RX_DMA_BUFFER_SIZE 64
228
c9e2e946
JL		 229#define DRIVER_NAME "fsl-lpuart"
230#define DEV_NAME "ttyLP"
231#define UART_NR 6
232
233struct lpuart_port {
234 struct uart_port port;
235 struct clk *clk;
236 unsigned int txfifo_size;
237 unsigned int rxfifo_size;
380c966c 238 bool lpuart32;
f1cd8c87
YY		 239
240 bool lpuart_dma_use;
241 struct dma_chan *dma_tx_chan;
242 struct dma_chan *dma_rx_chan;
243 struct dma_async_tx_descriptor *dma_tx_desc;
244 struct dma_async_tx_descriptor *dma_rx_desc;
245 dma_addr_t dma_tx_buf_bus;
246 dma_addr_t dma_rx_buf_bus;
247 dma_cookie_t dma_tx_cookie;
248 dma_cookie_t dma_rx_cookie;
249 unsigned char *dma_tx_buf_virt;
250 unsigned char *dma_rx_buf_virt;
251 unsigned int dma_tx_bytes;
252 unsigned int dma_rx_bytes;
253 int dma_tx_in_progress;
254 int dma_rx_in_progress;
255 unsigned int dma_rx_timeout;
256 struct timer_list lpuart_timer;
c9e2e946
JL		 257};
258
259static struct of_device_id lpuart_dt_ids[] = {
260 {
261 .compatible = "fsl,vf610-lpuart",
262 },
380c966c
JL		 263 {
264 .compatible = "fsl,ls1021a-lpuart",
265 },
c9e2e946
JL		 266 { /* sentinel */ }
267};
268MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
269
f1cd8c87
YY		 270/* Forward declare this for the dma callbacks*/
271static void lpuart_dma_tx_complete(void *arg);
272static void lpuart_dma_rx_complete(void *arg);
273
380c966c
JL		 274static u32 lpuart32_read(void __iomem *addr)
275{
276 return ioread32be(addr);
277}
278
279static void lpuart32_write(u32 val, void __iomem *addr)
280{
281 iowrite32be(val, addr);
282}
283
c9e2e946
JL		 284static void lpuart_stop_tx(struct uart_port *port)
285{
286 unsigned char temp;
287
288 temp = readb(port->membase + UARTCR2);
289 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
290 writeb(temp, port->membase + UARTCR2);
291}
292
380c966c
JL		 293static void lpuart32_stop_tx(struct uart_port *port)
294{
295 unsigned long temp;
296
297 temp = lpuart32_read(port->membase + UARTCTRL);
298 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
299 lpuart32_write(temp, port->membase + UARTCTRL);
300}
301
c9e2e946
JL		 302static void lpuart_stop_rx(struct uart_port *port)
303{
304 unsigned char temp;
305
306 temp = readb(port->membase + UARTCR2);
307 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
308}
309
380c966c
JL		 310static void lpuart32_stop_rx(struct uart_port *port)
311{
312 unsigned long temp;
313
314 temp = lpuart32_read(port->membase + UARTCTRL);
315 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
316}
317
f1cd8c87
YY		 318static void lpuart_copy_rx_to_tty(struct lpuart_port *sport,
319 struct tty_port *tty, int count)
320{
321 int copied;
322
323 sport->port.icount.rx += count;
324
325 if (!tty) {
326 dev_err(sport->port.dev, "No tty port\n");
327 return;
328 }
329
330 dma_sync_single_for_cpu(sport->port.dev, sport->dma_rx_buf_bus,
331 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
332 copied = tty_insert_flip_string(tty,
333 ((unsigned char *)(sport->dma_rx_buf_virt)), count);
334
335 if (copied != count) {
336 WARN_ON(1);
337 dev_err(sport->port.dev, "RxData copy to tty layer failed\n");
338 }
339
340 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
341 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
342}
343
344static void lpuart_pio_tx(struct lpuart_port *sport)
345{
346 struct circ_buf *xmit = &sport->port.state->xmit;
347 unsigned long flags;
348
349 spin_lock_irqsave(&sport->port.lock, flags);
350
351 while (!uart_circ_empty(xmit) &&
352 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
353 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
354 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
355 sport->port.icount.tx++;
356 }
357
358 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
359 uart_write_wakeup(&sport->port);
360
361 if (uart_circ_empty(xmit))
362 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
363 sport->port.membase + UARTCR5);
364
365 spin_unlock_irqrestore(&sport->port.lock, flags);
366}
367
368static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
369{
370 struct circ_buf *xmit = &sport->port.state->xmit;
371 dma_addr_t tx_bus_addr;
372
373 dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
374 UART_XMIT_SIZE, DMA_TO_DEVICE);
ed9891bf 375 sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1);
f1cd8c87
YY		 376 tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
377 sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
378 tx_bus_addr, sport->dma_tx_bytes,
379 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
380
381 if (!sport->dma_tx_desc) {
382 dev_err(sport->port.dev, "Not able to get desc for tx\n");
383 return -EIO;
384 }
385
386 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
387 sport->dma_tx_desc->callback_param = sport;
388 sport->dma_tx_in_progress = 1;
389 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
390 dma_async_issue_pending(sport->dma_tx_chan);
391
392 return 0;
393}
394
395static void lpuart_prepare_tx(struct lpuart_port *sport)
396{
397 struct circ_buf *xmit = &sport->port.state->xmit;
398 unsigned long count = CIRC_CNT_TO_END(xmit->head,
399 xmit->tail, UART_XMIT_SIZE);
400
401 if (!count)
402 return;
403
ed9891bf 404 if (count < sport->txfifo_size)
f1cd8c87
YY		 405 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
406 sport->port.membase + UARTCR5);
407 else {
408 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
409 sport->port.membase + UARTCR5);
410 lpuart_dma_tx(sport, count);
411 }
412}
413
414static void lpuart_dma_tx_complete(void *arg)
415{
416 struct lpuart_port *sport = arg;
417 struct circ_buf *xmit = &sport->port.state->xmit;
418 unsigned long flags;
419
420 async_tx_ack(sport->dma_tx_desc);
421
422 spin_lock_irqsave(&sport->port.lock, flags);
423
424 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
425 sport->dma_tx_in_progress = 0;
426
427 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
428 uart_write_wakeup(&sport->port);
429
430 lpuart_prepare_tx(sport);
431
432 spin_unlock_irqrestore(&sport->port.lock, flags);
433}
434
435static int lpuart_dma_rx(struct lpuart_port *sport)
436{
437 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
438 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
439 sport->dma_rx_desc = dmaengine_prep_slave_single(sport->dma_rx_chan,
440 sport->dma_rx_buf_bus, FSL_UART_RX_DMA_BUFFER_SIZE,
441 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
442
443 if (!sport->dma_rx_desc) {
444 dev_err(sport->port.dev, "Not able to get desc for rx\n");
445 return -EIO;
446 }
447
448 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
449 sport->dma_rx_desc->callback_param = sport;
450 sport->dma_rx_in_progress = 1;
451 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
452 dma_async_issue_pending(sport->dma_rx_chan);
453
454 return 0;
455}
456
457static void lpuart_dma_rx_complete(void *arg)
458{
459 struct lpuart_port *sport = arg;
460 struct tty_port *port = &sport->port.state->port;
461 unsigned long flags;
462
463 async_tx_ack(sport->dma_rx_desc);
464
465 spin_lock_irqsave(&sport->port.lock, flags);
466
467 sport->dma_rx_in_progress = 0;
468 lpuart_copy_rx_to_tty(sport, port, FSL_UART_RX_DMA_BUFFER_SIZE);
469 tty_flip_buffer_push(port);
470 lpuart_dma_rx(sport);
471
472 spin_unlock_irqrestore(&sport->port.lock, flags);
473}
474
475static void lpuart_timer_func(unsigned long data)
476{
477 struct lpuart_port *sport = (struct lpuart_port *)data;
478 struct tty_port *port = &sport->port.state->port;
479 struct dma_tx_state state;
480 unsigned long flags;
481 unsigned char temp;
482 int count;
483
484 del_timer(&sport->lpuart_timer);
485 dmaengine_pause(sport->dma_rx_chan);
486 dmaengine_tx_status(sport->dma_rx_chan, sport->dma_rx_cookie, &state);
487 dmaengine_terminate_all(sport->dma_rx_chan);
488 count = FSL_UART_RX_DMA_BUFFER_SIZE - state.residue;
489 async_tx_ack(sport->dma_rx_desc);
490
491 spin_lock_irqsave(&sport->port.lock, flags);
492
493 sport->dma_rx_in_progress = 0;
494 lpuart_copy_rx_to_tty(sport, port, count);
495 tty_flip_buffer_push(port);
496 temp = readb(sport->port.membase + UARTCR5);
497 writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
498
499 spin_unlock_irqrestore(&sport->port.lock, flags);
500}
501
502static inline void lpuart_prepare_rx(struct lpuart_port *sport)
503{
504 unsigned long flags;
505 unsigned char temp;
506
507 spin_lock_irqsave(&sport->port.lock, flags);
508
f1cd8c87
YY		 509 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
510 add_timer(&sport->lpuart_timer);
511
512 lpuart_dma_rx(sport);
513 temp = readb(sport->port.membase + UARTCR5);
514 writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5);
515
516 spin_unlock_irqrestore(&sport->port.lock, flags);
517}
518
c9e2e946
JL		 519static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
520{
521 struct circ_buf *xmit = &sport->port.state->xmit;
522
523 while (!uart_circ_empty(xmit) &&
524 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
525 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
526 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
527 sport->port.icount.tx++;
528 }
529
530 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
531 uart_write_wakeup(&sport->port);
532
533 if (uart_circ_empty(xmit))
534 lpuart_stop_tx(&sport->port);
535}
536
380c966c
JL		 537static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
538{
539 struct circ_buf *xmit = &sport->port.state->xmit;
540 unsigned long txcnt;
541
542 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
543 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
544 txcnt &= UARTWATER_COUNT_MASK;
545 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
546 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
547 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
548 sport->port.icount.tx++;
549 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
550 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
551 txcnt &= UARTWATER_COUNT_MASK;
552 }
553
554 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
555 uart_write_wakeup(&sport->port);
556
557 if (uart_circ_empty(xmit))
558 lpuart32_stop_tx(&sport->port);
559}
560
c9e2e946
JL		 561static void lpuart_start_tx(struct uart_port *port)
562{
f1cd8c87
YY		 563 struct lpuart_port *sport = container_of(port,
564 struct lpuart_port, port);
565 struct circ_buf *xmit = &sport->port.state->xmit;
c9e2e946
JL		 566 unsigned char temp;
567
568 temp = readb(port->membase + UARTCR2);
569 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
570
f1cd8c87
YY		 571 if (sport->lpuart_dma_use) {
572 if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress)
573 lpuart_prepare_tx(sport);
574 } else {
575 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
576 lpuart_transmit_buffer(sport);
577 }
c9e2e946
JL		 578}
579
380c966c
JL		 580static void lpuart32_start_tx(struct uart_port *port)
581{
582 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
583 unsigned long temp;
584
585 temp = lpuart32_read(port->membase + UARTCTRL);
586 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
587
588 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
589 lpuart32_transmit_buffer(sport);
590}
591
c9e2e946
JL		 592static irqreturn_t lpuart_txint(int irq, void *dev_id)
593{
594 struct lpuart_port *sport = dev_id;
595 struct circ_buf *xmit = &sport->port.state->xmit;
596 unsigned long flags;
597
598 spin_lock_irqsave(&sport->port.lock, flags);
599 if (sport->port.x_char) {
380c966c
JL		 600 if (sport->lpuart32)
601 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
602 else
603 writeb(sport->port.x_char, sport->port.membase + UARTDR);
c9e2e946
JL		 604 goto out;
605 }
606
607 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
380c966c
JL		 608 if (sport->lpuart32)
609 lpuart32_stop_tx(&sport->port);
610 else
611 lpuart_stop_tx(&sport->port);
c9e2e946
JL		 612 goto out;
613 }
614
380c966c
JL		 615 if (sport->lpuart32)
616 lpuart32_transmit_buffer(sport);
617 else
618 lpuart_transmit_buffer(sport);
c9e2e946
JL		 619
620 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
621 uart_write_wakeup(&sport->port);
622
623out:
624 spin_unlock_irqrestore(&sport->port.lock, flags);
625 return IRQ_HANDLED;
626}
627
628static irqreturn_t lpuart_rxint(int irq, void *dev_id)
629{
630 struct lpuart_port *sport = dev_id;
631 unsigned int flg, ignored = 0;
632 struct tty_port *port = &sport->port.state->port;
633 unsigned long flags;
634 unsigned char rx, sr;
635
636 spin_lock_irqsave(&sport->port.lock, flags);
637
638 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
639 flg = TTY_NORMAL;
640 sport->port.icount.rx++;
641 /*
642 * to clear the FE, OR, NF, FE, PE flags,
643 * read SR1 then read DR
644 */
645 sr = readb(sport->port.membase + UARTSR1);
646 rx = readb(sport->port.membase + UARTDR);
647
648 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
649 continue;
650
651 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
652 if (sr & UARTSR1_PE)
653 sport->port.icount.parity++;
654 else if (sr & UARTSR1_FE)
655 sport->port.icount.frame++;
656
657 if (sr & UARTSR1_OR)
658 sport->port.icount.overrun++;
659
660 if (sr & sport->port.ignore_status_mask) {
661 if (++ignored > 100)
662 goto out;
663 continue;
664 }
665
666 sr &= sport->port.read_status_mask;
667
668 if (sr & UARTSR1_PE)
669 flg = TTY_PARITY;
670 else if (sr & UARTSR1_FE)
671 flg = TTY_FRAME;
672
673 if (sr & UARTSR1_OR)
674 flg = TTY_OVERRUN;
675
676#ifdef SUPPORT_SYSRQ
677 sport->port.sysrq = 0;
678#endif
679 }
680
681 tty_insert_flip_char(port, rx, flg);
682 }
683
684out:
685 spin_unlock_irqrestore(&sport->port.lock, flags);
686
687 tty_flip_buffer_push(port);
688 return IRQ_HANDLED;
689}
690
380c966c
JL		 691static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
692{
693 struct lpuart_port *sport = dev_id;
694 unsigned int flg, ignored = 0;
695 struct tty_port *port = &sport->port.state->port;
696 unsigned long flags;
697 unsigned long rx, sr;
698
699 spin_lock_irqsave(&sport->port.lock, flags);
700
701 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
702 flg = TTY_NORMAL;
703 sport->port.icount.rx++;
704 /*
705 * to clear the FE, OR, NF, FE, PE flags,
706 * read STAT then read DATA reg
707 */
708 sr = lpuart32_read(sport->port.membase + UARTSTAT);
709 rx = lpuart32_read(sport->port.membase + UARTDATA);
710 rx &= 0x3ff;
711
712 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
713 continue;
714
715 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
716 if (sr & UARTSTAT_PE)
717 sport->port.icount.parity++;
718 else if (sr & UARTSTAT_FE)
719 sport->port.icount.frame++;
720
721 if (sr & UARTSTAT_OR)
722 sport->port.icount.overrun++;
723
724 if (sr & sport->port.ignore_status_mask) {
725 if (++ignored > 100)
726 goto out;
727 continue;
728 }
729
730 sr &= sport->port.read_status_mask;
731
732 if (sr & UARTSTAT_PE)
733 flg = TTY_PARITY;
734 else if (sr & UARTSTAT_FE)
735 flg = TTY_FRAME;
736
737 if (sr & UARTSTAT_OR)
738 flg = TTY_OVERRUN;
739
740#ifdef SUPPORT_SYSRQ
741 sport->port.sysrq = 0;
742#endif
743 }
744
745 tty_insert_flip_char(port, rx, flg);
746 }
747
748out:
749 spin_unlock_irqrestore(&sport->port.lock, flags);
750
751 tty_flip_buffer_push(port);
752 return IRQ_HANDLED;
753}
754
c9e2e946
JL		 755static irqreturn_t lpuart_int(int irq, void *dev_id)
756{
757 struct lpuart_port *sport = dev_id;
5f1437f6 758 unsigned char sts, crdma;
c9e2e946
JL		 759
760 sts = readb(sport->port.membase + UARTSR1);
5f1437f6 761 crdma = readb(sport->port.membase + UARTCR5);
c9e2e946 762
5f1437f6 763 if (sts & UARTSR1_RDRF && !(crdma & UARTCR5_RDMAS)) {
f1cd8c87
YY		 764 if (sport->lpuart_dma_use)
765 lpuart_prepare_rx(sport);
766 else
767 lpuart_rxint(irq, dev_id);
768 }
5f1437f6 769 if (sts & UARTSR1_TDRE && !(crdma & UARTCR5_TDMAS)) {
f1cd8c87
YY		 770 if (sport->lpuart_dma_use)
771 lpuart_pio_tx(sport);
772 else
773 lpuart_txint(irq, dev_id);
774 }
c9e2e946
JL		 775
776 return IRQ_HANDLED;
777}
778
380c966c
JL		 779static irqreturn_t lpuart32_int(int irq, void *dev_id)
780{
781 struct lpuart_port *sport = dev_id;
782 unsigned long sts, rxcount;
783
784 sts = lpuart32_read(sport->port.membase + UARTSTAT);
785 rxcount = lpuart32_read(sport->port.membase + UARTWATER);
786 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
787
788 if (sts & UARTSTAT_RDRF || rxcount > 0)
789 lpuart32_rxint(irq, dev_id);
790
791 if ((sts & UARTSTAT_TDRE) &&
792 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
793 lpuart_txint(irq, dev_id);
794
795 lpuart32_write(sts, sport->port.membase + UARTSTAT);
796 return IRQ_HANDLED;
797}
798
c9e2e946
JL		 799/* return TIOCSER_TEMT when transmitter is not busy */
800static unsigned int lpuart_tx_empty(struct uart_port *port)
801{
802 return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
803 TIOCSER_TEMT : 0;
804}
805
380c966c
JL		 806static unsigned int lpuart32_tx_empty(struct uart_port *port)
807{
808 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
809 TIOCSER_TEMT : 0;
810}
811
c9e2e946
JL		 812static unsigned int lpuart_get_mctrl(struct uart_port *port)
813{
814 unsigned int temp = 0;
815 unsigned char reg;
816
817 reg = readb(port->membase + UARTMODEM);
818 if (reg & UARTMODEM_TXCTSE)
819 temp |= TIOCM_CTS;
820
821 if (reg & UARTMODEM_RXRTSE)
822 temp |= TIOCM_RTS;
823
824 return temp;
825}
826
380c966c
JL		 827static unsigned int lpuart32_get_mctrl(struct uart_port *port)
828{
829 unsigned int temp = 0;
830 unsigned long reg;
831
832 reg = lpuart32_read(port->membase + UARTMODIR);
833 if (reg & UARTMODIR_TXCTSE)
834 temp |= TIOCM_CTS;
835
836 if (reg & UARTMODIR_RXRTSE)
837 temp |= TIOCM_RTS;
838
839 return temp;
840}
841
c9e2e946
JL		 842static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
843{
844 unsigned char temp;
845
846 temp = readb(port->membase + UARTMODEM) &
847 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
848
849 if (mctrl & TIOCM_RTS)
850 temp |= UARTMODEM_RXRTSE;
851
852 if (mctrl & TIOCM_CTS)
853 temp |= UARTMODEM_TXCTSE;
854
855 writeb(temp, port->membase + UARTMODEM);
856}
857
380c966c
JL		 858static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
859{
860 unsigned long temp;
861
862 temp = lpuart32_read(port->membase + UARTMODIR) &
863 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
864
865 if (mctrl & TIOCM_RTS)
866 temp |= UARTMODIR_RXRTSE;
867
868 if (mctrl & TIOCM_CTS)
869 temp |= UARTMODIR_TXCTSE;
870
871 lpuart32_write(temp, port->membase + UARTMODIR);
872}
873
c9e2e946
JL		 874static void lpuart_break_ctl(struct uart_port *port, int break_state)
875{
876 unsigned char temp;
877
878 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
879
880 if (break_state != 0)
881 temp |= UARTCR2_SBK;
882
883 writeb(temp, port->membase + UARTCR2);
884}
885
380c966c
JL		 886static void lpuart32_break_ctl(struct uart_port *port, int break_state)
887{
888 unsigned long temp;
889
890 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
891
892 if (break_state != 0)
893 temp |= UARTCTRL_SBK;
894
895 lpuart32_write(temp, port->membase + UARTCTRL);
896}
897
c9e2e946
JL		 898static void lpuart_setup_watermark(struct lpuart_port *sport)
899{
900 unsigned char val, cr2;
bc764b8f 901 unsigned char cr2_saved;
c9e2e946
JL		 902
903 cr2 = readb(sport->port.membase + UARTCR2);
bc764b8f 904 cr2_saved = cr2;
c9e2e946
JL		 905 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
906 UARTCR2_RIE | UARTCR2_RE);
907 writeb(cr2, sport->port.membase + UARTCR2);
908
c9e2e946 909 val = readb(sport->port.membase + UARTPFIFO);
c9e2e946
JL		 910 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
911 sport->port.membase + UARTPFIFO);
912
913 /* flush Tx and Rx FIFO */
914 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
915 sport->port.membase + UARTCFIFO);
916
f1cd8c87 917 writeb(0, sport->port.membase + UARTTWFIFO);
c9e2e946 918 writeb(1, sport->port.membase + UARTRWFIFO);
bc764b8f
SG		 919
920 /* Restore cr2 */
921 writeb(cr2_saved, sport->port.membase + UARTCR2);
c9e2e946
JL		 922}
923
380c966c
JL		 924static void lpuart32_setup_watermark(struct lpuart_port *sport)
925{
926 unsigned long val, ctrl;
927 unsigned long ctrl_saved;
928
929 ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
930 ctrl_saved = ctrl;
931 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
932 UARTCTRL_RIE | UARTCTRL_RE);
933 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
934
935 /* enable FIFO mode */
936 val = lpuart32_read(sport->port.membase + UARTFIFO);
937 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
938 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
939 lpuart32_write(val, sport->port.membase + UARTFIFO);
940
941 /* set the watermark */
942 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
943 lpuart32_write(val, sport->port.membase + UARTWATER);
944
945 /* Restore cr2 */
946 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
947}
948
f1cd8c87
YY		 949static int lpuart_dma_tx_request(struct uart_port *port)
950{
951 struct lpuart_port *sport = container_of(port,
952 struct lpuart_port, port);
953 struct dma_chan *tx_chan;
954 struct dma_slave_config dma_tx_sconfig;
955 dma_addr_t dma_bus;
956 unsigned char *dma_buf;
957 int ret;
958
959 tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
960
961 if (!tx_chan) {
962 dev_err(sport->port.dev, "Dma tx channel request failed!\n");
963 return -ENODEV;
964 }
965
966 dma_bus = dma_map_single(tx_chan->device->dev,
967 sport->port.state->xmit.buf,
968 UART_XMIT_SIZE, DMA_TO_DEVICE);
969
970 if (dma_mapping_error(tx_chan->device->dev, dma_bus)) {
971 dev_err(sport->port.dev, "dma_map_single tx failed\n");
972 dma_release_channel(tx_chan);
973 return -ENOMEM;
974 }
975
976 dma_buf = sport->port.state->xmit.buf;
977 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
978 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
ed9891bf 979 dma_tx_sconfig.dst_maxburst = sport->txfifo_size;
f1cd8c87
YY		 980 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
981 ret = dmaengine_slave_config(tx_chan, &dma_tx_sconfig);
982
983 if (ret < 0) {
984 dev_err(sport->port.dev,
985 "Dma slave config failed, err = %d\n", ret);
986 dma_release_channel(tx_chan);
987 return ret;
988 }
989
990 sport->dma_tx_chan = tx_chan;
991 sport->dma_tx_buf_virt = dma_buf;
992 sport->dma_tx_buf_bus = dma_bus;
993 sport->dma_tx_in_progress = 0;
994
995 return 0;
996}
997
998static int lpuart_dma_rx_request(struct uart_port *port)
999{
1000 struct lpuart_port *sport = container_of(port,
1001 struct lpuart_port, port);
1002 struct dma_chan *rx_chan;
1003 struct dma_slave_config dma_rx_sconfig;
1004 dma_addr_t dma_bus;
1005 unsigned char *dma_buf;
1006 int ret;
1007
1008 rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
1009
1010 if (!rx_chan) {
1011 dev_err(sport->port.dev, "Dma rx channel request failed!\n");
1012 return -ENODEV;
1013 }
1014
1015 dma_buf = devm_kzalloc(sport->port.dev,
1016 FSL_UART_RX_DMA_BUFFER_SIZE, GFP_KERNEL);
1017
1018 if (!dma_buf) {
1019 dev_err(sport->port.dev, "Dma rx alloc failed\n");
1020 dma_release_channel(rx_chan);
1021 return -ENOMEM;
1022 }
1023
1024 dma_bus = dma_map_single(rx_chan->device->dev, dma_buf,
1025 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1026
1027 if (dma_mapping_error(rx_chan->device->dev, dma_bus)) {
1028 dev_err(sport->port.dev, "dma_map_single rx failed\n");
1029 dma_release_channel(rx_chan);
1030 return -ENOMEM;
1031 }
1032
1033 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
1034 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1035 dma_rx_sconfig.src_maxburst = 1;
1036 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1037 ret = dmaengine_slave_config(rx_chan, &dma_rx_sconfig);
1038
1039 if (ret < 0) {
1040 dev_err(sport->port.dev,
1041 "Dma slave config failed, err = %d\n", ret);
1042 dma_release_channel(rx_chan);
1043 return ret;
1044 }
1045
1046 sport->dma_rx_chan = rx_chan;
1047 sport->dma_rx_buf_virt = dma_buf;
1048 sport->dma_rx_buf_bus = dma_bus;
1049 sport->dma_rx_in_progress = 0;
1050
f1cd8c87
YY		 1051 return 0;
1052}
1053
1054static void lpuart_dma_tx_free(struct uart_port *port)
1055{
1056 struct lpuart_port *sport = container_of(port,
1057 struct lpuart_port, port);
1058 struct dma_chan *dma_chan;
1059
1060 dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus,
1061 UART_XMIT_SIZE, DMA_TO_DEVICE);
1062 dma_chan = sport->dma_tx_chan;
1063 sport->dma_tx_chan = NULL;
1064 sport->dma_tx_buf_bus = 0;
1065 sport->dma_tx_buf_virt = NULL;
1066 dma_release_channel(dma_chan);
1067}
1068
1069static void lpuart_dma_rx_free(struct uart_port *port)
1070{
1071 struct lpuart_port *sport = container_of(port,
1072 struct lpuart_port, port);
1073 struct dma_chan *dma_chan;
1074
1075 dma_unmap_single(sport->port.dev, sport->dma_rx_buf_bus,
1076 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
1077
1078 dma_chan = sport->dma_rx_chan;
1079 sport->dma_rx_chan = NULL;
1080 sport->dma_rx_buf_bus = 0;
1081 sport->dma_rx_buf_virt = NULL;
1082 dma_release_channel(dma_chan);
1083}
1084
c9e2e946
JL		 1085static int lpuart_startup(struct uart_port *port)
1086{
1087 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1088 int ret;
1089 unsigned long flags;
1090 unsigned char temp;
1091
ed9891bf
SA		 1092 /* determine FIFO size and enable FIFO mode */
1093 temp = readb(sport->port.membase + UARTPFIFO);
1094
1095 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1096 UARTPFIFO_FIFOSIZE_MASK) + 1);
1097
1098 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1099 UARTPFIFO_FIFOSIZE_MASK) + 1);
1100
1101 /* Whether use dma support by dma request results */
f1cd8c87
YY		 1102 if (lpuart_dma_tx_request(port) || lpuart_dma_rx_request(port)) {
1103 sport->lpuart_dma_use = false;
1104 } else {
1105 sport->lpuart_dma_use = true;
4a8588a1
SA		 1106 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1107 (unsigned long)sport);
f1cd8c87 1108 temp = readb(port->membase + UARTCR5);
5f1437f6 1109 temp &= ~UARTCR5_RDMAS;
f1cd8c87
YY		 1110 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1111 }
1112
c9e2e946
JL		 1113 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1114 DRIVER_NAME, sport);
1115 if (ret)
1116 return ret;
1117
1118 spin_lock_irqsave(&sport->port.lock, flags);
1119
1120 lpuart_setup_watermark(sport);
1121
1122 temp = readb(sport->port.membase + UARTCR2);
1123 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1124 writeb(temp, sport->port.membase + UARTCR2);
1125
1126 spin_unlock_irqrestore(&sport->port.lock, flags);
1127 return 0;
1128}
1129
380c966c
JL		 1130static int lpuart32_startup(struct uart_port *port)
1131{
1132 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1133 int ret;
1134 unsigned long flags;
1135 unsigned long temp;
1136
1137 /* determine FIFO size */
1138 temp = lpuart32_read(sport->port.membase + UARTFIFO);
1139
1140 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1141 UARTFIFO_FIFOSIZE_MASK) - 1);
1142
1143 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1144 UARTFIFO_FIFOSIZE_MASK) - 1);
1145
1146 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1147 DRIVER_NAME, sport);
1148 if (ret)
1149 return ret;
1150
1151 spin_lock_irqsave(&sport->port.lock, flags);
1152
1153 lpuart32_setup_watermark(sport);
1154
1155 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1156 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1157 temp |= UARTCTRL_ILIE;
1158 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1159
1160 spin_unlock_irqrestore(&sport->port.lock, flags);
1161 return 0;
1162}
1163
c9e2e946
JL		 1164static void lpuart_shutdown(struct uart_port *port)
1165{
1166 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1167 unsigned char temp;
1168 unsigned long flags;
1169
1170 spin_lock_irqsave(&port->lock, flags);
1171
1172 /* disable Rx/Tx and interrupts */
1173 temp = readb(port->membase + UARTCR2);
1174 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1175 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1176 writeb(temp, port->membase + UARTCR2);
1177
1178 spin_unlock_irqrestore(&port->lock, flags);
1179
1180 devm_free_irq(port->dev, port->irq, sport);
f1cd8c87
YY		 1181
1182 if (sport->lpuart_dma_use) {
4a8588a1
SA		 1183 del_timer_sync(&sport->lpuart_timer);
1184
f1cd8c87
YY		 1185 lpuart_dma_tx_free(port);
1186 lpuart_dma_rx_free(port);
1187 }
c9e2e946
JL		 1188}
1189
380c966c
JL		 1190static void lpuart32_shutdown(struct uart_port *port)
1191{
1192 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1193 unsigned long temp;
1194 unsigned long flags;
1195
1196 spin_lock_irqsave(&port->lock, flags);
1197
1198 /* disable Rx/Tx and interrupts */
1199 temp = lpuart32_read(port->membase + UARTCTRL);
1200 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1201 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1202 lpuart32_write(temp, port->membase + UARTCTRL);
1203
1204 spin_unlock_irqrestore(&port->lock, flags);
1205
1206 devm_free_irq(port->dev, port->irq, sport);
1207}
1208
c9e2e946
JL		 1209static void
1210lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1211 struct ktermios *old)
1212{
1213 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1214 unsigned long flags;
1215 unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
1216 unsigned int baud;
1217 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1218 unsigned int sbr, brfa;
1219
1220 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1221 old_cr2 = readb(sport->port.membase + UARTCR2);
1222 cr4 = readb(sport->port.membase + UARTCR4);
1223 bdh = readb(sport->port.membase + UARTBDH);
1224 modem = readb(sport->port.membase + UARTMODEM);
1225 /*
1226 * only support CS8 and CS7, and for CS7 must enable PE.
1227 * supported mode:
1228 * - (7,e/o,1)
1229 * - (8,n,1)
1230 * - (8,m/s,1)
1231 * - (8,e/o,1)
1232 */
1233 while ((termios->c_cflag & CSIZE) != CS8 &&
1234 (termios->c_cflag & CSIZE) != CS7) {
1235 termios->c_cflag &= ~CSIZE;
1236 termios->c_cflag |= old_csize;
1237 old_csize = CS8;
1238 }
1239
1240 if ((termios->c_cflag & CSIZE) == CS8 ||
1241 (termios->c_cflag & CSIZE) == CS7)
1242 cr1 = old_cr1 & ~UARTCR1_M;
1243
1244 if (termios->c_cflag & CMSPAR) {
1245 if ((termios->c_cflag & CSIZE) != CS8) {
1246 termios->c_cflag &= ~CSIZE;
1247 termios->c_cflag |= CS8;
1248 }
1249 cr1 |= UARTCR1_M;
1250 }
1251
1252 if (termios->c_cflag & CRTSCTS) {
1253 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1254 } else {
1255 termios->c_cflag &= ~CRTSCTS;
1256 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1257 }
1258
1259 if (termios->c_cflag & CSTOPB)
1260 termios->c_cflag &= ~CSTOPB;
1261
1262 /* parity must be enabled when CS7 to match 8-bits format */
1263 if ((termios->c_cflag & CSIZE) == CS7)
1264 termios->c_cflag |= PARENB;
1265
1266 if ((termios->c_cflag & PARENB)) {
1267 if (termios->c_cflag & CMSPAR) {
1268 cr1 &= ~UARTCR1_PE;
1269 cr1 |= UARTCR1_M;
1270 } else {
1271 cr1 |= UARTCR1_PE;
1272 if ((termios->c_cflag & CSIZE) == CS8)
1273 cr1 |= UARTCR1_M;
1274 if (termios->c_cflag & PARODD)
1275 cr1 |= UARTCR1_PT;
1276 else
1277 cr1 &= ~UARTCR1_PT;
1278 }
1279 }
1280
1281 /* ask the core to calculate the divisor */
1282 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1283
1284 spin_lock_irqsave(&sport->port.lock, flags);
1285
1286 sport->port.read_status_mask = 0;
1287 if (termios->c_iflag & INPCK)
1288 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
ef8b9ddc 1289 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
c9e2e946
JL		 1290 sport->port.read_status_mask |= UARTSR1_FE;
1291
1292 /* characters to ignore */
1293 sport->port.ignore_status_mask = 0;
1294 if (termios->c_iflag & IGNPAR)
1295 sport->port.ignore_status_mask |= UARTSR1_PE;
1296 if (termios->c_iflag & IGNBRK) {
1297 sport->port.ignore_status_mask |= UARTSR1_FE;
1298 /*
1299 * if we're ignoring parity and break indicators,
1300 * ignore overruns too (for real raw support).
1301 */
1302 if (termios->c_iflag & IGNPAR)
1303 sport->port.ignore_status_mask |= UARTSR1_OR;
1304 }
1305
1306 /* update the per-port timeout */
1307 uart_update_timeout(port, termios->c_cflag, baud);
1308
90abef91
SA		 1309 if (sport->lpuart_dma_use) {
1310 /* Calculate delay for 1.5 DMA buffers */
1311 sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) *
1312 FSL_UART_RX_DMA_BUFFER_SIZE * 3 /
1313 sport->rxfifo_size / 2;
1314 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1315 sport->dma_rx_timeout * 1000 / HZ, sport->port.timeout);
1316 if (sport->dma_rx_timeout < msecs_to_jiffies(20))
1317 sport->dma_rx_timeout = msecs_to_jiffies(20);
1318 }
1319
c9e2e946
JL		 1320 /* wait transmit engin complete */
1321 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1322 barrier();
1323
1324 /* disable transmit and receive */
1325 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1326 sport->port.membase + UARTCR2);
1327
1328 sbr = sport->port.uartclk / (16 * baud);
1329 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1330 bdh &= ~UARTBDH_SBR_MASK;
1331 bdh |= (sbr >> 8) & 0x1F;
1332 cr4 &= ~UARTCR4_BRFA_MASK;
1333 brfa &= UARTCR4_BRFA_MASK;
1334 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1335 writeb(bdh, sport->port.membase + UARTBDH);
1336 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1337 writeb(cr1, sport->port.membase + UARTCR1);
1338 writeb(modem, sport->port.membase + UARTMODEM);
1339
1340 /* restore control register */
1341 writeb(old_cr2, sport->port.membase + UARTCR2);
1342
1343 spin_unlock_irqrestore(&sport->port.lock, flags);
1344}
1345
380c966c
JL		 1346static void
1347lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1348 struct ktermios *old)
1349{
1350 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1351 unsigned long flags;
1352 unsigned long ctrl, old_ctrl, bd, modem;
1353 unsigned int baud;
1354 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1355 unsigned int sbr;
1356
1357 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1358 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1359 modem = lpuart32_read(sport->port.membase + UARTMODIR);
1360 /*
1361 * only support CS8 and CS7, and for CS7 must enable PE.
1362 * supported mode:
1363 * - (7,e/o,1)
1364 * - (8,n,1)
1365 * - (8,m/s,1)
1366 * - (8,e/o,1)
1367 */
1368 while ((termios->c_cflag & CSIZE) != CS8 &&
1369 (termios->c_cflag & CSIZE) != CS7) {
1370 termios->c_cflag &= ~CSIZE;
1371 termios->c_cflag |= old_csize;
1372 old_csize = CS8;
1373 }
1374
1375 if ((termios->c_cflag & CSIZE) == CS8 ||
1376 (termios->c_cflag & CSIZE) == CS7)
1377 ctrl = old_ctrl & ~UARTCTRL_M;
1378
1379 if (termios->c_cflag & CMSPAR) {
1380 if ((termios->c_cflag & CSIZE) != CS8) {
1381 termios->c_cflag &= ~CSIZE;
1382 termios->c_cflag |= CS8;
1383 }
1384 ctrl |= UARTCTRL_M;
1385 }
1386
1387 if (termios->c_cflag & CRTSCTS) {
1388 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1389 } else {
1390 termios->c_cflag &= ~CRTSCTS;
1391 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1392 }
1393
1394 if (termios->c_cflag & CSTOPB)
1395 termios->c_cflag &= ~CSTOPB;
1396
1397 /* parity must be enabled when CS7 to match 8-bits format */
1398 if ((termios->c_cflag & CSIZE) == CS7)
1399 termios->c_cflag |= PARENB;
1400
1401 if ((termios->c_cflag & PARENB)) {
1402 if (termios->c_cflag & CMSPAR) {
1403 ctrl &= ~UARTCTRL_PE;
1404 ctrl |= UARTCTRL_M;
1405 } else {
1406 ctrl |= UARTCR1_PE;
1407 if ((termios->c_cflag & CSIZE) == CS8)
1408 ctrl |= UARTCTRL_M;
1409 if (termios->c_cflag & PARODD)
1410 ctrl |= UARTCTRL_PT;
1411 else
1412 ctrl &= ~UARTCTRL_PT;
1413 }
1414 }
1415
1416 /* ask the core to calculate the divisor */
1417 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1418
1419 spin_lock_irqsave(&sport->port.lock, flags);
1420
1421 sport->port.read_status_mask = 0;
1422 if (termios->c_iflag & INPCK)
1423 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1424 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1425 sport->port.read_status_mask |= UARTSTAT_FE;
1426
1427 /* characters to ignore */
1428 sport->port.ignore_status_mask = 0;
1429 if (termios->c_iflag & IGNPAR)
1430 sport->port.ignore_status_mask |= UARTSTAT_PE;
1431 if (termios->c_iflag & IGNBRK) {
1432 sport->port.ignore_status_mask |= UARTSTAT_FE;
1433 /*
1434 * if we're ignoring parity and break indicators,
1435 * ignore overruns too (for real raw support).
1436 */
1437 if (termios->c_iflag & IGNPAR)
1438 sport->port.ignore_status_mask |= UARTSTAT_OR;
1439 }
1440
1441 /* update the per-port timeout */
1442 uart_update_timeout(port, termios->c_cflag, baud);
1443
1444 /* wait transmit engin complete */
1445 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1446 barrier();
1447
1448 /* disable transmit and receive */
1449 lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1450 sport->port.membase + UARTCTRL);
1451
1452 sbr = sport->port.uartclk / (16 * baud);
1453 bd &= ~UARTBAUD_SBR_MASK;
1454 bd |= sbr & UARTBAUD_SBR_MASK;
1455 bd |= UARTBAUD_BOTHEDGE;
1456 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1457 lpuart32_write(bd, sport->port.membase + UARTBAUD);
1458 lpuart32_write(modem, sport->port.membase + UARTMODIR);
1459 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1460 /* restore control register */
1461
1462 spin_unlock_irqrestore(&sport->port.lock, flags);
1463}
1464
c9e2e946
JL		 1465static const char *lpuart_type(struct uart_port *port)
1466{
1467 return "FSL_LPUART";
1468}
1469
1470static void lpuart_release_port(struct uart_port *port)
1471{
1472 /* nothing to do */
1473}
1474
1475static int lpuart_request_port(struct uart_port *port)
1476{
1477 return 0;
1478}
1479
1480/* configure/autoconfigure the port */
1481static void lpuart_config_port(struct uart_port *port, int flags)
1482{
1483 if (flags & UART_CONFIG_TYPE)
1484 port->type = PORT_LPUART;
1485}
1486
1487static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1488{
1489 int ret = 0;
1490
1491 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1492 ret = -EINVAL;
1493 if (port->irq != ser->irq)
1494 ret = -EINVAL;
1495 if (ser->io_type != UPIO_MEM)
1496 ret = -EINVAL;
1497 if (port->uartclk / 16 != ser->baud_base)
1498 ret = -EINVAL;
1499 if (port->iobase != ser->port)
1500 ret = -EINVAL;
1501 if (ser->hub6 != 0)
1502 ret = -EINVAL;
1503 return ret;
1504}
1505
1506static struct uart_ops lpuart_pops = {
1507 .tx_empty = lpuart_tx_empty,
1508 .set_mctrl = lpuart_set_mctrl,
1509 .get_mctrl = lpuart_get_mctrl,
1510 .stop_tx = lpuart_stop_tx,
1511 .start_tx = lpuart_start_tx,
1512 .stop_rx = lpuart_stop_rx,
c9e2e946
JL		 1513 .break_ctl = lpuart_break_ctl,
1514 .startup = lpuart_startup,
1515 .shutdown = lpuart_shutdown,
1516 .set_termios = lpuart_set_termios,
1517 .type = lpuart_type,
1518 .request_port = lpuart_request_port,
1519 .release_port = lpuart_release_port,
1520 .config_port = lpuart_config_port,
1521 .verify_port = lpuart_verify_port,
1522};
1523
380c966c
JL		 1524static struct uart_ops lpuart32_pops = {
1525 .tx_empty = lpuart32_tx_empty,
1526 .set_mctrl = lpuart32_set_mctrl,
1527 .get_mctrl = lpuart32_get_mctrl,
1528 .stop_tx = lpuart32_stop_tx,
1529 .start_tx = lpuart32_start_tx,
1530 .stop_rx = lpuart32_stop_rx,
1531 .break_ctl = lpuart32_break_ctl,
1532 .startup = lpuart32_startup,
1533 .shutdown = lpuart32_shutdown,
1534 .set_termios = lpuart32_set_termios,
1535 .type = lpuart_type,
1536 .request_port = lpuart_request_port,
1537 .release_port = lpuart_release_port,
1538 .config_port = lpuart_config_port,
1539 .verify_port = lpuart_verify_port,
1540};
1541
c9e2e946
JL		 1542static struct lpuart_port *lpuart_ports[UART_NR];
1543
1544#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1545static void lpuart_console_putchar(struct uart_port *port, int ch)
1546{
1547 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1548 barrier();
1549
1550 writeb(ch, port->membase + UARTDR);
1551}
1552
380c966c
JL		 1553static void lpuart32_console_putchar(struct uart_port *port, int ch)
1554{
1555 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1556 barrier();
1557
1558 lpuart32_write(ch, port->membase + UARTDATA);
1559}
1560
c9e2e946
JL		 1561static void
1562lpuart_console_write(struct console *co, const char *s, unsigned int count)
1563{
1564 struct lpuart_port *sport = lpuart_ports[co->index];
1565 unsigned char old_cr2, cr2;
1566
1567 /* first save CR2 and then disable interrupts */
1568 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1569 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1570 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1571 writeb(cr2, sport->port.membase + UARTCR2);
1572
1573 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1574
1575 /* wait for transmitter finish complete and restore CR2 */
1576 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1577 barrier();
1578
1579 writeb(old_cr2, sport->port.membase + UARTCR2);
1580}
1581
380c966c
JL		 1582static void
1583lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1584{
1585 struct lpuart_port *sport = lpuart_ports[co->index];
1586 unsigned long old_cr, cr;
1587
1588 /* first save CR2 and then disable interrupts */
1589 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1590 cr |= (UARTCTRL_TE | UARTCTRL_RE);
1591 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1592 lpuart32_write(cr, sport->port.membase + UARTCTRL);
1593
1594 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1595
1596 /* wait for transmitter finish complete and restore CR2 */
1597 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1598 barrier();
1599
1600 lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1601}
1602
c9e2e946
JL		 1603/*
1604 * if the port was already initialised (eg, by a boot loader),
1605 * try to determine the current setup.
1606 */
1607static void __init
1608lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1609 int *parity, int *bits)
1610{
1611 unsigned char cr, bdh, bdl, brfa;
1612 unsigned int sbr, uartclk, baud_raw;
1613
1614 cr = readb(sport->port.membase + UARTCR2);
1615 cr &= UARTCR2_TE | UARTCR2_RE;
1616 if (!cr)
1617 return;
1618
1619 /* ok, the port was enabled */
1620
1621 cr = readb(sport->port.membase + UARTCR1);
1622
1623 *parity = 'n';
1624 if (cr & UARTCR1_PE) {
1625 if (cr & UARTCR1_PT)
1626 *parity = 'o';
1627 else
1628 *parity = 'e';
1629 }
1630
1631 if (cr & UARTCR1_M)
1632 *bits = 9;
1633 else
1634 *bits = 8;
1635
1636 bdh = readb(sport->port.membase + UARTBDH);
1637 bdh &= UARTBDH_SBR_MASK;
1638 bdl = readb(sport->port.membase + UARTBDL);
1639 sbr = bdh;
1640 sbr <<= 8;
1641 sbr |= bdl;
1642 brfa = readb(sport->port.membase + UARTCR4);
1643 brfa &= UARTCR4_BRFA_MASK;
1644
1645 uartclk = clk_get_rate(sport->clk);
1646 /*
1647 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1648 */
1649 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1650
1651 if (*baud != baud_raw)
1652 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1653 "from %d to %d\n", baud_raw, *baud);
1654}
1655
380c966c
JL		 1656static void __init
1657lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1658 int *parity, int *bits)
1659{
1660 unsigned long cr, bd;
1661 unsigned int sbr, uartclk, baud_raw;
1662
1663 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1664 cr &= UARTCTRL_TE | UARTCTRL_RE;
1665 if (!cr)
1666 return;
1667
1668 /* ok, the port was enabled */
1669
1670 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1671
1672 *parity = 'n';
1673 if (cr & UARTCTRL_PE) {
1674 if (cr & UARTCTRL_PT)
1675 *parity = 'o';
1676 else
1677 *parity = 'e';
1678 }
1679
1680 if (cr & UARTCTRL_M)
1681 *bits = 9;
1682 else
1683 *bits = 8;
1684
1685 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1686 bd &= UARTBAUD_SBR_MASK;
1687 sbr = bd;
1688 uartclk = clk_get_rate(sport->clk);
1689 /*
1690 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1691 */
1692 baud_raw = uartclk / (16 * sbr);
1693
1694 if (*baud != baud_raw)
1695 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1696 "from %d to %d\n", baud_raw, *baud);
1697}
1698
c9e2e946
JL		 1699static int __init lpuart_console_setup(struct console *co, char *options)
1700{
1701 struct lpuart_port *sport;
1702 int baud = 115200;
1703 int bits = 8;
1704 int parity = 'n';
1705 int flow = 'n';
1706
1707 /*
1708 * check whether an invalid uart number has been specified, and
1709 * if so, search for the first available port that does have
1710 * console support.
1711 */
1712 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1713 co->index = 0;
1714
1715 sport = lpuart_ports[co->index];
1716 if (sport == NULL)
1717 return -ENODEV;
1718
1719 if (options)
1720 uart_parse_options(options, &baud, &parity, &bits, &flow);
1721 else
380c966c
JL		 1722 if (sport->lpuart32)
1723 lpuart32_console_get_options(sport, &baud, &parity, &bits);
1724 else
1725 lpuart_console_get_options(sport, &baud, &parity, &bits);
c9e2e946 1726
380c966c
JL		 1727 if (sport->lpuart32)
1728 lpuart32_setup_watermark(sport);
1729 else
1730 lpuart_setup_watermark(sport);
c9e2e946
JL		 1731
1732 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1733}
1734
1735static struct uart_driver lpuart_reg;
1736static struct console lpuart_console = {
1737 .name = DEV_NAME,
1738 .write = lpuart_console_write,
1739 .device = uart_console_device,
1740 .setup = lpuart_console_setup,
1741 .flags = CON_PRINTBUFFER,
1742 .index = -1,
1743 .data = &lpuart_reg,
1744};
1745
380c966c
JL		 1746static struct console lpuart32_console = {
1747 .name = DEV_NAME,
1748 .write = lpuart32_console_write,
1749 .device = uart_console_device,
1750 .setup = lpuart_console_setup,
1751 .flags = CON_PRINTBUFFER,
1752 .index = -1,
1753 .data = &lpuart_reg,
1754};
1755
c9e2e946 1756#define LPUART_CONSOLE (&lpuart_console)
380c966c 1757#define LPUART32_CONSOLE (&lpuart32_console)
c9e2e946
JL		 1758#else
1759#define LPUART_CONSOLE NULL
380c966c 1760#define LPUART32_CONSOLE NULL
c9e2e946
JL		 1761#endif
1762
1763static struct uart_driver lpuart_reg = {
1764 .owner = THIS_MODULE,
1765 .driver_name = DRIVER_NAME,
1766 .dev_name = DEV_NAME,
1767 .nr = ARRAY_SIZE(lpuart_ports),
1768 .cons = LPUART_CONSOLE,
1769};
1770
1771static int lpuart_probe(struct platform_device *pdev)
1772{
1773 struct device_node *np = pdev->dev.of_node;
1774 struct lpuart_port *sport;
1775 struct resource *res;
1776 int ret;
1777
1778 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1779 if (!sport)
1780 return -ENOMEM;
1781
1782 pdev->dev.coherent_dma_mask = 0;
1783
1784 ret = of_alias_get_id(np, "serial");
1785 if (ret < 0) {
1786 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1787 return ret;
1788 }
1789 sport->port.line = ret;
380c966c 1790 sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
c9e2e946 1791
4ae612a3 1792 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c9e2e946
JL		 1793 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1794 if (IS_ERR(sport->port.membase))
1795 return PTR_ERR(sport->port.membase);
1796
4ae612a3 1797 sport->port.mapbase = res->start;
c9e2e946
JL		 1798 sport->port.dev = &pdev->dev;
1799 sport->port.type = PORT_LPUART;
1800 sport->port.iotype = UPIO_MEM;
1801 sport->port.irq = platform_get_irq(pdev, 0);
380c966c
JL		 1802 if (sport->lpuart32)
1803 sport->port.ops = &lpuart32_pops;
1804 else
1805 sport->port.ops = &lpuart_pops;
c9e2e946
JL		 1806 sport->port.flags = UPF_BOOT_AUTOCONF;
1807
1808 sport->clk = devm_clk_get(&pdev->dev, "ipg");
1809 if (IS_ERR(sport->clk)) {
1810 ret = PTR_ERR(sport->clk);
1811 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1812 return ret;
1813 }
1814
1815 ret = clk_prepare_enable(sport->clk);
1816 if (ret) {
1817 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1818 return ret;
1819 }
1820
1821 sport->port.uartclk = clk_get_rate(sport->clk);
1822
1823 lpuart_ports[sport->port.line] = sport;
1824
1825 platform_set_drvdata(pdev, &sport->port);
1826
380c966c
JL		 1827 if (sport->lpuart32)
1828 lpuart_reg.cons = LPUART32_CONSOLE;
1829 else
1830 lpuart_reg.cons = LPUART_CONSOLE;
1831
c9e2e946
JL		 1832 ret = uart_add_one_port(&lpuart_reg, &sport->port);
1833 if (ret) {
1834 clk_disable_unprepare(sport->clk);
1835 return ret;
1836 }
1837
1838 return 0;
1839}
1840
1841static int lpuart_remove(struct platform_device *pdev)
1842{
1843 struct lpuart_port *sport = platform_get_drvdata(pdev);
1844
1845 uart_remove_one_port(&lpuart_reg, &sport->port);
1846
1847 clk_disable_unprepare(sport->clk);
1848
1849 return 0;
1850}
1851
1852#ifdef CONFIG_PM_SLEEP
1853static int lpuart_suspend(struct device *dev)
1854{
1855 struct lpuart_port *sport = dev_get_drvdata(dev);
1856
1857 uart_suspend_port(&lpuart_reg, &sport->port);
1858
1859 return 0;
1860}
1861
1862static int lpuart_resume(struct device *dev)
1863{
1864 struct lpuart_port *sport = dev_get_drvdata(dev);
08de1014
JL		 1865 unsigned long temp;
1866
1867 if (sport->lpuart32) {
1868 lpuart32_setup_watermark(sport);
1869 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1870 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
1871 UARTCTRL_TE | UARTCTRL_ILIE);
1872 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1873 } else {
1874 lpuart_setup_watermark(sport);
1875 temp = readb(sport->port.membase + UARTCR2);
1876 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1877 writeb(temp, sport->port.membase + UARTCR2);
1878 }
c9e2e946
JL		 1879
1880 uart_resume_port(&lpuart_reg, &sport->port);
1881
1882 return 0;
1883}
1884#endif
1885
1886static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
1887
1888static struct platform_driver lpuart_driver = {
1889 .probe = lpuart_probe,
1890 .remove = lpuart_remove,
1891 .driver = {
1892 .name = "fsl-lpuart",
c9e2e946
JL		 1893 .of_match_table = lpuart_dt_ids,
1894 .pm = &lpuart_pm_ops,
1895 },
1896};
1897
1898static int __init lpuart_serial_init(void)
1899{
144c29ed 1900 int ret = uart_register_driver(&lpuart_reg);
c9e2e946 1901
c9e2e946
JL		 1902 if (ret)
1903 return ret;
1904
1905 ret = platform_driver_register(&lpuart_driver);
1906 if (ret)
1907 uart_unregister_driver(&lpuart_reg);
1908
39c34b09 1909 return ret;
c9e2e946
JL		 1910}
1911
1912static void __exit lpuart_serial_exit(void)
1913{
1914 platform_driver_unregister(&lpuart_driver);
1915 uart_unregister_driver(&lpuart_reg);
1916}
1917
1918module_init(lpuart_serial_init);
1919module_exit(lpuart_serial_exit);
1920
1921MODULE_DESCRIPTION("Freescale lpuart serial port driver");
1922MODULE_LICENSE("GPL v2");
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