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serial: fsl_lpuart: move DMA RX timeout calculation
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / fsl_lpuart.c
CommitLineData
c9e2e946
JL		 1/*
2 * Freescale lpuart serial port driver
3 *
4 * Copyright 2012-2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
f1cd8c87
YY		 16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/dmaengine.h>
20#include <linux/dmapool.h>
c9e2e946
JL		 21#include <linux/io.h>
22#include <linux/irq.h>
f1cd8c87 23#include <linux/module.h>
c9e2e946
JL		 24#include <linux/of.h>
25#include <linux/of_device.h>
f1cd8c87 26#include <linux/of_dma.h>
c9e2e946 27#include <linux/serial_core.h>
f1cd8c87 28#include <linux/slab.h>
c9e2e946
JL		 29#include <linux/tty_flip.h>
30
31/* All registers are 8-bit width */
32#define UARTBDH 0x00
33#define UARTBDL 0x01
34#define UARTCR1 0x02
35#define UARTCR2 0x03
36#define UARTSR1 0x04
37#define UARTCR3 0x06
38#define UARTDR 0x07
39#define UARTCR4 0x0a
40#define UARTCR5 0x0b
41#define UARTMODEM 0x0d
42#define UARTPFIFO 0x10
43#define UARTCFIFO 0x11
44#define UARTSFIFO 0x12
45#define UARTTWFIFO 0x13
46#define UARTTCFIFO 0x14
47#define UARTRWFIFO 0x15
48
49#define UARTBDH_LBKDIE 0x80
50#define UARTBDH_RXEDGIE 0x40
51#define UARTBDH_SBR_MASK 0x1f
52
53#define UARTCR1_LOOPS 0x80
54#define UARTCR1_RSRC 0x20
55#define UARTCR1_M 0x10
56#define UARTCR1_WAKE 0x08
57#define UARTCR1_ILT 0x04
58#define UARTCR1_PE 0x02
59#define UARTCR1_PT 0x01
60
61#define UARTCR2_TIE 0x80
62#define UARTCR2_TCIE 0x40
63#define UARTCR2_RIE 0x20
64#define UARTCR2_ILIE 0x10
65#define UARTCR2_TE 0x08
66#define UARTCR2_RE 0x04
67#define UARTCR2_RWU 0x02
68#define UARTCR2_SBK 0x01
69
70#define UARTSR1_TDRE 0x80
71#define UARTSR1_TC 0x40
72#define UARTSR1_RDRF 0x20
73#define UARTSR1_IDLE 0x10
74#define UARTSR1_OR 0x08
75#define UARTSR1_NF 0x04
76#define UARTSR1_FE 0x02
77#define UARTSR1_PE 0x01
78
79#define UARTCR3_R8 0x80
80#define UARTCR3_T8 0x40
81#define UARTCR3_TXDIR 0x20
82#define UARTCR3_TXINV 0x10
83#define UARTCR3_ORIE 0x08
84#define UARTCR3_NEIE 0x04
85#define UARTCR3_FEIE 0x02
86#define UARTCR3_PEIE 0x01
87
88#define UARTCR4_MAEN1 0x80
89#define UARTCR4_MAEN2 0x40
90#define UARTCR4_M10 0x20
91#define UARTCR4_BRFA_MASK 0x1f
92#define UARTCR4_BRFA_OFF 0
93
94#define UARTCR5_TDMAS 0x80
95#define UARTCR5_RDMAS 0x20
96
97#define UARTMODEM_RXRTSE 0x08
98#define UARTMODEM_TXRTSPOL 0x04
99#define UARTMODEM_TXRTSE 0x02
100#define UARTMODEM_TXCTSE 0x01
101
102#define UARTPFIFO_TXFE 0x80
103#define UARTPFIFO_FIFOSIZE_MASK 0x7
104#define UARTPFIFO_TXSIZE_OFF 4
105#define UARTPFIFO_RXFE 0x08
106#define UARTPFIFO_RXSIZE_OFF 0
107
108#define UARTCFIFO_TXFLUSH 0x80
109#define UARTCFIFO_RXFLUSH 0x40
110#define UARTCFIFO_RXOFE 0x04
111#define UARTCFIFO_TXOFE 0x02
112#define UARTCFIFO_RXUFE 0x01
113
114#define UARTSFIFO_TXEMPT 0x80
115#define UARTSFIFO_RXEMPT 0x40
116#define UARTSFIFO_RXOF 0x04
117#define UARTSFIFO_TXOF 0x02
118#define UARTSFIFO_RXUF 0x01
119
f1cd8c87
YY		 120#define DMA_MAXBURST 16
121#define DMA_MAXBURST_MASK (DMA_MAXBURST - 1)
122#define FSL_UART_RX_DMA_BUFFER_SIZE 64
123
c9e2e946
JL		 124#define DRIVER_NAME "fsl-lpuart"
125#define DEV_NAME "ttyLP"
126#define UART_NR 6
127
128struct lpuart_port {
129 struct uart_port port;
130 struct clk *clk;
131 unsigned int txfifo_size;
132 unsigned int rxfifo_size;
f1cd8c87
YY		 133
134 bool lpuart_dma_use;
135 struct dma_chan *dma_tx_chan;
136 struct dma_chan *dma_rx_chan;
137 struct dma_async_tx_descriptor *dma_tx_desc;
138 struct dma_async_tx_descriptor *dma_rx_desc;
139 dma_addr_t dma_tx_buf_bus;
140 dma_addr_t dma_rx_buf_bus;
141 dma_cookie_t dma_tx_cookie;
142 dma_cookie_t dma_rx_cookie;
143 unsigned char *dma_tx_buf_virt;
144 unsigned char *dma_rx_buf_virt;
145 unsigned int dma_tx_bytes;
146 unsigned int dma_rx_bytes;
147 int dma_tx_in_progress;
148 int dma_rx_in_progress;
149 unsigned int dma_rx_timeout;
150 struct timer_list lpuart_timer;
c9e2e946
JL		 151};
152
153static struct of_device_id lpuart_dt_ids[] = {
154 {
155 .compatible = "fsl,vf610-lpuart",
156 },
157 { /* sentinel */ }
158};
159MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
160
f1cd8c87
YY		 161/* Forward declare this for the dma callbacks*/
162static void lpuart_dma_tx_complete(void *arg);
163static void lpuart_dma_rx_complete(void *arg);
164
c9e2e946
JL		 165static void lpuart_stop_tx(struct uart_port *port)
166{
167 unsigned char temp;
168
169 temp = readb(port->membase + UARTCR2);
170 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
171 writeb(temp, port->membase + UARTCR2);
172}
173
174static void lpuart_stop_rx(struct uart_port *port)
175{
176 unsigned char temp;
177
178 temp = readb(port->membase + UARTCR2);
179 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
180}
181
f1cd8c87
YY		 182static void lpuart_copy_rx_to_tty(struct lpuart_port *sport,
183 struct tty_port *tty, int count)
184{
185 int copied;
186
187 sport->port.icount.rx += count;
188
189 if (!tty) {
190 dev_err(sport->port.dev, "No tty port\n");
191 return;
192 }
193
194 dma_sync_single_for_cpu(sport->port.dev, sport->dma_rx_buf_bus,
195 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
196 copied = tty_insert_flip_string(tty,
197 ((unsigned char *)(sport->dma_rx_buf_virt)), count);
198
199 if (copied != count) {
200 WARN_ON(1);
201 dev_err(sport->port.dev, "RxData copy to tty layer failed\n");
202 }
203
204 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
205 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
206}
207
208static void lpuart_pio_tx(struct lpuart_port *sport)
209{
210 struct circ_buf *xmit = &sport->port.state->xmit;
211 unsigned long flags;
212
213 spin_lock_irqsave(&sport->port.lock, flags);
214
215 while (!uart_circ_empty(xmit) &&
216 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
217 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
218 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
219 sport->port.icount.tx++;
220 }
221
222 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
223 uart_write_wakeup(&sport->port);
224
225 if (uart_circ_empty(xmit))
226 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
227 sport->port.membase + UARTCR5);
228
229 spin_unlock_irqrestore(&sport->port.lock, flags);
230}
231
232static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
233{
234 struct circ_buf *xmit = &sport->port.state->xmit;
235 dma_addr_t tx_bus_addr;
236
237 dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
238 UART_XMIT_SIZE, DMA_TO_DEVICE);
239 sport->dma_tx_bytes = count & ~(DMA_MAXBURST_MASK);
240 tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
241 sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
242 tx_bus_addr, sport->dma_tx_bytes,
243 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
244
245 if (!sport->dma_tx_desc) {
246 dev_err(sport->port.dev, "Not able to get desc for tx\n");
247 return -EIO;
248 }
249
250 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
251 sport->dma_tx_desc->callback_param = sport;
252 sport->dma_tx_in_progress = 1;
253 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
254 dma_async_issue_pending(sport->dma_tx_chan);
255
256 return 0;
257}
258
259static void lpuart_prepare_tx(struct lpuart_port *sport)
260{
261 struct circ_buf *xmit = &sport->port.state->xmit;
262 unsigned long count = CIRC_CNT_TO_END(xmit->head,
263 xmit->tail, UART_XMIT_SIZE);
264
265 if (!count)
266 return;
267
268 if (count < DMA_MAXBURST)
269 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
270 sport->port.membase + UARTCR5);
271 else {
272 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
273 sport->port.membase + UARTCR5);
274 lpuart_dma_tx(sport, count);
275 }
276}
277
278static void lpuart_dma_tx_complete(void *arg)
279{
280 struct lpuart_port *sport = arg;
281 struct circ_buf *xmit = &sport->port.state->xmit;
282 unsigned long flags;
283
284 async_tx_ack(sport->dma_tx_desc);
285
286 spin_lock_irqsave(&sport->port.lock, flags);
287
288 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
289 sport->dma_tx_in_progress = 0;
290
291 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
292 uart_write_wakeup(&sport->port);
293
294 lpuart_prepare_tx(sport);
295
296 spin_unlock_irqrestore(&sport->port.lock, flags);
297}
298
299static int lpuart_dma_rx(struct lpuart_port *sport)
300{
301 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
302 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
303 sport->dma_rx_desc = dmaengine_prep_slave_single(sport->dma_rx_chan,
304 sport->dma_rx_buf_bus, FSL_UART_RX_DMA_BUFFER_SIZE,
305 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
306
307 if (!sport->dma_rx_desc) {
308 dev_err(sport->port.dev, "Not able to get desc for rx\n");
309 return -EIO;
310 }
311
312 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
313 sport->dma_rx_desc->callback_param = sport;
314 sport->dma_rx_in_progress = 1;
315 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
316 dma_async_issue_pending(sport->dma_rx_chan);
317
318 return 0;
319}
320
321static void lpuart_dma_rx_complete(void *arg)
322{
323 struct lpuart_port *sport = arg;
324 struct tty_port *port = &sport->port.state->port;
325 unsigned long flags;
326
327 async_tx_ack(sport->dma_rx_desc);
328
329 spin_lock_irqsave(&sport->port.lock, flags);
330
331 sport->dma_rx_in_progress = 0;
332 lpuart_copy_rx_to_tty(sport, port, FSL_UART_RX_DMA_BUFFER_SIZE);
333 tty_flip_buffer_push(port);
334 lpuart_dma_rx(sport);
335
336 spin_unlock_irqrestore(&sport->port.lock, flags);
337}
338
339static void lpuart_timer_func(unsigned long data)
340{
341 struct lpuart_port *sport = (struct lpuart_port *)data;
342 struct tty_port *port = &sport->port.state->port;
343 struct dma_tx_state state;
344 unsigned long flags;
345 unsigned char temp;
346 int count;
347
348 del_timer(&sport->lpuart_timer);
349 dmaengine_pause(sport->dma_rx_chan);
350 dmaengine_tx_status(sport->dma_rx_chan, sport->dma_rx_cookie, &state);
351 dmaengine_terminate_all(sport->dma_rx_chan);
352 count = FSL_UART_RX_DMA_BUFFER_SIZE - state.residue;
353 async_tx_ack(sport->dma_rx_desc);
354
355 spin_lock_irqsave(&sport->port.lock, flags);
356
357 sport->dma_rx_in_progress = 0;
358 lpuart_copy_rx_to_tty(sport, port, count);
359 tty_flip_buffer_push(port);
360 temp = readb(sport->port.membase + UARTCR5);
361 writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
362
363 spin_unlock_irqrestore(&sport->port.lock, flags);
364}
365
366static inline void lpuart_prepare_rx(struct lpuart_port *sport)
367{
368 unsigned long flags;
369 unsigned char temp;
370
371 spin_lock_irqsave(&sport->port.lock, flags);
372
373 init_timer(&sport->lpuart_timer);
374 sport->lpuart_timer.function = lpuart_timer_func;
375 sport->lpuart_timer.data = (unsigned long)sport;
376 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
377 add_timer(&sport->lpuart_timer);
378
379 lpuart_dma_rx(sport);
380 temp = readb(sport->port.membase + UARTCR5);
381 writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5);
382
383 spin_unlock_irqrestore(&sport->port.lock, flags);
384}
385
c9e2e946
JL		 386static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
387{
388 struct circ_buf *xmit = &sport->port.state->xmit;
389
390 while (!uart_circ_empty(xmit) &&
391 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
392 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
393 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
394 sport->port.icount.tx++;
395 }
396
397 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
398 uart_write_wakeup(&sport->port);
399
400 if (uart_circ_empty(xmit))
401 lpuart_stop_tx(&sport->port);
402}
403
404static void lpuart_start_tx(struct uart_port *port)
405{
f1cd8c87
YY		 406 struct lpuart_port *sport = container_of(port,
407 struct lpuart_port, port);
408 struct circ_buf *xmit = &sport->port.state->xmit;
c9e2e946
JL		 409 unsigned char temp;
410
411 temp = readb(port->membase + UARTCR2);
412 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
413
f1cd8c87
YY		 414 if (sport->lpuart_dma_use) {
415 if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress)
416 lpuart_prepare_tx(sport);
417 } else {
418 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
419 lpuart_transmit_buffer(sport);
420 }
c9e2e946
JL		 421}
422
423static irqreturn_t lpuart_txint(int irq, void *dev_id)
424{
425 struct lpuart_port *sport = dev_id;
426 struct circ_buf *xmit = &sport->port.state->xmit;
427 unsigned long flags;
428
429 spin_lock_irqsave(&sport->port.lock, flags);
430 if (sport->port.x_char) {
431 writeb(sport->port.x_char, sport->port.membase + UARTDR);
432 goto out;
433 }
434
435 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
436 lpuart_stop_tx(&sport->port);
437 goto out;
438 }
439
440 lpuart_transmit_buffer(sport);
441
442 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
443 uart_write_wakeup(&sport->port);
444
445out:
446 spin_unlock_irqrestore(&sport->port.lock, flags);
447 return IRQ_HANDLED;
448}
449
450static irqreturn_t lpuart_rxint(int irq, void *dev_id)
451{
452 struct lpuart_port *sport = dev_id;
453 unsigned int flg, ignored = 0;
454 struct tty_port *port = &sport->port.state->port;
455 unsigned long flags;
456 unsigned char rx, sr;
457
458 spin_lock_irqsave(&sport->port.lock, flags);
459
460 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
461 flg = TTY_NORMAL;
462 sport->port.icount.rx++;
463 /*
464 * to clear the FE, OR, NF, FE, PE flags,
465 * read SR1 then read DR
466 */
467 sr = readb(sport->port.membase + UARTSR1);
468 rx = readb(sport->port.membase + UARTDR);
469
470 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
471 continue;
472
473 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
474 if (sr & UARTSR1_PE)
475 sport->port.icount.parity++;
476 else if (sr & UARTSR1_FE)
477 sport->port.icount.frame++;
478
479 if (sr & UARTSR1_OR)
480 sport->port.icount.overrun++;
481
482 if (sr & sport->port.ignore_status_mask) {
483 if (++ignored > 100)
484 goto out;
485 continue;
486 }
487
488 sr &= sport->port.read_status_mask;
489
490 if (sr & UARTSR1_PE)
491 flg = TTY_PARITY;
492 else if (sr & UARTSR1_FE)
493 flg = TTY_FRAME;
494
495 if (sr & UARTSR1_OR)
496 flg = TTY_OVERRUN;
497
498#ifdef SUPPORT_SYSRQ
499 sport->port.sysrq = 0;
500#endif
501 }
502
503 tty_insert_flip_char(port, rx, flg);
504 }
505
506out:
507 spin_unlock_irqrestore(&sport->port.lock, flags);
508
509 tty_flip_buffer_push(port);
510 return IRQ_HANDLED;
511}
512
513static irqreturn_t lpuart_int(int irq, void *dev_id)
514{
515 struct lpuart_port *sport = dev_id;
516 unsigned char sts;
517
518 sts = readb(sport->port.membase + UARTSR1);
519
f1cd8c87
YY		 520 if (sts & UARTSR1_RDRF) {
521 if (sport->lpuart_dma_use)
522 lpuart_prepare_rx(sport);
523 else
524 lpuart_rxint(irq, dev_id);
525 }
c9e2e946 526 if (sts & UARTSR1_TDRE &&
f1cd8c87
YY		 527 !(readb(sport->port.membase + UARTCR5) & UARTCR5_TDMAS)) {
528 if (sport->lpuart_dma_use)
529 lpuart_pio_tx(sport);
530 else
531 lpuart_txint(irq, dev_id);
532 }
c9e2e946
JL		 533
534 return IRQ_HANDLED;
535}
536
537/* return TIOCSER_TEMT when transmitter is not busy */
538static unsigned int lpuart_tx_empty(struct uart_port *port)
539{
540 return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
541 TIOCSER_TEMT : 0;
542}
543
544static unsigned int lpuart_get_mctrl(struct uart_port *port)
545{
546 unsigned int temp = 0;
547 unsigned char reg;
548
549 reg = readb(port->membase + UARTMODEM);
550 if (reg & UARTMODEM_TXCTSE)
551 temp |= TIOCM_CTS;
552
553 if (reg & UARTMODEM_RXRTSE)
554 temp |= TIOCM_RTS;
555
556 return temp;
557}
558
559static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
560{
561 unsigned char temp;
562
563 temp = readb(port->membase + UARTMODEM) &
564 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
565
566 if (mctrl & TIOCM_RTS)
567 temp |= UARTMODEM_RXRTSE;
568
569 if (mctrl & TIOCM_CTS)
570 temp |= UARTMODEM_TXCTSE;
571
572 writeb(temp, port->membase + UARTMODEM);
573}
574
575static void lpuart_break_ctl(struct uart_port *port, int break_state)
576{
577 unsigned char temp;
578
579 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
580
581 if (break_state != 0)
582 temp |= UARTCR2_SBK;
583
584 writeb(temp, port->membase + UARTCR2);
585}
586
587static void lpuart_setup_watermark(struct lpuart_port *sport)
588{
589 unsigned char val, cr2;
bc764b8f 590 unsigned char cr2_saved;
c9e2e946
JL		 591
592 cr2 = readb(sport->port.membase + UARTCR2);
bc764b8f 593 cr2_saved = cr2;
c9e2e946
JL		 594 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
595 UARTCR2_RIE | UARTCR2_RE);
596 writeb(cr2, sport->port.membase + UARTCR2);
597
598 /* determine FIFO size and enable FIFO mode */
599 val = readb(sport->port.membase + UARTPFIFO);
600
601 sport->txfifo_size = 0x1 << (((val >> UARTPFIFO_TXSIZE_OFF) &
602 UARTPFIFO_FIFOSIZE_MASK) + 1);
603
604 sport->rxfifo_size = 0x1 << (((val >> UARTPFIFO_RXSIZE_OFF) &
605 UARTPFIFO_FIFOSIZE_MASK) + 1);
606
607 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
608 sport->port.membase + UARTPFIFO);
609
610 /* flush Tx and Rx FIFO */
611 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
612 sport->port.membase + UARTCFIFO);
613
f1cd8c87 614 writeb(0, sport->port.membase + UARTTWFIFO);
c9e2e946 615 writeb(1, sport->port.membase + UARTRWFIFO);
bc764b8f
SG		 616
617 /* Restore cr2 */
618 writeb(cr2_saved, sport->port.membase + UARTCR2);
c9e2e946
JL		 619}
620
f1cd8c87
YY		 621static int lpuart_dma_tx_request(struct uart_port *port)
622{
623 struct lpuart_port *sport = container_of(port,
624 struct lpuart_port, port);
625 struct dma_chan *tx_chan;
626 struct dma_slave_config dma_tx_sconfig;
627 dma_addr_t dma_bus;
628 unsigned char *dma_buf;
629 int ret;
630
631 tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
632
633 if (!tx_chan) {
634 dev_err(sport->port.dev, "Dma tx channel request failed!\n");
635 return -ENODEV;
636 }
637
638 dma_bus = dma_map_single(tx_chan->device->dev,
639 sport->port.state->xmit.buf,
640 UART_XMIT_SIZE, DMA_TO_DEVICE);
641
642 if (dma_mapping_error(tx_chan->device->dev, dma_bus)) {
643 dev_err(sport->port.dev, "dma_map_single tx failed\n");
644 dma_release_channel(tx_chan);
645 return -ENOMEM;
646 }
647
648 dma_buf = sport->port.state->xmit.buf;
649 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
650 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
651 dma_tx_sconfig.dst_maxburst = DMA_MAXBURST;
652 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
653 ret = dmaengine_slave_config(tx_chan, &dma_tx_sconfig);
654
655 if (ret < 0) {
656 dev_err(sport->port.dev,
657 "Dma slave config failed, err = %d\n", ret);
658 dma_release_channel(tx_chan);
659 return ret;
660 }
661
662 sport->dma_tx_chan = tx_chan;
663 sport->dma_tx_buf_virt = dma_buf;
664 sport->dma_tx_buf_bus = dma_bus;
665 sport->dma_tx_in_progress = 0;
666
667 return 0;
668}
669
670static int lpuart_dma_rx_request(struct uart_port *port)
671{
672 struct lpuart_port *sport = container_of(port,
673 struct lpuart_port, port);
674 struct dma_chan *rx_chan;
675 struct dma_slave_config dma_rx_sconfig;
676 dma_addr_t dma_bus;
677 unsigned char *dma_buf;
678 int ret;
679
680 rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
681
682 if (!rx_chan) {
683 dev_err(sport->port.dev, "Dma rx channel request failed!\n");
684 return -ENODEV;
685 }
686
687 dma_buf = devm_kzalloc(sport->port.dev,
688 FSL_UART_RX_DMA_BUFFER_SIZE, GFP_KERNEL);
689
690 if (!dma_buf) {
691 dev_err(sport->port.dev, "Dma rx alloc failed\n");
692 dma_release_channel(rx_chan);
693 return -ENOMEM;
694 }
695
696 dma_bus = dma_map_single(rx_chan->device->dev, dma_buf,
697 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
698
699 if (dma_mapping_error(rx_chan->device->dev, dma_bus)) {
700 dev_err(sport->port.dev, "dma_map_single rx failed\n");
701 dma_release_channel(rx_chan);
702 return -ENOMEM;
703 }
704
705 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
706 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
707 dma_rx_sconfig.src_maxburst = 1;
708 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
709 ret = dmaengine_slave_config(rx_chan, &dma_rx_sconfig);
710
711 if (ret < 0) {
712 dev_err(sport->port.dev,
713 "Dma slave config failed, err = %d\n", ret);
714 dma_release_channel(rx_chan);
715 return ret;
716 }
717
718 sport->dma_rx_chan = rx_chan;
719 sport->dma_rx_buf_virt = dma_buf;
720 sport->dma_rx_buf_bus = dma_bus;
721 sport->dma_rx_in_progress = 0;
722
f1cd8c87
YY		 723 return 0;
724}
725
726static void lpuart_dma_tx_free(struct uart_port *port)
727{
728 struct lpuart_port *sport = container_of(port,
729 struct lpuart_port, port);
730 struct dma_chan *dma_chan;
731
732 dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus,
733 UART_XMIT_SIZE, DMA_TO_DEVICE);
734 dma_chan = sport->dma_tx_chan;
735 sport->dma_tx_chan = NULL;
736 sport->dma_tx_buf_bus = 0;
737 sport->dma_tx_buf_virt = NULL;
738 dma_release_channel(dma_chan);
739}
740
741static void lpuart_dma_rx_free(struct uart_port *port)
742{
743 struct lpuart_port *sport = container_of(port,
744 struct lpuart_port, port);
745 struct dma_chan *dma_chan;
746
747 dma_unmap_single(sport->port.dev, sport->dma_rx_buf_bus,
748 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
749
750 dma_chan = sport->dma_rx_chan;
751 sport->dma_rx_chan = NULL;
752 sport->dma_rx_buf_bus = 0;
753 sport->dma_rx_buf_virt = NULL;
754 dma_release_channel(dma_chan);
755}
756
c9e2e946
JL		 757static int lpuart_startup(struct uart_port *port)
758{
759 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
760 int ret;
761 unsigned long flags;
762 unsigned char temp;
763
f1cd8c87
YY		 764 /*whether use dma support by dma request results*/
765 if (lpuart_dma_tx_request(port) || lpuart_dma_rx_request(port)) {
766 sport->lpuart_dma_use = false;
767 } else {
768 sport->lpuart_dma_use = true;
769 temp = readb(port->membase + UARTCR5);
770 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
771 }
772
c9e2e946
JL		 773 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
774 DRIVER_NAME, sport);
775 if (ret)
776 return ret;
777
778 spin_lock_irqsave(&sport->port.lock, flags);
779
780 lpuart_setup_watermark(sport);
781
782 temp = readb(sport->port.membase + UARTCR2);
783 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
784 writeb(temp, sport->port.membase + UARTCR2);
785
786 spin_unlock_irqrestore(&sport->port.lock, flags);
787 return 0;
788}
789
790static void lpuart_shutdown(struct uart_port *port)
791{
792 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
793 unsigned char temp;
794 unsigned long flags;
795
796 spin_lock_irqsave(&port->lock, flags);
797
798 /* disable Rx/Tx and interrupts */
799 temp = readb(port->membase + UARTCR2);
800 temp &= ~(UARTCR2_TE | UARTCR2_RE |
801 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
802 writeb(temp, port->membase + UARTCR2);
803
804 spin_unlock_irqrestore(&port->lock, flags);
805
806 devm_free_irq(port->dev, port->irq, sport);
f1cd8c87
YY		 807
808 if (sport->lpuart_dma_use) {
809 lpuart_dma_tx_free(port);
810 lpuart_dma_rx_free(port);
811 }
c9e2e946
JL		 812}
813
814static void
815lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
816 struct ktermios *old)
817{
818 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
819 unsigned long flags;
820 unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
821 unsigned int baud;
822 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
823 unsigned int sbr, brfa;
824
825 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
826 old_cr2 = readb(sport->port.membase + UARTCR2);
827 cr4 = readb(sport->port.membase + UARTCR4);
828 bdh = readb(sport->port.membase + UARTBDH);
829 modem = readb(sport->port.membase + UARTMODEM);
830 /*
831 * only support CS8 and CS7, and for CS7 must enable PE.
832 * supported mode:
833 * - (7,e/o,1)
834 * - (8,n,1)
835 * - (8,m/s,1)
836 * - (8,e/o,1)
837 */
838 while ((termios->c_cflag & CSIZE) != CS8 &&
839 (termios->c_cflag & CSIZE) != CS7) {
840 termios->c_cflag &= ~CSIZE;
841 termios->c_cflag |= old_csize;
842 old_csize = CS8;
843 }
844
845 if ((termios->c_cflag & CSIZE) == CS8 ||
846 (termios->c_cflag & CSIZE) == CS7)
847 cr1 = old_cr1 & ~UARTCR1_M;
848
849 if (termios->c_cflag & CMSPAR) {
850 if ((termios->c_cflag & CSIZE) != CS8) {
851 termios->c_cflag &= ~CSIZE;
852 termios->c_cflag |= CS8;
853 }
854 cr1 |= UARTCR1_M;
855 }
856
857 if (termios->c_cflag & CRTSCTS) {
858 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
859 } else {
860 termios->c_cflag &= ~CRTSCTS;
861 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
862 }
863
864 if (termios->c_cflag & CSTOPB)
865 termios->c_cflag &= ~CSTOPB;
866
867 /* parity must be enabled when CS7 to match 8-bits format */
868 if ((termios->c_cflag & CSIZE) == CS7)
869 termios->c_cflag |= PARENB;
870
871 if ((termios->c_cflag & PARENB)) {
872 if (termios->c_cflag & CMSPAR) {
873 cr1 &= ~UARTCR1_PE;
874 cr1 |= UARTCR1_M;
875 } else {
876 cr1 |= UARTCR1_PE;
877 if ((termios->c_cflag & CSIZE) == CS8)
878 cr1 |= UARTCR1_M;
879 if (termios->c_cflag & PARODD)
880 cr1 |= UARTCR1_PT;
881 else
882 cr1 &= ~UARTCR1_PT;
883 }
884 }
885
886 /* ask the core to calculate the divisor */
887 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
888
889 spin_lock_irqsave(&sport->port.lock, flags);
890
891 sport->port.read_status_mask = 0;
892 if (termios->c_iflag & INPCK)
893 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
ef8b9ddc 894 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
c9e2e946
JL		 895 sport->port.read_status_mask |= UARTSR1_FE;
896
897 /* characters to ignore */
898 sport->port.ignore_status_mask = 0;
899 if (termios->c_iflag & IGNPAR)
900 sport->port.ignore_status_mask |= UARTSR1_PE;
901 if (termios->c_iflag & IGNBRK) {
902 sport->port.ignore_status_mask |= UARTSR1_FE;
903 /*
904 * if we're ignoring parity and break indicators,
905 * ignore overruns too (for real raw support).
906 */
907 if (termios->c_iflag & IGNPAR)
908 sport->port.ignore_status_mask |= UARTSR1_OR;
909 }
910
911 /* update the per-port timeout */
912 uart_update_timeout(port, termios->c_cflag, baud);
913
90abef91
SA		 914 if (sport->lpuart_dma_use) {
915 /* Calculate delay for 1.5 DMA buffers */
916 sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) *
917 FSL_UART_RX_DMA_BUFFER_SIZE * 3 /
918 sport->rxfifo_size / 2;
919 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
920 sport->dma_rx_timeout * 1000 / HZ, sport->port.timeout);
921 if (sport->dma_rx_timeout < msecs_to_jiffies(20))
922 sport->dma_rx_timeout = msecs_to_jiffies(20);
923 }
924
c9e2e946
JL		 925 /* wait transmit engin complete */
926 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
927 barrier();
928
929 /* disable transmit and receive */
930 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
931 sport->port.membase + UARTCR2);
932
933 sbr = sport->port.uartclk / (16 * baud);
934 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
935 bdh &= ~UARTBDH_SBR_MASK;
936 bdh |= (sbr >> 8) & 0x1F;
937 cr4 &= ~UARTCR4_BRFA_MASK;
938 brfa &= UARTCR4_BRFA_MASK;
939 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
940 writeb(bdh, sport->port.membase + UARTBDH);
941 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
942 writeb(cr1, sport->port.membase + UARTCR1);
943 writeb(modem, sport->port.membase + UARTMODEM);
944
945 /* restore control register */
946 writeb(old_cr2, sport->port.membase + UARTCR2);
947
948 spin_unlock_irqrestore(&sport->port.lock, flags);
949}
950
951static const char *lpuart_type(struct uart_port *port)
952{
953 return "FSL_LPUART";
954}
955
956static void lpuart_release_port(struct uart_port *port)
957{
958 /* nothing to do */
959}
960
961static int lpuart_request_port(struct uart_port *port)
962{
963 return 0;
964}
965
966/* configure/autoconfigure the port */
967static void lpuart_config_port(struct uart_port *port, int flags)
968{
969 if (flags & UART_CONFIG_TYPE)
970 port->type = PORT_LPUART;
971}
972
973static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
974{
975 int ret = 0;
976
977 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
978 ret = -EINVAL;
979 if (port->irq != ser->irq)
980 ret = -EINVAL;
981 if (ser->io_type != UPIO_MEM)
982 ret = -EINVAL;
983 if (port->uartclk / 16 != ser->baud_base)
984 ret = -EINVAL;
985 if (port->iobase != ser->port)
986 ret = -EINVAL;
987 if (ser->hub6 != 0)
988 ret = -EINVAL;
989 return ret;
990}
991
992static struct uart_ops lpuart_pops = {
993 .tx_empty = lpuart_tx_empty,
994 .set_mctrl = lpuart_set_mctrl,
995 .get_mctrl = lpuart_get_mctrl,
996 .stop_tx = lpuart_stop_tx,
997 .start_tx = lpuart_start_tx,
998 .stop_rx = lpuart_stop_rx,
c9e2e946
JL		 999 .break_ctl = lpuart_break_ctl,
1000 .startup = lpuart_startup,
1001 .shutdown = lpuart_shutdown,
1002 .set_termios = lpuart_set_termios,
1003 .type = lpuart_type,
1004 .request_port = lpuart_request_port,
1005 .release_port = lpuart_release_port,
1006 .config_port = lpuart_config_port,
1007 .verify_port = lpuart_verify_port,
1008};
1009
1010static struct lpuart_port *lpuart_ports[UART_NR];
1011
1012#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1013static void lpuart_console_putchar(struct uart_port *port, int ch)
1014{
1015 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1016 barrier();
1017
1018 writeb(ch, port->membase + UARTDR);
1019}
1020
1021static void
1022lpuart_console_write(struct console *co, const char *s, unsigned int count)
1023{
1024 struct lpuart_port *sport = lpuart_ports[co->index];
1025 unsigned char old_cr2, cr2;
1026
1027 /* first save CR2 and then disable interrupts */
1028 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1029 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1030 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1031 writeb(cr2, sport->port.membase + UARTCR2);
1032
1033 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1034
1035 /* wait for transmitter finish complete and restore CR2 */
1036 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1037 barrier();
1038
1039 writeb(old_cr2, sport->port.membase + UARTCR2);
1040}
1041
1042/*
1043 * if the port was already initialised (eg, by a boot loader),
1044 * try to determine the current setup.
1045 */
1046static void __init
1047lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1048 int *parity, int *bits)
1049{
1050 unsigned char cr, bdh, bdl, brfa;
1051 unsigned int sbr, uartclk, baud_raw;
1052
1053 cr = readb(sport->port.membase + UARTCR2);
1054 cr &= UARTCR2_TE | UARTCR2_RE;
1055 if (!cr)
1056 return;
1057
1058 /* ok, the port was enabled */
1059
1060 cr = readb(sport->port.membase + UARTCR1);
1061
1062 *parity = 'n';
1063 if (cr & UARTCR1_PE) {
1064 if (cr & UARTCR1_PT)
1065 *parity = 'o';
1066 else
1067 *parity = 'e';
1068 }
1069
1070 if (cr & UARTCR1_M)
1071 *bits = 9;
1072 else
1073 *bits = 8;
1074
1075 bdh = readb(sport->port.membase + UARTBDH);
1076 bdh &= UARTBDH_SBR_MASK;
1077 bdl = readb(sport->port.membase + UARTBDL);
1078 sbr = bdh;
1079 sbr <<= 8;
1080 sbr |= bdl;
1081 brfa = readb(sport->port.membase + UARTCR4);
1082 brfa &= UARTCR4_BRFA_MASK;
1083
1084 uartclk = clk_get_rate(sport->clk);
1085 /*
1086 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1087 */
1088 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1089
1090 if (*baud != baud_raw)
1091 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1092 "from %d to %d\n", baud_raw, *baud);
1093}
1094
1095static int __init lpuart_console_setup(struct console *co, char *options)
1096{
1097 struct lpuart_port *sport;
1098 int baud = 115200;
1099 int bits = 8;
1100 int parity = 'n';
1101 int flow = 'n';
1102
1103 /*
1104 * check whether an invalid uart number has been specified, and
1105 * if so, search for the first available port that does have
1106 * console support.
1107 */
1108 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1109 co->index = 0;
1110
1111 sport = lpuart_ports[co->index];
1112 if (sport == NULL)
1113 return -ENODEV;
1114
1115 if (options)
1116 uart_parse_options(options, &baud, &parity, &bits, &flow);
1117 else
1118 lpuart_console_get_options(sport, &baud, &parity, &bits);
1119
1120 lpuart_setup_watermark(sport);
1121
1122 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1123}
1124
1125static struct uart_driver lpuart_reg;
1126static struct console lpuart_console = {
1127 .name = DEV_NAME,
1128 .write = lpuart_console_write,
1129 .device = uart_console_device,
1130 .setup = lpuart_console_setup,
1131 .flags = CON_PRINTBUFFER,
1132 .index = -1,
1133 .data = &lpuart_reg,
1134};
1135
1136#define LPUART_CONSOLE (&lpuart_console)
1137#else
1138#define LPUART_CONSOLE NULL
1139#endif
1140
1141static struct uart_driver lpuart_reg = {
1142 .owner = THIS_MODULE,
1143 .driver_name = DRIVER_NAME,
1144 .dev_name = DEV_NAME,
1145 .nr = ARRAY_SIZE(lpuart_ports),
1146 .cons = LPUART_CONSOLE,
1147};
1148
1149static int lpuart_probe(struct platform_device *pdev)
1150{
1151 struct device_node *np = pdev->dev.of_node;
1152 struct lpuart_port *sport;
1153 struct resource *res;
1154 int ret;
1155
1156 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1157 if (!sport)
1158 return -ENOMEM;
1159
1160 pdev->dev.coherent_dma_mask = 0;
1161
1162 ret = of_alias_get_id(np, "serial");
1163 if (ret < 0) {
1164 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1165 return ret;
1166 }
1167 sport->port.line = ret;
1168
1169 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1170 if (!res)
1171 return -ENODEV;
1172
1173 sport->port.mapbase = res->start;
1174 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1175 if (IS_ERR(sport->port.membase))
1176 return PTR_ERR(sport->port.membase);
1177
1178 sport->port.dev = &pdev->dev;
1179 sport->port.type = PORT_LPUART;
1180 sport->port.iotype = UPIO_MEM;
1181 sport->port.irq = platform_get_irq(pdev, 0);
1182 sport->port.ops = &lpuart_pops;
1183 sport->port.flags = UPF_BOOT_AUTOCONF;
1184
1185 sport->clk = devm_clk_get(&pdev->dev, "ipg");
1186 if (IS_ERR(sport->clk)) {
1187 ret = PTR_ERR(sport->clk);
1188 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1189 return ret;
1190 }
1191
1192 ret = clk_prepare_enable(sport->clk);
1193 if (ret) {
1194 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1195 return ret;
1196 }
1197
1198 sport->port.uartclk = clk_get_rate(sport->clk);
1199
1200 lpuart_ports[sport->port.line] = sport;
1201
1202 platform_set_drvdata(pdev, &sport->port);
1203
1204 ret = uart_add_one_port(&lpuart_reg, &sport->port);
1205 if (ret) {
1206 clk_disable_unprepare(sport->clk);
1207 return ret;
1208 }
1209
1210 return 0;
1211}
1212
1213static int lpuart_remove(struct platform_device *pdev)
1214{
1215 struct lpuart_port *sport = platform_get_drvdata(pdev);
1216
1217 uart_remove_one_port(&lpuart_reg, &sport->port);
1218
1219 clk_disable_unprepare(sport->clk);
1220
1221 return 0;
1222}
1223
1224#ifdef CONFIG_PM_SLEEP
1225static int lpuart_suspend(struct device *dev)
1226{
1227 struct lpuart_port *sport = dev_get_drvdata(dev);
1228
1229 uart_suspend_port(&lpuart_reg, &sport->port);
1230
1231 return 0;
1232}
1233
1234static int lpuart_resume(struct device *dev)
1235{
1236 struct lpuart_port *sport = dev_get_drvdata(dev);
1237
1238 uart_resume_port(&lpuart_reg, &sport->port);
1239
1240 return 0;
1241}
1242#endif
1243
1244static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
1245
1246static struct platform_driver lpuart_driver = {
1247 .probe = lpuart_probe,
1248 .remove = lpuart_remove,
1249 .driver = {
1250 .name = "fsl-lpuart",
1251 .owner = THIS_MODULE,
1252 .of_match_table = lpuart_dt_ids,
1253 .pm = &lpuart_pm_ops,
1254 },
1255};
1256
1257static int __init lpuart_serial_init(void)
1258{
1259 int ret;
1260
1261 pr_info("serial: Freescale lpuart driver\n");
1262
1263 ret = uart_register_driver(&lpuart_reg);
1264 if (ret)
1265 return ret;
1266
1267 ret = platform_driver_register(&lpuart_driver);
1268 if (ret)
1269 uart_unregister_driver(&lpuart_reg);
1270
39c34b09 1271 return ret;
c9e2e946
JL		 1272}
1273
1274static void __exit lpuart_serial_exit(void)
1275{
1276 platform_driver_unregister(&lpuart_driver);
1277 uart_unregister_driver(&lpuart_reg);
1278}
1279
1280module_init(lpuart_serial_init);
1281module_exit(lpuart_serial_exit);
1282
1283MODULE_DESCRIPTION("Freescale lpuart serial port driver");
1284MODULE_LICENSE("GPL v2");
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