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c9e2e946 JL |
1 | /* |
2 | * Freescale lpuart serial port driver | |
3 | * | |
4 | * Copyright 2012-2013 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
13 | #define SUPPORT_SYSRQ | |
14 | #endif | |
15 | ||
16 | #include <linux/module.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/irq.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/of_device.h> | |
22 | #include <linux/console.h> | |
23 | #include <linux/serial_core.h> | |
24 | #include <linux/tty_flip.h> | |
25 | ||
26 | /* All registers are 8-bit width */ | |
27 | #define UARTBDH 0x00 | |
28 | #define UARTBDL 0x01 | |
29 | #define UARTCR1 0x02 | |
30 | #define UARTCR2 0x03 | |
31 | #define UARTSR1 0x04 | |
32 | #define UARTCR3 0x06 | |
33 | #define UARTDR 0x07 | |
34 | #define UARTCR4 0x0a | |
35 | #define UARTCR5 0x0b | |
36 | #define UARTMODEM 0x0d | |
37 | #define UARTPFIFO 0x10 | |
38 | #define UARTCFIFO 0x11 | |
39 | #define UARTSFIFO 0x12 | |
40 | #define UARTTWFIFO 0x13 | |
41 | #define UARTTCFIFO 0x14 | |
42 | #define UARTRWFIFO 0x15 | |
43 | ||
44 | #define UARTBDH_LBKDIE 0x80 | |
45 | #define UARTBDH_RXEDGIE 0x40 | |
46 | #define UARTBDH_SBR_MASK 0x1f | |
47 | ||
48 | #define UARTCR1_LOOPS 0x80 | |
49 | #define UARTCR1_RSRC 0x20 | |
50 | #define UARTCR1_M 0x10 | |
51 | #define UARTCR1_WAKE 0x08 | |
52 | #define UARTCR1_ILT 0x04 | |
53 | #define UARTCR1_PE 0x02 | |
54 | #define UARTCR1_PT 0x01 | |
55 | ||
56 | #define UARTCR2_TIE 0x80 | |
57 | #define UARTCR2_TCIE 0x40 | |
58 | #define UARTCR2_RIE 0x20 | |
59 | #define UARTCR2_ILIE 0x10 | |
60 | #define UARTCR2_TE 0x08 | |
61 | #define UARTCR2_RE 0x04 | |
62 | #define UARTCR2_RWU 0x02 | |
63 | #define UARTCR2_SBK 0x01 | |
64 | ||
65 | #define UARTSR1_TDRE 0x80 | |
66 | #define UARTSR1_TC 0x40 | |
67 | #define UARTSR1_RDRF 0x20 | |
68 | #define UARTSR1_IDLE 0x10 | |
69 | #define UARTSR1_OR 0x08 | |
70 | #define UARTSR1_NF 0x04 | |
71 | #define UARTSR1_FE 0x02 | |
72 | #define UARTSR1_PE 0x01 | |
73 | ||
74 | #define UARTCR3_R8 0x80 | |
75 | #define UARTCR3_T8 0x40 | |
76 | #define UARTCR3_TXDIR 0x20 | |
77 | #define UARTCR3_TXINV 0x10 | |
78 | #define UARTCR3_ORIE 0x08 | |
79 | #define UARTCR3_NEIE 0x04 | |
80 | #define UARTCR3_FEIE 0x02 | |
81 | #define UARTCR3_PEIE 0x01 | |
82 | ||
83 | #define UARTCR4_MAEN1 0x80 | |
84 | #define UARTCR4_MAEN2 0x40 | |
85 | #define UARTCR4_M10 0x20 | |
86 | #define UARTCR4_BRFA_MASK 0x1f | |
87 | #define UARTCR4_BRFA_OFF 0 | |
88 | ||
89 | #define UARTCR5_TDMAS 0x80 | |
90 | #define UARTCR5_RDMAS 0x20 | |
91 | ||
92 | #define UARTMODEM_RXRTSE 0x08 | |
93 | #define UARTMODEM_TXRTSPOL 0x04 | |
94 | #define UARTMODEM_TXRTSE 0x02 | |
95 | #define UARTMODEM_TXCTSE 0x01 | |
96 | ||
97 | #define UARTPFIFO_TXFE 0x80 | |
98 | #define UARTPFIFO_FIFOSIZE_MASK 0x7 | |
99 | #define UARTPFIFO_TXSIZE_OFF 4 | |
100 | #define UARTPFIFO_RXFE 0x08 | |
101 | #define UARTPFIFO_RXSIZE_OFF 0 | |
102 | ||
103 | #define UARTCFIFO_TXFLUSH 0x80 | |
104 | #define UARTCFIFO_RXFLUSH 0x40 | |
105 | #define UARTCFIFO_RXOFE 0x04 | |
106 | #define UARTCFIFO_TXOFE 0x02 | |
107 | #define UARTCFIFO_RXUFE 0x01 | |
108 | ||
109 | #define UARTSFIFO_TXEMPT 0x80 | |
110 | #define UARTSFIFO_RXEMPT 0x40 | |
111 | #define UARTSFIFO_RXOF 0x04 | |
112 | #define UARTSFIFO_TXOF 0x02 | |
113 | #define UARTSFIFO_RXUF 0x01 | |
114 | ||
115 | #define DRIVER_NAME "fsl-lpuart" | |
116 | #define DEV_NAME "ttyLP" | |
117 | #define UART_NR 6 | |
118 | ||
119 | struct lpuart_port { | |
120 | struct uart_port port; | |
121 | struct clk *clk; | |
122 | unsigned int txfifo_size; | |
123 | unsigned int rxfifo_size; | |
124 | }; | |
125 | ||
126 | static struct of_device_id lpuart_dt_ids[] = { | |
127 | { | |
128 | .compatible = "fsl,vf610-lpuart", | |
129 | }, | |
130 | { /* sentinel */ } | |
131 | }; | |
132 | MODULE_DEVICE_TABLE(of, lpuart_dt_ids); | |
133 | ||
134 | static void lpuart_stop_tx(struct uart_port *port) | |
135 | { | |
136 | unsigned char temp; | |
137 | ||
138 | temp = readb(port->membase + UARTCR2); | |
139 | temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); | |
140 | writeb(temp, port->membase + UARTCR2); | |
141 | } | |
142 | ||
143 | static void lpuart_stop_rx(struct uart_port *port) | |
144 | { | |
145 | unsigned char temp; | |
146 | ||
147 | temp = readb(port->membase + UARTCR2); | |
148 | writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); | |
149 | } | |
150 | ||
151 | static void lpuart_enable_ms(struct uart_port *port) | |
152 | { | |
153 | } | |
154 | ||
155 | static inline void lpuart_transmit_buffer(struct lpuart_port *sport) | |
156 | { | |
157 | struct circ_buf *xmit = &sport->port.state->xmit; | |
158 | ||
159 | while (!uart_circ_empty(xmit) && | |
160 | (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { | |
161 | writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); | |
162 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
163 | sport->port.icount.tx++; | |
164 | } | |
165 | ||
166 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
167 | uart_write_wakeup(&sport->port); | |
168 | ||
169 | if (uart_circ_empty(xmit)) | |
170 | lpuart_stop_tx(&sport->port); | |
171 | } | |
172 | ||
173 | static void lpuart_start_tx(struct uart_port *port) | |
174 | { | |
175 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
176 | unsigned char temp; | |
177 | ||
178 | temp = readb(port->membase + UARTCR2); | |
179 | writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); | |
180 | ||
181 | if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) | |
182 | lpuart_transmit_buffer(sport); | |
183 | } | |
184 | ||
185 | static irqreturn_t lpuart_txint(int irq, void *dev_id) | |
186 | { | |
187 | struct lpuart_port *sport = dev_id; | |
188 | struct circ_buf *xmit = &sport->port.state->xmit; | |
189 | unsigned long flags; | |
190 | ||
191 | spin_lock_irqsave(&sport->port.lock, flags); | |
192 | if (sport->port.x_char) { | |
193 | writeb(sport->port.x_char, sport->port.membase + UARTDR); | |
194 | goto out; | |
195 | } | |
196 | ||
197 | if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { | |
198 | lpuart_stop_tx(&sport->port); | |
199 | goto out; | |
200 | } | |
201 | ||
202 | lpuart_transmit_buffer(sport); | |
203 | ||
204 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
205 | uart_write_wakeup(&sport->port); | |
206 | ||
207 | out: | |
208 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
209 | return IRQ_HANDLED; | |
210 | } | |
211 | ||
212 | static irqreturn_t lpuart_rxint(int irq, void *dev_id) | |
213 | { | |
214 | struct lpuart_port *sport = dev_id; | |
215 | unsigned int flg, ignored = 0; | |
216 | struct tty_port *port = &sport->port.state->port; | |
217 | unsigned long flags; | |
218 | unsigned char rx, sr; | |
219 | ||
220 | spin_lock_irqsave(&sport->port.lock, flags); | |
221 | ||
222 | while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { | |
223 | flg = TTY_NORMAL; | |
224 | sport->port.icount.rx++; | |
225 | /* | |
226 | * to clear the FE, OR, NF, FE, PE flags, | |
227 | * read SR1 then read DR | |
228 | */ | |
229 | sr = readb(sport->port.membase + UARTSR1); | |
230 | rx = readb(sport->port.membase + UARTDR); | |
231 | ||
232 | if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) | |
233 | continue; | |
234 | ||
235 | if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { | |
236 | if (sr & UARTSR1_PE) | |
237 | sport->port.icount.parity++; | |
238 | else if (sr & UARTSR1_FE) | |
239 | sport->port.icount.frame++; | |
240 | ||
241 | if (sr & UARTSR1_OR) | |
242 | sport->port.icount.overrun++; | |
243 | ||
244 | if (sr & sport->port.ignore_status_mask) { | |
245 | if (++ignored > 100) | |
246 | goto out; | |
247 | continue; | |
248 | } | |
249 | ||
250 | sr &= sport->port.read_status_mask; | |
251 | ||
252 | if (sr & UARTSR1_PE) | |
253 | flg = TTY_PARITY; | |
254 | else if (sr & UARTSR1_FE) | |
255 | flg = TTY_FRAME; | |
256 | ||
257 | if (sr & UARTSR1_OR) | |
258 | flg = TTY_OVERRUN; | |
259 | ||
260 | #ifdef SUPPORT_SYSRQ | |
261 | sport->port.sysrq = 0; | |
262 | #endif | |
263 | } | |
264 | ||
265 | tty_insert_flip_char(port, rx, flg); | |
266 | } | |
267 | ||
268 | out: | |
269 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
270 | ||
271 | tty_flip_buffer_push(port); | |
272 | return IRQ_HANDLED; | |
273 | } | |
274 | ||
275 | static irqreturn_t lpuart_int(int irq, void *dev_id) | |
276 | { | |
277 | struct lpuart_port *sport = dev_id; | |
278 | unsigned char sts; | |
279 | ||
280 | sts = readb(sport->port.membase + UARTSR1); | |
281 | ||
282 | if (sts & UARTSR1_RDRF) | |
283 | lpuart_rxint(irq, dev_id); | |
284 | ||
285 | if (sts & UARTSR1_TDRE && | |
286 | !(readb(sport->port.membase + UARTCR5) & UARTCR5_TDMAS)) | |
287 | lpuart_txint(irq, dev_id); | |
288 | ||
289 | return IRQ_HANDLED; | |
290 | } | |
291 | ||
292 | /* return TIOCSER_TEMT when transmitter is not busy */ | |
293 | static unsigned int lpuart_tx_empty(struct uart_port *port) | |
294 | { | |
295 | return (readb(port->membase + UARTSR1) & UARTSR1_TC) ? | |
296 | TIOCSER_TEMT : 0; | |
297 | } | |
298 | ||
299 | static unsigned int lpuart_get_mctrl(struct uart_port *port) | |
300 | { | |
301 | unsigned int temp = 0; | |
302 | unsigned char reg; | |
303 | ||
304 | reg = readb(port->membase + UARTMODEM); | |
305 | if (reg & UARTMODEM_TXCTSE) | |
306 | temp |= TIOCM_CTS; | |
307 | ||
308 | if (reg & UARTMODEM_RXRTSE) | |
309 | temp |= TIOCM_RTS; | |
310 | ||
311 | return temp; | |
312 | } | |
313 | ||
314 | static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
315 | { | |
316 | unsigned char temp; | |
317 | ||
318 | temp = readb(port->membase + UARTMODEM) & | |
319 | ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); | |
320 | ||
321 | if (mctrl & TIOCM_RTS) | |
322 | temp |= UARTMODEM_RXRTSE; | |
323 | ||
324 | if (mctrl & TIOCM_CTS) | |
325 | temp |= UARTMODEM_TXCTSE; | |
326 | ||
327 | writeb(temp, port->membase + UARTMODEM); | |
328 | } | |
329 | ||
330 | static void lpuart_break_ctl(struct uart_port *port, int break_state) | |
331 | { | |
332 | unsigned char temp; | |
333 | ||
334 | temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; | |
335 | ||
336 | if (break_state != 0) | |
337 | temp |= UARTCR2_SBK; | |
338 | ||
339 | writeb(temp, port->membase + UARTCR2); | |
340 | } | |
341 | ||
342 | static void lpuart_setup_watermark(struct lpuart_port *sport) | |
343 | { | |
344 | unsigned char val, cr2; | |
bc764b8f | 345 | unsigned char cr2_saved; |
c9e2e946 JL |
346 | |
347 | cr2 = readb(sport->port.membase + UARTCR2); | |
bc764b8f | 348 | cr2_saved = cr2; |
c9e2e946 JL |
349 | cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | |
350 | UARTCR2_RIE | UARTCR2_RE); | |
351 | writeb(cr2, sport->port.membase + UARTCR2); | |
352 | ||
353 | /* determine FIFO size and enable FIFO mode */ | |
354 | val = readb(sport->port.membase + UARTPFIFO); | |
355 | ||
356 | sport->txfifo_size = 0x1 << (((val >> UARTPFIFO_TXSIZE_OFF) & | |
357 | UARTPFIFO_FIFOSIZE_MASK) + 1); | |
358 | ||
359 | sport->rxfifo_size = 0x1 << (((val >> UARTPFIFO_RXSIZE_OFF) & | |
360 | UARTPFIFO_FIFOSIZE_MASK) + 1); | |
361 | ||
362 | writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, | |
363 | sport->port.membase + UARTPFIFO); | |
364 | ||
365 | /* flush Tx and Rx FIFO */ | |
366 | writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, | |
367 | sport->port.membase + UARTCFIFO); | |
368 | ||
369 | writeb(2, sport->port.membase + UARTTWFIFO); | |
370 | writeb(1, sport->port.membase + UARTRWFIFO); | |
bc764b8f SG |
371 | |
372 | /* Restore cr2 */ | |
373 | writeb(cr2_saved, sport->port.membase + UARTCR2); | |
c9e2e946 JL |
374 | } |
375 | ||
376 | static int lpuart_startup(struct uart_port *port) | |
377 | { | |
378 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
379 | int ret; | |
380 | unsigned long flags; | |
381 | unsigned char temp; | |
382 | ||
383 | ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0, | |
384 | DRIVER_NAME, sport); | |
385 | if (ret) | |
386 | return ret; | |
387 | ||
388 | spin_lock_irqsave(&sport->port.lock, flags); | |
389 | ||
390 | lpuart_setup_watermark(sport); | |
391 | ||
392 | temp = readb(sport->port.membase + UARTCR2); | |
393 | temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); | |
394 | writeb(temp, sport->port.membase + UARTCR2); | |
395 | ||
396 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
397 | return 0; | |
398 | } | |
399 | ||
400 | static void lpuart_shutdown(struct uart_port *port) | |
401 | { | |
402 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
403 | unsigned char temp; | |
404 | unsigned long flags; | |
405 | ||
406 | spin_lock_irqsave(&port->lock, flags); | |
407 | ||
408 | /* disable Rx/Tx and interrupts */ | |
409 | temp = readb(port->membase + UARTCR2); | |
410 | temp &= ~(UARTCR2_TE | UARTCR2_RE | | |
411 | UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); | |
412 | writeb(temp, port->membase + UARTCR2); | |
413 | ||
414 | spin_unlock_irqrestore(&port->lock, flags); | |
415 | ||
416 | devm_free_irq(port->dev, port->irq, sport); | |
417 | } | |
418 | ||
419 | static void | |
420 | lpuart_set_termios(struct uart_port *port, struct ktermios *termios, | |
421 | struct ktermios *old) | |
422 | { | |
423 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
424 | unsigned long flags; | |
425 | unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem; | |
426 | unsigned int baud; | |
427 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
428 | unsigned int sbr, brfa; | |
429 | ||
430 | cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); | |
431 | old_cr2 = readb(sport->port.membase + UARTCR2); | |
432 | cr4 = readb(sport->port.membase + UARTCR4); | |
433 | bdh = readb(sport->port.membase + UARTBDH); | |
434 | modem = readb(sport->port.membase + UARTMODEM); | |
435 | /* | |
436 | * only support CS8 and CS7, and for CS7 must enable PE. | |
437 | * supported mode: | |
438 | * - (7,e/o,1) | |
439 | * - (8,n,1) | |
440 | * - (8,m/s,1) | |
441 | * - (8,e/o,1) | |
442 | */ | |
443 | while ((termios->c_cflag & CSIZE) != CS8 && | |
444 | (termios->c_cflag & CSIZE) != CS7) { | |
445 | termios->c_cflag &= ~CSIZE; | |
446 | termios->c_cflag |= old_csize; | |
447 | old_csize = CS8; | |
448 | } | |
449 | ||
450 | if ((termios->c_cflag & CSIZE) == CS8 || | |
451 | (termios->c_cflag & CSIZE) == CS7) | |
452 | cr1 = old_cr1 & ~UARTCR1_M; | |
453 | ||
454 | if (termios->c_cflag & CMSPAR) { | |
455 | if ((termios->c_cflag & CSIZE) != CS8) { | |
456 | termios->c_cflag &= ~CSIZE; | |
457 | termios->c_cflag |= CS8; | |
458 | } | |
459 | cr1 |= UARTCR1_M; | |
460 | } | |
461 | ||
462 | if (termios->c_cflag & CRTSCTS) { | |
463 | modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); | |
464 | } else { | |
465 | termios->c_cflag &= ~CRTSCTS; | |
466 | modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); | |
467 | } | |
468 | ||
469 | if (termios->c_cflag & CSTOPB) | |
470 | termios->c_cflag &= ~CSTOPB; | |
471 | ||
472 | /* parity must be enabled when CS7 to match 8-bits format */ | |
473 | if ((termios->c_cflag & CSIZE) == CS7) | |
474 | termios->c_cflag |= PARENB; | |
475 | ||
476 | if ((termios->c_cflag & PARENB)) { | |
477 | if (termios->c_cflag & CMSPAR) { | |
478 | cr1 &= ~UARTCR1_PE; | |
479 | cr1 |= UARTCR1_M; | |
480 | } else { | |
481 | cr1 |= UARTCR1_PE; | |
482 | if ((termios->c_cflag & CSIZE) == CS8) | |
483 | cr1 |= UARTCR1_M; | |
484 | if (termios->c_cflag & PARODD) | |
485 | cr1 |= UARTCR1_PT; | |
486 | else | |
487 | cr1 &= ~UARTCR1_PT; | |
488 | } | |
489 | } | |
490 | ||
491 | /* ask the core to calculate the divisor */ | |
492 | baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); | |
493 | ||
494 | spin_lock_irqsave(&sport->port.lock, flags); | |
495 | ||
496 | sport->port.read_status_mask = 0; | |
497 | if (termios->c_iflag & INPCK) | |
498 | sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); | |
499 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
500 | sport->port.read_status_mask |= UARTSR1_FE; | |
501 | ||
502 | /* characters to ignore */ | |
503 | sport->port.ignore_status_mask = 0; | |
504 | if (termios->c_iflag & IGNPAR) | |
505 | sport->port.ignore_status_mask |= UARTSR1_PE; | |
506 | if (termios->c_iflag & IGNBRK) { | |
507 | sport->port.ignore_status_mask |= UARTSR1_FE; | |
508 | /* | |
509 | * if we're ignoring parity and break indicators, | |
510 | * ignore overruns too (for real raw support). | |
511 | */ | |
512 | if (termios->c_iflag & IGNPAR) | |
513 | sport->port.ignore_status_mask |= UARTSR1_OR; | |
514 | } | |
515 | ||
516 | /* update the per-port timeout */ | |
517 | uart_update_timeout(port, termios->c_cflag, baud); | |
518 | ||
519 | /* wait transmit engin complete */ | |
520 | while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) | |
521 | barrier(); | |
522 | ||
523 | /* disable transmit and receive */ | |
524 | writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), | |
525 | sport->port.membase + UARTCR2); | |
526 | ||
527 | sbr = sport->port.uartclk / (16 * baud); | |
528 | brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; | |
529 | bdh &= ~UARTBDH_SBR_MASK; | |
530 | bdh |= (sbr >> 8) & 0x1F; | |
531 | cr4 &= ~UARTCR4_BRFA_MASK; | |
532 | brfa &= UARTCR4_BRFA_MASK; | |
533 | writeb(cr4 | brfa, sport->port.membase + UARTCR4); | |
534 | writeb(bdh, sport->port.membase + UARTBDH); | |
535 | writeb(sbr & 0xFF, sport->port.membase + UARTBDL); | |
536 | writeb(cr1, sport->port.membase + UARTCR1); | |
537 | writeb(modem, sport->port.membase + UARTMODEM); | |
538 | ||
539 | /* restore control register */ | |
540 | writeb(old_cr2, sport->port.membase + UARTCR2); | |
541 | ||
542 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
543 | } | |
544 | ||
545 | static const char *lpuart_type(struct uart_port *port) | |
546 | { | |
547 | return "FSL_LPUART"; | |
548 | } | |
549 | ||
550 | static void lpuart_release_port(struct uart_port *port) | |
551 | { | |
552 | /* nothing to do */ | |
553 | } | |
554 | ||
555 | static int lpuart_request_port(struct uart_port *port) | |
556 | { | |
557 | return 0; | |
558 | } | |
559 | ||
560 | /* configure/autoconfigure the port */ | |
561 | static void lpuart_config_port(struct uart_port *port, int flags) | |
562 | { | |
563 | if (flags & UART_CONFIG_TYPE) | |
564 | port->type = PORT_LPUART; | |
565 | } | |
566 | ||
567 | static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) | |
568 | { | |
569 | int ret = 0; | |
570 | ||
571 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) | |
572 | ret = -EINVAL; | |
573 | if (port->irq != ser->irq) | |
574 | ret = -EINVAL; | |
575 | if (ser->io_type != UPIO_MEM) | |
576 | ret = -EINVAL; | |
577 | if (port->uartclk / 16 != ser->baud_base) | |
578 | ret = -EINVAL; | |
579 | if (port->iobase != ser->port) | |
580 | ret = -EINVAL; | |
581 | if (ser->hub6 != 0) | |
582 | ret = -EINVAL; | |
583 | return ret; | |
584 | } | |
585 | ||
586 | static struct uart_ops lpuart_pops = { | |
587 | .tx_empty = lpuart_tx_empty, | |
588 | .set_mctrl = lpuart_set_mctrl, | |
589 | .get_mctrl = lpuart_get_mctrl, | |
590 | .stop_tx = lpuart_stop_tx, | |
591 | .start_tx = lpuart_start_tx, | |
592 | .stop_rx = lpuart_stop_rx, | |
593 | .enable_ms = lpuart_enable_ms, | |
594 | .break_ctl = lpuart_break_ctl, | |
595 | .startup = lpuart_startup, | |
596 | .shutdown = lpuart_shutdown, | |
597 | .set_termios = lpuart_set_termios, | |
598 | .type = lpuart_type, | |
599 | .request_port = lpuart_request_port, | |
600 | .release_port = lpuart_release_port, | |
601 | .config_port = lpuart_config_port, | |
602 | .verify_port = lpuart_verify_port, | |
603 | }; | |
604 | ||
605 | static struct lpuart_port *lpuart_ports[UART_NR]; | |
606 | ||
607 | #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE | |
608 | static void lpuart_console_putchar(struct uart_port *port, int ch) | |
609 | { | |
610 | while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) | |
611 | barrier(); | |
612 | ||
613 | writeb(ch, port->membase + UARTDR); | |
614 | } | |
615 | ||
616 | static void | |
617 | lpuart_console_write(struct console *co, const char *s, unsigned int count) | |
618 | { | |
619 | struct lpuart_port *sport = lpuart_ports[co->index]; | |
620 | unsigned char old_cr2, cr2; | |
621 | ||
622 | /* first save CR2 and then disable interrupts */ | |
623 | cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); | |
624 | cr2 |= (UARTCR2_TE | UARTCR2_RE); | |
625 | cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); | |
626 | writeb(cr2, sport->port.membase + UARTCR2); | |
627 | ||
628 | uart_console_write(&sport->port, s, count, lpuart_console_putchar); | |
629 | ||
630 | /* wait for transmitter finish complete and restore CR2 */ | |
631 | while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) | |
632 | barrier(); | |
633 | ||
634 | writeb(old_cr2, sport->port.membase + UARTCR2); | |
635 | } | |
636 | ||
637 | /* | |
638 | * if the port was already initialised (eg, by a boot loader), | |
639 | * try to determine the current setup. | |
640 | */ | |
641 | static void __init | |
642 | lpuart_console_get_options(struct lpuart_port *sport, int *baud, | |
643 | int *parity, int *bits) | |
644 | { | |
645 | unsigned char cr, bdh, bdl, brfa; | |
646 | unsigned int sbr, uartclk, baud_raw; | |
647 | ||
648 | cr = readb(sport->port.membase + UARTCR2); | |
649 | cr &= UARTCR2_TE | UARTCR2_RE; | |
650 | if (!cr) | |
651 | return; | |
652 | ||
653 | /* ok, the port was enabled */ | |
654 | ||
655 | cr = readb(sport->port.membase + UARTCR1); | |
656 | ||
657 | *parity = 'n'; | |
658 | if (cr & UARTCR1_PE) { | |
659 | if (cr & UARTCR1_PT) | |
660 | *parity = 'o'; | |
661 | else | |
662 | *parity = 'e'; | |
663 | } | |
664 | ||
665 | if (cr & UARTCR1_M) | |
666 | *bits = 9; | |
667 | else | |
668 | *bits = 8; | |
669 | ||
670 | bdh = readb(sport->port.membase + UARTBDH); | |
671 | bdh &= UARTBDH_SBR_MASK; | |
672 | bdl = readb(sport->port.membase + UARTBDL); | |
673 | sbr = bdh; | |
674 | sbr <<= 8; | |
675 | sbr |= bdl; | |
676 | brfa = readb(sport->port.membase + UARTCR4); | |
677 | brfa &= UARTCR4_BRFA_MASK; | |
678 | ||
679 | uartclk = clk_get_rate(sport->clk); | |
680 | /* | |
681 | * baud = mod_clk/(16*(sbr[13]+(brfa)/32) | |
682 | */ | |
683 | baud_raw = uartclk / (16 * (sbr + brfa / 32)); | |
684 | ||
685 | if (*baud != baud_raw) | |
686 | printk(KERN_INFO "Serial: Console lpuart rounded baud rate" | |
687 | "from %d to %d\n", baud_raw, *baud); | |
688 | } | |
689 | ||
690 | static int __init lpuart_console_setup(struct console *co, char *options) | |
691 | { | |
692 | struct lpuart_port *sport; | |
693 | int baud = 115200; | |
694 | int bits = 8; | |
695 | int parity = 'n'; | |
696 | int flow = 'n'; | |
697 | ||
698 | /* | |
699 | * check whether an invalid uart number has been specified, and | |
700 | * if so, search for the first available port that does have | |
701 | * console support. | |
702 | */ | |
703 | if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) | |
704 | co->index = 0; | |
705 | ||
706 | sport = lpuart_ports[co->index]; | |
707 | if (sport == NULL) | |
708 | return -ENODEV; | |
709 | ||
710 | if (options) | |
711 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
712 | else | |
713 | lpuart_console_get_options(sport, &baud, &parity, &bits); | |
714 | ||
715 | lpuart_setup_watermark(sport); | |
716 | ||
717 | return uart_set_options(&sport->port, co, baud, parity, bits, flow); | |
718 | } | |
719 | ||
720 | static struct uart_driver lpuart_reg; | |
721 | static struct console lpuart_console = { | |
722 | .name = DEV_NAME, | |
723 | .write = lpuart_console_write, | |
724 | .device = uart_console_device, | |
725 | .setup = lpuart_console_setup, | |
726 | .flags = CON_PRINTBUFFER, | |
727 | .index = -1, | |
728 | .data = &lpuart_reg, | |
729 | }; | |
730 | ||
731 | #define LPUART_CONSOLE (&lpuart_console) | |
732 | #else | |
733 | #define LPUART_CONSOLE NULL | |
734 | #endif | |
735 | ||
736 | static struct uart_driver lpuart_reg = { | |
737 | .owner = THIS_MODULE, | |
738 | .driver_name = DRIVER_NAME, | |
739 | .dev_name = DEV_NAME, | |
740 | .nr = ARRAY_SIZE(lpuart_ports), | |
741 | .cons = LPUART_CONSOLE, | |
742 | }; | |
743 | ||
744 | static int lpuart_probe(struct platform_device *pdev) | |
745 | { | |
746 | struct device_node *np = pdev->dev.of_node; | |
747 | struct lpuart_port *sport; | |
748 | struct resource *res; | |
749 | int ret; | |
750 | ||
751 | sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); | |
752 | if (!sport) | |
753 | return -ENOMEM; | |
754 | ||
755 | pdev->dev.coherent_dma_mask = 0; | |
756 | ||
757 | ret = of_alias_get_id(np, "serial"); | |
758 | if (ret < 0) { | |
759 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); | |
760 | return ret; | |
761 | } | |
762 | sport->port.line = ret; | |
763 | ||
764 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
765 | if (!res) | |
766 | return -ENODEV; | |
767 | ||
768 | sport->port.mapbase = res->start; | |
769 | sport->port.membase = devm_ioremap_resource(&pdev->dev, res); | |
770 | if (IS_ERR(sport->port.membase)) | |
771 | return PTR_ERR(sport->port.membase); | |
772 | ||
773 | sport->port.dev = &pdev->dev; | |
774 | sport->port.type = PORT_LPUART; | |
775 | sport->port.iotype = UPIO_MEM; | |
776 | sport->port.irq = platform_get_irq(pdev, 0); | |
777 | sport->port.ops = &lpuart_pops; | |
778 | sport->port.flags = UPF_BOOT_AUTOCONF; | |
779 | ||
780 | sport->clk = devm_clk_get(&pdev->dev, "ipg"); | |
781 | if (IS_ERR(sport->clk)) { | |
782 | ret = PTR_ERR(sport->clk); | |
783 | dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret); | |
784 | return ret; | |
785 | } | |
786 | ||
787 | ret = clk_prepare_enable(sport->clk); | |
788 | if (ret) { | |
789 | dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret); | |
790 | return ret; | |
791 | } | |
792 | ||
793 | sport->port.uartclk = clk_get_rate(sport->clk); | |
794 | ||
795 | lpuart_ports[sport->port.line] = sport; | |
796 | ||
797 | platform_set_drvdata(pdev, &sport->port); | |
798 | ||
799 | ret = uart_add_one_port(&lpuart_reg, &sport->port); | |
800 | if (ret) { | |
801 | clk_disable_unprepare(sport->clk); | |
802 | return ret; | |
803 | } | |
804 | ||
805 | return 0; | |
806 | } | |
807 | ||
808 | static int lpuart_remove(struct platform_device *pdev) | |
809 | { | |
810 | struct lpuart_port *sport = platform_get_drvdata(pdev); | |
811 | ||
812 | uart_remove_one_port(&lpuart_reg, &sport->port); | |
813 | ||
814 | clk_disable_unprepare(sport->clk); | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
819 | #ifdef CONFIG_PM_SLEEP | |
820 | static int lpuart_suspend(struct device *dev) | |
821 | { | |
822 | struct lpuart_port *sport = dev_get_drvdata(dev); | |
823 | ||
824 | uart_suspend_port(&lpuart_reg, &sport->port); | |
825 | ||
826 | return 0; | |
827 | } | |
828 | ||
829 | static int lpuart_resume(struct device *dev) | |
830 | { | |
831 | struct lpuart_port *sport = dev_get_drvdata(dev); | |
832 | ||
833 | uart_resume_port(&lpuart_reg, &sport->port); | |
834 | ||
835 | return 0; | |
836 | } | |
837 | #endif | |
838 | ||
839 | static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); | |
840 | ||
841 | static struct platform_driver lpuart_driver = { | |
842 | .probe = lpuart_probe, | |
843 | .remove = lpuart_remove, | |
844 | .driver = { | |
845 | .name = "fsl-lpuart", | |
846 | .owner = THIS_MODULE, | |
847 | .of_match_table = lpuart_dt_ids, | |
848 | .pm = &lpuart_pm_ops, | |
849 | }, | |
850 | }; | |
851 | ||
852 | static int __init lpuart_serial_init(void) | |
853 | { | |
854 | int ret; | |
855 | ||
856 | pr_info("serial: Freescale lpuart driver\n"); | |
857 | ||
858 | ret = uart_register_driver(&lpuart_reg); | |
859 | if (ret) | |
860 | return ret; | |
861 | ||
862 | ret = platform_driver_register(&lpuart_driver); | |
863 | if (ret) | |
864 | uart_unregister_driver(&lpuart_reg); | |
865 | ||
866 | return 0; | |
867 | } | |
868 | ||
869 | static void __exit lpuart_serial_exit(void) | |
870 | { | |
871 | platform_driver_unregister(&lpuart_driver); | |
872 | uart_unregister_driver(&lpuart_reg); | |
873 | } | |
874 | ||
875 | module_init(lpuart_serial_init); | |
876 | module_exit(lpuart_serial_exit); | |
877 | ||
878 | MODULE_DESCRIPTION("Freescale lpuart serial port driver"); | |
879 | MODULE_LICENSE("GPL v2"); |