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tty: serial: fsl_lpuart: Update suspend/resume for DMA mode
[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / fsl_lpuart.c
CommitLineData
c9e2e946
JL		 1/*
2 * Freescale lpuart serial port driver
3 *
380c966c 4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
c9e2e946
JL		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
f1cd8c87
YY		 16#include <linux/clk.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/dmaengine.h>
20#include <linux/dmapool.h>
c9e2e946
JL		 21#include <linux/io.h>
22#include <linux/irq.h>
f1cd8c87 23#include <linux/module.h>
c9e2e946
JL		 24#include <linux/of.h>
25#include <linux/of_device.h>
f1cd8c87 26#include <linux/of_dma.h>
c9e2e946 27#include <linux/serial_core.h>
f1cd8c87 28#include <linux/slab.h>
c9e2e946
JL		 29#include <linux/tty_flip.h>
30
31/* All registers are 8-bit width */
32#define UARTBDH 0x00
33#define UARTBDL 0x01
34#define UARTCR1 0x02
35#define UARTCR2 0x03
36#define UARTSR1 0x04
37#define UARTCR3 0x06
38#define UARTDR 0x07
39#define UARTCR4 0x0a
40#define UARTCR5 0x0b
41#define UARTMODEM 0x0d
42#define UARTPFIFO 0x10
43#define UARTCFIFO 0x11
44#define UARTSFIFO 0x12
45#define UARTTWFIFO 0x13
46#define UARTTCFIFO 0x14
47#define UARTRWFIFO 0x15
48
49#define UARTBDH_LBKDIE 0x80
50#define UARTBDH_RXEDGIE 0x40
51#define UARTBDH_SBR_MASK 0x1f
52
53#define UARTCR1_LOOPS 0x80
54#define UARTCR1_RSRC 0x20
55#define UARTCR1_M 0x10
56#define UARTCR1_WAKE 0x08
57#define UARTCR1_ILT 0x04
58#define UARTCR1_PE 0x02
59#define UARTCR1_PT 0x01
60
61#define UARTCR2_TIE 0x80
62#define UARTCR2_TCIE 0x40
63#define UARTCR2_RIE 0x20
64#define UARTCR2_ILIE 0x10
65#define UARTCR2_TE 0x08
66#define UARTCR2_RE 0x04
67#define UARTCR2_RWU 0x02
68#define UARTCR2_SBK 0x01
69
70#define UARTSR1_TDRE 0x80
71#define UARTSR1_TC 0x40
72#define UARTSR1_RDRF 0x20
73#define UARTSR1_IDLE 0x10
74#define UARTSR1_OR 0x08
75#define UARTSR1_NF 0x04
76#define UARTSR1_FE 0x02
77#define UARTSR1_PE 0x01
78
79#define UARTCR3_R8 0x80
80#define UARTCR3_T8 0x40
81#define UARTCR3_TXDIR 0x20
82#define UARTCR3_TXINV 0x10
83#define UARTCR3_ORIE 0x08
84#define UARTCR3_NEIE 0x04
85#define UARTCR3_FEIE 0x02
86#define UARTCR3_PEIE 0x01
87
88#define UARTCR4_MAEN1 0x80
89#define UARTCR4_MAEN2 0x40
90#define UARTCR4_M10 0x20
91#define UARTCR4_BRFA_MASK 0x1f
92#define UARTCR4_BRFA_OFF 0
93
94#define UARTCR5_TDMAS 0x80
95#define UARTCR5_RDMAS 0x20
96
97#define UARTMODEM_RXRTSE 0x08
98#define UARTMODEM_TXRTSPOL 0x04
99#define UARTMODEM_TXRTSE 0x02
100#define UARTMODEM_TXCTSE 0x01
101
102#define UARTPFIFO_TXFE 0x80
103#define UARTPFIFO_FIFOSIZE_MASK 0x7
104#define UARTPFIFO_TXSIZE_OFF 4
105#define UARTPFIFO_RXFE 0x08
106#define UARTPFIFO_RXSIZE_OFF 0
107
108#define UARTCFIFO_TXFLUSH 0x80
109#define UARTCFIFO_RXFLUSH 0x40
110#define UARTCFIFO_RXOFE 0x04
111#define UARTCFIFO_TXOFE 0x02
112#define UARTCFIFO_RXUFE 0x01
113
114#define UARTSFIFO_TXEMPT 0x80
115#define UARTSFIFO_RXEMPT 0x40
116#define UARTSFIFO_RXOF 0x04
117#define UARTSFIFO_TXOF 0x02
118#define UARTSFIFO_RXUF 0x01
119
380c966c
JL		 120/* 32-bit register defination */
121#define UARTBAUD 0x00
122#define UARTSTAT 0x04
123#define UARTCTRL 0x08
124#define UARTDATA 0x0C
125#define UARTMATCH 0x10
126#define UARTMODIR 0x14
127#define UARTFIFO 0x18
128#define UARTWATER 0x1c
129
130#define UARTBAUD_MAEN1 0x80000000
131#define UARTBAUD_MAEN2 0x40000000
132#define UARTBAUD_M10 0x20000000
133#define UARTBAUD_TDMAE 0x00800000
134#define UARTBAUD_RDMAE 0x00200000
135#define UARTBAUD_MATCFG 0x00400000
136#define UARTBAUD_BOTHEDGE 0x00020000
137#define UARTBAUD_RESYNCDIS 0x00010000
138#define UARTBAUD_LBKDIE 0x00008000
139#define UARTBAUD_RXEDGIE 0x00004000
140#define UARTBAUD_SBNS 0x00002000
141#define UARTBAUD_SBR 0x00000000
142#define UARTBAUD_SBR_MASK 0x1fff
143
144#define UARTSTAT_LBKDIF 0x80000000
145#define UARTSTAT_RXEDGIF 0x40000000
146#define UARTSTAT_MSBF 0x20000000
147#define UARTSTAT_RXINV 0x10000000
148#define UARTSTAT_RWUID 0x08000000
149#define UARTSTAT_BRK13 0x04000000
150#define UARTSTAT_LBKDE 0x02000000
151#define UARTSTAT_RAF 0x01000000
152#define UARTSTAT_TDRE 0x00800000
153#define UARTSTAT_TC 0x00400000
154#define UARTSTAT_RDRF 0x00200000
155#define UARTSTAT_IDLE 0x00100000
156#define UARTSTAT_OR 0x00080000
157#define UARTSTAT_NF 0x00040000
158#define UARTSTAT_FE 0x00020000
159#define UARTSTAT_PE 0x00010000
160#define UARTSTAT_MA1F 0x00008000
161#define UARTSTAT_M21F 0x00004000
162
163#define UARTCTRL_R8T9 0x80000000
164#define UARTCTRL_R9T8 0x40000000
165#define UARTCTRL_TXDIR 0x20000000
166#define UARTCTRL_TXINV 0x10000000
167#define UARTCTRL_ORIE 0x08000000
168#define UARTCTRL_NEIE 0x04000000
169#define UARTCTRL_FEIE 0x02000000
170#define UARTCTRL_PEIE 0x01000000
171#define UARTCTRL_TIE 0x00800000
172#define UARTCTRL_TCIE 0x00400000
173#define UARTCTRL_RIE 0x00200000
174#define UARTCTRL_ILIE 0x00100000
175#define UARTCTRL_TE 0x00080000
176#define UARTCTRL_RE 0x00040000
177#define UARTCTRL_RWU 0x00020000
178#define UARTCTRL_SBK 0x00010000
179#define UARTCTRL_MA1IE 0x00008000
180#define UARTCTRL_MA2IE 0x00004000
181#define UARTCTRL_IDLECFG 0x00000100
182#define UARTCTRL_LOOPS 0x00000080
183#define UARTCTRL_DOZEEN 0x00000040
184#define UARTCTRL_RSRC 0x00000020
185#define UARTCTRL_M 0x00000010
186#define UARTCTRL_WAKE 0x00000008
187#define UARTCTRL_ILT 0x00000004
188#define UARTCTRL_PE 0x00000002
189#define UARTCTRL_PT 0x00000001
190
191#define UARTDATA_NOISY 0x00008000
192#define UARTDATA_PARITYE 0x00004000
193#define UARTDATA_FRETSC 0x00002000
194#define UARTDATA_RXEMPT 0x00001000
195#define UARTDATA_IDLINE 0x00000800
196#define UARTDATA_MASK 0x3ff
197
198#define UARTMODIR_IREN 0x00020000
199#define UARTMODIR_TXCTSSRC 0x00000020
200#define UARTMODIR_TXCTSC 0x00000010
201#define UARTMODIR_RXRTSE 0x00000008
202#define UARTMODIR_TXRTSPOL 0x00000004
203#define UARTMODIR_TXRTSE 0x00000002
204#define UARTMODIR_TXCTSE 0x00000001
205
206#define UARTFIFO_TXEMPT 0x00800000
207#define UARTFIFO_RXEMPT 0x00400000
208#define UARTFIFO_TXOF 0x00020000
209#define UARTFIFO_RXUF 0x00010000
210#define UARTFIFO_TXFLUSH 0x00008000
211#define UARTFIFO_RXFLUSH 0x00004000
212#define UARTFIFO_TXOFE 0x00000200
213#define UARTFIFO_RXUFE 0x00000100
214#define UARTFIFO_TXFE 0x00000080
215#define UARTFIFO_FIFOSIZE_MASK 0x7
216#define UARTFIFO_TXSIZE_OFF 4
217#define UARTFIFO_RXFE 0x00000008
218#define UARTFIFO_RXSIZE_OFF 0
219
220#define UARTWATER_COUNT_MASK 0xff
221#define UARTWATER_TXCNT_OFF 8
222#define UARTWATER_RXCNT_OFF 24
223#define UARTWATER_WATER_MASK 0xff
224#define UARTWATER_TXWATER_OFF 0
225#define UARTWATER_RXWATER_OFF 16
226
5887ad43
BD		 227/* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
228#define DMA_RX_TIMEOUT (10)
f1cd8c87 229
c9e2e946
JL		 230#define DRIVER_NAME "fsl-lpuart"
231#define DEV_NAME "ttyLP"
232#define UART_NR 6
233
234struct lpuart_port {
235 struct uart_port port;
236 struct clk *clk;
237 unsigned int txfifo_size;
238 unsigned int rxfifo_size;
380c966c 239 bool lpuart32;
f1cd8c87 240
4a818c43
SA		 241 bool lpuart_dma_tx_use;
242 bool lpuart_dma_rx_use;
f1cd8c87
YY		 243 struct dma_chan *dma_tx_chan;
244 struct dma_chan *dma_rx_chan;
245 struct dma_async_tx_descriptor *dma_tx_desc;
246 struct dma_async_tx_descriptor *dma_rx_desc;
f1cd8c87
YY		 247 dma_cookie_t dma_tx_cookie;
248 dma_cookie_t dma_rx_cookie;
f1cd8c87
YY		 249 unsigned int dma_tx_bytes;
250 unsigned int dma_rx_bytes;
6250cc30 251 bool dma_tx_in_progress;
f1cd8c87
YY		 252 unsigned int dma_rx_timeout;
253 struct timer_list lpuart_timer;
6250cc30 254 struct scatterlist rx_sgl, tx_sgl[2];
5887ad43
BD		 255 struct circ_buf rx_ring;
256 int rx_dma_rng_buf_len;
6250cc30
BD		 257 unsigned int dma_tx_nents;
258 wait_queue_head_t dma_wait;
c9e2e946
JL		 259};
260
ed0bb232 261static const struct of_device_id lpuart_dt_ids[] = {
c9e2e946
JL		 262 {
263 .compatible = "fsl,vf610-lpuart",
264 },
380c966c
JL		 265 {
266 .compatible = "fsl,ls1021a-lpuart",
267 },
c9e2e946
JL		 268 { /* sentinel */ }
269};
270MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
271
f1cd8c87
YY		 272/* Forward declare this for the dma callbacks*/
273static void lpuart_dma_tx_complete(void *arg);
f1cd8c87 274
380c966c
JL		 275static u32 lpuart32_read(void __iomem *addr)
276{
277 return ioread32be(addr);
278}
279
280static void lpuart32_write(u32 val, void __iomem *addr)
281{
282 iowrite32be(val, addr);
283}
284
c9e2e946
JL		 285static void lpuart_stop_tx(struct uart_port *port)
286{
287 unsigned char temp;
288
289 temp = readb(port->membase + UARTCR2);
290 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
291 writeb(temp, port->membase + UARTCR2);
292}
293
380c966c
JL		 294static void lpuart32_stop_tx(struct uart_port *port)
295{
296 unsigned long temp;
297
298 temp = lpuart32_read(port->membase + UARTCTRL);
299 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
300 lpuart32_write(temp, port->membase + UARTCTRL);
301}
302
c9e2e946
JL		 303static void lpuart_stop_rx(struct uart_port *port)
304{
305 unsigned char temp;
306
307 temp = readb(port->membase + UARTCR2);
308 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
309}
310
380c966c
JL		 311static void lpuart32_stop_rx(struct uart_port *port)
312{
313 unsigned long temp;
314
315 temp = lpuart32_read(port->membase + UARTCTRL);
316 lpuart32_write(temp & ~UARTCTRL_RE, port->membase + UARTCTRL);
317}
318
6250cc30 319static void lpuart_dma_tx(struct lpuart_port *sport)
f1cd8c87
YY		 320{
321 struct circ_buf *xmit = &sport->port.state->xmit;
6250cc30
BD		 322 struct scatterlist *sgl = sport->tx_sgl;
323 struct device *dev = sport->port.dev;
324 int ret;
f1cd8c87 325
6250cc30
BD		 326 if (sport->dma_tx_in_progress)
327 return;
f1cd8c87 328
6250cc30 329 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
f1cd8c87 330
6250cc30
BD		 331 if (xmit->tail < xmit->head) {
332 sport->dma_tx_nents = 1;
333 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
334 } else {
335 sport->dma_tx_nents = 2;
336 sg_init_table(sgl, 2);
337 sg_set_buf(sgl, xmit->buf + xmit->tail,
338 UART_XMIT_SIZE - xmit->tail);
339 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
340 }
f1cd8c87 341
6250cc30
BD		 342 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
343 if (!ret) {
344 dev_err(dev, "DMA mapping error for TX.\n");
345 return;
346 }
f1cd8c87 347
6250cc30
BD		 348 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
349 sport->dma_tx_nents,
f1cd8c87 350 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
f1cd8c87 351 if (!sport->dma_tx_desc) {
6250cc30
BD		 352 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
353 dev_err(dev, "Cannot prepare TX slave DMA!\n");
354 return;
f1cd8c87
YY		 355 }
356
357 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
358 sport->dma_tx_desc->callback_param = sport;
6250cc30 359 sport->dma_tx_in_progress = true;
f1cd8c87
YY		 360 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
361 dma_async_issue_pending(sport->dma_tx_chan);
362
f1cd8c87
YY		 363}
364
365static void lpuart_dma_tx_complete(void *arg)
366{
367 struct lpuart_port *sport = arg;
6250cc30 368 struct scatterlist *sgl = &sport->tx_sgl[0];
f1cd8c87
YY		 369 struct circ_buf *xmit = &sport->port.state->xmit;
370 unsigned long flags;
371
f1cd8c87
YY		 372 spin_lock_irqsave(&sport->port.lock, flags);
373
6250cc30
BD		 374 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
375
f1cd8c87 376 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
6250cc30
BD		 377
378 sport->port.icount.tx += sport->dma_tx_bytes;
379 sport->dma_tx_in_progress = false;
380 spin_unlock_irqrestore(&sport->port.lock, flags);
f1cd8c87
YY		 381
382 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
383 uart_write_wakeup(&sport->port);
384
6250cc30
BD		 385 if (waitqueue_active(&sport->dma_wait)) {
386 wake_up(&sport->dma_wait);
387 return;
388 }
389
390 spin_lock_irqsave(&sport->port.lock, flags);
391
392 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
393 lpuart_dma_tx(sport);
f1cd8c87
YY		 394
395 spin_unlock_irqrestore(&sport->port.lock, flags);
396}
397
6250cc30
BD		 398static int lpuart_dma_tx_request(struct uart_port *port)
399{
400 struct lpuart_port *sport = container_of(port,
401 struct lpuart_port, port);
402 struct dma_slave_config dma_tx_sconfig = {};
403 int ret;
404
405 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
406 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
407 dma_tx_sconfig.dst_maxburst = 1;
408 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
409 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
410
411 if (ret) {
412 dev_err(sport->port.dev,
413 "DMA slave config failed, err = %d\n", ret);
414 return ret;
415 }
416
417 return 0;
418}
419
bfc2e07f
SA		 420static void lpuart_flush_buffer(struct uart_port *port)
421{
422 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
6250cc30 423
bfc2e07f 424 if (sport->lpuart_dma_tx_use) {
6250cc30
BD		 425 if (sport->dma_tx_in_progress) {
426 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
427 sport->dma_tx_nents, DMA_TO_DEVICE);
428 sport->dma_tx_in_progress = false;
429 }
bfc2e07f 430 dmaengine_terminate_all(sport->dma_tx_chan);
bfc2e07f
SA		 431 }
432}
433
c9e2e946
JL		 434static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
435{
436 struct circ_buf *xmit = &sport->port.state->xmit;
437
438 while (!uart_circ_empty(xmit) &&
439 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
440 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
441 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
442 sport->port.icount.tx++;
443 }
444
445 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
446 uart_write_wakeup(&sport->port);
447
448 if (uart_circ_empty(xmit))
449 lpuart_stop_tx(&sport->port);
450}
451
380c966c
JL		 452static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
453{
454 struct circ_buf *xmit = &sport->port.state->xmit;
455 unsigned long txcnt;
456
457 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
458 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
459 txcnt &= UARTWATER_COUNT_MASK;
460 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
461 lpuart32_write(xmit->buf[xmit->tail], sport->port.membase + UARTDATA);
462 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
463 sport->port.icount.tx++;
464 txcnt = lpuart32_read(sport->port.membase + UARTWATER);
465 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
466 txcnt &= UARTWATER_COUNT_MASK;
467 }
468
469 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
470 uart_write_wakeup(&sport->port);
471
472 if (uart_circ_empty(xmit))
473 lpuart32_stop_tx(&sport->port);
474}
475
c9e2e946
JL		 476static void lpuart_start_tx(struct uart_port *port)
477{
f1cd8c87
YY		 478 struct lpuart_port *sport = container_of(port,
479 struct lpuart_port, port);
480 struct circ_buf *xmit = &sport->port.state->xmit;
c9e2e946
JL		 481 unsigned char temp;
482
483 temp = readb(port->membase + UARTCR2);
484 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
485
4a818c43 486 if (sport->lpuart_dma_tx_use) {
6250cc30
BD		 487 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port))
488 lpuart_dma_tx(sport);
f1cd8c87
YY		 489 } else {
490 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
491 lpuart_transmit_buffer(sport);
492 }
c9e2e946
JL		 493}
494
380c966c
JL		 495static void lpuart32_start_tx(struct uart_port *port)
496{
497 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
498 unsigned long temp;
499
500 temp = lpuart32_read(port->membase + UARTCTRL);
501 lpuart32_write(temp | UARTCTRL_TIE, port->membase + UARTCTRL);
502
503 if (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE)
504 lpuart32_transmit_buffer(sport);
505}
506
6250cc30
BD		 507/* return TIOCSER_TEMT when transmitter is not busy */
508static unsigned int lpuart_tx_empty(struct uart_port *port)
509{
510 struct lpuart_port *sport = container_of(port,
511 struct lpuart_port, port);
512 unsigned char sr1 = readb(port->membase + UARTSR1);
513 unsigned char sfifo = readb(port->membase + UARTSFIFO);
514
515 if (sport->dma_tx_in_progress)
516 return 0;
517
518 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
519 return TIOCSER_TEMT;
520
521 return 0;
522}
523
524static unsigned int lpuart32_tx_empty(struct uart_port *port)
525{
526 return (lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TC) ?
527 TIOCSER_TEMT : 0;
528}
529
c9e2e946
JL		 530static irqreturn_t lpuart_txint(int irq, void *dev_id)
531{
532 struct lpuart_port *sport = dev_id;
533 struct circ_buf *xmit = &sport->port.state->xmit;
534 unsigned long flags;
535
536 spin_lock_irqsave(&sport->port.lock, flags);
537 if (sport->port.x_char) {
380c966c
JL		 538 if (sport->lpuart32)
539 lpuart32_write(sport->port.x_char, sport->port.membase + UARTDATA);
540 else
541 writeb(sport->port.x_char, sport->port.membase + UARTDR);
c9e2e946
JL		 542 goto out;
543 }
544
545 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
380c966c
JL		 546 if (sport->lpuart32)
547 lpuart32_stop_tx(&sport->port);
548 else
549 lpuart_stop_tx(&sport->port);
c9e2e946
JL		 550 goto out;
551 }
552
380c966c
JL		 553 if (sport->lpuart32)
554 lpuart32_transmit_buffer(sport);
555 else
556 lpuart_transmit_buffer(sport);
c9e2e946
JL		 557
558 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
559 uart_write_wakeup(&sport->port);
560
561out:
562 spin_unlock_irqrestore(&sport->port.lock, flags);
563 return IRQ_HANDLED;
564}
565
566static irqreturn_t lpuart_rxint(int irq, void *dev_id)
567{
568 struct lpuart_port *sport = dev_id;
569 unsigned int flg, ignored = 0;
570 struct tty_port *port = &sport->port.state->port;
571 unsigned long flags;
572 unsigned char rx, sr;
573
574 spin_lock_irqsave(&sport->port.lock, flags);
575
576 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
577 flg = TTY_NORMAL;
578 sport->port.icount.rx++;
579 /*
580 * to clear the FE, OR, NF, FE, PE flags,
581 * read SR1 then read DR
582 */
583 sr = readb(sport->port.membase + UARTSR1);
584 rx = readb(sport->port.membase + UARTDR);
585
586 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
587 continue;
588
589 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
590 if (sr & UARTSR1_PE)
591 sport->port.icount.parity++;
592 else if (sr & UARTSR1_FE)
593 sport->port.icount.frame++;
594
595 if (sr & UARTSR1_OR)
596 sport->port.icount.overrun++;
597
598 if (sr & sport->port.ignore_status_mask) {
599 if (++ignored > 100)
600 goto out;
601 continue;
602 }
603
604 sr &= sport->port.read_status_mask;
605
606 if (sr & UARTSR1_PE)
607 flg = TTY_PARITY;
608 else if (sr & UARTSR1_FE)
609 flg = TTY_FRAME;
610
611 if (sr & UARTSR1_OR)
612 flg = TTY_OVERRUN;
613
614#ifdef SUPPORT_SYSRQ
615 sport->port.sysrq = 0;
616#endif
617 }
618
619 tty_insert_flip_char(port, rx, flg);
620 }
621
622out:
623 spin_unlock_irqrestore(&sport->port.lock, flags);
624
625 tty_flip_buffer_push(port);
626 return IRQ_HANDLED;
627}
628
380c966c
JL		 629static irqreturn_t lpuart32_rxint(int irq, void *dev_id)
630{
631 struct lpuart_port *sport = dev_id;
632 unsigned int flg, ignored = 0;
633 struct tty_port *port = &sport->port.state->port;
634 unsigned long flags;
635 unsigned long rx, sr;
636
637 spin_lock_irqsave(&sport->port.lock, flags);
638
639 while (!(lpuart32_read(sport->port.membase + UARTFIFO) & UARTFIFO_RXEMPT)) {
640 flg = TTY_NORMAL;
641 sport->port.icount.rx++;
642 /*
643 * to clear the FE, OR, NF, FE, PE flags,
644 * read STAT then read DATA reg
645 */
646 sr = lpuart32_read(sport->port.membase + UARTSTAT);
647 rx = lpuart32_read(sport->port.membase + UARTDATA);
648 rx &= 0x3ff;
649
650 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
651 continue;
652
653 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
654 if (sr & UARTSTAT_PE)
655 sport->port.icount.parity++;
656 else if (sr & UARTSTAT_FE)
657 sport->port.icount.frame++;
658
659 if (sr & UARTSTAT_OR)
660 sport->port.icount.overrun++;
661
662 if (sr & sport->port.ignore_status_mask) {
663 if (++ignored > 100)
664 goto out;
665 continue;
666 }
667
668 sr &= sport->port.read_status_mask;
669
670 if (sr & UARTSTAT_PE)
671 flg = TTY_PARITY;
672 else if (sr & UARTSTAT_FE)
673 flg = TTY_FRAME;
674
675 if (sr & UARTSTAT_OR)
676 flg = TTY_OVERRUN;
677
678#ifdef SUPPORT_SYSRQ
679 sport->port.sysrq = 0;
680#endif
681 }
682
683 tty_insert_flip_char(port, rx, flg);
684 }
685
686out:
687 spin_unlock_irqrestore(&sport->port.lock, flags);
688
689 tty_flip_buffer_push(port);
690 return IRQ_HANDLED;
691}
692
c9e2e946
JL		 693static irqreturn_t lpuart_int(int irq, void *dev_id)
694{
695 struct lpuart_port *sport = dev_id;
5887ad43 696 unsigned char sts;
c9e2e946
JL		 697
698 sts = readb(sport->port.membase + UARTSR1);
699
5887ad43
BD		 700 if (sts & UARTSR1_RDRF)
701 lpuart_rxint(irq, dev_id);
702
6250cc30
BD		 703 if (sts & UARTSR1_TDRE)
704 lpuart_txint(irq, dev_id);
c9e2e946
JL		 705
706 return IRQ_HANDLED;
707}
708
380c966c
JL		 709static irqreturn_t lpuart32_int(int irq, void *dev_id)
710{
711 struct lpuart_port *sport = dev_id;
712 unsigned long sts, rxcount;
713
714 sts = lpuart32_read(sport->port.membase + UARTSTAT);
715 rxcount = lpuart32_read(sport->port.membase + UARTWATER);
716 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
717
718 if (sts & UARTSTAT_RDRF || rxcount > 0)
719 lpuart32_rxint(irq, dev_id);
720
721 if ((sts & UARTSTAT_TDRE) &&
722 !(lpuart32_read(sport->port.membase + UARTBAUD) & UARTBAUD_TDMAE))
723 lpuart_txint(irq, dev_id);
724
725 lpuart32_write(sts, sport->port.membase + UARTSTAT);
726 return IRQ_HANDLED;
727}
728
5887ad43
BD		 729static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
730{
731 struct tty_port *port = &sport->port.state->port;
732 struct dma_tx_state state;
733 enum dma_status dmastat;
734 struct circ_buf *ring = &sport->rx_ring;
735 unsigned long flags;
736 int count = 0;
737 unsigned char sr;
738
739 sr = readb(sport->port.membase + UARTSR1);
740
741 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
742 /* Read DR to clear the error flags */
743 readb(sport->port.membase + UARTDR);
744
745 if (sr & UARTSR1_PE)
746 sport->port.icount.parity++;
747 else if (sr & UARTSR1_FE)
748 sport->port.icount.frame++;
749 }
750
751 async_tx_ack(sport->dma_rx_desc);
752
753 spin_lock_irqsave(&sport->port.lock, flags);
754
755 dmastat = dmaengine_tx_status(sport->dma_rx_chan,
756 sport->dma_rx_cookie,
757 &state);
758
759 if (dmastat == DMA_ERROR) {
760 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
761 spin_unlock_irqrestore(&sport->port.lock, flags);
762 return;
763 }
764
765 /* CPU claims ownership of RX DMA buffer */
766 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
767
768 /*
769 * ring->head points to the end of data already written by the DMA.
770 * ring->tail points to the beginning of data to be read by the
771 * framework.
772 * The current transfer size should not be larger than the dma buffer
773 * length.
774 */
775 ring->head = sport->rx_sgl.length - state.residue;
776 BUG_ON(ring->head > sport->rx_sgl.length);
777 /*
778 * At this point ring->head may point to the first byte right after the
779 * last byte of the dma buffer:
780 * 0 <= ring->head <= sport->rx_sgl.length
781 *
782 * However ring->tail must always points inside the dma buffer:
783 * 0 <= ring->tail <= sport->rx_sgl.length - 1
784 *
785 * Since we use a ring buffer, we have to handle the case
786 * where head is lower than tail. In such a case, we first read from
787 * tail to the end of the buffer then reset tail.
788 */
789 if (ring->head < ring->tail) {
790 count = sport->rx_sgl.length - ring->tail;
791
792 tty_insert_flip_string(port, ring->buf + ring->tail, count);
793 ring->tail = 0;
794 sport->port.icount.rx += count;
795 }
796
797 /* Finally we read data from tail to head */
798 if (ring->tail < ring->head) {
799 count = ring->head - ring->tail;
800 tty_insert_flip_string(port, ring->buf + ring->tail, count);
801 /* Wrap ring->head if needed */
802 if (ring->head >= sport->rx_sgl.length)
803 ring->head = 0;
804 ring->tail = ring->head;
805 sport->port.icount.rx += count;
806 }
807
808 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
809 DMA_FROM_DEVICE);
810
811 spin_unlock_irqrestore(&sport->port.lock, flags);
812
813 tty_flip_buffer_push(port);
814 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
815}
816
817static void lpuart_dma_rx_complete(void *arg)
818{
819 struct lpuart_port *sport = arg;
820
821 lpuart_copy_rx_to_tty(sport);
822}
823
824static void lpuart_timer_func(unsigned long data)
825{
826 struct lpuart_port *sport = (struct lpuart_port *)data;
827
828 lpuart_copy_rx_to_tty(sport);
829}
830
831static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
832{
833 struct dma_slave_config dma_rx_sconfig = {};
834 struct circ_buf *ring = &sport->rx_ring;
835 int ret, nent;
836 int bits, baud;
837 struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port);
838 struct ktermios *termios = &tty->termios;
839
840 baud = tty_get_baud_rate(tty);
841
842 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
843 if (termios->c_cflag & PARENB)
844 bits++;
845
846 /*
847 * Calculate length of one DMA buffer size to keep latency below
848 * 10ms at any baud rate.
849 */
850 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
851 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
852 if (sport->rx_dma_rng_buf_len < 16)
853 sport->rx_dma_rng_buf_len = 16;
854
855 ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_KERNEL);
856 if (!ring->buf) {
857 dev_err(sport->port.dev, "Ring buf alloc failed\n");
858 return -ENOMEM;
859 }
860
861 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
862 sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
863 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
864
865 if (!nent) {
866 dev_err(sport->port.dev, "DMA Rx mapping error\n");
867 return -EINVAL;
868 }
869
870 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
871 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
872 dma_rx_sconfig.src_maxburst = 1;
873 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
874 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
875
876 if (ret < 0) {
877 dev_err(sport->port.dev,
878 "DMA Rx slave config failed, err = %d\n", ret);
879 return ret;
880 }
881
882 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
883 sg_dma_address(&sport->rx_sgl),
884 sport->rx_sgl.length,
885 sport->rx_sgl.length / 2,
886 DMA_DEV_TO_MEM,
887 DMA_PREP_INTERRUPT);
888 if (!sport->dma_rx_desc) {
889 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
890 return -EFAULT;
891 }
892
893 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
894 sport->dma_rx_desc->callback_param = sport;
895 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
896 dma_async_issue_pending(sport->dma_rx_chan);
897
898 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
899 sport->port.membase + UARTCR5);
900
901 return 0;
902}
903
5887ad43
BD		 904static void lpuart_dma_rx_free(struct uart_port *port)
905{
906 struct lpuart_port *sport = container_of(port,
907 struct lpuart_port, port);
908
909 if (sport->dma_rx_chan)
910 dmaengine_terminate_all(sport->dma_rx_chan);
911
912 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
913 kfree(sport->rx_ring.buf);
914 sport->rx_ring.tail = 0;
915 sport->rx_ring.head = 0;
916 sport->dma_rx_desc = NULL;
917 sport->dma_rx_cookie = -EINVAL;
918}
919
c9e2e946
JL		 920static unsigned int lpuart_get_mctrl(struct uart_port *port)
921{
922 unsigned int temp = 0;
923 unsigned char reg;
924
925 reg = readb(port->membase + UARTMODEM);
926 if (reg & UARTMODEM_TXCTSE)
927 temp |= TIOCM_CTS;
928
929 if (reg & UARTMODEM_RXRTSE)
930 temp |= TIOCM_RTS;
931
932 return temp;
933}
934
380c966c
JL		 935static unsigned int lpuart32_get_mctrl(struct uart_port *port)
936{
937 unsigned int temp = 0;
938 unsigned long reg;
939
940 reg = lpuart32_read(port->membase + UARTMODIR);
941 if (reg & UARTMODIR_TXCTSE)
942 temp |= TIOCM_CTS;
943
944 if (reg & UARTMODIR_RXRTSE)
945 temp |= TIOCM_RTS;
946
947 return temp;
948}
949
c9e2e946
JL		 950static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
951{
952 unsigned char temp;
953
954 temp = readb(port->membase + UARTMODEM) &
955 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
956
957 if (mctrl & TIOCM_RTS)
958 temp |= UARTMODEM_RXRTSE;
959
960 if (mctrl & TIOCM_CTS)
961 temp |= UARTMODEM_TXCTSE;
962
963 writeb(temp, port->membase + UARTMODEM);
964}
965
380c966c
JL		 966static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
967{
968 unsigned long temp;
969
970 temp = lpuart32_read(port->membase + UARTMODIR) &
971 ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
972
973 if (mctrl & TIOCM_RTS)
974 temp |= UARTMODIR_RXRTSE;
975
976 if (mctrl & TIOCM_CTS)
977 temp |= UARTMODIR_TXCTSE;
978
979 lpuart32_write(temp, port->membase + UARTMODIR);
980}
981
c9e2e946
JL		 982static void lpuart_break_ctl(struct uart_port *port, int break_state)
983{
984 unsigned char temp;
985
986 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
987
988 if (break_state != 0)
989 temp |= UARTCR2_SBK;
990
991 writeb(temp, port->membase + UARTCR2);
992}
993
380c966c
JL		 994static void lpuart32_break_ctl(struct uart_port *port, int break_state)
995{
996 unsigned long temp;
997
998 temp = lpuart32_read(port->membase + UARTCTRL) & ~UARTCTRL_SBK;
999
1000 if (break_state != 0)
1001 temp |= UARTCTRL_SBK;
1002
1003 lpuart32_write(temp, port->membase + UARTCTRL);
1004}
1005
c9e2e946
JL		 1006static void lpuart_setup_watermark(struct lpuart_port *sport)
1007{
1008 unsigned char val, cr2;
bc764b8f 1009 unsigned char cr2_saved;
c9e2e946
JL		 1010
1011 cr2 = readb(sport->port.membase + UARTCR2);
bc764b8f 1012 cr2_saved = cr2;
c9e2e946
JL		 1013 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1014 UARTCR2_RIE | UARTCR2_RE);
1015 writeb(cr2, sport->port.membase + UARTCR2);
1016
c9e2e946 1017 val = readb(sport->port.membase + UARTPFIFO);
c9e2e946
JL		 1018 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1019 sport->port.membase + UARTPFIFO);
1020
1021 /* flush Tx and Rx FIFO */
1022 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1023 sport->port.membase + UARTCFIFO);
1024
d68827c6
SA		 1025 /* explicitly clear RDRF */
1026 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1027 readb(sport->port.membase + UARTDR);
1028 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1029 }
1030
f1cd8c87 1031 writeb(0, sport->port.membase + UARTTWFIFO);
c9e2e946 1032 writeb(1, sport->port.membase + UARTRWFIFO);
bc764b8f
SG		 1033
1034 /* Restore cr2 */
1035 writeb(cr2_saved, sport->port.membase + UARTCR2);
c9e2e946
JL		 1036}
1037
380c966c
JL		 1038static void lpuart32_setup_watermark(struct lpuart_port *sport)
1039{
1040 unsigned long val, ctrl;
1041 unsigned long ctrl_saved;
1042
1043 ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1044 ctrl_saved = ctrl;
1045 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1046 UARTCTRL_RIE | UARTCTRL_RE);
1047 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1048
1049 /* enable FIFO mode */
1050 val = lpuart32_read(sport->port.membase + UARTFIFO);
1051 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1052 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1053 lpuart32_write(val, sport->port.membase + UARTFIFO);
1054
1055 /* set the watermark */
1056 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1057 lpuart32_write(val, sport->port.membase + UARTWATER);
1058
1059 /* Restore cr2 */
1060 lpuart32_write(ctrl_saved, sport->port.membase + UARTCTRL);
1061}
1062
5887ad43 1063static void rx_dma_timer_init(struct lpuart_port *sport)
f1cd8c87 1064{
5887ad43
BD		 1065 setup_timer(&sport->lpuart_timer, lpuart_timer_func,
1066 (unsigned long)sport);
1067 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1068 add_timer(&sport->lpuart_timer);
f1cd8c87
YY		 1069}
1070
c9e2e946
JL		 1071static int lpuart_startup(struct uart_port *port)
1072{
1073 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1074 int ret;
1075 unsigned long flags;
1076 unsigned char temp;
1077
ed9891bf
SA		 1078 /* determine FIFO size and enable FIFO mode */
1079 temp = readb(sport->port.membase + UARTPFIFO);
1080
1081 sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
1082 UARTPFIFO_FIFOSIZE_MASK) + 1);
1083
4e8f2459
SA		 1084 sport->port.fifosize = sport->txfifo_size;
1085
ed9891bf
SA		 1086 sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
1087 UARTPFIFO_FIFOSIZE_MASK) + 1);
1088
c9e2e946
JL		 1089 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
1090 DRIVER_NAME, sport);
1091 if (ret)
1092 return ret;
1093
1094 spin_lock_irqsave(&sport->port.lock, flags);
1095
1096 lpuart_setup_watermark(sport);
1097
1098 temp = readb(sport->port.membase + UARTCR2);
1099 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
1100 writeb(temp, sport->port.membase + UARTCR2);
1101
5887ad43
BD		 1102 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1103 /* set Rx DMA timeout */
1104 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1105 if (!sport->dma_rx_timeout)
1106 sport->dma_rx_timeout = 1;
1107
1108 sport->lpuart_dma_rx_use = true;
1109 rx_dma_timer_init(sport);
1110 } else {
1111 sport->lpuart_dma_rx_use = false;
1112 }
1113
1114 if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) {
6250cc30 1115 init_waitqueue_head(&sport->dma_wait);
5887ad43
BD		 1116 sport->lpuart_dma_tx_use = true;
1117 temp = readb(port->membase + UARTCR5);
1118 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
1119 } else {
1120 sport->lpuart_dma_tx_use = false;
1121 }
1122
c9e2e946 1123 spin_unlock_irqrestore(&sport->port.lock, flags);
5887ad43 1124
c9e2e946
JL		 1125 return 0;
1126}
1127
380c966c
JL		 1128static int lpuart32_startup(struct uart_port *port)
1129{
1130 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1131 int ret;
1132 unsigned long flags;
1133 unsigned long temp;
1134
1135 /* determine FIFO size */
1136 temp = lpuart32_read(sport->port.membase + UARTFIFO);
1137
1138 sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) &
1139 UARTFIFO_FIFOSIZE_MASK) - 1);
1140
1141 sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) &
1142 UARTFIFO_FIFOSIZE_MASK) - 1);
1143
1144 ret = devm_request_irq(port->dev, port->irq, lpuart32_int, 0,
1145 DRIVER_NAME, sport);
1146 if (ret)
1147 return ret;
1148
1149 spin_lock_irqsave(&sport->port.lock, flags);
1150
1151 lpuart32_setup_watermark(sport);
1152
1153 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1154 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE);
1155 temp |= UARTCTRL_ILIE;
1156 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1157
1158 spin_unlock_irqrestore(&sport->port.lock, flags);
1159 return 0;
1160}
1161
c9e2e946
JL		 1162static void lpuart_shutdown(struct uart_port *port)
1163{
1164 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1165 unsigned char temp;
1166 unsigned long flags;
1167
1168 spin_lock_irqsave(&port->lock, flags);
1169
1170 /* disable Rx/Tx and interrupts */
1171 temp = readb(port->membase + UARTCR2);
1172 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1173 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1174 writeb(temp, port->membase + UARTCR2);
1175
1176 spin_unlock_irqrestore(&port->lock, flags);
1177
1178 devm_free_irq(port->dev, port->irq, sport);
f1cd8c87 1179
4a818c43 1180 if (sport->lpuart_dma_rx_use) {
4a8588a1 1181 del_timer_sync(&sport->lpuart_timer);
5887ad43 1182 lpuart_dma_rx_free(&sport->port);
f1cd8c87 1183 }
4a818c43 1184
6250cc30
BD		 1185 if (sport->lpuart_dma_tx_use) {
1186 if (wait_event_interruptible(sport->dma_wait,
1187 !sport->dma_tx_in_progress) != false) {
1188 sport->dma_tx_in_progress = false;
1189 dmaengine_terminate_all(sport->dma_tx_chan);
1190 }
1191
1192 lpuart_stop_tx(port);
1193 }
c9e2e946
JL		 1194}
1195
380c966c
JL		 1196static void lpuart32_shutdown(struct uart_port *port)
1197{
1198 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1199 unsigned long temp;
1200 unsigned long flags;
1201
1202 spin_lock_irqsave(&port->lock, flags);
1203
1204 /* disable Rx/Tx and interrupts */
1205 temp = lpuart32_read(port->membase + UARTCTRL);
1206 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1207 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1208 lpuart32_write(temp, port->membase + UARTCTRL);
1209
1210 spin_unlock_irqrestore(&port->lock, flags);
1211
1212 devm_free_irq(port->dev, port->irq, sport);
1213}
1214
c9e2e946
JL		 1215static void
1216lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1217 struct ktermios *old)
1218{
1219 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1220 unsigned long flags;
aa9e7d78 1221 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
c9e2e946
JL		 1222 unsigned int baud;
1223 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1224 unsigned int sbr, brfa;
1225
1226 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1227 old_cr2 = readb(sport->port.membase + UARTCR2);
aa9e7d78 1228 cr3 = readb(sport->port.membase + UARTCR3);
c9e2e946
JL		 1229 cr4 = readb(sport->port.membase + UARTCR4);
1230 bdh = readb(sport->port.membase + UARTBDH);
1231 modem = readb(sport->port.membase + UARTMODEM);
1232 /*
1233 * only support CS8 and CS7, and for CS7 must enable PE.
1234 * supported mode:
1235 * - (7,e/o,1)
1236 * - (8,n,1)
1237 * - (8,m/s,1)
1238 * - (8,e/o,1)
1239 */
1240 while ((termios->c_cflag & CSIZE) != CS8 &&
1241 (termios->c_cflag & CSIZE) != CS7) {
1242 termios->c_cflag &= ~CSIZE;
1243 termios->c_cflag |= old_csize;
1244 old_csize = CS8;
1245 }
1246
1247 if ((termios->c_cflag & CSIZE) == CS8 ||
1248 (termios->c_cflag & CSIZE) == CS7)
1249 cr1 = old_cr1 & ~UARTCR1_M;
1250
1251 if (termios->c_cflag & CMSPAR) {
1252 if ((termios->c_cflag & CSIZE) != CS8) {
1253 termios->c_cflag &= ~CSIZE;
1254 termios->c_cflag |= CS8;
1255 }
1256 cr1 |= UARTCR1_M;
1257 }
1258
1259 if (termios->c_cflag & CRTSCTS) {
1260 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1261 } else {
1262 termios->c_cflag &= ~CRTSCTS;
1263 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1264 }
1265
1266 if (termios->c_cflag & CSTOPB)
1267 termios->c_cflag &= ~CSTOPB;
1268
1269 /* parity must be enabled when CS7 to match 8-bits format */
1270 if ((termios->c_cflag & CSIZE) == CS7)
1271 termios->c_cflag |= PARENB;
1272
1273 if ((termios->c_cflag & PARENB)) {
1274 if (termios->c_cflag & CMSPAR) {
1275 cr1 &= ~UARTCR1_PE;
aa9e7d78
BD		 1276 if (termios->c_cflag & PARODD)
1277 cr3 |= UARTCR3_T8;
1278 else
1279 cr3 &= ~UARTCR3_T8;
c9e2e946
JL		 1280 } else {
1281 cr1 |= UARTCR1_PE;
1282 if ((termios->c_cflag & CSIZE) == CS8)
1283 cr1 |= UARTCR1_M;
1284 if (termios->c_cflag & PARODD)
1285 cr1 |= UARTCR1_PT;
1286 else
1287 cr1 &= ~UARTCR1_PT;
1288 }
1289 }
1290
1291 /* ask the core to calculate the divisor */
1292 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1293
1294 spin_lock_irqsave(&sport->port.lock, flags);
1295
1296 sport->port.read_status_mask = 0;
1297 if (termios->c_iflag & INPCK)
1298 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
ef8b9ddc 1299 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
c9e2e946
JL		 1300 sport->port.read_status_mask |= UARTSR1_FE;
1301
1302 /* characters to ignore */
1303 sport->port.ignore_status_mask = 0;
1304 if (termios->c_iflag & IGNPAR)
1305 sport->port.ignore_status_mask |= UARTSR1_PE;
1306 if (termios->c_iflag & IGNBRK) {
1307 sport->port.ignore_status_mask |= UARTSR1_FE;
1308 /*
1309 * if we're ignoring parity and break indicators,
1310 * ignore overruns too (for real raw support).
1311 */
1312 if (termios->c_iflag & IGNPAR)
1313 sport->port.ignore_status_mask |= UARTSR1_OR;
1314 }
1315
1316 /* update the per-port timeout */
1317 uart_update_timeout(port, termios->c_cflag, baud);
1318
1319 /* wait transmit engin complete */
1320 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1321 barrier();
1322
1323 /* disable transmit and receive */
1324 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1325 sport->port.membase + UARTCR2);
1326
1327 sbr = sport->port.uartclk / (16 * baud);
1328 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1329 bdh &= ~UARTBDH_SBR_MASK;
1330 bdh |= (sbr >> 8) & 0x1F;
1331 cr4 &= ~UARTCR4_BRFA_MASK;
1332 brfa &= UARTCR4_BRFA_MASK;
1333 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1334 writeb(bdh, sport->port.membase + UARTBDH);
1335 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
aa9e7d78 1336 writeb(cr3, sport->port.membase + UARTCR3);
c9e2e946
JL		 1337 writeb(cr1, sport->port.membase + UARTCR1);
1338 writeb(modem, sport->port.membase + UARTMODEM);
1339
1340 /* restore control register */
1341 writeb(old_cr2, sport->port.membase + UARTCR2);
1342
5887ad43
BD		 1343 /*
1344 * If new baud rate is set, we will also need to update the Ring buffer
1345 * length according to the selected baud rate and restart Rx DMA path.
1346 */
1347 if (old) {
1348 if (sport->lpuart_dma_rx_use) {
1349 del_timer_sync(&sport->lpuart_timer);
1350 lpuart_dma_rx_free(&sport->port);
1351 }
1352
1353 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1354 sport->lpuart_dma_rx_use = true;
1355 rx_dma_timer_init(sport);
1356 } else {
1357 sport->lpuart_dma_rx_use = false;
1358 }
1359 }
1360
c9e2e946
JL		 1361 spin_unlock_irqrestore(&sport->port.lock, flags);
1362}
1363
380c966c
JL		 1364static void
1365lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1366 struct ktermios *old)
1367{
1368 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1369 unsigned long flags;
1370 unsigned long ctrl, old_ctrl, bd, modem;
1371 unsigned int baud;
1372 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1373 unsigned int sbr;
1374
1375 ctrl = old_ctrl = lpuart32_read(sport->port.membase + UARTCTRL);
1376 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1377 modem = lpuart32_read(sport->port.membase + UARTMODIR);
1378 /*
1379 * only support CS8 and CS7, and for CS7 must enable PE.
1380 * supported mode:
1381 * - (7,e/o,1)
1382 * - (8,n,1)
1383 * - (8,m/s,1)
1384 * - (8,e/o,1)
1385 */
1386 while ((termios->c_cflag & CSIZE) != CS8 &&
1387 (termios->c_cflag & CSIZE) != CS7) {
1388 termios->c_cflag &= ~CSIZE;
1389 termios->c_cflag |= old_csize;
1390 old_csize = CS8;
1391 }
1392
1393 if ((termios->c_cflag & CSIZE) == CS8 ||
1394 (termios->c_cflag & CSIZE) == CS7)
1395 ctrl = old_ctrl & ~UARTCTRL_M;
1396
1397 if (termios->c_cflag & CMSPAR) {
1398 if ((termios->c_cflag & CSIZE) != CS8) {
1399 termios->c_cflag &= ~CSIZE;
1400 termios->c_cflag |= CS8;
1401 }
1402 ctrl |= UARTCTRL_M;
1403 }
1404
1405 if (termios->c_cflag & CRTSCTS) {
1406 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1407 } else {
1408 termios->c_cflag &= ~CRTSCTS;
1409 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1410 }
1411
1412 if (termios->c_cflag & CSTOPB)
1413 termios->c_cflag &= ~CSTOPB;
1414
1415 /* parity must be enabled when CS7 to match 8-bits format */
1416 if ((termios->c_cflag & CSIZE) == CS7)
1417 termios->c_cflag |= PARENB;
1418
1419 if ((termios->c_cflag & PARENB)) {
1420 if (termios->c_cflag & CMSPAR) {
1421 ctrl &= ~UARTCTRL_PE;
1422 ctrl |= UARTCTRL_M;
1423 } else {
1424 ctrl |= UARTCR1_PE;
1425 if ((termios->c_cflag & CSIZE) == CS8)
1426 ctrl |= UARTCTRL_M;
1427 if (termios->c_cflag & PARODD)
1428 ctrl |= UARTCTRL_PT;
1429 else
1430 ctrl &= ~UARTCTRL_PT;
1431 }
1432 }
1433
1434 /* ask the core to calculate the divisor */
1435 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1436
1437 spin_lock_irqsave(&sport->port.lock, flags);
1438
1439 sport->port.read_status_mask = 0;
1440 if (termios->c_iflag & INPCK)
1441 sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE);
1442 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1443 sport->port.read_status_mask |= UARTSTAT_FE;
1444
1445 /* characters to ignore */
1446 sport->port.ignore_status_mask = 0;
1447 if (termios->c_iflag & IGNPAR)
1448 sport->port.ignore_status_mask |= UARTSTAT_PE;
1449 if (termios->c_iflag & IGNBRK) {
1450 sport->port.ignore_status_mask |= UARTSTAT_FE;
1451 /*
1452 * if we're ignoring parity and break indicators,
1453 * ignore overruns too (for real raw support).
1454 */
1455 if (termios->c_iflag & IGNPAR)
1456 sport->port.ignore_status_mask |= UARTSTAT_OR;
1457 }
1458
1459 /* update the per-port timeout */
1460 uart_update_timeout(port, termios->c_cflag, baud);
1461
1462 /* wait transmit engin complete */
1463 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1464 barrier();
1465
1466 /* disable transmit and receive */
1467 lpuart32_write(old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
1468 sport->port.membase + UARTCTRL);
1469
1470 sbr = sport->port.uartclk / (16 * baud);
1471 bd &= ~UARTBAUD_SBR_MASK;
1472 bd |= sbr & UARTBAUD_SBR_MASK;
1473 bd |= UARTBAUD_BOTHEDGE;
1474 bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1475 lpuart32_write(bd, sport->port.membase + UARTBAUD);
1476 lpuart32_write(modem, sport->port.membase + UARTMODIR);
1477 lpuart32_write(ctrl, sport->port.membase + UARTCTRL);
1478 /* restore control register */
1479
1480 spin_unlock_irqrestore(&sport->port.lock, flags);
1481}
1482
c9e2e946
JL		 1483static const char *lpuart_type(struct uart_port *port)
1484{
1485 return "FSL_LPUART";
1486}
1487
1488static void lpuart_release_port(struct uart_port *port)
1489{
1490 /* nothing to do */
1491}
1492
1493static int lpuart_request_port(struct uart_port *port)
1494{
1495 return 0;
1496}
1497
1498/* configure/autoconfigure the port */
1499static void lpuart_config_port(struct uart_port *port, int flags)
1500{
1501 if (flags & UART_CONFIG_TYPE)
1502 port->type = PORT_LPUART;
1503}
1504
1505static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
1506{
1507 int ret = 0;
1508
1509 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
1510 ret = -EINVAL;
1511 if (port->irq != ser->irq)
1512 ret = -EINVAL;
1513 if (ser->io_type != UPIO_MEM)
1514 ret = -EINVAL;
1515 if (port->uartclk / 16 != ser->baud_base)
1516 ret = -EINVAL;
1517 if (port->iobase != ser->port)
1518 ret = -EINVAL;
1519 if (ser->hub6 != 0)
1520 ret = -EINVAL;
1521 return ret;
1522}
1523
1524static struct uart_ops lpuart_pops = {
1525 .tx_empty = lpuart_tx_empty,
1526 .set_mctrl = lpuart_set_mctrl,
1527 .get_mctrl = lpuart_get_mctrl,
1528 .stop_tx = lpuart_stop_tx,
1529 .start_tx = lpuart_start_tx,
1530 .stop_rx = lpuart_stop_rx,
c9e2e946
JL		 1531 .break_ctl = lpuart_break_ctl,
1532 .startup = lpuart_startup,
1533 .shutdown = lpuart_shutdown,
1534 .set_termios = lpuart_set_termios,
1535 .type = lpuart_type,
1536 .request_port = lpuart_request_port,
1537 .release_port = lpuart_release_port,
1538 .config_port = lpuart_config_port,
1539 .verify_port = lpuart_verify_port,
bfc2e07f 1540 .flush_buffer = lpuart_flush_buffer,
c9e2e946
JL		 1541};
1542
380c966c
JL		 1543static struct uart_ops lpuart32_pops = {
1544 .tx_empty = lpuart32_tx_empty,
1545 .set_mctrl = lpuart32_set_mctrl,
1546 .get_mctrl = lpuart32_get_mctrl,
1547 .stop_tx = lpuart32_stop_tx,
1548 .start_tx = lpuart32_start_tx,
1549 .stop_rx = lpuart32_stop_rx,
1550 .break_ctl = lpuart32_break_ctl,
1551 .startup = lpuart32_startup,
1552 .shutdown = lpuart32_shutdown,
1553 .set_termios = lpuart32_set_termios,
1554 .type = lpuart_type,
1555 .request_port = lpuart_request_port,
1556 .release_port = lpuart_release_port,
1557 .config_port = lpuart_config_port,
1558 .verify_port = lpuart_verify_port,
bfc2e07f 1559 .flush_buffer = lpuart_flush_buffer,
380c966c
JL		 1560};
1561
c9e2e946
JL		 1562static struct lpuart_port *lpuart_ports[UART_NR];
1563
1564#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1565static void lpuart_console_putchar(struct uart_port *port, int ch)
1566{
1567 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1568 barrier();
1569
1570 writeb(ch, port->membase + UARTDR);
1571}
1572
380c966c
JL		 1573static void lpuart32_console_putchar(struct uart_port *port, int ch)
1574{
1575 while (!(lpuart32_read(port->membase + UARTSTAT) & UARTSTAT_TDRE))
1576 barrier();
1577
1578 lpuart32_write(ch, port->membase + UARTDATA);
1579}
1580
c9e2e946
JL		 1581static void
1582lpuart_console_write(struct console *co, const char *s, unsigned int count)
1583{
1584 struct lpuart_port *sport = lpuart_ports[co->index];
1585 unsigned char old_cr2, cr2;
1586
1587 /* first save CR2 and then disable interrupts */
1588 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1589 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1590 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1591 writeb(cr2, sport->port.membase + UARTCR2);
1592
1593 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1594
1595 /* wait for transmitter finish complete and restore CR2 */
1596 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1597 barrier();
1598
1599 writeb(old_cr2, sport->port.membase + UARTCR2);
1600}
1601
380c966c
JL		 1602static void
1603lpuart32_console_write(struct console *co, const char *s, unsigned int count)
1604{
1605 struct lpuart_port *sport = lpuart_ports[co->index];
1606 unsigned long old_cr, cr;
1607
1608 /* first save CR2 and then disable interrupts */
1609 cr = old_cr = lpuart32_read(sport->port.membase + UARTCTRL);
1610 cr |= (UARTCTRL_TE | UARTCTRL_RE);
1611 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1612 lpuart32_write(cr, sport->port.membase + UARTCTRL);
1613
1614 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
1615
1616 /* wait for transmitter finish complete and restore CR2 */
1617 while (!(lpuart32_read(sport->port.membase + UARTSTAT) & UARTSTAT_TC))
1618 barrier();
1619
1620 lpuart32_write(old_cr, sport->port.membase + UARTCTRL);
1621}
1622
c9e2e946
JL		 1623/*
1624 * if the port was already initialised (eg, by a boot loader),
1625 * try to determine the current setup.
1626 */
1627static void __init
1628lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1629 int *parity, int *bits)
1630{
1631 unsigned char cr, bdh, bdl, brfa;
1632 unsigned int sbr, uartclk, baud_raw;
1633
1634 cr = readb(sport->port.membase + UARTCR2);
1635 cr &= UARTCR2_TE | UARTCR2_RE;
1636 if (!cr)
1637 return;
1638
1639 /* ok, the port was enabled */
1640
1641 cr = readb(sport->port.membase + UARTCR1);
1642
1643 *parity = 'n';
1644 if (cr & UARTCR1_PE) {
1645 if (cr & UARTCR1_PT)
1646 *parity = 'o';
1647 else
1648 *parity = 'e';
1649 }
1650
1651 if (cr & UARTCR1_M)
1652 *bits = 9;
1653 else
1654 *bits = 8;
1655
1656 bdh = readb(sport->port.membase + UARTBDH);
1657 bdh &= UARTBDH_SBR_MASK;
1658 bdl = readb(sport->port.membase + UARTBDL);
1659 sbr = bdh;
1660 sbr <<= 8;
1661 sbr |= bdl;
1662 brfa = readb(sport->port.membase + UARTCR4);
1663 brfa &= UARTCR4_BRFA_MASK;
1664
1665 uartclk = clk_get_rate(sport->clk);
1666 /*
1667 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1668 */
1669 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1670
1671 if (*baud != baud_raw)
1672 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1673 "from %d to %d\n", baud_raw, *baud);
1674}
1675
380c966c
JL		 1676static void __init
1677lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
1678 int *parity, int *bits)
1679{
1680 unsigned long cr, bd;
1681 unsigned int sbr, uartclk, baud_raw;
1682
1683 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1684 cr &= UARTCTRL_TE | UARTCTRL_RE;
1685 if (!cr)
1686 return;
1687
1688 /* ok, the port was enabled */
1689
1690 cr = lpuart32_read(sport->port.membase + UARTCTRL);
1691
1692 *parity = 'n';
1693 if (cr & UARTCTRL_PE) {
1694 if (cr & UARTCTRL_PT)
1695 *parity = 'o';
1696 else
1697 *parity = 'e';
1698 }
1699
1700 if (cr & UARTCTRL_M)
1701 *bits = 9;
1702 else
1703 *bits = 8;
1704
1705 bd = lpuart32_read(sport->port.membase + UARTBAUD);
1706 bd &= UARTBAUD_SBR_MASK;
1707 sbr = bd;
1708 uartclk = clk_get_rate(sport->clk);
1709 /*
1710 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1711 */
1712 baud_raw = uartclk / (16 * sbr);
1713
1714 if (*baud != baud_raw)
1715 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1716 "from %d to %d\n", baud_raw, *baud);
1717}
1718
c9e2e946
JL		 1719static int __init lpuart_console_setup(struct console *co, char *options)
1720{
1721 struct lpuart_port *sport;
1722 int baud = 115200;
1723 int bits = 8;
1724 int parity = 'n';
1725 int flow = 'n';
1726
1727 /*
1728 * check whether an invalid uart number has been specified, and
1729 * if so, search for the first available port that does have
1730 * console support.
1731 */
1732 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1733 co->index = 0;
1734
1735 sport = lpuart_ports[co->index];
1736 if (sport == NULL)
1737 return -ENODEV;
1738
1739 if (options)
1740 uart_parse_options(options, &baud, &parity, &bits, &flow);
1741 else
380c966c
JL		 1742 if (sport->lpuart32)
1743 lpuart32_console_get_options(sport, &baud, &parity, &bits);
1744 else
1745 lpuart_console_get_options(sport, &baud, &parity, &bits);
c9e2e946 1746
380c966c
JL		 1747 if (sport->lpuart32)
1748 lpuart32_setup_watermark(sport);
1749 else
1750 lpuart_setup_watermark(sport);
c9e2e946
JL		 1751
1752 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1753}
1754
1755static struct uart_driver lpuart_reg;
1756static struct console lpuart_console = {
1757 .name = DEV_NAME,
1758 .write = lpuart_console_write,
1759 .device = uart_console_device,
1760 .setup = lpuart_console_setup,
1761 .flags = CON_PRINTBUFFER,
1762 .index = -1,
1763 .data = &lpuart_reg,
1764};
1765
380c966c
JL		 1766static struct console lpuart32_console = {
1767 .name = DEV_NAME,
1768 .write = lpuart32_console_write,
1769 .device = uart_console_device,
1770 .setup = lpuart_console_setup,
1771 .flags = CON_PRINTBUFFER,
1772 .index = -1,
1773 .data = &lpuart_reg,
1774};
1775
1d59b382
SA		 1776static void lpuart_early_write(struct console *con, const char *s, unsigned n)
1777{
1778 struct earlycon_device *dev = con->data;
1779
1780 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
1781}
1782
1783static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
1784{
1785 struct earlycon_device *dev = con->data;
1786
1787 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
1788}
1789
1790static int __init lpuart_early_console_setup(struct earlycon_device *device,
1791 const char *opt)
1792{
1793 if (!device->port.membase)
1794 return -ENODEV;
1795
1796 device->con->write = lpuart_early_write;
1797 return 0;
1798}
1799
1800static int __init lpuart32_early_console_setup(struct earlycon_device *device,
1801 const char *opt)
1802{
1803 if (!device->port.membase)
1804 return -ENODEV;
1805
1806 device->con->write = lpuart32_early_write;
1807 return 0;
1808}
1809
1810OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
1811OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
1812EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
1813EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
1814
c9e2e946 1815#define LPUART_CONSOLE (&lpuart_console)
380c966c 1816#define LPUART32_CONSOLE (&lpuart32_console)
c9e2e946
JL		 1817#else
1818#define LPUART_CONSOLE NULL
380c966c 1819#define LPUART32_CONSOLE NULL
c9e2e946
JL		 1820#endif
1821
1822static struct uart_driver lpuart_reg = {
1823 .owner = THIS_MODULE,
1824 .driver_name = DRIVER_NAME,
1825 .dev_name = DEV_NAME,
1826 .nr = ARRAY_SIZE(lpuart_ports),
1827 .cons = LPUART_CONSOLE,
1828};
1829
1830static int lpuart_probe(struct platform_device *pdev)
1831{
1832 struct device_node *np = pdev->dev.of_node;
1833 struct lpuart_port *sport;
1834 struct resource *res;
1835 int ret;
1836
1837 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1838 if (!sport)
1839 return -ENOMEM;
1840
1841 pdev->dev.coherent_dma_mask = 0;
1842
1843 ret = of_alias_get_id(np, "serial");
1844 if (ret < 0) {
1845 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1846 return ret;
1847 }
1848 sport->port.line = ret;
380c966c 1849 sport->lpuart32 = of_device_is_compatible(np, "fsl,ls1021a-lpuart");
c9e2e946 1850
4ae612a3 1851 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c9e2e946
JL		 1852 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1853 if (IS_ERR(sport->port.membase))
1854 return PTR_ERR(sport->port.membase);
1855
4ae612a3 1856 sport->port.mapbase = res->start;
c9e2e946
JL		 1857 sport->port.dev = &pdev->dev;
1858 sport->port.type = PORT_LPUART;
1859 sport->port.iotype = UPIO_MEM;
394a9e2c
JS		 1860 ret = platform_get_irq(pdev, 0);
1861 if (ret < 0) {
1862 dev_err(&pdev->dev, "cannot obtain irq\n");
1863 return ret;
1864 }
1865 sport->port.irq = ret;
1866
380c966c
JL		 1867 if (sport->lpuart32)
1868 sport->port.ops = &lpuart32_pops;
1869 else
1870 sport->port.ops = &lpuart_pops;
c9e2e946
JL		 1871 sport->port.flags = UPF_BOOT_AUTOCONF;
1872
1873 sport->clk = devm_clk_get(&pdev->dev, "ipg");
1874 if (IS_ERR(sport->clk)) {
1875 ret = PTR_ERR(sport->clk);
1876 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1877 return ret;
1878 }
1879
1880 ret = clk_prepare_enable(sport->clk);
1881 if (ret) {
1882 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1883 return ret;
1884 }
1885
1886 sport->port.uartclk = clk_get_rate(sport->clk);
1887
1888 lpuart_ports[sport->port.line] = sport;
1889
1890 platform_set_drvdata(pdev, &sport->port);
1891
380c966c
JL		 1892 if (sport->lpuart32)
1893 lpuart_reg.cons = LPUART32_CONSOLE;
1894 else
1895 lpuart_reg.cons = LPUART_CONSOLE;
1896
c9e2e946
JL		 1897 ret = uart_add_one_port(&lpuart_reg, &sport->port);
1898 if (ret) {
1899 clk_disable_unprepare(sport->clk);
1900 return ret;
1901 }
1902
4a818c43
SA		 1903 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
1904 if (!sport->dma_tx_chan)
1905 dev_info(sport->port.dev, "DMA tx channel request failed, "
1906 "operating without tx DMA\n");
1907
1908 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
1909 if (!sport->dma_rx_chan)
1910 dev_info(sport->port.dev, "DMA rx channel request failed, "
1911 "operating without rx DMA\n");
1912
c9e2e946
JL		 1913 return 0;
1914}
1915
1916static int lpuart_remove(struct platform_device *pdev)
1917{
1918 struct lpuart_port *sport = platform_get_drvdata(pdev);
1919
1920 uart_remove_one_port(&lpuart_reg, &sport->port);
1921
1922 clk_disable_unprepare(sport->clk);
1923
4a818c43
SA		 1924 if (sport->dma_tx_chan)
1925 dma_release_channel(sport->dma_tx_chan);
1926
1927 if (sport->dma_rx_chan)
1928 dma_release_channel(sport->dma_rx_chan);
1929
c9e2e946
JL		 1930 return 0;
1931}
1932
1933#ifdef CONFIG_PM_SLEEP
1934static int lpuart_suspend(struct device *dev)
1935{
1936 struct lpuart_port *sport = dev_get_drvdata(dev);
2fe605df
YY		 1937 unsigned long temp;
1938
1939 if (sport->lpuart32) {
1940 /* disable Rx/Tx and interrupts */
1941 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1942 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
1943 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1944 } else {
1945 /* disable Rx/Tx and interrupts */
1946 temp = readb(sport->port.membase + UARTCR2);
1947 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
1948 writeb(temp, sport->port.membase + UARTCR2);
1949 }
c9e2e946
JL		 1950
1951 uart_suspend_port(&lpuart_reg, &sport->port);
c05efd69
BD		 1952
1953 if (sport->lpuart_dma_rx_use) {
1954 /*
1955 * EDMA driver during suspend will forcefully release any
1956 * non-idle DMA channels. If port wakeup is enabled or if port
1957 * is console port or 'no_console_suspend' is set the Rx DMA
1958 * cannot resume as as expected, hence gracefully release the
1959 * Rx DMA path before suspend and start Rx DMA path on resume.
1960 */
1961 if (sport->port.irq_wake) {
1962 del_timer_sync(&sport->lpuart_timer);
1963 lpuart_dma_rx_free(&sport->port);
1964 }
1965
1966 /* Disable Rx DMA to use UART port as wakeup source */
1967 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS,
1968 sport->port.membase + UARTCR5);
1969 }
1970
1971 if (sport->lpuart_dma_tx_use) {
1972 sport->dma_tx_in_progress = false;
1973 dmaengine_terminate_all(sport->dma_tx_chan);
1974 }
1975
d6b0d2f2
SA		 1976 if (sport->port.suspended && !sport->port.irq_wake)
1977 clk_disable_unprepare(sport->clk);
c9e2e946
JL		 1978
1979 return 0;
1980}
1981
1982static int lpuart_resume(struct device *dev)
1983{
1984 struct lpuart_port *sport = dev_get_drvdata(dev);
08de1014
JL		 1985 unsigned long temp;
1986
d6b0d2f2
SA		 1987 if (sport->port.suspended && !sport->port.irq_wake)
1988 clk_prepare_enable(sport->clk);
1989
08de1014
JL		 1990 if (sport->lpuart32) {
1991 lpuart32_setup_watermark(sport);
1992 temp = lpuart32_read(sport->port.membase + UARTCTRL);
1993 temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE |
1994 UARTCTRL_TE | UARTCTRL_ILIE);
1995 lpuart32_write(temp, sport->port.membase + UARTCTRL);
1996 } else {
1997 lpuart_setup_watermark(sport);
1998 temp = readb(sport->port.membase + UARTCR2);
1999 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
2000 writeb(temp, sport->port.membase + UARTCR2);
2001 }
c9e2e946 2002
c05efd69
BD		 2003 if (sport->lpuart_dma_rx_use) {
2004 if (sport->port.irq_wake) {
2005 if (!lpuart_start_rx_dma(sport)) {
2006 sport->lpuart_dma_rx_use = true;
2007 rx_dma_timer_init(sport);
2008 } else {
2009 sport->lpuart_dma_rx_use = false;
2010 }
2011 }
2012 }
2013
2014 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
2015 init_waitqueue_head(&sport->dma_wait);
2016 sport->lpuart_dma_tx_use = true;
2017 writeb(readb(sport->port.membase + UARTCR5) |
2018 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
2019 } else {
2020 sport->lpuart_dma_tx_use = false;
2021 }
2022
c9e2e946
JL		 2023 uart_resume_port(&lpuart_reg, &sport->port);
2024
2025 return 0;
2026}
2027#endif
2028
2029static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2030
2031static struct platform_driver lpuart_driver = {
2032 .probe = lpuart_probe,
2033 .remove = lpuart_remove,
2034 .driver = {
2035 .name = "fsl-lpuart",
c9e2e946
JL		 2036 .of_match_table = lpuart_dt_ids,
2037 .pm = &lpuart_pm_ops,
2038 },
2039};
2040
2041static int __init lpuart_serial_init(void)
2042{
144c29ed 2043 int ret = uart_register_driver(&lpuart_reg);
c9e2e946 2044
c9e2e946
JL		 2045 if (ret)
2046 return ret;
2047
2048 ret = platform_driver_register(&lpuart_driver);
2049 if (ret)
2050 uart_unregister_driver(&lpuart_reg);
2051
39c34b09 2052 return ret;
c9e2e946
JL		 2053}
2054
2055static void __exit lpuart_serial_exit(void)
2056{
2057 platform_driver_unregister(&lpuart_driver);
2058 uart_unregister_driver(&lpuart_reg);
2059}
2060
2061module_init(lpuart_serial_init);
2062module_exit(lpuart_serial_exit);
2063
2064MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2065MODULE_LICENSE("GPL v2");
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