]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Driver for Zilog serial chips found on SGI workstations and | |
3 | * servers. This driver could actually be made more generic. | |
4 | * | |
5 | * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the | |
6 | * old drivers/sgi/char/sgiserial.c code which itself is based of the original | |
7 | * drivers/sbus/char/zs.c code. A lot of code has been simply moved over | |
8 | * directly from there but much has been rewritten. Credits therefore go out | |
9 | * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell | |
10 | * for their work there. | |
11 | * | |
12 | * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org) | |
13 | * Copyright (C) 2002 David S. Miller (davem@redhat.com) | |
14 | */ | |
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/kernel.h> | |
1da177e4 LT |
17 | #include <linux/errno.h> |
18 | #include <linux/delay.h> | |
19 | #include <linux/tty.h> | |
20 | #include <linux/tty_flip.h> | |
21 | #include <linux/major.h> | |
22 | #include <linux/string.h> | |
23 | #include <linux/ptrace.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/circ_buf.h> | |
27 | #include <linux/serial.h> | |
28 | #include <linux/sysrq.h> | |
29 | #include <linux/console.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/init.h> | |
32 | ||
33 | #include <asm/io.h> | |
34 | #include <asm/irq.h> | |
35 | #include <asm/sgialib.h> | |
36 | #include <asm/sgi/ioc.h> | |
37 | #include <asm/sgi/hpc3.h> | |
38 | #include <asm/sgi/ip22.h> | |
39 | ||
40 | #if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
41 | #define SUPPORT_SYSRQ | |
42 | #endif | |
43 | ||
44 | #include <linux/serial_core.h> | |
45 | ||
46 | #include "ip22zilog.h" | |
47 | ||
1da177e4 LT |
48 | /* |
49 | * On IP22 we need to delay after register accesses but we do not need to | |
50 | * flush writes. | |
51 | */ | |
52 | #define ZSDELAY() udelay(5) | |
53 | #define ZSDELAY_LONG() udelay(20) | |
54 | #define ZS_WSYNC(channel) do { } while (0) | |
55 | ||
56 | #define NUM_IP22ZILOG 1 | |
57 | #define NUM_CHANNELS (NUM_IP22ZILOG * 2) | |
58 | ||
59 | #define ZS_CLOCK 3672000 /* Zilog input clock rate. */ | |
60 | #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */ | |
61 | ||
62 | /* | |
63 | * We wrap our port structure around the generic uart_port. | |
64 | */ | |
65 | struct uart_ip22zilog_port { | |
66 | struct uart_port port; | |
67 | ||
68 | /* IRQ servicing chain. */ | |
69 | struct uart_ip22zilog_port *next; | |
70 | ||
71 | /* Current values of Zilog write registers. */ | |
72 | unsigned char curregs[NUM_ZSREGS]; | |
73 | ||
74 | unsigned int flags; | |
75 | #define IP22ZILOG_FLAG_IS_CONS 0x00000004 | |
76 | #define IP22ZILOG_FLAG_IS_KGDB 0x00000008 | |
77 | #define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010 | |
78 | #define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020 | |
79 | #define IP22ZILOG_FLAG_REGS_HELD 0x00000040 | |
80 | #define IP22ZILOG_FLAG_TX_STOPPED 0x00000080 | |
81 | #define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100 | |
68576cf1 | 82 | #define IP22ZILOG_FLAG_RESET_DONE 0x00000200 |
1da177e4 | 83 | |
68576cf1 | 84 | unsigned int tty_break; |
1da177e4 LT |
85 | |
86 | unsigned char parity_mask; | |
87 | unsigned char prev_status; | |
88 | }; | |
89 | ||
90 | #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase)) | |
91 | #define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT)) | |
92 | #define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \ | |
93 | (UART_ZILOG(PORT)->curregs[REGNUM]) | |
94 | #define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \ | |
95 | ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL)) | |
96 | #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS) | |
97 | #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB) | |
98 | #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS) | |
99 | #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A) | |
100 | #define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD) | |
101 | #define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED) | |
102 | #define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE) | |
103 | ||
104 | /* Reading and writing Zilog8530 registers. The delays are to make this | |
105 | * driver work on the IP22 which needs a settling delay after each chip | |
106 | * register access, other machines handle this in hardware via auxiliary | |
107 | * flip-flops which implement the settle time we do in software. | |
108 | * | |
109 | * The port lock must be held and local IRQs must be disabled | |
110 | * when {read,write}_zsreg is invoked. | |
111 | */ | |
112 | static unsigned char read_zsreg(struct zilog_channel *channel, | |
113 | unsigned char reg) | |
114 | { | |
115 | unsigned char retval; | |
116 | ||
117 | writeb(reg, &channel->control); | |
118 | ZSDELAY(); | |
119 | retval = readb(&channel->control); | |
120 | ZSDELAY(); | |
121 | ||
122 | return retval; | |
123 | } | |
124 | ||
125 | static void write_zsreg(struct zilog_channel *channel, | |
126 | unsigned char reg, unsigned char value) | |
127 | { | |
128 | writeb(reg, &channel->control); | |
129 | ZSDELAY(); | |
130 | writeb(value, &channel->control); | |
131 | ZSDELAY(); | |
132 | } | |
133 | ||
134 | static void ip22zilog_clear_fifo(struct zilog_channel *channel) | |
135 | { | |
136 | int i; | |
137 | ||
138 | for (i = 0; i < 32; i++) { | |
139 | unsigned char regval; | |
140 | ||
141 | regval = readb(&channel->control); | |
142 | ZSDELAY(); | |
143 | if (regval & Rx_CH_AV) | |
144 | break; | |
145 | ||
146 | regval = read_zsreg(channel, R1); | |
147 | readb(&channel->data); | |
148 | ZSDELAY(); | |
149 | ||
150 | if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) { | |
151 | writeb(ERR_RES, &channel->control); | |
152 | ZSDELAY(); | |
153 | ZS_WSYNC(channel); | |
154 | } | |
155 | } | |
156 | } | |
157 | ||
158 | /* This function must only be called when the TX is not busy. The UART | |
159 | * port lock must be held and local interrupts disabled. | |
160 | */ | |
161 | static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs) | |
162 | { | |
163 | int i; | |
164 | ||
165 | /* Let pending transmits finish. */ | |
166 | for (i = 0; i < 1000; i++) { | |
167 | unsigned char stat = read_zsreg(channel, R1); | |
168 | if (stat & ALL_SNT) | |
169 | break; | |
170 | udelay(100); | |
171 | } | |
172 | ||
173 | writeb(ERR_RES, &channel->control); | |
174 | ZSDELAY(); | |
175 | ZS_WSYNC(channel); | |
176 | ||
177 | ip22zilog_clear_fifo(channel); | |
178 | ||
179 | /* Disable all interrupts. */ | |
180 | write_zsreg(channel, R1, | |
181 | regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); | |
182 | ||
183 | /* Set parity, sync config, stop bits, and clock divisor. */ | |
184 | write_zsreg(channel, R4, regs[R4]); | |
185 | ||
186 | /* Set misc. TX/RX control bits. */ | |
187 | write_zsreg(channel, R10, regs[R10]); | |
188 | ||
189 | /* Set TX/RX controls sans the enable bits. */ | |
190 | write_zsreg(channel, R3, regs[R3] & ~RxENAB); | |
191 | write_zsreg(channel, R5, regs[R5] & ~TxENAB); | |
192 | ||
193 | /* Synchronous mode config. */ | |
194 | write_zsreg(channel, R6, regs[R6]); | |
195 | write_zsreg(channel, R7, regs[R7]); | |
196 | ||
197 | /* Don't mess with the interrupt vector (R2, unused by us) and | |
198 | * master interrupt control (R9). We make sure this is setup | |
199 | * properly at probe time then never touch it again. | |
200 | */ | |
201 | ||
202 | /* Disable baud generator. */ | |
203 | write_zsreg(channel, R14, regs[R14] & ~BRENAB); | |
204 | ||
205 | /* Clock mode control. */ | |
206 | write_zsreg(channel, R11, regs[R11]); | |
207 | ||
208 | /* Lower and upper byte of baud rate generator divisor. */ | |
209 | write_zsreg(channel, R12, regs[R12]); | |
210 | write_zsreg(channel, R13, regs[R13]); | |
7369a8b3 | 211 | |
1da177e4 LT |
212 | /* Now rewrite R14, with BRENAB (if set). */ |
213 | write_zsreg(channel, R14, regs[R14]); | |
214 | ||
215 | /* External status interrupt control. */ | |
216 | write_zsreg(channel, R15, regs[R15]); | |
217 | ||
218 | /* Reset external status interrupts. */ | |
219 | write_zsreg(channel, R0, RES_EXT_INT); | |
220 | write_zsreg(channel, R0, RES_EXT_INT); | |
221 | ||
222 | /* Rewrite R3/R5, this time without enables masked. */ | |
223 | write_zsreg(channel, R3, regs[R3]); | |
224 | write_zsreg(channel, R5, regs[R5]); | |
225 | ||
226 | /* Rewrite R1, this time without IRQ enabled masked. */ | |
227 | write_zsreg(channel, R1, regs[R1]); | |
228 | } | |
229 | ||
230 | /* Reprogram the Zilog channel HW registers with the copies found in the | |
231 | * software state struct. If the transmitter is busy, we defer this update | |
232 | * until the next TX complete interrupt. Else, we do it right now. | |
233 | * | |
234 | * The UART port lock must be held and local interrupts disabled. | |
235 | */ | |
236 | static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up, | |
237 | struct zilog_channel *channel) | |
238 | { | |
239 | if (!ZS_REGS_HELD(up)) { | |
240 | if (ZS_TX_ACTIVE(up)) { | |
241 | up->flags |= IP22ZILOG_FLAG_REGS_HELD; | |
242 | } else { | |
243 | __load_zsregs(channel, up->curregs); | |
244 | } | |
245 | } | |
246 | } | |
247 | ||
68576cf1 TB |
248 | #define Rx_BRK 0x0100 /* BREAK event software flag. */ |
249 | #define Rx_SYS 0x0200 /* SysRq event software flag. */ | |
250 | ||
2894500d | 251 | static bool ip22zilog_receive_chars(struct uart_ip22zilog_port *up, |
68576cf1 | 252 | struct zilog_channel *channel) |
1da177e4 | 253 | { |
68576cf1 TB |
254 | unsigned char ch, flag; |
255 | unsigned int r1; | |
2894500d | 256 | bool push = up->port.state != NULL; |
68576cf1 TB |
257 | |
258 | for (;;) { | |
259 | ch = readb(&channel->control); | |
260 | ZSDELAY(); | |
261 | if (!(ch & Rx_CH_AV)) | |
262 | break; | |
1da177e4 LT |
263 | |
264 | r1 = read_zsreg(channel, R1); | |
265 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { | |
266 | writeb(ERR_RES, &channel->control); | |
267 | ZSDELAY(); | |
268 | ZS_WSYNC(channel); | |
269 | } | |
270 | ||
1da177e4 LT |
271 | ch = readb(&channel->data); |
272 | ZSDELAY(); | |
273 | ||
274 | ch &= up->parity_mask; | |
275 | ||
68576cf1 TB |
276 | /* Handle the null char got when BREAK is removed. */ |
277 | if (!ch) | |
278 | r1 |= up->tty_break; | |
1da177e4 LT |
279 | |
280 | /* A real serial line, record the character and status. */ | |
33f0f88f | 281 | flag = TTY_NORMAL; |
1da177e4 | 282 | up->port.icount.rx++; |
68576cf1 TB |
283 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | Rx_SYS | Rx_BRK)) { |
284 | up->tty_break = 0; | |
285 | ||
286 | if (r1 & (Rx_SYS | Rx_BRK)) { | |
1da177e4 | 287 | up->port.icount.brk++; |
68576cf1 TB |
288 | if (r1 & Rx_SYS) |
289 | continue; | |
290 | r1 &= ~(PAR_ERR | CRC_ERR); | |
1da177e4 LT |
291 | } |
292 | else if (r1 & PAR_ERR) | |
293 | up->port.icount.parity++; | |
294 | else if (r1 & CRC_ERR) | |
295 | up->port.icount.frame++; | |
296 | if (r1 & Rx_OVR) | |
297 | up->port.icount.overrun++; | |
298 | r1 &= up->port.read_status_mask; | |
68576cf1 | 299 | if (r1 & Rx_BRK) |
33f0f88f | 300 | flag = TTY_BREAK; |
1da177e4 | 301 | else if (r1 & PAR_ERR) |
33f0f88f | 302 | flag = TTY_PARITY; |
1da177e4 | 303 | else if (r1 & CRC_ERR) |
33f0f88f | 304 | flag = TTY_FRAME; |
1da177e4 | 305 | } |
1da177e4 | 306 | |
68576cf1 TB |
307 | if (uart_handle_sysrq_char(&up->port, ch)) |
308 | continue; | |
33f0f88f | 309 | |
2894500d | 310 | if (push) |
68576cf1 | 311 | uart_insert_char(&up->port, r1, Rx_OVR, ch, flag); |
1da177e4 | 312 | } |
2894500d | 313 | return push; |
1da177e4 LT |
314 | } |
315 | ||
316 | static void ip22zilog_status_handle(struct uart_ip22zilog_port *up, | |
7d12e780 | 317 | struct zilog_channel *channel) |
1da177e4 LT |
318 | { |
319 | unsigned char status; | |
320 | ||
321 | status = readb(&channel->control); | |
322 | ZSDELAY(); | |
323 | ||
324 | writeb(RES_EXT_INT, &channel->control); | |
325 | ZSDELAY(); | |
326 | ZS_WSYNC(channel); | |
327 | ||
68576cf1 TB |
328 | if (up->curregs[R15] & BRKIE) { |
329 | if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) { | |
330 | if (uart_handle_break(&up->port)) | |
331 | up->tty_break = Rx_SYS; | |
332 | else | |
333 | up->tty_break = Rx_BRK; | |
334 | } | |
335 | } | |
336 | ||
1da177e4 LT |
337 | if (ZS_WANTS_MODEM_STATUS(up)) { |
338 | if (status & SYNC) | |
339 | up->port.icount.dsr++; | |
340 | ||
341 | /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. | |
342 | * But it does not tell us which bit has changed, we have to keep | |
343 | * track of this ourselves. | |
344 | */ | |
68576cf1 | 345 | if ((status ^ up->prev_status) ^ DCD) |
1da177e4 LT |
346 | uart_handle_dcd_change(&up->port, |
347 | (status & DCD)); | |
68576cf1 | 348 | if ((status ^ up->prev_status) ^ CTS) |
1da177e4 LT |
349 | uart_handle_cts_change(&up->port, |
350 | (status & CTS)); | |
351 | ||
bdc04e31 | 352 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); |
1da177e4 LT |
353 | } |
354 | ||
355 | up->prev_status = status; | |
356 | } | |
357 | ||
358 | static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up, | |
359 | struct zilog_channel *channel) | |
360 | { | |
361 | struct circ_buf *xmit; | |
362 | ||
363 | if (ZS_IS_CONS(up)) { | |
364 | unsigned char status = readb(&channel->control); | |
365 | ZSDELAY(); | |
366 | ||
367 | /* TX still busy? Just wait for the next TX done interrupt. | |
368 | * | |
369 | * It can occur because of how we do serial console writes. It would | |
370 | * be nice to transmit console writes just like we normally would for | |
371 | * a TTY line. (ie. buffered and TX interrupt driven). That is not | |
372 | * easy because console writes cannot sleep. One solution might be | |
25985edc | 373 | * to poll on enough port->xmit space becoming free. -DaveM |
1da177e4 LT |
374 | */ |
375 | if (!(status & Tx_BUF_EMP)) | |
376 | return; | |
377 | } | |
378 | ||
379 | up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE; | |
380 | ||
381 | if (ZS_REGS_HELD(up)) { | |
382 | __load_zsregs(channel, up->curregs); | |
383 | up->flags &= ~IP22ZILOG_FLAG_REGS_HELD; | |
384 | } | |
385 | ||
386 | if (ZS_TX_STOPPED(up)) { | |
387 | up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; | |
388 | goto ack_tx_int; | |
389 | } | |
390 | ||
391 | if (up->port.x_char) { | |
392 | up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; | |
393 | writeb(up->port.x_char, &channel->data); | |
394 | ZSDELAY(); | |
395 | ZS_WSYNC(channel); | |
396 | ||
397 | up->port.icount.tx++; | |
398 | up->port.x_char = 0; | |
399 | return; | |
400 | } | |
401 | ||
ebd2c8f6 | 402 | if (up->port.state == NULL) |
1da177e4 | 403 | goto ack_tx_int; |
ebd2c8f6 | 404 | xmit = &up->port.state->xmit; |
c4432c41 | 405 | if (uart_circ_empty(xmit)) |
1da177e4 | 406 | goto ack_tx_int; |
1da177e4 LT |
407 | if (uart_tx_stopped(&up->port)) |
408 | goto ack_tx_int; | |
409 | ||
410 | up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; | |
411 | writeb(xmit->buf[xmit->tail], &channel->data); | |
412 | ZSDELAY(); | |
413 | ZS_WSYNC(channel); | |
414 | ||
415 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
416 | up->port.icount.tx++; | |
417 | ||
418 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
419 | uart_write_wakeup(&up->port); | |
420 | ||
421 | return; | |
422 | ||
423 | ack_tx_int: | |
424 | writeb(RES_Tx_P, &channel->control); | |
425 | ZSDELAY(); | |
426 | ZS_WSYNC(channel); | |
427 | } | |
428 | ||
7d12e780 | 429 | static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id) |
1da177e4 LT |
430 | { |
431 | struct uart_ip22zilog_port *up = dev_id; | |
432 | ||
433 | while (up) { | |
434 | struct zilog_channel *channel | |
435 | = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
436 | unsigned char r3; | |
2894500d | 437 | bool push = false; |
1da177e4 LT |
438 | |
439 | spin_lock(&up->port.lock); | |
440 | r3 = read_zsreg(channel, R3); | |
441 | ||
442 | /* Channel A */ | |
443 | if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { | |
444 | writeb(RES_H_IUS, &channel->control); | |
445 | ZSDELAY(); | |
446 | ZS_WSYNC(channel); | |
447 | ||
448 | if (r3 & CHARxIP) | |
2894500d | 449 | push = ip22zilog_receive_chars(up, channel); |
1da177e4 | 450 | if (r3 & CHAEXT) |
7d12e780 | 451 | ip22zilog_status_handle(up, channel); |
1da177e4 LT |
452 | if (r3 & CHATxIP) |
453 | ip22zilog_transmit_chars(up, channel); | |
454 | } | |
455 | spin_unlock(&up->port.lock); | |
456 | ||
2894500d JS |
457 | if (push) |
458 | tty_flip_buffer_push(&up->port.state->port); | |
68576cf1 | 459 | |
1da177e4 LT |
460 | /* Channel B */ |
461 | up = up->next; | |
462 | channel = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
2894500d | 463 | push = false; |
1da177e4 LT |
464 | |
465 | spin_lock(&up->port.lock); | |
466 | if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { | |
467 | writeb(RES_H_IUS, &channel->control); | |
468 | ZSDELAY(); | |
469 | ZS_WSYNC(channel); | |
470 | ||
471 | if (r3 & CHBRxIP) | |
2894500d | 472 | push = ip22zilog_receive_chars(up, channel); |
1da177e4 | 473 | if (r3 & CHBEXT) |
7d12e780 | 474 | ip22zilog_status_handle(up, channel); |
1da177e4 LT |
475 | if (r3 & CHBTxIP) |
476 | ip22zilog_transmit_chars(up, channel); | |
477 | } | |
478 | spin_unlock(&up->port.lock); | |
479 | ||
2894500d JS |
480 | if (push) |
481 | tty_flip_buffer_push(&up->port.state->port); | |
68576cf1 | 482 | |
1da177e4 LT |
483 | up = up->next; |
484 | } | |
485 | ||
486 | return IRQ_HANDLED; | |
487 | } | |
488 | ||
489 | /* A convenient way to quickly get R0 status. The caller must _not_ hold the | |
490 | * port lock, it is acquired here. | |
491 | */ | |
492 | static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port) | |
493 | { | |
494 | struct zilog_channel *channel; | |
1da177e4 LT |
495 | unsigned char status; |
496 | ||
1da177e4 LT |
497 | channel = ZILOG_CHANNEL_FROM_PORT(port); |
498 | status = readb(&channel->control); | |
499 | ZSDELAY(); | |
500 | ||
1da177e4 LT |
501 | return status; |
502 | } | |
503 | ||
504 | /* The port lock is not held. */ | |
505 | static unsigned int ip22zilog_tx_empty(struct uart_port *port) | |
506 | { | |
c5f4644e | 507 | unsigned long flags; |
1da177e4 LT |
508 | unsigned char status; |
509 | unsigned int ret; | |
510 | ||
c5f4644e RK |
511 | spin_lock_irqsave(&port->lock, flags); |
512 | ||
1da177e4 | 513 | status = ip22zilog_read_channel_status(port); |
c5f4644e RK |
514 | |
515 | spin_unlock_irqrestore(&port->lock, flags); | |
516 | ||
1da177e4 LT |
517 | if (status & Tx_BUF_EMP) |
518 | ret = TIOCSER_TEMT; | |
519 | else | |
520 | ret = 0; | |
521 | ||
522 | return ret; | |
523 | } | |
524 | ||
c5f4644e | 525 | /* The port lock is held and interrupts are disabled. */ |
1da177e4 LT |
526 | static unsigned int ip22zilog_get_mctrl(struct uart_port *port) |
527 | { | |
528 | unsigned char status; | |
529 | unsigned int ret; | |
530 | ||
531 | status = ip22zilog_read_channel_status(port); | |
532 | ||
533 | ret = 0; | |
534 | if (status & DCD) | |
535 | ret |= TIOCM_CAR; | |
536 | if (status & SYNC) | |
537 | ret |= TIOCM_DSR; | |
538 | if (status & CTS) | |
539 | ret |= TIOCM_CTS; | |
540 | ||
541 | return ret; | |
542 | } | |
543 | ||
544 | /* The port lock is held and interrupts are disabled. */ | |
545 | static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
546 | { | |
547 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
548 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); | |
549 | unsigned char set_bits, clear_bits; | |
550 | ||
551 | set_bits = clear_bits = 0; | |
552 | ||
553 | if (mctrl & TIOCM_RTS) | |
554 | set_bits |= RTS; | |
555 | else | |
556 | clear_bits |= RTS; | |
557 | if (mctrl & TIOCM_DTR) | |
558 | set_bits |= DTR; | |
559 | else | |
560 | clear_bits |= DTR; | |
561 | ||
7369a8b3 | 562 | /* NOTE: Not subject to 'transmitter active' rule. */ |
1da177e4 LT |
563 | up->curregs[R5] |= set_bits; |
564 | up->curregs[R5] &= ~clear_bits; | |
565 | write_zsreg(channel, R5, up->curregs[R5]); | |
566 | } | |
567 | ||
568 | /* The port lock is held and interrupts are disabled. */ | |
b129a8cc | 569 | static void ip22zilog_stop_tx(struct uart_port *port) |
1da177e4 LT |
570 | { |
571 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
572 | ||
573 | up->flags |= IP22ZILOG_FLAG_TX_STOPPED; | |
574 | } | |
575 | ||
576 | /* The port lock is held and interrupts are disabled. */ | |
b129a8cc | 577 | static void ip22zilog_start_tx(struct uart_port *port) |
1da177e4 LT |
578 | { |
579 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
580 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); | |
581 | unsigned char status; | |
582 | ||
583 | up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; | |
584 | up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; | |
585 | ||
586 | status = readb(&channel->control); | |
587 | ZSDELAY(); | |
588 | ||
589 | /* TX busy? Just wait for the TX done interrupt. */ | |
590 | if (!(status & Tx_BUF_EMP)) | |
591 | return; | |
592 | ||
593 | /* Send the first character to jump-start the TX done | |
594 | * IRQ sending engine. | |
595 | */ | |
596 | if (port->x_char) { | |
597 | writeb(port->x_char, &channel->data); | |
598 | ZSDELAY(); | |
599 | ZS_WSYNC(channel); | |
600 | ||
601 | port->icount.tx++; | |
602 | port->x_char = 0; | |
603 | } else { | |
ebd2c8f6 | 604 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 LT |
605 | |
606 | writeb(xmit->buf[xmit->tail], &channel->data); | |
607 | ZSDELAY(); | |
608 | ZS_WSYNC(channel); | |
609 | ||
610 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
611 | port->icount.tx++; | |
612 | ||
613 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
614 | uart_write_wakeup(&up->port); | |
615 | } | |
616 | } | |
617 | ||
618 | /* The port lock is held and interrupts are disabled. */ | |
619 | static void ip22zilog_stop_rx(struct uart_port *port) | |
620 | { | |
621 | struct uart_ip22zilog_port *up = UART_ZILOG(port); | |
622 | struct zilog_channel *channel; | |
623 | ||
624 | if (ZS_IS_CONS(up)) | |
625 | return; | |
626 | ||
627 | channel = ZILOG_CHANNEL_FROM_PORT(port); | |
628 | ||
629 | /* Disable all RX interrupts. */ | |
630 | up->curregs[R1] &= ~RxINT_MASK; | |
631 | ip22zilog_maybe_update_regs(up, channel); | |
632 | } | |
633 | ||
634 | /* The port lock is held. */ | |
635 | static void ip22zilog_enable_ms(struct uart_port *port) | |
636 | { | |
637 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
638 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); | |
639 | unsigned char new_reg; | |
640 | ||
641 | new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE); | |
642 | if (new_reg != up->curregs[R15]) { | |
643 | up->curregs[R15] = new_reg; | |
644 | ||
7369a8b3 | 645 | /* NOTE: Not subject to 'transmitter active' rule. */ |
1da177e4 LT |
646 | write_zsreg(channel, R15, up->curregs[R15]); |
647 | } | |
648 | } | |
649 | ||
650 | /* The port lock is not held. */ | |
651 | static void ip22zilog_break_ctl(struct uart_port *port, int break_state) | |
652 | { | |
653 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
654 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); | |
655 | unsigned char set_bits, clear_bits, new_reg; | |
656 | unsigned long flags; | |
657 | ||
658 | set_bits = clear_bits = 0; | |
659 | ||
660 | if (break_state) | |
661 | set_bits |= SND_BRK; | |
662 | else | |
663 | clear_bits |= SND_BRK; | |
664 | ||
665 | spin_lock_irqsave(&port->lock, flags); | |
666 | ||
667 | new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; | |
668 | if (new_reg != up->curregs[R5]) { | |
669 | up->curregs[R5] = new_reg; | |
670 | ||
7369a8b3 | 671 | /* NOTE: Not subject to 'transmitter active' rule. */ |
1da177e4 LT |
672 | write_zsreg(channel, R5, up->curregs[R5]); |
673 | } | |
674 | ||
675 | spin_unlock_irqrestore(&port->lock, flags); | |
676 | } | |
677 | ||
68576cf1 TB |
678 | static void __ip22zilog_reset(struct uart_ip22zilog_port *up) |
679 | { | |
680 | struct zilog_channel *channel; | |
681 | int i; | |
682 | ||
683 | if (up->flags & IP22ZILOG_FLAG_RESET_DONE) | |
684 | return; | |
685 | ||
686 | /* Let pending transmits finish. */ | |
687 | channel = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
688 | for (i = 0; i < 1000; i++) { | |
689 | unsigned char stat = read_zsreg(channel, R1); | |
690 | if (stat & ALL_SNT) | |
691 | break; | |
692 | udelay(100); | |
693 | } | |
694 | ||
695 | if (!ZS_IS_CHANNEL_A(up)) { | |
696 | up++; | |
697 | channel = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
698 | } | |
699 | write_zsreg(channel, R9, FHWRES); | |
700 | ZSDELAY_LONG(); | |
701 | (void) read_zsreg(channel, R0); | |
702 | ||
703 | up->flags |= IP22ZILOG_FLAG_RESET_DONE; | |
704 | up->next->flags |= IP22ZILOG_FLAG_RESET_DONE; | |
705 | } | |
706 | ||
1da177e4 LT |
707 | static void __ip22zilog_startup(struct uart_ip22zilog_port *up) |
708 | { | |
709 | struct zilog_channel *channel; | |
710 | ||
711 | channel = ZILOG_CHANNEL_FROM_PORT(&up->port); | |
68576cf1 TB |
712 | |
713 | __ip22zilog_reset(up); | |
714 | ||
715 | __load_zsregs(channel, up->curregs); | |
716 | /* set master interrupt enable */ | |
717 | write_zsreg(channel, R9, up->curregs[R9]); | |
1da177e4 LT |
718 | up->prev_status = readb(&channel->control); |
719 | ||
720 | /* Enable receiver and transmitter. */ | |
721 | up->curregs[R3] |= RxENAB; | |
722 | up->curregs[R5] |= TxENAB; | |
723 | ||
724 | up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; | |
725 | ip22zilog_maybe_update_regs(up, channel); | |
726 | } | |
727 | ||
728 | static int ip22zilog_startup(struct uart_port *port) | |
729 | { | |
730 | struct uart_ip22zilog_port *up = UART_ZILOG(port); | |
731 | unsigned long flags; | |
732 | ||
733 | if (ZS_IS_CONS(up)) | |
734 | return 0; | |
735 | ||
736 | spin_lock_irqsave(&port->lock, flags); | |
737 | __ip22zilog_startup(up); | |
738 | spin_unlock_irqrestore(&port->lock, flags); | |
739 | return 0; | |
740 | } | |
741 | ||
742 | /* | |
743 | * The test for ZS_IS_CONS is explained by the following e-mail: | |
744 | ***** | |
745 | * From: Russell King <rmk@arm.linux.org.uk> | |
746 | * Date: Sun, 8 Dec 2002 10:18:38 +0000 | |
747 | * | |
748 | * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote: | |
749 | * > I boot my 2.5 boxes using "console=ttyS0,9600" argument, | |
750 | * > and I noticed that something is not right with reference | |
751 | * > counting in this case. It seems that when the console | |
752 | * > is open by kernel initially, this is not accounted | |
753 | * > as an open, and uart_startup is not called. | |
754 | * | |
755 | * That is correct. We are unable to call uart_startup when the serial | |
756 | * console is initialised because it may need to allocate memory (as | |
757 | * request_irq does) and the memory allocators may not have been | |
758 | * initialised. | |
759 | * | |
760 | * 1. initialise the port into a state where it can send characters in the | |
761 | * console write method. | |
762 | * | |
763 | * 2. don't do the actual hardware shutdown in your shutdown() method (but | |
764 | * do the normal software shutdown - ie, free irqs etc) | |
765 | ***** | |
766 | */ | |
767 | static void ip22zilog_shutdown(struct uart_port *port) | |
768 | { | |
769 | struct uart_ip22zilog_port *up = UART_ZILOG(port); | |
770 | struct zilog_channel *channel; | |
771 | unsigned long flags; | |
772 | ||
773 | if (ZS_IS_CONS(up)) | |
774 | return; | |
775 | ||
776 | spin_lock_irqsave(&port->lock, flags); | |
777 | ||
778 | channel = ZILOG_CHANNEL_FROM_PORT(port); | |
779 | ||
780 | /* Disable receiver and transmitter. */ | |
781 | up->curregs[R3] &= ~RxENAB; | |
782 | up->curregs[R5] &= ~TxENAB; | |
783 | ||
784 | /* Disable all interrupts and BRK assertion. */ | |
785 | up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); | |
786 | up->curregs[R5] &= ~SND_BRK; | |
787 | ip22zilog_maybe_update_regs(up, channel); | |
788 | ||
789 | spin_unlock_irqrestore(&port->lock, flags); | |
790 | } | |
791 | ||
792 | /* Shared by TTY driver and serial console setup. The port lock is held | |
793 | * and local interrupts are disabled. | |
794 | */ | |
795 | static void | |
796 | ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag, | |
797 | unsigned int iflag, int brg) | |
798 | { | |
799 | ||
800 | up->curregs[R10] = NRZ; | |
801 | up->curregs[R11] = TCBR | RCBR; | |
802 | ||
803 | /* Program BAUD and clock source. */ | |
804 | up->curregs[R4] &= ~XCLK_MASK; | |
805 | up->curregs[R4] |= X16CLK; | |
806 | up->curregs[R12] = brg & 0xff; | |
807 | up->curregs[R13] = (brg >> 8) & 0xff; | |
808 | up->curregs[R14] = BRENAB; | |
809 | ||
810 | /* Character size, stop bits, and parity. */ | |
811 | up->curregs[3] &= ~RxN_MASK; | |
812 | up->curregs[5] &= ~TxN_MASK; | |
813 | switch (cflag & CSIZE) { | |
814 | case CS5: | |
815 | up->curregs[3] |= Rx5; | |
816 | up->curregs[5] |= Tx5; | |
817 | up->parity_mask = 0x1f; | |
818 | break; | |
819 | case CS6: | |
820 | up->curregs[3] |= Rx6; | |
821 | up->curregs[5] |= Tx6; | |
822 | up->parity_mask = 0x3f; | |
823 | break; | |
824 | case CS7: | |
825 | up->curregs[3] |= Rx7; | |
826 | up->curregs[5] |= Tx7; | |
827 | up->parity_mask = 0x7f; | |
828 | break; | |
829 | case CS8: | |
830 | default: | |
831 | up->curregs[3] |= Rx8; | |
832 | up->curregs[5] |= Tx8; | |
833 | up->parity_mask = 0xff; | |
834 | break; | |
fc811472 | 835 | } |
1da177e4 LT |
836 | up->curregs[4] &= ~0x0c; |
837 | if (cflag & CSTOPB) | |
838 | up->curregs[4] |= SB2; | |
839 | else | |
840 | up->curregs[4] |= SB1; | |
841 | if (cflag & PARENB) | |
842 | up->curregs[4] |= PAR_ENAB; | |
843 | else | |
844 | up->curregs[4] &= ~PAR_ENAB; | |
845 | if (!(cflag & PARODD)) | |
846 | up->curregs[4] |= PAR_EVEN; | |
847 | else | |
848 | up->curregs[4] &= ~PAR_EVEN; | |
849 | ||
850 | up->port.read_status_mask = Rx_OVR; | |
851 | if (iflag & INPCK) | |
852 | up->port.read_status_mask |= CRC_ERR | PAR_ERR; | |
853 | if (iflag & (BRKINT | PARMRK)) | |
854 | up->port.read_status_mask |= BRK_ABRT; | |
855 | ||
856 | up->port.ignore_status_mask = 0; | |
857 | if (iflag & IGNPAR) | |
858 | up->port.ignore_status_mask |= CRC_ERR | PAR_ERR; | |
859 | if (iflag & IGNBRK) { | |
860 | up->port.ignore_status_mask |= BRK_ABRT; | |
861 | if (iflag & IGNPAR) | |
862 | up->port.ignore_status_mask |= Rx_OVR; | |
863 | } | |
864 | ||
865 | if ((cflag & CREAD) == 0) | |
866 | up->port.ignore_status_mask = 0xff; | |
867 | } | |
868 | ||
869 | /* The port lock is not held. */ | |
870 | static void | |
606d099c AC |
871 | ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios, |
872 | struct ktermios *old) | |
1da177e4 LT |
873 | { |
874 | struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; | |
875 | unsigned long flags; | |
876 | int baud, brg; | |
877 | ||
878 | baud = uart_get_baud_rate(port, termios, old, 1200, 76800); | |
879 | ||
880 | spin_lock_irqsave(&up->port.lock, flags); | |
881 | ||
882 | brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); | |
883 | ||
884 | ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg); | |
885 | ||
886 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
887 | up->flags |= IP22ZILOG_FLAG_MODEM_STATUS; | |
888 | else | |
889 | up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS; | |
890 | ||
1da177e4 | 891 | ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port)); |
c1fbac44 | 892 | uart_update_timeout(port, termios->c_cflag, baud); |
1da177e4 LT |
893 | |
894 | spin_unlock_irqrestore(&up->port.lock, flags); | |
895 | } | |
896 | ||
897 | static const char *ip22zilog_type(struct uart_port *port) | |
898 | { | |
899 | return "IP22-Zilog"; | |
900 | } | |
901 | ||
902 | /* We do not request/release mappings of the registers here, this | |
903 | * happens at early serial probe time. | |
904 | */ | |
905 | static void ip22zilog_release_port(struct uart_port *port) | |
906 | { | |
907 | } | |
908 | ||
909 | static int ip22zilog_request_port(struct uart_port *port) | |
910 | { | |
911 | return 0; | |
912 | } | |
913 | ||
914 | /* These do not need to do anything interesting either. */ | |
915 | static void ip22zilog_config_port(struct uart_port *port, int flags) | |
916 | { | |
917 | } | |
918 | ||
919 | /* We do not support letting the user mess with the divisor, IRQ, etc. */ | |
920 | static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser) | |
921 | { | |
922 | return -EINVAL; | |
923 | } | |
924 | ||
925 | static struct uart_ops ip22zilog_pops = { | |
926 | .tx_empty = ip22zilog_tx_empty, | |
927 | .set_mctrl = ip22zilog_set_mctrl, | |
928 | .get_mctrl = ip22zilog_get_mctrl, | |
929 | .stop_tx = ip22zilog_stop_tx, | |
930 | .start_tx = ip22zilog_start_tx, | |
931 | .stop_rx = ip22zilog_stop_rx, | |
932 | .enable_ms = ip22zilog_enable_ms, | |
933 | .break_ctl = ip22zilog_break_ctl, | |
934 | .startup = ip22zilog_startup, | |
935 | .shutdown = ip22zilog_shutdown, | |
936 | .set_termios = ip22zilog_set_termios, | |
937 | .type = ip22zilog_type, | |
938 | .release_port = ip22zilog_release_port, | |
939 | .request_port = ip22zilog_request_port, | |
940 | .config_port = ip22zilog_config_port, | |
941 | .verify_port = ip22zilog_verify_port, | |
942 | }; | |
943 | ||
944 | static struct uart_ip22zilog_port *ip22zilog_port_table; | |
945 | static struct zilog_layout **ip22zilog_chip_regs; | |
946 | ||
947 | static struct uart_ip22zilog_port *ip22zilog_irq_chain; | |
948 | static int zilog_irq = -1; | |
949 | ||
950 | static void * __init alloc_one_table(unsigned long size) | |
951 | { | |
8f31bb39 | 952 | return kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
953 | } |
954 | ||
955 | static void __init ip22zilog_alloc_tables(void) | |
956 | { | |
957 | ip22zilog_port_table = (struct uart_ip22zilog_port *) | |
958 | alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port)); | |
959 | ip22zilog_chip_regs = (struct zilog_layout **) | |
960 | alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *)); | |
961 | ||
962 | if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) { | |
963 | panic("IP22-Zilog: Cannot allocate IP22-Zilog tables."); | |
964 | } | |
965 | } | |
966 | ||
967 | /* Get the address of the registers for IP22-Zilog instance CHIP. */ | |
968 | static struct zilog_layout * __init get_zs(int chip) | |
969 | { | |
970 | unsigned long base; | |
971 | ||
972 | if (chip < 0 || chip >= NUM_IP22ZILOG) { | |
973 | panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip); | |
974 | } | |
975 | ||
976 | /* Not probe-able, hard code it. */ | |
977 | base = (unsigned long) &sgioc->uart; | |
978 | ||
979 | zilog_irq = SGI_SERIAL_IRQ; | |
980 | request_mem_region(base, 8, "IP22-Zilog"); | |
981 | ||
982 | return (struct zilog_layout *) base; | |
983 | } | |
984 | ||
985 | #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */ | |
986 | ||
987 | #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE | |
d358788f | 988 | static void ip22zilog_put_char(struct uart_port *port, int ch) |
1da177e4 | 989 | { |
d358788f | 990 | struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); |
1da177e4 LT |
991 | int loops = ZS_PUT_CHAR_MAX_DELAY; |
992 | ||
993 | /* This is a timed polling loop so do not switch the explicit | |
994 | * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM | |
995 | */ | |
996 | do { | |
997 | unsigned char val = readb(&channel->control); | |
998 | if (val & Tx_BUF_EMP) { | |
999 | ZSDELAY(); | |
1000 | break; | |
1001 | } | |
1002 | udelay(5); | |
1003 | } while (--loops); | |
1004 | ||
1005 | writeb(ch, &channel->data); | |
1006 | ZSDELAY(); | |
1007 | ZS_WSYNC(channel); | |
1008 | } | |
1009 | ||
1010 | static void | |
1011 | ip22zilog_console_write(struct console *con, const char *s, unsigned int count) | |
1012 | { | |
1013 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; | |
1da177e4 | 1014 | unsigned long flags; |
1da177e4 LT |
1015 | |
1016 | spin_lock_irqsave(&up->port.lock, flags); | |
d358788f | 1017 | uart_console_write(&up->port, s, count, ip22zilog_put_char); |
1da177e4 LT |
1018 | udelay(2); |
1019 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1020 | } | |
1021 | ||
1da177e4 LT |
1022 | static int __init ip22zilog_console_setup(struct console *con, char *options) |
1023 | { | |
1024 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; | |
1025 | unsigned long flags; | |
68576cf1 TB |
1026 | int baud = 9600, bits = 8; |
1027 | int parity = 'n'; | |
1028 | int flow = 'n'; | |
1da177e4 | 1029 | |
68576cf1 | 1030 | up->flags |= IP22ZILOG_FLAG_IS_CONS; |
1da177e4 | 1031 | |
68576cf1 | 1032 | printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index); |
1da177e4 LT |
1033 | |
1034 | spin_lock_irqsave(&up->port.lock, flags); | |
1035 | ||
68576cf1 | 1036 | up->curregs[R15] |= BRKIE; |
1da177e4 LT |
1037 | |
1038 | __ip22zilog_startup(up); | |
1039 | ||
1040 | spin_unlock_irqrestore(&up->port.lock, flags); | |
1041 | ||
68576cf1 TB |
1042 | if (options) |
1043 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1044 | return uart_set_options(&up->port, con, baud, parity, bits, flow); | |
1da177e4 LT |
1045 | } |
1046 | ||
1047 | static struct uart_driver ip22zilog_reg; | |
1048 | ||
1049 | static struct console ip22zilog_console = { | |
1050 | .name = "ttyS", | |
1051 | .write = ip22zilog_console_write, | |
1052 | .device = uart_console_device, | |
1053 | .setup = ip22zilog_console_setup, | |
1054 | .flags = CON_PRINTBUFFER, | |
1055 | .index = -1, | |
1056 | .data = &ip22zilog_reg, | |
1057 | }; | |
1058 | #endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */ | |
1059 | ||
1060 | static struct uart_driver ip22zilog_reg = { | |
1061 | .owner = THIS_MODULE, | |
1062 | .driver_name = "serial", | |
1da177e4 LT |
1063 | .dev_name = "ttyS", |
1064 | .major = TTY_MAJOR, | |
1065 | .minor = 64, | |
1066 | .nr = NUM_CHANNELS, | |
1067 | #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE | |
1068 | .cons = &ip22zilog_console, | |
1069 | #endif | |
1070 | }; | |
1071 | ||
1072 | static void __init ip22zilog_prepare(void) | |
1073 | { | |
1074 | struct uart_ip22zilog_port *up; | |
1075 | struct zilog_layout *rp; | |
1076 | int channel, chip; | |
1077 | ||
1078 | /* | |
1079 | * Temporary fix. | |
1080 | */ | |
1081 | for (channel = 0; channel < NUM_CHANNELS; channel++) | |
1082 | spin_lock_init(&ip22zilog_port_table[channel].port.lock); | |
1083 | ||
1084 | ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1]; | |
1085 | up = &ip22zilog_port_table[0]; | |
1086 | for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--) | |
1087 | up[channel].next = &up[channel - 1]; | |
1088 | up[channel].next = NULL; | |
1089 | ||
1090 | for (chip = 0; chip < NUM_IP22ZILOG; chip++) { | |
1091 | if (!ip22zilog_chip_regs[chip]) { | |
1092 | ip22zilog_chip_regs[chip] = rp = get_zs(chip); | |
1093 | ||
1094 | up[(chip * 2) + 0].port.membase = (char *) &rp->channelB; | |
1095 | up[(chip * 2) + 1].port.membase = (char *) &rp->channelA; | |
1096 | ||
1097 | /* In theory mapbase is the physical address ... */ | |
1098 | up[(chip * 2) + 0].port.mapbase = | |
1099 | (unsigned long) ioremap((unsigned long) &rp->channelB, 8); | |
1100 | up[(chip * 2) + 1].port.mapbase = | |
1101 | (unsigned long) ioremap((unsigned long) &rp->channelA, 8); | |
1102 | } | |
1103 | ||
1104 | /* Channel A */ | |
1105 | up[(chip * 2) + 0].port.iotype = UPIO_MEM; | |
1106 | up[(chip * 2) + 0].port.irq = zilog_irq; | |
1107 | up[(chip * 2) + 0].port.uartclk = ZS_CLOCK; | |
1108 | up[(chip * 2) + 0].port.fifosize = 1; | |
1109 | up[(chip * 2) + 0].port.ops = &ip22zilog_pops; | |
1110 | up[(chip * 2) + 0].port.type = PORT_IP22ZILOG; | |
1111 | up[(chip * 2) + 0].port.flags = 0; | |
1112 | up[(chip * 2) + 0].port.line = (chip * 2) + 0; | |
1113 | up[(chip * 2) + 0].flags = 0; | |
1114 | ||
1115 | /* Channel B */ | |
1116 | up[(chip * 2) + 1].port.iotype = UPIO_MEM; | |
1117 | up[(chip * 2) + 1].port.irq = zilog_irq; | |
1118 | up[(chip * 2) + 1].port.uartclk = ZS_CLOCK; | |
1119 | up[(chip * 2) + 1].port.fifosize = 1; | |
1120 | up[(chip * 2) + 1].port.ops = &ip22zilog_pops; | |
1121 | up[(chip * 2) + 1].port.type = PORT_IP22ZILOG; | |
1da177e4 | 1122 | up[(chip * 2) + 1].port.line = (chip * 2) + 1; |
c65b15cf | 1123 | up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A; |
1da177e4 | 1124 | } |
1da177e4 | 1125 | |
68576cf1 TB |
1126 | for (channel = 0; channel < NUM_CHANNELS; channel++) { |
1127 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel]; | |
1128 | int brg; | |
1da177e4 LT |
1129 | |
1130 | /* Normal serial TTY. */ | |
1131 | up->parity_mask = 0xff; | |
1132 | up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; | |
1133 | up->curregs[R4] = PAR_EVEN | X16CLK | SB1; | |
1134 | up->curregs[R3] = RxENAB | Rx8; | |
1135 | up->curregs[R5] = TxENAB | Tx8; | |
1136 | up->curregs[R9] = NV | MIE; | |
1137 | up->curregs[R10] = NRZ; | |
1138 | up->curregs[R11] = TCBR | RCBR; | |
68576cf1 | 1139 | brg = BPS_TO_BRG(9600, ZS_CLOCK / ZS_CLOCK_DIVISOR); |
1da177e4 LT |
1140 | up->curregs[R12] = (brg & 0xff); |
1141 | up->curregs[R13] = (brg >> 8) & 0xff; | |
1142 | up->curregs[R14] = BRENAB; | |
1da177e4 LT |
1143 | } |
1144 | } | |
1145 | ||
1146 | static int __init ip22zilog_ports_init(void) | |
1147 | { | |
1148 | int ret; | |
1149 | ||
1150 | printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG); | |
1151 | ||
1152 | ip22zilog_prepare(); | |
1153 | ||
1154 | if (request_irq(zilog_irq, ip22zilog_interrupt, 0, | |
1155 | "IP22-Zilog", ip22zilog_irq_chain)) { | |
1156 | panic("IP22-Zilog: Unable to register zs interrupt handler.\n"); | |
1157 | } | |
1158 | ||
1da177e4 LT |
1159 | ret = uart_register_driver(&ip22zilog_reg); |
1160 | if (ret == 0) { | |
1161 | int i; | |
1162 | ||
1163 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1164 | struct uart_ip22zilog_port *up = &ip22zilog_port_table[i]; | |
1165 | ||
1166 | uart_add_one_port(&ip22zilog_reg, &up->port); | |
1167 | } | |
1168 | } | |
1169 | ||
1170 | return ret; | |
1171 | } | |
1172 | ||
1173 | static int __init ip22zilog_init(void) | |
1174 | { | |
1175 | /* IP22 Zilog setup is hard coded, no probing to do. */ | |
1176 | ip22zilog_alloc_tables(); | |
1177 | ip22zilog_ports_init(); | |
1178 | ||
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | static void __exit ip22zilog_exit(void) | |
1183 | { | |
1184 | int i; | |
6257b3bd | 1185 | struct uart_ip22zilog_port *up; |
1da177e4 LT |
1186 | |
1187 | for (i = 0; i < NUM_CHANNELS; i++) { | |
6257b3bd | 1188 | up = &ip22zilog_port_table[i]; |
1da177e4 LT |
1189 | |
1190 | uart_remove_one_port(&ip22zilog_reg, &up->port); | |
1191 | } | |
1192 | ||
6257b3bd AL |
1193 | /* Free IO mem */ |
1194 | up = &ip22zilog_port_table[0]; | |
1195 | for (i = 0; i < NUM_IP22ZILOG; i++) { | |
1196 | if (up[(i * 2) + 0].port.mapbase) { | |
1197 | iounmap((void*)up[(i * 2) + 0].port.mapbase); | |
1198 | up[(i * 2) + 0].port.mapbase = 0; | |
1199 | } | |
1200 | if (up[(i * 2) + 1].port.mapbase) { | |
1201 | iounmap((void*)up[(i * 2) + 1].port.mapbase); | |
1202 | up[(i * 2) + 1].port.mapbase = 0; | |
1203 | } | |
1204 | } | |
1205 | ||
1da177e4 LT |
1206 | uart_unregister_driver(&ip22zilog_reg); |
1207 | } | |
1208 | ||
1209 | module_init(ip22zilog_init); | |
1210 | module_exit(ip22zilog_exit); | |
1211 | ||
1212 | /* David wrote it but I'm to blame for the bugs ... */ | |
1213 | MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>"); | |
1214 | MODULE_DESCRIPTION("SGI Zilog serial port driver"); | |
1215 | MODULE_LICENSE("GPL"); |