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f6544418 AS |
1 | /* |
2 | * Maxim (Dallas) MAX3107/8 serial driver | |
3 | * | |
4 | * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> | |
5 | * | |
6 | * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> | |
7 | * Based on max3110.c, by Feng Tang <feng.tang@intel.com> | |
8 | * Based on max3107.c, by Aavamobile | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | */ | |
15 | ||
16 | /* TODO: MAX3109 support (Dual) */ | |
17 | /* TODO: MAX14830 support (Quad) */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/serial_core.h> | |
22 | #include <linux/serial.h> | |
23 | #include <linux/tty.h> | |
24 | #include <linux/tty_flip.h> | |
25 | #include <linux/regmap.h> | |
26 | #include <linux/gpio.h> | |
27 | #include <linux/spi/spi.h> | |
28 | #include <linux/platform_data/max310x.h> | |
29 | ||
30 | #define MAX310X_MAJOR 204 | |
31 | #define MAX310X_MINOR 209 | |
32 | ||
33 | /* MAX310X register definitions */ | |
34 | #define MAX310X_RHR_REG (0x00) /* RX FIFO */ | |
35 | #define MAX310X_THR_REG (0x00) /* TX FIFO */ | |
36 | #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ | |
37 | #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ | |
38 | #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ | |
39 | #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ | |
40 | #define MAX310X_SPCHR_IRQEN_REG (0x05) /* Special char IRQ enable */ | |
41 | #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ | |
42 | #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ | |
43 | #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ | |
44 | #define MAX310X_MODE1_REG (0x09) /* MODE1 */ | |
45 | #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ | |
46 | #define MAX310X_LCR_REG (0x0b) /* LCR */ | |
47 | #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ | |
48 | #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ | |
49 | #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ | |
50 | #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ | |
51 | #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ | |
52 | #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ | |
53 | #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ | |
54 | #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ | |
55 | #define MAX310X_XON1_REG (0x14) /* XON1 character */ | |
56 | #define MAX310X_XON2_REG (0x15) /* XON2 character */ | |
57 | #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ | |
58 | #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ | |
59 | #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ | |
60 | #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ | |
61 | #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ | |
62 | #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ | |
63 | #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ | |
64 | #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ | |
65 | #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ | |
66 | /* Only present in MAX3107 */ | |
67 | #define MAX3107_REVID_REG (0x1f) /* Revision identification */ | |
68 | ||
69 | /* IRQ register bits */ | |
70 | #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ | |
71 | #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ | |
72 | #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ | |
73 | #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ | |
74 | #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ | |
75 | #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ | |
76 | #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ | |
77 | #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ | |
78 | ||
79 | /* LSR register bits */ | |
80 | #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ | |
81 | #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ | |
82 | #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ | |
83 | #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ | |
84 | #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ | |
85 | #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ | |
86 | #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ | |
87 | ||
88 | /* Special character register bits */ | |
89 | #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ | |
90 | #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ | |
91 | #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ | |
92 | #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ | |
93 | #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ | |
94 | #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ | |
95 | ||
96 | /* Status register bits */ | |
97 | #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ | |
98 | #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ | |
99 | #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ | |
100 | #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ | |
101 | #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ | |
102 | #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ | |
103 | ||
104 | /* MODE1 register bits */ | |
105 | #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ | |
106 | #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ | |
107 | #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ | |
108 | #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ | |
109 | #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ | |
110 | #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ | |
111 | #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ | |
112 | #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ | |
113 | ||
114 | /* MODE2 register bits */ | |
115 | #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ | |
116 | #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ | |
117 | #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ | |
118 | #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ | |
119 | #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ | |
120 | #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ | |
121 | #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ | |
122 | #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ | |
123 | ||
124 | /* LCR register bits */ | |
125 | #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ | |
126 | #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 | |
127 | * | |
128 | * Word length bits table: | |
129 | * 00 -> 5 bit words | |
130 | * 01 -> 6 bit words | |
131 | * 10 -> 7 bit words | |
132 | * 11 -> 8 bit words | |
133 | */ | |
134 | #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit | |
135 | * | |
136 | * STOP length bit table: | |
137 | * 0 -> 1 stop bit | |
138 | * 1 -> 1-1.5 stop bits if | |
139 | * word length is 5, | |
140 | * 2 stop bits otherwise | |
141 | */ | |
142 | #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ | |
143 | #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ | |
144 | #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ | |
145 | #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ | |
146 | #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ | |
147 | #define MAX310X_LCR_WORD_LEN_5 (0x00) | |
148 | #define MAX310X_LCR_WORD_LEN_6 (0x01) | |
149 | #define MAX310X_LCR_WORD_LEN_7 (0x02) | |
150 | #define MAX310X_LCR_WORD_LEN_8 (0x03) | |
151 | ||
152 | /* IRDA register bits */ | |
153 | #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ | |
154 | #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ | |
155 | #define MAX310X_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */ | |
156 | #define MAX310X_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */ | |
157 | #define MAX310X_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */ | |
158 | #define MAX310X_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */ | |
159 | ||
160 | /* Flow control trigger level register masks */ | |
161 | #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ | |
162 | #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ | |
163 | #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) | |
164 | #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) | |
165 | ||
166 | /* FIFO interrupt trigger level register masks */ | |
167 | #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ | |
168 | #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ | |
169 | #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) | |
170 | #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) | |
171 | ||
172 | /* Flow control register bits */ | |
173 | #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ | |
174 | #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ | |
175 | #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs | |
176 | * are used in conjunction with | |
177 | * XOFF2 for definition of | |
178 | * special character */ | |
179 | #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ | |
180 | #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ | |
181 | #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 | |
182 | * | |
183 | * SWFLOW bits 1 & 0 table: | |
184 | * 00 -> no transmitter flow | |
185 | * control | |
186 | * 01 -> receiver compares | |
187 | * XON2 and XOFF2 | |
188 | * and controls | |
189 | * transmitter | |
190 | * 10 -> receiver compares | |
191 | * XON1 and XOFF1 | |
192 | * and controls | |
193 | * transmitter | |
194 | * 11 -> receiver compares | |
195 | * XON1, XON2, XOFF1 and | |
196 | * XOFF2 and controls | |
197 | * transmitter | |
198 | */ | |
199 | #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ | |
200 | #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 | |
201 | * | |
202 | * SWFLOW bits 3 & 2 table: | |
203 | * 00 -> no received flow | |
204 | * control | |
205 | * 01 -> transmitter generates | |
206 | * XON2 and XOFF2 | |
207 | * 10 -> transmitter generates | |
208 | * XON1 and XOFF1 | |
209 | * 11 -> transmitter generates | |
210 | * XON1, XON2, XOFF1 and | |
211 | * XOFF2 | |
212 | */ | |
213 | ||
214 | /* GPIO configuration register bits */ | |
215 | #define MAX310X_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */ | |
216 | #define MAX310X_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */ | |
217 | #define MAX310X_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */ | |
218 | #define MAX310X_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */ | |
219 | #define MAX310X_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */ | |
220 | #define MAX310X_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */ | |
221 | #define MAX310X_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */ | |
222 | #define MAX310X_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */ | |
223 | ||
224 | /* GPIO DATA register bits */ | |
225 | #define MAX310X_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */ | |
226 | #define MAX310X_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */ | |
227 | #define MAX310X_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */ | |
228 | #define MAX310X_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */ | |
229 | #define MAX310X_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */ | |
230 | #define MAX310X_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */ | |
231 | #define MAX310X_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */ | |
232 | #define MAX310X_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */ | |
233 | ||
234 | /* PLL configuration register masks */ | |
235 | #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ | |
236 | #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ | |
237 | ||
238 | /* Baud rate generator configuration register bits */ | |
239 | #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ | |
240 | #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ | |
241 | ||
242 | /* Clock source register bits */ | |
243 | #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ | |
244 | #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ | |
245 | #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ | |
246 | #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ | |
247 | #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ | |
248 | ||
249 | /* Misc definitions */ | |
250 | #define MAX310X_FIFO_SIZE (128) | |
251 | ||
252 | /* MAX3107 specific */ | |
253 | #define MAX3107_REV_ID (0xa0) | |
254 | #define MAX3107_REV_MASK (0xfe) | |
255 | ||
256 | /* IRQ status bits definitions */ | |
257 | #define MAX310X_IRQ_TX (MAX310X_IRQ_TXFIFO_BIT | \ | |
258 | MAX310X_IRQ_TXEMPTY_BIT) | |
259 | #define MAX310X_IRQ_RX (MAX310X_IRQ_RXFIFO_BIT | \ | |
260 | MAX310X_IRQ_RXEMPTY_BIT) | |
261 | ||
262 | /* Supported chip types */ | |
263 | enum { | |
264 | MAX310X_TYPE_MAX3107 = 3107, | |
265 | MAX310X_TYPE_MAX3108 = 3108, | |
266 | }; | |
267 | ||
268 | struct max310x_port { | |
269 | struct uart_driver uart; | |
270 | struct uart_port port; | |
271 | ||
272 | const char *name; | |
273 | int uartclk; | |
274 | ||
275 | unsigned int nr_gpio; | |
276 | #ifdef CONFIG_GPIOLIB | |
277 | struct gpio_chip gpio; | |
278 | #endif | |
279 | ||
280 | struct regmap *regmap; | |
281 | struct regmap_config regcfg; | |
282 | ||
283 | struct workqueue_struct *wq; | |
284 | struct work_struct tx_work; | |
285 | ||
286 | struct mutex max310x_mutex; | |
287 | ||
288 | struct max310x_pdata *pdata; | |
289 | }; | |
290 | ||
291 | static bool max3107_8_reg_writeable(struct device *dev, unsigned int reg) | |
292 | { | |
293 | switch (reg) { | |
294 | case MAX310X_IRQSTS_REG: | |
295 | case MAX310X_LSR_IRQSTS_REG: | |
296 | case MAX310X_SPCHR_IRQSTS_REG: | |
297 | case MAX310X_STS_IRQSTS_REG: | |
298 | case MAX310X_TXFIFOLVL_REG: | |
299 | case MAX310X_RXFIFOLVL_REG: | |
300 | case MAX3107_REVID_REG: /* Only available on MAX3107 */ | |
301 | return false; | |
302 | default: | |
303 | break; | |
304 | } | |
305 | ||
306 | return true; | |
307 | } | |
308 | ||
309 | static bool max310x_reg_volatile(struct device *dev, unsigned int reg) | |
310 | { | |
311 | switch (reg) { | |
312 | case MAX310X_RHR_REG: | |
313 | case MAX310X_IRQSTS_REG: | |
314 | case MAX310X_LSR_IRQSTS_REG: | |
315 | case MAX310X_SPCHR_IRQSTS_REG: | |
316 | case MAX310X_STS_IRQSTS_REG: | |
317 | case MAX310X_TXFIFOLVL_REG: | |
318 | case MAX310X_RXFIFOLVL_REG: | |
319 | case MAX310X_GPIODATA_REG: | |
320 | return true; | |
321 | default: | |
322 | break; | |
323 | } | |
324 | ||
325 | return false; | |
326 | } | |
327 | ||
328 | static bool max310x_reg_precious(struct device *dev, unsigned int reg) | |
329 | { | |
330 | switch (reg) { | |
331 | case MAX310X_RHR_REG: | |
332 | case MAX310X_IRQSTS_REG: | |
333 | case MAX310X_SPCHR_IRQSTS_REG: | |
334 | case MAX310X_STS_IRQSTS_REG: | |
335 | return true; | |
336 | default: | |
337 | break; | |
338 | } | |
339 | ||
340 | return false; | |
341 | } | |
342 | ||
343 | static void max310x_set_baud(struct max310x_port *s, int baud) | |
344 | { | |
345 | unsigned int mode = 0, div = s->uartclk / baud; | |
346 | ||
347 | if (!(div / 16)) { | |
348 | /* Mode x2 */ | |
349 | mode = MAX310X_BRGCFG_2XMODE_BIT; | |
350 | div = (s->uartclk * 2) / baud; | |
351 | } | |
352 | ||
353 | if (!(div / 16)) { | |
354 | /* Mode x4 */ | |
355 | mode = MAX310X_BRGCFG_4XMODE_BIT; | |
356 | div = (s->uartclk * 4) / baud; | |
357 | } | |
358 | ||
359 | regmap_write(s->regmap, MAX310X_BRGDIVMSB_REG, | |
360 | ((div / 16) >> 8) & 0xff); | |
361 | regmap_write(s->regmap, MAX310X_BRGDIVLSB_REG, (div / 16) & 0xff); | |
362 | regmap_write(s->regmap, MAX310X_BRGCFG_REG, (div % 16) | mode); | |
363 | } | |
364 | ||
365 | static void max310x_wait_pll(struct max310x_port *s) | |
366 | { | |
367 | int tryes = 1000; | |
368 | ||
369 | /* Wait for PLL only if crystal is used */ | |
370 | if (!(s->pdata->driver_flags & MAX310X_EXT_CLK)) { | |
371 | unsigned int sts = 0; | |
372 | ||
373 | while (tryes--) { | |
374 | regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &sts); | |
375 | if (sts & MAX310X_STS_CLKREADY_BIT) | |
376 | break; | |
377 | } | |
378 | } | |
379 | } | |
380 | ||
381 | static int __devinit max310x_update_best_err(unsigned long f, long *besterr) | |
382 | { | |
383 | /* Use baudrate 115200 for calculate error */ | |
384 | long err = f % (115200 * 16); | |
385 | ||
386 | if ((*besterr < 0) || (*besterr > err)) { | |
387 | *besterr = err; | |
388 | return 0; | |
389 | } | |
390 | ||
391 | return 1; | |
392 | } | |
393 | ||
394 | static int __devinit max310x_set_ref_clk(struct max310x_port *s) | |
395 | { | |
396 | unsigned int div, clksrc, pllcfg = 0; | |
397 | long besterr = -1; | |
398 | unsigned long fdiv, fmul, bestfreq = s->pdata->frequency; | |
399 | ||
400 | /* First, update error without PLL */ | |
401 | max310x_update_best_err(s->pdata->frequency, &besterr); | |
402 | ||
403 | /* Try all possible PLL dividers */ | |
404 | for (div = 1; (div <= 63) && besterr; div++) { | |
405 | fdiv = DIV_ROUND_CLOSEST(s->pdata->frequency, div); | |
406 | ||
407 | /* Try multiplier 6 */ | |
408 | fmul = fdiv * 6; | |
409 | if ((fdiv >= 500000) && (fdiv <= 800000)) | |
410 | if (!max310x_update_best_err(fmul, &besterr)) { | |
411 | pllcfg = (0 << 6) | div; | |
412 | bestfreq = fmul; | |
413 | } | |
414 | /* Try multiplier 48 */ | |
415 | fmul = fdiv * 48; | |
416 | if ((fdiv >= 850000) && (fdiv <= 1200000)) | |
417 | if (!max310x_update_best_err(fmul, &besterr)) { | |
418 | pllcfg = (1 << 6) | div; | |
419 | bestfreq = fmul; | |
420 | } | |
421 | /* Try multiplier 96 */ | |
422 | fmul = fdiv * 96; | |
423 | if ((fdiv >= 425000) && (fdiv <= 1000000)) | |
424 | if (!max310x_update_best_err(fmul, &besterr)) { | |
425 | pllcfg = (2 << 6) | div; | |
426 | bestfreq = fmul; | |
427 | } | |
428 | /* Try multiplier 144 */ | |
429 | fmul = fdiv * 144; | |
430 | if ((fdiv >= 390000) && (fdiv <= 667000)) | |
431 | if (!max310x_update_best_err(fmul, &besterr)) { | |
432 | pllcfg = (3 << 6) | div; | |
433 | bestfreq = fmul; | |
434 | } | |
435 | } | |
436 | ||
437 | /* Configure clock source */ | |
438 | if (s->pdata->driver_flags & MAX310X_EXT_CLK) | |
439 | clksrc = MAX310X_CLKSRC_EXTCLK_BIT; | |
440 | else | |
441 | clksrc = MAX310X_CLKSRC_CRYST_BIT; | |
442 | ||
443 | /* Configure PLL */ | |
444 | if (pllcfg) { | |
445 | clksrc |= MAX310X_CLKSRC_PLL_BIT; | |
446 | regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); | |
447 | } else | |
448 | clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; | |
449 | ||
450 | regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); | |
451 | ||
452 | if (pllcfg) | |
453 | max310x_wait_pll(s); | |
454 | ||
455 | dev_dbg(s->port.dev, "Reference clock set to %lu Hz\n", bestfreq); | |
456 | ||
457 | return (int)bestfreq; | |
458 | } | |
459 | ||
460 | static void max310x_handle_rx(struct max310x_port *s, unsigned int rxlen) | |
461 | { | |
462 | unsigned int sts = 0, ch = 0, flag; | |
463 | struct tty_struct *tty = tty_port_tty_get(&s->port.state->port); | |
464 | ||
465 | if (!tty) | |
466 | return; | |
467 | ||
468 | if (unlikely(rxlen >= MAX310X_FIFO_SIZE)) { | |
469 | dev_warn(s->port.dev, "Possible RX FIFO overrun %d\n", rxlen); | |
470 | /* Ensure sanity of RX level */ | |
471 | rxlen = MAX310X_FIFO_SIZE; | |
472 | } | |
473 | ||
474 | dev_dbg(s->port.dev, "RX Len = %u\n", rxlen); | |
475 | ||
476 | while (rxlen--) { | |
477 | regmap_read(s->regmap, MAX310X_RHR_REG, &ch); | |
478 | regmap_read(s->regmap, MAX310X_LSR_IRQSTS_REG, &sts); | |
479 | ||
480 | sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | | |
481 | MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; | |
482 | ||
483 | s->port.icount.rx++; | |
484 | flag = TTY_NORMAL; | |
485 | ||
486 | if (unlikely(sts)) { | |
487 | if (sts & MAX310X_LSR_RXBRK_BIT) { | |
488 | s->port.icount.brk++; | |
489 | if (uart_handle_break(&s->port)) | |
490 | continue; | |
491 | } else if (sts & MAX310X_LSR_RXPAR_BIT) | |
492 | s->port.icount.parity++; | |
493 | else if (sts & MAX310X_LSR_FRERR_BIT) | |
494 | s->port.icount.frame++; | |
495 | else if (sts & MAX310X_LSR_RXOVR_BIT) | |
496 | s->port.icount.overrun++; | |
497 | ||
498 | sts &= s->port.read_status_mask; | |
499 | if (sts & MAX310X_LSR_RXBRK_BIT) | |
500 | flag = TTY_BREAK; | |
501 | else if (sts & MAX310X_LSR_RXPAR_BIT) | |
502 | flag = TTY_PARITY; | |
503 | else if (sts & MAX310X_LSR_FRERR_BIT) | |
504 | flag = TTY_FRAME; | |
505 | else if (sts & MAX310X_LSR_RXOVR_BIT) | |
506 | flag = TTY_OVERRUN; | |
507 | } | |
508 | ||
509 | if (uart_handle_sysrq_char(s->port, ch)) | |
510 | continue; | |
511 | ||
512 | if (sts & s->port.ignore_status_mask) | |
513 | continue; | |
514 | ||
515 | uart_insert_char(&s->port, sts, MAX310X_LSR_RXOVR_BIT, | |
516 | ch, flag); | |
517 | } | |
518 | ||
519 | tty_flip_buffer_push(tty); | |
520 | ||
521 | tty_kref_put(tty); | |
522 | } | |
523 | ||
524 | static void max310x_handle_tx(struct max310x_port *s) | |
525 | { | |
526 | struct circ_buf *xmit = &s->port.state->xmit; | |
527 | unsigned int txlen = 0, to_send; | |
528 | ||
529 | if (unlikely(s->port.x_char)) { | |
530 | regmap_write(s->regmap, MAX310X_THR_REG, s->port.x_char); | |
531 | s->port.icount.tx++; | |
532 | s->port.x_char = 0; | |
533 | return; | |
534 | } | |
535 | ||
536 | if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port)) | |
537 | return; | |
538 | ||
539 | /* Get length of data pending in circular buffer */ | |
540 | to_send = uart_circ_chars_pending(xmit); | |
541 | if (likely(to_send)) { | |
542 | /* Limit to size of TX FIFO */ | |
543 | regmap_read(s->regmap, MAX310X_TXFIFOLVL_REG, &txlen); | |
544 | txlen = MAX310X_FIFO_SIZE - txlen; | |
545 | to_send = (to_send > txlen) ? txlen : to_send; | |
546 | ||
547 | dev_dbg(s->port.dev, "TX Len = %u\n", to_send); | |
548 | ||
549 | /* Add data to send */ | |
550 | s->port.icount.tx += to_send; | |
551 | while (to_send--) { | |
552 | regmap_write(s->regmap, MAX310X_THR_REG, | |
553 | xmit->buf[xmit->tail]); | |
554 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
555 | }; | |
556 | } | |
557 | ||
558 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
559 | uart_write_wakeup(&s->port); | |
560 | } | |
561 | ||
562 | static irqreturn_t max310x_ist(int irq, void *dev_id) | |
563 | { | |
564 | struct max310x_port *s = (struct max310x_port *)dev_id; | |
565 | unsigned int ists = 0, lsr = 0, rxlen = 0; | |
566 | ||
567 | mutex_lock(&s->max310x_mutex); | |
568 | ||
569 | for (;;) { | |
570 | /* Read IRQ status & RX FIFO level */ | |
571 | regmap_read(s->regmap, MAX310X_IRQSTS_REG, &ists); | |
572 | regmap_read(s->regmap, MAX310X_LSR_IRQSTS_REG, &lsr); | |
573 | regmap_read(s->regmap, MAX310X_RXFIFOLVL_REG, &rxlen); | |
574 | if (!ists && !(lsr & MAX310X_LSR_RXTO_BIT) && !rxlen) | |
575 | break; | |
576 | ||
577 | dev_dbg(s->port.dev, "IRQ status: 0x%02x\n", ists); | |
578 | ||
579 | if (rxlen) | |
580 | max310x_handle_rx(s, rxlen); | |
581 | if (ists & MAX310X_IRQ_TX) | |
582 | max310x_handle_tx(s); | |
583 | if (ists & MAX310X_IRQ_CTS_BIT) | |
584 | uart_handle_cts_change(&s->port, | |
585 | !!(lsr & MAX310X_LSR_CTS_BIT)); | |
586 | } | |
587 | ||
588 | mutex_unlock(&s->max310x_mutex); | |
589 | ||
590 | return IRQ_HANDLED; | |
591 | } | |
592 | ||
593 | static void max310x_wq_proc(struct work_struct *ws) | |
594 | { | |
595 | struct max310x_port *s = container_of(ws, struct max310x_port, tx_work); | |
596 | ||
597 | mutex_lock(&s->max310x_mutex); | |
598 | max310x_handle_tx(s); | |
599 | mutex_unlock(&s->max310x_mutex); | |
600 | } | |
601 | ||
602 | static void max310x_start_tx(struct uart_port *port) | |
603 | { | |
604 | struct max310x_port *s = container_of(port, struct max310x_port, port); | |
605 | ||
606 | queue_work(s->wq, &s->tx_work); | |
607 | } | |
608 | ||
609 | static void max310x_stop_tx(struct uart_port *port) | |
610 | { | |
611 | /* Do nothing */ | |
612 | } | |
613 | ||
614 | static void max310x_stop_rx(struct uart_port *port) | |
615 | { | |
616 | /* Do nothing */ | |
617 | } | |
618 | ||
619 | static unsigned int max310x_tx_empty(struct uart_port *port) | |
620 | { | |
621 | unsigned int val = 0; | |
622 | struct max310x_port *s = container_of(port, struct max310x_port, port); | |
623 | ||
624 | mutex_lock(&s->max310x_mutex); | |
625 | regmap_read(s->regmap, MAX310X_TXFIFOLVL_REG, &val); | |
626 | mutex_unlock(&s->max310x_mutex); | |
627 | ||
628 | return val ? 0 : TIOCSER_TEMT; | |
629 | } | |
630 | ||
631 | static void max310x_enable_ms(struct uart_port *port) | |
632 | { | |
633 | /* Modem status not supported */ | |
634 | } | |
635 | ||
636 | static unsigned int max310x_get_mctrl(struct uart_port *port) | |
637 | { | |
638 | /* DCD and DSR are not wired and CTS/RTS is handled automatically | |
639 | * so just indicate DSR and CAR asserted | |
640 | */ | |
641 | return TIOCM_DSR | TIOCM_CAR; | |
642 | } | |
643 | ||
644 | static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
645 | { | |
646 | /* DCD and DSR are not wired and CTS/RTS is hadnled automatically | |
647 | * so do nothing | |
648 | */ | |
649 | } | |
650 | ||
651 | static void max310x_break_ctl(struct uart_port *port, int break_state) | |
652 | { | |
653 | struct max310x_port *s = container_of(port, struct max310x_port, port); | |
654 | ||
655 | mutex_lock(&s->max310x_mutex); | |
656 | regmap_update_bits(s->regmap, MAX310X_LCR_REG, | |
657 | MAX310X_LCR_TXBREAK_BIT, | |
658 | break_state ? MAX310X_LCR_TXBREAK_BIT : 0); | |
659 | mutex_unlock(&s->max310x_mutex); | |
660 | } | |
661 | ||
662 | static void max310x_set_termios(struct uart_port *port, | |
663 | struct ktermios *termios, | |
664 | struct ktermios *old) | |
665 | { | |
666 | struct max310x_port *s = container_of(port, struct max310x_port, port); | |
667 | unsigned int lcr, flow = 0; | |
668 | int baud; | |
669 | ||
670 | mutex_lock(&s->max310x_mutex); | |
671 | ||
672 | /* Mask termios capabilities we don't support */ | |
673 | termios->c_cflag &= ~CMSPAR; | |
674 | termios->c_iflag &= ~IXANY; | |
675 | ||
676 | /* Word size */ | |
677 | switch (termios->c_cflag & CSIZE) { | |
678 | case CS5: | |
679 | lcr = MAX310X_LCR_WORD_LEN_5; | |
680 | break; | |
681 | case CS6: | |
682 | lcr = MAX310X_LCR_WORD_LEN_6; | |
683 | break; | |
684 | case CS7: | |
685 | lcr = MAX310X_LCR_WORD_LEN_7; | |
686 | break; | |
687 | case CS8: | |
688 | default: | |
689 | lcr = MAX310X_LCR_WORD_LEN_8; | |
690 | break; | |
691 | } | |
692 | ||
693 | /* Parity */ | |
694 | if (termios->c_cflag & PARENB) { | |
695 | lcr |= MAX310X_LCR_PARITY_BIT; | |
696 | if (!(termios->c_cflag & PARODD)) | |
697 | lcr |= MAX310X_LCR_EVENPARITY_BIT; | |
698 | } | |
699 | ||
700 | /* Stop bits */ | |
701 | if (termios->c_cflag & CSTOPB) | |
702 | lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ | |
703 | ||
704 | /* Update LCR register */ | |
705 | regmap_write(s->regmap, MAX310X_LCR_REG, lcr); | |
706 | ||
707 | /* Set read status mask */ | |
708 | port->read_status_mask = MAX310X_LSR_RXOVR_BIT; | |
709 | if (termios->c_iflag & INPCK) | |
710 | port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | | |
711 | MAX310X_LSR_FRERR_BIT; | |
712 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
713 | port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; | |
714 | ||
715 | /* Set status ignore mask */ | |
716 | port->ignore_status_mask = 0; | |
717 | if (termios->c_iflag & IGNBRK) | |
718 | port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; | |
719 | if (!(termios->c_cflag & CREAD)) | |
720 | port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | | |
721 | MAX310X_LSR_RXOVR_BIT | | |
722 | MAX310X_LSR_FRERR_BIT | | |
723 | MAX310X_LSR_RXBRK_BIT; | |
724 | ||
725 | /* Configure flow control */ | |
726 | regmap_write(s->regmap, MAX310X_XON1_REG, termios->c_cc[VSTART]); | |
727 | regmap_write(s->regmap, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); | |
728 | if (termios->c_cflag & CRTSCTS) | |
729 | flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | | |
730 | MAX310X_FLOWCTRL_AUTORTS_BIT; | |
731 | if (termios->c_iflag & IXON) | |
732 | flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | | |
733 | MAX310X_FLOWCTRL_SWFLOWEN_BIT; | |
734 | if (termios->c_iflag & IXOFF) | |
735 | flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | | |
736 | MAX310X_FLOWCTRL_SWFLOWEN_BIT; | |
737 | regmap_write(s->regmap, MAX310X_FLOWCTRL_REG, flow); | |
738 | ||
739 | /* Get baud rate generator configuration */ | |
740 | baud = uart_get_baud_rate(port, termios, old, | |
741 | port->uartclk / 16 / 0xffff, | |
742 | port->uartclk / 4); | |
743 | ||
744 | /* Setup baudrate generator */ | |
745 | max310x_set_baud(s, baud); | |
746 | ||
747 | /* Update timeout according to new baud rate */ | |
748 | uart_update_timeout(port, termios->c_cflag, baud); | |
749 | ||
750 | mutex_unlock(&s->max310x_mutex); | |
751 | } | |
752 | ||
753 | static int max310x_startup(struct uart_port *port) | |
754 | { | |
755 | unsigned int val, line = port->line; | |
756 | struct max310x_port *s = container_of(port, struct max310x_port, port); | |
757 | ||
758 | if (s->pdata->suspend) | |
759 | s->pdata->suspend(0); | |
760 | ||
761 | mutex_lock(&s->max310x_mutex); | |
762 | ||
763 | /* Configure baud rate, 9600 as default */ | |
764 | max310x_set_baud(s, 9600); | |
765 | ||
766 | /* Configure LCR register, 8N1 mode by default */ | |
767 | val = MAX310X_LCR_WORD_LEN_8; | |
768 | regmap_write(s->regmap, MAX310X_LCR_REG, val); | |
769 | ||
770 | /* Configure MODE1 register */ | |
771 | regmap_update_bits(s->regmap, MAX310X_MODE1_REG, | |
772 | MAX310X_MODE1_TRNSCVCTRL_BIT, | |
773 | (s->pdata->uart_flags[line] & MAX310X_AUTO_DIR_CTRL) | |
774 | ? MAX310X_MODE1_TRNSCVCTRL_BIT : 0); | |
775 | ||
776 | /* Configure MODE2 register */ | |
777 | val = MAX310X_MODE2_RXEMPTINV_BIT; | |
778 | if (s->pdata->uart_flags[line] & MAX310X_LOOPBACK) | |
779 | val |= MAX310X_MODE2_LOOPBACK_BIT; | |
780 | if (s->pdata->uart_flags[line] & MAX310X_ECHO_SUPRESS) | |
781 | val |= MAX310X_MODE2_ECHOSUPR_BIT; | |
782 | ||
783 | /* Reset FIFOs */ | |
784 | val |= MAX310X_MODE2_FIFORST_BIT; | |
785 | regmap_write(s->regmap, MAX310X_MODE2_REG, val); | |
786 | ||
787 | /* Configure FIFO trigger level register */ | |
788 | /* RX FIFO trigger for 16 words, TX FIFO trigger for 64 words */ | |
789 | val = MAX310X_FIFOTRIGLVL_RX(16) | MAX310X_FIFOTRIGLVL_TX(64); | |
790 | regmap_write(s->regmap, MAX310X_FIFOTRIGLVL_REG, val); | |
791 | ||
792 | /* Configure flow control levels */ | |
793 | /* Flow control halt level 96, resume level 48 */ | |
794 | val = MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96); | |
795 | regmap_write(s->regmap, MAX310X_FLOWLVL_REG, val); | |
796 | ||
797 | /* Clear timeout register */ | |
798 | regmap_write(s->regmap, MAX310X_RXTO_REG, 0); | |
799 | ||
800 | /* Configure LSR interrupt enable register */ | |
801 | /* Enable RX timeout interrupt */ | |
802 | val = MAX310X_LSR_RXTO_BIT; | |
803 | regmap_write(s->regmap, MAX310X_LSR_IRQEN_REG, val); | |
804 | ||
805 | /* Clear FIFO reset */ | |
806 | regmap_update_bits(s->regmap, MAX310X_MODE2_REG, | |
807 | MAX310X_MODE2_FIFORST_BIT, 0); | |
808 | ||
809 | /* Clear IRQ status register by reading it */ | |
810 | regmap_read(s->regmap, MAX310X_IRQSTS_REG, &val); | |
811 | ||
812 | /* Configure interrupt enable register */ | |
813 | /* Enable CTS change interrupt */ | |
814 | val = MAX310X_IRQ_CTS_BIT; | |
815 | /* Enable RX, TX interrupts */ | |
816 | val |= MAX310X_IRQ_RX | MAX310X_IRQ_TX; | |
817 | regmap_write(s->regmap, MAX310X_IRQEN_REG, val); | |
818 | ||
819 | mutex_unlock(&s->max310x_mutex); | |
820 | ||
821 | return 0; | |
822 | } | |
823 | ||
824 | static void max310x_shutdown(struct uart_port *port) | |
825 | { | |
826 | struct max310x_port *s = container_of(port, struct max310x_port, port); | |
827 | ||
828 | /* Disable all interrupts */ | |
829 | mutex_lock(&s->max310x_mutex); | |
830 | regmap_write(s->regmap, MAX310X_IRQEN_REG, 0); | |
831 | mutex_unlock(&s->max310x_mutex); | |
832 | ||
833 | if (s->pdata->suspend) | |
834 | s->pdata->suspend(1); | |
835 | } | |
836 | ||
837 | static const char *max310x_type(struct uart_port *port) | |
838 | { | |
839 | struct max310x_port *s = container_of(port, struct max310x_port, port); | |
840 | ||
841 | return (port->type == PORT_MAX310X) ? s->name : NULL; | |
842 | } | |
843 | ||
844 | static int max310x_request_port(struct uart_port *port) | |
845 | { | |
846 | /* Do nothing */ | |
847 | return 0; | |
848 | } | |
849 | ||
850 | static void max310x_release_port(struct uart_port *port) | |
851 | { | |
852 | /* Do nothing */ | |
853 | } | |
854 | ||
855 | static void max310x_config_port(struct uart_port *port, int flags) | |
856 | { | |
857 | if (flags & UART_CONFIG_TYPE) | |
858 | port->type = PORT_MAX310X; | |
859 | } | |
860 | ||
861 | static int max310x_verify_port(struct uart_port *port, struct serial_struct *ser) | |
862 | { | |
863 | if ((ser->type == PORT_UNKNOWN) || (ser->type == PORT_MAX310X)) | |
864 | return 0; | |
865 | if (ser->irq == port->irq) | |
866 | return 0; | |
867 | ||
868 | return -EINVAL; | |
869 | } | |
870 | ||
871 | static struct uart_ops max310x_ops = { | |
872 | .tx_empty = max310x_tx_empty, | |
873 | .set_mctrl = max310x_set_mctrl, | |
874 | .get_mctrl = max310x_get_mctrl, | |
875 | .stop_tx = max310x_stop_tx, | |
876 | .start_tx = max310x_start_tx, | |
877 | .stop_rx = max310x_stop_rx, | |
878 | .enable_ms = max310x_enable_ms, | |
879 | .break_ctl = max310x_break_ctl, | |
880 | .startup = max310x_startup, | |
881 | .shutdown = max310x_shutdown, | |
882 | .set_termios = max310x_set_termios, | |
883 | .type = max310x_type, | |
884 | .request_port = max310x_request_port, | |
885 | .release_port = max310x_release_port, | |
886 | .config_port = max310x_config_port, | |
887 | .verify_port = max310x_verify_port, | |
888 | }; | |
889 | ||
890 | static int max310x_suspend(struct spi_device *spi, pm_message_t state) | |
891 | { | |
892 | int ret; | |
893 | struct max310x_port *s = dev_get_drvdata(&spi->dev); | |
894 | ||
895 | dev_dbg(&spi->dev, "Suspend\n"); | |
896 | ||
897 | ret = uart_suspend_port(&s->uart, &s->port); | |
898 | ||
899 | mutex_lock(&s->max310x_mutex); | |
900 | ||
901 | /* Enable sleep mode */ | |
902 | regmap_update_bits(s->regmap, MAX310X_MODE1_REG, | |
903 | MAX310X_MODE1_FORCESLEEP_BIT, | |
904 | MAX310X_MODE1_FORCESLEEP_BIT); | |
905 | ||
906 | mutex_unlock(&s->max310x_mutex); | |
907 | ||
908 | if (s->pdata->suspend) | |
909 | s->pdata->suspend(1); | |
910 | ||
911 | return ret; | |
912 | } | |
913 | ||
914 | static int max310x_resume(struct spi_device *spi) | |
915 | { | |
916 | struct max310x_port *s = dev_get_drvdata(&spi->dev); | |
917 | ||
918 | dev_dbg(&spi->dev, "Resume\n"); | |
919 | ||
920 | if (s->pdata->suspend) | |
921 | s->pdata->suspend(0); | |
922 | ||
923 | mutex_lock(&s->max310x_mutex); | |
924 | ||
925 | /* Disable sleep mode */ | |
926 | regmap_update_bits(s->regmap, MAX310X_MODE1_REG, | |
927 | MAX310X_MODE1_FORCESLEEP_BIT, | |
928 | 0); | |
929 | ||
930 | max310x_wait_pll(s); | |
931 | ||
932 | mutex_unlock(&s->max310x_mutex); | |
933 | ||
934 | return uart_resume_port(&s->uart, &s->port); | |
935 | } | |
936 | ||
937 | #ifdef CONFIG_GPIOLIB | |
938 | static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) | |
939 | { | |
940 | unsigned int val = 0; | |
941 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | |
942 | ||
943 | mutex_lock(&s->max310x_mutex); | |
944 | regmap_read(s->regmap, MAX310X_GPIODATA_REG, &val); | |
945 | mutex_unlock(&s->max310x_mutex); | |
946 | ||
947 | return !!((val >> 4) & (1 << offset)); | |
948 | } | |
949 | ||
950 | static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
951 | { | |
952 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | |
953 | ||
954 | mutex_lock(&s->max310x_mutex); | |
955 | regmap_update_bits(s->regmap, MAX310X_GPIODATA_REG, 1 << offset, value ? | |
956 | 1 << offset : 0); | |
957 | mutex_unlock(&s->max310x_mutex); | |
958 | } | |
959 | ||
960 | static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
961 | { | |
962 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | |
963 | ||
964 | mutex_lock(&s->max310x_mutex); | |
965 | ||
966 | regmap_update_bits(s->regmap, MAX310X_GPIOCFG_REG, 1 << offset, 0); | |
967 | ||
968 | mutex_unlock(&s->max310x_mutex); | |
969 | ||
970 | return 0; | |
971 | } | |
972 | ||
973 | static int max310x_gpio_direction_output(struct gpio_chip *chip, | |
974 | unsigned offset, int value) | |
975 | { | |
976 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | |
977 | ||
978 | mutex_lock(&s->max310x_mutex); | |
979 | ||
980 | regmap_update_bits(s->regmap, MAX310X_GPIOCFG_REG, 1 << offset, | |
981 | 1 << offset); | |
982 | regmap_update_bits(s->regmap, MAX310X_GPIODATA_REG, 1 << offset, value ? | |
983 | 1 << offset : 0); | |
984 | ||
985 | mutex_unlock(&s->max310x_mutex); | |
986 | ||
987 | return 0; | |
988 | } | |
989 | #endif | |
990 | ||
991 | /* Generic platform data */ | |
992 | static struct max310x_pdata generic_plat_data = { | |
993 | .driver_flags = MAX310X_EXT_CLK, | |
994 | .uart_flags[0] = MAX310X_ECHO_SUPRESS, | |
995 | .frequency = 26000000, | |
996 | }; | |
997 | ||
998 | static int __devinit max310x_probe(struct spi_device *spi) | |
999 | { | |
1000 | struct max310x_port *s; | |
1001 | struct device *dev = &spi->dev; | |
1002 | int chiptype = spi_get_device_id(spi)->driver_data; | |
1003 | struct max310x_pdata *pdata = dev->platform_data; | |
1004 | unsigned int val = 0; | |
1005 | int ret; | |
1006 | ||
1007 | /* Check for IRQ */ | |
1008 | if (spi->irq <= 0) { | |
1009 | dev_err(dev, "No IRQ specified\n"); | |
1010 | return -ENOTSUPP; | |
1011 | } | |
1012 | ||
1013 | /* Alloc port structure */ | |
1014 | s = devm_kzalloc(dev, sizeof(struct max310x_port), GFP_KERNEL); | |
1015 | if (!s) { | |
1016 | dev_err(dev, "Error allocating port structure\n"); | |
1017 | return -ENOMEM; | |
1018 | } | |
1019 | dev_set_drvdata(dev, s); | |
1020 | ||
1021 | if (!pdata) { | |
1022 | dev_warn(dev, "No platform data supplied, using defaults\n"); | |
1023 | pdata = &generic_plat_data; | |
1024 | } | |
1025 | s->pdata = pdata; | |
1026 | ||
1027 | /* Individual chip settings */ | |
1028 | switch (chiptype) { | |
1029 | case MAX310X_TYPE_MAX3107: | |
1030 | s->name = "MAX3107"; | |
1031 | s->nr_gpio = 4; | |
1032 | s->uart.nr = 1; | |
1033 | s->regcfg.max_register = 0x1f; | |
1034 | break; | |
1035 | case MAX310X_TYPE_MAX3108: | |
1036 | s->name = "MAX3108"; | |
1037 | s->nr_gpio = 4; | |
1038 | s->uart.nr = 1; | |
1039 | s->regcfg.max_register = 0x1e; | |
1040 | break; | |
1041 | default: | |
1042 | dev_err(dev, "Unsupported chip type %i\n", chiptype); | |
1043 | return -ENOTSUPP; | |
1044 | } | |
1045 | ||
1046 | /* Check input frequency */ | |
1047 | if ((pdata->driver_flags & MAX310X_EXT_CLK) && | |
1048 | ((pdata->frequency < 500000) || (pdata->frequency > 35000000))) | |
1049 | goto err_freq; | |
1050 | /* Check frequency for quartz */ | |
1051 | if (!(pdata->driver_flags & MAX310X_EXT_CLK) && | |
1052 | ((pdata->frequency < 1000000) || (pdata->frequency > 4000000))) | |
1053 | goto err_freq; | |
1054 | ||
1055 | mutex_init(&s->max310x_mutex); | |
1056 | ||
1057 | /* Setup SPI bus */ | |
1058 | spi->mode = SPI_MODE_0; | |
1059 | spi->bits_per_word = 8; | |
1060 | spi->max_speed_hz = 26000000; | |
1061 | spi_setup(spi); | |
1062 | ||
1063 | /* Setup regmap */ | |
1064 | s->regcfg.reg_bits = 8; | |
1065 | s->regcfg.val_bits = 8; | |
1066 | s->regcfg.read_flag_mask = 0x00; | |
1067 | s->regcfg.write_flag_mask = 0x80; | |
1068 | s->regcfg.cache_type = REGCACHE_RBTREE; | |
1069 | s->regcfg.writeable_reg = max3107_8_reg_writeable; | |
1070 | s->regcfg.volatile_reg = max310x_reg_volatile; | |
1071 | s->regcfg.precious_reg = max310x_reg_precious; | |
1072 | s->regmap = devm_regmap_init_spi(spi, &s->regcfg); | |
1073 | if (IS_ERR(s->regmap)) { | |
1074 | ret = PTR_ERR(s->regmap); | |
1075 | dev_err(dev, "Failed to initialize register map\n"); | |
1076 | goto err_out; | |
1077 | } | |
1078 | ||
1079 | /* Reset chip & check SPI function */ | |
1080 | ret = regmap_write(s->regmap, MAX310X_MODE2_REG, MAX310X_MODE2_RST_BIT); | |
1081 | if (ret) { | |
1082 | dev_err(dev, "SPI transfer failed\n"); | |
1083 | goto err_out; | |
1084 | } | |
1085 | /* Clear chip reset */ | |
1086 | regmap_write(s->regmap, MAX310X_MODE2_REG, 0); | |
1087 | ||
1088 | switch (chiptype) { | |
1089 | case MAX310X_TYPE_MAX3107: | |
1090 | /* Check REV ID to ensure we are talking to what we expect */ | |
1091 | regmap_read(s->regmap, MAX3107_REVID_REG, &val); | |
1092 | if (((val & MAX3107_REV_MASK) != MAX3107_REV_ID)) { | |
1093 | dev_err(dev, "%s ID 0x%02x does not match\n", | |
1094 | s->name, val); | |
1095 | ret = -ENODEV; | |
1096 | goto err_out; | |
1097 | } | |
1098 | break; | |
1099 | case MAX310X_TYPE_MAX3108: | |
1100 | /* MAX3108 have not REV ID register, we just check default value | |
1101 | * from clocksource register to make sure everything works. | |
1102 | */ | |
1103 | regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); | |
1104 | if (val != (MAX310X_CLKSRC_EXTCLK_BIT | | |
1105 | MAX310X_CLKSRC_PLLBYP_BIT)) { | |
1106 | dev_err(dev, "%s not present\n", s->name); | |
1107 | ret = -ENODEV; | |
1108 | goto err_out; | |
1109 | } | |
1110 | break; | |
1111 | } | |
1112 | ||
1113 | /* Board specific configure */ | |
1114 | if (pdata->init) | |
1115 | pdata->init(); | |
1116 | if (pdata->suspend) | |
1117 | pdata->suspend(0); | |
1118 | ||
1119 | /* Calculate referecne clock */ | |
1120 | s->uartclk = max310x_set_ref_clk(s); | |
1121 | ||
1122 | /* Disable all interrupts */ | |
1123 | regmap_write(s->regmap, MAX310X_IRQEN_REG, 0); | |
1124 | ||
1125 | /* Setup MODE1 register */ | |
1126 | val = MAX310X_MODE1_IRQSEL_BIT; /* Enable IRQ pin */ | |
1127 | if (pdata->driver_flags & MAX310X_AUTOSLEEP) | |
1128 | val = MAX310X_MODE1_AUTOSLEEP_BIT; | |
1129 | regmap_write(s->regmap, MAX310X_MODE1_REG, val); | |
1130 | ||
1131 | /* Setup interrupt */ | |
1132 | ret = devm_request_threaded_irq(dev, spi->irq, NULL, max310x_ist, | |
1133 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | |
1134 | dev_name(dev), s); | |
1135 | if (ret) { | |
1136 | dev_err(dev, "Unable to reguest IRQ %i\n", spi->irq); | |
1137 | goto err_out; | |
1138 | } | |
1139 | ||
1140 | /* Register UART driver */ | |
1141 | s->uart.owner = THIS_MODULE; | |
1142 | s->uart.driver_name = dev_name(dev); | |
1143 | s->uart.dev_name = "ttyMAX"; | |
1144 | s->uart.major = MAX310X_MAJOR; | |
1145 | s->uart.minor = MAX310X_MINOR; | |
1146 | ret = uart_register_driver(&s->uart); | |
1147 | if (ret) { | |
1148 | dev_err(dev, "Registering UART driver failed\n"); | |
1149 | goto err_out; | |
1150 | } | |
1151 | ||
1152 | /* Initialize workqueue for start TX */ | |
1153 | s->wq = create_freezable_workqueue(dev_name(dev)); | |
1154 | INIT_WORK(&s->tx_work, max310x_wq_proc); | |
1155 | ||
1156 | /* Initialize UART port data */ | |
1157 | s->port.line = 0; | |
1158 | s->port.dev = dev; | |
1159 | s->port.irq = spi->irq; | |
1160 | s->port.type = PORT_MAX310X; | |
1161 | s->port.fifosize = MAX310X_FIFO_SIZE; | |
1162 | s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; | |
1163 | s->port.iotype = UPIO_PORT; | |
1164 | s->port.membase = (void __iomem *)0xffffffff; /* Bogus value */ | |
1165 | s->port.uartclk = s->uartclk; | |
1166 | s->port.ops = &max310x_ops; | |
1167 | uart_add_one_port(&s->uart, &s->port); | |
1168 | ||
1169 | #ifdef CONFIG_GPIOLIB | |
1170 | /* Setup GPIO cotroller */ | |
1171 | if (pdata->gpio_base) { | |
1172 | s->gpio.owner = THIS_MODULE; | |
1173 | s->gpio.dev = dev; | |
1174 | s->gpio.label = dev_name(dev); | |
1175 | s->gpio.direction_input = max310x_gpio_direction_input; | |
1176 | s->gpio.get = max310x_gpio_get; | |
1177 | s->gpio.direction_output= max310x_gpio_direction_output; | |
1178 | s->gpio.set = max310x_gpio_set; | |
1179 | s->gpio.base = pdata->gpio_base; | |
1180 | s->gpio.ngpio = s->nr_gpio; | |
1181 | if (gpiochip_add(&s->gpio)) { | |
1182 | /* Indicate that we should not call gpiochip_remove */ | |
1183 | s->gpio.base = 0; | |
1184 | } | |
1185 | } else | |
1186 | dev_info(dev, "GPIO support not enabled\n"); | |
1187 | #endif | |
1188 | ||
1189 | /* Go to suspend mode */ | |
1190 | if (pdata->suspend) | |
1191 | pdata->suspend(1); | |
1192 | ||
1193 | return 0; | |
1194 | ||
1195 | err_freq: | |
1196 | dev_err(dev, "Frequency parameter incorrect\n"); | |
1197 | ret = -EINVAL; | |
1198 | ||
1199 | err_out: | |
1200 | dev_set_drvdata(dev, NULL); | |
1201 | devm_kfree(dev, s); | |
1202 | ||
1203 | return ret; | |
1204 | } | |
1205 | ||
1206 | static int __devexit max310x_remove(struct spi_device *spi) | |
1207 | { | |
1208 | struct device *dev = &spi->dev; | |
1209 | struct max310x_port *s = dev_get_drvdata(dev); | |
1210 | ||
1211 | dev_dbg(dev, "Removing port\n"); | |
1212 | ||
1213 | devm_free_irq(dev, s->port.irq, s); | |
1214 | ||
1215 | destroy_workqueue(s->wq); | |
1216 | ||
1217 | uart_remove_one_port(&s->uart, &s->port); | |
1218 | ||
1219 | uart_unregister_driver(&s->uart); | |
1220 | ||
1221 | #ifdef CONFIG_GPIOLIB | |
1222 | if (s->pdata->gpio_base) | |
1223 | gpiochip_remove(&s->gpio); | |
1224 | #endif | |
1225 | ||
1226 | dev_set_drvdata(dev, NULL); | |
1227 | ||
1228 | if (s->pdata->suspend) | |
1229 | s->pdata->suspend(1); | |
1230 | if (s->pdata->exit) | |
1231 | s->pdata->exit(); | |
1232 | ||
1233 | devm_kfree(dev, s); | |
1234 | ||
1235 | return 0; | |
1236 | } | |
1237 | ||
1238 | static const struct spi_device_id max310x_id_table[] = { | |
1239 | { "max3107", MAX310X_TYPE_MAX3107 }, | |
1240 | { "max3108", MAX310X_TYPE_MAX3108 }, | |
1241 | }; | |
1242 | MODULE_DEVICE_TABLE(spi, max310x_id_table); | |
1243 | ||
1244 | static struct spi_driver max310x_driver = { | |
1245 | .driver = { | |
1246 | .name = "max310x", | |
1247 | .owner = THIS_MODULE, | |
1248 | }, | |
1249 | .probe = max310x_probe, | |
1250 | .remove = __devexit_p(max310x_remove), | |
1251 | .suspend = max310x_suspend, | |
1252 | .resume = max310x_resume, | |
1253 | .id_table = max310x_id_table, | |
1254 | }; | |
1255 | module_spi_driver(max310x_driver); | |
1256 | ||
1257 | MODULE_LICENSE("GPL v2"); | |
1258 | MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); | |
1259 | MODULE_DESCRIPTION("MAX310X serial driver"); |