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49aa49bf GU |
1 | /****************************************************************************/ |
2 | ||
3 | /* | |
4 | * mcf.c -- Freescale ColdFire UART driver | |
5 | * | |
6a1c34f4 | 6 | * (C) Copyright 2003-2007, Greg Ungerer <gerg@uclinux.org> |
49aa49bf GU |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | /****************************************************************************/ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/console.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/tty_flip.h> | |
23 | #include <linux/serial.h> | |
24 | #include <linux/serial_core.h> | |
25 | #include <linux/io.h> | |
496c9077 | 26 | #include <linux/uaccess.h> |
574de559 | 27 | #include <linux/platform_device.h> |
49aa49bf GU |
28 | #include <asm/coldfire.h> |
29 | #include <asm/mcfsim.h> | |
30 | #include <asm/mcfuart.h> | |
31 | #include <asm/nettel.h> | |
32 | ||
33 | /****************************************************************************/ | |
34 | ||
35 | /* | |
36 | * Some boards implement the DTR/DCD lines using GPIO lines, most | |
37 | * don't. Dummy out the access macros for those that don't. Those | |
38 | * that do should define these macros somewhere in there board | |
39 | * specific inlude files. | |
40 | */ | |
41 | #if !defined(mcf_getppdcd) | |
42 | #define mcf_getppdcd(p) (1) | |
43 | #endif | |
44 | #if !defined(mcf_getppdtr) | |
45 | #define mcf_getppdtr(p) (1) | |
46 | #endif | |
47 | #if !defined(mcf_setppdtr) | |
48 | #define mcf_setppdtr(p, v) do { } while (0) | |
49 | #endif | |
50 | ||
51 | /****************************************************************************/ | |
52 | ||
53 | /* | |
54 | * Local per-uart structure. | |
55 | */ | |
56 | struct mcf_uart { | |
57 | struct uart_port port; | |
58 | unsigned int sigs; /* Local copy of line sigs */ | |
59 | unsigned char imr; /* Local IMR mirror */ | |
60 | }; | |
61 | ||
62 | /****************************************************************************/ | |
63 | ||
64 | static unsigned int mcf_tx_empty(struct uart_port *port) | |
65 | { | |
66 | return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ? | |
67 | TIOCSER_TEMT : 0; | |
68 | } | |
69 | ||
70 | /****************************************************************************/ | |
71 | ||
72 | static unsigned int mcf_get_mctrl(struct uart_port *port) | |
73 | { | |
9f69ba86 | 74 | struct mcf_uart *pp = container_of(port, struct mcf_uart, port); |
49aa49bf GU |
75 | unsigned int sigs; |
76 | ||
49aa49bf GU |
77 | sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ? |
78 | 0 : TIOCM_CTS; | |
79 | sigs |= (pp->sigs & TIOCM_RTS); | |
80 | sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0); | |
81 | sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0); | |
0ac8382e | 82 | |
49aa49bf GU |
83 | return sigs; |
84 | } | |
85 | ||
86 | /****************************************************************************/ | |
87 | ||
88 | static void mcf_set_mctrl(struct uart_port *port, unsigned int sigs) | |
89 | { | |
9f69ba86 | 90 | struct mcf_uart *pp = container_of(port, struct mcf_uart, port); |
49aa49bf | 91 | |
49aa49bf GU |
92 | pp->sigs = sigs; |
93 | mcf_setppdtr(port->line, (sigs & TIOCM_DTR)); | |
94 | if (sigs & TIOCM_RTS) | |
95 | writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); | |
96 | else | |
97 | writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0); | |
49aa49bf GU |
98 | } |
99 | ||
100 | /****************************************************************************/ | |
101 | ||
102 | static void mcf_start_tx(struct uart_port *port) | |
103 | { | |
9f69ba86 | 104 | struct mcf_uart *pp = container_of(port, struct mcf_uart, port); |
49aa49bf | 105 | |
2fc0184d | 106 | if (port->rs485.flags & SER_RS485_ENABLED) { |
496c9077 QVN |
107 | /* Enable Transmitter */ |
108 | writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR); | |
109 | /* Manually assert RTS */ | |
110 | writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); | |
111 | } | |
49aa49bf GU |
112 | pp->imr |= MCFUART_UIR_TXREADY; |
113 | writeb(pp->imr, port->membase + MCFUART_UIMR); | |
49aa49bf GU |
114 | } |
115 | ||
116 | /****************************************************************************/ | |
117 | ||
118 | static void mcf_stop_tx(struct uart_port *port) | |
119 | { | |
9f69ba86 | 120 | struct mcf_uart *pp = container_of(port, struct mcf_uart, port); |
49aa49bf | 121 | |
49aa49bf GU |
122 | pp->imr &= ~MCFUART_UIR_TXREADY; |
123 | writeb(pp->imr, port->membase + MCFUART_UIMR); | |
49aa49bf GU |
124 | } |
125 | ||
126 | /****************************************************************************/ | |
127 | ||
128 | static void mcf_stop_rx(struct uart_port *port) | |
129 | { | |
9f69ba86 | 130 | struct mcf_uart *pp = container_of(port, struct mcf_uart, port); |
49aa49bf | 131 | |
49aa49bf GU |
132 | pp->imr &= ~MCFUART_UIR_RXREADY; |
133 | writeb(pp->imr, port->membase + MCFUART_UIMR); | |
49aa49bf GU |
134 | } |
135 | ||
136 | /****************************************************************************/ | |
137 | ||
138 | static void mcf_break_ctl(struct uart_port *port, int break_state) | |
139 | { | |
140 | unsigned long flags; | |
141 | ||
142 | spin_lock_irqsave(&port->lock, flags); | |
143 | if (break_state == -1) | |
144 | writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR); | |
145 | else | |
146 | writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR); | |
147 | spin_unlock_irqrestore(&port->lock, flags); | |
148 | } | |
149 | ||
150 | /****************************************************************************/ | |
151 | ||
49aa49bf GU |
152 | static int mcf_startup(struct uart_port *port) |
153 | { | |
9f69ba86 | 154 | struct mcf_uart *pp = container_of(port, struct mcf_uart, port); |
49aa49bf GU |
155 | unsigned long flags; |
156 | ||
157 | spin_lock_irqsave(&port->lock, flags); | |
158 | ||
159 | /* Reset UART, get it into known state... */ | |
160 | writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); | |
161 | writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); | |
162 | ||
163 | /* Enable the UART transmitter and receiver */ | |
164 | writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE, | |
165 | port->membase + MCFUART_UCR); | |
166 | ||
167 | /* Enable RX interrupts now */ | |
168 | pp->imr = MCFUART_UIR_RXREADY; | |
169 | writeb(pp->imr, port->membase + MCFUART_UIMR); | |
170 | ||
171 | spin_unlock_irqrestore(&port->lock, flags); | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | /****************************************************************************/ | |
177 | ||
178 | static void mcf_shutdown(struct uart_port *port) | |
179 | { | |
9f69ba86 | 180 | struct mcf_uart *pp = container_of(port, struct mcf_uart, port); |
49aa49bf GU |
181 | unsigned long flags; |
182 | ||
183 | spin_lock_irqsave(&port->lock, flags); | |
184 | ||
185 | /* Disable all interrupts now */ | |
186 | pp->imr = 0; | |
187 | writeb(pp->imr, port->membase + MCFUART_UIMR); | |
188 | ||
189 | /* Disable UART transmitter and receiver */ | |
190 | writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); | |
191 | writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); | |
192 | ||
193 | spin_unlock_irqrestore(&port->lock, flags); | |
194 | } | |
195 | ||
196 | /****************************************************************************/ | |
197 | ||
198 | static void mcf_set_termios(struct uart_port *port, struct ktermios *termios, | |
199 | struct ktermios *old) | |
200 | { | |
201 | unsigned long flags; | |
202 | unsigned int baud, baudclk; | |
26a4bc66 JA |
203 | #if defined(CONFIG_M5272) |
204 | unsigned int baudfr; | |
205 | #endif | |
49aa49bf GU |
206 | unsigned char mr1, mr2; |
207 | ||
208 | baud = uart_get_baud_rate(port, termios, old, 0, 230400); | |
26a4bc66 JA |
209 | #if defined(CONFIG_M5272) |
210 | baudclk = (MCF_BUSCLK / baud) / 32; | |
211 | baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16; | |
212 | #else | |
49aa49bf | 213 | baudclk = ((MCF_BUSCLK / baud) + 16) / 32; |
26a4bc66 | 214 | #endif |
49aa49bf GU |
215 | |
216 | mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR; | |
217 | mr2 = 0; | |
218 | ||
219 | switch (termios->c_cflag & CSIZE) { | |
220 | case CS5: mr1 |= MCFUART_MR1_CS5; break; | |
221 | case CS6: mr1 |= MCFUART_MR1_CS6; break; | |
222 | case CS7: mr1 |= MCFUART_MR1_CS7; break; | |
223 | case CS8: | |
224 | default: mr1 |= MCFUART_MR1_CS8; break; | |
225 | } | |
226 | ||
227 | if (termios->c_cflag & PARENB) { | |
228 | if (termios->c_cflag & CMSPAR) { | |
229 | if (termios->c_cflag & PARODD) | |
230 | mr1 |= MCFUART_MR1_PARITYMARK; | |
231 | else | |
232 | mr1 |= MCFUART_MR1_PARITYSPACE; | |
233 | } else { | |
234 | if (termios->c_cflag & PARODD) | |
235 | mr1 |= MCFUART_MR1_PARITYODD; | |
236 | else | |
237 | mr1 |= MCFUART_MR1_PARITYEVEN; | |
238 | } | |
239 | } else { | |
240 | mr1 |= MCFUART_MR1_PARITYNONE; | |
241 | } | |
242 | ||
ef8b9ddc PH |
243 | /* |
244 | * FIXME: port->read_status_mask and port->ignore_status_mask | |
245 | * need to be initialized based on termios settings for | |
246 | * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT | |
247 | */ | |
248 | ||
49aa49bf GU |
249 | if (termios->c_cflag & CSTOPB) |
250 | mr2 |= MCFUART_MR2_STOP2; | |
251 | else | |
252 | mr2 |= MCFUART_MR2_STOP1; | |
253 | ||
254 | if (termios->c_cflag & CRTSCTS) { | |
255 | mr1 |= MCFUART_MR1_RXRTS; | |
256 | mr2 |= MCFUART_MR2_TXCTS; | |
257 | } | |
258 | ||
bd737f87 | 259 | spin_lock_irqsave(&port->lock, flags); |
2fc0184d | 260 | if (port->rs485.flags & SER_RS485_ENABLED) { |
496c9077 QVN |
261 | dev_dbg(port->dev, "Setting UART to RS485\n"); |
262 | mr2 |= MCFUART_MR2_TXRTS; | |
263 | } | |
264 | ||
3732b68f | 265 | uart_update_timeout(port, termios->c_cflag, baud); |
49aa49bf GU |
266 | writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); |
267 | writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); | |
268 | writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR); | |
269 | writeb(mr1, port->membase + MCFUART_UMR); | |
270 | writeb(mr2, port->membase + MCFUART_UMR); | |
271 | writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1); | |
272 | writeb((baudclk & 0xff), port->membase + MCFUART_UBG2); | |
26a4bc66 JA |
273 | #if defined(CONFIG_M5272) |
274 | writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD); | |
275 | #endif | |
49aa49bf GU |
276 | writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER, |
277 | port->membase + MCFUART_UCSR); | |
278 | writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE, | |
279 | port->membase + MCFUART_UCR); | |
280 | spin_unlock_irqrestore(&port->lock, flags); | |
281 | } | |
282 | ||
283 | /****************************************************************************/ | |
284 | ||
285 | static void mcf_rx_chars(struct mcf_uart *pp) | |
286 | { | |
9f69ba86 | 287 | struct uart_port *port = &pp->port; |
49aa49bf GU |
288 | unsigned char status, ch, flag; |
289 | ||
290 | while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) { | |
291 | ch = readb(port->membase + MCFUART_URB); | |
292 | flag = TTY_NORMAL; | |
293 | port->icount.rx++; | |
294 | ||
295 | if (status & MCFUART_USR_RXERR) { | |
296 | writeb(MCFUART_UCR_CMDRESETERR, | |
297 | port->membase + MCFUART_UCR); | |
298 | ||
299 | if (status & MCFUART_USR_RXBREAK) { | |
300 | port->icount.brk++; | |
301 | if (uart_handle_break(port)) | |
302 | continue; | |
303 | } else if (status & MCFUART_USR_RXPARITY) { | |
304 | port->icount.parity++; | |
305 | } else if (status & MCFUART_USR_RXOVERRUN) { | |
306 | port->icount.overrun++; | |
307 | } else if (status & MCFUART_USR_RXFRAMING) { | |
308 | port->icount.frame++; | |
309 | } | |
310 | ||
311 | status &= port->read_status_mask; | |
312 | ||
313 | if (status & MCFUART_USR_RXBREAK) | |
314 | flag = TTY_BREAK; | |
315 | else if (status & MCFUART_USR_RXPARITY) | |
316 | flag = TTY_PARITY; | |
317 | else if (status & MCFUART_USR_RXFRAMING) | |
318 | flag = TTY_FRAME; | |
319 | } | |
320 | ||
321 | if (uart_handle_sysrq_char(port, ch)) | |
322 | continue; | |
323 | uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag); | |
324 | } | |
325 | ||
5275ad70 | 326 | spin_unlock(&port->lock); |
2e124b4a | 327 | tty_flip_buffer_push(&port->state->port); |
5275ad70 | 328 | spin_lock(&port->lock); |
49aa49bf GU |
329 | } |
330 | ||
331 | /****************************************************************************/ | |
332 | ||
333 | static void mcf_tx_chars(struct mcf_uart *pp) | |
334 | { | |
9f69ba86 | 335 | struct uart_port *port = &pp->port; |
ebd2c8f6 | 336 | struct circ_buf *xmit = &port->state->xmit; |
49aa49bf GU |
337 | |
338 | if (port->x_char) { | |
339 | /* Send special char - probably flow control */ | |
340 | writeb(port->x_char, port->membase + MCFUART_UTB); | |
341 | port->x_char = 0; | |
342 | port->icount.tx++; | |
343 | return; | |
344 | } | |
345 | ||
346 | while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) { | |
347 | if (xmit->head == xmit->tail) | |
348 | break; | |
349 | writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB); | |
350 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1); | |
351 | port->icount.tx++; | |
352 | } | |
353 | ||
354 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
355 | uart_write_wakeup(port); | |
356 | ||
357 | if (xmit->head == xmit->tail) { | |
358 | pp->imr &= ~MCFUART_UIR_TXREADY; | |
359 | writeb(pp->imr, port->membase + MCFUART_UIMR); | |
496c9077 | 360 | /* Disable TX to negate RTS automatically */ |
2fc0184d | 361 | if (port->rs485.flags & SER_RS485_ENABLED) |
496c9077 QVN |
362 | writeb(MCFUART_UCR_TXDISABLE, |
363 | port->membase + MCFUART_UCR); | |
49aa49bf GU |
364 | } |
365 | } | |
366 | ||
367 | /****************************************************************************/ | |
368 | ||
369 | static irqreturn_t mcf_interrupt(int irq, void *data) | |
370 | { | |
371 | struct uart_port *port = data; | |
9f69ba86 | 372 | struct mcf_uart *pp = container_of(port, struct mcf_uart, port); |
49aa49bf | 373 | unsigned int isr; |
0ac8382e | 374 | irqreturn_t ret = IRQ_NONE; |
49aa49bf GU |
375 | |
376 | isr = readb(port->membase + MCFUART_UISR) & pp->imr; | |
0ac8382e YG |
377 | |
378 | spin_lock(&port->lock); | |
379 | if (isr & MCFUART_UIR_RXREADY) { | |
49aa49bf | 380 | mcf_rx_chars(pp); |
0ac8382e YG |
381 | ret = IRQ_HANDLED; |
382 | } | |
383 | if (isr & MCFUART_UIR_TXREADY) { | |
49aa49bf | 384 | mcf_tx_chars(pp); |
0ac8382e YG |
385 | ret = IRQ_HANDLED; |
386 | } | |
387 | spin_unlock(&port->lock); | |
388 | ||
389 | return ret; | |
49aa49bf GU |
390 | } |
391 | ||
392 | /****************************************************************************/ | |
393 | ||
394 | static void mcf_config_port(struct uart_port *port, int flags) | |
395 | { | |
396 | port->type = PORT_MCF; | |
3732b68f | 397 | port->fifosize = MCFUART_TXFIFOSIZE; |
49aa49bf GU |
398 | |
399 | /* Clear mask, so no surprise interrupts. */ | |
400 | writeb(0, port->membase + MCFUART_UIMR); | |
401 | ||
9cfb5c05 | 402 | if (request_irq(port->irq, mcf_interrupt, 0, "UART", port)) |
49aa49bf GU |
403 | printk(KERN_ERR "MCF: unable to attach ColdFire UART %d " |
404 | "interrupt vector=%d\n", port->line, port->irq); | |
405 | } | |
406 | ||
407 | /****************************************************************************/ | |
408 | ||
409 | static const char *mcf_type(struct uart_port *port) | |
410 | { | |
411 | return (port->type == PORT_MCF) ? "ColdFire UART" : NULL; | |
412 | } | |
413 | ||
414 | /****************************************************************************/ | |
415 | ||
416 | static int mcf_request_port(struct uart_port *port) | |
417 | { | |
418 | /* UARTs always present */ | |
419 | return 0; | |
420 | } | |
421 | ||
422 | /****************************************************************************/ | |
423 | ||
424 | static void mcf_release_port(struct uart_port *port) | |
425 | { | |
426 | /* Nothing to release... */ | |
427 | } | |
428 | ||
429 | /****************************************************************************/ | |
430 | ||
431 | static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser) | |
432 | { | |
433 | if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF)) | |
434 | return -EINVAL; | |
435 | return 0; | |
436 | } | |
437 | ||
438 | /****************************************************************************/ | |
439 | ||
496c9077 | 440 | /* Enable or disable the RS485 support */ |
2fc0184d | 441 | static int mcf_config_rs485(struct uart_port *port, struct serial_rs485 *rs485) |
496c9077 | 442 | { |
496c9077 QVN |
443 | unsigned char mr1, mr2; |
444 | ||
496c9077 QVN |
445 | /* Get mode registers */ |
446 | mr1 = readb(port->membase + MCFUART_UMR); | |
447 | mr2 = readb(port->membase + MCFUART_UMR); | |
448 | if (rs485->flags & SER_RS485_ENABLED) { | |
449 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
450 | /* Automatically negate RTS after TX completes */ | |
451 | mr2 |= MCFUART_MR2_TXRTS; | |
452 | } else { | |
453 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
454 | mr2 &= ~MCFUART_MR2_TXRTS; | |
455 | } | |
456 | writeb(mr1, port->membase + MCFUART_UMR); | |
457 | writeb(mr2, port->membase + MCFUART_UMR); | |
2fc0184d | 458 | port->rs485 = *rs485; |
496c9077 | 459 | |
496c9077 QVN |
460 | return 0; |
461 | } | |
462 | ||
463 | /****************************************************************************/ | |
464 | ||
49aa49bf GU |
465 | /* |
466 | * Define the basic serial functions we support. | |
467 | */ | |
3732b68f | 468 | static const struct uart_ops mcf_uart_ops = { |
49aa49bf GU |
469 | .tx_empty = mcf_tx_empty, |
470 | .get_mctrl = mcf_get_mctrl, | |
471 | .set_mctrl = mcf_set_mctrl, | |
472 | .start_tx = mcf_start_tx, | |
473 | .stop_tx = mcf_stop_tx, | |
474 | .stop_rx = mcf_stop_rx, | |
49aa49bf GU |
475 | .break_ctl = mcf_break_ctl, |
476 | .startup = mcf_startup, | |
477 | .shutdown = mcf_shutdown, | |
478 | .set_termios = mcf_set_termios, | |
479 | .type = mcf_type, | |
480 | .request_port = mcf_request_port, | |
481 | .release_port = mcf_release_port, | |
482 | .config_port = mcf_config_port, | |
483 | .verify_port = mcf_verify_port, | |
484 | }; | |
485 | ||
2545cf6e | 486 | static struct mcf_uart mcf_ports[4]; |
49aa49bf | 487 | |
16791963 | 488 | #define MCF_MAXPORTS ARRAY_SIZE(mcf_ports) |
49aa49bf GU |
489 | |
490 | /****************************************************************************/ | |
491 | #if defined(CONFIG_SERIAL_MCF_CONSOLE) | |
492 | /****************************************************************************/ | |
493 | ||
494 | int __init early_mcf_setup(struct mcf_platform_uart *platp) | |
495 | { | |
496 | struct uart_port *port; | |
497 | int i; | |
498 | ||
499 | for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) { | |
500 | port = &mcf_ports[i].port; | |
501 | ||
502 | port->line = i; | |
503 | port->type = PORT_MCF; | |
504 | port->mapbase = platp[i].mapbase; | |
505 | port->membase = (platp[i].membase) ? platp[i].membase : | |
506 | (unsigned char __iomem *) port->mapbase; | |
507 | port->iotype = SERIAL_IO_MEM; | |
508 | port->irq = platp[i].irq; | |
509 | port->uartclk = MCF_BUSCLK; | |
5fda7a0e | 510 | port->flags = UPF_BOOT_AUTOCONF; |
2fc0184d | 511 | port->rs485_config = mcf_config_rs485; |
49aa49bf GU |
512 | port->ops = &mcf_uart_ops; |
513 | } | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
518 | /****************************************************************************/ | |
519 | ||
520 | static void mcf_console_putc(struct console *co, const char c) | |
521 | { | |
522 | struct uart_port *port = &(mcf_ports + co->index)->port; | |
523 | int i; | |
524 | ||
525 | for (i = 0; (i < 0x10000); i++) { | |
526 | if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) | |
527 | break; | |
528 | } | |
529 | writeb(c, port->membase + MCFUART_UTB); | |
530 | for (i = 0; (i < 0x10000); i++) { | |
531 | if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) | |
532 | break; | |
533 | } | |
534 | } | |
535 | ||
536 | /****************************************************************************/ | |
537 | ||
538 | static void mcf_console_write(struct console *co, const char *s, unsigned int count) | |
539 | { | |
540 | for (; (count); count--, s++) { | |
541 | mcf_console_putc(co, *s); | |
542 | if (*s == '\n') | |
543 | mcf_console_putc(co, '\r'); | |
544 | } | |
545 | } | |
546 | ||
547 | /****************************************************************************/ | |
548 | ||
549 | static int __init mcf_console_setup(struct console *co, char *options) | |
550 | { | |
551 | struct uart_port *port; | |
552 | int baud = CONFIG_SERIAL_MCF_BAUDRATE; | |
553 | int bits = 8; | |
554 | int parity = 'n'; | |
555 | int flow = 'n'; | |
556 | ||
4330e179 | 557 | if ((co->index < 0) || (co->index >= MCF_MAXPORTS)) |
49aa49bf GU |
558 | co->index = 0; |
559 | port = &mcf_ports[co->index].port; | |
560 | if (port->membase == 0) | |
561 | return -ENODEV; | |
562 | ||
563 | if (options) | |
564 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
565 | ||
566 | return uart_set_options(port, co, baud, parity, bits, flow); | |
567 | } | |
568 | ||
569 | /****************************************************************************/ | |
570 | ||
571 | static struct uart_driver mcf_driver; | |
572 | ||
573 | static struct console mcf_console = { | |
574 | .name = "ttyS", | |
575 | .write = mcf_console_write, | |
576 | .device = uart_console_device, | |
577 | .setup = mcf_console_setup, | |
578 | .flags = CON_PRINTBUFFER, | |
579 | .index = -1, | |
580 | .data = &mcf_driver, | |
581 | }; | |
582 | ||
583 | static int __init mcf_console_init(void) | |
584 | { | |
585 | register_console(&mcf_console); | |
586 | return 0; | |
587 | } | |
588 | ||
589 | console_initcall(mcf_console_init); | |
590 | ||
591 | #define MCF_CONSOLE &mcf_console | |
592 | ||
593 | /****************************************************************************/ | |
594 | #else | |
595 | /****************************************************************************/ | |
596 | ||
597 | #define MCF_CONSOLE NULL | |
598 | ||
599 | /****************************************************************************/ | |
bbdfe620 | 600 | #endif /* CONFIG_SERIAL_MCF_CONSOLE */ |
49aa49bf GU |
601 | /****************************************************************************/ |
602 | ||
603 | /* | |
604 | * Define the mcf UART driver structure. | |
605 | */ | |
606 | static struct uart_driver mcf_driver = { | |
607 | .owner = THIS_MODULE, | |
608 | .driver_name = "mcf", | |
609 | .dev_name = "ttyS", | |
610 | .major = TTY_MAJOR, | |
611 | .minor = 64, | |
612 | .nr = MCF_MAXPORTS, | |
613 | .cons = MCF_CONSOLE, | |
614 | }; | |
615 | ||
616 | /****************************************************************************/ | |
617 | ||
9671f099 | 618 | static int mcf_probe(struct platform_device *pdev) |
49aa49bf | 619 | { |
574de559 | 620 | struct mcf_platform_uart *platp = dev_get_platdata(&pdev->dev); |
49aa49bf GU |
621 | struct uart_port *port; |
622 | int i; | |
623 | ||
624 | for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) { | |
625 | port = &mcf_ports[i].port; | |
626 | ||
627 | port->line = i; | |
628 | port->type = PORT_MCF; | |
629 | port->mapbase = platp[i].mapbase; | |
630 | port->membase = (platp[i].membase) ? platp[i].membase : | |
631 | (unsigned char __iomem *) platp[i].mapbase; | |
201d8975 | 632 | port->dev = &pdev->dev; |
49aa49bf GU |
633 | port->iotype = SERIAL_IO_MEM; |
634 | port->irq = platp[i].irq; | |
635 | port->uartclk = MCF_BUSCLK; | |
636 | port->ops = &mcf_uart_ops; | |
5fda7a0e | 637 | port->flags = UPF_BOOT_AUTOCONF; |
2fc0184d | 638 | port->rs485_config = mcf_config_rs485; |
49aa49bf GU |
639 | |
640 | uart_add_one_port(&mcf_driver, port); | |
641 | } | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
646 | /****************************************************************************/ | |
647 | ||
ae8d8a14 | 648 | static int mcf_remove(struct platform_device *pdev) |
49aa49bf GU |
649 | { |
650 | struct uart_port *port; | |
651 | int i; | |
652 | ||
653 | for (i = 0; (i < MCF_MAXPORTS); i++) { | |
654 | port = &mcf_ports[i].port; | |
655 | if (port) | |
656 | uart_remove_one_port(&mcf_driver, port); | |
657 | } | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
662 | /****************************************************************************/ | |
663 | ||
664 | static struct platform_driver mcf_platform_driver = { | |
665 | .probe = mcf_probe, | |
2d47b716 | 666 | .remove = mcf_remove, |
49aa49bf GU |
667 | .driver = { |
668 | .name = "mcfuart", | |
49aa49bf GU |
669 | }, |
670 | }; | |
671 | ||
672 | /****************************************************************************/ | |
673 | ||
674 | static int __init mcf_init(void) | |
675 | { | |
676 | int rc; | |
677 | ||
678 | printk("ColdFire internal UART serial driver\n"); | |
679 | ||
680 | rc = uart_register_driver(&mcf_driver); | |
681 | if (rc) | |
682 | return rc; | |
683 | rc = platform_driver_register(&mcf_platform_driver); | |
2b359172 WY |
684 | if (rc) { |
685 | uart_unregister_driver(&mcf_driver); | |
49aa49bf | 686 | return rc; |
2b359172 | 687 | } |
49aa49bf GU |
688 | return 0; |
689 | } | |
690 | ||
691 | /****************************************************************************/ | |
692 | ||
693 | static void __exit mcf_exit(void) | |
694 | { | |
695 | platform_driver_unregister(&mcf_platform_driver); | |
696 | uart_unregister_driver(&mcf_driver); | |
697 | } | |
698 | ||
699 | /****************************************************************************/ | |
700 | ||
701 | module_init(mcf_init); | |
702 | module_exit(mcf_exit); | |
703 | ||
6a1c34f4 | 704 | MODULE_AUTHOR("Greg Ungerer <gerg@uclinux.org>"); |
49aa49bf GU |
705 | MODULE_DESCRIPTION("Freescale ColdFire UART driver"); |
706 | MODULE_LICENSE("GPL"); | |
e169c139 | 707 | MODULE_ALIAS("platform:mcfuart"); |
49aa49bf GU |
708 | |
709 | /****************************************************************************/ |