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e264ebf4 JT |
1 | /* |
2 | * MEN 16z135 High Speed UART | |
3 | * | |
4 | * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de) | |
5 | * Author: Johannes Thumshirn <johannes.thumshirn@men.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the Free | |
9 | * Software Foundation; version 2 of the License. | |
10 | */ | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ":" fmt | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/serial_core.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/tty_flip.h> | |
20 | #include <linux/bitops.h> | |
21 | #include <linux/mcb.h> | |
22 | ||
23 | #define MEN_Z135_MAX_PORTS 12 | |
24 | #define MEN_Z135_BASECLK 29491200 | |
25 | #define MEN_Z135_FIFO_SIZE 1024 | |
26 | #define MEN_Z135_NUM_MSI_VECTORS 2 | |
27 | #define MEN_Z135_FIFO_WATERMARK 1020 | |
28 | ||
29 | #define MEN_Z135_STAT_REG 0x0 | |
30 | #define MEN_Z135_RX_RAM 0x4 | |
31 | #define MEN_Z135_TX_RAM 0x400 | |
32 | #define MEN_Z135_RX_CTRL 0x800 | |
33 | #define MEN_Z135_TX_CTRL 0x804 | |
34 | #define MEN_Z135_CONF_REG 0x808 | |
35 | #define MEN_Z135_UART_FREQ 0x80c | |
36 | #define MEN_Z135_BAUD_REG 0x810 | |
37 | #define MENZ135_TIMEOUT 0x814 | |
38 | ||
39 | #define MEN_Z135_MEM_SIZE 0x818 | |
40 | ||
41 | #define IS_IRQ(x) ((x) & 1) | |
42 | #define IRQ_ID(x) (((x) >> 1) & 7) | |
43 | ||
10389e66 JT |
44 | #define MEN_Z135_IER_RXCIEN BIT(0) /* RX Space IRQ */ |
45 | #define MEN_Z135_IER_TXCIEN BIT(1) /* TX Space IRQ */ | |
e264ebf4 JT |
46 | #define MEN_Z135_IER_RLSIEN BIT(2) /* Receiver Line Status IRQ */ |
47 | #define MEN_Z135_IER_MSIEN BIT(3) /* Modem Status IRQ */ | |
48 | #define MEN_Z135_ALL_IRQS (MEN_Z135_IER_RXCIEN \ | |
49 | | MEN_Z135_IER_RLSIEN \ | |
50 | | MEN_Z135_IER_MSIEN \ | |
51 | | MEN_Z135_IER_TXCIEN) | |
52 | ||
53 | #define MEN_Z135_MCR_DTR BIT(24) | |
54 | #define MEN_Z135_MCR_RTS BIT(25) | |
55 | #define MEN_Z135_MCR_OUT1 BIT(26) | |
56 | #define MEN_Z135_MCR_OUT2 BIT(27) | |
57 | #define MEN_Z135_MCR_LOOP BIT(28) | |
58 | #define MEN_Z135_MCR_RCFC BIT(29) | |
59 | ||
60 | #define MEN_Z135_MSR_DCTS BIT(0) | |
61 | #define MEN_Z135_MSR_DDSR BIT(1) | |
62 | #define MEN_Z135_MSR_DRI BIT(2) | |
63 | #define MEN_Z135_MSR_DDCD BIT(3) | |
64 | #define MEN_Z135_MSR_CTS BIT(4) | |
65 | #define MEN_Z135_MSR_DSR BIT(5) | |
66 | #define MEN_Z135_MSR_RI BIT(6) | |
67 | #define MEN_Z135_MSR_DCD BIT(7) | |
68 | ||
69 | #define MEN_Z135_LCR_SHIFT 8 /* LCR shift mask */ | |
70 | ||
71 | #define MEN_Z135_WL5 0 /* CS5 */ | |
72 | #define MEN_Z135_WL6 1 /* CS6 */ | |
73 | #define MEN_Z135_WL7 2 /* CS7 */ | |
74 | #define MEN_Z135_WL8 3 /* CS8 */ | |
75 | ||
76 | #define MEN_Z135_STB_SHIFT 2 /* Stopbits */ | |
77 | #define MEN_Z135_NSTB1 0 | |
78 | #define MEN_Z135_NSTB2 1 | |
79 | ||
80 | #define MEN_Z135_PEN_SHIFT 3 /* Parity enable */ | |
81 | #define MEN_Z135_PAR_DIS 0 | |
82 | #define MEN_Z135_PAR_ENA 1 | |
83 | ||
84 | #define MEN_Z135_PTY_SHIFT 4 /* Parity type */ | |
85 | #define MEN_Z135_PTY_ODD 0 | |
86 | #define MEN_Z135_PTY_EVN 1 | |
87 | ||
88 | #define MEN_Z135_LSR_DR BIT(0) | |
89 | #define MEN_Z135_LSR_OE BIT(1) | |
90 | #define MEN_Z135_LSR_PE BIT(2) | |
91 | #define MEN_Z135_LSR_FE BIT(3) | |
92 | #define MEN_Z135_LSR_BI BIT(4) | |
93 | #define MEN_Z135_LSR_THEP BIT(5) | |
94 | #define MEN_Z135_LSR_TEXP BIT(6) | |
95 | #define MEN_Z135_LSR_RXFIFOERR BIT(7) | |
96 | ||
97 | #define MEN_Z135_IRQ_ID_MST 0 | |
98 | #define MEN_Z135_IRQ_ID_TSA 1 | |
99 | #define MEN_Z135_IRQ_ID_RDA 2 | |
100 | #define MEN_Z135_IRQ_ID_RLS 3 | |
101 | #define MEN_Z135_IRQ_ID_CTI 6 | |
102 | ||
103 | #define LCR(x) (((x) >> MEN_Z135_LCR_SHIFT) & 0xff) | |
104 | ||
105 | #define BYTES_TO_ALIGN(x) ((x) & 0x3) | |
106 | ||
107 | static int line; | |
108 | ||
109 | static int txlvl = 5; | |
110 | module_param(txlvl, int, S_IRUGO); | |
111 | MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)"); | |
112 | ||
113 | static int rxlvl = 6; | |
114 | module_param(rxlvl, int, S_IRUGO); | |
115 | MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)"); | |
116 | ||
117 | static int align; | |
118 | module_param(align, int, S_IRUGO); | |
119 | MODULE_PARM_DESC(align, "Keep hardware FIFO write pointer aligned, default 0"); | |
120 | ||
121 | struct men_z135_port { | |
122 | struct uart_port port; | |
123 | struct mcb_device *mdev; | |
124 | unsigned char *rxbuf; | |
125 | u32 stat_reg; | |
126 | spinlock_t lock; | |
127 | }; | |
128 | #define to_men_z135(port) container_of((port), struct men_z135_port, port) | |
129 | ||
130 | /** | |
131 | * men_z135_reg_set() - Set value in register | |
132 | * @uart: The UART port | |
133 | * @addr: Register address | |
134 | * @val: value to set | |
135 | */ | |
136 | static inline void men_z135_reg_set(struct men_z135_port *uart, | |
137 | u32 addr, u32 val) | |
138 | { | |
139 | struct uart_port *port = &uart->port; | |
140 | unsigned long flags; | |
141 | u32 reg; | |
142 | ||
143 | spin_lock_irqsave(&uart->lock, flags); | |
144 | ||
145 | reg = ioread32(port->membase + addr); | |
146 | reg |= val; | |
147 | iowrite32(reg, port->membase + addr); | |
148 | ||
149 | spin_unlock_irqrestore(&uart->lock, flags); | |
150 | } | |
151 | ||
152 | /** | |
153 | * men_z135_reg_clr() - Unset value in register | |
154 | * @uart: The UART port | |
155 | * @addr: Register address | |
156 | * @val: value to clear | |
157 | */ | |
158 | static inline void men_z135_reg_clr(struct men_z135_port *uart, | |
159 | u32 addr, u32 val) | |
160 | { | |
161 | struct uart_port *port = &uart->port; | |
162 | unsigned long flags; | |
163 | u32 reg; | |
164 | ||
165 | spin_lock_irqsave(&uart->lock, flags); | |
166 | ||
167 | reg = ioread32(port->membase + addr); | |
168 | reg &= ~val; | |
169 | iowrite32(reg, port->membase + addr); | |
170 | ||
171 | spin_unlock_irqrestore(&uart->lock, flags); | |
172 | } | |
173 | ||
174 | /** | |
175 | * men_z135_handle_modem_status() - Handle change of modem status | |
176 | * @port: The UART port | |
177 | * | |
178 | * Handle change of modem status register. This is done by reading the "delta" | |
179 | * versions of DCD (Data Carrier Detect) and CTS (Clear To Send). | |
180 | */ | |
181 | static void men_z135_handle_modem_status(struct men_z135_port *uart) | |
182 | { | |
183 | if (uart->stat_reg & MEN_Z135_MSR_DDCD) | |
184 | uart_handle_dcd_change(&uart->port, | |
185 | uart->stat_reg & ~MEN_Z135_MSR_DCD); | |
186 | if (uart->stat_reg & MEN_Z135_MSR_DCTS) | |
187 | uart_handle_cts_change(&uart->port, | |
188 | uart->stat_reg & ~MEN_Z135_MSR_CTS); | |
189 | } | |
190 | ||
191 | static void men_z135_handle_lsr(struct men_z135_port *uart) | |
192 | { | |
193 | struct uart_port *port = &uart->port; | |
194 | u8 lsr; | |
195 | ||
196 | lsr = (uart->stat_reg >> 16) & 0xff; | |
197 | ||
198 | if (lsr & MEN_Z135_LSR_OE) | |
199 | port->icount.overrun++; | |
200 | if (lsr & MEN_Z135_LSR_PE) | |
201 | port->icount.parity++; | |
202 | if (lsr & MEN_Z135_LSR_FE) | |
203 | port->icount.frame++; | |
204 | if (lsr & MEN_Z135_LSR_BI) { | |
205 | port->icount.brk++; | |
206 | uart_handle_break(port); | |
207 | } | |
208 | } | |
209 | ||
210 | /** | |
211 | * get_rx_fifo_content() - Get the number of bytes in RX FIFO | |
212 | * @uart: The UART port | |
213 | * | |
214 | * Read RXC register from hardware and return current FIFO fill size. | |
215 | */ | |
216 | static u16 get_rx_fifo_content(struct men_z135_port *uart) | |
217 | { | |
218 | struct uart_port *port = &uart->port; | |
219 | u32 stat_reg; | |
220 | u16 rxc; | |
221 | u8 rxc_lo; | |
222 | u8 rxc_hi; | |
223 | ||
224 | stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG); | |
225 | rxc_lo = stat_reg >> 24; | |
226 | rxc_hi = (stat_reg & 0xC0) >> 6; | |
227 | ||
228 | rxc = rxc_lo | (rxc_hi << 8); | |
229 | ||
230 | return rxc; | |
231 | } | |
232 | ||
233 | /** | |
234 | * men_z135_handle_rx() - RX tasklet routine | |
235 | * @arg: Pointer to struct men_z135_port | |
236 | * | |
237 | * Copy from RX FIFO and acknowledge number of bytes copied. | |
238 | */ | |
239 | static void men_z135_handle_rx(struct men_z135_port *uart) | |
240 | { | |
241 | struct uart_port *port = &uart->port; | |
242 | struct tty_port *tport = &port->state->port; | |
243 | int copied; | |
244 | u16 size; | |
245 | int room; | |
246 | ||
247 | size = get_rx_fifo_content(uart); | |
248 | ||
249 | if (size == 0) | |
250 | return; | |
251 | ||
252 | /* Avoid accidently accessing TX FIFO instead of RX FIFO. Last | |
253 | * longword in RX FIFO cannot be read.(0x004-0x3FF) | |
254 | */ | |
255 | if (size > MEN_Z135_FIFO_WATERMARK) | |
256 | size = MEN_Z135_FIFO_WATERMARK; | |
257 | ||
258 | room = tty_buffer_request_room(tport, size); | |
259 | if (room != size) | |
260 | dev_warn(&uart->mdev->dev, | |
261 | "Not enough room in flip buffer, truncating to %d\n", | |
262 | room); | |
263 | ||
264 | if (room == 0) | |
265 | return; | |
266 | ||
267 | memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room); | |
268 | /* Be sure to first copy all data and then acknowledge it */ | |
269 | mb(); | |
270 | iowrite32(room, port->membase + MEN_Z135_RX_CTRL); | |
271 | ||
272 | copied = tty_insert_flip_string(tport, uart->rxbuf, room); | |
273 | if (copied != room) | |
274 | dev_warn(&uart->mdev->dev, | |
275 | "Only copied %d instead of %d bytes\n", | |
276 | copied, room); | |
277 | ||
278 | port->icount.rx += copied; | |
279 | ||
280 | tty_flip_buffer_push(tport); | |
281 | ||
282 | } | |
283 | ||
284 | /** | |
285 | * men_z135_handle_tx() - TX tasklet routine | |
286 | * @arg: Pointer to struct men_z135_port | |
287 | * | |
288 | */ | |
289 | static void men_z135_handle_tx(struct men_z135_port *uart) | |
290 | { | |
291 | struct uart_port *port = &uart->port; | |
292 | struct circ_buf *xmit = &port->state->xmit; | |
293 | u32 txc; | |
294 | u32 wptr; | |
295 | int qlen; | |
296 | int n; | |
297 | int txfree; | |
298 | int head; | |
299 | int tail; | |
300 | int s; | |
301 | ||
302 | if (uart_circ_empty(xmit)) | |
303 | goto out; | |
304 | ||
305 | if (uart_tx_stopped(port)) | |
306 | goto out; | |
307 | ||
308 | if (port->x_char) | |
309 | goto out; | |
310 | ||
e264ebf4 JT |
311 | /* calculate bytes to copy */ |
312 | qlen = uart_circ_chars_pending(xmit); | |
313 | if (qlen <= 0) | |
314 | goto out; | |
315 | ||
316 | wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); | |
317 | txc = (wptr >> 16) & 0x3ff; | |
318 | wptr &= 0x3ff; | |
319 | ||
320 | if (txc > MEN_Z135_FIFO_WATERMARK) | |
321 | txc = MEN_Z135_FIFO_WATERMARK; | |
322 | ||
323 | txfree = MEN_Z135_FIFO_WATERMARK - txc; | |
324 | if (txfree <= 0) { | |
325 | pr_err("Not enough room in TX FIFO have %d, need %d\n", | |
326 | txfree, qlen); | |
327 | goto irq_en; | |
328 | } | |
329 | ||
330 | /* if we're not aligned, it's better to copy only 1 or 2 bytes and | |
331 | * then the rest. | |
332 | */ | |
333 | if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr)) | |
334 | n = 4 - BYTES_TO_ALIGN(wptr); | |
335 | else if (qlen > txfree) | |
336 | n = txfree; | |
337 | else | |
338 | n = qlen; | |
339 | ||
340 | if (n <= 0) | |
341 | goto irq_en; | |
342 | ||
343 | head = xmit->head & (UART_XMIT_SIZE - 1); | |
344 | tail = xmit->tail & (UART_XMIT_SIZE - 1); | |
345 | ||
346 | s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail; | |
347 | n = min(n, s); | |
348 | ||
349 | memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n); | |
350 | xmit->tail = (xmit->tail + n) & (UART_XMIT_SIZE - 1); | |
351 | mmiowb(); | |
352 | ||
353 | iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL); | |
354 | ||
355 | port->icount.tx += n; | |
356 | ||
a9977620 JT |
357 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
358 | uart_write_wakeup(port); | |
359 | ||
e264ebf4 JT |
360 | irq_en: |
361 | if (!uart_circ_empty(xmit)) | |
362 | men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN); | |
363 | else | |
364 | men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN); | |
365 | ||
366 | out: | |
367 | return; | |
368 | ||
369 | } | |
370 | ||
371 | /** | |
372 | * men_z135_intr() - Handle legacy IRQs | |
373 | * @irq: The IRQ number | |
374 | * @data: Pointer to UART port | |
375 | * | |
376 | * Check IIR register to see which tasklet to start. | |
377 | */ | |
378 | static irqreturn_t men_z135_intr(int irq, void *data) | |
379 | { | |
380 | struct men_z135_port *uart = (struct men_z135_port *)data; | |
381 | struct uart_port *port = &uart->port; | |
382 | int irq_id; | |
383 | ||
384 | uart->stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG); | |
385 | /* IRQ pending is low active */ | |
386 | if (IS_IRQ(uart->stat_reg)) | |
387 | return IRQ_NONE; | |
388 | ||
389 | irq_id = IRQ_ID(uart->stat_reg); | |
390 | switch (irq_id) { | |
391 | case MEN_Z135_IRQ_ID_MST: | |
392 | men_z135_handle_modem_status(uart); | |
393 | break; | |
394 | case MEN_Z135_IRQ_ID_TSA: | |
395 | men_z135_handle_tx(uart); | |
396 | break; | |
397 | case MEN_Z135_IRQ_ID_CTI: | |
398 | dev_dbg(&uart->mdev->dev, "Character Timeout Indication\n"); | |
399 | /* Fallthrough */ | |
400 | case MEN_Z135_IRQ_ID_RDA: | |
401 | /* Reading data clears RX IRQ */ | |
402 | men_z135_handle_rx(uart); | |
403 | break; | |
404 | case MEN_Z135_IRQ_ID_RLS: | |
405 | men_z135_handle_lsr(uart); | |
406 | break; | |
407 | default: | |
408 | dev_warn(&uart->mdev->dev, "Unknown IRQ id %d\n", irq_id); | |
409 | return IRQ_NONE; | |
410 | } | |
411 | ||
412 | return IRQ_HANDLED; | |
413 | } | |
414 | ||
415 | /** | |
416 | * men_z135_request_irq() - Request IRQ for 16z135 core | |
417 | * @uart: z135 private uart port structure | |
418 | * | |
419 | * Request an IRQ for 16z135 to use. First try using MSI, if it fails | |
420 | * fall back to using legacy interrupts. | |
421 | */ | |
422 | static int men_z135_request_irq(struct men_z135_port *uart) | |
423 | { | |
424 | struct device *dev = &uart->mdev->dev; | |
425 | struct uart_port *port = &uart->port; | |
426 | int err = 0; | |
427 | ||
428 | err = request_irq(port->irq, men_z135_intr, IRQF_SHARED, | |
429 | "men_z135_intr", uart); | |
430 | if (err) | |
431 | dev_err(dev, "Error %d getting interrupt\n", err); | |
432 | ||
433 | return err; | |
434 | } | |
435 | ||
436 | /** | |
437 | * men_z135_tx_empty() - Handle tx_empty call | |
438 | * @port: The UART port | |
439 | * | |
440 | * This function tests whether the TX FIFO and shifter for the port | |
441 | * described by @port is empty. | |
442 | */ | |
443 | static unsigned int men_z135_tx_empty(struct uart_port *port) | |
444 | { | |
445 | u32 wptr; | |
446 | u16 txc; | |
447 | ||
448 | wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); | |
449 | txc = (wptr >> 16) & 0x3ff; | |
450 | ||
451 | if (txc == 0) | |
452 | return TIOCSER_TEMT; | |
453 | else | |
454 | return 0; | |
455 | } | |
456 | ||
457 | /** | |
458 | * men_z135_set_mctrl() - Set modem control lines | |
459 | * @port: The UART port | |
460 | * @mctrl: The modem control lines | |
461 | * | |
462 | * This function sets the modem control lines for a port described by @port | |
463 | * to the state described by @mctrl | |
464 | */ | |
465 | static void men_z135_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
466 | { | |
467 | struct men_z135_port *uart = to_men_z135(port); | |
468 | u32 conf_reg = 0; | |
469 | ||
470 | if (mctrl & TIOCM_RTS) | |
471 | conf_reg |= MEN_Z135_MCR_RTS; | |
472 | if (mctrl & TIOCM_DTR) | |
473 | conf_reg |= MEN_Z135_MCR_DTR; | |
474 | if (mctrl & TIOCM_OUT1) | |
475 | conf_reg |= MEN_Z135_MCR_OUT1; | |
476 | if (mctrl & TIOCM_OUT2) | |
477 | conf_reg |= MEN_Z135_MCR_OUT2; | |
478 | if (mctrl & TIOCM_LOOP) | |
479 | conf_reg |= MEN_Z135_MCR_LOOP; | |
480 | ||
481 | men_z135_reg_set(uart, MEN_Z135_CONF_REG, conf_reg); | |
482 | } | |
483 | ||
484 | /** | |
485 | * men_z135_get_mctrl() - Get modem control lines | |
486 | * @port: The UART port | |
487 | * | |
488 | * Retruns the current state of modem control inputs. | |
489 | */ | |
490 | static unsigned int men_z135_get_mctrl(struct uart_port *port) | |
491 | { | |
492 | unsigned int mctrl = 0; | |
493 | u32 stat_reg; | |
494 | u8 msr; | |
495 | ||
496 | stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG); | |
497 | ||
498 | msr = ~((stat_reg >> 8) & 0xff); | |
499 | ||
500 | if (msr & MEN_Z135_MSR_CTS) | |
501 | mctrl |= TIOCM_CTS; | |
502 | if (msr & MEN_Z135_MSR_DSR) | |
503 | mctrl |= TIOCM_DSR; | |
504 | if (msr & MEN_Z135_MSR_RI) | |
505 | mctrl |= TIOCM_RI; | |
506 | if (msr & MEN_Z135_MSR_DCD) | |
507 | mctrl |= TIOCM_CAR; | |
508 | ||
509 | return mctrl; | |
510 | } | |
511 | ||
512 | /** | |
513 | * men_z135_stop_tx() - Stop transmitting characters | |
514 | * @port: The UART port | |
515 | * | |
516 | * Stop transmitting characters. This might be due to CTS line becomming | |
517 | * inactive or the tty layer indicating we want to stop transmission due to | |
518 | * an XOFF character. | |
519 | */ | |
520 | static void men_z135_stop_tx(struct uart_port *port) | |
521 | { | |
522 | struct men_z135_port *uart = to_men_z135(port); | |
523 | ||
524 | men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN); | |
525 | } | |
526 | ||
527 | /** | |
528 | * men_z135_start_tx() - Start transmitting characters | |
529 | * @port: The UART port | |
530 | * | |
531 | * Start transmitting character. This actually doesn't transmit anything, but | |
532 | * fires off the TX tasklet. | |
533 | */ | |
534 | static void men_z135_start_tx(struct uart_port *port) | |
535 | { | |
536 | struct men_z135_port *uart = to_men_z135(port); | |
537 | ||
538 | men_z135_handle_tx(uart); | |
539 | } | |
540 | ||
541 | /** | |
542 | * men_z135_stop_rx() - Stop receiving characters | |
543 | * @port: The UART port | |
544 | * | |
545 | * Stop receiving characters; the port is in the process of being closed. | |
546 | */ | |
547 | static void men_z135_stop_rx(struct uart_port *port) | |
548 | { | |
549 | struct men_z135_port *uart = to_men_z135(port); | |
550 | ||
551 | men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_RXCIEN); | |
552 | } | |
553 | ||
554 | /** | |
555 | * men_z135_enable_ms() - Enable Modem Status | |
556 | * port: | |
557 | * | |
558 | * Enable Modem Status IRQ. | |
559 | */ | |
560 | static void men_z135_enable_ms(struct uart_port *port) | |
561 | { | |
562 | struct men_z135_port *uart = to_men_z135(port); | |
563 | ||
564 | men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN); | |
565 | } | |
566 | ||
567 | static int men_z135_startup(struct uart_port *port) | |
568 | { | |
569 | struct men_z135_port *uart = to_men_z135(port); | |
570 | int err; | |
571 | u32 conf_reg = 0; | |
572 | ||
573 | err = men_z135_request_irq(uart); | |
574 | if (err) | |
575 | return -ENODEV; | |
576 | ||
577 | conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG); | |
578 | ||
10389e66 JT |
579 | /* Activate all but TX space available IRQ */ |
580 | conf_reg |= MEN_Z135_ALL_IRQS & ~MEN_Z135_IER_TXCIEN; | |
e264ebf4 JT |
581 | conf_reg &= ~(0xff << 16); |
582 | conf_reg |= (txlvl << 16); | |
583 | conf_reg |= (rxlvl << 20); | |
584 | ||
585 | iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static void men_z135_shutdown(struct uart_port *port) | |
591 | { | |
592 | struct men_z135_port *uart = to_men_z135(port); | |
593 | u32 conf_reg = 0; | |
594 | ||
595 | conf_reg |= MEN_Z135_ALL_IRQS; | |
596 | ||
597 | men_z135_reg_clr(uart, MEN_Z135_CONF_REG, conf_reg); | |
598 | ||
599 | free_irq(uart->port.irq, uart); | |
600 | } | |
601 | ||
602 | static void men_z135_set_termios(struct uart_port *port, | |
603 | struct ktermios *termios, | |
604 | struct ktermios *old) | |
605 | { | |
606 | unsigned int baud; | |
607 | u32 conf_reg; | |
608 | u32 bd_reg; | |
609 | u32 uart_freq; | |
610 | u8 lcr; | |
611 | ||
612 | conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG); | |
613 | lcr = LCR(conf_reg); | |
614 | ||
615 | /* byte size */ | |
616 | switch (termios->c_cflag & CSIZE) { | |
617 | case CS5: | |
618 | lcr |= MEN_Z135_WL5; | |
619 | break; | |
620 | case CS6: | |
621 | lcr |= MEN_Z135_WL6; | |
622 | break; | |
623 | case CS7: | |
624 | lcr |= MEN_Z135_WL7; | |
625 | break; | |
626 | case CS8: | |
627 | lcr |= MEN_Z135_WL8; | |
628 | break; | |
629 | } | |
630 | ||
631 | /* stop bits */ | |
632 | if (termios->c_cflag & CSTOPB) | |
633 | lcr |= MEN_Z135_NSTB2 << MEN_Z135_STB_SHIFT; | |
634 | ||
635 | /* parity */ | |
636 | if (termios->c_cflag & PARENB) { | |
637 | lcr |= MEN_Z135_PAR_ENA << MEN_Z135_PEN_SHIFT; | |
638 | ||
639 | if (termios->c_cflag & PARODD) | |
640 | lcr |= MEN_Z135_PTY_ODD << MEN_Z135_PTY_SHIFT; | |
641 | else | |
642 | lcr |= MEN_Z135_PTY_EVN << MEN_Z135_PTY_SHIFT; | |
643 | } else | |
644 | lcr |= MEN_Z135_PAR_DIS << MEN_Z135_PEN_SHIFT; | |
645 | ||
646 | termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ | |
647 | ||
648 | conf_reg |= lcr << MEN_Z135_LCR_SHIFT; | |
649 | iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); | |
650 | ||
651 | uart_freq = ioread32(port->membase + MEN_Z135_UART_FREQ); | |
652 | if (uart_freq == 0) | |
653 | uart_freq = MEN_Z135_BASECLK; | |
654 | ||
655 | baud = uart_get_baud_rate(port, termios, old, 0, uart_freq / 16); | |
656 | ||
657 | spin_lock(&port->lock); | |
658 | if (tty_termios_baud_rate(termios)) | |
659 | tty_termios_encode_baud_rate(termios, baud, baud); | |
660 | ||
661 | bd_reg = uart_freq / (4 * baud); | |
662 | iowrite32(bd_reg, port->membase + MEN_Z135_BAUD_REG); | |
663 | ||
664 | uart_update_timeout(port, termios->c_cflag, baud); | |
665 | spin_unlock(&port->lock); | |
666 | } | |
667 | ||
668 | static const char *men_z135_type(struct uart_port *port) | |
669 | { | |
670 | return KBUILD_MODNAME; | |
671 | } | |
672 | ||
673 | static void men_z135_release_port(struct uart_port *port) | |
674 | { | |
675 | iounmap(port->membase); | |
676 | port->membase = NULL; | |
677 | ||
678 | release_mem_region(port->mapbase, MEN_Z135_MEM_SIZE); | |
679 | } | |
680 | ||
681 | static int men_z135_request_port(struct uart_port *port) | |
682 | { | |
683 | int size = MEN_Z135_MEM_SIZE; | |
684 | ||
685 | if (!request_mem_region(port->mapbase, size, "men_z135_port")) | |
686 | return -EBUSY; | |
687 | ||
688 | port->membase = ioremap(port->mapbase, MEN_Z135_MEM_SIZE); | |
689 | if (port->membase == NULL) { | |
690 | release_mem_region(port->mapbase, MEN_Z135_MEM_SIZE); | |
691 | return -ENOMEM; | |
692 | } | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
697 | static void men_z135_config_port(struct uart_port *port, int type) | |
698 | { | |
699 | port->type = PORT_MEN_Z135; | |
700 | men_z135_request_port(port); | |
701 | } | |
702 | ||
703 | static int men_z135_verify_port(struct uart_port *port, | |
704 | struct serial_struct *serinfo) | |
705 | { | |
706 | return -EINVAL; | |
707 | } | |
708 | ||
709 | static struct uart_ops men_z135_ops = { | |
710 | .tx_empty = men_z135_tx_empty, | |
711 | .set_mctrl = men_z135_set_mctrl, | |
712 | .get_mctrl = men_z135_get_mctrl, | |
713 | .stop_tx = men_z135_stop_tx, | |
714 | .start_tx = men_z135_start_tx, | |
715 | .stop_rx = men_z135_stop_rx, | |
716 | .enable_ms = men_z135_enable_ms, | |
717 | .startup = men_z135_startup, | |
718 | .shutdown = men_z135_shutdown, | |
719 | .set_termios = men_z135_set_termios, | |
720 | .type = men_z135_type, | |
721 | .release_port = men_z135_release_port, | |
722 | .request_port = men_z135_request_port, | |
723 | .config_port = men_z135_config_port, | |
724 | .verify_port = men_z135_verify_port, | |
725 | }; | |
726 | ||
727 | static struct uart_driver men_z135_driver = { | |
728 | .owner = THIS_MODULE, | |
729 | .driver_name = KBUILD_MODNAME, | |
730 | .dev_name = "ttyHSU", | |
731 | .major = 0, | |
732 | .minor = 0, | |
733 | .nr = MEN_Z135_MAX_PORTS, | |
734 | }; | |
735 | ||
736 | /** | |
737 | * men_z135_probe() - Probe a z135 instance | |
738 | * @mdev: The MCB device | |
739 | * @id: The MCB device ID | |
740 | * | |
741 | * men_z135_probe does the basic setup of hardware resources and registers the | |
742 | * new uart port to the tty layer. | |
743 | */ | |
744 | static int men_z135_probe(struct mcb_device *mdev, | |
745 | const struct mcb_device_id *id) | |
746 | { | |
747 | struct men_z135_port *uart; | |
748 | struct resource *mem; | |
749 | struct device *dev; | |
750 | int err; | |
751 | ||
752 | dev = &mdev->dev; | |
753 | ||
754 | uart = devm_kzalloc(dev, sizeof(struct men_z135_port), GFP_KERNEL); | |
755 | if (!uart) | |
756 | return -ENOMEM; | |
757 | ||
758 | uart->rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); | |
759 | if (!uart->rxbuf) | |
760 | return -ENOMEM; | |
761 | ||
762 | mem = &mdev->mem; | |
763 | ||
764 | mcb_set_drvdata(mdev, uart); | |
765 | ||
766 | uart->port.uartclk = MEN_Z135_BASECLK * 16; | |
767 | uart->port.fifosize = MEN_Z135_FIFO_SIZE; | |
768 | uart->port.iotype = UPIO_MEM; | |
769 | uart->port.ops = &men_z135_ops; | |
770 | uart->port.irq = mcb_get_irq(mdev); | |
771 | uart->port.iotype = UPIO_MEM; | |
772 | uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; | |
773 | uart->port.line = line++; | |
774 | uart->port.dev = dev; | |
775 | uart->port.type = PORT_MEN_Z135; | |
776 | uart->port.mapbase = mem->start; | |
777 | uart->port.membase = NULL; | |
778 | uart->mdev = mdev; | |
779 | ||
780 | spin_lock_init(&uart->port.lock); | |
781 | spin_lock_init(&uart->lock); | |
782 | ||
783 | err = uart_add_one_port(&men_z135_driver, &uart->port); | |
784 | if (err) | |
785 | goto err; | |
786 | ||
787 | return 0; | |
788 | ||
789 | err: | |
790 | free_page((unsigned long) uart->rxbuf); | |
791 | dev_err(dev, "Failed to add UART: %d\n", err); | |
792 | ||
793 | return err; | |
794 | } | |
795 | ||
796 | /** | |
797 | * men_z135_remove() - Remove a z135 instance from the system | |
798 | * | |
799 | * @mdev: The MCB device | |
800 | */ | |
801 | static void men_z135_remove(struct mcb_device *mdev) | |
802 | { | |
803 | struct men_z135_port *uart = mcb_get_drvdata(mdev); | |
804 | ||
805 | line--; | |
806 | uart_remove_one_port(&men_z135_driver, &uart->port); | |
807 | free_page((unsigned long) uart->rxbuf); | |
808 | } | |
809 | ||
810 | static const struct mcb_device_id men_z135_ids[] = { | |
811 | { .device = 0x87 }, | |
812 | }; | |
813 | MODULE_DEVICE_TABLE(mcb, men_z135_ids); | |
814 | ||
815 | static struct mcb_driver mcb_driver = { | |
816 | .driver = { | |
817 | .name = "z135-uart", | |
818 | .owner = THIS_MODULE, | |
819 | }, | |
820 | .probe = men_z135_probe, | |
821 | .remove = men_z135_remove, | |
822 | .id_table = men_z135_ids, | |
823 | }; | |
824 | ||
825 | /** | |
826 | * men_z135_init() - Driver Registration Routine | |
827 | * | |
828 | * men_z135_init is the first routine called when the driver is loaded. All it | |
829 | * does is register with the legacy MEN Chameleon subsystem. | |
830 | */ | |
831 | static int __init men_z135_init(void) | |
832 | { | |
833 | int err; | |
834 | ||
835 | err = uart_register_driver(&men_z135_driver); | |
836 | if (err) { | |
837 | pr_err("Failed to register UART: %d\n", err); | |
838 | return err; | |
839 | } | |
840 | ||
841 | err = mcb_register_driver(&mcb_driver); | |
842 | if (err) { | |
843 | pr_err("Failed to register MCB driver: %d\n", err); | |
844 | uart_unregister_driver(&men_z135_driver); | |
845 | return err; | |
846 | } | |
847 | ||
848 | return 0; | |
849 | } | |
850 | module_init(men_z135_init); | |
851 | ||
852 | /** | |
853 | * men_z135_exit() - Driver Exit Routine | |
854 | * | |
855 | * men_z135_exit is called just before the driver is removed from memory. | |
856 | */ | |
857 | static void __exit men_z135_exit(void) | |
858 | { | |
859 | mcb_unregister_driver(&mcb_driver); | |
860 | uart_unregister_driver(&men_z135_driver); | |
861 | } | |
862 | module_exit(men_z135_exit); | |
863 | ||
864 | MODULE_AUTHOR("Johannes Thumshirn <johannes.thumshirn@men.de>"); | |
865 | MODULE_LICENSE("GPL v2"); | |
866 | MODULE_DESCRIPTION("MEN 16z135 High Speed UART"); | |
867 | MODULE_ALIAS("mcb:16z135"); |