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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
1da177e4 LT |
3 | * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs. |
4 | * | |
5 | * FIXME According to the usermanual the status bits in the status register | |
6 | * are only updated when the peripherals access the FIFO and not when the | |
7 | * CPU access them. So since we use this bits to know when we stop writing | |
8 | * and reading, they may not be updated in-time and a race condition may | |
9 | * exists. But I haven't be able to prove this and I don't care. But if | |
10 | * any problem arises, it might worth checking. The TX/RX FIFO Stats | |
11 | * registers should be used in addition. | |
12 | * Update: Actually, they seem updated ... At least the bits we use. | |
13 | * | |
14 | * | |
15 | * Maintainer : Sylvain Munaut <tnt@246tNt.com> | |
9b9129e7 | 16 | * |
1da177e4 LT |
17 | * Some of the code has been inspired/copied from the 2.4 code written |
18 | * by Dale Farnsworth <dfarnsworth@mvista.com>. | |
9b9129e7 | 19 | * |
25ae3a07 JR |
20 | * Copyright (C) 2008 Freescale Semiconductor Inc. |
21 | * John Rigby <jrigby@gmail.com> | |
22 | * Added support for MPC5121 | |
b9272dfd GL |
23 | * Copyright (C) 2006 Secret Lab Technologies Ltd. |
24 | * Grant Likely <grant.likely@secretlab.ca> | |
25 | * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com> | |
1da177e4 | 26 | * Copyright (C) 2003 MontaVista, Software, Inc. |
1da177e4 | 27 | */ |
9b9129e7 | 28 | |
b9272dfd GL |
29 | #undef DEBUG |
30 | ||
31 | #include <linux/device.h> | |
1da177e4 LT |
32 | #include <linux/module.h> |
33 | #include <linux/tty.h> | |
ee160a38 | 34 | #include <linux/tty_flip.h> |
1da177e4 LT |
35 | #include <linux/serial.h> |
36 | #include <linux/sysrq.h> | |
37 | #include <linux/console.h> | |
406b7d4f JR |
38 | #include <linux/delay.h> |
39 | #include <linux/io.h> | |
283029d1 GL |
40 | #include <linux/of.h> |
41 | #include <linux/of_platform.h> | |
6acc6833 | 42 | #include <linux/clk.h> |
b9272dfd | 43 | |
1da177e4 LT |
44 | #include <asm/mpc52xx.h> |
45 | #include <asm/mpc52xx_psc.h> | |
46 | ||
1da177e4 LT |
47 | #include <linux/serial_core.h> |
48 | ||
49 | ||
d62de3aa SM |
50 | /* We've been assigned a range on the "Low-density serial ports" major */ |
51 | #define SERIAL_PSC_MAJOR 204 | |
52 | #define SERIAL_PSC_MINOR 148 | |
53 | ||
1da177e4 LT |
54 | |
55 | #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */ | |
56 | ||
57 | ||
58 | static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM]; | |
59 | /* Rem: - We use the read_status_mask as a shadow of | |
60 | * psc->mpc52xx_psc_imr | |
61 | * - It's important that is array is all zero on start as we | |
62 | * use it to know if it's initialized or not ! If it's not sure | |
63 | * it's cleared, then a memset(...,0,...) should be added to | |
64 | * the console_init | |
65 | */ | |
8d1fb8cb | 66 | |
b9272dfd GL |
67 | /* lookup table for matching device nodes to index numbers */ |
68 | static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM]; | |
69 | ||
70 | static void mpc52xx_uart_of_enumerate(void); | |
1da177e4 | 71 | |
599f030c | 72 | |
1da177e4 LT |
73 | #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) |
74 | ||
75 | ||
76 | /* Forward declaration of the interruption handling routine */ | |
406b7d4f | 77 | static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id); |
6acc6833 | 78 | static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port); |
1da177e4 | 79 | |
599f030c JR |
80 | /* ======================================================================== */ |
81 | /* PSC fifo operations for isolating differences between 52xx and 512x */ | |
82 | /* ======================================================================== */ | |
83 | ||
84 | struct psc_ops { | |
85 | void (*fifo_init)(struct uart_port *port); | |
86 | int (*raw_rx_rdy)(struct uart_port *port); | |
87 | int (*raw_tx_rdy)(struct uart_port *port); | |
88 | int (*rx_rdy)(struct uart_port *port); | |
89 | int (*tx_rdy)(struct uart_port *port); | |
90 | int (*tx_empty)(struct uart_port *port); | |
91 | void (*stop_rx)(struct uart_port *port); | |
92 | void (*start_tx)(struct uart_port *port); | |
93 | void (*stop_tx)(struct uart_port *port); | |
94 | void (*rx_clr_irq)(struct uart_port *port); | |
95 | void (*tx_clr_irq)(struct uart_port *port); | |
96 | void (*write_char)(struct uart_port *port, unsigned char c); | |
97 | unsigned char (*read_char)(struct uart_port *port); | |
98 | void (*cw_disable_ints)(struct uart_port *port); | |
99 | void (*cw_restore_ints)(struct uart_port *port); | |
0d1f22e4 AD |
100 | unsigned int (*set_baudrate)(struct uart_port *port, |
101 | struct ktermios *new, | |
102 | struct ktermios *old); | |
2d30ccac GS |
103 | int (*clock_alloc)(struct uart_port *port); |
104 | void (*clock_relse)(struct uart_port *port); | |
6acc6833 AG |
105 | int (*clock)(struct uart_port *port, int enable); |
106 | int (*fifoc_init)(void); | |
107 | void (*fifoc_uninit)(void); | |
108 | void (*get_irq)(struct uart_port *, struct device_node *); | |
109 | irqreturn_t (*handle_irq)(struct uart_port *port); | |
2574b27e MF |
110 | u16 (*get_status)(struct uart_port *port); |
111 | u8 (*get_ipcr)(struct uart_port *port); | |
112 | void (*command)(struct uart_port *port, u8 cmd); | |
113 | void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2); | |
114 | void (*set_rts)(struct uart_port *port, int state); | |
115 | void (*enable_ms)(struct uart_port *port); | |
116 | void (*set_sicr)(struct uart_port *port, u32 val); | |
117 | void (*set_imr)(struct uart_port *port, u16 val); | |
118 | u8 (*get_mr1)(struct uart_port *port); | |
599f030c JR |
119 | }; |
120 | ||
0d1f22e4 AD |
121 | /* setting the prescaler and divisor reg is common for all chips */ |
122 | static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc, | |
123 | u16 prescaler, unsigned int divisor) | |
124 | { | |
125 | /* select prescaler */ | |
126 | out_be16(&psc->mpc52xx_psc_clock_select, prescaler); | |
127 | out_8(&psc->ctur, divisor >> 8); | |
128 | out_8(&psc->ctlr, divisor & 0xff); | |
129 | } | |
130 | ||
2574b27e MF |
131 | static u16 mpc52xx_psc_get_status(struct uart_port *port) |
132 | { | |
133 | return in_be16(&PSC(port)->mpc52xx_psc_status); | |
134 | } | |
135 | ||
136 | static u8 mpc52xx_psc_get_ipcr(struct uart_port *port) | |
137 | { | |
138 | return in_8(&PSC(port)->mpc52xx_psc_ipcr); | |
139 | } | |
140 | ||
141 | static void mpc52xx_psc_command(struct uart_port *port, u8 cmd) | |
142 | { | |
143 | out_8(&PSC(port)->command, cmd); | |
144 | } | |
145 | ||
146 | static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) | |
147 | { | |
148 | out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); | |
149 | out_8(&PSC(port)->mode, mr1); | |
150 | out_8(&PSC(port)->mode, mr2); | |
151 | } | |
152 | ||
153 | static void mpc52xx_psc_set_rts(struct uart_port *port, int state) | |
154 | { | |
155 | if (state) | |
156 | out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); | |
157 | else | |
158 | out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS); | |
159 | } | |
160 | ||
161 | static void mpc52xx_psc_enable_ms(struct uart_port *port) | |
162 | { | |
163 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
164 | ||
165 | /* clear D_*-bits by reading them */ | |
166 | in_8(&psc->mpc52xx_psc_ipcr); | |
167 | /* enable CTS and DCD as IPC interrupts */ | |
168 | out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); | |
169 | ||
170 | port->read_status_mask |= MPC52xx_PSC_IMR_IPC; | |
171 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); | |
172 | } | |
173 | ||
174 | static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val) | |
175 | { | |
176 | out_be32(&PSC(port)->sicr, val); | |
177 | } | |
178 | ||
179 | static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val) | |
180 | { | |
181 | out_be16(&PSC(port)->mpc52xx_psc_imr, val); | |
182 | } | |
183 | ||
184 | static u8 mpc52xx_psc_get_mr1(struct uart_port *port) | |
185 | { | |
186 | out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1); | |
187 | return in_8(&PSC(port)->mode); | |
188 | } | |
189 | ||
25ae3a07 | 190 | #ifdef CONFIG_PPC_MPC52xx |
599f030c JR |
191 | #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) |
192 | static void mpc52xx_psc_fifo_init(struct uart_port *port) | |
193 | { | |
194 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
195 | struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port); | |
196 | ||
599f030c JR |
197 | out_8(&fifo->rfcntl, 0x00); |
198 | out_be16(&fifo->rfalarm, 0x1ff); | |
199 | out_8(&fifo->tfcntl, 0x07); | |
200 | out_be16(&fifo->tfalarm, 0x80); | |
201 | ||
202 | port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; | |
203 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); | |
204 | } | |
205 | ||
206 | static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port) | |
207 | { | |
208 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
209 | & MPC52xx_PSC_SR_RXRDY; | |
210 | } | |
211 | ||
212 | static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port) | |
213 | { | |
214 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
215 | & MPC52xx_PSC_SR_TXRDY; | |
216 | } | |
217 | ||
218 | ||
219 | static int mpc52xx_psc_rx_rdy(struct uart_port *port) | |
220 | { | |
221 | return in_be16(&PSC(port)->mpc52xx_psc_isr) | |
222 | & port->read_status_mask | |
223 | & MPC52xx_PSC_IMR_RXRDY; | |
224 | } | |
225 | ||
226 | static int mpc52xx_psc_tx_rdy(struct uart_port *port) | |
227 | { | |
228 | return in_be16(&PSC(port)->mpc52xx_psc_isr) | |
229 | & port->read_status_mask | |
230 | & MPC52xx_PSC_IMR_TXRDY; | |
231 | } | |
232 | ||
233 | static int mpc52xx_psc_tx_empty(struct uart_port *port) | |
234 | { | |
7d07ada0 UKK |
235 | u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status); |
236 | ||
237 | return (sts & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0; | |
599f030c JR |
238 | } |
239 | ||
240 | static void mpc52xx_psc_start_tx(struct uart_port *port) | |
241 | { | |
242 | port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; | |
243 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
244 | } | |
245 | ||
246 | static void mpc52xx_psc_stop_tx(struct uart_port *port) | |
247 | { | |
248 | port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; | |
249 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
250 | } | |
251 | ||
252 | static void mpc52xx_psc_stop_rx(struct uart_port *port) | |
253 | { | |
254 | port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; | |
255 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
256 | } | |
257 | ||
258 | static void mpc52xx_psc_rx_clr_irq(struct uart_port *port) | |
259 | { | |
260 | } | |
261 | ||
262 | static void mpc52xx_psc_tx_clr_irq(struct uart_port *port) | |
263 | { | |
264 | } | |
265 | ||
266 | static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c) | |
267 | { | |
268 | out_8(&PSC(port)->mpc52xx_psc_buffer_8, c); | |
269 | } | |
270 | ||
271 | static unsigned char mpc52xx_psc_read_char(struct uart_port *port) | |
272 | { | |
273 | return in_8(&PSC(port)->mpc52xx_psc_buffer_8); | |
274 | } | |
275 | ||
276 | static void mpc52xx_psc_cw_disable_ints(struct uart_port *port) | |
277 | { | |
278 | out_be16(&PSC(port)->mpc52xx_psc_imr, 0); | |
279 | } | |
280 | ||
281 | static void mpc52xx_psc_cw_restore_ints(struct uart_port *port) | |
282 | { | |
283 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
284 | } | |
285 | ||
0d1f22e4 AD |
286 | static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port, |
287 | struct ktermios *new, | |
288 | struct ktermios *old) | |
599f030c | 289 | { |
0d1f22e4 AD |
290 | unsigned int baud; |
291 | unsigned int divisor; | |
292 | ||
293 | /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */ | |
294 | baud = uart_get_baud_rate(port, new, old, | |
295 | port->uartclk / (32 * 0xffff) + 1, | |
296 | port->uartclk / 32); | |
297 | divisor = (port->uartclk + 16 * baud) / (32 * baud); | |
298 | ||
299 | /* enable the /32 prescaler and set the divisor */ | |
300 | mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); | |
301 | return baud; | |
302 | } | |
303 | ||
304 | static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port, | |
305 | struct ktermios *new, | |
306 | struct ktermios *old) | |
307 | { | |
308 | unsigned int baud; | |
309 | unsigned int divisor; | |
310 | u16 prescaler; | |
311 | ||
312 | /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the | |
313 | * ipb freq */ | |
314 | baud = uart_get_baud_rate(port, new, old, | |
315 | port->uartclk / (32 * 0xffff) + 1, | |
316 | port->uartclk / 4); | |
317 | divisor = (port->uartclk + 2 * baud) / (4 * baud); | |
318 | ||
e0955ace FB |
319 | /* select the proper prescaler and set the divisor |
320 | * prefer high prescaler for more tolerance on low baudrates */ | |
321 | if (divisor > 0xffff || baud <= 115200) { | |
0d1f22e4 AD |
322 | divisor = (divisor + 4) / 8; |
323 | prescaler = 0xdd00; /* /32 */ | |
324 | } else | |
325 | prescaler = 0xff00; /* /4 */ | |
326 | mpc52xx_set_divisor(PSC(port), prescaler, divisor); | |
327 | return baud; | |
599f030c JR |
328 | } |
329 | ||
6acc6833 AG |
330 | static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np) |
331 | { | |
9cfb5c05 | 332 | port->irqflags = 0; |
6acc6833 AG |
333 | port->irq = irq_of_parse_and_map(np, 0); |
334 | } | |
335 | ||
336 | /* 52xx specific interrupt handler. The caller holds the port lock */ | |
337 | static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port) | |
338 | { | |
339 | return mpc5xxx_uart_process_int(port); | |
340 | } | |
341 | ||
cc74bd1d | 342 | static const struct psc_ops mpc52xx_psc_ops = { |
599f030c JR |
343 | .fifo_init = mpc52xx_psc_fifo_init, |
344 | .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, | |
345 | .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, | |
346 | .rx_rdy = mpc52xx_psc_rx_rdy, | |
347 | .tx_rdy = mpc52xx_psc_tx_rdy, | |
348 | .tx_empty = mpc52xx_psc_tx_empty, | |
349 | .stop_rx = mpc52xx_psc_stop_rx, | |
350 | .start_tx = mpc52xx_psc_start_tx, | |
351 | .stop_tx = mpc52xx_psc_stop_tx, | |
352 | .rx_clr_irq = mpc52xx_psc_rx_clr_irq, | |
353 | .tx_clr_irq = mpc52xx_psc_tx_clr_irq, | |
354 | .write_char = mpc52xx_psc_write_char, | |
355 | .read_char = mpc52xx_psc_read_char, | |
356 | .cw_disable_ints = mpc52xx_psc_cw_disable_ints, | |
357 | .cw_restore_ints = mpc52xx_psc_cw_restore_ints, | |
0d1f22e4 AD |
358 | .set_baudrate = mpc5200_psc_set_baudrate, |
359 | .get_irq = mpc52xx_psc_get_irq, | |
360 | .handle_irq = mpc52xx_psc_handle_irq, | |
2574b27e MF |
361 | .get_status = mpc52xx_psc_get_status, |
362 | .get_ipcr = mpc52xx_psc_get_ipcr, | |
363 | .command = mpc52xx_psc_command, | |
364 | .set_mode = mpc52xx_psc_set_mode, | |
365 | .set_rts = mpc52xx_psc_set_rts, | |
366 | .enable_ms = mpc52xx_psc_enable_ms, | |
367 | .set_sicr = mpc52xx_psc_set_sicr, | |
368 | .set_imr = mpc52xx_psc_set_imr, | |
369 | .get_mr1 = mpc52xx_psc_get_mr1, | |
0d1f22e4 AD |
370 | }; |
371 | ||
cc74bd1d | 372 | static const struct psc_ops mpc5200b_psc_ops = { |
0d1f22e4 AD |
373 | .fifo_init = mpc52xx_psc_fifo_init, |
374 | .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, | |
375 | .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, | |
376 | .rx_rdy = mpc52xx_psc_rx_rdy, | |
377 | .tx_rdy = mpc52xx_psc_tx_rdy, | |
378 | .tx_empty = mpc52xx_psc_tx_empty, | |
379 | .stop_rx = mpc52xx_psc_stop_rx, | |
380 | .start_tx = mpc52xx_psc_start_tx, | |
381 | .stop_tx = mpc52xx_psc_stop_tx, | |
382 | .rx_clr_irq = mpc52xx_psc_rx_clr_irq, | |
383 | .tx_clr_irq = mpc52xx_psc_tx_clr_irq, | |
384 | .write_char = mpc52xx_psc_write_char, | |
385 | .read_char = mpc52xx_psc_read_char, | |
386 | .cw_disable_ints = mpc52xx_psc_cw_disable_ints, | |
387 | .cw_restore_ints = mpc52xx_psc_cw_restore_ints, | |
388 | .set_baudrate = mpc5200b_psc_set_baudrate, | |
6acc6833 AG |
389 | .get_irq = mpc52xx_psc_get_irq, |
390 | .handle_irq = mpc52xx_psc_handle_irq, | |
2574b27e MF |
391 | .get_status = mpc52xx_psc_get_status, |
392 | .get_ipcr = mpc52xx_psc_get_ipcr, | |
393 | .command = mpc52xx_psc_command, | |
394 | .set_mode = mpc52xx_psc_set_mode, | |
395 | .set_rts = mpc52xx_psc_set_rts, | |
396 | .enable_ms = mpc52xx_psc_enable_ms, | |
397 | .set_sicr = mpc52xx_psc_set_sicr, | |
398 | .set_imr = mpc52xx_psc_set_imr, | |
399 | .get_mr1 = mpc52xx_psc_get_mr1, | |
599f030c JR |
400 | }; |
401 | ||
5b84c967 | 402 | #endif /* CONFIG_PPC_MPC52xx */ |
25ae3a07 JR |
403 | |
404 | #ifdef CONFIG_PPC_MPC512x | |
405 | #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1)) | |
6acc6833 AG |
406 | |
407 | /* PSC FIFO Controller for mpc512x */ | |
408 | struct psc_fifoc { | |
409 | u32 fifoc_cmd; | |
410 | u32 fifoc_int; | |
411 | u32 fifoc_dma; | |
412 | u32 fifoc_axe; | |
413 | u32 fifoc_debug; | |
414 | }; | |
415 | ||
416 | static struct psc_fifoc __iomem *psc_fifoc; | |
417 | static unsigned int psc_fifoc_irq; | |
cb1ea812 | 418 | static struct clk *psc_fifoc_clk; |
6acc6833 | 419 | |
25ae3a07 JR |
420 | static void mpc512x_psc_fifo_init(struct uart_port *port) |
421 | { | |
6acc6833 AG |
422 | /* /32 prescaler */ |
423 | out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00); | |
424 | ||
25ae3a07 JR |
425 | out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); |
426 | out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); | |
427 | out_be32(&FIFO_512x(port)->txalarm, 1); | |
428 | out_be32(&FIFO_512x(port)->tximr, 0); | |
429 | ||
430 | out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); | |
431 | out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); | |
432 | out_be32(&FIFO_512x(port)->rxalarm, 1); | |
433 | out_be32(&FIFO_512x(port)->rximr, 0); | |
434 | ||
435 | out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM); | |
436 | out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM); | |
437 | } | |
438 | ||
439 | static int mpc512x_psc_raw_rx_rdy(struct uart_port *port) | |
440 | { | |
441 | return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); | |
442 | } | |
443 | ||
444 | static int mpc512x_psc_raw_tx_rdy(struct uart_port *port) | |
445 | { | |
446 | return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL); | |
447 | } | |
448 | ||
449 | static int mpc512x_psc_rx_rdy(struct uart_port *port) | |
450 | { | |
451 | return in_be32(&FIFO_512x(port)->rxsr) | |
452 | & in_be32(&FIFO_512x(port)->rximr) | |
453 | & MPC512x_PSC_FIFO_ALARM; | |
454 | } | |
455 | ||
456 | static int mpc512x_psc_tx_rdy(struct uart_port *port) | |
457 | { | |
458 | return in_be32(&FIFO_512x(port)->txsr) | |
459 | & in_be32(&FIFO_512x(port)->tximr) | |
460 | & MPC512x_PSC_FIFO_ALARM; | |
461 | } | |
462 | ||
463 | static int mpc512x_psc_tx_empty(struct uart_port *port) | |
464 | { | |
465 | return in_be32(&FIFO_512x(port)->txsr) | |
466 | & MPC512x_PSC_FIFO_EMPTY; | |
467 | } | |
468 | ||
469 | static void mpc512x_psc_stop_rx(struct uart_port *port) | |
470 | { | |
471 | unsigned long rx_fifo_imr; | |
472 | ||
473 | rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr); | |
474 | rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; | |
475 | out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr); | |
476 | } | |
477 | ||
478 | static void mpc512x_psc_start_tx(struct uart_port *port) | |
479 | { | |
480 | unsigned long tx_fifo_imr; | |
481 | ||
482 | tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); | |
483 | tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; | |
484 | out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); | |
485 | } | |
486 | ||
487 | static void mpc512x_psc_stop_tx(struct uart_port *port) | |
488 | { | |
489 | unsigned long tx_fifo_imr; | |
490 | ||
491 | tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); | |
492 | tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; | |
493 | out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); | |
494 | } | |
495 | ||
496 | static void mpc512x_psc_rx_clr_irq(struct uart_port *port) | |
497 | { | |
498 | out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr)); | |
499 | } | |
500 | ||
501 | static void mpc512x_psc_tx_clr_irq(struct uart_port *port) | |
502 | { | |
503 | out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr)); | |
504 | } | |
505 | ||
506 | static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c) | |
507 | { | |
508 | out_8(&FIFO_512x(port)->txdata_8, c); | |
509 | } | |
510 | ||
511 | static unsigned char mpc512x_psc_read_char(struct uart_port *port) | |
512 | { | |
513 | return in_8(&FIFO_512x(port)->rxdata_8); | |
514 | } | |
515 | ||
516 | static void mpc512x_psc_cw_disable_ints(struct uart_port *port) | |
517 | { | |
518 | port->read_status_mask = | |
519 | in_be32(&FIFO_512x(port)->tximr) << 16 | | |
520 | in_be32(&FIFO_512x(port)->rximr); | |
521 | out_be32(&FIFO_512x(port)->tximr, 0); | |
522 | out_be32(&FIFO_512x(port)->rximr, 0); | |
523 | } | |
524 | ||
525 | static void mpc512x_psc_cw_restore_ints(struct uart_port *port) | |
526 | { | |
527 | out_be32(&FIFO_512x(port)->tximr, | |
528 | (port->read_status_mask >> 16) & 0x7f); | |
529 | out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f); | |
530 | } | |
531 | ||
0d1f22e4 AD |
532 | static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port, |
533 | struct ktermios *new, | |
534 | struct ktermios *old) | |
25ae3a07 | 535 | { |
0d1f22e4 AD |
536 | unsigned int baud; |
537 | unsigned int divisor; | |
538 | ||
539 | /* | |
540 | * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on | |
541 | * pg. 30-10 that the chip supports a /32 and a /10 prescaler. | |
542 | * Furthermore, it states that "After reset, the prescaler by 10 | |
543 | * for the UART mode is selected", but the reset register value is | |
544 | * 0x0000 which means a /32 prescaler. This is wrong. | |
545 | * | |
546 | * In reality using /32 prescaler doesn't work, as it is not supported! | |
547 | * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide", | |
548 | * Chapter 4.1 PSC in UART Mode. | |
549 | * Calculate with a /16 prescaler here. | |
550 | */ | |
551 | ||
552 | /* uartclk contains the ips freq */ | |
553 | baud = uart_get_baud_rate(port, new, old, | |
554 | port->uartclk / (16 * 0xffff) + 1, | |
555 | port->uartclk / 16); | |
556 | divisor = (port->uartclk + 8 * baud) / (16 * baud); | |
557 | ||
558 | /* enable the /16 prescaler and set the divisor */ | |
559 | mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); | |
560 | return baud; | |
25ae3a07 JR |
561 | } |
562 | ||
6acc6833 AG |
563 | /* Init PSC FIFO Controller */ |
564 | static int __init mpc512x_psc_fifoc_init(void) | |
565 | { | |
cb1ea812 | 566 | int err; |
6acc6833 | 567 | struct device_node *np; |
cb1ea812 GS |
568 | struct clk *clk; |
569 | ||
570 | /* default error code, potentially overwritten by clock calls */ | |
571 | err = -ENODEV; | |
6acc6833 AG |
572 | |
573 | np = of_find_compatible_node(NULL, NULL, | |
574 | "fsl,mpc5121-psc-fifo"); | |
575 | if (!np) { | |
576 | pr_err("%s: Can't find FIFOC node\n", __func__); | |
cb1ea812 GS |
577 | goto out_err; |
578 | } | |
579 | ||
580 | clk = of_clk_get(np, 0); | |
581 | if (IS_ERR(clk)) { | |
582 | /* backwards compat with device trees that lack clock specs */ | |
583 | clk = clk_get_sys(np->name, "ipg"); | |
6acc6833 | 584 | } |
cb1ea812 GS |
585 | if (IS_ERR(clk)) { |
586 | pr_err("%s: Can't lookup FIFO clock\n", __func__); | |
587 | err = PTR_ERR(clk); | |
588 | goto out_ofnode_put; | |
589 | } | |
590 | if (clk_prepare_enable(clk)) { | |
591 | pr_err("%s: Can't enable FIFO clock\n", __func__); | |
592 | clk_put(clk); | |
593 | goto out_ofnode_put; | |
594 | } | |
595 | psc_fifoc_clk = clk; | |
6acc6833 AG |
596 | |
597 | psc_fifoc = of_iomap(np, 0); | |
598 | if (!psc_fifoc) { | |
599 | pr_err("%s: Can't map FIFOC\n", __func__); | |
cb1ea812 | 600 | goto out_clk_disable; |
6acc6833 AG |
601 | } |
602 | ||
603 | psc_fifoc_irq = irq_of_parse_and_map(np, 0); | |
d4e33fac | 604 | if (psc_fifoc_irq == 0) { |
6acc6833 | 605 | pr_err("%s: Can't get FIFOC irq\n", __func__); |
cb1ea812 | 606 | goto out_unmap; |
6acc6833 AG |
607 | } |
608 | ||
cb1ea812 | 609 | of_node_put(np); |
6acc6833 | 610 | return 0; |
cb1ea812 GS |
611 | |
612 | out_unmap: | |
613 | iounmap(psc_fifoc); | |
614 | out_clk_disable: | |
615 | clk_disable_unprepare(psc_fifoc_clk); | |
616 | clk_put(psc_fifoc_clk); | |
617 | out_ofnode_put: | |
618 | of_node_put(np); | |
619 | out_err: | |
620 | return err; | |
6acc6833 AG |
621 | } |
622 | ||
623 | static void __exit mpc512x_psc_fifoc_uninit(void) | |
624 | { | |
625 | iounmap(psc_fifoc); | |
cb1ea812 GS |
626 | |
627 | /* disable the clock, errors are not fatal */ | |
628 | if (psc_fifoc_clk) { | |
629 | clk_disable_unprepare(psc_fifoc_clk); | |
630 | clk_put(psc_fifoc_clk); | |
631 | psc_fifoc_clk = NULL; | |
632 | } | |
6acc6833 AG |
633 | } |
634 | ||
635 | /* 512x specific interrupt handler. The caller holds the port lock */ | |
636 | static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port) | |
637 | { | |
638 | unsigned long fifoc_int; | |
639 | int psc_num; | |
640 | ||
641 | /* Read pending PSC FIFOC interrupts */ | |
642 | fifoc_int = in_be32(&psc_fifoc->fifoc_int); | |
643 | ||
644 | /* Check if it is an interrupt for this port */ | |
645 | psc_num = (port->mapbase & 0xf00) >> 8; | |
646 | if (test_bit(psc_num, &fifoc_int) || | |
647 | test_bit(psc_num + 16, &fifoc_int)) | |
648 | return mpc5xxx_uart_process_int(port); | |
649 | ||
650 | return IRQ_NONE; | |
651 | } | |
652 | ||
2d30ccac | 653 | static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM]; |
e149b42b | 654 | static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM]; |
2d30ccac GS |
655 | |
656 | /* called from within the .request_port() callback (allocation) */ | |
657 | static int mpc512x_psc_alloc_clock(struct uart_port *port) | |
6acc6833 | 658 | { |
6acc6833 | 659 | int psc_num; |
2d30ccac GS |
660 | struct clk *clk; |
661 | int err; | |
662 | ||
663 | psc_num = (port->mapbase & 0xf00) >> 8; | |
e149b42b GS |
664 | |
665 | clk = devm_clk_get(port->dev, "mclk"); | |
2d30ccac GS |
666 | if (IS_ERR(clk)) { |
667 | dev_err(port->dev, "Failed to get MCLK!\n"); | |
e149b42b GS |
668 | err = PTR_ERR(clk); |
669 | goto out_err; | |
2d30ccac GS |
670 | } |
671 | err = clk_prepare_enable(clk); | |
672 | if (err) { | |
673 | dev_err(port->dev, "Failed to enable MCLK!\n"); | |
e149b42b | 674 | goto out_err; |
2d30ccac GS |
675 | } |
676 | psc_mclk_clk[psc_num] = clk; | |
e149b42b GS |
677 | |
678 | clk = devm_clk_get(port->dev, "ipg"); | |
679 | if (IS_ERR(clk)) { | |
680 | dev_err(port->dev, "Failed to get IPG clock!\n"); | |
681 | err = PTR_ERR(clk); | |
682 | goto out_err; | |
683 | } | |
684 | err = clk_prepare_enable(clk); | |
685 | if (err) { | |
686 | dev_err(port->dev, "Failed to enable IPG clock!\n"); | |
687 | goto out_err; | |
688 | } | |
689 | psc_ipg_clk[psc_num] = clk; | |
690 | ||
2d30ccac | 691 | return 0; |
e149b42b GS |
692 | |
693 | out_err: | |
694 | if (psc_mclk_clk[psc_num]) { | |
695 | clk_disable_unprepare(psc_mclk_clk[psc_num]); | |
696 | psc_mclk_clk[psc_num] = NULL; | |
697 | } | |
698 | if (psc_ipg_clk[psc_num]) { | |
699 | clk_disable_unprepare(psc_ipg_clk[psc_num]); | |
700 | psc_ipg_clk[psc_num] = NULL; | |
701 | } | |
702 | return err; | |
2d30ccac GS |
703 | } |
704 | ||
705 | /* called from within the .release_port() callback (release) */ | |
706 | static void mpc512x_psc_relse_clock(struct uart_port *port) | |
707 | { | |
708 | int psc_num; | |
709 | struct clk *clk; | |
710 | ||
711 | psc_num = (port->mapbase & 0xf00) >> 8; | |
712 | clk = psc_mclk_clk[psc_num]; | |
713 | if (clk) { | |
714 | clk_disable_unprepare(clk); | |
715 | psc_mclk_clk[psc_num] = NULL; | |
716 | } | |
e149b42b GS |
717 | if (psc_ipg_clk[psc_num]) { |
718 | clk_disable_unprepare(psc_ipg_clk[psc_num]); | |
719 | psc_ipg_clk[psc_num] = NULL; | |
720 | } | |
2d30ccac GS |
721 | } |
722 | ||
723 | /* implementation of the .clock() callback (enable/disable) */ | |
724 | static int mpc512x_psc_endis_clock(struct uart_port *port, int enable) | |
725 | { | |
726 | int psc_num; | |
727 | struct clk *psc_clk; | |
728 | int ret; | |
6acc6833 AG |
729 | |
730 | if (uart_console(port)) | |
731 | return 0; | |
732 | ||
733 | psc_num = (port->mapbase & 0xf00) >> 8; | |
2d30ccac GS |
734 | psc_clk = psc_mclk_clk[psc_num]; |
735 | if (!psc_clk) { | |
6acc6833 AG |
736 | dev_err(port->dev, "Failed to get PSC clock entry!\n"); |
737 | return -ENODEV; | |
738 | } | |
739 | ||
2d30ccac GS |
740 | dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis"); |
741 | if (enable) { | |
742 | ret = clk_enable(psc_clk); | |
743 | if (ret) | |
744 | dev_err(port->dev, "Failed to enable MCLK!\n"); | |
745 | return ret; | |
746 | } else { | |
6acc6833 | 747 | clk_disable(psc_clk); |
2d30ccac GS |
748 | return 0; |
749 | } | |
6acc6833 AG |
750 | } |
751 | ||
752 | static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np) | |
753 | { | |
754 | port->irqflags = IRQF_SHARED; | |
755 | port->irq = psc_fifoc_irq; | |
756 | } | |
1f48c499 MF |
757 | #endif |
758 | ||
759 | #ifdef CONFIG_PPC_MPC512x | |
760 | ||
761 | #define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase)) | |
762 | #define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1)) | |
763 | ||
764 | static void mpc5125_psc_fifo_init(struct uart_port *port) | |
765 | { | |
766 | /* /32 prescaler */ | |
767 | out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd); | |
768 | ||
769 | out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); | |
770 | out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); | |
771 | out_be32(&FIFO_5125(port)->txalarm, 1); | |
772 | out_be32(&FIFO_5125(port)->tximr, 0); | |
773 | ||
774 | out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); | |
775 | out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); | |
776 | out_be32(&FIFO_5125(port)->rxalarm, 1); | |
777 | out_be32(&FIFO_5125(port)->rximr, 0); | |
778 | ||
779 | out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM); | |
780 | out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM); | |
781 | } | |
782 | ||
783 | static int mpc5125_psc_raw_rx_rdy(struct uart_port *port) | |
784 | { | |
785 | return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); | |
786 | } | |
787 | ||
788 | static int mpc5125_psc_raw_tx_rdy(struct uart_port *port) | |
789 | { | |
790 | return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL); | |
791 | } | |
792 | ||
793 | static int mpc5125_psc_rx_rdy(struct uart_port *port) | |
794 | { | |
795 | return in_be32(&FIFO_5125(port)->rxsr) & | |
796 | in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM; | |
797 | } | |
798 | ||
799 | static int mpc5125_psc_tx_rdy(struct uart_port *port) | |
800 | { | |
801 | return in_be32(&FIFO_5125(port)->txsr) & | |
802 | in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM; | |
803 | } | |
804 | ||
805 | static int mpc5125_psc_tx_empty(struct uart_port *port) | |
806 | { | |
807 | return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY; | |
808 | } | |
809 | ||
810 | static void mpc5125_psc_stop_rx(struct uart_port *port) | |
811 | { | |
812 | unsigned long rx_fifo_imr; | |
813 | ||
814 | rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr); | |
815 | rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; | |
816 | out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr); | |
817 | } | |
818 | ||
819 | static void mpc5125_psc_start_tx(struct uart_port *port) | |
820 | { | |
821 | unsigned long tx_fifo_imr; | |
822 | ||
823 | tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr); | |
824 | tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; | |
825 | out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr); | |
826 | } | |
827 | ||
828 | static void mpc5125_psc_stop_tx(struct uart_port *port) | |
829 | { | |
830 | unsigned long tx_fifo_imr; | |
831 | ||
832 | tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr); | |
833 | tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; | |
834 | out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr); | |
835 | } | |
836 | ||
837 | static void mpc5125_psc_rx_clr_irq(struct uart_port *port) | |
838 | { | |
839 | out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr)); | |
840 | } | |
841 | ||
842 | static void mpc5125_psc_tx_clr_irq(struct uart_port *port) | |
843 | { | |
844 | out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr)); | |
845 | } | |
846 | ||
847 | static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c) | |
848 | { | |
849 | out_8(&FIFO_5125(port)->txdata_8, c); | |
850 | } | |
851 | ||
852 | static unsigned char mpc5125_psc_read_char(struct uart_port *port) | |
853 | { | |
854 | return in_8(&FIFO_5125(port)->rxdata_8); | |
855 | } | |
856 | ||
857 | static void mpc5125_psc_cw_disable_ints(struct uart_port *port) | |
858 | { | |
859 | port->read_status_mask = | |
860 | in_be32(&FIFO_5125(port)->tximr) << 16 | | |
861 | in_be32(&FIFO_5125(port)->rximr); | |
862 | out_be32(&FIFO_5125(port)->tximr, 0); | |
863 | out_be32(&FIFO_5125(port)->rximr, 0); | |
864 | } | |
865 | ||
866 | static void mpc5125_psc_cw_restore_ints(struct uart_port *port) | |
867 | { | |
868 | out_be32(&FIFO_5125(port)->tximr, | |
869 | (port->read_status_mask >> 16) & 0x7f); | |
870 | out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f); | |
871 | } | |
872 | ||
873 | static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc, | |
874 | u8 prescaler, unsigned int divisor) | |
875 | { | |
876 | /* select prescaler */ | |
877 | out_8(&psc->mpc52xx_psc_clock_select, prescaler); | |
878 | out_8(&psc->ctur, divisor >> 8); | |
879 | out_8(&psc->ctlr, divisor & 0xff); | |
880 | } | |
881 | ||
882 | static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port, | |
883 | struct ktermios *new, | |
884 | struct ktermios *old) | |
885 | { | |
886 | unsigned int baud; | |
887 | unsigned int divisor; | |
888 | ||
889 | /* | |
890 | * Calculate with a /16 prescaler here. | |
891 | */ | |
892 | ||
893 | /* uartclk contains the ips freq */ | |
894 | baud = uart_get_baud_rate(port, new, old, | |
895 | port->uartclk / (16 * 0xffff) + 1, | |
896 | port->uartclk / 16); | |
897 | divisor = (port->uartclk + 8 * baud) / (16 * baud); | |
898 | ||
899 | /* enable the /16 prescaler and set the divisor */ | |
900 | mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor); | |
901 | return baud; | |
902 | } | |
903 | ||
904 | /* | |
905 | * MPC5125 have compatible PSC FIFO Controller. | |
906 | * Special init not needed. | |
907 | */ | |
908 | static u16 mpc5125_psc_get_status(struct uart_port *port) | |
909 | { | |
910 | return in_be16(&PSC_5125(port)->mpc52xx_psc_status); | |
911 | } | |
912 | ||
913 | static u8 mpc5125_psc_get_ipcr(struct uart_port *port) | |
914 | { | |
915 | return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr); | |
916 | } | |
917 | ||
918 | static void mpc5125_psc_command(struct uart_port *port, u8 cmd) | |
919 | { | |
920 | out_8(&PSC_5125(port)->command, cmd); | |
921 | } | |
922 | ||
923 | static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) | |
924 | { | |
925 | out_8(&PSC_5125(port)->mr1, mr1); | |
926 | out_8(&PSC_5125(port)->mr2, mr2); | |
927 | } | |
928 | ||
929 | static void mpc5125_psc_set_rts(struct uart_port *port, int state) | |
930 | { | |
931 | if (state & TIOCM_RTS) | |
932 | out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS); | |
933 | else | |
934 | out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS); | |
935 | } | |
936 | ||
937 | static void mpc5125_psc_enable_ms(struct uart_port *port) | |
938 | { | |
939 | struct mpc5125_psc __iomem *psc = PSC_5125(port); | |
940 | ||
941 | /* clear D_*-bits by reading them */ | |
942 | in_8(&psc->mpc52xx_psc_ipcr); | |
943 | /* enable CTS and DCD as IPC interrupts */ | |
944 | out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); | |
945 | ||
946 | port->read_status_mask |= MPC52xx_PSC_IMR_IPC; | |
947 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); | |
948 | } | |
949 | ||
950 | static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val) | |
951 | { | |
952 | out_be32(&PSC_5125(port)->sicr, val); | |
953 | } | |
954 | ||
955 | static void mpc5125_psc_set_imr(struct uart_port *port, u16 val) | |
956 | { | |
957 | out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val); | |
958 | } | |
959 | ||
960 | static u8 mpc5125_psc_get_mr1(struct uart_port *port) | |
961 | { | |
962 | return in_8(&PSC_5125(port)->mr1); | |
963 | } | |
964 | ||
cc74bd1d | 965 | static const struct psc_ops mpc5125_psc_ops = { |
1f48c499 MF |
966 | .fifo_init = mpc5125_psc_fifo_init, |
967 | .raw_rx_rdy = mpc5125_psc_raw_rx_rdy, | |
968 | .raw_tx_rdy = mpc5125_psc_raw_tx_rdy, | |
969 | .rx_rdy = mpc5125_psc_rx_rdy, | |
970 | .tx_rdy = mpc5125_psc_tx_rdy, | |
971 | .tx_empty = mpc5125_psc_tx_empty, | |
972 | .stop_rx = mpc5125_psc_stop_rx, | |
973 | .start_tx = mpc5125_psc_start_tx, | |
974 | .stop_tx = mpc5125_psc_stop_tx, | |
975 | .rx_clr_irq = mpc5125_psc_rx_clr_irq, | |
976 | .tx_clr_irq = mpc5125_psc_tx_clr_irq, | |
977 | .write_char = mpc5125_psc_write_char, | |
978 | .read_char = mpc5125_psc_read_char, | |
979 | .cw_disable_ints = mpc5125_psc_cw_disable_ints, | |
980 | .cw_restore_ints = mpc5125_psc_cw_restore_ints, | |
981 | .set_baudrate = mpc5125_psc_set_baudrate, | |
2d30ccac GS |
982 | .clock_alloc = mpc512x_psc_alloc_clock, |
983 | .clock_relse = mpc512x_psc_relse_clock, | |
984 | .clock = mpc512x_psc_endis_clock, | |
1f48c499 MF |
985 | .fifoc_init = mpc512x_psc_fifoc_init, |
986 | .fifoc_uninit = mpc512x_psc_fifoc_uninit, | |
987 | .get_irq = mpc512x_psc_get_irq, | |
988 | .handle_irq = mpc512x_psc_handle_irq, | |
989 | .get_status = mpc5125_psc_get_status, | |
990 | .get_ipcr = mpc5125_psc_get_ipcr, | |
991 | .command = mpc5125_psc_command, | |
992 | .set_mode = mpc5125_psc_set_mode, | |
993 | .set_rts = mpc5125_psc_set_rts, | |
994 | .enable_ms = mpc5125_psc_enable_ms, | |
995 | .set_sicr = mpc5125_psc_set_sicr, | |
996 | .set_imr = mpc5125_psc_set_imr, | |
997 | .get_mr1 = mpc5125_psc_get_mr1, | |
998 | }; | |
6acc6833 | 999 | |
cc74bd1d | 1000 | static const struct psc_ops mpc512x_psc_ops = { |
25ae3a07 JR |
1001 | .fifo_init = mpc512x_psc_fifo_init, |
1002 | .raw_rx_rdy = mpc512x_psc_raw_rx_rdy, | |
1003 | .raw_tx_rdy = mpc512x_psc_raw_tx_rdy, | |
1004 | .rx_rdy = mpc512x_psc_rx_rdy, | |
1005 | .tx_rdy = mpc512x_psc_tx_rdy, | |
1006 | .tx_empty = mpc512x_psc_tx_empty, | |
1007 | .stop_rx = mpc512x_psc_stop_rx, | |
1008 | .start_tx = mpc512x_psc_start_tx, | |
1009 | .stop_tx = mpc512x_psc_stop_tx, | |
1010 | .rx_clr_irq = mpc512x_psc_rx_clr_irq, | |
1011 | .tx_clr_irq = mpc512x_psc_tx_clr_irq, | |
1012 | .write_char = mpc512x_psc_write_char, | |
1013 | .read_char = mpc512x_psc_read_char, | |
1014 | .cw_disable_ints = mpc512x_psc_cw_disable_ints, | |
1015 | .cw_restore_ints = mpc512x_psc_cw_restore_ints, | |
0d1f22e4 | 1016 | .set_baudrate = mpc512x_psc_set_baudrate, |
2d30ccac GS |
1017 | .clock_alloc = mpc512x_psc_alloc_clock, |
1018 | .clock_relse = mpc512x_psc_relse_clock, | |
1019 | .clock = mpc512x_psc_endis_clock, | |
6acc6833 AG |
1020 | .fifoc_init = mpc512x_psc_fifoc_init, |
1021 | .fifoc_uninit = mpc512x_psc_fifoc_uninit, | |
1022 | .get_irq = mpc512x_psc_get_irq, | |
1023 | .handle_irq = mpc512x_psc_handle_irq, | |
2574b27e MF |
1024 | .get_status = mpc52xx_psc_get_status, |
1025 | .get_ipcr = mpc52xx_psc_get_ipcr, | |
1026 | .command = mpc52xx_psc_command, | |
1027 | .set_mode = mpc52xx_psc_set_mode, | |
1028 | .set_rts = mpc52xx_psc_set_rts, | |
1029 | .enable_ms = mpc52xx_psc_enable_ms, | |
1030 | .set_sicr = mpc52xx_psc_set_sicr, | |
1031 | .set_imr = mpc52xx_psc_set_imr, | |
1032 | .get_mr1 = mpc52xx_psc_get_mr1, | |
25ae3a07 | 1033 | }; |
2574b27e MF |
1034 | #endif /* CONFIG_PPC_MPC512x */ |
1035 | ||
25ae3a07 | 1036 | |
76d28e44 | 1037 | static const struct psc_ops *psc_ops; |
1da177e4 LT |
1038 | |
1039 | /* ======================================================================== */ | |
1040 | /* UART operations */ | |
1041 | /* ======================================================================== */ | |
1042 | ||
9b9129e7 | 1043 | static unsigned int |
1da177e4 LT |
1044 | mpc52xx_uart_tx_empty(struct uart_port *port) |
1045 | { | |
599f030c | 1046 | return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0; |
1da177e4 LT |
1047 | } |
1048 | ||
9b9129e7 | 1049 | static void |
1da177e4 LT |
1050 | mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1051 | { | |
2574b27e | 1052 | psc_ops->set_rts(port, mctrl & TIOCM_RTS); |
1da177e4 LT |
1053 | } |
1054 | ||
9b9129e7 | 1055 | static unsigned int |
1da177e4 LT |
1056 | mpc52xx_uart_get_mctrl(struct uart_port *port) |
1057 | { | |
aec739e0 | 1058 | unsigned int ret = TIOCM_DSR; |
2574b27e | 1059 | u8 status = psc_ops->get_ipcr(port); |
aec739e0 WS |
1060 | |
1061 | if (!(status & MPC52xx_PSC_CTS)) | |
1062 | ret |= TIOCM_CTS; | |
1063 | if (!(status & MPC52xx_PSC_DCD)) | |
1064 | ret |= TIOCM_CAR; | |
1065 | ||
1066 | return ret; | |
1da177e4 LT |
1067 | } |
1068 | ||
9b9129e7 | 1069 | static void |
b129a8cc | 1070 | mpc52xx_uart_stop_tx(struct uart_port *port) |
1da177e4 LT |
1071 | { |
1072 | /* port->lock taken by caller */ | |
599f030c | 1073 | psc_ops->stop_tx(port); |
1da177e4 LT |
1074 | } |
1075 | ||
9b9129e7 | 1076 | static void |
b129a8cc | 1077 | mpc52xx_uart_start_tx(struct uart_port *port) |
1da177e4 LT |
1078 | { |
1079 | /* port->lock taken by caller */ | |
599f030c | 1080 | psc_ops->start_tx(port); |
1da177e4 LT |
1081 | } |
1082 | ||
1da177e4 LT |
1083 | static void |
1084 | mpc52xx_uart_stop_rx(struct uart_port *port) | |
1085 | { | |
1086 | /* port->lock taken by caller */ | |
599f030c | 1087 | psc_ops->stop_rx(port); |
1da177e4 LT |
1088 | } |
1089 | ||
1090 | static void | |
1091 | mpc52xx_uart_enable_ms(struct uart_port *port) | |
1092 | { | |
2574b27e | 1093 | psc_ops->enable_ms(port); |
1da177e4 LT |
1094 | } |
1095 | ||
1096 | static void | |
1097 | mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) | |
1098 | { | |
1099 | unsigned long flags; | |
1100 | spin_lock_irqsave(&port->lock, flags); | |
1101 | ||
406b7d4f | 1102 | if (ctl == -1) |
2574b27e | 1103 | psc_ops->command(port, MPC52xx_PSC_START_BRK); |
1da177e4 | 1104 | else |
2574b27e | 1105 | psc_ops->command(port, MPC52xx_PSC_STOP_BRK); |
9b9129e7 | 1106 | |
1da177e4 LT |
1107 | spin_unlock_irqrestore(&port->lock, flags); |
1108 | } | |
1109 | ||
1110 | static int | |
1111 | mpc52xx_uart_startup(struct uart_port *port) | |
1112 | { | |
1da177e4 LT |
1113 | int ret; |
1114 | ||
6acc6833 AG |
1115 | if (psc_ops->clock) { |
1116 | ret = psc_ops->clock(port, 1); | |
1117 | if (ret) | |
1118 | return ret; | |
1119 | } | |
1120 | ||
1da177e4 LT |
1121 | /* Request IRQ */ |
1122 | ret = request_irq(port->irq, mpc52xx_uart_int, | |
6acc6833 | 1123 | port->irqflags, "mpc52xx_psc_uart", port); |
1da177e4 LT |
1124 | if (ret) |
1125 | return ret; | |
1126 | ||
1127 | /* Reset/activate the port, clear and enable interrupts */ | |
2574b27e MF |
1128 | psc_ops->command(port, MPC52xx_PSC_RST_RX); |
1129 | psc_ops->command(port, MPC52xx_PSC_RST_TX); | |
9b9129e7 | 1130 | |
e4b4e317 UKK |
1131 | /* |
1132 | * According to Freescale's support the RST_TX command can produce a | |
1133 | * spike on the TX pin. So they recommend to delay "for one character". | |
1134 | * One millisecond should be enough for everyone. | |
1135 | */ | |
1136 | msleep(1); | |
1137 | ||
2574b27e | 1138 | psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */ |
1da177e4 | 1139 | |
599f030c | 1140 | psc_ops->fifo_init(port); |
9b9129e7 | 1141 | |
2574b27e MF |
1142 | psc_ops->command(port, MPC52xx_PSC_TX_ENABLE); |
1143 | psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); | |
9b9129e7 | 1144 | |
1da177e4 LT |
1145 | return 0; |
1146 | } | |
1147 | ||
1148 | static void | |
1149 | mpc52xx_uart_shutdown(struct uart_port *port) | |
1150 | { | |
a3481197 | 1151 | /* Shut down the port. Leave TX active if on a console port */ |
2574b27e | 1152 | psc_ops->command(port, MPC52xx_PSC_RST_RX); |
a3481197 | 1153 | if (!uart_console(port)) |
2574b27e | 1154 | psc_ops->command(port, MPC52xx_PSC_RST_TX); |
9b9129e7 GL |
1155 | |
1156 | port->read_status_mask = 0; | |
2574b27e | 1157 | psc_ops->set_imr(port, port->read_status_mask); |
1da177e4 | 1158 | |
6acc6833 AG |
1159 | if (psc_ops->clock) |
1160 | psc_ops->clock(port, 0); | |
1161 | ||
8a29dfb8 MF |
1162 | /* Disable interrupt */ |
1163 | psc_ops->cw_disable_ints(port); | |
1164 | ||
1da177e4 LT |
1165 | /* Release interrupt */ |
1166 | free_irq(port->irq, port); | |
1167 | } | |
1168 | ||
9b9129e7 | 1169 | static void |
606d099c | 1170 | mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, |
406b7d4f | 1171 | struct ktermios *old) |
1da177e4 | 1172 | { |
1da177e4 LT |
1173 | unsigned long flags; |
1174 | unsigned char mr1, mr2; | |
0d1f22e4 AD |
1175 | unsigned int j; |
1176 | unsigned int baud; | |
9b9129e7 | 1177 | |
1da177e4 LT |
1178 | /* Prepare what we're gonna write */ |
1179 | mr1 = 0; | |
9b9129e7 | 1180 | |
1da177e4 | 1181 | switch (new->c_cflag & CSIZE) { |
406b7d4f JR |
1182 | case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; |
1183 | break; | |
1184 | case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; | |
1185 | break; | |
1186 | case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS; | |
1187 | break; | |
1188 | case CS8: | |
1189 | default: mr1 |= MPC52xx_PSC_MODE_8_BITS; | |
1da177e4 LT |
1190 | } |
1191 | ||
1192 | if (new->c_cflag & PARENB) { | |
d3dec96e WS |
1193 | if (new->c_cflag & CMSPAR) |
1194 | mr1 |= MPC52xx_PSC_MODE_PARFORCE; | |
1195 | ||
1196 | /* With CMSPAR, PARODD also means high parity (same as termios) */ | |
1da177e4 LT |
1197 | mr1 |= (new->c_cflag & PARODD) ? |
1198 | MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; | |
d3dec96e | 1199 | } else { |
1da177e4 | 1200 | mr1 |= MPC52xx_PSC_MODE_PARNONE; |
d3dec96e | 1201 | } |
9b9129e7 | 1202 | |
1da177e4 LT |
1203 | mr2 = 0; |
1204 | ||
1205 | if (new->c_cflag & CSTOPB) | |
1206 | mr2 |= MPC52xx_PSC_MODE_TWO_STOP; | |
1207 | else | |
1208 | mr2 |= ((new->c_cflag & CSIZE) == CS5) ? | |
1209 | MPC52xx_PSC_MODE_ONE_STOP_5_BITS : | |
1210 | MPC52xx_PSC_MODE_ONE_STOP; | |
1211 | ||
aec739e0 WS |
1212 | if (new->c_cflag & CRTSCTS) { |
1213 | mr1 |= MPC52xx_PSC_MODE_RXRTS; | |
1214 | mr2 |= MPC52xx_PSC_MODE_TXCTS; | |
1215 | } | |
1da177e4 | 1216 | |
1da177e4 LT |
1217 | /* Get the lock */ |
1218 | spin_lock_irqsave(&port->lock, flags); | |
1219 | ||
c4f01240 NA |
1220 | /* Do our best to flush TX & RX, so we don't lose anything */ |
1221 | /* But we don't wait indefinitely ! */ | |
1da177e4 LT |
1222 | j = 5000000; /* Maximum wait */ |
1223 | /* FIXME Can't receive chars since set_termios might be called at early | |
1224 | * boot for the console, all stuff is not yet ready to receive at that | |
1225 | * time and that just makes the kernel oops */ | |
1226 | /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ | |
599f030c | 1227 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
1228 | udelay(1); |
1229 | ||
1230 | if (!j) | |
406b7d4f | 1231 | printk(KERN_ERR "mpc52xx_uart.c: " |
1da177e4 | 1232 | "Unable to flush RX & TX fifos in-time in set_termios." |
406b7d4f | 1233 | "Some chars may have been lost.\n"); |
1da177e4 LT |
1234 | |
1235 | /* Reset the TX & RX */ | |
2574b27e MF |
1236 | psc_ops->command(port, MPC52xx_PSC_RST_RX); |
1237 | psc_ops->command(port, MPC52xx_PSC_RST_TX); | |
1da177e4 LT |
1238 | |
1239 | /* Send new mode settings */ | |
2574b27e | 1240 | psc_ops->set_mode(port, mr1, mr2); |
0d1f22e4 AD |
1241 | baud = psc_ops->set_baudrate(port, new, old); |
1242 | ||
1243 | /* Update the per-port timeout */ | |
1244 | uart_update_timeout(port, new->c_cflag, baud); | |
9b9129e7 | 1245 | |
aec739e0 WS |
1246 | if (UART_ENABLE_MS(port, new->c_cflag)) |
1247 | mpc52xx_uart_enable_ms(port); | |
1248 | ||
1da177e4 | 1249 | /* Reenable TX & RX */ |
2574b27e MF |
1250 | psc_ops->command(port, MPC52xx_PSC_TX_ENABLE); |
1251 | psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); | |
1da177e4 LT |
1252 | |
1253 | /* We're all set, release the lock */ | |
1254 | spin_unlock_irqrestore(&port->lock, flags); | |
1255 | } | |
1256 | ||
1257 | static const char * | |
1258 | mpc52xx_uart_type(struct uart_port *port) | |
1259 | { | |
e44dcb6c WS |
1260 | /* |
1261 | * We keep using PORT_MPC52xx for historic reasons although it applies | |
1262 | * for MPC512x, too, but print "MPC5xxx" to not irritate users | |
1263 | */ | |
1264 | return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL; | |
1da177e4 LT |
1265 | } |
1266 | ||
1267 | static void | |
1268 | mpc52xx_uart_release_port(struct uart_port *port) | |
1269 | { | |
2d30ccac GS |
1270 | if (psc_ops->clock_relse) |
1271 | psc_ops->clock_relse(port); | |
1272 | ||
406b7d4f JR |
1273 | /* remapped by us ? */ |
1274 | if (port->flags & UPF_IOREMAP) { | |
1da177e4 LT |
1275 | iounmap(port->membase); |
1276 | port->membase = NULL; | |
1277 | } | |
1278 | ||
b9272dfd | 1279 | release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); |
1da177e4 LT |
1280 | } |
1281 | ||
1282 | static int | |
1283 | mpc52xx_uart_request_port(struct uart_port *port) | |
1284 | { | |
be618f55 AL |
1285 | int err; |
1286 | ||
1da177e4 | 1287 | if (port->flags & UPF_IOREMAP) /* Need to remap ? */ |
b9272dfd | 1288 | port->membase = ioremap(port->mapbase, |
406b7d4f | 1289 | sizeof(struct mpc52xx_psc)); |
1da177e4 LT |
1290 | |
1291 | if (!port->membase) | |
1292 | return -EINVAL; | |
1293 | ||
b9272dfd | 1294 | err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc), |
1da177e4 | 1295 | "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY; |
be618f55 | 1296 | |
2d30ccac GS |
1297 | if (err) |
1298 | goto out_membase; | |
1299 | ||
1300 | if (psc_ops->clock_alloc) { | |
1301 | err = psc_ops->clock_alloc(port); | |
1302 | if (err) | |
1303 | goto out_mapregion; | |
1304 | } | |
1305 | ||
1306 | return 0; | |
1307 | ||
1308 | out_mapregion: | |
1309 | release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); | |
1310 | out_membase: | |
1311 | if (port->flags & UPF_IOREMAP) { | |
be618f55 AL |
1312 | iounmap(port->membase); |
1313 | port->membase = NULL; | |
1314 | } | |
be618f55 | 1315 | return err; |
1da177e4 LT |
1316 | } |
1317 | ||
1318 | static void | |
1319 | mpc52xx_uart_config_port(struct uart_port *port, int flags) | |
1320 | { | |
406b7d4f JR |
1321 | if ((flags & UART_CONFIG_TYPE) |
1322 | && (mpc52xx_uart_request_port(port) == 0)) | |
1323 | port->type = PORT_MPC52xx; | |
1da177e4 LT |
1324 | } |
1325 | ||
1326 | static int | |
1327 | mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1328 | { | |
406b7d4f | 1329 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx) |
1da177e4 LT |
1330 | return -EINVAL; |
1331 | ||
406b7d4f | 1332 | if ((ser->irq != port->irq) || |
b7a8212c | 1333 | (ser->io_type != UPIO_MEM) || |
406b7d4f JR |
1334 | (ser->baud_base != port->uartclk) || |
1335 | (ser->iomem_base != (void *)port->mapbase) || | |
1336 | (ser->hub6 != 0)) | |
1da177e4 LT |
1337 | return -EINVAL; |
1338 | ||
1339 | return 0; | |
1340 | } | |
1341 | ||
1342 | ||
6f137a75 | 1343 | static const struct uart_ops mpc52xx_uart_ops = { |
1da177e4 LT |
1344 | .tx_empty = mpc52xx_uart_tx_empty, |
1345 | .set_mctrl = mpc52xx_uart_set_mctrl, | |
1346 | .get_mctrl = mpc52xx_uart_get_mctrl, | |
1347 | .stop_tx = mpc52xx_uart_stop_tx, | |
1348 | .start_tx = mpc52xx_uart_start_tx, | |
1da177e4 LT |
1349 | .stop_rx = mpc52xx_uart_stop_rx, |
1350 | .enable_ms = mpc52xx_uart_enable_ms, | |
1351 | .break_ctl = mpc52xx_uart_break_ctl, | |
1352 | .startup = mpc52xx_uart_startup, | |
1353 | .shutdown = mpc52xx_uart_shutdown, | |
1354 | .set_termios = mpc52xx_uart_set_termios, | |
1355 | /* .pm = mpc52xx_uart_pm, Not supported yet */ | |
1da177e4 LT |
1356 | .type = mpc52xx_uart_type, |
1357 | .release_port = mpc52xx_uart_release_port, | |
1358 | .request_port = mpc52xx_uart_request_port, | |
1359 | .config_port = mpc52xx_uart_config_port, | |
1360 | .verify_port = mpc52xx_uart_verify_port | |
1361 | }; | |
1362 | ||
9b9129e7 | 1363 | |
1da177e4 LT |
1364 | /* ======================================================================== */ |
1365 | /* Interrupt handling */ | |
1366 | /* ======================================================================== */ | |
9b9129e7 | 1367 | |
1da177e4 | 1368 | static inline int |
7d12e780 | 1369 | mpc52xx_uart_int_rx_chars(struct uart_port *port) |
1da177e4 | 1370 | { |
92a19f9c | 1371 | struct tty_port *tport = &port->state->port; |
33f0f88f | 1372 | unsigned char ch, flag; |
1da177e4 LT |
1373 | unsigned short status; |
1374 | ||
1375 | /* While we can read, do so ! */ | |
599f030c | 1376 | while (psc_ops->raw_rx_rdy(port)) { |
1da177e4 | 1377 | /* Get the char */ |
599f030c | 1378 | ch = psc_ops->read_char(port); |
1da177e4 LT |
1379 | |
1380 | /* Handle sysreq char */ | |
7cbfd6a0 | 1381 | if (uart_handle_sysrq_char(port, ch)) |
1da177e4 | 1382 | continue; |
1da177e4 LT |
1383 | |
1384 | /* Store it */ | |
33f0f88f AC |
1385 | |
1386 | flag = TTY_NORMAL; | |
1da177e4 | 1387 | port->icount.rx++; |
9b9129e7 | 1388 | |
2574b27e | 1389 | status = psc_ops->get_status(port); |
599f030c | 1390 | |
406b7d4f JR |
1391 | if (status & (MPC52xx_PSC_SR_PE | |
1392 | MPC52xx_PSC_SR_FE | | |
1393 | MPC52xx_PSC_SR_RB)) { | |
9b9129e7 | 1394 | |
1da177e4 | 1395 | if (status & MPC52xx_PSC_SR_RB) { |
33f0f88f | 1396 | flag = TTY_BREAK; |
1da177e4 | 1397 | uart_handle_break(port); |
b6514988 RB |
1398 | port->icount.brk++; |
1399 | } else if (status & MPC52xx_PSC_SR_PE) { | |
33f0f88f | 1400 | flag = TTY_PARITY; |
b6514988 RB |
1401 | port->icount.parity++; |
1402 | } | |
1403 | else if (status & MPC52xx_PSC_SR_FE) { | |
33f0f88f | 1404 | flag = TTY_FRAME; |
b6514988 RB |
1405 | port->icount.frame++; |
1406 | } | |
1da177e4 LT |
1407 | |
1408 | /* Clear error condition */ | |
2574b27e | 1409 | psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT); |
1da177e4 LT |
1410 | |
1411 | } | |
92a19f9c | 1412 | tty_insert_flip_char(tport, ch, flag); |
33f0f88f AC |
1413 | if (status & MPC52xx_PSC_SR_OE) { |
1414 | /* | |
1415 | * Overrun is special, since it's | |
1416 | * reported immediately, and doesn't | |
1417 | * affect the current character | |
1418 | */ | |
92a19f9c | 1419 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); |
b6514988 | 1420 | port->icount.overrun++; |
33f0f88f | 1421 | } |
1da177e4 LT |
1422 | } |
1423 | ||
2e124b4a | 1424 | tty_flip_buffer_push(tport); |
9b9129e7 | 1425 | |
599f030c | 1426 | return psc_ops->raw_rx_rdy(port); |
1da177e4 LT |
1427 | } |
1428 | ||
1429 | static inline int | |
1430 | mpc52xx_uart_int_tx_chars(struct uart_port *port) | |
1431 | { | |
ebd2c8f6 | 1432 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 LT |
1433 | |
1434 | /* Process out of band chars */ | |
1435 | if (port->x_char) { | |
599f030c | 1436 | psc_ops->write_char(port, port->x_char); |
1da177e4 LT |
1437 | port->icount.tx++; |
1438 | port->x_char = 0; | |
1439 | return 1; | |
1440 | } | |
1441 | ||
1442 | /* Nothing to do ? */ | |
1443 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 1444 | mpc52xx_uart_stop_tx(port); |
1da177e4 LT |
1445 | return 0; |
1446 | } | |
1447 | ||
1448 | /* Send chars */ | |
599f030c JR |
1449 | while (psc_ops->raw_tx_rdy(port)) { |
1450 | psc_ops->write_char(port, xmit->buf[xmit->tail]); | |
1da177e4 LT |
1451 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1452 | port->icount.tx++; | |
1453 | if (uart_circ_empty(xmit)) | |
1454 | break; | |
1455 | } | |
1456 | ||
1457 | /* Wake up */ | |
1458 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1459 | uart_write_wakeup(port); | |
1460 | ||
1461 | /* Maybe we're done after all */ | |
1462 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 1463 | mpc52xx_uart_stop_tx(port); |
1da177e4 LT |
1464 | return 0; |
1465 | } | |
1466 | ||
1467 | return 1; | |
1468 | } | |
1469 | ||
9b9129e7 | 1470 | static irqreturn_t |
6acc6833 | 1471 | mpc5xxx_uart_process_int(struct uart_port *port) |
1da177e4 | 1472 | { |
1da177e4 LT |
1473 | unsigned long pass = ISR_PASS_LIMIT; |
1474 | unsigned int keepgoing; | |
aec739e0 | 1475 | u8 status; |
9b9129e7 | 1476 | |
1da177e4 LT |
1477 | /* While we have stuff to do, we continue */ |
1478 | do { | |
1479 | /* If we don't find anything to do, we stop */ | |
9b9129e7 GL |
1480 | keepgoing = 0; |
1481 | ||
599f030c JR |
1482 | psc_ops->rx_clr_irq(port); |
1483 | if (psc_ops->rx_rdy(port)) | |
7d12e780 | 1484 | keepgoing |= mpc52xx_uart_int_rx_chars(port); |
1da177e4 | 1485 | |
599f030c JR |
1486 | psc_ops->tx_clr_irq(port); |
1487 | if (psc_ops->tx_rdy(port)) | |
1da177e4 | 1488 | keepgoing |= mpc52xx_uart_int_tx_chars(port); |
9b9129e7 | 1489 | |
2574b27e | 1490 | status = psc_ops->get_ipcr(port); |
aec739e0 WS |
1491 | if (status & MPC52xx_PSC_D_DCD) |
1492 | uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD)); | |
1493 | ||
1494 | if (status & MPC52xx_PSC_D_CTS) | |
1495 | uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS)); | |
1496 | ||
1da177e4 | 1497 | /* Limit number of iteration */ |
406b7d4f | 1498 | if (!(--pass)) |
1da177e4 LT |
1499 | keepgoing = 0; |
1500 | ||
1501 | } while (keepgoing); | |
9b9129e7 | 1502 | |
1da177e4 LT |
1503 | return IRQ_HANDLED; |
1504 | } | |
1505 | ||
6acc6833 AG |
1506 | static irqreturn_t |
1507 | mpc52xx_uart_int(int irq, void *dev_id) | |
1508 | { | |
1509 | struct uart_port *port = dev_id; | |
1510 | irqreturn_t ret; | |
1511 | ||
1512 | spin_lock(&port->lock); | |
1513 | ||
1514 | ret = psc_ops->handle_irq(port); | |
1515 | ||
1516 | spin_unlock(&port->lock); | |
1517 | ||
1518 | return ret; | |
1519 | } | |
1da177e4 LT |
1520 | |
1521 | /* ======================================================================== */ | |
1522 | /* Console ( if applicable ) */ | |
1523 | /* ======================================================================== */ | |
1524 | ||
1525 | #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE | |
1526 | ||
1527 | static void __init | |
1528 | mpc52xx_console_get_options(struct uart_port *port, | |
406b7d4f | 1529 | int *baud, int *parity, int *bits, int *flow) |
1da177e4 | 1530 | { |
1da177e4 LT |
1531 | unsigned char mr1; |
1532 | ||
b9272dfd GL |
1533 | pr_debug("mpc52xx_console_get_options(port=%p)\n", port); |
1534 | ||
1da177e4 | 1535 | /* Read the mode registers */ |
2574b27e | 1536 | mr1 = psc_ops->get_mr1(port); |
9b9129e7 | 1537 | |
1da177e4 | 1538 | /* CT{U,L}R are write-only ! */ |
b9272dfd | 1539 | *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; |
1da177e4 LT |
1540 | |
1541 | /* Parse them */ | |
1542 | switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) { | |
406b7d4f JR |
1543 | case MPC52xx_PSC_MODE_5_BITS: |
1544 | *bits = 5; | |
1545 | break; | |
1546 | case MPC52xx_PSC_MODE_6_BITS: | |
1547 | *bits = 6; | |
1548 | break; | |
1549 | case MPC52xx_PSC_MODE_7_BITS: | |
1550 | *bits = 7; | |
1551 | break; | |
1552 | case MPC52xx_PSC_MODE_8_BITS: | |
1553 | default: | |
1554 | *bits = 8; | |
1da177e4 | 1555 | } |
9b9129e7 | 1556 | |
1da177e4 LT |
1557 | if (mr1 & MPC52xx_PSC_MODE_PARNONE) |
1558 | *parity = 'n'; | |
1559 | else | |
1560 | *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e'; | |
1561 | } | |
1562 | ||
9b9129e7 | 1563 | static void |
1da177e4 LT |
1564 | mpc52xx_console_write(struct console *co, const char *s, unsigned int count) |
1565 | { | |
1566 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; | |
1da177e4 | 1567 | unsigned int i, j; |
9b9129e7 | 1568 | |
1da177e4 | 1569 | /* Disable interrupts */ |
599f030c | 1570 | psc_ops->cw_disable_ints(port); |
1da177e4 LT |
1571 | |
1572 | /* Wait the TX buffer to be empty */ | |
9b9129e7 | 1573 | j = 5000000; /* Maximum wait */ |
599f030c | 1574 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
1575 | udelay(1); |
1576 | ||
1577 | /* Write all the chars */ | |
d358788f | 1578 | for (i = 0; i < count; i++, s++) { |
1da177e4 | 1579 | /* Line return handling */ |
d358788f | 1580 | if (*s == '\n') |
599f030c | 1581 | psc_ops->write_char(port, '\r'); |
9b9129e7 | 1582 | |
d358788f | 1583 | /* Send the char */ |
599f030c | 1584 | psc_ops->write_char(port, *s); |
d358788f | 1585 | |
1da177e4 | 1586 | /* Wait the TX buffer to be empty */ |
9b9129e7 | 1587 | j = 20000; /* Maximum wait */ |
599f030c | 1588 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
1589 | udelay(1); |
1590 | } | |
1591 | ||
1592 | /* Restore interrupt state */ | |
599f030c | 1593 | psc_ops->cw_restore_ints(port); |
1da177e4 LT |
1594 | } |
1595 | ||
b9272dfd GL |
1596 | |
1597 | static int __init | |
1598 | mpc52xx_console_setup(struct console *co, char *options) | |
1599 | { | |
1600 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; | |
1601 | struct device_node *np = mpc52xx_uart_nodes[co->index]; | |
599f030c | 1602 | unsigned int uartclk; |
b9272dfd GL |
1603 | struct resource res; |
1604 | int ret; | |
1605 | ||
1606 | int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; | |
1607 | int bits = 8; | |
1608 | int parity = 'n'; | |
1609 | int flow = 'n'; | |
1610 | ||
1611 | pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n", | |
1612 | co, co->index, options); | |
1613 | ||
b898f4f8 | 1614 | if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) { |
b9272dfd GL |
1615 | pr_debug("PSC%x out of range\n", co->index); |
1616 | return -EINVAL; | |
1617 | } | |
1618 | ||
1619 | if (!np) { | |
1620 | pr_debug("PSC%x not found in device tree\n", co->index); | |
1621 | return -EINVAL; | |
1622 | } | |
1623 | ||
a73ee843 RH |
1624 | pr_debug("Console on ttyPSC%x is %pOF\n", |
1625 | co->index, mpc52xx_uart_nodes[co->index]); | |
b9272dfd GL |
1626 | |
1627 | /* Fetch register locations */ | |
406b7d4f JR |
1628 | ret = of_address_to_resource(np, 0, &res); |
1629 | if (ret) { | |
b9272dfd GL |
1630 | pr_debug("Could not get resources for PSC%x\n", co->index); |
1631 | return ret; | |
1632 | } | |
1633 | ||
0d1f22e4 | 1634 | uartclk = mpc5xxx_get_bus_frequency(np); |
599f030c JR |
1635 | if (uartclk == 0) { |
1636 | pr_debug("Could not find uart clock frequency!\n"); | |
b9272dfd GL |
1637 | return -EINVAL; |
1638 | } | |
1639 | ||
1640 | /* Basic port init. Needed since we use some uart_??? func before | |
1641 | * real init for early access */ | |
1642 | spin_lock_init(&port->lock); | |
599f030c | 1643 | port->uartclk = uartclk; |
b9272dfd GL |
1644 | port->ops = &mpc52xx_uart_ops; |
1645 | port->mapbase = res.start; | |
1646 | port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); | |
1647 | port->irq = irq_of_parse_and_map(np, 0); | |
1648 | ||
1649 | if (port->membase == NULL) | |
1650 | return -EINVAL; | |
1651 | ||
5dd80d5d | 1652 | pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n", |
406b7d4f JR |
1653 | (void *)port->mapbase, port->membase, |
1654 | port->irq, port->uartclk); | |
b9272dfd GL |
1655 | |
1656 | /* Setup the port parameters accoding to options */ | |
1657 | if (options) | |
1658 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1659 | else | |
1660 | mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow); | |
1661 | ||
1662 | pr_debug("Setting console parameters: %i %i%c1 flow=%c\n", | |
406b7d4f | 1663 | baud, bits, parity, flow); |
b9272dfd GL |
1664 | |
1665 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1666 | } | |
b9272dfd | 1667 | |
1da177e4 | 1668 | |
2d8179c0 | 1669 | static struct uart_driver mpc52xx_uart_driver; |
1da177e4 LT |
1670 | |
1671 | static struct console mpc52xx_console = { | |
d62de3aa | 1672 | .name = "ttyPSC", |
1da177e4 LT |
1673 | .write = mpc52xx_console_write, |
1674 | .device = uart_console_device, | |
1675 | .setup = mpc52xx_console_setup, | |
1676 | .flags = CON_PRINTBUFFER, | |
406b7d4f | 1677 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */ |
1da177e4 LT |
1678 | .data = &mpc52xx_uart_driver, |
1679 | }; | |
1680 | ||
9b9129e7 GL |
1681 | |
1682 | static int __init | |
1da177e4 LT |
1683 | mpc52xx_console_init(void) |
1684 | { | |
b9272dfd | 1685 | mpc52xx_uart_of_enumerate(); |
1da177e4 LT |
1686 | register_console(&mpc52xx_console); |
1687 | return 0; | |
1688 | } | |
1689 | ||
1690 | console_initcall(mpc52xx_console_init); | |
1691 | ||
1692 | #define MPC52xx_PSC_CONSOLE &mpc52xx_console | |
1693 | #else | |
1694 | #define MPC52xx_PSC_CONSOLE NULL | |
1695 | #endif | |
1696 | ||
1697 | ||
1698 | /* ======================================================================== */ | |
1699 | /* UART Driver */ | |
1700 | /* ======================================================================== */ | |
1701 | ||
1702 | static struct uart_driver mpc52xx_uart_driver = { | |
1da177e4 | 1703 | .driver_name = "mpc52xx_psc_uart", |
d62de3aa | 1704 | .dev_name = "ttyPSC", |
d62de3aa SM |
1705 | .major = SERIAL_PSC_MAJOR, |
1706 | .minor = SERIAL_PSC_MINOR, | |
1da177e4 LT |
1707 | .nr = MPC52xx_PSC_MAXNUM, |
1708 | .cons = MPC52xx_PSC_CONSOLE, | |
1709 | }; | |
1710 | ||
b9272dfd GL |
1711 | /* ======================================================================== */ |
1712 | /* OF Platform Driver */ | |
1713 | /* ======================================================================== */ | |
1714 | ||
ed0bb232 | 1715 | static const struct of_device_id mpc52xx_uart_of_match[] = { |
52b80482 | 1716 | #ifdef CONFIG_PPC_MPC52xx |
0d1f22e4 | 1717 | { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, }, |
52b80482 GL |
1718 | { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, |
1719 | /* binding used by old lite5200 device trees: */ | |
1720 | { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, | |
1721 | /* binding used by efika: */ | |
1722 | { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, }, | |
1723 | #endif | |
1724 | #ifdef CONFIG_PPC_MPC512x | |
1725 | { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, }, | |
1f48c499 | 1726 | { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, }, |
52b80482 | 1727 | #endif |
bc775eac | 1728 | {}, |
52b80482 GL |
1729 | }; |
1730 | ||
9671f099 | 1731 | static int mpc52xx_uart_of_probe(struct platform_device *op) |
b9272dfd GL |
1732 | { |
1733 | int idx = -1; | |
599f030c | 1734 | unsigned int uartclk; |
b9272dfd GL |
1735 | struct uart_port *port = NULL; |
1736 | struct resource res; | |
1737 | int ret; | |
1738 | ||
b9272dfd GL |
1739 | /* Check validity & presence */ |
1740 | for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++) | |
61c7a080 | 1741 | if (mpc52xx_uart_nodes[idx] == op->dev.of_node) |
b9272dfd GL |
1742 | break; |
1743 | if (idx >= MPC52xx_PSC_MAXNUM) | |
1744 | return -EINVAL; | |
a73ee843 RH |
1745 | pr_debug("Found %pOF assigned to ttyPSC%x\n", |
1746 | mpc52xx_uart_nodes[idx], idx); | |
b9272dfd | 1747 | |
0d1f22e4 AD |
1748 | /* set the uart clock to the input clock of the psc, the different |
1749 | * prescalers are taken into account in the set_baudrate() methods | |
1750 | * of the respective chip */ | |
1751 | uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node); | |
599f030c JR |
1752 | if (uartclk == 0) { |
1753 | dev_dbg(&op->dev, "Could not find uart clock frequency!\n"); | |
b9272dfd GL |
1754 | return -EINVAL; |
1755 | } | |
1756 | ||
1757 | /* Init the port structure */ | |
1758 | port = &mpc52xx_uart_ports[idx]; | |
1759 | ||
1760 | spin_lock_init(&port->lock); | |
599f030c | 1761 | port->uartclk = uartclk; |
b9272dfd | 1762 | port->fifosize = 512; |
ba4508db | 1763 | port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MPC52xx_CONSOLE); |
b9272dfd GL |
1764 | port->iotype = UPIO_MEM; |
1765 | port->flags = UPF_BOOT_AUTOCONF | | |
406b7d4f | 1766 | (uart_console(port) ? 0 : UPF_IOREMAP); |
b9272dfd GL |
1767 | port->line = idx; |
1768 | port->ops = &mpc52xx_uart_ops; | |
1769 | port->dev = &op->dev; | |
1770 | ||
1771 | /* Search for IRQ and mapbase */ | |
61c7a080 | 1772 | ret = of_address_to_resource(op->dev.of_node, 0, &res); |
406b7d4f | 1773 | if (ret) |
b9272dfd GL |
1774 | return ret; |
1775 | ||
1776 | port->mapbase = res.start; | |
418441d9 WS |
1777 | if (!port->mapbase) { |
1778 | dev_dbg(&op->dev, "Could not allocate resources for PSC\n"); | |
1779 | return -EINVAL; | |
1780 | } | |
1781 | ||
61c7a080 | 1782 | psc_ops->get_irq(port, op->dev.of_node); |
d4e33fac | 1783 | if (port->irq == 0) { |
418441d9 WS |
1784 | dev_dbg(&op->dev, "Could not get irq\n"); |
1785 | return -EINVAL; | |
1786 | } | |
b9272dfd | 1787 | |
5dd80d5d | 1788 | dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n", |
406b7d4f | 1789 | (void *)port->mapbase, port->irq, port->uartclk); |
b9272dfd | 1790 | |
b9272dfd GL |
1791 | /* Add the port to the uart sub-system */ |
1792 | ret = uart_add_one_port(&mpc52xx_uart_driver, port); | |
6acc6833 | 1793 | if (ret) |
418441d9 | 1794 | return ret; |
b9272dfd | 1795 | |
696faedd | 1796 | platform_set_drvdata(op, (void *)port); |
418441d9 | 1797 | return 0; |
b9272dfd GL |
1798 | } |
1799 | ||
1800 | static int | |
2dc11581 | 1801 | mpc52xx_uart_of_remove(struct platform_device *op) |
b9272dfd | 1802 | { |
696faedd | 1803 | struct uart_port *port = platform_get_drvdata(op); |
b9272dfd | 1804 | |
6acc6833 | 1805 | if (port) |
b9272dfd GL |
1806 | uart_remove_one_port(&mpc52xx_uart_driver, port); |
1807 | ||
1808 | return 0; | |
1809 | } | |
1810 | ||
1811 | #ifdef CONFIG_PM | |
1812 | static int | |
2dc11581 | 1813 | mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state) |
b9272dfd | 1814 | { |
4190390a | 1815 | struct uart_port *port = platform_get_drvdata(op); |
b9272dfd GL |
1816 | |
1817 | if (port) | |
1818 | uart_suspend_port(&mpc52xx_uart_driver, port); | |
1819 | ||
1820 | return 0; | |
1821 | } | |
1822 | ||
1823 | static int | |
2dc11581 | 1824 | mpc52xx_uart_of_resume(struct platform_device *op) |
b9272dfd | 1825 | { |
4190390a | 1826 | struct uart_port *port = platform_get_drvdata(op); |
b9272dfd GL |
1827 | |
1828 | if (port) | |
1829 | uart_resume_port(&mpc52xx_uart_driver, port); | |
1830 | ||
1831 | return 0; | |
1832 | } | |
1833 | #endif | |
1834 | ||
1835 | static void | |
3b5ebf8e | 1836 | mpc52xx_uart_of_assign(struct device_node *np) |
b9272dfd | 1837 | { |
b9272dfd GL |
1838 | int i; |
1839 | ||
3b5ebf8e | 1840 | /* Find the first free PSC number */ |
b9272dfd GL |
1841 | for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { |
1842 | if (mpc52xx_uart_nodes[i] == NULL) { | |
3b5ebf8e GL |
1843 | of_node_get(np); |
1844 | mpc52xx_uart_nodes[i] = np; | |
1845 | return; | |
b9272dfd GL |
1846 | } |
1847 | } | |
b9272dfd GL |
1848 | } |
1849 | ||
1850 | static void | |
1851 | mpc52xx_uart_of_enumerate(void) | |
1852 | { | |
406b7d4f | 1853 | static int enum_done; |
b9272dfd | 1854 | struct device_node *np; |
25ae3a07 | 1855 | const struct of_device_id *match; |
b9272dfd GL |
1856 | int i; |
1857 | ||
1858 | if (enum_done) | |
1859 | return; | |
1860 | ||
3b5ebf8e GL |
1861 | /* Assign index to each PSC in device tree */ |
1862 | for_each_matching_node(np, mpc52xx_uart_of_match) { | |
25ae3a07 | 1863 | match = of_match_node(mpc52xx_uart_of_match, np); |
25ae3a07 | 1864 | psc_ops = match->data; |
3b5ebf8e | 1865 | mpc52xx_uart_of_assign(np); |
b9272dfd GL |
1866 | } |
1867 | ||
1868 | enum_done = 1; | |
1869 | ||
1870 | for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { | |
1871 | if (mpc52xx_uart_nodes[i]) | |
a73ee843 RH |
1872 | pr_debug("%pOF assigned to ttyPSC%x\n", |
1873 | mpc52xx_uart_nodes[i], i); | |
b9272dfd GL |
1874 | } |
1875 | } | |
1876 | ||
1877 | MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match); | |
1878 | ||
793218df | 1879 | static struct platform_driver mpc52xx_uart_of_driver = { |
b9272dfd GL |
1880 | .probe = mpc52xx_uart_of_probe, |
1881 | .remove = mpc52xx_uart_of_remove, | |
1882 | #ifdef CONFIG_PM | |
1883 | .suspend = mpc52xx_uart_of_suspend, | |
1884 | .resume = mpc52xx_uart_of_resume, | |
1885 | #endif | |
4018294b GL |
1886 | .driver = { |
1887 | .name = "mpc52xx-psc-uart", | |
4018294b | 1888 | .of_match_table = mpc52xx_uart_of_match, |
b9272dfd GL |
1889 | }, |
1890 | }; | |
1da177e4 LT |
1891 | |
1892 | ||
1893 | /* ======================================================================== */ | |
1894 | /* Module */ | |
1895 | /* ======================================================================== */ | |
1896 | ||
1897 | static int __init | |
1898 | mpc52xx_uart_init(void) | |
1899 | { | |
1900 | int ret; | |
1901 | ||
b9272dfd | 1902 | printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n"); |
1da177e4 | 1903 | |
406b7d4f JR |
1904 | ret = uart_register_driver(&mpc52xx_uart_driver); |
1905 | if (ret) { | |
b9272dfd GL |
1906 | printk(KERN_ERR "%s: uart_register_driver failed (%i)\n", |
1907 | __FILE__, ret); | |
1908 | return ret; | |
1da177e4 LT |
1909 | } |
1910 | ||
b9272dfd GL |
1911 | mpc52xx_uart_of_enumerate(); |
1912 | ||
6acc6833 AG |
1913 | /* |
1914 | * Map the PSC FIFO Controller and init if on MPC512x. | |
1915 | */ | |
e6114fa1 | 1916 | if (psc_ops && psc_ops->fifoc_init) { |
6acc6833 AG |
1917 | ret = psc_ops->fifoc_init(); |
1918 | if (ret) | |
9bcc3278 | 1919 | goto err_init; |
6acc6833 AG |
1920 | } |
1921 | ||
793218df | 1922 | ret = platform_driver_register(&mpc52xx_uart_of_driver); |
b9272dfd | 1923 | if (ret) { |
793218df | 1924 | printk(KERN_ERR "%s: platform_driver_register failed (%i)\n", |
b9272dfd | 1925 | __FILE__, ret); |
9bcc3278 | 1926 | goto err_reg; |
b9272dfd | 1927 | } |
b9272dfd GL |
1928 | |
1929 | return 0; | |
9bcc3278 WY |
1930 | err_reg: |
1931 | if (psc_ops && psc_ops->fifoc_uninit) | |
1932 | psc_ops->fifoc_uninit(); | |
1933 | err_init: | |
1934 | uart_unregister_driver(&mpc52xx_uart_driver); | |
1935 | return ret; | |
1da177e4 LT |
1936 | } |
1937 | ||
1938 | static void __exit | |
1939 | mpc52xx_uart_exit(void) | |
1940 | { | |
6acc6833 AG |
1941 | if (psc_ops->fifoc_uninit) |
1942 | psc_ops->fifoc_uninit(); | |
1943 | ||
793218df | 1944 | platform_driver_unregister(&mpc52xx_uart_of_driver); |
1da177e4 LT |
1945 | uart_unregister_driver(&mpc52xx_uart_driver); |
1946 | } | |
1947 | ||
1948 | ||
1949 | module_init(mpc52xx_uart_init); | |
1950 | module_exit(mpc52xx_uart_exit); | |
1951 | ||
1952 | MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); | |
1953 | MODULE_DESCRIPTION("Freescale MPC52xx PSC UART"); | |
1954 | MODULE_LICENSE("GPL"); |