[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / mvebu-uart.c

/*
* ***************************************************************************
* Marvell Armada-3700 Serial Driver
* Author: Wilson Ding <dingwei@marvell.com>
* Copyright (C) 2015 Marvell International Ltd.
* ***************************************************************************
* This program is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 2 of the License, or any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program.  If not, see <http://www.gnu.org/licenses/>.
* ***************************************************************************
*/

#include <linux/clk.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>

/* Register Map */
#define UART_RBR		0x00
#define  RBR_BRK_DET		BIT(15)
#define  RBR_FRM_ERR_DET	BIT(14)
#define  RBR_PAR_ERR_DET	BIT(13)
#define  RBR_OVR_ERR_DET	BIT(12)

#define UART_TSH		0x04

#define UART_CTRL		0x08
#define  CTRL_SOFT_RST		BIT(31)
#define  CTRL_TXFIFO_RST	BIT(15)
#define  CTRL_RXFIFO_RST	BIT(14)
#define  CTRL_ST_MIRR_EN	BIT(13)
#define  CTRL_LPBK_EN		BIT(12)
#define  CTRL_SND_BRK_SEQ	BIT(11)
#define  CTRL_PAR_EN		BIT(10)
#define  CTRL_TWO_STOP		BIT(9)
#define  CTRL_TX_HFL_INT	BIT(8)
#define  CTRL_RX_HFL_INT	BIT(7)
#define  CTRL_TX_EMP_INT	BIT(6)
#define  CTRL_TX_RDY_INT	BIT(5)
#define  CTRL_RX_RDY_INT	BIT(4)
#define  CTRL_BRK_DET_INT	BIT(3)
#define  CTRL_FRM_ERR_INT	BIT(2)
#define  CTRL_PAR_ERR_INT	BIT(1)
#define  CTRL_OVR_ERR_INT	BIT(0)
#define  CTRL_RX_INT			(CTRL_RX_RDY_INT | CTRL_BRK_DET_INT |\
	CTRL_FRM_ERR_INT | CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)

#define UART_STAT		0x0c
#define  STAT_TX_FIFO_EMP	BIT(13)
#define  STAT_RX_FIFO_EMP	BIT(12)
#define  STAT_TX_FIFO_FUL	BIT(11)
#define  STAT_TX_FIFO_HFL	BIT(10)
#define  STAT_RX_TOGL		BIT(9)
#define  STAT_RX_FIFO_FUL	BIT(8)
#define  STAT_RX_FIFO_HFL	BIT(7)
#define  STAT_TX_EMP		BIT(6)
#define  STAT_TX_RDY		BIT(5)
#define  STAT_RX_RDY		BIT(4)
#define  STAT_BRK_DET		BIT(3)
#define  STAT_FRM_ERR		BIT(2)
#define  STAT_PAR_ERR		BIT(1)
#define  STAT_OVR_ERR		BIT(0)
#define  STAT_BRK_ERR		(STAT_BRK_DET | STAT_FRM_ERR | STAT_FRM_ERR\
				 | STAT_PAR_ERR | STAT_OVR_ERR)

#define UART_BRDV		0x10

#define MVEBU_NR_UARTS		1

#define MVEBU_UART_TYPE		"mvebu-uart"

static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];

struct mvebu_uart_data {
	struct uart_port *port;
	struct clk       *clk;
};

/* Core UART Driver Operations */
static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
{
	unsigned long flags;
	unsigned int st;

	spin_lock_irqsave(&port->lock, flags);
	st = readl(port->membase + UART_STAT);
	spin_unlock_irqrestore(&port->lock, flags);

	return (st & STAT_TX_FIFO_EMP) ? TIOCSER_TEMT : 0;
}

static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
{
	return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
}

static void mvebu_uart_set_mctrl(struct uart_port *port,
				 unsigned int mctrl)
{
/*
 * Even if we do not support configuring the modem control lines, this
 * function must be proided to the serial core
 */
}

static void mvebu_uart_stop_tx(struct uart_port *port)
{
	unsigned int ctl = readl(port->membase + UART_CTRL);

	ctl &= ~CTRL_TX_RDY_INT;
	writel(ctl, port->membase + UART_CTRL);
}

static void mvebu_uart_start_tx(struct uart_port *port)
{
	unsigned int ctl = readl(port->membase + UART_CTRL);

	ctl |= CTRL_TX_RDY_INT;
	writel(ctl, port->membase + UART_CTRL);
}

static void mvebu_uart_stop_rx(struct uart_port *port)
{
	unsigned int ctl = readl(port->membase + UART_CTRL);

	ctl &= ~CTRL_RX_INT;
	writel(ctl, port->membase + UART_CTRL);
}

static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
{
	unsigned int ctl;
	unsigned long flags;

	spin_lock_irqsave(&port->lock, flags);
	ctl = readl(port->membase + UART_CTRL);
	if (brk == -1)
		ctl |= CTRL_SND_BRK_SEQ;
	else
		ctl &= ~CTRL_SND_BRK_SEQ;
	writel(ctl, port->membase + UART_CTRL);
	spin_unlock_irqrestore(&port->lock, flags);
}

static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
{
	struct tty_port *tport = &port->state->port;
	unsigned char ch = 0;
	char flag = 0;

	do {
		if (status & STAT_RX_RDY) {
			ch = readl(port->membase + UART_RBR);
			ch &= 0xff;
			flag = TTY_NORMAL;
			port->icount.rx++;

			if (status & STAT_PAR_ERR)
				port->icount.parity++;
		}

		if (status & STAT_BRK_DET) {
			port->icount.brk++;
			status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
			if (uart_handle_break(port))
				goto ignore_char;
		}

		if (status & STAT_OVR_ERR)
			port->icount.overrun++;

		if (status & STAT_FRM_ERR)
			port->icount.frame++;

		if (uart_handle_sysrq_char(port, ch))
			goto ignore_char;

		if (status & port->ignore_status_mask & STAT_PAR_ERR)
			status &= ~STAT_RX_RDY;

		status &= port->read_status_mask;

		if (status & STAT_PAR_ERR)
			flag = TTY_PARITY;

		status &= ~port->ignore_status_mask;

		if (status & STAT_RX_RDY)
			tty_insert_flip_char(tport, ch, flag);

		if (status & STAT_BRK_DET)
			tty_insert_flip_char(tport, 0, TTY_BREAK);

		if (status & STAT_FRM_ERR)
			tty_insert_flip_char(tport, 0, TTY_FRAME);

		if (status & STAT_OVR_ERR)
			tty_insert_flip_char(tport, 0, TTY_OVERRUN);

ignore_char:
		status = readl(port->membase + UART_STAT);
	} while (status & (STAT_RX_RDY | STAT_BRK_DET));

	tty_flip_buffer_push(tport);
}

static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
{
	struct circ_buf *xmit = &port->state->xmit;
	unsigned int count;
	unsigned int st;

	if (port->x_char) {
		writel(port->x_char, port->membase + UART_TSH);
		port->icount.tx++;
		port->x_char = 0;
		return;
	}

	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
		mvebu_uart_stop_tx(port);
		return;
	}

	for (count = 0; count < port->fifosize; count++) {
		writel(xmit->buf[xmit->tail], port->membase + UART_TSH);
		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
		port->icount.tx++;

		if (uart_circ_empty(xmit))
			break;

		st = readl(port->membase + UART_STAT);
		if (st & STAT_TX_FIFO_FUL)
			break;
	}

	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	if (uart_circ_empty(xmit))
		mvebu_uart_stop_tx(port);
}

static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
{
	struct uart_port *port = (struct uart_port *)dev_id;
	unsigned int st = readl(port->membase + UART_STAT);

	if (st & (STAT_RX_RDY | STAT_OVR_ERR | STAT_FRM_ERR | STAT_BRK_DET))
		mvebu_uart_rx_chars(port, st);

	if (st & STAT_TX_RDY)
		mvebu_uart_tx_chars(port, st);

	return IRQ_HANDLED;
}

static int mvebu_uart_startup(struct uart_port *port)
{
	int ret;

	writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
	       port->membase + UART_CTRL);
	udelay(1);
	writel(CTRL_RX_INT, port->membase + UART_CTRL);

	ret = request_irq(port->irq, mvebu_uart_isr, port->irqflags, "serial",
			  port);
	if (ret) {
		dev_err(port->dev, "failed to request irq\n");
		return ret;
	}

	return 0;
}

static void mvebu_uart_shutdown(struct uart_port *port)
{
	writel(0, port->membase + UART_CTRL);

	free_irq(port->irq, port);
}

static void mvebu_uart_set_termios(struct uart_port *port,
				   struct ktermios *termios,
				   struct ktermios *old)
{
	unsigned long flags;
	unsigned int baud;

	spin_lock_irqsave(&port->lock, flags);

	port->read_status_mask = STAT_RX_RDY | STAT_OVR_ERR |
		STAT_TX_RDY | STAT_TX_FIFO_FUL;

	if (termios->c_iflag & INPCK)
		port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;

	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |=
			STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;

	if ((termios->c_cflag & CREAD) == 0)
		port->ignore_status_mask |= STAT_RX_RDY | STAT_BRK_ERR;

	if (old)
		tty_termios_copy_hw(termios, old);

	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	uart_update_timeout(port, termios->c_cflag, baud);

	spin_unlock_irqrestore(&port->lock, flags);
}

static const char *mvebu_uart_type(struct uart_port *port)
{
	return MVEBU_UART_TYPE;
}

static void mvebu_uart_release_port(struct uart_port *port)
{
	/* Nothing to do here */
}

static int mvebu_uart_request_port(struct uart_port *port)
{
	return 0;
}

#ifdef CONFIG_CONSOLE_POLL
static int mvebu_uart_get_poll_char(struct uart_port *port)
{
	unsigned int st = readl(port->membase + UART_STAT);

	if (!(st & STAT_RX_RDY))
		return NO_POLL_CHAR;

	return readl(port->membase + UART_RBR);
}

static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
{
	unsigned int st;

	for (;;) {
		st = readl(port->membase + UART_STAT);

		if (!(st & STAT_TX_FIFO_FUL))
			break;

		udelay(1);
	}

	writel(c, port->membase + UART_TSH);
}
#endif

static const struct uart_ops mvebu_uart_ops = {
	.tx_empty	= mvebu_uart_tx_empty,
	.set_mctrl	= mvebu_uart_set_mctrl,
	.get_mctrl	= mvebu_uart_get_mctrl,
	.stop_tx	= mvebu_uart_stop_tx,
	.start_tx	= mvebu_uart_start_tx,
	.stop_rx	= mvebu_uart_stop_rx,
	.break_ctl	= mvebu_uart_break_ctl,
	.startup	= mvebu_uart_startup,
	.shutdown	= mvebu_uart_shutdown,
	.set_termios	= mvebu_uart_set_termios,
	.type		= mvebu_uart_type,
	.release_port	= mvebu_uart_release_port,
	.request_port	= mvebu_uart_request_port,
#ifdef CONFIG_CONSOLE_POLL
	.poll_get_char	= mvebu_uart_get_poll_char,
	.poll_put_char	= mvebu_uart_put_poll_char,
#endif
};

/* Console Driver Operations  */

#ifdef CONFIG_SERIAL_MVEBU_CONSOLE
/* Early Console */
static void mvebu_uart_putc(struct uart_port *port, int c)
{
	unsigned int st;

	for (;;) {
		st = readl(port->membase + UART_STAT);
		if (!(st & STAT_TX_FIFO_FUL))
			break;
	}

	writel(c, port->membase + UART_TSH);

	for (;;) {
		st = readl(port->membase + UART_STAT);
		if (st & STAT_TX_FIFO_EMP)
			break;
	}
}

static void mvebu_uart_putc_early_write(struct console *con,
					const char *s,
					unsigned n)
{
	struct earlycon_device *dev = con->data;

	uart_console_write(&dev->port, s, n, mvebu_uart_putc);
}

static int __init
mvebu_uart_early_console_setup(struct earlycon_device *device,
			       const char *opt)
{
	if (!device->port.membase)
		return -ENODEV;

	device->con->write = mvebu_uart_putc_early_write;

	return 0;
}

EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
		    mvebu_uart_early_console_setup);

static void wait_for_xmitr(struct uart_port *port)
{
	u32 val;

	readl_poll_timeout_atomic(port->membase + UART_STAT, val,
				  (val & STAT_TX_EMP), 1, 10000);
}

static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
{
	wait_for_xmitr(port);
	writel(ch, port->membase + UART_TSH);
}

static void mvebu_uart_console_write(struct console *co, const char *s,
				     unsigned int count)
{
	struct uart_port *port = &mvebu_uart_ports[co->index];
	unsigned long flags;
	unsigned int ier;
	int locked = 1;

	if (oops_in_progress)
		locked = spin_trylock_irqsave(&port->lock, flags);
	else
		spin_lock_irqsave(&port->lock, flags);

	ier = readl(port->membase + UART_CTRL) &
		(CTRL_RX_INT | CTRL_TX_RDY_INT);
	writel(0, port->membase + UART_CTRL);

	uart_console_write(port, s, count, mvebu_uart_console_putchar);

	wait_for_xmitr(port);

	if (ier)
		writel(ier, port->membase + UART_CTRL);

	if (locked)
		spin_unlock_irqrestore(&port->lock, flags);
}

static int mvebu_uart_console_setup(struct console *co, char *options)
{
	struct uart_port *port;
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
		return -EINVAL;

	port = &mvebu_uart_ports[co->index];

	if (!port->mapbase || !port->membase) {
		pr_debug("console on ttyMV%i not present\n", co->index);
		return -ENODEV;
	}

	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);

	return uart_set_options(port, co, baud, parity, bits, flow);
}

static struct uart_driver mvebu_uart_driver;

static struct console mvebu_uart_console = {
	.name	= "ttyMV",
	.write	= mvebu_uart_console_write,
	.device	= uart_console_device,
	.setup	= mvebu_uart_console_setup,
	.flags	= CON_PRINTBUFFER,
	.index	= -1,
	.data	= &mvebu_uart_driver,
};

static int __init mvebu_uart_console_init(void)
{
	register_console(&mvebu_uart_console);
	return 0;
}

console_initcall(mvebu_uart_console_init);


#endif /* CONFIG_SERIAL_MVEBU_CONSOLE */

static struct uart_driver mvebu_uart_driver = {
	.owner			= THIS_MODULE,
	.driver_name		= "mvebu_serial",
	.dev_name		= "ttyMV",
	.nr			= MVEBU_NR_UARTS,
#ifdef CONFIG_SERIAL_MVEBU_CONSOLE
	.cons			= &mvebu_uart_console,
#endif
};

static int mvebu_uart_probe(struct platform_device *pdev)
{
	struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	struct uart_port *port;
	struct mvebu_uart_data *data;
	int ret;

	if (!reg || !irq) {
		dev_err(&pdev->dev, "no registers/irq defined\n");
		return -EINVAL;
	}

	port = &mvebu_uart_ports[0];

	spin_lock_init(&port->lock);

	port->dev        = &pdev->dev;
	port->type       = PORT_MVEBU;
	port->ops        = &mvebu_uart_ops;
	port->regshift   = 0;

	port->fifosize   = 32;
	port->iotype     = UPIO_MEM32;
	port->flags      = UPF_FIXED_PORT;
	port->line       = 0; /* single port: force line number to  0 */

	port->irq        = irq->start;
	port->irqflags   = 0;
	port->mapbase    = reg->start;

	port->membase = devm_ioremap_resource(&pdev->dev, reg);
	if (IS_ERR(port->membase))
		return -PTR_ERR(port->membase);

	data = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart_data),
			    GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->port = port;

	port->private_data = data;
	platform_set_drvdata(pdev, data);

	ret = uart_add_one_port(&mvebu_uart_driver, port);
	if (ret)
		return ret;
	return 0;
}

/* Match table for of_platform binding */
static const struct of_device_id mvebu_uart_of_match[] = {
	{ .compatible = "marvell,armada-3700-uart", },
	{}
};

static struct platform_driver mvebu_uart_platform_driver = {
	.probe	= mvebu_uart_probe,
	.driver	= {
		.name  = "mvebu-uart",
		.of_match_table = of_match_ptr(mvebu_uart_of_match),
		.suppress_bind_attrs = true,
	},
};

static int __init mvebu_uart_init(void)
{
	int ret;

	ret = uart_register_driver(&mvebu_uart_driver);
	if (ret)
		return ret;

	ret = platform_driver_register(&mvebu_uart_platform_driver);
	if (ret)
		uart_unregister_driver(&mvebu_uart_driver);

	return ret;
}
arch_initcall(mvebu_uart_init);
Commit	Line	Data
30530791 WD	1	/*
30530791 WD	2	* ***************************************************************************
89ebc274 PG	3	* Marvell Armada-3700 Serial Driver
89ebc274 PG	4	* Author: Wilson Ding <dingwei@marvell.com>
30530791 WD	5	* Copyright (C) 2015 Marvell International Ltd.
	6	* ***************************************************************************
	7	* This program is free software: you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the Free
	9	* Software Foundation, either version 2 of the License, or any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	* ***************************************************************************
	19	*/
	20
	21	#include <linux/clk.h>
	22	#include <linux/console.h>
	23	#include <linux/delay.h>
	24	#include <linux/device.h>
	25	#include <linux/init.h>
	26	#include <linux/io.h>
	27	#include <linux/iopoll.h>
30530791 WD	28	#include <linux/of.h>
	29	#include <linux/of_address.h>
	30	#include <linux/of_device.h>
	31	#include <linux/of_irq.h>
	32	#include <linux/of_platform.h>
	33	#include <linux/platform_device.h>
	34	#include <linux/serial.h>
	35	#include <linux/serial_core.h>
	36	#include <linux/slab.h>
	37	#include <linux/tty.h>
	38	#include <linux/tty_flip.h>
	39
	40	/* Register Map */
	41	#define UART_RBR 0x00
	42	#define RBR_BRK_DET BIT(15)
	43	#define RBR_FRM_ERR_DET BIT(14)
	44	#define RBR_PAR_ERR_DET BIT(13)
	45	#define RBR_OVR_ERR_DET BIT(12)
	46
	47	#define UART_TSH 0x04
	48
	49	#define UART_CTRL 0x08
	50	#define CTRL_SOFT_RST BIT(31)
	51	#define CTRL_TXFIFO_RST BIT(15)
	52	#define CTRL_RXFIFO_RST BIT(14)
	53	#define CTRL_ST_MIRR_EN BIT(13)
	54	#define CTRL_LPBK_EN BIT(12)
	55	#define CTRL_SND_BRK_SEQ BIT(11)
	56	#define CTRL_PAR_EN BIT(10)
	57	#define CTRL_TWO_STOP BIT(9)
	58	#define CTRL_TX_HFL_INT BIT(8)
	59	#define CTRL_RX_HFL_INT BIT(7)
	60	#define CTRL_TX_EMP_INT BIT(6)
	61	#define CTRL_TX_RDY_INT BIT(5)
	62	#define CTRL_RX_RDY_INT BIT(4)
	63	#define CTRL_BRK_DET_INT BIT(3)
	64	#define CTRL_FRM_ERR_INT BIT(2)
	65	#define CTRL_PAR_ERR_INT BIT(1)
	66	#define CTRL_OVR_ERR_INT BIT(0)
	67	#define CTRL_RX_INT (CTRL_RX_RDY_INT \| CTRL_BRK_DET_INT \|\
	68	CTRL_FRM_ERR_INT \| CTRL_PAR_ERR_INT \| CTRL_OVR_ERR_INT)
	69
	70	#define UART_STAT 0x0c
	71	#define STAT_TX_FIFO_EMP BIT(13)
	72	#define STAT_RX_FIFO_EMP BIT(12)
	73	#define STAT_TX_FIFO_FUL BIT(11)
	74	#define STAT_TX_FIFO_HFL BIT(10)
	75	#define STAT_RX_TOGL BIT(9)
	76	#define STAT_RX_FIFO_FUL BIT(8)
	77	#define STAT_RX_FIFO_HFL BIT(7)
	78	#define STAT_TX_EMP BIT(6)
	79	#define STAT_TX_RDY BIT(5)
	80	#define STAT_RX_RDY BIT(4)
	81	#define STAT_BRK_DET BIT(3)
	82	#define STAT_FRM_ERR BIT(2)
	83	#define STAT_PAR_ERR BIT(1)
	84	#define STAT_OVR_ERR BIT(0)
	85	#define STAT_BRK_ERR (STAT_BRK_DET \| STAT_FRM_ERR \| STAT_FRM_ERR\
	86	\| STAT_PAR_ERR \| STAT_OVR_ERR)
	87
	88	#define UART_BRDV 0x10
	89
	90	#define MVEBU_NR_UARTS 1
	91
92	#define MVEBU_UART_TYPE "mvebu-uart"
93
94	static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
95
96	struct mvebu_uart_data {
97	struct uart_port *port;
98	struct clk *clk;
99	};
100
101	/* Core UART Driver Operations */
102	static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
103	{
104	unsigned long flags;
105	unsigned int st;
106
107	spin_lock_irqsave(&port->lock, flags);
108	st = readl(port->membase + UART_STAT);
109	spin_unlock_irqrestore(&port->lock, flags);
110
111	return (st & STAT_TX_FIFO_EMP) ? TIOCSER_TEMT : 0;
112	}
113
114	static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
115	{
116	return TIOCM_CTS \| TIOCM_DSR \| TIOCM_CAR;
117	}
118
119	static void mvebu_uart_set_mctrl(struct uart_port *port,
120	unsigned int mctrl)
121	{
122	/*
123	* Even if we do not support configuring the modem control lines, this
124	* function must be proided to the serial core
125	*/
126	}
127
128	static void mvebu_uart_stop_tx(struct uart_port *port)
129	{
130	unsigned int ctl = readl(port->membase + UART_CTRL);
131
132	ctl &= ~CTRL_TX_RDY_INT;
133	writel(ctl, port->membase + UART_CTRL);
134	}
135
136	static void mvebu_uart_start_tx(struct uart_port *port)
137	{
138	unsigned int ctl = readl(port->membase + UART_CTRL);
139
140	ctl \|= CTRL_TX_RDY_INT;
141	writel(ctl, port->membase + UART_CTRL);
142	}
143
144	static void mvebu_uart_stop_rx(struct uart_port *port)
145	{
146	unsigned int ctl = readl(port->membase + UART_CTRL);
147
148	ctl &= ~CTRL_RX_INT;
149	writel(ctl, port->membase + UART_CTRL);
150	}
151
152	static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
153	{
154	unsigned int ctl;
155	unsigned long flags;
156
157	spin_lock_irqsave(&port->lock, flags);
158	ctl = readl(port->membase + UART_CTRL);
159	if (brk == -1)
160	ctl \|= CTRL_SND_BRK_SEQ;
161	else
162	ctl &= ~CTRL_SND_BRK_SEQ;
163	writel(ctl, port->membase + UART_CTRL);
164	spin_unlock_irqrestore(&port->lock, flags);
165	}
166
167	static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
168	{
169	struct tty_port *tport = &port->state->port;
170	unsigned char ch = 0;
171	char flag = 0;
172
173	do {
174	if (status & STAT_RX_RDY) {
175	ch = readl(port->membase + UART_RBR);
176	ch &= 0xff;
177	flag = TTY_NORMAL;
178	port->icount.rx++;
179
180	if (status & STAT_PAR_ERR)
181	port->icount.parity++;
182	}
183
184	if (status & STAT_BRK_DET) {
185	port->icount.brk++;
186	status &= ~(STAT_FRM_ERR \| STAT_PAR_ERR);
187	if (uart_handle_break(port))
188	goto ignore_char;
189	}
190
191	if (status & STAT_OVR_ERR)
192	port->icount.overrun++;
193
194	if (status & STAT_FRM_ERR)
195	port->icount.frame++;
196
197	if (uart_handle_sysrq_char(port, ch))
198	goto ignore_char;
199
200	if (status & port->ignore_status_mask & STAT_PAR_ERR)
201	status &= ~STAT_RX_RDY;
202
203	status &= port->read_status_mask;
204
205	if (status & STAT_PAR_ERR)
206	flag = TTY_PARITY;
207
208	status &= ~port->ignore_status_mask;
209
210	if (status & STAT_RX_RDY)
211	tty_insert_flip_char(tport, ch, flag);
212
213	if (status & STAT_BRK_DET)
214	tty_insert_flip_char(tport, 0, TTY_BREAK);
215
216	if (status & STAT_FRM_ERR)
217	tty_insert_flip_char(tport, 0, TTY_FRAME);
218
219	if (status & STAT_OVR_ERR)
220	tty_insert_flip_char(tport, 0, TTY_OVERRUN);
221
222	ignore_char:
223	status = readl(port->membase + UART_STAT);
224	} while (status & (STAT_RX_RDY \| STAT_BRK_DET));
225
226	tty_flip_buffer_push(tport);
227	}
228
229	static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
230	{
231	struct circ_buf *xmit = &port->state->xmit;
232	unsigned int count;
233	unsigned int st;
234
235	if (port->x_char) {
236	writel(port->x_char, port->membase + UART_TSH);
237	port->icount.tx++;
238	port->x_char = 0;
239	return;
240	}
241
242	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
243	mvebu_uart_stop_tx(port);
244	return;
245	}
246
247	for (count = 0; count < port->fifosize; count++) {
248	writel(xmit->buf[xmit->tail], port->membase + UART_TSH);
249	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
250	port->icount.tx++;
251
252	if (uart_circ_empty(xmit))
253	break;
254
255	st = readl(port->membase + UART_STAT);
256	if (st & STAT_TX_FIFO_FUL)
257	break;
258	}
259
260	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
261	uart_write_wakeup(port);
262
263	if (uart_circ_empty(xmit))
264	mvebu_uart_stop_tx(port);
265	}
266
267	static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
268	{
269	struct uart_port port = (struct uart_port )dev_id;
270	unsigned int st = readl(port->membase + UART_STAT);
271
272	if (st & (STAT_RX_RDY \| STAT_OVR_ERR \| STAT_FRM_ERR \| STAT_BRK_DET))
273	mvebu_uart_rx_chars(port, st);
274
275	if (st & STAT_TX_RDY)
276	mvebu_uart_tx_chars(port, st);
277
278	return IRQ_HANDLED;
279	}
280
281	static int mvebu_uart_startup(struct uart_port *port)
282	{
283	int ret;
284
285	writel(CTRL_TXFIFO_RST \| CTRL_RXFIFO_RST,
286	port->membase + UART_CTRL);
287	udelay(1);
288	writel(CTRL_RX_INT, port->membase + UART_CTRL);
289
290	ret = request_irq(port->irq, mvebu_uart_isr, port->irqflags, "serial",
291	port);
292	if (ret) {
293	dev_err(port->dev, "failed to request irq\n");
294	return ret;
295	}
296
297	return 0;
298	}
299
300	static void mvebu_uart_shutdown(struct uart_port *port)
301	{
302	writel(0, port->membase + UART_CTRL);
c2c1659b TP	303
c2c1659b TP	304	free_irq(port->irq, port);
30530791 WD	305	}
	306
	307	static void mvebu_uart_set_termios(struct uart_port *port,
	308	struct ktermios *termios,
	309	struct ktermios *old)
	310	{
	311	unsigned long flags;
	312	unsigned int baud;
	313
	314	spin_lock_irqsave(&port->lock, flags);
	315
	316	port->read_status_mask = STAT_RX_RDY \| STAT_OVR_ERR \|
	317	STAT_TX_RDY \| STAT_TX_FIFO_FUL;
	318
	319	if (termios->c_iflag & INPCK)
	320	port->read_status_mask \|= STAT_FRM_ERR \| STAT_PAR_ERR;
	321
	322	port->ignore_status_mask = 0;
	323	if (termios->c_iflag & IGNPAR)
	324	port->ignore_status_mask \|=
	325	STAT_FRM_ERR \| STAT_PAR_ERR \| STAT_OVR_ERR;
	326
	327	if ((termios->c_cflag & CREAD) == 0)
	328	port->ignore_status_mask \|= STAT_RX_RDY \| STAT_BRK_ERR;
	329
	330	if (old)
	331	tty_termios_copy_hw(termios, old);
	332
	333	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	334	uart_update_timeout(port, termios->c_cflag, baud);
	335
	336	spin_unlock_irqrestore(&port->lock, flags);
	337	}
	338
	339	static const char mvebu_uart_type(struct uart_port port)
	340	{
	341	return MVEBU_UART_TYPE;
	342	}
	343
	344	static void mvebu_uart_release_port(struct uart_port *port)
	345	{
	346	/* Nothing to do here */
	347	}
	348
	349	static int mvebu_uart_request_port(struct uart_port *port)
	350	{
	351	return 0;
	352	}
	353
	354	#ifdef CONFIG_CONSOLE_POLL
	355	static int mvebu_uart_get_poll_char(struct uart_port *port)
	356	{
	357	unsigned int st = readl(port->membase + UART_STAT);
	358
	359	if (!(st & STAT_RX_RDY))
	360	return NO_POLL_CHAR;
	361
	362	return readl(port->membase + UART_RBR);
	363	}
	364
	365	static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
	366	{
	367	unsigned int st;
	368
369	for (;;) {
370	st = readl(port->membase + UART_STAT);
371
372	if (!(st & STAT_TX_FIFO_FUL))
373	break;
374
375	udelay(1);
376	}
377
378	writel(c, port->membase + UART_TSH);
379	}
380	#endif
381
382	static const struct uart_ops mvebu_uart_ops = {
383	.tx_empty = mvebu_uart_tx_empty,
384	.set_mctrl = mvebu_uart_set_mctrl,
385	.get_mctrl = mvebu_uart_get_mctrl,
386	.stop_tx = mvebu_uart_stop_tx,
387	.start_tx = mvebu_uart_start_tx,
388	.stop_rx = mvebu_uart_stop_rx,
389	.break_ctl = mvebu_uart_break_ctl,
390	.startup = mvebu_uart_startup,
391	.shutdown = mvebu_uart_shutdown,
392	.set_termios = mvebu_uart_set_termios,
393	.type = mvebu_uart_type,
394	.release_port = mvebu_uart_release_port,
395	.request_port = mvebu_uart_request_port,
396	#ifdef CONFIG_CONSOLE_POLL
397	.poll_get_char = mvebu_uart_get_poll_char,
398	.poll_put_char = mvebu_uart_put_poll_char,
399	#endif
400	};
401
402	/* Console Driver Operations */
403
404	#ifdef CONFIG_SERIAL_MVEBU_CONSOLE
405	/* Early Console */
406	static void mvebu_uart_putc(struct uart_port *port, int c)
407	{
408	unsigned int st;
409
410	for (;;) {
411	st = readl(port->membase + UART_STAT);
412	if (!(st & STAT_TX_FIFO_FUL))
413	break;
414	}
415
416	writel(c, port->membase + UART_TSH);
417
418	for (;;) {
419	st = readl(port->membase + UART_STAT);
420	if (st & STAT_TX_FIFO_EMP)
421	break;
422	}
423	}
424
425	static void mvebu_uart_putc_early_write(struct console *con,
426	const char *s,
427	unsigned n)
428	{
429	struct earlycon_device *dev = con->data;
430
431	uart_console_write(&dev->port, s, n, mvebu_uart_putc);
432	}
433
434	static int __init
435	mvebu_uart_early_console_setup(struct earlycon_device *device,
436	const char *opt)
437	{
438	if (!device->port.membase)
439	return -ENODEV;
440
441	device->con->write = mvebu_uart_putc_early_write;
442
443	return 0;
444	}
445
446	EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
447	OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
448	mvebu_uart_early_console_setup);
449
450	static void wait_for_xmitr(struct uart_port *port)
451	{
452	u32 val;
453
454	readl_poll_timeout_atomic(port->membase + UART_STAT, val,
455	(val & STAT_TX_EMP), 1, 10000);
456	}
457
458	static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
459	{
460	wait_for_xmitr(port);
461	writel(ch, port->membase + UART_TSH);
462	}
463
464	static void mvebu_uart_console_write(struct console co, const char s,
465	unsigned int count)
466	{
467	struct uart_port *port = &mvebu_uart_ports[co->index];
468	unsigned long flags;
469	unsigned int ier;
470	int locked = 1;
471
472	if (oops_in_progress)
473	locked = spin_trylock_irqsave(&port->lock, flags);
474	else
475	spin_lock_irqsave(&port->lock, flags);
476
477	ier = readl(port->membase + UART_CTRL) &
478	(CTRL_RX_INT \| CTRL_TX_RDY_INT);
479	writel(0, port->membase + UART_CTRL);
480
481	uart_console_write(port, s, count, mvebu_uart_console_putchar);
482
483	wait_for_xmitr(port);
484
485	if (ier)
486	writel(ier, port->membase + UART_CTRL);
487
488	if (locked)
489	spin_unlock_irqrestore(&port->lock, flags);
490	}
491
492	static int mvebu_uart_console_setup(struct console co, char options)
493	{
494	struct uart_port *port;
495	int baud = 9600;
496	int bits = 8;
497	int parity = 'n';
498	int flow = 'n';
499
500	if (co->index < 0 \|\| co->index >= MVEBU_NR_UARTS)
501	return -EINVAL;
502
503	port = &mvebu_uart_ports[co->index];
504
505	if (!port->mapbase \|\| !port->membase) {
506	pr_debug("console on ttyMV%i not present\n", co->index);
507	return -ENODEV;
508	}
509
510	if (options)
511	uart_parse_options(options, &baud, &parity, &bits, &flow);
512
513	return uart_set_options(port, co, baud, parity, bits, flow);
514	}
515
516	static struct uart_driver mvebu_uart_driver;
517
518	static struct console mvebu_uart_console = {
519	.name = "ttyMV",
520	.write = mvebu_uart_console_write,
521	.device = uart_console_device,
522	.setup = mvebu_uart_console_setup,
523	.flags = CON_PRINTBUFFER,
524	.index = -1,
525	.data = &mvebu_uart_driver,
526	};
527
528	static int __init mvebu_uart_console_init(void)
529	{
530	register_console(&mvebu_uart_console);
531	return 0;
532	}
533
534	console_initcall(mvebu_uart_console_init);
535
536
537	#endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
538
539	static struct uart_driver mvebu_uart_driver = {
540	.owner = THIS_MODULE,
541	.driver_name = "mvebu_serial",
542	.dev_name = "ttyMV",
543	.nr = MVEBU_NR_UARTS,
544	#ifdef CONFIG_SERIAL_MVEBU_CONSOLE
545	.cons = &mvebu_uart_console,
546	#endif
547	};
548
549	static int mvebu_uart_probe(struct platform_device *pdev)
550	{
551	struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
552	struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
553	struct uart_port *port;
554	struct mvebu_uart_data *data;
555	int ret;
556
557	if (!reg \|\| !irq) {
558	dev_err(&pdev->dev, "no registers/irq defined\n");
559	return -EINVAL;
560	}
561
562	port = &mvebu_uart_ports[0];
563
564	spin_lock_init(&port->lock);
565
566	port->dev = &pdev->dev;
567	port->type = PORT_MVEBU;
568	port->ops = &mvebu_uart_ops;
569	port->regshift = 0;
570
571	port->fifosize = 32;
572	port->iotype = UPIO_MEM32;
573	port->flags = UPF_FIXED_PORT;
574	port->line = 0; /* single port: force line number to 0 */
575
576	port->irq = irq->start;
577	port->irqflags = 0;
578	port->mapbase = reg->start;
579
580	port->membase = devm_ioremap_resource(&pdev->dev, reg);
581	if (IS_ERR(port->membase))
582	return -PTR_ERR(port->membase);
583
584	data = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart_data),
585	GFP_KERNEL);
586	if (!data)
587	return -ENOMEM;
588
589	data->port = port;
590
591	port->private_data = data;
592	platform_set_drvdata(pdev, data);
593
594	ret = uart_add_one_port(&mvebu_uart_driver, port);
595	if (ret)
596	return ret;
597	return 0;
598	}
599
30530791 WD	600	/* Match table for of_platform binding */
	601	static const struct of_device_id mvebu_uart_of_match[] = {
	602	{ .compatible = "marvell,armada-3700-uart", },
	603	{}
	604	};
30530791 WD	605
	606	static struct platform_driver mvebu_uart_platform_driver = {
	607	.probe = mvebu_uart_probe,
30530791	608	.driver = {
30530791 WD	609	.name = "mvebu-uart",
30530791 WD	610	.of_match_table = of_match_ptr(mvebu_uart_of_match),
89ebc274	611	.suppress_bind_attrs = true,
30530791 WD	612	},
	613	};
	614
	615	static int __init mvebu_uart_init(void)
	616	{
	617	int ret;
	618
	619	ret = uart_register_driver(&mvebu_uart_driver);
	620	if (ret)
	621	return ret;
	622
	623	ret = platform_driver_register(&mvebu_uart_platform_driver);
	624	if (ret)
	625	uart_unregister_driver(&mvebu_uart_driver);
	626
	627	return ret;
	628	}
30530791	629	arch_initcall(mvebu_uart_init);