[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / mvebu-uart.c

/*
* ***************************************************************************
* Copyright (C) 2015 Marvell International Ltd.
* ***************************************************************************
* This program is free software: you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 2 of the License, or any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program.  If not, see <http://www.gnu.org/licenses/>.
* ***************************************************************************
*/

#include <linux/clk.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>

/* Register Map */
#define UART_RBR		0x00
#define  RBR_BRK_DET		BIT(15)
#define  RBR_FRM_ERR_DET	BIT(14)
#define  RBR_PAR_ERR_DET	BIT(13)
#define  RBR_OVR_ERR_DET	BIT(12)

#define UART_TSH		0x04

#define UART_CTRL		0x08
#define  CTRL_SOFT_RST		BIT(31)
#define  CTRL_TXFIFO_RST	BIT(15)
#define  CTRL_RXFIFO_RST	BIT(14)
#define  CTRL_ST_MIRR_EN	BIT(13)
#define  CTRL_LPBK_EN		BIT(12)
#define  CTRL_SND_BRK_SEQ	BIT(11)
#define  CTRL_PAR_EN		BIT(10)
#define  CTRL_TWO_STOP		BIT(9)
#define  CTRL_TX_HFL_INT	BIT(8)
#define  CTRL_RX_HFL_INT	BIT(7)
#define  CTRL_TX_EMP_INT	BIT(6)
#define  CTRL_TX_RDY_INT	BIT(5)
#define  CTRL_RX_RDY_INT	BIT(4)
#define  CTRL_BRK_DET_INT	BIT(3)
#define  CTRL_FRM_ERR_INT	BIT(2)
#define  CTRL_PAR_ERR_INT	BIT(1)
#define  CTRL_OVR_ERR_INT	BIT(0)
#define  CTRL_RX_INT			(CTRL_RX_RDY_INT | CTRL_BRK_DET_INT |\
	CTRL_FRM_ERR_INT | CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)

#define UART_STAT		0x0c
#define  STAT_TX_FIFO_EMP	BIT(13)
#define  STAT_RX_FIFO_EMP	BIT(12)
#define  STAT_TX_FIFO_FUL	BIT(11)
#define  STAT_TX_FIFO_HFL	BIT(10)
#define  STAT_RX_TOGL		BIT(9)
#define  STAT_RX_FIFO_FUL	BIT(8)
#define  STAT_RX_FIFO_HFL	BIT(7)
#define  STAT_TX_EMP		BIT(6)
#define  STAT_TX_RDY		BIT(5)
#define  STAT_RX_RDY		BIT(4)
#define  STAT_BRK_DET		BIT(3)
#define  STAT_FRM_ERR		BIT(2)
#define  STAT_PAR_ERR		BIT(1)
#define  STAT_OVR_ERR		BIT(0)
#define  STAT_BRK_ERR		(STAT_BRK_DET | STAT_FRM_ERR | STAT_FRM_ERR\
				 | STAT_PAR_ERR | STAT_OVR_ERR)

#define UART_BRDV		0x10

#define MVEBU_NR_UARTS		1

#define MVEBU_UART_TYPE		"mvebu-uart"

static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];

struct mvebu_uart_data {
	struct uart_port *port;
	struct clk       *clk;
};

/* Core UART Driver Operations */
static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
{
	unsigned long flags;
	unsigned int st;

	spin_lock_irqsave(&port->lock, flags);
	st = readl(port->membase + UART_STAT);
	spin_unlock_irqrestore(&port->lock, flags);

	return (st & STAT_TX_FIFO_EMP) ? TIOCSER_TEMT : 0;
}

static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
{
	return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
}

static void mvebu_uart_set_mctrl(struct uart_port *port,
				 unsigned int mctrl)
{
/*
 * Even if we do not support configuring the modem control lines, this
 * function must be proided to the serial core
 */
}

static void mvebu_uart_stop_tx(struct uart_port *port)
{
	unsigned int ctl = readl(port->membase + UART_CTRL);

	ctl &= ~CTRL_TX_RDY_INT;
	writel(ctl, port->membase + UART_CTRL);
}

static void mvebu_uart_start_tx(struct uart_port *port)
{
	unsigned int ctl = readl(port->membase + UART_CTRL);

	ctl |= CTRL_TX_RDY_INT;
	writel(ctl, port->membase + UART_CTRL);
}

static void mvebu_uart_stop_rx(struct uart_port *port)
{
	unsigned int ctl = readl(port->membase + UART_CTRL);

	ctl &= ~CTRL_RX_INT;
	writel(ctl, port->membase + UART_CTRL);
}

static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
{
	unsigned int ctl;
	unsigned long flags;

	spin_lock_irqsave(&port->lock, flags);
	ctl = readl(port->membase + UART_CTRL);
	if (brk == -1)
		ctl |= CTRL_SND_BRK_SEQ;
	else
		ctl &= ~CTRL_SND_BRK_SEQ;
	writel(ctl, port->membase + UART_CTRL);
	spin_unlock_irqrestore(&port->lock, flags);
}

static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
{
	struct tty_port *tport = &port->state->port;
	unsigned char ch = 0;
	char flag = 0;

	do {
		if (status & STAT_RX_RDY) {
			ch = readl(port->membase + UART_RBR);
			ch &= 0xff;
			flag = TTY_NORMAL;
			port->icount.rx++;

			if (status & STAT_PAR_ERR)
				port->icount.parity++;
		}

		if (status & STAT_BRK_DET) {
			port->icount.brk++;
			status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
			if (uart_handle_break(port))
				goto ignore_char;
		}

		if (status & STAT_OVR_ERR)
			port->icount.overrun++;

		if (status & STAT_FRM_ERR)
			port->icount.frame++;

		if (uart_handle_sysrq_char(port, ch))
			goto ignore_char;

		if (status & port->ignore_status_mask & STAT_PAR_ERR)
			status &= ~STAT_RX_RDY;

		status &= port->read_status_mask;

		if (status & STAT_PAR_ERR)
			flag = TTY_PARITY;

		status &= ~port->ignore_status_mask;

		if (status & STAT_RX_RDY)
			tty_insert_flip_char(tport, ch, flag);

		if (status & STAT_BRK_DET)
			tty_insert_flip_char(tport, 0, TTY_BREAK);

		if (status & STAT_FRM_ERR)
			tty_insert_flip_char(tport, 0, TTY_FRAME);

		if (status & STAT_OVR_ERR)
			tty_insert_flip_char(tport, 0, TTY_OVERRUN);

ignore_char:
		status = readl(port->membase + UART_STAT);
	} while (status & (STAT_RX_RDY | STAT_BRK_DET));

	tty_flip_buffer_push(tport);
}

static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
{
	struct circ_buf *xmit = &port->state->xmit;
	unsigned int count;
	unsigned int st;

	if (port->x_char) {
		writel(port->x_char, port->membase + UART_TSH);
		port->icount.tx++;
		port->x_char = 0;
		return;
	}

	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
		mvebu_uart_stop_tx(port);
		return;
	}

	for (count = 0; count < port->fifosize; count++) {
		writel(xmit->buf[xmit->tail], port->membase + UART_TSH);
		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
		port->icount.tx++;

		if (uart_circ_empty(xmit))
			break;

		st = readl(port->membase + UART_STAT);
		if (st & STAT_TX_FIFO_FUL)
			break;
	}

	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	if (uart_circ_empty(xmit))
		mvebu_uart_stop_tx(port);
}

static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
{
	struct uart_port *port = (struct uart_port *)dev_id;
	unsigned int st = readl(port->membase + UART_STAT);

	if (st & (STAT_RX_RDY | STAT_OVR_ERR | STAT_FRM_ERR | STAT_BRK_DET))
		mvebu_uart_rx_chars(port, st);

	if (st & STAT_TX_RDY)
		mvebu_uart_tx_chars(port, st);

	return IRQ_HANDLED;
}

static int mvebu_uart_startup(struct uart_port *port)
{
	int ret;

	writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
	       port->membase + UART_CTRL);
	udelay(1);
	writel(CTRL_RX_INT, port->membase + UART_CTRL);

	ret = request_irq(port->irq, mvebu_uart_isr, port->irqflags, "serial",
			  port);
	if (ret) {
		dev_err(port->dev, "failed to request irq\n");
		return ret;
	}

	return 0;
}

static void mvebu_uart_shutdown(struct uart_port *port)
{
	writel(0, port->membase + UART_CTRL);
}

static void mvebu_uart_set_termios(struct uart_port *port,
				   struct ktermios *termios,
				   struct ktermios *old)
{
	unsigned long flags;
	unsigned int baud;

	spin_lock_irqsave(&port->lock, flags);

	port->read_status_mask = STAT_RX_RDY | STAT_OVR_ERR |
		STAT_TX_RDY | STAT_TX_FIFO_FUL;

	if (termios->c_iflag & INPCK)
		port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;

	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |=
			STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;

	if ((termios->c_cflag & CREAD) == 0)
		port->ignore_status_mask |= STAT_RX_RDY | STAT_BRK_ERR;

	if (old)
		tty_termios_copy_hw(termios, old);

	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	uart_update_timeout(port, termios->c_cflag, baud);

	spin_unlock_irqrestore(&port->lock, flags);
}

static const char *mvebu_uart_type(struct uart_port *port)
{
	return MVEBU_UART_TYPE;
}

static void mvebu_uart_release_port(struct uart_port *port)
{
	/* Nothing to do here */
}

static int mvebu_uart_request_port(struct uart_port *port)
{
	return 0;
}

#ifdef CONFIG_CONSOLE_POLL
static int mvebu_uart_get_poll_char(struct uart_port *port)
{
	unsigned int st = readl(port->membase + UART_STAT);

	if (!(st & STAT_RX_RDY))
		return NO_POLL_CHAR;

	return readl(port->membase + UART_RBR);
}

static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
{
	unsigned int st;

	for (;;) {
		st = readl(port->membase + UART_STAT);

		if (!(st & STAT_TX_FIFO_FUL))
			break;

		udelay(1);
	}

	writel(c, port->membase + UART_TSH);
}
#endif

static const struct uart_ops mvebu_uart_ops = {
	.tx_empty	= mvebu_uart_tx_empty,
	.set_mctrl	= mvebu_uart_set_mctrl,
	.get_mctrl	= mvebu_uart_get_mctrl,
	.stop_tx	= mvebu_uart_stop_tx,
	.start_tx	= mvebu_uart_start_tx,
	.stop_rx	= mvebu_uart_stop_rx,
	.break_ctl	= mvebu_uart_break_ctl,
	.startup	= mvebu_uart_startup,
	.shutdown	= mvebu_uart_shutdown,
	.set_termios	= mvebu_uart_set_termios,
	.type		= mvebu_uart_type,
	.release_port	= mvebu_uart_release_port,
	.request_port	= mvebu_uart_request_port,
#ifdef CONFIG_CONSOLE_POLL
	.poll_get_char	= mvebu_uart_get_poll_char,
	.poll_put_char	= mvebu_uart_put_poll_char,
#endif
};

/* Console Driver Operations  */

#ifdef CONFIG_SERIAL_MVEBU_CONSOLE
/* Early Console */
static void mvebu_uart_putc(struct uart_port *port, int c)
{
	unsigned int st;

	for (;;) {
		st = readl(port->membase + UART_STAT);
		if (!(st & STAT_TX_FIFO_FUL))
			break;
	}

	writel(c, port->membase + UART_TSH);

	for (;;) {
		st = readl(port->membase + UART_STAT);
		if (st & STAT_TX_FIFO_EMP)
			break;
	}
}

static void mvebu_uart_putc_early_write(struct console *con,
					const char *s,
					unsigned n)
{
	struct earlycon_device *dev = con->data;

	uart_console_write(&dev->port, s, n, mvebu_uart_putc);
}

static int __init
mvebu_uart_early_console_setup(struct earlycon_device *device,
			       const char *opt)
{
	if (!device->port.membase)
		return -ENODEV;

	device->con->write = mvebu_uart_putc_early_write;

	return 0;
}

EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
		    mvebu_uart_early_console_setup);

static void wait_for_xmitr(struct uart_port *port)
{
	u32 val;

	readl_poll_timeout_atomic(port->membase + UART_STAT, val,
				  (val & STAT_TX_EMP), 1, 10000);
}

static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
{
	wait_for_xmitr(port);
	writel(ch, port->membase + UART_TSH);
}

static void mvebu_uart_console_write(struct console *co, const char *s,
				     unsigned int count)
{
	struct uart_port *port = &mvebu_uart_ports[co->index];
	unsigned long flags;
	unsigned int ier;
	int locked = 1;

	if (oops_in_progress)
		locked = spin_trylock_irqsave(&port->lock, flags);
	else
		spin_lock_irqsave(&port->lock, flags);

	ier = readl(port->membase + UART_CTRL) &
		(CTRL_RX_INT | CTRL_TX_RDY_INT);
	writel(0, port->membase + UART_CTRL);

	uart_console_write(port, s, count, mvebu_uart_console_putchar);

	wait_for_xmitr(port);

	if (ier)
		writel(ier, port->membase + UART_CTRL);

	if (locked)
		spin_unlock_irqrestore(&port->lock, flags);
}

static int mvebu_uart_console_setup(struct console *co, char *options)
{
	struct uart_port *port;
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
		return -EINVAL;

	port = &mvebu_uart_ports[co->index];

	if (!port->mapbase || !port->membase) {
		pr_debug("console on ttyMV%i not present\n", co->index);
		return -ENODEV;
	}

	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);

	return uart_set_options(port, co, baud, parity, bits, flow);
}

static struct uart_driver mvebu_uart_driver;

static struct console mvebu_uart_console = {
	.name	= "ttyMV",
	.write	= mvebu_uart_console_write,
	.device	= uart_console_device,
	.setup	= mvebu_uart_console_setup,
	.flags	= CON_PRINTBUFFER,
	.index	= -1,
	.data	= &mvebu_uart_driver,
};

static int __init mvebu_uart_console_init(void)
{
	register_console(&mvebu_uart_console);
	return 0;
}

console_initcall(mvebu_uart_console_init);


#endif /* CONFIG_SERIAL_MVEBU_CONSOLE */

static struct uart_driver mvebu_uart_driver = {
	.owner			= THIS_MODULE,
	.driver_name		= "mvebu_serial",
	.dev_name		= "ttyMV",
	.nr			= MVEBU_NR_UARTS,
#ifdef CONFIG_SERIAL_MVEBU_CONSOLE
	.cons			= &mvebu_uart_console,
#endif
};

static int mvebu_uart_probe(struct platform_device *pdev)
{
	struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	struct uart_port *port;
	struct mvebu_uart_data *data;
	int ret;

	if (!reg || !irq) {
		dev_err(&pdev->dev, "no registers/irq defined\n");
		return -EINVAL;
	}

	port = &mvebu_uart_ports[0];

	spin_lock_init(&port->lock);

	port->dev        = &pdev->dev;
	port->type       = PORT_MVEBU;
	port->ops        = &mvebu_uart_ops;
	port->regshift   = 0;

	port->fifosize   = 32;
	port->iotype     = UPIO_MEM32;
	port->flags      = UPF_FIXED_PORT;
	port->line       = 0; /* single port: force line number to  0 */

	port->irq        = irq->start;
	port->irqflags   = 0;
	port->mapbase    = reg->start;

	port->membase = devm_ioremap_resource(&pdev->dev, reg);
	if (IS_ERR(port->membase))
		return -PTR_ERR(port->membase);

	data = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart_data),
			    GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->port = port;

	port->private_data = data;
	platform_set_drvdata(pdev, data);

	ret = uart_add_one_port(&mvebu_uart_driver, port);
	if (ret)
		return ret;
	return 0;
}

static int mvebu_uart_remove(struct platform_device *pdev)
{
	struct mvebu_uart_data *data = platform_get_drvdata(pdev);

	uart_remove_one_port(&mvebu_uart_driver, data->port);
	data->port->private_data = NULL;
	data->port->mapbase      = 0;
	return 0;
}

/* Match table for of_platform binding */
static const struct of_device_id mvebu_uart_of_match[] = {
	{ .compatible = "marvell,armada-3700-uart", },
	{}
};
MODULE_DEVICE_TABLE(of, mvebu_uart_of_match);

static struct platform_driver mvebu_uart_platform_driver = {
	.probe	= mvebu_uart_probe,
	.remove	= mvebu_uart_remove,
	.driver	= {
		.owner	= THIS_MODULE,
		.name  = "mvebu-uart",
		.of_match_table = of_match_ptr(mvebu_uart_of_match),
	},
};

static int __init mvebu_uart_init(void)
{
	int ret;

	ret = uart_register_driver(&mvebu_uart_driver);
	if (ret)
		return ret;

	ret = platform_driver_register(&mvebu_uart_platform_driver);
	if (ret)
		uart_unregister_driver(&mvebu_uart_driver);

	return ret;
}

static void __exit mvebu_uart_exit(void)
{
	platform_driver_unregister(&mvebu_uart_platform_driver);
	uart_unregister_driver(&mvebu_uart_driver);
}

arch_initcall(mvebu_uart_init);
module_exit(mvebu_uart_exit);

MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>");
MODULE_DESCRIPTION("Marvell Armada-3700 Serial Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
30530791 WD	1	/*
	2	* ***************************************************************************
	3	* Copyright (C) 2015 Marvell International Ltd.
	4	* ***************************************************************************
	5	* This program is free software: you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the Free
	7	* Software Foundation, either version 2 of the License, or any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	* ***************************************************************************
	17	*/
	18
	19	#include <linux/clk.h>
	20	#include <linux/console.h>
	21	#include <linux/delay.h>
	22	#include <linux/device.h>
	23	#include <linux/init.h>
	24	#include <linux/io.h>
	25	#include <linux/iopoll.h>
	26	#include <linux/module.h>
	27	#include <linux/of.h>
	28	#include <linux/of_address.h>
	29	#include <linux/of_device.h>
	30	#include <linux/of_irq.h>
	31	#include <linux/of_platform.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/serial.h>
	34	#include <linux/serial_core.h>
	35	#include <linux/slab.h>
	36	#include <linux/tty.h>
	37	#include <linux/tty_flip.h>
	38
	39	/* Register Map */
	40	#define UART_RBR 0x00
	41	#define RBR_BRK_DET BIT(15)
	42	#define RBR_FRM_ERR_DET BIT(14)
	43	#define RBR_PAR_ERR_DET BIT(13)
	44	#define RBR_OVR_ERR_DET BIT(12)
	45
	46	#define UART_TSH 0x04
	47
	48	#define UART_CTRL 0x08
	49	#define CTRL_SOFT_RST BIT(31)
	50	#define CTRL_TXFIFO_RST BIT(15)
	51	#define CTRL_RXFIFO_RST BIT(14)
	52	#define CTRL_ST_MIRR_EN BIT(13)
	53	#define CTRL_LPBK_EN BIT(12)
	54	#define CTRL_SND_BRK_SEQ BIT(11)
	55	#define CTRL_PAR_EN BIT(10)
	56	#define CTRL_TWO_STOP BIT(9)
	57	#define CTRL_TX_HFL_INT BIT(8)
	58	#define CTRL_RX_HFL_INT BIT(7)
	59	#define CTRL_TX_EMP_INT BIT(6)
	60	#define CTRL_TX_RDY_INT BIT(5)
	61	#define CTRL_RX_RDY_INT BIT(4)
	62	#define CTRL_BRK_DET_INT BIT(3)
	63	#define CTRL_FRM_ERR_INT BIT(2)
	64	#define CTRL_PAR_ERR_INT BIT(1)
65	#define CTRL_OVR_ERR_INT BIT(0)
66	#define CTRL_RX_INT (CTRL_RX_RDY_INT \| CTRL_BRK_DET_INT \|\
67	CTRL_FRM_ERR_INT \| CTRL_PAR_ERR_INT \| CTRL_OVR_ERR_INT)
68
69	#define UART_STAT 0x0c
70	#define STAT_TX_FIFO_EMP BIT(13)
71	#define STAT_RX_FIFO_EMP BIT(12)
72	#define STAT_TX_FIFO_FUL BIT(11)
73	#define STAT_TX_FIFO_HFL BIT(10)
74	#define STAT_RX_TOGL BIT(9)
75	#define STAT_RX_FIFO_FUL BIT(8)
76	#define STAT_RX_FIFO_HFL BIT(7)
77	#define STAT_TX_EMP BIT(6)
78	#define STAT_TX_RDY BIT(5)
79	#define STAT_RX_RDY BIT(4)
80	#define STAT_BRK_DET BIT(3)
81	#define STAT_FRM_ERR BIT(2)
82	#define STAT_PAR_ERR BIT(1)
83	#define STAT_OVR_ERR BIT(0)
84	#define STAT_BRK_ERR (STAT_BRK_DET \| STAT_FRM_ERR \| STAT_FRM_ERR\
85	\| STAT_PAR_ERR \| STAT_OVR_ERR)
86
87	#define UART_BRDV 0x10
88
89	#define MVEBU_NR_UARTS 1
90
91	#define MVEBU_UART_TYPE "mvebu-uart"
92
93	static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
94
95	struct mvebu_uart_data {
96	struct uart_port *port;
97	struct clk *clk;
98	};
99
100	/* Core UART Driver Operations */
101	static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
102	{
103	unsigned long flags;
104	unsigned int st;
105
106	spin_lock_irqsave(&port->lock, flags);
107	st = readl(port->membase + UART_STAT);
108	spin_unlock_irqrestore(&port->lock, flags);
109
110	return (st & STAT_TX_FIFO_EMP) ? TIOCSER_TEMT : 0;
111	}
112
113	static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
114	{
115	return TIOCM_CTS \| TIOCM_DSR \| TIOCM_CAR;
116	}
117
118	static void mvebu_uart_set_mctrl(struct uart_port *port,
119	unsigned int mctrl)
120	{
121	/*
122	* Even if we do not support configuring the modem control lines, this
123	* function must be proided to the serial core
124	*/
125	}
126
127	static void mvebu_uart_stop_tx(struct uart_port *port)
128	{
129	unsigned int ctl = readl(port->membase + UART_CTRL);
130
131	ctl &= ~CTRL_TX_RDY_INT;
132	writel(ctl, port->membase + UART_CTRL);
133	}
134
135	static void mvebu_uart_start_tx(struct uart_port *port)
136	{
137	unsigned int ctl = readl(port->membase + UART_CTRL);
138
139	ctl \|= CTRL_TX_RDY_INT;
140	writel(ctl, port->membase + UART_CTRL);
141	}
142
143	static void mvebu_uart_stop_rx(struct uart_port *port)
144	{
145	unsigned int ctl = readl(port->membase + UART_CTRL);
146
147	ctl &= ~CTRL_RX_INT;
148	writel(ctl, port->membase + UART_CTRL);
149	}
150
151	static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
152	{
153	unsigned int ctl;
154	unsigned long flags;
155
156	spin_lock_irqsave(&port->lock, flags);
157	ctl = readl(port->membase + UART_CTRL);
158	if (brk == -1)
159	ctl \|= CTRL_SND_BRK_SEQ;
160	else
161	ctl &= ~CTRL_SND_BRK_SEQ;
162	writel(ctl, port->membase + UART_CTRL);
163	spin_unlock_irqrestore(&port->lock, flags);
164	}
165
166	static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
167	{
168	struct tty_port *tport = &port->state->port;
169	unsigned char ch = 0;
170	char flag = 0;
171
172	do {
173	if (status & STAT_RX_RDY) {
174	ch = readl(port->membase + UART_RBR);
175	ch &= 0xff;
176	flag = TTY_NORMAL;
177	port->icount.rx++;
178
179	if (status & STAT_PAR_ERR)
180	port->icount.parity++;
181	}
182
183	if (status & STAT_BRK_DET) {
184	port->icount.brk++;
185	status &= ~(STAT_FRM_ERR \| STAT_PAR_ERR);
186	if (uart_handle_break(port))
187	goto ignore_char;
188	}
189
190	if (status & STAT_OVR_ERR)
191	port->icount.overrun++;
192
193	if (status & STAT_FRM_ERR)
194	port->icount.frame++;
195
196	if (uart_handle_sysrq_char(port, ch))
197	goto ignore_char;
198
199	if (status & port->ignore_status_mask & STAT_PAR_ERR)
200	status &= ~STAT_RX_RDY;
201
202	status &= port->read_status_mask;
203
204	if (status & STAT_PAR_ERR)
205	flag = TTY_PARITY;
206
207	status &= ~port->ignore_status_mask;
208
209	if (status & STAT_RX_RDY)
210	tty_insert_flip_char(tport, ch, flag);
211
212	if (status & STAT_BRK_DET)
213	tty_insert_flip_char(tport, 0, TTY_BREAK);
214
215	if (status & STAT_FRM_ERR)
216	tty_insert_flip_char(tport, 0, TTY_FRAME);
217
218	if (status & STAT_OVR_ERR)
219	tty_insert_flip_char(tport, 0, TTY_OVERRUN);
220
221	ignore_char:
222	status = readl(port->membase + UART_STAT);
223	} while (status & (STAT_RX_RDY \| STAT_BRK_DET));
224
225	tty_flip_buffer_push(tport);
226	}
227
228	static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
229	{
230	struct circ_buf *xmit = &port->state->xmit;
231	unsigned int count;
232	unsigned int st;
233
234	if (port->x_char) {
235	writel(port->x_char, port->membase + UART_TSH);
236	port->icount.tx++;
237	port->x_char = 0;
238	return;
239	}
240
241	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
242	mvebu_uart_stop_tx(port);
243	return;
244	}
245
246	for (count = 0; count < port->fifosize; count++) {
247	writel(xmit->buf[xmit->tail], port->membase + UART_TSH);
248	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
249	port->icount.tx++;
250
251	if (uart_circ_empty(xmit))
252	break;
253
254	st = readl(port->membase + UART_STAT);
255	if (st & STAT_TX_FIFO_FUL)
256	break;
257	}
258
259	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
260	uart_write_wakeup(port);
261
262	if (uart_circ_empty(xmit))
263	mvebu_uart_stop_tx(port);
264	}
265
266	static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
267	{
268	struct uart_port port = (struct uart_port )dev_id;
269	unsigned int st = readl(port->membase + UART_STAT);
270
271	if (st & (STAT_RX_RDY \| STAT_OVR_ERR \| STAT_FRM_ERR \| STAT_BRK_DET))
272	mvebu_uart_rx_chars(port, st);
273
274	if (st & STAT_TX_RDY)
275	mvebu_uart_tx_chars(port, st);
276
277	return IRQ_HANDLED;
278	}
279
280	static int mvebu_uart_startup(struct uart_port *port)
281	{
282	int ret;
283
284	writel(CTRL_TXFIFO_RST \| CTRL_RXFIFO_RST,
285	port->membase + UART_CTRL);
286	udelay(1);
287	writel(CTRL_RX_INT, port->membase + UART_CTRL);
288
289	ret = request_irq(port->irq, mvebu_uart_isr, port->irqflags, "serial",
290	port);
291	if (ret) {
292	dev_err(port->dev, "failed to request irq\n");
293	return ret;
294	}
295
296	return 0;
297	}
298
299	static void mvebu_uart_shutdown(struct uart_port *port)
300	{
301	writel(0, port->membase + UART_CTRL);
302	}
303
304	static void mvebu_uart_set_termios(struct uart_port *port,
305	struct ktermios *termios,
306	struct ktermios *old)
307	{
308	unsigned long flags;
309	unsigned int baud;
310
311	spin_lock_irqsave(&port->lock, flags);
312
313	port->read_status_mask = STAT_RX_RDY \| STAT_OVR_ERR \|
314	STAT_TX_RDY \| STAT_TX_FIFO_FUL;
315
316	if (termios->c_iflag & INPCK)
317	port->read_status_mask \|= STAT_FRM_ERR \| STAT_PAR_ERR;
318
319	port->ignore_status_mask = 0;
320	if (termios->c_iflag & IGNPAR)
321	port->ignore_status_mask \|=
322	STAT_FRM_ERR \| STAT_PAR_ERR \| STAT_OVR_ERR;
323
324	if ((termios->c_cflag & CREAD) == 0)
325	port->ignore_status_mask \|= STAT_RX_RDY \| STAT_BRK_ERR;
326
327	if (old)
328	tty_termios_copy_hw(termios, old);
329
330	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
331	uart_update_timeout(port, termios->c_cflag, baud);
332
333	spin_unlock_irqrestore(&port->lock, flags);
334	}
335
336	static const char mvebu_uart_type(struct uart_port port)
337	{
338	return MVEBU_UART_TYPE;
339	}
340
341	static void mvebu_uart_release_port(struct uart_port *port)
342	{
343	/* Nothing to do here */
344	}
345
346	static int mvebu_uart_request_port(struct uart_port *port)
347	{
348	return 0;
349	}
350
351	#ifdef CONFIG_CONSOLE_POLL
352	static int mvebu_uart_get_poll_char(struct uart_port *port)
353	{
354	unsigned int st = readl(port->membase + UART_STAT);
355
356	if (!(st & STAT_RX_RDY))
357	return NO_POLL_CHAR;
358
359	return readl(port->membase + UART_RBR);
360	}
361
362	static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
363	{
364	unsigned int st;
365
366	for (;;) {
367	st = readl(port->membase + UART_STAT);
368
369	if (!(st & STAT_TX_FIFO_FUL))
370	break;
371
372	udelay(1);
373	}
374
375	writel(c, port->membase + UART_TSH);
376	}
377	#endif
378
379	static const struct uart_ops mvebu_uart_ops = {
380	.tx_empty = mvebu_uart_tx_empty,
381	.set_mctrl = mvebu_uart_set_mctrl,
382	.get_mctrl = mvebu_uart_get_mctrl,
383	.stop_tx = mvebu_uart_stop_tx,
384	.start_tx = mvebu_uart_start_tx,
385	.stop_rx = mvebu_uart_stop_rx,
386	.break_ctl = mvebu_uart_break_ctl,
387	.startup = mvebu_uart_startup,
388	.shutdown = mvebu_uart_shutdown,
389	.set_termios = mvebu_uart_set_termios,
390	.type = mvebu_uart_type,
391	.release_port = mvebu_uart_release_port,
392	.request_port = mvebu_uart_request_port,
393	#ifdef CONFIG_CONSOLE_POLL
394	.poll_get_char = mvebu_uart_get_poll_char,
395	.poll_put_char = mvebu_uart_put_poll_char,
396	#endif
397	};
398
399	/* Console Driver Operations */
400
401	#ifdef CONFIG_SERIAL_MVEBU_CONSOLE
402	/* Early Console */
403	static void mvebu_uart_putc(struct uart_port *port, int c)
404	{
405	unsigned int st;
406
407	for (;;) {
408	st = readl(port->membase + UART_STAT);
409	if (!(st & STAT_TX_FIFO_FUL))
410	break;
411	}
412
413	writel(c, port->membase + UART_TSH);
414
415	for (;;) {
416	st = readl(port->membase + UART_STAT);
417	if (st & STAT_TX_FIFO_EMP)
418	break;
419	}
420	}
421
422	static void mvebu_uart_putc_early_write(struct console *con,
423	const char *s,
424	unsigned n)
425	{
426	struct earlycon_device *dev = con->data;
427
428	uart_console_write(&dev->port, s, n, mvebu_uart_putc);
429	}
430
431	static int __init
432	mvebu_uart_early_console_setup(struct earlycon_device *device,
433	const char *opt)
434	{
435	if (!device->port.membase)
436	return -ENODEV;
437
438	device->con->write = mvebu_uart_putc_early_write;
439
440	return 0;
441	}
442
443	EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
444	OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
445	mvebu_uart_early_console_setup);
446
447	static void wait_for_xmitr(struct uart_port *port)
448	{
449	u32 val;
450
451	readl_poll_timeout_atomic(port->membase + UART_STAT, val,
452	(val & STAT_TX_EMP), 1, 10000);
453	}
454
455	static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
456	{
457	wait_for_xmitr(port);
458	writel(ch, port->membase + UART_TSH);
459	}
460
461	static void mvebu_uart_console_write(struct console co, const char s,
462	unsigned int count)
463	{
464	struct uart_port *port = &mvebu_uart_ports[co->index];
465	unsigned long flags;
466	unsigned int ier;
467	int locked = 1;
468
469	if (oops_in_progress)
470	locked = spin_trylock_irqsave(&port->lock, flags);
471	else
472	spin_lock_irqsave(&port->lock, flags);
473
474	ier = readl(port->membase + UART_CTRL) &
475	(CTRL_RX_INT \| CTRL_TX_RDY_INT);
476	writel(0, port->membase + UART_CTRL);
477
478	uart_console_write(port, s, count, mvebu_uart_console_putchar);
479
480	wait_for_xmitr(port);
481
482	if (ier)
483	writel(ier, port->membase + UART_CTRL);
484
485	if (locked)
486	spin_unlock_irqrestore(&port->lock, flags);
487	}
488
489	static int mvebu_uart_console_setup(struct console co, char options)
490	{
491	struct uart_port *port;
492	int baud = 9600;
493	int bits = 8;
494	int parity = 'n';
495	int flow = 'n';
496
497	if (co->index < 0 \|\| co->index >= MVEBU_NR_UARTS)
498	return -EINVAL;
499
500	port = &mvebu_uart_ports[co->index];
501
502	if (!port->mapbase \|\| !port->membase) {
503	pr_debug("console on ttyMV%i not present\n", co->index);
504	return -ENODEV;
505	}
506
507	if (options)
508	uart_parse_options(options, &baud, &parity, &bits, &flow);
509
510	return uart_set_options(port, co, baud, parity, bits, flow);
511	}
512
513	static struct uart_driver mvebu_uart_driver;
514
515	static struct console mvebu_uart_console = {
516	.name = "ttyMV",
517	.write = mvebu_uart_console_write,
518	.device = uart_console_device,
519	.setup = mvebu_uart_console_setup,
520	.flags = CON_PRINTBUFFER,
521	.index = -1,
522	.data = &mvebu_uart_driver,
523	};
524
525	static int __init mvebu_uart_console_init(void)
526	{
527	register_console(&mvebu_uart_console);
528	return 0;
529	}
530
531	console_initcall(mvebu_uart_console_init);
532
533
534	#endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
535
536	static struct uart_driver mvebu_uart_driver = {
537	.owner = THIS_MODULE,
538	.driver_name = "mvebu_serial",
539	.dev_name = "ttyMV",
540	.nr = MVEBU_NR_UARTS,
541	#ifdef CONFIG_SERIAL_MVEBU_CONSOLE
542	.cons = &mvebu_uart_console,
543	#endif
544	};
545
546	static int mvebu_uart_probe(struct platform_device *pdev)
547	{
548	struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
549	struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
550	struct uart_port *port;
551	struct mvebu_uart_data *data;
552	int ret;
553
554	if (!reg \|\| !irq) {
555	dev_err(&pdev->dev, "no registers/irq defined\n");
556	return -EINVAL;
557	}
558
559	port = &mvebu_uart_ports[0];
560
561	spin_lock_init(&port->lock);
562
563	port->dev = &pdev->dev;
564	port->type = PORT_MVEBU;
565	port->ops = &mvebu_uart_ops;
566	port->regshift = 0;
567
568	port->fifosize = 32;
569	port->iotype = UPIO_MEM32;
570	port->flags = UPF_FIXED_PORT;
571	port->line = 0; /* single port: force line number to 0 */
572
573	port->irq = irq->start;
574	port->irqflags = 0;
575	port->mapbase = reg->start;
576
577	port->membase = devm_ioremap_resource(&pdev->dev, reg);
578	if (IS_ERR(port->membase))
579	return -PTR_ERR(port->membase);
580
581	data = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart_data),
582	GFP_KERNEL);
583	if (!data)
584	return -ENOMEM;
585
586	data->port = port;
587
588	port->private_data = data;
589	platform_set_drvdata(pdev, data);
590
591	ret = uart_add_one_port(&mvebu_uart_driver, port);
592	if (ret)
593	return ret;
594	return 0;
595	}
596
597	static int mvebu_uart_remove(struct platform_device *pdev)
598	{
599	struct mvebu_uart_data *data = platform_get_drvdata(pdev);
600
601	uart_remove_one_port(&mvebu_uart_driver, data->port);
602	data->port->private_data = NULL;
603	data->port->mapbase = 0;
604	return 0;
605	}
606
607	/* Match table for of_platform binding */
608	static const struct of_device_id mvebu_uart_of_match[] = {
609	{ .compatible = "marvell,armada-3700-uart", },
610	{}
611	};
612	MODULE_DEVICE_TABLE(of, mvebu_uart_of_match);
613
614	static struct platform_driver mvebu_uart_platform_driver = {
615	.probe = mvebu_uart_probe,
616	.remove = mvebu_uart_remove,
617	.driver = {
618	.owner = THIS_MODULE,
619	.name = "mvebu-uart",
620	.of_match_table = of_match_ptr(mvebu_uart_of_match),
621	},
622	};
623
624	static int __init mvebu_uart_init(void)
625	{
626	int ret;
627
628	ret = uart_register_driver(&mvebu_uart_driver);
629	if (ret)
630	return ret;
631
632	ret = platform_driver_register(&mvebu_uart_platform_driver);
633	if (ret)
634	uart_unregister_driver(&mvebu_uart_driver);
635
636	return ret;
637	}
638
639	static void __exit mvebu_uart_exit(void)
640	{
641	platform_driver_unregister(&mvebu_uart_platform_driver);
642	uart_unregister_driver(&mvebu_uart_driver);
643	}
644
645	arch_initcall(mvebu_uart_init);
646	module_exit(mvebu_uart_exit);
647
648	MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>");
649	MODULE_DESCRIPTION("Marvell Armada-3700 Serial Driver");
650	MODULE_LICENSE("GPL");