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Commit | Line | Data |
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b612633b G |
1 | /* |
2 | * Driver for OMAP-UART controller. | |
3 | * Based on drivers/serial/8250.c | |
4 | * | |
5 | * Copyright (C) 2010 Texas Instruments. | |
6 | * | |
7 | * Authors: | |
8 | * Govindraj R <govindraj.raja@ti.com> | |
9 | * Thara Gopinath <thara@ti.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
25985edc | 16 | * Note: This driver is made separate from 8250 driver as we cannot |
b612633b G |
17 | * over load 8250 driver with omap platform specific configuration for |
18 | * features like DMA, it makes easier to implement features like DMA and | |
19 | * hardware flow control and software flow control configuration with | |
20 | * this driver as required for the omap-platform. | |
21 | */ | |
22 | ||
364a6ece TW |
23 | #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
24 | #define SUPPORT_SYSRQ | |
25 | #endif | |
26 | ||
b612633b G |
27 | #include <linux/module.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/console.h> | |
30 | #include <linux/serial_reg.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/tty.h> | |
34 | #include <linux/tty_flip.h> | |
d21e4005 | 35 | #include <linux/platform_device.h> |
b612633b | 36 | #include <linux/io.h> |
b612633b G |
37 | #include <linux/clk.h> |
38 | #include <linux/serial_core.h> | |
39 | #include <linux/irq.h> | |
fcdca757 | 40 | #include <linux/pm_runtime.h> |
d92b0dfc | 41 | #include <linux/of.h> |
9574f36f | 42 | #include <linux/gpio.h> |
d9ba5737 | 43 | #include <linux/platform_data/serial-omap.h> |
b612633b | 44 | |
f91b55ab RK |
45 | #define OMAP_MAX_HSUART_PORTS 6 |
46 | ||
7c77c8de G |
47 | #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) |
48 | ||
49 | #define OMAP_UART_REV_42 0x0402 | |
50 | #define OMAP_UART_REV_46 0x0406 | |
51 | #define OMAP_UART_REV_52 0x0502 | |
52 | #define OMAP_UART_REV_63 0x0603 | |
53 | ||
f64ffda6 G |
54 | #define OMAP_UART_TX_WAKEUP_EN BIT(7) |
55 | ||
56 | /* Feature flags */ | |
57 | #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0) | |
58 | ||
f91b55ab RK |
59 | #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) |
60 | #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) | |
61 | ||
8fe789dc RN |
62 | #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/ |
63 | ||
0ba5f668 PW |
64 | /* SCR register bitmasks */ |
65 | #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) | |
1776fd05 | 66 | #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) |
f91b55ab | 67 | #define OMAP_UART_SCR_TX_EMPTY (1 << 3) |
0ba5f668 PW |
68 | |
69 | /* FCR register bitmasks */ | |
0ba5f668 | 70 | #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) |
6721ab7f | 71 | #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) |
0ba5f668 | 72 | |
7c77c8de G |
73 | /* MVR register bitmasks */ |
74 | #define OMAP_UART_MVR_SCHEME_SHIFT 30 | |
75 | ||
76 | #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 | |
77 | #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 | |
78 | #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f | |
79 | ||
80 | #define OMAP_UART_MVR_MAJ_MASK 0x700 | |
81 | #define OMAP_UART_MVR_MAJ_SHIFT 8 | |
82 | #define OMAP_UART_MVR_MIN_MASK 0x3f | |
83 | ||
f91b55ab RK |
84 | #define OMAP_UART_DMA_CH_FREE -1 |
85 | ||
86 | #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA | |
87 | #define OMAP_MODE13X_SPEED 230400 | |
88 | ||
89 | /* WER = 0x7F | |
90 | * Enable module level wakeup in WER reg | |
91 | */ | |
92 | #define OMAP_UART_WER_MOD_WKUP 0X7F | |
93 | ||
94 | /* Enable XON/XOFF flow control on output */ | |
3af08bd7 | 95 | #define OMAP_UART_SW_TX 0x08 |
f91b55ab RK |
96 | |
97 | /* Enable XON/XOFF flow control on input */ | |
3af08bd7 | 98 | #define OMAP_UART_SW_RX 0x02 |
f91b55ab RK |
99 | |
100 | #define OMAP_UART_SW_CLR 0xF0 | |
101 | ||
102 | #define OMAP_UART_TCR_TRIG 0x0F | |
103 | ||
104 | struct uart_omap_dma { | |
105 | u8 uart_dma_tx; | |
106 | u8 uart_dma_rx; | |
107 | int rx_dma_channel; | |
108 | int tx_dma_channel; | |
109 | dma_addr_t rx_buf_dma_phys; | |
110 | dma_addr_t tx_buf_dma_phys; | |
111 | unsigned int uart_base; | |
112 | /* | |
113 | * Buffer for rx dma.It is not required for tx because the buffer | |
114 | * comes from port structure. | |
115 | */ | |
116 | unsigned char *rx_buf; | |
117 | unsigned int prev_rx_dma_pos; | |
118 | int tx_buf_size; | |
119 | int tx_dma_used; | |
120 | int rx_dma_used; | |
121 | spinlock_t tx_lock; | |
122 | spinlock_t rx_lock; | |
123 | /* timer to poll activity on rx dma */ | |
124 | struct timer_list rx_timer; | |
125 | unsigned int rx_buf_size; | |
126 | unsigned int rx_poll_rate; | |
127 | unsigned int rx_timeout; | |
128 | }; | |
129 | ||
d37c6ceb FB |
130 | struct uart_omap_port { |
131 | struct uart_port port; | |
132 | struct uart_omap_dma uart_dma; | |
133 | struct device *dev; | |
134 | ||
135 | unsigned char ier; | |
136 | unsigned char lcr; | |
137 | unsigned char mcr; | |
138 | unsigned char fcr; | |
139 | unsigned char efr; | |
140 | unsigned char dll; | |
141 | unsigned char dlh; | |
142 | unsigned char mdr1; | |
143 | unsigned char scr; | |
f64ffda6 | 144 | unsigned char wer; |
d37c6ceb FB |
145 | |
146 | int use_dma; | |
147 | /* | |
148 | * Some bits in registers are cleared on a read, so they must | |
149 | * be saved whenever the register is read but the bits will not | |
150 | * be immediately processed. | |
151 | */ | |
152 | unsigned int lsr_break_flag; | |
153 | unsigned char msr_saved_flags; | |
154 | char name[20]; | |
155 | unsigned long port_activity; | |
39aee51d | 156 | int context_loss_cnt; |
d37c6ceb FB |
157 | u32 errata; |
158 | u8 wakeups_enabled; | |
f64ffda6 | 159 | u32 features; |
d37c6ceb | 160 | |
e36851d0 FB |
161 | int DTR_gpio; |
162 | int DTR_inverted; | |
163 | int DTR_active; | |
164 | ||
d37c6ceb FB |
165 | struct pm_qos_request pm_qos_request; |
166 | u32 latency; | |
167 | u32 calc_latency; | |
168 | struct work_struct qos_work; | |
ddd85e22 | 169 | bool is_suspending; |
d37c6ceb FB |
170 | }; |
171 | ||
172 | #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) | |
173 | ||
b612633b G |
174 | static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; |
175 | ||
176 | /* Forward declaration of functions */ | |
94734749 | 177 | static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); |
b612633b | 178 | |
2fd14964 | 179 | static struct workqueue_struct *serial_omap_uart_wq; |
b612633b G |
180 | |
181 | static inline unsigned int serial_in(struct uart_omap_port *up, int offset) | |
182 | { | |
183 | offset <<= up->port.regshift; | |
184 | return readw(up->port.membase + offset); | |
185 | } | |
186 | ||
187 | static inline void serial_out(struct uart_omap_port *up, int offset, int value) | |
188 | { | |
189 | offset <<= up->port.regshift; | |
190 | writew(value, up->port.membase + offset); | |
191 | } | |
192 | ||
193 | static inline void serial_omap_clear_fifos(struct uart_omap_port *up) | |
194 | { | |
195 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
196 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
197 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
198 | serial_out(up, UART_FCR, 0); | |
199 | } | |
200 | ||
e5b57c03 FB |
201 | static int serial_omap_get_context_loss_count(struct uart_omap_port *up) |
202 | { | |
d8ee4ea6 | 203 | struct omap_uart_port_info *pdata = up->dev->platform_data; |
e5b57c03 | 204 | |
ce2f08de | 205 | if (!pdata || !pdata->get_context_loss_count) |
a630fbfb | 206 | return -EINVAL; |
e5b57c03 | 207 | |
d8ee4ea6 | 208 | return pdata->get_context_loss_count(up->dev); |
e5b57c03 FB |
209 | } |
210 | ||
e5b57c03 FB |
211 | static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) |
212 | { | |
d8ee4ea6 | 213 | struct omap_uart_port_info *pdata = up->dev->platform_data; |
e5b57c03 | 214 | |
ce2f08de FB |
215 | if (!pdata || !pdata->enable_wakeup) |
216 | return; | |
217 | ||
218 | pdata->enable_wakeup(up->dev, enable); | |
e5b57c03 FB |
219 | } |
220 | ||
5fe21236 AP |
221 | /* |
222 | * serial_omap_baud_is_mode16 - check if baud rate is MODE16X | |
223 | * @port: uart port info | |
224 | * @baud: baudrate for which mode needs to be determined | |
225 | * | |
226 | * Returns true if baud rate is MODE16X and false if MODE13X | |
227 | * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values, | |
228 | * and Error Rates" determines modes not for all common baud rates. | |
229 | * E.g. for 1000000 baud rate mode must be 16x, but according to that | |
230 | * table it's determined as 13x. | |
231 | */ | |
232 | static bool | |
233 | serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud) | |
234 | { | |
235 | unsigned int n13 = port->uartclk / (13 * baud); | |
236 | unsigned int n16 = port->uartclk / (16 * baud); | |
237 | int baudAbsDiff13 = baud - (port->uartclk / (13 * n13)); | |
238 | int baudAbsDiff16 = baud - (port->uartclk / (16 * n16)); | |
239 | if(baudAbsDiff13 < 0) | |
240 | baudAbsDiff13 = -baudAbsDiff13; | |
241 | if(baudAbsDiff16 < 0) | |
242 | baudAbsDiff16 = -baudAbsDiff16; | |
243 | ||
244 | return (baudAbsDiff13 > baudAbsDiff16); | |
245 | } | |
246 | ||
b612633b G |
247 | /* |
248 | * serial_omap_get_divisor - calculate divisor value | |
249 | * @port: uart port info | |
250 | * @baud: baudrate for which divisor needs to be calculated. | |
b612633b G |
251 | */ |
252 | static unsigned int | |
253 | serial_omap_get_divisor(struct uart_port *port, unsigned int baud) | |
254 | { | |
255 | unsigned int divisor; | |
256 | ||
5fe21236 | 257 | if (!serial_omap_baud_is_mode16(port, baud)) |
b612633b G |
258 | divisor = 13; |
259 | else | |
260 | divisor = 16; | |
261 | return port->uartclk/(baud * divisor); | |
262 | } | |
263 | ||
b612633b G |
264 | static void serial_omap_enable_ms(struct uart_port *port) |
265 | { | |
c990f351 | 266 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 267 | |
ba77433d | 268 | dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); |
fcdca757 | 269 | |
d8ee4ea6 | 270 | pm_runtime_get_sync(up->dev); |
b612633b G |
271 | up->ier |= UART_IER_MSI; |
272 | serial_out(up, UART_IER, up->ier); | |
660ac5f4 FB |
273 | pm_runtime_mark_last_busy(up->dev); |
274 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
275 | } |
276 | ||
277 | static void serial_omap_stop_tx(struct uart_port *port) | |
278 | { | |
c990f351 | 279 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 280 | |
d8ee4ea6 | 281 | pm_runtime_get_sync(up->dev); |
b612633b G |
282 | if (up->ier & UART_IER_THRI) { |
283 | up->ier &= ~UART_IER_THRI; | |
284 | serial_out(up, UART_IER, up->ier); | |
285 | } | |
fcdca757 | 286 | |
d8ee4ea6 FB |
287 | pm_runtime_mark_last_busy(up->dev); |
288 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
289 | } |
290 | ||
291 | static void serial_omap_stop_rx(struct uart_port *port) | |
292 | { | |
c990f351 | 293 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 294 | |
d8ee4ea6 | 295 | pm_runtime_get_sync(up->dev); |
b612633b G |
296 | up->ier &= ~UART_IER_RLSI; |
297 | up->port.read_status_mask &= ~UART_LSR_DR; | |
298 | serial_out(up, UART_IER, up->ier); | |
d8ee4ea6 FB |
299 | pm_runtime_mark_last_busy(up->dev); |
300 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
301 | } |
302 | ||
bf63a086 | 303 | static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) |
b612633b G |
304 | { |
305 | struct circ_buf *xmit = &up->port.state->xmit; | |
306 | int count; | |
307 | ||
308 | if (up->port.x_char) { | |
309 | serial_out(up, UART_TX, up->port.x_char); | |
310 | up->port.icount.tx++; | |
311 | up->port.x_char = 0; | |
312 | return; | |
313 | } | |
314 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
315 | serial_omap_stop_tx(&up->port); | |
316 | return; | |
317 | } | |
c4415084 DF |
318 | count = up->port.fifosize - |
319 | (serial_in(up, UART_OMAP_TXFIFO_LVL) & 0xFF); | |
b612633b G |
320 | do { |
321 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
322 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
323 | up->port.icount.tx++; | |
324 | if (uart_circ_empty(xmit)) | |
325 | break; | |
326 | } while (--count > 0); | |
327 | ||
0324a821 RK |
328 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { |
329 | spin_unlock(&up->port.lock); | |
b612633b | 330 | uart_write_wakeup(&up->port); |
0324a821 RK |
331 | spin_lock(&up->port.lock); |
332 | } | |
b612633b G |
333 | |
334 | if (uart_circ_empty(xmit)) | |
335 | serial_omap_stop_tx(&up->port); | |
336 | } | |
337 | ||
338 | static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) | |
339 | { | |
340 | if (!(up->ier & UART_IER_THRI)) { | |
341 | up->ier |= UART_IER_THRI; | |
342 | serial_out(up, UART_IER, up->ier); | |
343 | } | |
344 | } | |
345 | ||
346 | static void serial_omap_start_tx(struct uart_port *port) | |
347 | { | |
c990f351 | 348 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 349 | |
49457430 FB |
350 | pm_runtime_get_sync(up->dev); |
351 | serial_omap_enable_ier_thri(up); | |
49457430 FB |
352 | pm_runtime_mark_last_busy(up->dev); |
353 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
354 | } |
355 | ||
3af08bd7 RK |
356 | static void serial_omap_throttle(struct uart_port *port) |
357 | { | |
358 | struct uart_omap_port *up = to_uart_omap_port(port); | |
359 | unsigned long flags; | |
360 | ||
361 | pm_runtime_get_sync(up->dev); | |
362 | spin_lock_irqsave(&up->port.lock, flags); | |
363 | up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); | |
364 | serial_out(up, UART_IER, up->ier); | |
365 | spin_unlock_irqrestore(&up->port.lock, flags); | |
366 | pm_runtime_mark_last_busy(up->dev); | |
367 | pm_runtime_put_autosuspend(up->dev); | |
368 | } | |
369 | ||
370 | static void serial_omap_unthrottle(struct uart_port *port) | |
371 | { | |
372 | struct uart_omap_port *up = to_uart_omap_port(port); | |
373 | unsigned long flags; | |
374 | ||
375 | pm_runtime_get_sync(up->dev); | |
376 | spin_lock_irqsave(&up->port.lock, flags); | |
377 | up->ier |= UART_IER_RLSI | UART_IER_RDI; | |
378 | serial_out(up, UART_IER, up->ier); | |
379 | spin_unlock_irqrestore(&up->port.lock, flags); | |
380 | pm_runtime_mark_last_busy(up->dev); | |
381 | pm_runtime_put_autosuspend(up->dev); | |
382 | } | |
383 | ||
b612633b G |
384 | static unsigned int check_modem_status(struct uart_omap_port *up) |
385 | { | |
386 | unsigned int status; | |
387 | ||
388 | status = serial_in(up, UART_MSR); | |
389 | status |= up->msr_saved_flags; | |
390 | up->msr_saved_flags = 0; | |
391 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
392 | return status; | |
393 | ||
394 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && | |
395 | up->port.state != NULL) { | |
396 | if (status & UART_MSR_TERI) | |
397 | up->port.icount.rng++; | |
398 | if (status & UART_MSR_DDSR) | |
399 | up->port.icount.dsr++; | |
400 | if (status & UART_MSR_DDCD) | |
401 | uart_handle_dcd_change | |
402 | (&up->port, status & UART_MSR_DCD); | |
403 | if (status & UART_MSR_DCTS) | |
404 | uart_handle_cts_change | |
405 | (&up->port, status & UART_MSR_CTS); | |
406 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); | |
407 | } | |
408 | ||
409 | return status; | |
410 | } | |
411 | ||
72256cbd FB |
412 | static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) |
413 | { | |
414 | unsigned int flag; | |
9a12fcf8 S |
415 | unsigned char ch = 0; |
416 | ||
417 | if (likely(lsr & UART_LSR_DR)) | |
418 | ch = serial_in(up, UART_RX); | |
72256cbd FB |
419 | |
420 | up->port.icount.rx++; | |
421 | flag = TTY_NORMAL; | |
422 | ||
423 | if (lsr & UART_LSR_BI) { | |
424 | flag = TTY_BREAK; | |
425 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
426 | up->port.icount.brk++; | |
427 | /* | |
428 | * We do the SysRQ and SAK checking | |
429 | * here because otherwise the break | |
430 | * may get masked by ignore_status_mask | |
431 | * or read_status_mask. | |
432 | */ | |
433 | if (uart_handle_break(&up->port)) | |
434 | return; | |
435 | ||
436 | } | |
437 | ||
438 | if (lsr & UART_LSR_PE) { | |
439 | flag = TTY_PARITY; | |
440 | up->port.icount.parity++; | |
441 | } | |
442 | ||
443 | if (lsr & UART_LSR_FE) { | |
444 | flag = TTY_FRAME; | |
445 | up->port.icount.frame++; | |
446 | } | |
447 | ||
448 | if (lsr & UART_LSR_OE) | |
449 | up->port.icount.overrun++; | |
450 | ||
451 | #ifdef CONFIG_SERIAL_OMAP_CONSOLE | |
452 | if (up->port.line == up->port.cons->index) { | |
453 | /* Recover the break flag from console xmit */ | |
454 | lsr |= up->lsr_break_flag; | |
455 | } | |
456 | #endif | |
457 | uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); | |
458 | } | |
459 | ||
460 | static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) | |
461 | { | |
462 | unsigned char ch = 0; | |
463 | unsigned int flag; | |
464 | ||
465 | if (!(lsr & UART_LSR_DR)) | |
466 | return; | |
467 | ||
468 | ch = serial_in(up, UART_RX); | |
469 | flag = TTY_NORMAL; | |
470 | up->port.icount.rx++; | |
471 | ||
472 | if (uart_handle_sysrq_char(&up->port, ch)) | |
473 | return; | |
474 | ||
475 | uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); | |
476 | } | |
477 | ||
b612633b G |
478 | /** |
479 | * serial_omap_irq() - This handles the interrupt from one port | |
480 | * @irq: uart port irq number | |
481 | * @dev_id: uart port info | |
482 | */ | |
52c5513d | 483 | static irqreturn_t serial_omap_irq(int irq, void *dev_id) |
b612633b G |
484 | { |
485 | struct uart_omap_port *up = dev_id; | |
486 | unsigned int iir, lsr; | |
81b75aef | 487 | unsigned int type; |
72256cbd | 488 | int max_count = 256; |
b612633b | 489 | |
6c3a30c7 | 490 | spin_lock(&up->port.lock); |
d8ee4ea6 | 491 | pm_runtime_get_sync(up->dev); |
72256cbd FB |
492 | |
493 | do { | |
81b75aef | 494 | iir = serial_in(up, UART_IIR); |
72256cbd FB |
495 | if (iir & UART_IIR_NO_INT) |
496 | break; | |
497 | ||
72256cbd FB |
498 | lsr = serial_in(up, UART_LSR); |
499 | ||
500 | /* extract IRQ type from IIR register */ | |
501 | type = iir & 0x3e; | |
502 | ||
503 | switch (type) { | |
504 | case UART_IIR_MSI: | |
505 | check_modem_status(up); | |
506 | break; | |
507 | case UART_IIR_THRI: | |
bf63a086 | 508 | transmit_chars(up, lsr); |
72256cbd FB |
509 | break; |
510 | case UART_IIR_RX_TIMEOUT: | |
511 | /* FALLTHROUGH */ | |
512 | case UART_IIR_RDI: | |
513 | serial_omap_rdi(up, lsr); | |
514 | break; | |
515 | case UART_IIR_RLSI: | |
516 | serial_omap_rlsi(up, lsr); | |
517 | break; | |
518 | case UART_IIR_CTS_RTS_DSR: | |
519 | /* simply try again */ | |
520 | break; | |
521 | case UART_IIR_XOFF: | |
522 | /* FALLTHROUGH */ | |
523 | default: | |
524 | break; | |
525 | } | |
526 | } while (!(iir & UART_IIR_NO_INT) && max_count--); | |
b612633b | 527 | |
6c3a30c7 | 528 | spin_unlock(&up->port.lock); |
72256cbd | 529 | |
2e124b4a | 530 | tty_flip_buffer_push(&up->port.state->port); |
72256cbd | 531 | |
d8ee4ea6 FB |
532 | pm_runtime_mark_last_busy(up->dev); |
533 | pm_runtime_put_autosuspend(up->dev); | |
b612633b | 534 | up->port_activity = jiffies; |
81b75aef | 535 | |
908fd7e5 | 536 | return IRQ_HANDLED; |
b612633b G |
537 | } |
538 | ||
539 | static unsigned int serial_omap_tx_empty(struct uart_port *port) | |
540 | { | |
c990f351 | 541 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
542 | unsigned long flags = 0; |
543 | unsigned int ret = 0; | |
544 | ||
d8ee4ea6 | 545 | pm_runtime_get_sync(up->dev); |
ba77433d | 546 | dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); |
b612633b G |
547 | spin_lock_irqsave(&up->port.lock, flags); |
548 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
549 | spin_unlock_irqrestore(&up->port.lock, flags); | |
660ac5f4 FB |
550 | pm_runtime_mark_last_busy(up->dev); |
551 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
552 | return ret; |
553 | } | |
554 | ||
555 | static unsigned int serial_omap_get_mctrl(struct uart_port *port) | |
556 | { | |
c990f351 | 557 | struct uart_omap_port *up = to_uart_omap_port(port); |
514f31d1 | 558 | unsigned int status; |
b612633b G |
559 | unsigned int ret = 0; |
560 | ||
d8ee4ea6 | 561 | pm_runtime_get_sync(up->dev); |
b612633b | 562 | status = check_modem_status(up); |
660ac5f4 FB |
563 | pm_runtime_mark_last_busy(up->dev); |
564 | pm_runtime_put_autosuspend(up->dev); | |
fcdca757 | 565 | |
ba77433d | 566 | dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); |
b612633b G |
567 | |
568 | if (status & UART_MSR_DCD) | |
569 | ret |= TIOCM_CAR; | |
570 | if (status & UART_MSR_RI) | |
571 | ret |= TIOCM_RNG; | |
572 | if (status & UART_MSR_DSR) | |
573 | ret |= TIOCM_DSR; | |
574 | if (status & UART_MSR_CTS) | |
575 | ret |= TIOCM_CTS; | |
576 | return ret; | |
577 | } | |
578 | ||
579 | static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
580 | { | |
c990f351 | 581 | struct uart_omap_port *up = to_uart_omap_port(port); |
9363f8fa | 582 | unsigned char mcr = 0, old_mcr; |
b612633b | 583 | |
ba77433d | 584 | dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); |
b612633b G |
585 | if (mctrl & TIOCM_RTS) |
586 | mcr |= UART_MCR_RTS; | |
587 | if (mctrl & TIOCM_DTR) | |
588 | mcr |= UART_MCR_DTR; | |
589 | if (mctrl & TIOCM_OUT1) | |
590 | mcr |= UART_MCR_OUT1; | |
591 | if (mctrl & TIOCM_OUT2) | |
592 | mcr |= UART_MCR_OUT2; | |
593 | if (mctrl & TIOCM_LOOP) | |
594 | mcr |= UART_MCR_LOOP; | |
595 | ||
d8ee4ea6 | 596 | pm_runtime_get_sync(up->dev); |
9363f8fa RK |
597 | old_mcr = serial_in(up, UART_MCR); |
598 | old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | | |
599 | UART_MCR_DTR | UART_MCR_RTS); | |
600 | up->mcr = old_mcr | mcr; | |
c538d20c | 601 | serial_out(up, UART_MCR, up->mcr); |
660ac5f4 FB |
602 | pm_runtime_mark_last_busy(up->dev); |
603 | pm_runtime_put_autosuspend(up->dev); | |
9574f36f N |
604 | |
605 | if (gpio_is_valid(up->DTR_gpio) && | |
606 | !!(mctrl & TIOCM_DTR) != up->DTR_active) { | |
607 | up->DTR_active = !up->DTR_active; | |
608 | if (gpio_cansleep(up->DTR_gpio)) | |
609 | schedule_work(&up->qos_work); | |
610 | else | |
611 | gpio_set_value(up->DTR_gpio, | |
612 | up->DTR_active != up->DTR_inverted); | |
613 | } | |
b612633b G |
614 | } |
615 | ||
616 | static void serial_omap_break_ctl(struct uart_port *port, int break_state) | |
617 | { | |
c990f351 | 618 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
619 | unsigned long flags = 0; |
620 | ||
ba77433d | 621 | dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); |
d8ee4ea6 | 622 | pm_runtime_get_sync(up->dev); |
b612633b G |
623 | spin_lock_irqsave(&up->port.lock, flags); |
624 | if (break_state == -1) | |
625 | up->lcr |= UART_LCR_SBC; | |
626 | else | |
627 | up->lcr &= ~UART_LCR_SBC; | |
628 | serial_out(up, UART_LCR, up->lcr); | |
629 | spin_unlock_irqrestore(&up->port.lock, flags); | |
660ac5f4 FB |
630 | pm_runtime_mark_last_busy(up->dev); |
631 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
632 | } |
633 | ||
634 | static int serial_omap_startup(struct uart_port *port) | |
635 | { | |
c990f351 | 636 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
637 | unsigned long flags = 0; |
638 | int retval; | |
639 | ||
640 | /* | |
641 | * Allocate the IRQ | |
642 | */ | |
643 | retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, | |
644 | up->name, up); | |
645 | if (retval) | |
646 | return retval; | |
647 | ||
ba77433d | 648 | dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); |
b612633b | 649 | |
d8ee4ea6 | 650 | pm_runtime_get_sync(up->dev); |
b612633b G |
651 | /* |
652 | * Clear the FIFO buffers and disable them. | |
653 | * (they will be reenabled in set_termios()) | |
654 | */ | |
655 | serial_omap_clear_fifos(up); | |
656 | /* For Hardware flow control */ | |
657 | serial_out(up, UART_MCR, UART_MCR_RTS); | |
658 | ||
659 | /* | |
660 | * Clear the interrupt registers. | |
661 | */ | |
662 | (void) serial_in(up, UART_LSR); | |
663 | if (serial_in(up, UART_LSR) & UART_LSR_DR) | |
664 | (void) serial_in(up, UART_RX); | |
665 | (void) serial_in(up, UART_IIR); | |
666 | (void) serial_in(up, UART_MSR); | |
667 | ||
668 | /* | |
669 | * Now, initialize the UART | |
670 | */ | |
671 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
672 | spin_lock_irqsave(&up->port.lock, flags); | |
673 | /* | |
674 | * Most PC uarts need OUT2 raised to enable interrupts. | |
675 | */ | |
676 | up->port.mctrl |= TIOCM_OUT2; | |
677 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
678 | spin_unlock_irqrestore(&up->port.lock, flags); | |
679 | ||
680 | up->msr_saved_flags = 0; | |
b612633b G |
681 | /* |
682 | * Finally, enable interrupts. Note: Modem status interrupts | |
683 | * are set via set_termios(), which will be occurring imminently | |
684 | * anyway, so we don't enable them here. | |
685 | */ | |
686 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
687 | serial_out(up, UART_IER, up->ier); | |
688 | ||
78841462 | 689 | /* Enable module level wake up */ |
f64ffda6 G |
690 | up->wer = OMAP_UART_WER_MOD_WKUP; |
691 | if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP) | |
692 | up->wer |= OMAP_UART_TX_WAKEUP_EN; | |
693 | ||
694 | serial_out(up, UART_OMAP_WER, up->wer); | |
78841462 | 695 | |
d8ee4ea6 FB |
696 | pm_runtime_mark_last_busy(up->dev); |
697 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
698 | up->port_activity = jiffies; |
699 | return 0; | |
700 | } | |
701 | ||
702 | static void serial_omap_shutdown(struct uart_port *port) | |
703 | { | |
c990f351 | 704 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
705 | unsigned long flags = 0; |
706 | ||
ba77433d | 707 | dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); |
fcdca757 | 708 | |
d8ee4ea6 | 709 | pm_runtime_get_sync(up->dev); |
b612633b G |
710 | /* |
711 | * Disable interrupts from this port | |
712 | */ | |
713 | up->ier = 0; | |
714 | serial_out(up, UART_IER, 0); | |
715 | ||
716 | spin_lock_irqsave(&up->port.lock, flags); | |
717 | up->port.mctrl &= ~TIOCM_OUT2; | |
718 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
719 | spin_unlock_irqrestore(&up->port.lock, flags); | |
720 | ||
721 | /* | |
722 | * Disable break condition and FIFOs | |
723 | */ | |
724 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | |
725 | serial_omap_clear_fifos(up); | |
726 | ||
727 | /* | |
728 | * Read data port to reset things, and then free the irq | |
729 | */ | |
730 | if (serial_in(up, UART_LSR) & UART_LSR_DR) | |
731 | (void) serial_in(up, UART_RX); | |
fcdca757 | 732 | |
660ac5f4 FB |
733 | pm_runtime_mark_last_busy(up->dev); |
734 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
735 | free_irq(up->port.irq, up); |
736 | } | |
737 | ||
2fd14964 G |
738 | static void serial_omap_uart_qos_work(struct work_struct *work) |
739 | { | |
740 | struct uart_omap_port *up = container_of(work, struct uart_omap_port, | |
741 | qos_work); | |
742 | ||
743 | pm_qos_update_request(&up->pm_qos_request, up->latency); | |
9574f36f N |
744 | if (gpio_is_valid(up->DTR_gpio)) |
745 | gpio_set_value_cansleep(up->DTR_gpio, | |
746 | up->DTR_active != up->DTR_inverted); | |
2fd14964 G |
747 | } |
748 | ||
b612633b G |
749 | static void |
750 | serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, | |
751 | struct ktermios *old) | |
752 | { | |
c990f351 | 753 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 754 | unsigned char cval = 0; |
b612633b G |
755 | unsigned long flags = 0; |
756 | unsigned int baud, quot; | |
757 | ||
758 | switch (termios->c_cflag & CSIZE) { | |
759 | case CS5: | |
760 | cval = UART_LCR_WLEN5; | |
761 | break; | |
762 | case CS6: | |
763 | cval = UART_LCR_WLEN6; | |
764 | break; | |
765 | case CS7: | |
766 | cval = UART_LCR_WLEN7; | |
767 | break; | |
768 | default: | |
769 | case CS8: | |
770 | cval = UART_LCR_WLEN8; | |
771 | break; | |
772 | } | |
773 | ||
774 | if (termios->c_cflag & CSTOPB) | |
775 | cval |= UART_LCR_STOP; | |
776 | if (termios->c_cflag & PARENB) | |
777 | cval |= UART_LCR_PARITY; | |
778 | if (!(termios->c_cflag & PARODD)) | |
779 | cval |= UART_LCR_EPAR; | |
fdbc7353 EBS |
780 | if (termios->c_cflag & CMSPAR) |
781 | cval |= UART_LCR_SPAR; | |
b612633b G |
782 | |
783 | /* | |
784 | * Ask the core to calculate the divisor for us. | |
785 | */ | |
786 | ||
787 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); | |
788 | quot = serial_omap_get_divisor(port, baud); | |
789 | ||
2fd14964 | 790 | /* calculate wakeup latency constraint */ |
19723452 | 791 | up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); |
2fd14964 G |
792 | up->latency = up->calc_latency; |
793 | schedule_work(&up->qos_work); | |
794 | ||
c538d20c G |
795 | up->dll = quot & 0xff; |
796 | up->dlh = quot >> 8; | |
797 | up->mdr1 = UART_OMAP_MDR1_DISABLE; | |
798 | ||
b612633b G |
799 | up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | |
800 | UART_FCR_ENABLE_FIFO; | |
b612633b G |
801 | |
802 | /* | |
803 | * Ok, we're now changing the port state. Do it with | |
804 | * interrupts disabled. | |
805 | */ | |
d8ee4ea6 | 806 | pm_runtime_get_sync(up->dev); |
b612633b G |
807 | spin_lock_irqsave(&up->port.lock, flags); |
808 | ||
809 | /* | |
810 | * Update the per-port timeout. | |
811 | */ | |
812 | uart_update_timeout(port, termios->c_cflag, baud); | |
813 | ||
814 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
815 | if (termios->c_iflag & INPCK) | |
816 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
817 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
818 | up->port.read_status_mask |= UART_LSR_BI; | |
819 | ||
820 | /* | |
821 | * Characters to ignore | |
822 | */ | |
823 | up->port.ignore_status_mask = 0; | |
824 | if (termios->c_iflag & IGNPAR) | |
825 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
826 | if (termios->c_iflag & IGNBRK) { | |
827 | up->port.ignore_status_mask |= UART_LSR_BI; | |
828 | /* | |
829 | * If we're ignoring parity and break indicators, | |
830 | * ignore overruns too (for real raw support). | |
831 | */ | |
832 | if (termios->c_iflag & IGNPAR) | |
833 | up->port.ignore_status_mask |= UART_LSR_OE; | |
834 | } | |
835 | ||
836 | /* | |
837 | * ignore all characters if CREAD is not set | |
838 | */ | |
839 | if ((termios->c_cflag & CREAD) == 0) | |
840 | up->port.ignore_status_mask |= UART_LSR_DR; | |
841 | ||
842 | /* | |
843 | * Modem status interrupts | |
844 | */ | |
845 | up->ier &= ~UART_IER_MSI; | |
846 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
847 | up->ier |= UART_IER_MSI; | |
848 | serial_out(up, UART_IER, up->ier); | |
849 | serial_out(up, UART_LCR, cval); /* reset DLAB */ | |
c538d20c | 850 | up->lcr = cval; |
1776fd05 | 851 | up->scr = 0; |
b612633b G |
852 | |
853 | /* FIFOs and DMA Settings */ | |
854 | ||
855 | /* FCR can be changed only when the | |
856 | * baud clock is not running | |
857 | * DLL_REG and DLH_REG set to 0. | |
858 | */ | |
662b083a | 859 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
860 | serial_out(up, UART_DLL, 0); |
861 | serial_out(up, UART_DLM, 0); | |
862 | serial_out(up, UART_LCR, 0); | |
863 | ||
662b083a | 864 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b | 865 | |
08bd4903 | 866 | up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; |
d864c03b | 867 | up->efr &= ~UART_EFR_SCD; |
b612633b G |
868 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); |
869 | ||
662b083a | 870 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
08bd4903 | 871 | up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; |
b612633b G |
872 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); |
873 | /* FIFO ENABLE, DMA MODE */ | |
0ba5f668 | 874 | |
1f663966 AP |
875 | up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; |
876 | /* | |
877 | * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | |
878 | * sets Enables the granularity of 1 for TRIGGER RX | |
879 | * level. Along with setting RX FIFO trigger level | |
880 | * to 1 (as noted below, 16 characters) and TLR[3:0] | |
881 | * to zero this will result RX FIFO threshold level | |
882 | * to 1 character, instead of 16 as noted in comment | |
883 | * below. | |
884 | */ | |
885 | ||
6721ab7f FB |
886 | /* Set receive FIFO threshold to 16 characters and |
887 | * transmit FIFO threshold to 16 spaces | |
888 | */ | |
49457430 | 889 | up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; |
6721ab7f FB |
890 | up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; |
891 | up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | | |
892 | UART_FCR_ENABLE_FIFO; | |
b612633b | 893 | |
0ba5f668 PW |
894 | serial_out(up, UART_FCR, up->fcr); |
895 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
896 | ||
c538d20c G |
897 | serial_out(up, UART_OMAP_SCR, up->scr); |
898 | ||
08bd4903 | 899 | /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ |
662b083a | 900 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b | 901 | serial_out(up, UART_MCR, up->mcr); |
08bd4903 RK |
902 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
903 | serial_out(up, UART_EFR, up->efr); | |
904 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
b612633b G |
905 | |
906 | /* Protocol, Baud Rate, and Interrupt Settings */ | |
907 | ||
94734749 G |
908 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
909 | serial_omap_mdr1_errataset(up, up->mdr1); | |
910 | else | |
911 | serial_out(up, UART_OMAP_MDR1, up->mdr1); | |
912 | ||
662b083a | 913 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
914 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); |
915 | ||
916 | serial_out(up, UART_LCR, 0); | |
917 | serial_out(up, UART_IER, 0); | |
662b083a | 918 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b | 919 | |
c538d20c G |
920 | serial_out(up, UART_DLL, up->dll); /* LS of divisor */ |
921 | serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ | |
b612633b G |
922 | |
923 | serial_out(up, UART_LCR, 0); | |
924 | serial_out(up, UART_IER, up->ier); | |
662b083a | 925 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
926 | |
927 | serial_out(up, UART_EFR, up->efr); | |
928 | serial_out(up, UART_LCR, cval); | |
929 | ||
5fe21236 | 930 | if (!serial_omap_baud_is_mode16(port, baud)) |
c538d20c | 931 | up->mdr1 = UART_OMAP_MDR1_13X_MODE; |
b612633b | 932 | else |
c538d20c G |
933 | up->mdr1 = UART_OMAP_MDR1_16X_MODE; |
934 | ||
94734749 G |
935 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
936 | serial_omap_mdr1_errataset(up, up->mdr1); | |
937 | else | |
938 | serial_out(up, UART_OMAP_MDR1, up->mdr1); | |
b612633b | 939 | |
c533e51b | 940 | /* Configure flow control */ |
c7d059ca | 941 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
c533e51b RK |
942 | |
943 | /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ | |
944 | serial_out(up, UART_XON1, termios->c_cc[VSTART]); | |
945 | serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); | |
946 | ||
947 | /* Enable access to TCR/TLR */ | |
c7d059ca RK |
948 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); |
949 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
950 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); | |
b612633b | 951 | |
c7d059ca | 952 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); |
b612633b | 953 | |
c7d059ca | 954 | if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { |
08bd4903 RK |
955 | /* Enable AUTORTS and AUTOCTS */ |
956 | up->efr |= UART_EFR_CTS | UART_EFR_RTS; | |
957 | ||
1fe8aa88 RK |
958 | /* Ensure MCR RTS is asserted */ |
959 | up->mcr |= UART_MCR_RTS; | |
0d5b1663 RK |
960 | } else { |
961 | /* Disable AUTORTS and AUTOCTS */ | |
962 | up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); | |
b612633b | 963 | } |
b612633b | 964 | |
01d70bb3 | 965 | if (up->port.flags & UPF_SOFT_FLOW) { |
01d70bb3 RK |
966 | /* clear SW control mode bits */ |
967 | up->efr &= OMAP_UART_SW_CLR; | |
b612633b | 968 | |
01d70bb3 RK |
969 | /* |
970 | * IXON Flag: | |
3af08bd7 RK |
971 | * Enable XON/XOFF flow control on input. |
972 | * Receiver compares XON1, XOFF1. | |
01d70bb3 RK |
973 | */ |
974 | if (termios->c_iflag & IXON) | |
3af08bd7 | 975 | up->efr |= OMAP_UART_SW_RX; |
b612633b | 976 | |
01d70bb3 RK |
977 | /* |
978 | * IXOFF Flag: | |
3af08bd7 RK |
979 | * Enable XON/XOFF flow control on output. |
980 | * Transmit XON1, XOFF1 | |
01d70bb3 RK |
981 | */ |
982 | if (termios->c_iflag & IXOFF) | |
3af08bd7 | 983 | up->efr |= OMAP_UART_SW_TX; |
b612633b | 984 | |
01d70bb3 RK |
985 | /* |
986 | * IXANY Flag: | |
987 | * Enable any character to restart output. | |
988 | * Operation resumes after receiving any | |
989 | * character after recognition of the XOFF character | |
990 | */ | |
991 | if (termios->c_iflag & IXANY) | |
992 | up->mcr |= UART_MCR_XONANY; | |
993 | else | |
994 | up->mcr &= ~UART_MCR_XONANY; | |
b612633b | 995 | } |
c7d059ca | 996 | serial_out(up, UART_MCR, up->mcr); |
18f360f8 RK |
997 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
998 | serial_out(up, UART_EFR, up->efr); | |
999 | serial_out(up, UART_LCR, up->lcr); | |
b612633b G |
1000 | |
1001 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
b612633b G |
1002 | |
1003 | spin_unlock_irqrestore(&up->port.lock, flags); | |
660ac5f4 FB |
1004 | pm_runtime_mark_last_busy(up->dev); |
1005 | pm_runtime_put_autosuspend(up->dev); | |
ba77433d | 1006 | dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); |
b612633b G |
1007 | } |
1008 | ||
9727faf4 FB |
1009 | static int serial_omap_set_wake(struct uart_port *port, unsigned int state) |
1010 | { | |
1011 | struct uart_omap_port *up = to_uart_omap_port(port); | |
1012 | ||
1013 | serial_omap_enable_wakeup(up, state); | |
1014 | ||
1015 | return 0; | |
1016 | } | |
1017 | ||
b612633b G |
1018 | static void |
1019 | serial_omap_pm(struct uart_port *port, unsigned int state, | |
1020 | unsigned int oldstate) | |
1021 | { | |
c990f351 | 1022 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
1023 | unsigned char efr; |
1024 | ||
ba77433d | 1025 | dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); |
fcdca757 | 1026 | |
d8ee4ea6 | 1027 | pm_runtime_get_sync(up->dev); |
662b083a | 1028 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
1029 | efr = serial_in(up, UART_EFR); |
1030 | serial_out(up, UART_EFR, efr | UART_EFR_ECB); | |
1031 | serial_out(up, UART_LCR, 0); | |
1032 | ||
1033 | serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); | |
662b083a | 1034 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
1035 | serial_out(up, UART_EFR, efr); |
1036 | serial_out(up, UART_LCR, 0); | |
fcdca757 | 1037 | |
d8ee4ea6 | 1038 | if (!device_may_wakeup(up->dev)) { |
fcdca757 | 1039 | if (!state) |
d8ee4ea6 | 1040 | pm_runtime_forbid(up->dev); |
fcdca757 | 1041 | else |
d8ee4ea6 | 1042 | pm_runtime_allow(up->dev); |
fcdca757 G |
1043 | } |
1044 | ||
660ac5f4 FB |
1045 | pm_runtime_mark_last_busy(up->dev); |
1046 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
1047 | } |
1048 | ||
1049 | static void serial_omap_release_port(struct uart_port *port) | |
1050 | { | |
1051 | dev_dbg(port->dev, "serial_omap_release_port+\n"); | |
1052 | } | |
1053 | ||
1054 | static int serial_omap_request_port(struct uart_port *port) | |
1055 | { | |
1056 | dev_dbg(port->dev, "serial_omap_request_port+\n"); | |
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | static void serial_omap_config_port(struct uart_port *port, int flags) | |
1061 | { | |
c990f351 | 1062 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
1063 | |
1064 | dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", | |
ba77433d | 1065 | up->port.line); |
b612633b | 1066 | up->port.type = PORT_OMAP; |
3af08bd7 | 1067 | up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW; |
b612633b G |
1068 | } |
1069 | ||
1070 | static int | |
1071 | serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1072 | { | |
1073 | /* we don't want the core code to modify any port params */ | |
1074 | dev_dbg(port->dev, "serial_omap_verify_port+\n"); | |
1075 | return -EINVAL; | |
1076 | } | |
1077 | ||
1078 | static const char * | |
1079 | serial_omap_type(struct uart_port *port) | |
1080 | { | |
c990f351 | 1081 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 1082 | |
ba77433d | 1083 | dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); |
b612633b G |
1084 | return up->name; |
1085 | } | |
1086 | ||
b612633b G |
1087 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
1088 | ||
1089 | static inline void wait_for_xmitr(struct uart_omap_port *up) | |
1090 | { | |
1091 | unsigned int status, tmout = 10000; | |
1092 | ||
1093 | /* Wait up to 10ms for the character(s) to be sent. */ | |
1094 | do { | |
1095 | status = serial_in(up, UART_LSR); | |
1096 | ||
1097 | if (status & UART_LSR_BI) | |
1098 | up->lsr_break_flag = UART_LSR_BI; | |
1099 | ||
1100 | if (--tmout == 0) | |
1101 | break; | |
1102 | udelay(1); | |
1103 | } while ((status & BOTH_EMPTY) != BOTH_EMPTY); | |
1104 | ||
1105 | /* Wait up to 1s for flow control if necessary */ | |
1106 | if (up->port.flags & UPF_CONS_FLOW) { | |
1107 | tmout = 1000000; | |
1108 | for (tmout = 1000000; tmout; tmout--) { | |
1109 | unsigned int msr = serial_in(up, UART_MSR); | |
1110 | ||
1111 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; | |
1112 | if (msr & UART_MSR_CTS) | |
1113 | break; | |
1114 | ||
1115 | udelay(1); | |
1116 | } | |
1117 | } | |
1118 | } | |
1119 | ||
1b41dbc1 CC |
1120 | #ifdef CONFIG_CONSOLE_POLL |
1121 | ||
1122 | static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) | |
1123 | { | |
c990f351 | 1124 | struct uart_omap_port *up = to_uart_omap_port(port); |
fcdca757 | 1125 | |
d8ee4ea6 | 1126 | pm_runtime_get_sync(up->dev); |
1b41dbc1 CC |
1127 | wait_for_xmitr(up); |
1128 | serial_out(up, UART_TX, ch); | |
660ac5f4 FB |
1129 | pm_runtime_mark_last_busy(up->dev); |
1130 | pm_runtime_put_autosuspend(up->dev); | |
1b41dbc1 CC |
1131 | } |
1132 | ||
1133 | static int serial_omap_poll_get_char(struct uart_port *port) | |
1134 | { | |
c990f351 | 1135 | struct uart_omap_port *up = to_uart_omap_port(port); |
fcdca757 | 1136 | unsigned int status; |
1b41dbc1 | 1137 | |
d8ee4ea6 | 1138 | pm_runtime_get_sync(up->dev); |
fcdca757 | 1139 | status = serial_in(up, UART_LSR); |
a6b19c33 FB |
1140 | if (!(status & UART_LSR_DR)) { |
1141 | status = NO_POLL_CHAR; | |
1142 | goto out; | |
1143 | } | |
1b41dbc1 | 1144 | |
fcdca757 | 1145 | status = serial_in(up, UART_RX); |
a6b19c33 FB |
1146 | |
1147 | out: | |
660ac5f4 FB |
1148 | pm_runtime_mark_last_busy(up->dev); |
1149 | pm_runtime_put_autosuspend(up->dev); | |
a6b19c33 | 1150 | |
fcdca757 | 1151 | return status; |
1b41dbc1 CC |
1152 | } |
1153 | ||
1154 | #endif /* CONFIG_CONSOLE_POLL */ | |
1155 | ||
1156 | #ifdef CONFIG_SERIAL_OMAP_CONSOLE | |
1157 | ||
40477d0e | 1158 | static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS]; |
1b41dbc1 CC |
1159 | |
1160 | static struct uart_driver serial_omap_reg; | |
1161 | ||
b612633b G |
1162 | static void serial_omap_console_putchar(struct uart_port *port, int ch) |
1163 | { | |
c990f351 | 1164 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
1165 | |
1166 | wait_for_xmitr(up); | |
1167 | serial_out(up, UART_TX, ch); | |
1168 | } | |
1169 | ||
1170 | static void | |
1171 | serial_omap_console_write(struct console *co, const char *s, | |
1172 | unsigned int count) | |
1173 | { | |
1174 | struct uart_omap_port *up = serial_omap_console_ports[co->index]; | |
1175 | unsigned long flags; | |
1176 | unsigned int ier; | |
1177 | int locked = 1; | |
1178 | ||
d8ee4ea6 | 1179 | pm_runtime_get_sync(up->dev); |
fcdca757 | 1180 | |
b612633b G |
1181 | local_irq_save(flags); |
1182 | if (up->port.sysrq) | |
1183 | locked = 0; | |
1184 | else if (oops_in_progress) | |
1185 | locked = spin_trylock(&up->port.lock); | |
1186 | else | |
1187 | spin_lock(&up->port.lock); | |
1188 | ||
1189 | /* | |
1190 | * First save the IER then disable the interrupts | |
1191 | */ | |
1192 | ier = serial_in(up, UART_IER); | |
1193 | serial_out(up, UART_IER, 0); | |
1194 | ||
1195 | uart_console_write(&up->port, s, count, serial_omap_console_putchar); | |
1196 | ||
1197 | /* | |
1198 | * Finally, wait for transmitter to become empty | |
1199 | * and restore the IER | |
1200 | */ | |
1201 | wait_for_xmitr(up); | |
1202 | serial_out(up, UART_IER, ier); | |
1203 | /* | |
1204 | * The receive handling will happen properly because the | |
1205 | * receive ready bit will still be set; it is not cleared | |
1206 | * on read. However, modem control will not, we must | |
1207 | * call it if we have saved something in the saved flags | |
1208 | * while processing with interrupts off. | |
1209 | */ | |
1210 | if (up->msr_saved_flags) | |
1211 | check_modem_status(up); | |
1212 | ||
d8ee4ea6 FB |
1213 | pm_runtime_mark_last_busy(up->dev); |
1214 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
1215 | if (locked) |
1216 | spin_unlock(&up->port.lock); | |
1217 | local_irq_restore(flags); | |
1218 | } | |
1219 | ||
1220 | static int __init | |
1221 | serial_omap_console_setup(struct console *co, char *options) | |
1222 | { | |
1223 | struct uart_omap_port *up; | |
1224 | int baud = 115200; | |
1225 | int bits = 8; | |
1226 | int parity = 'n'; | |
1227 | int flow = 'n'; | |
1228 | ||
1229 | if (serial_omap_console_ports[co->index] == NULL) | |
1230 | return -ENODEV; | |
1231 | up = serial_omap_console_ports[co->index]; | |
1232 | ||
1233 | if (options) | |
1234 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1235 | ||
1236 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
1237 | } | |
1238 | ||
1239 | static struct console serial_omap_console = { | |
1240 | .name = OMAP_SERIAL_NAME, | |
1241 | .write = serial_omap_console_write, | |
1242 | .device = uart_console_device, | |
1243 | .setup = serial_omap_console_setup, | |
1244 | .flags = CON_PRINTBUFFER, | |
1245 | .index = -1, | |
1246 | .data = &serial_omap_reg, | |
1247 | }; | |
1248 | ||
1249 | static void serial_omap_add_console_port(struct uart_omap_port *up) | |
1250 | { | |
ba77433d | 1251 | serial_omap_console_ports[up->port.line] = up; |
b612633b G |
1252 | } |
1253 | ||
1254 | #define OMAP_CONSOLE (&serial_omap_console) | |
1255 | ||
1256 | #else | |
1257 | ||
1258 | #define OMAP_CONSOLE NULL | |
1259 | ||
1260 | static inline void serial_omap_add_console_port(struct uart_omap_port *up) | |
1261 | {} | |
1262 | ||
1263 | #endif | |
1264 | ||
1265 | static struct uart_ops serial_omap_pops = { | |
1266 | .tx_empty = serial_omap_tx_empty, | |
1267 | .set_mctrl = serial_omap_set_mctrl, | |
1268 | .get_mctrl = serial_omap_get_mctrl, | |
1269 | .stop_tx = serial_omap_stop_tx, | |
1270 | .start_tx = serial_omap_start_tx, | |
3af08bd7 RK |
1271 | .throttle = serial_omap_throttle, |
1272 | .unthrottle = serial_omap_unthrottle, | |
b612633b G |
1273 | .stop_rx = serial_omap_stop_rx, |
1274 | .enable_ms = serial_omap_enable_ms, | |
1275 | .break_ctl = serial_omap_break_ctl, | |
1276 | .startup = serial_omap_startup, | |
1277 | .shutdown = serial_omap_shutdown, | |
1278 | .set_termios = serial_omap_set_termios, | |
1279 | .pm = serial_omap_pm, | |
9727faf4 | 1280 | .set_wake = serial_omap_set_wake, |
b612633b G |
1281 | .type = serial_omap_type, |
1282 | .release_port = serial_omap_release_port, | |
1283 | .request_port = serial_omap_request_port, | |
1284 | .config_port = serial_omap_config_port, | |
1285 | .verify_port = serial_omap_verify_port, | |
1b41dbc1 CC |
1286 | #ifdef CONFIG_CONSOLE_POLL |
1287 | .poll_put_char = serial_omap_poll_put_char, | |
1288 | .poll_get_char = serial_omap_poll_get_char, | |
1289 | #endif | |
b612633b G |
1290 | }; |
1291 | ||
1292 | static struct uart_driver serial_omap_reg = { | |
1293 | .owner = THIS_MODULE, | |
1294 | .driver_name = "OMAP-SERIAL", | |
1295 | .dev_name = OMAP_SERIAL_NAME, | |
1296 | .nr = OMAP_MAX_HSUART_PORTS, | |
1297 | .cons = OMAP_CONSOLE, | |
1298 | }; | |
1299 | ||
3bc4f0d8 | 1300 | #ifdef CONFIG_PM_SLEEP |
ddd85e22 SP |
1301 | static int serial_omap_prepare(struct device *dev) |
1302 | { | |
1303 | struct uart_omap_port *up = dev_get_drvdata(dev); | |
1304 | ||
1305 | up->is_suspending = true; | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | ||
1310 | static void serial_omap_complete(struct device *dev) | |
1311 | { | |
1312 | struct uart_omap_port *up = dev_get_drvdata(dev); | |
1313 | ||
1314 | up->is_suspending = false; | |
1315 | } | |
1316 | ||
fcdca757 | 1317 | static int serial_omap_suspend(struct device *dev) |
b612633b | 1318 | { |
fcdca757 | 1319 | struct uart_omap_port *up = dev_get_drvdata(dev); |
b612633b | 1320 | |
ac57e7f3 | 1321 | uart_suspend_port(&serial_omap_reg, &up->port); |
033d9959 | 1322 | flush_work(&up->qos_work); |
2fd14964 | 1323 | |
b612633b G |
1324 | return 0; |
1325 | } | |
1326 | ||
fcdca757 | 1327 | static int serial_omap_resume(struct device *dev) |
b612633b | 1328 | { |
fcdca757 | 1329 | struct uart_omap_port *up = dev_get_drvdata(dev); |
b612633b | 1330 | |
ac57e7f3 SP |
1331 | uart_resume_port(&serial_omap_reg, &up->port); |
1332 | ||
b612633b G |
1333 | return 0; |
1334 | } | |
ddd85e22 SP |
1335 | #else |
1336 | #define serial_omap_prepare NULL | |
2cb5a2fa | 1337 | #define serial_omap_complete NULL |
ddd85e22 | 1338 | #endif /* CONFIG_PM_SLEEP */ |
b612633b | 1339 | |
9671f099 | 1340 | static void omap_serial_fill_features_erratas(struct uart_omap_port *up) |
7c77c8de G |
1341 | { |
1342 | u32 mvr, scheme; | |
1343 | u16 revision, major, minor; | |
1344 | ||
76bac198 | 1345 | mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift)); |
7c77c8de G |
1346 | |
1347 | /* Check revision register scheme */ | |
1348 | scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; | |
1349 | ||
1350 | switch (scheme) { | |
1351 | case 0: /* Legacy Scheme: OMAP2/3 */ | |
1352 | /* MINOR_REV[0:4], MAJOR_REV[4:7] */ | |
1353 | major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> | |
1354 | OMAP_UART_LEGACY_MVR_MAJ_SHIFT; | |
1355 | minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); | |
1356 | break; | |
1357 | case 1: | |
1358 | /* New Scheme: OMAP4+ */ | |
1359 | /* MINOR_REV[0:5], MAJOR_REV[8:10] */ | |
1360 | major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> | |
1361 | OMAP_UART_MVR_MAJ_SHIFT; | |
1362 | minor = (mvr & OMAP_UART_MVR_MIN_MASK); | |
1363 | break; | |
1364 | default: | |
d8ee4ea6 | 1365 | dev_warn(up->dev, |
7c77c8de G |
1366 | "Unknown %s revision, defaulting to highest\n", |
1367 | up->name); | |
1368 | /* highest possible revision */ | |
1369 | major = 0xff; | |
1370 | minor = 0xff; | |
1371 | } | |
1372 | ||
1373 | /* normalize revision for the driver */ | |
1374 | revision = UART_BUILD_REVISION(major, minor); | |
1375 | ||
1376 | switch (revision) { | |
1377 | case OMAP_UART_REV_46: | |
1378 | up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | | |
1379 | UART_ERRATA_i291_DMA_FORCEIDLE); | |
1380 | break; | |
1381 | case OMAP_UART_REV_52: | |
1382 | up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | | |
1383 | UART_ERRATA_i291_DMA_FORCEIDLE); | |
f64ffda6 | 1384 | up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; |
7c77c8de G |
1385 | break; |
1386 | case OMAP_UART_REV_63: | |
1387 | up->errata |= UART_ERRATA_i202_MDR1_ACCESS; | |
f64ffda6 | 1388 | up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; |
7c77c8de G |
1389 | break; |
1390 | default: | |
1391 | break; | |
1392 | } | |
1393 | } | |
1394 | ||
9671f099 | 1395 | static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) |
d92b0dfc RN |
1396 | { |
1397 | struct omap_uart_port_info *omap_up_info; | |
1398 | ||
1399 | omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); | |
1400 | if (!omap_up_info) | |
1401 | return NULL; /* out of memory */ | |
1402 | ||
1403 | of_property_read_u32(dev->of_node, "clock-frequency", | |
1404 | &omap_up_info->uartclk); | |
1405 | return omap_up_info; | |
1406 | } | |
1407 | ||
9671f099 | 1408 | static int serial_omap_probe(struct platform_device *pdev) |
b612633b G |
1409 | { |
1410 | struct uart_omap_port *up; | |
49457430 | 1411 | struct resource *mem, *irq; |
b612633b | 1412 | struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; |
9574f36f | 1413 | int ret; |
b612633b | 1414 | |
a0a490f9 | 1415 | if (pdev->dev.of_node) { |
d92b0dfc | 1416 | omap_up_info = of_get_uart_port_info(&pdev->dev); |
a0a490f9 VP |
1417 | pdev->dev.platform_data = omap_up_info; |
1418 | } | |
d92b0dfc | 1419 | |
b612633b G |
1420 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1421 | if (!mem) { | |
1422 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1423 | return -ENODEV; | |
1424 | } | |
1425 | ||
1426 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1427 | if (!irq) { | |
1428 | dev_err(&pdev->dev, "no irq resource?\n"); | |
1429 | return -ENODEV; | |
1430 | } | |
1431 | ||
388bc262 | 1432 | if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem), |
28f65c11 | 1433 | pdev->dev.driver->name)) { |
b612633b G |
1434 | dev_err(&pdev->dev, "memory region already claimed\n"); |
1435 | return -EBUSY; | |
1436 | } | |
1437 | ||
9574f36f N |
1438 | if (gpio_is_valid(omap_up_info->DTR_gpio) && |
1439 | omap_up_info->DTR_present) { | |
1440 | ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial"); | |
1441 | if (ret < 0) | |
1442 | return ret; | |
1443 | ret = gpio_direction_output(omap_up_info->DTR_gpio, | |
1444 | omap_up_info->DTR_inverted); | |
1445 | if (ret < 0) | |
1446 | return ret; | |
1447 | } | |
1448 | ||
388bc262 S |
1449 | up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); |
1450 | if (!up) | |
1451 | return -ENOMEM; | |
b612633b | 1452 | |
9574f36f N |
1453 | if (gpio_is_valid(omap_up_info->DTR_gpio) && |
1454 | omap_up_info->DTR_present) { | |
1455 | up->DTR_gpio = omap_up_info->DTR_gpio; | |
1456 | up->DTR_inverted = omap_up_info->DTR_inverted; | |
1457 | } else | |
1458 | up->DTR_gpio = -EINVAL; | |
1459 | up->DTR_active = 0; | |
1460 | ||
d8ee4ea6 | 1461 | up->dev = &pdev->dev; |
b612633b G |
1462 | up->port.dev = &pdev->dev; |
1463 | up->port.type = PORT_OMAP; | |
1464 | up->port.iotype = UPIO_MEM; | |
1465 | up->port.irq = irq->start; | |
1466 | ||
1467 | up->port.regshift = 2; | |
1468 | up->port.fifosize = 64; | |
1469 | up->port.ops = &serial_omap_pops; | |
b612633b | 1470 | |
d92b0dfc RN |
1471 | if (pdev->dev.of_node) |
1472 | up->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); | |
1473 | else | |
1474 | up->port.line = pdev->id; | |
1475 | ||
1476 | if (up->port.line < 0) { | |
1477 | dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", | |
1478 | up->port.line); | |
1479 | ret = -ENODEV; | |
388bc262 | 1480 | goto err_port_line; |
d92b0dfc RN |
1481 | } |
1482 | ||
1483 | sprintf(up->name, "OMAP UART%d", up->port.line); | |
edd70ad7 | 1484 | up->port.mapbase = mem->start; |
388bc262 S |
1485 | up->port.membase = devm_ioremap(&pdev->dev, mem->start, |
1486 | resource_size(mem)); | |
edd70ad7 G |
1487 | if (!up->port.membase) { |
1488 | dev_err(&pdev->dev, "can't ioremap UART\n"); | |
1489 | ret = -ENOMEM; | |
388bc262 | 1490 | goto err_ioremap; |
edd70ad7 G |
1491 | } |
1492 | ||
b612633b | 1493 | up->port.flags = omap_up_info->flags; |
b612633b | 1494 | up->port.uartclk = omap_up_info->uartclk; |
8fe789dc RN |
1495 | if (!up->port.uartclk) { |
1496 | up->port.uartclk = DEFAULT_CLK_SPEED; | |
1497 | dev_warn(&pdev->dev, "No clock speed specified: using default:" | |
1498 | "%d\n", DEFAULT_CLK_SPEED); | |
1499 | } | |
b612633b | 1500 | |
2fd14964 G |
1501 | up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
1502 | up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; | |
1503 | pm_qos_add_request(&up->pm_qos_request, | |
1504 | PM_QOS_CPU_DMA_LATENCY, up->latency); | |
1505 | serial_omap_uart_wq = create_singlethread_workqueue(up->name); | |
1506 | INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); | |
1507 | ||
93220dcc | 1508 | platform_set_drvdata(pdev, up); |
856e35bf | 1509 | pm_runtime_enable(&pdev->dev); |
a630fbfb TL |
1510 | if (omap_up_info->autosuspend_timeout == 0) |
1511 | omap_up_info->autosuspend_timeout = -1; | |
1512 | device_init_wakeup(up->dev, true); | |
fcdca757 G |
1513 | pm_runtime_use_autosuspend(&pdev->dev); |
1514 | pm_runtime_set_autosuspend_delay(&pdev->dev, | |
c86845db | 1515 | omap_up_info->autosuspend_timeout); |
fcdca757 G |
1516 | |
1517 | pm_runtime_irq_safe(&pdev->dev); | |
fcdca757 G |
1518 | pm_runtime_get_sync(&pdev->dev); |
1519 | ||
7c77c8de G |
1520 | omap_serial_fill_features_erratas(up); |
1521 | ||
ba77433d | 1522 | ui[up->port.line] = up; |
b612633b G |
1523 | serial_omap_add_console_port(up); |
1524 | ||
1525 | ret = uart_add_one_port(&serial_omap_reg, &up->port); | |
1526 | if (ret != 0) | |
388bc262 | 1527 | goto err_add_port; |
b612633b | 1528 | |
660ac5f4 FB |
1529 | pm_runtime_mark_last_busy(up->dev); |
1530 | pm_runtime_put_autosuspend(up->dev); | |
b612633b | 1531 | return 0; |
388bc262 S |
1532 | |
1533 | err_add_port: | |
1534 | pm_runtime_put(&pdev->dev); | |
1535 | pm_runtime_disable(&pdev->dev); | |
1536 | err_ioremap: | |
1537 | err_port_line: | |
b612633b G |
1538 | dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", |
1539 | pdev->id, __func__, ret); | |
b612633b G |
1540 | return ret; |
1541 | } | |
1542 | ||
ae8d8a14 | 1543 | static int serial_omap_remove(struct platform_device *dev) |
b612633b G |
1544 | { |
1545 | struct uart_omap_port *up = platform_get_drvdata(dev); | |
1546 | ||
7e9c8e7d | 1547 | pm_runtime_put_sync(up->dev); |
1b42c8b2 FB |
1548 | pm_runtime_disable(up->dev); |
1549 | uart_remove_one_port(&serial_omap_reg, &up->port); | |
1550 | pm_qos_remove_request(&up->pm_qos_request); | |
fcdca757 | 1551 | |
fcdca757 G |
1552 | return 0; |
1553 | } | |
1554 | ||
94734749 G |
1555 | /* |
1556 | * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) | |
1557 | * The access to uart register after MDR1 Access | |
1558 | * causes UART to corrupt data. | |
1559 | * | |
1560 | * Need a delay = | |
1561 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) | |
1562 | * give 10 times as much | |
1563 | */ | |
1564 | static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) | |
1565 | { | |
1566 | u8 timeout = 255; | |
1567 | ||
1568 | serial_out(up, UART_OMAP_MDR1, mdr1); | |
1569 | udelay(2); | |
1570 | serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | | |
1571 | UART_FCR_CLEAR_RCVR); | |
1572 | /* | |
1573 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and | |
1574 | * TX_FIFO_E bit is 1. | |
1575 | */ | |
1576 | while (UART_LSR_THRE != (serial_in(up, UART_LSR) & | |
1577 | (UART_LSR_THRE | UART_LSR_DR))) { | |
1578 | timeout--; | |
1579 | if (!timeout) { | |
1580 | /* Should *never* happen. we warn and carry on */ | |
d8ee4ea6 | 1581 | dev_crit(up->dev, "Errata i202: timedout %x\n", |
94734749 G |
1582 | serial_in(up, UART_LSR)); |
1583 | break; | |
1584 | } | |
1585 | udelay(1); | |
1586 | } | |
1587 | } | |
1588 | ||
b5148856 | 1589 | #ifdef CONFIG_PM_RUNTIME |
9f9ac1e8 G |
1590 | static void serial_omap_restore_context(struct uart_omap_port *up) |
1591 | { | |
94734749 G |
1592 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
1593 | serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); | |
1594 | else | |
1595 | serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); | |
1596 | ||
9f9ac1e8 G |
1597 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ |
1598 | serial_out(up, UART_EFR, UART_EFR_ECB); | |
1599 | serial_out(up, UART_LCR, 0x0); /* Operational mode */ | |
1600 | serial_out(up, UART_IER, 0x0); | |
1601 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ | |
c538d20c G |
1602 | serial_out(up, UART_DLL, up->dll); |
1603 | serial_out(up, UART_DLM, up->dlh); | |
9f9ac1e8 G |
1604 | serial_out(up, UART_LCR, 0x0); /* Operational mode */ |
1605 | serial_out(up, UART_IER, up->ier); | |
1606 | serial_out(up, UART_FCR, up->fcr); | |
1607 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
1608 | serial_out(up, UART_MCR, up->mcr); | |
1609 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ | |
c538d20c | 1610 | serial_out(up, UART_OMAP_SCR, up->scr); |
9f9ac1e8 G |
1611 | serial_out(up, UART_EFR, up->efr); |
1612 | serial_out(up, UART_LCR, up->lcr); | |
94734749 G |
1613 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
1614 | serial_omap_mdr1_errataset(up, up->mdr1); | |
1615 | else | |
1616 | serial_out(up, UART_OMAP_MDR1, up->mdr1); | |
f64ffda6 | 1617 | serial_out(up, UART_OMAP_WER, up->wer); |
9f9ac1e8 G |
1618 | } |
1619 | ||
fcdca757 G |
1620 | static int serial_omap_runtime_suspend(struct device *dev) |
1621 | { | |
ec3bebc6 | 1622 | struct uart_omap_port *up = dev_get_drvdata(dev); |
ec3bebc6 | 1623 | |
7f25301d WY |
1624 | if (!up) |
1625 | return -EINVAL; | |
1626 | ||
ddd85e22 SP |
1627 | /* |
1628 | * When using 'no_console_suspend', the console UART must not be | |
1629 | * suspended. Since driver suspend is managed by runtime suspend, | |
1630 | * preventing runtime suspend (by returning error) will keep device | |
1631 | * active during suspend. | |
1632 | */ | |
1633 | if (up->is_suspending && !console_suspend_enabled && | |
1634 | uart_console(&up->port)) | |
1635 | return -EBUSY; | |
1636 | ||
e5b57c03 | 1637 | up->context_loss_cnt = serial_omap_get_context_loss_count(up); |
ec3bebc6 | 1638 | |
62f3ec5f G |
1639 | if (device_may_wakeup(dev)) { |
1640 | if (!up->wakeups_enabled) { | |
e5b57c03 | 1641 | serial_omap_enable_wakeup(up, true); |
62f3ec5f G |
1642 | up->wakeups_enabled = true; |
1643 | } | |
1644 | } else { | |
1645 | if (up->wakeups_enabled) { | |
e5b57c03 | 1646 | serial_omap_enable_wakeup(up, false); |
62f3ec5f G |
1647 | up->wakeups_enabled = false; |
1648 | } | |
1649 | } | |
1650 | ||
2fd14964 G |
1651 | up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
1652 | schedule_work(&up->qos_work); | |
1653 | ||
b612633b G |
1654 | return 0; |
1655 | } | |
1656 | ||
fcdca757 G |
1657 | static int serial_omap_runtime_resume(struct device *dev) |
1658 | { | |
9f9ac1e8 G |
1659 | struct uart_omap_port *up = dev_get_drvdata(dev); |
1660 | ||
39aee51d | 1661 | int loss_cnt = serial_omap_get_context_loss_count(up); |
ec3bebc6 | 1662 | |
39aee51d | 1663 | if (loss_cnt < 0) { |
a630fbfb | 1664 | dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n", |
39aee51d | 1665 | loss_cnt); |
ac57e7f3 | 1666 | serial_omap_restore_context(up); |
39aee51d S |
1667 | } else if (up->context_loss_cnt != loss_cnt) { |
1668 | serial_omap_restore_context(up); | |
1669 | } | |
ac57e7f3 SP |
1670 | up->latency = up->calc_latency; |
1671 | schedule_work(&up->qos_work); | |
9f9ac1e8 | 1672 | |
b612633b G |
1673 | return 0; |
1674 | } | |
fcdca757 G |
1675 | #endif |
1676 | ||
1677 | static const struct dev_pm_ops serial_omap_dev_pm_ops = { | |
1678 | SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) | |
1679 | SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, | |
1680 | serial_omap_runtime_resume, NULL) | |
ddd85e22 SP |
1681 | .prepare = serial_omap_prepare, |
1682 | .complete = serial_omap_complete, | |
fcdca757 G |
1683 | }; |
1684 | ||
d92b0dfc RN |
1685 | #if defined(CONFIG_OF) |
1686 | static const struct of_device_id omap_serial_of_match[] = { | |
1687 | { .compatible = "ti,omap2-uart" }, | |
1688 | { .compatible = "ti,omap3-uart" }, | |
1689 | { .compatible = "ti,omap4-uart" }, | |
1690 | {}, | |
1691 | }; | |
1692 | MODULE_DEVICE_TABLE(of, omap_serial_of_match); | |
1693 | #endif | |
b612633b G |
1694 | |
1695 | static struct platform_driver serial_omap_driver = { | |
1696 | .probe = serial_omap_probe, | |
2d47b716 | 1697 | .remove = serial_omap_remove, |
b612633b G |
1698 | .driver = { |
1699 | .name = DRIVER_NAME, | |
fcdca757 | 1700 | .pm = &serial_omap_dev_pm_ops, |
d92b0dfc | 1701 | .of_match_table = of_match_ptr(omap_serial_of_match), |
b612633b G |
1702 | }, |
1703 | }; | |
1704 | ||
1705 | static int __init serial_omap_init(void) | |
1706 | { | |
1707 | int ret; | |
1708 | ||
1709 | ret = uart_register_driver(&serial_omap_reg); | |
1710 | if (ret != 0) | |
1711 | return ret; | |
1712 | ret = platform_driver_register(&serial_omap_driver); | |
1713 | if (ret != 0) | |
1714 | uart_unregister_driver(&serial_omap_reg); | |
1715 | return ret; | |
1716 | } | |
1717 | ||
1718 | static void __exit serial_omap_exit(void) | |
1719 | { | |
1720 | platform_driver_unregister(&serial_omap_driver); | |
1721 | uart_unregister_driver(&serial_omap_reg); | |
1722 | } | |
1723 | ||
1724 | module_init(serial_omap_init); | |
1725 | module_exit(serial_omap_exit); | |
1726 | ||
1727 | MODULE_DESCRIPTION("OMAP High Speed UART driver"); | |
1728 | MODULE_LICENSE("GPL"); | |
1729 | MODULE_AUTHOR("Texas Instruments Inc"); |