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tty: serial: omap: switch over to platform_get_resource
[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / omap-serial.c
CommitLineData
b612633b
G		 1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
25985edc 16 * Note: This driver is made separate from 8250 driver as we cannot
b612633b
G		 17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
364a6ece
TW		 23#if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
b612633b
G		 27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/serial_reg.h>
31#include <linux/delay.h>
32#include <linux/slab.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
d21e4005 35#include <linux/platform_device.h>
b612633b 36#include <linux/io.h>
b612633b
G		 37#include <linux/clk.h>
38#include <linux/serial_core.h>
39#include <linux/irq.h>
fcdca757 40#include <linux/pm_runtime.h>
d92b0dfc 41#include <linux/of.h>
2a0b965c 42#include <linux/of_irq.h>
9574f36f 43#include <linux/gpio.h>
4a0ac0f5 44#include <linux/of_gpio.h>
d9ba5737 45#include <linux/platform_data/serial-omap.h>
b612633b 46
4a0ac0f5
MJ		 47#include <dt-bindings/gpio/gpio.h>
48
f91b55ab
RK		 49#define OMAP_MAX_HSUART_PORTS 6
50
7c77c8de
G		 51#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
52
53#define OMAP_UART_REV_42 0x0402
54#define OMAP_UART_REV_46 0x0406
55#define OMAP_UART_REV_52 0x0502
56#define OMAP_UART_REV_63 0x0603
57
f64ffda6
G		 58#define OMAP_UART_TX_WAKEUP_EN BIT(7)
59
60/* Feature flags */
61#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
62
f91b55ab
RK		 63#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
64#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
65
8fe789dc
RN		 66#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
67
0ba5f668
PW		 68/* SCR register bitmasks */
69#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
1776fd05 70#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
f91b55ab 71#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
0ba5f668
PW		 72
73/* FCR register bitmasks */
0ba5f668 74#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
6721ab7f 75#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
0ba5f668 76
7c77c8de
G		 77/* MVR register bitmasks */
78#define OMAP_UART_MVR_SCHEME_SHIFT 30
79
80#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
81#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
82#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
83
84#define OMAP_UART_MVR_MAJ_MASK 0x700
85#define OMAP_UART_MVR_MAJ_SHIFT 8
86#define OMAP_UART_MVR_MIN_MASK 0x3f
87
f91b55ab
RK		 88#define OMAP_UART_DMA_CH_FREE -1
89
90#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
91#define OMAP_MODE13X_SPEED 230400
92
93/* WER = 0x7F
94 * Enable module level wakeup in WER reg
95 */
96#define OMAP_UART_WER_MOD_WKUP 0X7F
97
98/* Enable XON/XOFF flow control on output */
3af08bd7 99#define OMAP_UART_SW_TX 0x08
f91b55ab
RK		 100
101/* Enable XON/XOFF flow control on input */
3af08bd7 102#define OMAP_UART_SW_RX 0x02
f91b55ab
RK		 103
104#define OMAP_UART_SW_CLR 0xF0
105
106#define OMAP_UART_TCR_TRIG 0x0F
107
108struct uart_omap_dma {
109 u8 uart_dma_tx;
110 u8 uart_dma_rx;
111 int rx_dma_channel;
112 int tx_dma_channel;
113 dma_addr_t rx_buf_dma_phys;
114 dma_addr_t tx_buf_dma_phys;
115 unsigned int uart_base;
116 /*
117 * Buffer for rx dma.It is not required for tx because the buffer
118 * comes from port structure.
119 */
120 unsigned char *rx_buf;
121 unsigned int prev_rx_dma_pos;
122 int tx_buf_size;
123 int tx_dma_used;
124 int rx_dma_used;
125 spinlock_t tx_lock;
126 spinlock_t rx_lock;
127 /* timer to poll activity on rx dma */
128 struct timer_list rx_timer;
129 unsigned int rx_buf_size;
130 unsigned int rx_poll_rate;
131 unsigned int rx_timeout;
132};
133
d37c6ceb
FB		 134struct uart_omap_port {
135 struct uart_port port;
136 struct uart_omap_dma uart_dma;
137 struct device *dev;
2a0b965c 138 int wakeirq;
d37c6ceb
FB		 139
140 unsigned char ier;
141 unsigned char lcr;
142 unsigned char mcr;
143 unsigned char fcr;
144 unsigned char efr;
145 unsigned char dll;
146 unsigned char dlh;
147 unsigned char mdr1;
148 unsigned char scr;
f64ffda6 149 unsigned char wer;
d37c6ceb
FB		 150
151 int use_dma;
152 /*
153 * Some bits in registers are cleared on a read, so they must
154 * be saved whenever the register is read but the bits will not
155 * be immediately processed.
156 */
157 unsigned int lsr_break_flag;
158 unsigned char msr_saved_flags;
159 char name[20];
160 unsigned long port_activity;
39aee51d 161 int context_loss_cnt;
d37c6ceb
FB		 162 u32 errata;
163 u8 wakeups_enabled;
f64ffda6 164 u32 features;
d37c6ceb 165
e36851d0
FB		 166 int DTR_gpio;
167 int DTR_inverted;
168 int DTR_active;
169
4a0ac0f5
MJ		 170 struct serial_rs485 rs485;
171 int rts_gpio;
172
d37c6ceb
FB		 173 struct pm_qos_request pm_qos_request;
174 u32 latency;
175 u32 calc_latency;
176 struct work_struct qos_work;
ddd85e22 177 bool is_suspending;
d37c6ceb
FB		 178};
179
e5f9bf72 180#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
d37c6ceb 181
b612633b
G		 182static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
183
184/* Forward declaration of functions */
94734749 185static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
b612633b 186
2fd14964 187static struct workqueue_struct *serial_omap_uart_wq;
b612633b
G		 188
189static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
190{
191 offset <<= up->port.regshift;
192 return readw(up->port.membase + offset);
193}
194
195static inline void serial_out(struct uart_omap_port *up, int offset, int value)
196{
197 offset <<= up->port.regshift;
198 writew(value, up->port.membase + offset);
199}
200
201static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
202{
203 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
204 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
205 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
206 serial_out(up, UART_FCR, 0);
207}
208
e5b57c03
FB		 209static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
210{
574de559 211 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
e5b57c03 212
ce2f08de 213 if (!pdata || !pdata->get_context_loss_count)
a630fbfb 214 return -EINVAL;
e5b57c03 215
d8ee4ea6 216 return pdata->get_context_loss_count(up->dev);
e5b57c03
FB		 217}
218
2a0b965c
TL		 219static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
220 bool enable)
221{
222 if (!up->wakeirq)
223 return;
224
225 if (enable)
226 enable_irq(up->wakeirq);
227 else
d758c9c1 228 disable_irq_nosync(up->wakeirq);
2a0b965c
TL		 229}
230
e5b57c03
FB		 231static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
232{
574de559 233 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
e5b57c03 234
d758c9c1
TL		 235 if (enable == up->wakeups_enabled)
236 return;
237
2a0b965c 238 serial_omap_enable_wakeirq(up, enable);
d758c9c1
TL		 239 up->wakeups_enabled = enable;
240
ce2f08de
FB		 241 if (!pdata || !pdata->enable_wakeup)
242 return;
243
244 pdata->enable_wakeup(up->dev, enable);
e5b57c03
FB		 245}
246
5fe21236
AP		 247/*
248 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
249 * @port: uart port info
250 * @baud: baudrate for which mode needs to be determined
251 *
252 * Returns true if baud rate is MODE16X and false if MODE13X
253 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
254 * and Error Rates" determines modes not for all common baud rates.
255 * E.g. for 1000000 baud rate mode must be 16x, but according to that
256 * table it's determined as 13x.
257 */
258static bool
259serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
260{
261 unsigned int n13 = port->uartclk / (13 * baud);
262 unsigned int n16 = port->uartclk / (16 * baud);
263 int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
264 int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
e5f9bf72 265 if (baudAbsDiff13 < 0)
5fe21236 266 baudAbsDiff13 = -baudAbsDiff13;
e5f9bf72 267 if (baudAbsDiff16 < 0)
5fe21236
AP		 268 baudAbsDiff16 = -baudAbsDiff16;
269
18d8519d 270 return (baudAbsDiff13 >= baudAbsDiff16);
5fe21236
AP		 271}
272
b612633b
G		 273/*
274 * serial_omap_get_divisor - calculate divisor value
275 * @port: uart port info
276 * @baud: baudrate for which divisor needs to be calculated.
b612633b
G		 277 */
278static unsigned int
279serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
280{
4250b5d9 281 unsigned int mode;
b612633b 282
5fe21236 283 if (!serial_omap_baud_is_mode16(port, baud))
4250b5d9 284 mode = 13;
b612633b 285 else
4250b5d9
AP		 286 mode = 16;
287 return port->uartclk/(mode * baud);
b612633b
G		 288}
289
b612633b
G		 290static void serial_omap_enable_ms(struct uart_port *port)
291{
c990f351 292 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 293
ba77433d 294 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
fcdca757 295
d8ee4ea6 296 pm_runtime_get_sync(up->dev);
b612633b
G		 297 up->ier |= UART_IER_MSI;
298 serial_out(up, UART_IER, up->ier);
660ac5f4
FB		 299 pm_runtime_mark_last_busy(up->dev);
300 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 301}
302
303static void serial_omap_stop_tx(struct uart_port *port)
304{
c990f351 305 struct uart_omap_port *up = to_uart_omap_port(port);
4a0ac0f5 306 int res;
b612633b 307
d8ee4ea6 308 pm_runtime_get_sync(up->dev);
4a0ac0f5 309
018e7448 310 /* Handle RS-485 */
4a0ac0f5 311 if (up->rs485.flags & SER_RS485_ENABLED) {
018e7448
PP		 312 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
313 /* THR interrupt is fired when both TX FIFO and TX
314 * shift register are empty. This means there's nothing
315 * left to transmit now, so make sure the THR interrupt
316 * is fired when TX FIFO is below the trigger level,
317 * disable THR interrupts and toggle the RS-485 GPIO
318 * data direction pin if needed.
319 */
320 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
321 serial_out(up, UART_OMAP_SCR, up->scr);
4a0ac0f5
MJ		 322 res = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
323 if (gpio_get_value(up->rts_gpio) != res) {
e5f9bf72 324 if (up->rs485.delay_rts_after_send > 0)
4a0ac0f5 325 mdelay(up->rs485.delay_rts_after_send);
4a0ac0f5
MJ		 326 gpio_set_value(up->rts_gpio, res);
327 }
018e7448
PP		 328 } else {
329 /* We're asked to stop, but there's still stuff in the
330 * UART FIFO, so make sure the THR interrupt is fired
331 * when both TX FIFO and TX shift register are empty.
332 * The next THR interrupt (if no transmission is started
333 * in the meantime) will indicate the end of a
334 * transmission. Therefore we _don't_ disable THR
335 * interrupts in this situation.
336 */
337 up->scr |= OMAP_UART_SCR_TX_EMPTY;
338 serial_out(up, UART_OMAP_SCR, up->scr);
339 return;
4a0ac0f5
MJ		 340 }
341 }
342
b612633b
G		 343 if (up->ier & UART_IER_THRI) {
344 up->ier &= ~UART_IER_THRI;
345 serial_out(up, UART_IER, up->ier);
346 }
fcdca757 347
4a0ac0f5
MJ		 348 if ((up->rs485.flags & SER_RS485_ENABLED) &&
349 !(up->rs485.flags & SER_RS485_RX_DURING_TX)) {
3a13884a
DL		 350 /*
351 * Empty the RX FIFO, we are not interested in anything
352 * received during the half-duplex transmission.
353 */
354 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
355 /* Re-enable RX interrupts */
cab53dc9
DL		 356 up->ier |= UART_IER_RLSI | UART_IER_RDI;
357 up->port.read_status_mask |= UART_LSR_DR;
4a0ac0f5
MJ		 358 serial_out(up, UART_IER, up->ier);
359 }
360
d8ee4ea6
FB		 361 pm_runtime_mark_last_busy(up->dev);
362 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 363}
364
365static void serial_omap_stop_rx(struct uart_port *port)
366{
c990f351 367 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 368
d8ee4ea6 369 pm_runtime_get_sync(up->dev);
cab53dc9 370 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
b612633b
G		 371 up->port.read_status_mask &= ~UART_LSR_DR;
372 serial_out(up, UART_IER, up->ier);
d8ee4ea6
FB		 373 pm_runtime_mark_last_busy(up->dev);
374 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 375}
376
bf63a086 377static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
b612633b
G		 378{
379 struct circ_buf *xmit = &up->port.state->xmit;
380 int count;
381
382 if (up->port.x_char) {
383 serial_out(up, UART_TX, up->port.x_char);
384 up->port.icount.tx++;
385 up->port.x_char = 0;
386 return;
387 }
388 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
389 serial_omap_stop_tx(&up->port);
390 return;
391 }
355fe568 392 count = up->port.fifosize / 4;
b612633b
G		 393 do {
394 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
395 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
396 up->port.icount.tx++;
397 if (uart_circ_empty(xmit))
398 break;
399 } while (--count > 0);
400
6bf78967 401 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
b612633b
G		 402 uart_write_wakeup(&up->port);
403
404 if (uart_circ_empty(xmit))
405 serial_omap_stop_tx(&up->port);
406}
407
408static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
409{
410 if (!(up->ier & UART_IER_THRI)) {
411 up->ier |= UART_IER_THRI;
412 serial_out(up, UART_IER, up->ier);
413 }
414}
415
416static void serial_omap_start_tx(struct uart_port *port)
417{
c990f351 418 struct uart_omap_port *up = to_uart_omap_port(port);
4a0ac0f5 419 int res;
b612633b 420
49457430 421 pm_runtime_get_sync(up->dev);
4a0ac0f5 422
018e7448 423 /* Handle RS-485 */
4a0ac0f5 424 if (up->rs485.flags & SER_RS485_ENABLED) {
018e7448
PP		 425 /* Fire THR interrupts when FIFO is below trigger level */
426 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
427 serial_out(up, UART_OMAP_SCR, up->scr);
428
4a0ac0f5
MJ		 429 /* if rts not already enabled */
430 res = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
431 if (gpio_get_value(up->rts_gpio) != res) {
432 gpio_set_value(up->rts_gpio, res);
e5f9bf72 433 if (up->rs485.delay_rts_before_send > 0)
4a0ac0f5 434 mdelay(up->rs485.delay_rts_before_send);
4a0ac0f5
MJ		 435 }
436 }
437
438 if ((up->rs485.flags & SER_RS485_ENABLED) &&
439 !(up->rs485.flags & SER_RS485_RX_DURING_TX))
440 serial_omap_stop_rx(port);
441
49457430 442 serial_omap_enable_ier_thri(up);
49457430
FB		 443 pm_runtime_mark_last_busy(up->dev);
444 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 445}
446
3af08bd7
RK		 447static void serial_omap_throttle(struct uart_port *port)
448{
449 struct uart_omap_port *up = to_uart_omap_port(port);
450 unsigned long flags;
451
452 pm_runtime_get_sync(up->dev);
453 spin_lock_irqsave(&up->port.lock, flags);
454 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
455 serial_out(up, UART_IER, up->ier);
456 spin_unlock_irqrestore(&up->port.lock, flags);
457 pm_runtime_mark_last_busy(up->dev);
458 pm_runtime_put_autosuspend(up->dev);
459}
460
461static void serial_omap_unthrottle(struct uart_port *port)
462{
463 struct uart_omap_port *up = to_uart_omap_port(port);
464 unsigned long flags;
465
466 pm_runtime_get_sync(up->dev);
467 spin_lock_irqsave(&up->port.lock, flags);
468 up->ier |= UART_IER_RLSI | UART_IER_RDI;
469 serial_out(up, UART_IER, up->ier);
470 spin_unlock_irqrestore(&up->port.lock, flags);
471 pm_runtime_mark_last_busy(up->dev);
472 pm_runtime_put_autosuspend(up->dev);
473}
474
b612633b
G		 475static unsigned int check_modem_status(struct uart_omap_port *up)
476{
477 unsigned int status;
478
479 status = serial_in(up, UART_MSR);
480 status |= up->msr_saved_flags;
481 up->msr_saved_flags = 0;
482 if ((status & UART_MSR_ANY_DELTA) == 0)
483 return status;
484
485 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
486 up->port.state != NULL) {
487 if (status & UART_MSR_TERI)
488 up->port.icount.rng++;
489 if (status & UART_MSR_DDSR)
490 up->port.icount.dsr++;
491 if (status & UART_MSR_DDCD)
492 uart_handle_dcd_change
493 (&up->port, status & UART_MSR_DCD);
494 if (status & UART_MSR_DCTS)
495 uart_handle_cts_change
496 (&up->port, status & UART_MSR_CTS);
497 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
498 }
499
500 return status;
501}
502
72256cbd
FB		 503static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
504{
505 unsigned int flag;
9a12fcf8
S		 506 unsigned char ch = 0;
507
508 if (likely(lsr & UART_LSR_DR))
509 ch = serial_in(up, UART_RX);
72256cbd
FB		 510
511 up->port.icount.rx++;
512 flag = TTY_NORMAL;
513
514 if (lsr & UART_LSR_BI) {
515 flag = TTY_BREAK;
516 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
517 up->port.icount.brk++;
518 /*
519 * We do the SysRQ and SAK checking
520 * here because otherwise the break
521 * may get masked by ignore_status_mask
522 * or read_status_mask.
523 */
524 if (uart_handle_break(&up->port))
525 return;
526
527 }
528
529 if (lsr & UART_LSR_PE) {
530 flag = TTY_PARITY;
531 up->port.icount.parity++;
532 }
533
534 if (lsr & UART_LSR_FE) {
535 flag = TTY_FRAME;
536 up->port.icount.frame++;
537 }
538
539 if (lsr & UART_LSR_OE)
540 up->port.icount.overrun++;
541
542#ifdef CONFIG_SERIAL_OMAP_CONSOLE
543 if (up->port.line == up->port.cons->index) {
544 /* Recover the break flag from console xmit */
545 lsr |= up->lsr_break_flag;
546 }
547#endif
548 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
549}
550
551static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
552{
553 unsigned char ch = 0;
554 unsigned int flag;
555
556 if (!(lsr & UART_LSR_DR))
557 return;
558
559 ch = serial_in(up, UART_RX);
560 flag = TTY_NORMAL;
561 up->port.icount.rx++;
562
563 if (uart_handle_sysrq_char(&up->port, ch))
564 return;
565
566 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
567}
568
b612633b
G		 569/**
570 * serial_omap_irq() - This handles the interrupt from one port
571 * @irq: uart port irq number
572 * @dev_id: uart port info
573 */
52c5513d 574static irqreturn_t serial_omap_irq(int irq, void *dev_id)
b612633b
G		 575{
576 struct uart_omap_port *up = dev_id;
577 unsigned int iir, lsr;
81b75aef 578 unsigned int type;
7b013e44 579 irqreturn_t ret = IRQ_NONE;
72256cbd 580 int max_count = 256;
b612633b 581
6c3a30c7 582 spin_lock(&up->port.lock);
d8ee4ea6 583 pm_runtime_get_sync(up->dev);
72256cbd
FB		 584
585 do {
81b75aef 586 iir = serial_in(up, UART_IIR);
72256cbd
FB		 587 if (iir & UART_IIR_NO_INT)
588 break;
589
7b013e44 590 ret = IRQ_HANDLED;
72256cbd
FB		 591 lsr = serial_in(up, UART_LSR);
592
593 /* extract IRQ type from IIR register */
594 type = iir & 0x3e;
595
596 switch (type) {
597 case UART_IIR_MSI:
598 check_modem_status(up);
599 break;
600 case UART_IIR_THRI:
bf63a086 601 transmit_chars(up, lsr);
72256cbd
FB		 602 break;
603 case UART_IIR_RX_TIMEOUT:
604 /* FALLTHROUGH */
605 case UART_IIR_RDI:
606 serial_omap_rdi(up, lsr);
607 break;
608 case UART_IIR_RLSI:
609 serial_omap_rlsi(up, lsr);
610 break;
611 case UART_IIR_CTS_RTS_DSR:
612 /* simply try again */
613 break;
614 case UART_IIR_XOFF:
615 /* FALLTHROUGH */
616 default:
617 break;
618 }
619 } while (!(iir & UART_IIR_NO_INT) && max_count--);
b612633b 620
6c3a30c7 621 spin_unlock(&up->port.lock);
72256cbd 622
2e124b4a 623 tty_flip_buffer_push(&up->port.state->port);
72256cbd 624
d8ee4ea6
FB		 625 pm_runtime_mark_last_busy(up->dev);
626 pm_runtime_put_autosuspend(up->dev);
b612633b 627 up->port_activity = jiffies;
81b75aef 628
7b013e44 629 return ret;
b612633b
G		 630}
631
632static unsigned int serial_omap_tx_empty(struct uart_port *port)
633{
c990f351 634 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 635 unsigned long flags = 0;
636 unsigned int ret = 0;
637
d8ee4ea6 638 pm_runtime_get_sync(up->dev);
ba77433d 639 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
b612633b
G		 640 spin_lock_irqsave(&up->port.lock, flags);
641 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
642 spin_unlock_irqrestore(&up->port.lock, flags);
660ac5f4
FB		 643 pm_runtime_mark_last_busy(up->dev);
644 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 645 return ret;
646}
647
648static unsigned int serial_omap_get_mctrl(struct uart_port *port)
649{
c990f351 650 struct uart_omap_port *up = to_uart_omap_port(port);
514f31d1 651 unsigned int status;
b612633b
G		 652 unsigned int ret = 0;
653
d8ee4ea6 654 pm_runtime_get_sync(up->dev);
b612633b 655 status = check_modem_status(up);
660ac5f4
FB		 656 pm_runtime_mark_last_busy(up->dev);
657 pm_runtime_put_autosuspend(up->dev);
fcdca757 658
ba77433d 659 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
b612633b
G		 660
661 if (status & UART_MSR_DCD)
662 ret |= TIOCM_CAR;
663 if (status & UART_MSR_RI)
664 ret |= TIOCM_RNG;
665 if (status & UART_MSR_DSR)
666 ret |= TIOCM_DSR;
667 if (status & UART_MSR_CTS)
668 ret |= TIOCM_CTS;
669 return ret;
670}
671
672static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
673{
c990f351 674 struct uart_omap_port *up = to_uart_omap_port(port);
9363f8fa 675 unsigned char mcr = 0, old_mcr;
b612633b 676
ba77433d 677 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
b612633b
G		 678 if (mctrl & TIOCM_RTS)
679 mcr |= UART_MCR_RTS;
680 if (mctrl & TIOCM_DTR)
681 mcr |= UART_MCR_DTR;
682 if (mctrl & TIOCM_OUT1)
683 mcr |= UART_MCR_OUT1;
684 if (mctrl & TIOCM_OUT2)
685 mcr |= UART_MCR_OUT2;
686 if (mctrl & TIOCM_LOOP)
687 mcr |= UART_MCR_LOOP;
688
d8ee4ea6 689 pm_runtime_get_sync(up->dev);
9363f8fa
RK		 690 old_mcr = serial_in(up, UART_MCR);
691 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
692 UART_MCR_DTR | UART_MCR_RTS);
693 up->mcr = old_mcr | mcr;
c538d20c 694 serial_out(up, UART_MCR, up->mcr);
660ac5f4
FB		 695 pm_runtime_mark_last_busy(up->dev);
696 pm_runtime_put_autosuspend(up->dev);
9574f36f
N		 697
698 if (gpio_is_valid(up->DTR_gpio) &&
699 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
700 up->DTR_active = !up->DTR_active;
701 if (gpio_cansleep(up->DTR_gpio))
702 schedule_work(&up->qos_work);
703 else
704 gpio_set_value(up->DTR_gpio,
705 up->DTR_active != up->DTR_inverted);
706 }
b612633b
G		 707}
708
709static void serial_omap_break_ctl(struct uart_port *port, int break_state)
710{
c990f351 711 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 712 unsigned long flags = 0;
713
ba77433d 714 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
d8ee4ea6 715 pm_runtime_get_sync(up->dev);
b612633b
G		 716 spin_lock_irqsave(&up->port.lock, flags);
717 if (break_state == -1)
718 up->lcr |= UART_LCR_SBC;
719 else
720 up->lcr &= ~UART_LCR_SBC;
721 serial_out(up, UART_LCR, up->lcr);
722 spin_unlock_irqrestore(&up->port.lock, flags);
660ac5f4
FB		 723 pm_runtime_mark_last_busy(up->dev);
724 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 725}
726
727static int serial_omap_startup(struct uart_port *port)
728{
c990f351 729 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 730 unsigned long flags = 0;
731 int retval;
732
733 /*
734 * Allocate the IRQ
735 */
736 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
737 up->name, up);
738 if (retval)
739 return retval;
740
2a0b965c
TL		 741 /* Optional wake-up IRQ */
742 if (up->wakeirq) {
743 retval = request_irq(up->wakeirq, serial_omap_irq,
744 up->port.irqflags, up->name, up);
745 if (retval) {
746 free_irq(up->port.irq, up);
747 return retval;
748 }
749 disable_irq(up->wakeirq);
2a0b965c
TL		 750 }
751
ba77433d 752 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
b612633b 753
d8ee4ea6 754 pm_runtime_get_sync(up->dev);
b612633b
G		 755 /*
756 * Clear the FIFO buffers and disable them.
757 * (they will be reenabled in set_termios())
758 */
759 serial_omap_clear_fifos(up);
760 /* For Hardware flow control */
761 serial_out(up, UART_MCR, UART_MCR_RTS);
762
763 /*
764 * Clear the interrupt registers.
765 */
766 (void) serial_in(up, UART_LSR);
767 if (serial_in(up, UART_LSR) & UART_LSR_DR)
768 (void) serial_in(up, UART_RX);
769 (void) serial_in(up, UART_IIR);
770 (void) serial_in(up, UART_MSR);
771
772 /*
773 * Now, initialize the UART
774 */
775 serial_out(up, UART_LCR, UART_LCR_WLEN8);
776 spin_lock_irqsave(&up->port.lock, flags);
777 /*
778 * Most PC uarts need OUT2 raised to enable interrupts.
779 */
780 up->port.mctrl |= TIOCM_OUT2;
781 serial_omap_set_mctrl(&up->port, up->port.mctrl);
782 spin_unlock_irqrestore(&up->port.lock, flags);
783
784 up->msr_saved_flags = 0;
b612633b
G		 785 /*
786 * Finally, enable interrupts. Note: Modem status interrupts
787 * are set via set_termios(), which will be occurring imminently
788 * anyway, so we don't enable them here.
789 */
790 up->ier = UART_IER_RLSI | UART_IER_RDI;
791 serial_out(up, UART_IER, up->ier);
792
78841462 793 /* Enable module level wake up */
f64ffda6
G		 794 up->wer = OMAP_UART_WER_MOD_WKUP;
795 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
796 up->wer |= OMAP_UART_TX_WAKEUP_EN;
797
798 serial_out(up, UART_OMAP_WER, up->wer);
78841462 799
d8ee4ea6
FB		 800 pm_runtime_mark_last_busy(up->dev);
801 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 802 up->port_activity = jiffies;
803 return 0;
804}
805
806static void serial_omap_shutdown(struct uart_port *port)
807{
c990f351 808 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 809 unsigned long flags = 0;
810
ba77433d 811 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
fcdca757 812
d8ee4ea6 813 pm_runtime_get_sync(up->dev);
b612633b
G		 814 /*
815 * Disable interrupts from this port
816 */
817 up->ier = 0;
818 serial_out(up, UART_IER, 0);
819
820 spin_lock_irqsave(&up->port.lock, flags);
821 up->port.mctrl &= ~TIOCM_OUT2;
822 serial_omap_set_mctrl(&up->port, up->port.mctrl);
823 spin_unlock_irqrestore(&up->port.lock, flags);
824
825 /*
826 * Disable break condition and FIFOs
827 */
828 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
829 serial_omap_clear_fifos(up);
830
831 /*
832 * Read data port to reset things, and then free the irq
833 */
834 if (serial_in(up, UART_LSR) & UART_LSR_DR)
835 (void) serial_in(up, UART_RX);
fcdca757 836
660ac5f4
FB		 837 pm_runtime_mark_last_busy(up->dev);
838 pm_runtime_put_autosuspend(up->dev);
b612633b 839 free_irq(up->port.irq, up);
2a0b965c
TL		 840 if (up->wakeirq)
841 free_irq(up->wakeirq, up);
b612633b
G		 842}
843
2fd14964
G		 844static void serial_omap_uart_qos_work(struct work_struct *work)
845{
846 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
847 qos_work);
848
849 pm_qos_update_request(&up->pm_qos_request, up->latency);
9574f36f
N		 850 if (gpio_is_valid(up->DTR_gpio))
851 gpio_set_value_cansleep(up->DTR_gpio,
852 up->DTR_active != up->DTR_inverted);
2fd14964
G		 853}
854
b612633b
G		 855static void
856serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
857 struct ktermios *old)
858{
c990f351 859 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 860 unsigned char cval = 0;
b612633b
G		 861 unsigned long flags = 0;
862 unsigned int baud, quot;
863
864 switch (termios->c_cflag & CSIZE) {
865 case CS5:
866 cval = UART_LCR_WLEN5;
867 break;
868 case CS6:
869 cval = UART_LCR_WLEN6;
870 break;
871 case CS7:
872 cval = UART_LCR_WLEN7;
873 break;
874 default:
875 case CS8:
876 cval = UART_LCR_WLEN8;
877 break;
878 }
879
880 if (termios->c_cflag & CSTOPB)
881 cval |= UART_LCR_STOP;
882 if (termios->c_cflag & PARENB)
883 cval |= UART_LCR_PARITY;
884 if (!(termios->c_cflag & PARODD))
885 cval |= UART_LCR_EPAR;
fdbc7353
EBS		 886 if (termios->c_cflag & CMSPAR)
887 cval |= UART_LCR_SPAR;
b612633b
G		 888
889 /*
890 * Ask the core to calculate the divisor for us.
891 */
892
893 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
894 quot = serial_omap_get_divisor(port, baud);
895
2fd14964 896 /* calculate wakeup latency constraint */
19723452 897 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
2fd14964
G		 898 up->latency = up->calc_latency;
899 schedule_work(&up->qos_work);
900
c538d20c
G		 901 up->dll = quot & 0xff;
902 up->dlh = quot >> 8;
903 up->mdr1 = UART_OMAP_MDR1_DISABLE;
904
b612633b
G		 905 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
906 UART_FCR_ENABLE_FIFO;
b612633b
G		 907
908 /*
909 * Ok, we're now changing the port state. Do it with
910 * interrupts disabled.
911 */
d8ee4ea6 912 pm_runtime_get_sync(up->dev);
b612633b
G		 913 spin_lock_irqsave(&up->port.lock, flags);
914
915 /*
916 * Update the per-port timeout.
917 */
918 uart_update_timeout(port, termios->c_cflag, baud);
919
920 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
921 if (termios->c_iflag & INPCK)
922 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
923 if (termios->c_iflag & (BRKINT | PARMRK))
924 up->port.read_status_mask |= UART_LSR_BI;
925
926 /*
927 * Characters to ignore
928 */
929 up->port.ignore_status_mask = 0;
930 if (termios->c_iflag & IGNPAR)
931 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
932 if (termios->c_iflag & IGNBRK) {
933 up->port.ignore_status_mask |= UART_LSR_BI;
934 /*
935 * If we're ignoring parity and break indicators,
936 * ignore overruns too (for real raw support).
937 */
938 if (termios->c_iflag & IGNPAR)
939 up->port.ignore_status_mask |= UART_LSR_OE;
940 }
941
942 /*
943 * ignore all characters if CREAD is not set
944 */
945 if ((termios->c_cflag & CREAD) == 0)
946 up->port.ignore_status_mask |= UART_LSR_DR;
947
948 /*
949 * Modem status interrupts
950 */
951 up->ier &= ~UART_IER_MSI;
952 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
953 up->ier |= UART_IER_MSI;
954 serial_out(up, UART_IER, up->ier);
955 serial_out(up, UART_LCR, cval); /* reset DLAB */
c538d20c 956 up->lcr = cval;
1776fd05 957 up->scr = 0;
b612633b
G		 958
959 /* FIFOs and DMA Settings */
960
961 /* FCR can be changed only when the
962 * baud clock is not running
963 * DLL_REG and DLH_REG set to 0.
964 */
662b083a 965 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b
G		 966 serial_out(up, UART_DLL, 0);
967 serial_out(up, UART_DLM, 0);
968 serial_out(up, UART_LCR, 0);
969
662b083a 970 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b 971
08bd4903 972 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
d864c03b 973 up->efr &= ~UART_EFR_SCD;
b612633b
G		 974 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
975
662b083a 976 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
08bd4903 977 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
b612633b
G		 978 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
979 /* FIFO ENABLE, DMA MODE */
0ba5f668 980
1f663966
AP		 981 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
982 /*
983 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
984 * sets Enables the granularity of 1 for TRIGGER RX
985 * level. Along with setting RX FIFO trigger level
986 * to 1 (as noted below, 16 characters) and TLR[3:0]
987 * to zero this will result RX FIFO threshold level
988 * to 1 character, instead of 16 as noted in comment
989 * below.
990 */
991
6721ab7f 992 /* Set receive FIFO threshold to 16 characters and
018e7448 993 * transmit FIFO threshold to 32 spaces
6721ab7f 994 */
49457430 995 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
6721ab7f
FB		 996 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
997 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
998 UART_FCR_ENABLE_FIFO;
b612633b 999
0ba5f668
PW		 1000 serial_out(up, UART_FCR, up->fcr);
1001 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1002
c538d20c
G		 1003 serial_out(up, UART_OMAP_SCR, up->scr);
1004
08bd4903 1005 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
662b083a 1006 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b 1007 serial_out(up, UART_MCR, up->mcr);
08bd4903
RK		 1008 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1009 serial_out(up, UART_EFR, up->efr);
1010 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b
G		 1011
1012 /* Protocol, Baud Rate, and Interrupt Settings */
1013
94734749
G		 1014 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1015 serial_omap_mdr1_errataset(up, up->mdr1);
1016 else
1017 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1018
662b083a 1019 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 1020 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1021
1022 serial_out(up, UART_LCR, 0);
1023 serial_out(up, UART_IER, 0);
662b083a 1024 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b 1025
c538d20c
G		 1026 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1027 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
b612633b
G		 1028
1029 serial_out(up, UART_LCR, 0);
1030 serial_out(up, UART_IER, up->ier);
662b083a 1031 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 1032
1033 serial_out(up, UART_EFR, up->efr);
1034 serial_out(up, UART_LCR, cval);
1035
5fe21236 1036 if (!serial_omap_baud_is_mode16(port, baud))
c538d20c 1037 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
b612633b 1038 else
c538d20c
G		 1039 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1040
94734749
G		 1041 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1042 serial_omap_mdr1_errataset(up, up->mdr1);
1043 else
1044 serial_out(up, UART_OMAP_MDR1, up->mdr1);
b612633b 1045
c533e51b 1046 /* Configure flow control */
c7d059ca 1047 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
c533e51b
RK		 1048
1049 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1050 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1051 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1052
1053 /* Enable access to TCR/TLR */
c7d059ca
RK		 1054 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1055 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1056 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
b612633b 1057
c7d059ca 1058 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
b612633b 1059
c7d059ca 1060 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
08bd4903
RK		 1061 /* Enable AUTORTS and AUTOCTS */
1062 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1063
1fe8aa88
RK		 1064 /* Ensure MCR RTS is asserted */
1065 up->mcr |= UART_MCR_RTS;
0d5b1663
RK		 1066 } else {
1067 /* Disable AUTORTS and AUTOCTS */
1068 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
b612633b 1069 }
b612633b 1070
01d70bb3 1071 if (up->port.flags & UPF_SOFT_FLOW) {
01d70bb3
RK		 1072 /* clear SW control mode bits */
1073 up->efr &= OMAP_UART_SW_CLR;
b612633b 1074
01d70bb3
RK		 1075 /*
1076 * IXON Flag:
3af08bd7
RK		 1077 * Enable XON/XOFF flow control on input.
1078 * Receiver compares XON1, XOFF1.
01d70bb3
RK		 1079 */
1080 if (termios->c_iflag & IXON)
3af08bd7 1081 up->efr |= OMAP_UART_SW_RX;
b612633b 1082
01d70bb3
RK		 1083 /*
1084 * IXOFF Flag:
3af08bd7
RK		 1085 * Enable XON/XOFF flow control on output.
1086 * Transmit XON1, XOFF1
01d70bb3
RK		 1087 */
1088 if (termios->c_iflag & IXOFF)
3af08bd7 1089 up->efr |= OMAP_UART_SW_TX;
b612633b 1090
01d70bb3
RK		 1091 /*
1092 * IXANY Flag:
1093 * Enable any character to restart output.
1094 * Operation resumes after receiving any
1095 * character after recognition of the XOFF character
1096 */
1097 if (termios->c_iflag & IXANY)
1098 up->mcr |= UART_MCR_XONANY;
1099 else
1100 up->mcr &= ~UART_MCR_XONANY;
b612633b 1101 }
c7d059ca 1102 serial_out(up, UART_MCR, up->mcr);
18f360f8
RK		 1103 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1104 serial_out(up, UART_EFR, up->efr);
1105 serial_out(up, UART_LCR, up->lcr);
b612633b
G		 1106
1107 serial_omap_set_mctrl(&up->port, up->port.mctrl);
b612633b
G		 1108
1109 spin_unlock_irqrestore(&up->port.lock, flags);
660ac5f4
FB		 1110 pm_runtime_mark_last_busy(up->dev);
1111 pm_runtime_put_autosuspend(up->dev);
ba77433d 1112 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
b612633b
G		 1113}
1114
1115static void
1116serial_omap_pm(struct uart_port *port, unsigned int state,
1117 unsigned int oldstate)
1118{
c990f351 1119 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 1120 unsigned char efr;
1121
ba77433d 1122 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
fcdca757 1123
d8ee4ea6 1124 pm_runtime_get_sync(up->dev);
662b083a 1125 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 1126 efr = serial_in(up, UART_EFR);
1127 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1128 serial_out(up, UART_LCR, 0);
1129
1130 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
662b083a 1131 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 1132 serial_out(up, UART_EFR, efr);
1133 serial_out(up, UART_LCR, 0);
fcdca757 1134
d8ee4ea6 1135 if (!device_may_wakeup(up->dev)) {
fcdca757 1136 if (!state)
d8ee4ea6 1137 pm_runtime_forbid(up->dev);
fcdca757 1138 else
d8ee4ea6 1139 pm_runtime_allow(up->dev);
fcdca757
G		 1140 }
1141
660ac5f4
FB		 1142 pm_runtime_mark_last_busy(up->dev);
1143 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 1144}
1145
1146static void serial_omap_release_port(struct uart_port *port)
1147{
1148 dev_dbg(port->dev, "serial_omap_release_port+\n");
1149}
1150
1151static int serial_omap_request_port(struct uart_port *port)
1152{
1153 dev_dbg(port->dev, "serial_omap_request_port+\n");
1154 return 0;
1155}
1156
1157static void serial_omap_config_port(struct uart_port *port, int flags)
1158{
c990f351 1159 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 1160
1161 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
ba77433d 1162 up->port.line);
b612633b 1163 up->port.type = PORT_OMAP;
3af08bd7 1164 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
b612633b
G		 1165}
1166
1167static int
1168serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1169{
1170 /* we don't want the core code to modify any port params */
1171 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1172 return -EINVAL;
1173}
1174
1175static const char *
1176serial_omap_type(struct uart_port *port)
1177{
c990f351 1178 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 1179
ba77433d 1180 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
b612633b
G		 1181 return up->name;
1182}
1183
b612633b
G		 1184#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1185
1186static inline void wait_for_xmitr(struct uart_omap_port *up)
1187{
1188 unsigned int status, tmout = 10000;
1189
1190 /* Wait up to 10ms for the character(s) to be sent. */
1191 do {
1192 status = serial_in(up, UART_LSR);
1193
1194 if (status & UART_LSR_BI)
1195 up->lsr_break_flag = UART_LSR_BI;
1196
1197 if (--tmout == 0)
1198 break;
1199 udelay(1);
1200 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1201
1202 /* Wait up to 1s for flow control if necessary */
1203 if (up->port.flags & UPF_CONS_FLOW) {
1204 tmout = 1000000;
1205 for (tmout = 1000000; tmout; tmout--) {
1206 unsigned int msr = serial_in(up, UART_MSR);
1207
1208 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1209 if (msr & UART_MSR_CTS)
1210 break;
1211
1212 udelay(1);
1213 }
1214 }
1215}
1216
1b41dbc1
CC		 1217#ifdef CONFIG_CONSOLE_POLL
1218
1219static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1220{
c990f351 1221 struct uart_omap_port *up = to_uart_omap_port(port);
fcdca757 1222
d8ee4ea6 1223 pm_runtime_get_sync(up->dev);
1b41dbc1
CC		 1224 wait_for_xmitr(up);
1225 serial_out(up, UART_TX, ch);
660ac5f4
FB		 1226 pm_runtime_mark_last_busy(up->dev);
1227 pm_runtime_put_autosuspend(up->dev);
1b41dbc1
CC		 1228}
1229
1230static int serial_omap_poll_get_char(struct uart_port *port)
1231{
c990f351 1232 struct uart_omap_port *up = to_uart_omap_port(port);
fcdca757 1233 unsigned int status;
1b41dbc1 1234
d8ee4ea6 1235 pm_runtime_get_sync(up->dev);
fcdca757 1236 status = serial_in(up, UART_LSR);
a6b19c33
FB		 1237 if (!(status & UART_LSR_DR)) {
1238 status = NO_POLL_CHAR;
1239 goto out;
1240 }
1b41dbc1 1241
fcdca757 1242 status = serial_in(up, UART_RX);
a6b19c33
FB		 1243
1244out:
660ac5f4
FB		 1245 pm_runtime_mark_last_busy(up->dev);
1246 pm_runtime_put_autosuspend(up->dev);
a6b19c33 1247
fcdca757 1248 return status;
1b41dbc1
CC		 1249}
1250
1251#endif /* CONFIG_CONSOLE_POLL */
1252
1253#ifdef CONFIG_SERIAL_OMAP_CONSOLE
1254
40477d0e 1255static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1b41dbc1
CC		 1256
1257static struct uart_driver serial_omap_reg;
1258
b612633b
G		 1259static void serial_omap_console_putchar(struct uart_port *port, int ch)
1260{
c990f351 1261 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 1262
1263 wait_for_xmitr(up);
1264 serial_out(up, UART_TX, ch);
1265}
1266
1267static void
1268serial_omap_console_write(struct console *co, const char *s,
1269 unsigned int count)
1270{
1271 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1272 unsigned long flags;
1273 unsigned int ier;
1274 int locked = 1;
1275
d8ee4ea6 1276 pm_runtime_get_sync(up->dev);
fcdca757 1277
b612633b
G		 1278 local_irq_save(flags);
1279 if (up->port.sysrq)
1280 locked = 0;
1281 else if (oops_in_progress)
1282 locked = spin_trylock(&up->port.lock);
1283 else
1284 spin_lock(&up->port.lock);
1285
1286 /*
1287 * First save the IER then disable the interrupts
1288 */
1289 ier = serial_in(up, UART_IER);
1290 serial_out(up, UART_IER, 0);
1291
1292 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1293
1294 /*
1295 * Finally, wait for transmitter to become empty
1296 * and restore the IER
1297 */
1298 wait_for_xmitr(up);
1299 serial_out(up, UART_IER, ier);
1300 /*
1301 * The receive handling will happen properly because the
1302 * receive ready bit will still be set; it is not cleared
1303 * on read. However, modem control will not, we must
1304 * call it if we have saved something in the saved flags
1305 * while processing with interrupts off.
1306 */
1307 if (up->msr_saved_flags)
1308 check_modem_status(up);
1309
d8ee4ea6
FB		 1310 pm_runtime_mark_last_busy(up->dev);
1311 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 1312 if (locked)
1313 spin_unlock(&up->port.lock);
1314 local_irq_restore(flags);
1315}
1316
1317static int __init
1318serial_omap_console_setup(struct console *co, char *options)
1319{
1320 struct uart_omap_port *up;
1321 int baud = 115200;
1322 int bits = 8;
1323 int parity = 'n';
1324 int flow = 'n';
1325
1326 if (serial_omap_console_ports[co->index] == NULL)
1327 return -ENODEV;
1328 up = serial_omap_console_ports[co->index];
1329
1330 if (options)
1331 uart_parse_options(options, &baud, &parity, &bits, &flow);
1332
1333 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1334}
1335
1336static struct console serial_omap_console = {
1337 .name = OMAP_SERIAL_NAME,
1338 .write = serial_omap_console_write,
1339 .device = uart_console_device,
1340 .setup = serial_omap_console_setup,
1341 .flags = CON_PRINTBUFFER,
1342 .index = -1,
1343 .data = &serial_omap_reg,
1344};
1345
1346static void serial_omap_add_console_port(struct uart_omap_port *up)
1347{
ba77433d 1348 serial_omap_console_ports[up->port.line] = up;
b612633b
G		 1349}
1350
1351#define OMAP_CONSOLE (&serial_omap_console)
1352
1353#else
1354
1355#define OMAP_CONSOLE NULL
1356
1357static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1358{}
1359
1360#endif
1361
4a0ac0f5
MJ		 1362/* Enable or disable the rs485 support */
1363static void
1364serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1365{
1366 struct uart_omap_port *up = to_uart_omap_port(port);
1367 unsigned long flags;
1368 unsigned int mode;
1369 int val;
1370
1371 pm_runtime_get_sync(up->dev);
1372 spin_lock_irqsave(&up->port.lock, flags);
1373
4a0ac0f5
MJ		 1374 /* Disable interrupts from this port */
1375 mode = up->ier;
1376 up->ier = 0;
1377 serial_out(up, UART_IER, 0);
1378
1379 /* store new config */
1380 up->rs485 = *rs485conf;
1381
1382 /*
1383 * Just as a precaution, only allow rs485
1384 * to be enabled if the gpio pin is valid
1385 */
1386 if (gpio_is_valid(up->rts_gpio)) {
1387 /* enable / disable rts */
1388 val = (up->rs485.flags & SER_RS485_ENABLED) ?
1389 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1390 val = (up->rs485.flags & val) ? 1 : 0;
1391 gpio_set_value(up->rts_gpio, val);
1392 } else
1393 up->rs485.flags &= ~SER_RS485_ENABLED;
1394
1395 /* Enable interrupts */
1396 up->ier = mode;
1397 serial_out(up, UART_IER, up->ier);
1398
018e7448
PP		 1399 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1400 * TX FIFO is below the trigger level.
1401 */
1402 if (!(up->rs485.flags & SER_RS485_ENABLED) &&
1403 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1404 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1405 serial_out(up, UART_OMAP_SCR, up->scr);
1406 }
1407
4a0ac0f5
MJ		 1408 spin_unlock_irqrestore(&up->port.lock, flags);
1409 pm_runtime_mark_last_busy(up->dev);
1410 pm_runtime_put_autosuspend(up->dev);
1411}
1412
1413static int
1414serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1415{
1416 struct serial_rs485 rs485conf;
1417
1418 switch (cmd) {
1419 case TIOCSRS485:
1420 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1421 sizeof(rs485conf)))
1422 return -EFAULT;
1423
1424 serial_omap_config_rs485(port, &rs485conf);
1425 break;
1426
1427 case TIOCGRS485:
1428 if (copy_to_user((struct serial_rs485 *) arg,
1429 &(to_uart_omap_port(port)->rs485),
1430 sizeof(rs485conf)))
1431 return -EFAULT;
1432 break;
1433
1434 default:
1435 return -ENOIOCTLCMD;
1436 }
1437 return 0;
1438}
1439
1440
b612633b
G		 1441static struct uart_ops serial_omap_pops = {
1442 .tx_empty = serial_omap_tx_empty,
1443 .set_mctrl = serial_omap_set_mctrl,
1444 .get_mctrl = serial_omap_get_mctrl,
1445 .stop_tx = serial_omap_stop_tx,
1446 .start_tx = serial_omap_start_tx,
3af08bd7
RK		 1447 .throttle = serial_omap_throttle,
1448 .unthrottle = serial_omap_unthrottle,
b612633b
G		 1449 .stop_rx = serial_omap_stop_rx,
1450 .enable_ms = serial_omap_enable_ms,
1451 .break_ctl = serial_omap_break_ctl,
1452 .startup = serial_omap_startup,
1453 .shutdown = serial_omap_shutdown,
1454 .set_termios = serial_omap_set_termios,
1455 .pm = serial_omap_pm,
1456 .type = serial_omap_type,
1457 .release_port = serial_omap_release_port,
1458 .request_port = serial_omap_request_port,
1459 .config_port = serial_omap_config_port,
1460 .verify_port = serial_omap_verify_port,
4a0ac0f5 1461 .ioctl = serial_omap_ioctl,
1b41dbc1
CC		 1462#ifdef CONFIG_CONSOLE_POLL
1463 .poll_put_char = serial_omap_poll_put_char,
1464 .poll_get_char = serial_omap_poll_get_char,
1465#endif
b612633b
G		 1466};
1467
1468static struct uart_driver serial_omap_reg = {
1469 .owner = THIS_MODULE,
1470 .driver_name = "OMAP-SERIAL",
1471 .dev_name = OMAP_SERIAL_NAME,
1472 .nr = OMAP_MAX_HSUART_PORTS,
1473 .cons = OMAP_CONSOLE,
1474};
1475
3bc4f0d8 1476#ifdef CONFIG_PM_SLEEP
ddd85e22
SP		 1477static int serial_omap_prepare(struct device *dev)
1478{
1479 struct uart_omap_port *up = dev_get_drvdata(dev);
1480
1481 up->is_suspending = true;
1482
1483 return 0;
1484}
1485
1486static void serial_omap_complete(struct device *dev)
1487{
1488 struct uart_omap_port *up = dev_get_drvdata(dev);
1489
1490 up->is_suspending = false;
1491}
1492
fcdca757 1493static int serial_omap_suspend(struct device *dev)
b612633b 1494{
fcdca757 1495 struct uart_omap_port *up = dev_get_drvdata(dev);
b612633b 1496
ac57e7f3 1497 uart_suspend_port(&serial_omap_reg, &up->port);
033d9959 1498 flush_work(&up->qos_work);
2fd14964 1499
d758c9c1
TL		 1500 if (device_may_wakeup(dev))
1501 serial_omap_enable_wakeup(up, true);
1502 else
1503 serial_omap_enable_wakeup(up, false);
1504
b612633b
G		 1505 return 0;
1506}
1507
fcdca757 1508static int serial_omap_resume(struct device *dev)
b612633b 1509{
fcdca757 1510 struct uart_omap_port *up = dev_get_drvdata(dev);
b612633b 1511
d758c9c1
TL		 1512 if (device_may_wakeup(dev))
1513 serial_omap_enable_wakeup(up, false);
1514
ac57e7f3
SP		 1515 uart_resume_port(&serial_omap_reg, &up->port);
1516
b612633b
G		 1517 return 0;
1518}
ddd85e22
SP		 1519#else
1520#define serial_omap_prepare NULL
2cb5a2fa 1521#define serial_omap_complete NULL
ddd85e22 1522#endif /* CONFIG_PM_SLEEP */
b612633b 1523
9671f099 1524static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
7c77c8de
G		 1525{
1526 u32 mvr, scheme;
1527 u16 revision, major, minor;
1528
76bac198 1529 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
7c77c8de
G		 1530
1531 /* Check revision register scheme */
1532 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1533
1534 switch (scheme) {
1535 case 0: /* Legacy Scheme: OMAP2/3 */
1536 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1537 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1538 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1539 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1540 break;
1541 case 1:
1542 /* New Scheme: OMAP4+ */
1543 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1544 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1545 OMAP_UART_MVR_MAJ_SHIFT;
1546 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1547 break;
1548 default:
d8ee4ea6 1549 dev_warn(up->dev,
7c77c8de
G		 1550 "Unknown %s revision, defaulting to highest\n",
1551 up->name);
1552 /* highest possible revision */
1553 major = 0xff;
1554 minor = 0xff;
1555 }
1556
1557 /* normalize revision for the driver */
1558 revision = UART_BUILD_REVISION(major, minor);
1559
1560 switch (revision) {
1561 case OMAP_UART_REV_46:
1562 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1563 UART_ERRATA_i291_DMA_FORCEIDLE);
1564 break;
1565 case OMAP_UART_REV_52:
1566 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1567 UART_ERRATA_i291_DMA_FORCEIDLE);
f64ffda6 1568 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
7c77c8de
G		 1569 break;
1570 case OMAP_UART_REV_63:
1571 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
f64ffda6 1572 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
7c77c8de
G		 1573 break;
1574 default:
1575 break;
1576 }
1577}
1578
9671f099 1579static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
d92b0dfc
RN		 1580{
1581 struct omap_uart_port_info *omap_up_info;
1582
1583 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1584 if (!omap_up_info)
1585 return NULL; /* out of memory */
1586
1587 of_property_read_u32(dev->of_node, "clock-frequency",
1588 &omap_up_info->uartclk);
1589 return omap_up_info;
1590}
1591
4a0ac0f5
MJ		 1592static int serial_omap_probe_rs485(struct uart_omap_port *up,
1593 struct device_node *np)
1594{
1595 struct serial_rs485 *rs485conf = &up->rs485;
1596 u32 rs485_delay[2];
1597 enum of_gpio_flags flags;
1598 int ret;
1599
1600 rs485conf->flags = 0;
1601 up->rts_gpio = -EINVAL;
1602
1603 if (!np)
1604 return 0;
1605
1606 if (of_property_read_bool(np, "rs485-rts-active-high"))
1607 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1608 else
1609 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1610
1611 /* check for tx enable gpio */
1612 up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1613 if (gpio_is_valid(up->rts_gpio)) {
404dc57c 1614 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
4a0ac0f5
MJ		 1615 if (ret < 0)
1616 return ret;
1617 ret = gpio_direction_output(up->rts_gpio,
1618 flags & SER_RS485_RTS_AFTER_SEND);
1619 if (ret < 0)
1620 return ret;
a64c1a1c
MG		 1621 } else if (up->rts_gpio == -EPROBE_DEFER) {
1622 return -EPROBE_DEFER;
1623 } else {
4a0ac0f5 1624 up->rts_gpio = -EINVAL;
a64c1a1c 1625 }
4a0ac0f5
MJ		 1626
1627 if (of_property_read_u32_array(np, "rs485-rts-delay",
1628 rs485_delay, 2) == 0) {
1629 rs485conf->delay_rts_before_send = rs485_delay[0];
1630 rs485conf->delay_rts_after_send = rs485_delay[1];
1631 }
1632
1633 if (of_property_read_bool(np, "rs485-rx-during-tx"))
1634 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1635
1636 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1637 rs485conf->flags |= SER_RS485_ENABLED;
1638
1639 return 0;
1640}
1641
9671f099 1642static int serial_omap_probe(struct platform_device *pdev)
b612633b 1643{
574de559 1644 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
cc51638a
FB		 1645 struct uart_omap_port *up;
1646 struct resource *mem;
cc51638a
FB		 1647 int uartirq = 0;
1648 int wakeirq = 0;
1649 int ret;
b612633b 1650
2a0b965c 1651 /* The optional wakeirq may be specified in the board dts file */
a0a490f9 1652 if (pdev->dev.of_node) {
2a0b965c
TL		 1653 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1654 if (!uartirq)
1655 return -EPROBE_DEFER;
1656 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
d92b0dfc 1657 omap_up_info = of_get_uart_port_info(&pdev->dev);
a0a490f9 1658 pdev->dev.platform_data = omap_up_info;
2a0b965c 1659 } else {
54af692c
FB		 1660 uartirq = platform_get_irq(pdev, 0);
1661 if (uartirq < 0)
1662 return -EPROBE_DEFER;
a0a490f9 1663 }
d92b0dfc 1664
b612633b
G		 1665 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1666 if (!mem) {
1667 dev_err(&pdev->dev, "no mem resource?\n");
1668 return -ENODEV;
1669 }
1670
388bc262 1671 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
28f65c11 1672 pdev->dev.driver->name)) {
b612633b
G		 1673 dev_err(&pdev->dev, "memory region already claimed\n");
1674 return -EBUSY;
1675 }
1676
9574f36f
N		 1677 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1678 omap_up_info->DTR_present) {
404dc57c
FB		 1679 ret = devm_gpio_request(&pdev->dev, omap_up_info->DTR_gpio,
1680 "omap-serial");
9574f36f
N		 1681 if (ret < 0)
1682 return ret;
1683 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1684 omap_up_info->DTR_inverted);
1685 if (ret < 0)
1686 return ret;
1687 }
1688
388bc262
S		 1689 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1690 if (!up)
1691 return -ENOMEM;
b612633b 1692
9574f36f
N		 1693 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1694 omap_up_info->DTR_present) {
1695 up->DTR_gpio = omap_up_info->DTR_gpio;
1696 up->DTR_inverted = omap_up_info->DTR_inverted;
5b6acc79 1697 } else {
9574f36f 1698 up->DTR_gpio = -EINVAL;
5b6acc79
FB		 1699 }
1700
9574f36f
N		 1701 up->DTR_active = 0;
1702
d8ee4ea6 1703 up->dev = &pdev->dev;
b612633b
G		 1704 up->port.dev = &pdev->dev;
1705 up->port.type = PORT_OMAP;
1706 up->port.iotype = UPIO_MEM;
2a0b965c
TL		 1707 up->port.irq = uartirq;
1708 up->wakeirq = wakeirq;
ce6acca6
MP		 1709 if (!up->wakeirq)
1710 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1711 up->port.line);
b612633b
G		 1712
1713 up->port.regshift = 2;
1714 up->port.fifosize = 64;
1715 up->port.ops = &serial_omap_pops;
b612633b 1716
d92b0dfc
RN		 1717 if (pdev->dev.of_node)
1718 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1719 else
1720 up->port.line = pdev->id;
1721
1722 if (up->port.line < 0) {
1723 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1724 up->port.line);
1725 ret = -ENODEV;
388bc262 1726 goto err_port_line;
d92b0dfc
RN		 1727 }
1728
4a0ac0f5
MJ		 1729 ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1730 if (ret < 0)
1731 goto err_rs485;
1732
d92b0dfc 1733 sprintf(up->name, "OMAP UART%d", up->port.line);
edd70ad7 1734 up->port.mapbase = mem->start;
388bc262
S		 1735 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1736 resource_size(mem));
edd70ad7
G		 1737 if (!up->port.membase) {
1738 dev_err(&pdev->dev, "can't ioremap UART\n");
1739 ret = -ENOMEM;
388bc262 1740 goto err_ioremap;
edd70ad7
G		 1741 }
1742
b612633b 1743 up->port.flags = omap_up_info->flags;
b612633b 1744 up->port.uartclk = omap_up_info->uartclk;
8fe789dc
RN		 1745 if (!up->port.uartclk) {
1746 up->port.uartclk = DEFAULT_CLK_SPEED;
e5f9bf72 1747 dev_warn(&pdev->dev,
80d8611d 1748 "No clock speed specified: using default: %d\n",
e5f9bf72 1749 DEFAULT_CLK_SPEED);
8fe789dc 1750 }
b612633b 1751
2fd14964
G		 1752 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1753 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1754 pm_qos_add_request(&up->pm_qos_request,
1755 PM_QOS_CPU_DMA_LATENCY, up->latency);
1756 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1757 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1758
93220dcc 1759 platform_set_drvdata(pdev, up);
a630fbfb
TL		 1760 if (omap_up_info->autosuspend_timeout == 0)
1761 omap_up_info->autosuspend_timeout = -1;
5b6acc79 1762
a630fbfb 1763 device_init_wakeup(up->dev, true);
fcdca757
G		 1764 pm_runtime_use_autosuspend(&pdev->dev);
1765 pm_runtime_set_autosuspend_delay(&pdev->dev,
c86845db 1766 omap_up_info->autosuspend_timeout);
fcdca757
G		 1767
1768 pm_runtime_irq_safe(&pdev->dev);
3026d14a
GS		 1769 pm_runtime_enable(&pdev->dev);
1770
fcdca757
G		 1771 pm_runtime_get_sync(&pdev->dev);
1772
7c77c8de
G		 1773 omap_serial_fill_features_erratas(up);
1774
ba77433d 1775 ui[up->port.line] = up;
b612633b
G		 1776 serial_omap_add_console_port(up);
1777
1778 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1779 if (ret != 0)
388bc262 1780 goto err_add_port;
b612633b 1781
660ac5f4
FB		 1782 pm_runtime_mark_last_busy(up->dev);
1783 pm_runtime_put_autosuspend(up->dev);
b612633b 1784 return 0;
388bc262
S		 1785
1786err_add_port:
1787 pm_runtime_put(&pdev->dev);
1788 pm_runtime_disable(&pdev->dev);
1789err_ioremap:
4a0ac0f5 1790err_rs485:
388bc262 1791err_port_line:
b612633b
G		 1792 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1793 pdev->id, __func__, ret);
b612633b
G		 1794 return ret;
1795}
1796
ae8d8a14 1797static int serial_omap_remove(struct platform_device *dev)
b612633b
G		 1798{
1799 struct uart_omap_port *up = platform_get_drvdata(dev);
1800
7e9c8e7d 1801 pm_runtime_put_sync(up->dev);
1b42c8b2
FB		 1802 pm_runtime_disable(up->dev);
1803 uart_remove_one_port(&serial_omap_reg, &up->port);
1804 pm_qos_remove_request(&up->pm_qos_request);
93a2e470 1805 device_init_wakeup(&dev->dev, false);
fcdca757 1806
fcdca757
G		 1807 return 0;
1808}
1809
94734749
G		 1810/*
1811 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1812 * The access to uart register after MDR1 Access
1813 * causes UART to corrupt data.
1814 *
1815 * Need a delay =
1816 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1817 * give 10 times as much
1818 */
1819static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1820{
1821 u8 timeout = 255;
1822
1823 serial_out(up, UART_OMAP_MDR1, mdr1);
1824 udelay(2);
1825 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1826 UART_FCR_CLEAR_RCVR);
1827 /*
1828 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1829 * TX_FIFO_E bit is 1.
1830 */
1831 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1832 (UART_LSR_THRE | UART_LSR_DR))) {
1833 timeout--;
1834 if (!timeout) {
1835 /* Should *never* happen. we warn and carry on */
d8ee4ea6 1836 dev_crit(up->dev, "Errata i202: timedout %x\n",
94734749
G		 1837 serial_in(up, UART_LSR));
1838 break;
1839 }
1840 udelay(1);
1841 }
1842}
1843
b5148856 1844#ifdef CONFIG_PM_RUNTIME
9f9ac1e8
G		 1845static void serial_omap_restore_context(struct uart_omap_port *up)
1846{
94734749
G		 1847 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1848 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1849 else
1850 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1851
9f9ac1e8
G		 1852 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1853 serial_out(up, UART_EFR, UART_EFR_ECB);
1854 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1855 serial_out(up, UART_IER, 0x0);
1856 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
c538d20c
G		 1857 serial_out(up, UART_DLL, up->dll);
1858 serial_out(up, UART_DLM, up->dlh);
9f9ac1e8
G		 1859 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1860 serial_out(up, UART_IER, up->ier);
1861 serial_out(up, UART_FCR, up->fcr);
1862 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1863 serial_out(up, UART_MCR, up->mcr);
1864 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
c538d20c 1865 serial_out(up, UART_OMAP_SCR, up->scr);
9f9ac1e8
G		 1866 serial_out(up, UART_EFR, up->efr);
1867 serial_out(up, UART_LCR, up->lcr);
94734749
G		 1868 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1869 serial_omap_mdr1_errataset(up, up->mdr1);
1870 else
1871 serial_out(up, UART_OMAP_MDR1, up->mdr1);
f64ffda6 1872 serial_out(up, UART_OMAP_WER, up->wer);
9f9ac1e8
G		 1873}
1874
fcdca757
G		 1875static int serial_omap_runtime_suspend(struct device *dev)
1876{
ec3bebc6 1877 struct uart_omap_port *up = dev_get_drvdata(dev);
ec3bebc6 1878
7f25301d
WY		 1879 if (!up)
1880 return -EINVAL;
1881
ddd85e22
SP		 1882 /*
1883 * When using 'no_console_suspend', the console UART must not be
1884 * suspended. Since driver suspend is managed by runtime suspend,
1885 * preventing runtime suspend (by returning error) will keep device
1886 * active during suspend.
1887 */
1888 if (up->is_suspending && !console_suspend_enabled &&
1889 uart_console(&up->port))
1890 return -EBUSY;
1891
e5b57c03 1892 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
ec3bebc6 1893
d758c9c1 1894 serial_omap_enable_wakeup(up, true);
62f3ec5f 1895
2fd14964
G		 1896 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1897 schedule_work(&up->qos_work);
1898
b612633b
G		 1899 return 0;
1900}
1901
fcdca757
G		 1902static int serial_omap_runtime_resume(struct device *dev)
1903{
9f9ac1e8
G		 1904 struct uart_omap_port *up = dev_get_drvdata(dev);
1905
39aee51d 1906 int loss_cnt = serial_omap_get_context_loss_count(up);
ec3bebc6 1907
d758c9c1
TL		 1908 serial_omap_enable_wakeup(up, false);
1909
39aee51d 1910 if (loss_cnt < 0) {
a630fbfb 1911 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
39aee51d 1912 loss_cnt);
ac57e7f3 1913 serial_omap_restore_context(up);
39aee51d
S		 1914 } else if (up->context_loss_cnt != loss_cnt) {
1915 serial_omap_restore_context(up);
1916 }
ac57e7f3
SP		 1917 up->latency = up->calc_latency;
1918 schedule_work(&up->qos_work);
9f9ac1e8 1919
b612633b
G		 1920 return 0;
1921}
fcdca757
G		 1922#endif
1923
1924static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1925 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1926 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1927 serial_omap_runtime_resume, NULL)
ddd85e22
SP		 1928 .prepare = serial_omap_prepare,
1929 .complete = serial_omap_complete,
fcdca757
G		 1930};
1931
d92b0dfc
RN		 1932#if defined(CONFIG_OF)
1933static const struct of_device_id omap_serial_of_match[] = {
1934 { .compatible = "ti,omap2-uart" },
1935 { .compatible = "ti,omap3-uart" },
1936 { .compatible = "ti,omap4-uart" },
1937 {},
1938};
1939MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1940#endif
b612633b
G		 1941
1942static struct platform_driver serial_omap_driver = {
1943 .probe = serial_omap_probe,
2d47b716 1944 .remove = serial_omap_remove,
b612633b
G		 1945 .driver = {
1946 .name = DRIVER_NAME,
fcdca757 1947 .pm = &serial_omap_dev_pm_ops,
d92b0dfc 1948 .of_match_table = of_match_ptr(omap_serial_of_match),
b612633b
G		 1949 },
1950};
1951
1952static int __init serial_omap_init(void)
1953{
1954 int ret;
1955
1956 ret = uart_register_driver(&serial_omap_reg);
1957 if (ret != 0)
1958 return ret;
1959 ret = platform_driver_register(&serial_omap_driver);
1960 if (ret != 0)
1961 uart_unregister_driver(&serial_omap_reg);
1962 return ret;
1963}
1964
1965static void __exit serial_omap_exit(void)
1966{
1967 platform_driver_unregister(&serial_omap_driver);
1968 uart_unregister_driver(&serial_omap_reg);
1969}
1970
1971module_init(serial_omap_init);
1972module_exit(serial_omap_exit);
1973
1974MODULE_DESCRIPTION("OMAP High Speed UART driver");
1975MODULE_LICENSE("GPL");
1976MODULE_AUTHOR("Texas Instruments Inc");
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