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Commit | Line | Data |
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b612633b G |
1 | /* |
2 | * Driver for OMAP-UART controller. | |
3 | * Based on drivers/serial/8250.c | |
4 | * | |
5 | * Copyright (C) 2010 Texas Instruments. | |
6 | * | |
7 | * Authors: | |
8 | * Govindraj R <govindraj.raja@ti.com> | |
9 | * Thara Gopinath <thara@ti.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
25985edc | 16 | * Note: This driver is made separate from 8250 driver as we cannot |
b612633b G |
17 | * over load 8250 driver with omap platform specific configuration for |
18 | * features like DMA, it makes easier to implement features like DMA and | |
19 | * hardware flow control and software flow control configuration with | |
20 | * this driver as required for the omap-platform. | |
21 | */ | |
22 | ||
364a6ece TW |
23 | #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
24 | #define SUPPORT_SYSRQ | |
25 | #endif | |
26 | ||
b612633b G |
27 | #include <linux/module.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/console.h> | |
30 | #include <linux/serial_reg.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/tty.h> | |
34 | #include <linux/tty_flip.h> | |
d21e4005 | 35 | #include <linux/platform_device.h> |
b612633b | 36 | #include <linux/io.h> |
b612633b G |
37 | #include <linux/clk.h> |
38 | #include <linux/serial_core.h> | |
39 | #include <linux/irq.h> | |
fcdca757 | 40 | #include <linux/pm_runtime.h> |
d92b0dfc | 41 | #include <linux/of.h> |
9574f36f | 42 | #include <linux/gpio.h> |
3dbc5ce2 | 43 | #include <linux/pinctrl/consumer.h> |
b612633b | 44 | |
b612633b G |
45 | #include <plat/omap-serial.h> |
46 | ||
7c77c8de G |
47 | #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) |
48 | ||
49 | #define OMAP_UART_REV_42 0x0402 | |
50 | #define OMAP_UART_REV_46 0x0406 | |
51 | #define OMAP_UART_REV_52 0x0502 | |
52 | #define OMAP_UART_REV_63 0x0603 | |
53 | ||
8fe789dc RN |
54 | #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/ |
55 | ||
0ba5f668 PW |
56 | /* SCR register bitmasks */ |
57 | #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) | |
58 | ||
59 | /* FCR register bitmasks */ | |
0ba5f668 | 60 | #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) |
6721ab7f | 61 | #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) |
0ba5f668 | 62 | |
7c77c8de G |
63 | /* MVR register bitmasks */ |
64 | #define OMAP_UART_MVR_SCHEME_SHIFT 30 | |
65 | ||
66 | #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 | |
67 | #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 | |
68 | #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f | |
69 | ||
70 | #define OMAP_UART_MVR_MAJ_MASK 0x700 | |
71 | #define OMAP_UART_MVR_MAJ_SHIFT 8 | |
72 | #define OMAP_UART_MVR_MIN_MASK 0x3f | |
73 | ||
d37c6ceb FB |
74 | struct uart_omap_port { |
75 | struct uart_port port; | |
76 | struct uart_omap_dma uart_dma; | |
77 | struct device *dev; | |
78 | ||
79 | unsigned char ier; | |
80 | unsigned char lcr; | |
81 | unsigned char mcr; | |
82 | unsigned char fcr; | |
83 | unsigned char efr; | |
84 | unsigned char dll; | |
85 | unsigned char dlh; | |
86 | unsigned char mdr1; | |
87 | unsigned char scr; | |
88 | ||
89 | int use_dma; | |
90 | /* | |
91 | * Some bits in registers are cleared on a read, so they must | |
92 | * be saved whenever the register is read but the bits will not | |
93 | * be immediately processed. | |
94 | */ | |
95 | unsigned int lsr_break_flag; | |
96 | unsigned char msr_saved_flags; | |
97 | char name[20]; | |
98 | unsigned long port_activity; | |
99 | u32 context_loss_cnt; | |
100 | u32 errata; | |
101 | u8 wakeups_enabled; | |
102 | unsigned int irq_pending:1; | |
103 | ||
e36851d0 FB |
104 | int DTR_gpio; |
105 | int DTR_inverted; | |
106 | int DTR_active; | |
107 | ||
d37c6ceb FB |
108 | struct pm_qos_request pm_qos_request; |
109 | u32 latency; | |
110 | u32 calc_latency; | |
111 | struct work_struct qos_work; | |
3dbc5ce2 | 112 | struct pinctrl *pins; |
d37c6ceb FB |
113 | }; |
114 | ||
115 | #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) | |
116 | ||
b612633b G |
117 | static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; |
118 | ||
119 | /* Forward declaration of functions */ | |
94734749 | 120 | static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); |
b612633b | 121 | |
2fd14964 | 122 | static struct workqueue_struct *serial_omap_uart_wq; |
b612633b G |
123 | |
124 | static inline unsigned int serial_in(struct uart_omap_port *up, int offset) | |
125 | { | |
126 | offset <<= up->port.regshift; | |
127 | return readw(up->port.membase + offset); | |
128 | } | |
129 | ||
130 | static inline void serial_out(struct uart_omap_port *up, int offset, int value) | |
131 | { | |
132 | offset <<= up->port.regshift; | |
133 | writew(value, up->port.membase + offset); | |
134 | } | |
135 | ||
136 | static inline void serial_omap_clear_fifos(struct uart_omap_port *up) | |
137 | { | |
138 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
139 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
140 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
141 | serial_out(up, UART_FCR, 0); | |
142 | } | |
143 | ||
e5b57c03 FB |
144 | static int serial_omap_get_context_loss_count(struct uart_omap_port *up) |
145 | { | |
d8ee4ea6 | 146 | struct omap_uart_port_info *pdata = up->dev->platform_data; |
e5b57c03 | 147 | |
ce2f08de | 148 | if (!pdata || !pdata->get_context_loss_count) |
e5b57c03 FB |
149 | return 0; |
150 | ||
d8ee4ea6 | 151 | return pdata->get_context_loss_count(up->dev); |
e5b57c03 FB |
152 | } |
153 | ||
154 | static void serial_omap_set_forceidle(struct uart_omap_port *up) | |
155 | { | |
d8ee4ea6 | 156 | struct omap_uart_port_info *pdata = up->dev->platform_data; |
e5b57c03 | 157 | |
ce2f08de FB |
158 | if (!pdata || !pdata->set_forceidle) |
159 | return; | |
160 | ||
161 | pdata->set_forceidle(up->dev); | |
e5b57c03 FB |
162 | } |
163 | ||
164 | static void serial_omap_set_noidle(struct uart_omap_port *up) | |
165 | { | |
d8ee4ea6 | 166 | struct omap_uart_port_info *pdata = up->dev->platform_data; |
e5b57c03 | 167 | |
ce2f08de FB |
168 | if (!pdata || !pdata->set_noidle) |
169 | return; | |
170 | ||
171 | pdata->set_noidle(up->dev); | |
e5b57c03 FB |
172 | } |
173 | ||
174 | static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) | |
175 | { | |
d8ee4ea6 | 176 | struct omap_uart_port_info *pdata = up->dev->platform_data; |
e5b57c03 | 177 | |
ce2f08de FB |
178 | if (!pdata || !pdata->enable_wakeup) |
179 | return; | |
180 | ||
181 | pdata->enable_wakeup(up->dev, enable); | |
e5b57c03 FB |
182 | } |
183 | ||
b612633b G |
184 | /* |
185 | * serial_omap_get_divisor - calculate divisor value | |
186 | * @port: uart port info | |
187 | * @baud: baudrate for which divisor needs to be calculated. | |
188 | * | |
189 | * We have written our own function to get the divisor so as to support | |
190 | * 13x mode. 3Mbps Baudrate as an different divisor. | |
191 | * Reference OMAP TRM Chapter 17: | |
192 | * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates | |
193 | * referring to oversampling - divisor value | |
194 | * baudrate 460,800 to 3,686,400 all have divisor 13 | |
195 | * except 3,000,000 which has divisor value 16 | |
196 | */ | |
197 | static unsigned int | |
198 | serial_omap_get_divisor(struct uart_port *port, unsigned int baud) | |
199 | { | |
200 | unsigned int divisor; | |
201 | ||
202 | if (baud > OMAP_MODE13X_SPEED && baud != 3000000) | |
203 | divisor = 13; | |
204 | else | |
205 | divisor = 16; | |
206 | return port->uartclk/(baud * divisor); | |
207 | } | |
208 | ||
b612633b G |
209 | static void serial_omap_enable_ms(struct uart_port *port) |
210 | { | |
c990f351 | 211 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 212 | |
ba77433d | 213 | dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); |
fcdca757 | 214 | |
d8ee4ea6 | 215 | pm_runtime_get_sync(up->dev); |
b612633b G |
216 | up->ier |= UART_IER_MSI; |
217 | serial_out(up, UART_IER, up->ier); | |
660ac5f4 FB |
218 | pm_runtime_mark_last_busy(up->dev); |
219 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
220 | } |
221 | ||
222 | static void serial_omap_stop_tx(struct uart_port *port) | |
223 | { | |
c990f351 | 224 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 225 | |
d8ee4ea6 | 226 | pm_runtime_get_sync(up->dev); |
b612633b G |
227 | if (up->ier & UART_IER_THRI) { |
228 | up->ier &= ~UART_IER_THRI; | |
229 | serial_out(up, UART_IER, up->ier); | |
230 | } | |
fcdca757 | 231 | |
49457430 | 232 | serial_omap_set_forceidle(up); |
be4b0281 | 233 | |
d8ee4ea6 FB |
234 | pm_runtime_mark_last_busy(up->dev); |
235 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
236 | } |
237 | ||
238 | static void serial_omap_stop_rx(struct uart_port *port) | |
239 | { | |
c990f351 | 240 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 241 | |
d8ee4ea6 | 242 | pm_runtime_get_sync(up->dev); |
b612633b G |
243 | up->ier &= ~UART_IER_RLSI; |
244 | up->port.read_status_mask &= ~UART_LSR_DR; | |
245 | serial_out(up, UART_IER, up->ier); | |
d8ee4ea6 FB |
246 | pm_runtime_mark_last_busy(up->dev); |
247 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
248 | } |
249 | ||
bf63a086 | 250 | static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) |
b612633b G |
251 | { |
252 | struct circ_buf *xmit = &up->port.state->xmit; | |
253 | int count; | |
254 | ||
bf63a086 FB |
255 | if (!(lsr & UART_LSR_THRE)) |
256 | return; | |
257 | ||
b612633b G |
258 | if (up->port.x_char) { |
259 | serial_out(up, UART_TX, up->port.x_char); | |
260 | up->port.icount.tx++; | |
261 | up->port.x_char = 0; | |
262 | return; | |
263 | } | |
264 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
265 | serial_omap_stop_tx(&up->port); | |
266 | return; | |
267 | } | |
af681cad | 268 | count = up->port.fifosize / 4; |
b612633b G |
269 | do { |
270 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
271 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
272 | up->port.icount.tx++; | |
273 | if (uart_circ_empty(xmit)) | |
274 | break; | |
275 | } while (--count > 0); | |
276 | ||
0324a821 RK |
277 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { |
278 | spin_unlock(&up->port.lock); | |
b612633b | 279 | uart_write_wakeup(&up->port); |
0324a821 RK |
280 | spin_lock(&up->port.lock); |
281 | } | |
b612633b G |
282 | |
283 | if (uart_circ_empty(xmit)) | |
284 | serial_omap_stop_tx(&up->port); | |
285 | } | |
286 | ||
287 | static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) | |
288 | { | |
289 | if (!(up->ier & UART_IER_THRI)) { | |
290 | up->ier |= UART_IER_THRI; | |
291 | serial_out(up, UART_IER, up->ier); | |
292 | } | |
293 | } | |
294 | ||
295 | static void serial_omap_start_tx(struct uart_port *port) | |
296 | { | |
c990f351 | 297 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 298 | |
49457430 FB |
299 | pm_runtime_get_sync(up->dev); |
300 | serial_omap_enable_ier_thri(up); | |
301 | serial_omap_set_noidle(up); | |
302 | pm_runtime_mark_last_busy(up->dev); | |
303 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
304 | } |
305 | ||
306 | static unsigned int check_modem_status(struct uart_omap_port *up) | |
307 | { | |
308 | unsigned int status; | |
309 | ||
310 | status = serial_in(up, UART_MSR); | |
311 | status |= up->msr_saved_flags; | |
312 | up->msr_saved_flags = 0; | |
313 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
314 | return status; | |
315 | ||
316 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && | |
317 | up->port.state != NULL) { | |
318 | if (status & UART_MSR_TERI) | |
319 | up->port.icount.rng++; | |
320 | if (status & UART_MSR_DDSR) | |
321 | up->port.icount.dsr++; | |
322 | if (status & UART_MSR_DDCD) | |
323 | uart_handle_dcd_change | |
324 | (&up->port, status & UART_MSR_DCD); | |
325 | if (status & UART_MSR_DCTS) | |
326 | uart_handle_cts_change | |
327 | (&up->port, status & UART_MSR_CTS); | |
328 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); | |
329 | } | |
330 | ||
331 | return status; | |
332 | } | |
333 | ||
72256cbd FB |
334 | static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) |
335 | { | |
336 | unsigned int flag; | |
9a12fcf8 S |
337 | unsigned char ch = 0; |
338 | ||
339 | if (likely(lsr & UART_LSR_DR)) | |
340 | ch = serial_in(up, UART_RX); | |
72256cbd FB |
341 | |
342 | up->port.icount.rx++; | |
343 | flag = TTY_NORMAL; | |
344 | ||
345 | if (lsr & UART_LSR_BI) { | |
346 | flag = TTY_BREAK; | |
347 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
348 | up->port.icount.brk++; | |
349 | /* | |
350 | * We do the SysRQ and SAK checking | |
351 | * here because otherwise the break | |
352 | * may get masked by ignore_status_mask | |
353 | * or read_status_mask. | |
354 | */ | |
355 | if (uart_handle_break(&up->port)) | |
356 | return; | |
357 | ||
358 | } | |
359 | ||
360 | if (lsr & UART_LSR_PE) { | |
361 | flag = TTY_PARITY; | |
362 | up->port.icount.parity++; | |
363 | } | |
364 | ||
365 | if (lsr & UART_LSR_FE) { | |
366 | flag = TTY_FRAME; | |
367 | up->port.icount.frame++; | |
368 | } | |
369 | ||
370 | if (lsr & UART_LSR_OE) | |
371 | up->port.icount.overrun++; | |
372 | ||
373 | #ifdef CONFIG_SERIAL_OMAP_CONSOLE | |
374 | if (up->port.line == up->port.cons->index) { | |
375 | /* Recover the break flag from console xmit */ | |
376 | lsr |= up->lsr_break_flag; | |
377 | } | |
378 | #endif | |
379 | uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); | |
380 | } | |
381 | ||
382 | static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) | |
383 | { | |
384 | unsigned char ch = 0; | |
385 | unsigned int flag; | |
386 | ||
387 | if (!(lsr & UART_LSR_DR)) | |
388 | return; | |
389 | ||
390 | ch = serial_in(up, UART_RX); | |
391 | flag = TTY_NORMAL; | |
392 | up->port.icount.rx++; | |
393 | ||
394 | if (uart_handle_sysrq_char(&up->port, ch)) | |
395 | return; | |
396 | ||
397 | uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); | |
398 | } | |
399 | ||
b612633b G |
400 | /** |
401 | * serial_omap_irq() - This handles the interrupt from one port | |
402 | * @irq: uart port irq number | |
403 | * @dev_id: uart port info | |
404 | */ | |
52c5513d | 405 | static irqreturn_t serial_omap_irq(int irq, void *dev_id) |
b612633b G |
406 | { |
407 | struct uart_omap_port *up = dev_id; | |
72256cbd | 408 | struct tty_struct *tty = up->port.state->port.tty; |
b612633b | 409 | unsigned int iir, lsr; |
81b75aef | 410 | unsigned int type; |
81b75aef | 411 | irqreturn_t ret = IRQ_NONE; |
72256cbd | 412 | int max_count = 256; |
b612633b | 413 | |
6c3a30c7 | 414 | spin_lock(&up->port.lock); |
d8ee4ea6 | 415 | pm_runtime_get_sync(up->dev); |
72256cbd FB |
416 | |
417 | do { | |
81b75aef | 418 | iir = serial_in(up, UART_IIR); |
72256cbd FB |
419 | if (iir & UART_IIR_NO_INT) |
420 | break; | |
421 | ||
422 | ret = IRQ_HANDLED; | |
423 | lsr = serial_in(up, UART_LSR); | |
424 | ||
425 | /* extract IRQ type from IIR register */ | |
426 | type = iir & 0x3e; | |
427 | ||
428 | switch (type) { | |
429 | case UART_IIR_MSI: | |
430 | check_modem_status(up); | |
431 | break; | |
432 | case UART_IIR_THRI: | |
bf63a086 | 433 | transmit_chars(up, lsr); |
72256cbd FB |
434 | break; |
435 | case UART_IIR_RX_TIMEOUT: | |
436 | /* FALLTHROUGH */ | |
437 | case UART_IIR_RDI: | |
438 | serial_omap_rdi(up, lsr); | |
439 | break; | |
440 | case UART_IIR_RLSI: | |
441 | serial_omap_rlsi(up, lsr); | |
442 | break; | |
443 | case UART_IIR_CTS_RTS_DSR: | |
444 | /* simply try again */ | |
445 | break; | |
446 | case UART_IIR_XOFF: | |
447 | /* FALLTHROUGH */ | |
448 | default: | |
449 | break; | |
450 | } | |
451 | } while (!(iir & UART_IIR_NO_INT) && max_count--); | |
b612633b | 452 | |
6c3a30c7 | 453 | spin_unlock(&up->port.lock); |
72256cbd FB |
454 | |
455 | tty_flip_buffer_push(tty); | |
456 | ||
d8ee4ea6 FB |
457 | pm_runtime_mark_last_busy(up->dev); |
458 | pm_runtime_put_autosuspend(up->dev); | |
b612633b | 459 | up->port_activity = jiffies; |
81b75aef FB |
460 | |
461 | return ret; | |
b612633b G |
462 | } |
463 | ||
464 | static unsigned int serial_omap_tx_empty(struct uart_port *port) | |
465 | { | |
c990f351 | 466 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
467 | unsigned long flags = 0; |
468 | unsigned int ret = 0; | |
469 | ||
d8ee4ea6 | 470 | pm_runtime_get_sync(up->dev); |
ba77433d | 471 | dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); |
b612633b G |
472 | spin_lock_irqsave(&up->port.lock, flags); |
473 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
474 | spin_unlock_irqrestore(&up->port.lock, flags); | |
660ac5f4 FB |
475 | pm_runtime_mark_last_busy(up->dev); |
476 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
477 | return ret; |
478 | } | |
479 | ||
480 | static unsigned int serial_omap_get_mctrl(struct uart_port *port) | |
481 | { | |
c990f351 | 482 | struct uart_omap_port *up = to_uart_omap_port(port); |
514f31d1 | 483 | unsigned int status; |
b612633b G |
484 | unsigned int ret = 0; |
485 | ||
d8ee4ea6 | 486 | pm_runtime_get_sync(up->dev); |
b612633b | 487 | status = check_modem_status(up); |
660ac5f4 FB |
488 | pm_runtime_mark_last_busy(up->dev); |
489 | pm_runtime_put_autosuspend(up->dev); | |
fcdca757 | 490 | |
ba77433d | 491 | dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); |
b612633b G |
492 | |
493 | if (status & UART_MSR_DCD) | |
494 | ret |= TIOCM_CAR; | |
495 | if (status & UART_MSR_RI) | |
496 | ret |= TIOCM_RNG; | |
497 | if (status & UART_MSR_DSR) | |
498 | ret |= TIOCM_DSR; | |
499 | if (status & UART_MSR_CTS) | |
500 | ret |= TIOCM_CTS; | |
501 | return ret; | |
502 | } | |
503 | ||
504 | static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
505 | { | |
c990f351 | 506 | struct uart_omap_port *up = to_uart_omap_port(port); |
9363f8fa | 507 | unsigned char mcr = 0, old_mcr; |
b612633b | 508 | |
ba77433d | 509 | dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); |
b612633b G |
510 | if (mctrl & TIOCM_RTS) |
511 | mcr |= UART_MCR_RTS; | |
512 | if (mctrl & TIOCM_DTR) | |
513 | mcr |= UART_MCR_DTR; | |
514 | if (mctrl & TIOCM_OUT1) | |
515 | mcr |= UART_MCR_OUT1; | |
516 | if (mctrl & TIOCM_OUT2) | |
517 | mcr |= UART_MCR_OUT2; | |
518 | if (mctrl & TIOCM_LOOP) | |
519 | mcr |= UART_MCR_LOOP; | |
520 | ||
d8ee4ea6 | 521 | pm_runtime_get_sync(up->dev); |
9363f8fa RK |
522 | old_mcr = serial_in(up, UART_MCR); |
523 | old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | | |
524 | UART_MCR_DTR | UART_MCR_RTS); | |
525 | up->mcr = old_mcr | mcr; | |
c538d20c | 526 | serial_out(up, UART_MCR, up->mcr); |
660ac5f4 FB |
527 | pm_runtime_mark_last_busy(up->dev); |
528 | pm_runtime_put_autosuspend(up->dev); | |
9574f36f N |
529 | |
530 | if (gpio_is_valid(up->DTR_gpio) && | |
531 | !!(mctrl & TIOCM_DTR) != up->DTR_active) { | |
532 | up->DTR_active = !up->DTR_active; | |
533 | if (gpio_cansleep(up->DTR_gpio)) | |
534 | schedule_work(&up->qos_work); | |
535 | else | |
536 | gpio_set_value(up->DTR_gpio, | |
537 | up->DTR_active != up->DTR_inverted); | |
538 | } | |
b612633b G |
539 | } |
540 | ||
541 | static void serial_omap_break_ctl(struct uart_port *port, int break_state) | |
542 | { | |
c990f351 | 543 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
544 | unsigned long flags = 0; |
545 | ||
ba77433d | 546 | dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); |
d8ee4ea6 | 547 | pm_runtime_get_sync(up->dev); |
b612633b G |
548 | spin_lock_irqsave(&up->port.lock, flags); |
549 | if (break_state == -1) | |
550 | up->lcr |= UART_LCR_SBC; | |
551 | else | |
552 | up->lcr &= ~UART_LCR_SBC; | |
553 | serial_out(up, UART_LCR, up->lcr); | |
554 | spin_unlock_irqrestore(&up->port.lock, flags); | |
660ac5f4 FB |
555 | pm_runtime_mark_last_busy(up->dev); |
556 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
557 | } |
558 | ||
559 | static int serial_omap_startup(struct uart_port *port) | |
560 | { | |
c990f351 | 561 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
562 | unsigned long flags = 0; |
563 | int retval; | |
564 | ||
565 | /* | |
566 | * Allocate the IRQ | |
567 | */ | |
568 | retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, | |
569 | up->name, up); | |
570 | if (retval) | |
571 | return retval; | |
572 | ||
ba77433d | 573 | dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); |
b612633b | 574 | |
d8ee4ea6 | 575 | pm_runtime_get_sync(up->dev); |
b612633b G |
576 | /* |
577 | * Clear the FIFO buffers and disable them. | |
578 | * (they will be reenabled in set_termios()) | |
579 | */ | |
580 | serial_omap_clear_fifos(up); | |
581 | /* For Hardware flow control */ | |
582 | serial_out(up, UART_MCR, UART_MCR_RTS); | |
583 | ||
584 | /* | |
585 | * Clear the interrupt registers. | |
586 | */ | |
587 | (void) serial_in(up, UART_LSR); | |
588 | if (serial_in(up, UART_LSR) & UART_LSR_DR) | |
589 | (void) serial_in(up, UART_RX); | |
590 | (void) serial_in(up, UART_IIR); | |
591 | (void) serial_in(up, UART_MSR); | |
592 | ||
593 | /* | |
594 | * Now, initialize the UART | |
595 | */ | |
596 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
597 | spin_lock_irqsave(&up->port.lock, flags); | |
598 | /* | |
599 | * Most PC uarts need OUT2 raised to enable interrupts. | |
600 | */ | |
601 | up->port.mctrl |= TIOCM_OUT2; | |
602 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
603 | spin_unlock_irqrestore(&up->port.lock, flags); | |
604 | ||
605 | up->msr_saved_flags = 0; | |
b612633b G |
606 | /* |
607 | * Finally, enable interrupts. Note: Modem status interrupts | |
608 | * are set via set_termios(), which will be occurring imminently | |
609 | * anyway, so we don't enable them here. | |
610 | */ | |
611 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
612 | serial_out(up, UART_IER, up->ier); | |
613 | ||
78841462 JN |
614 | /* Enable module level wake up */ |
615 | serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); | |
616 | ||
d8ee4ea6 FB |
617 | pm_runtime_mark_last_busy(up->dev); |
618 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
619 | up->port_activity = jiffies; |
620 | return 0; | |
621 | } | |
622 | ||
623 | static void serial_omap_shutdown(struct uart_port *port) | |
624 | { | |
c990f351 | 625 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
626 | unsigned long flags = 0; |
627 | ||
ba77433d | 628 | dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); |
fcdca757 | 629 | |
d8ee4ea6 | 630 | pm_runtime_get_sync(up->dev); |
b612633b G |
631 | /* |
632 | * Disable interrupts from this port | |
633 | */ | |
634 | up->ier = 0; | |
635 | serial_out(up, UART_IER, 0); | |
636 | ||
637 | spin_lock_irqsave(&up->port.lock, flags); | |
638 | up->port.mctrl &= ~TIOCM_OUT2; | |
639 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
640 | spin_unlock_irqrestore(&up->port.lock, flags); | |
641 | ||
642 | /* | |
643 | * Disable break condition and FIFOs | |
644 | */ | |
645 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | |
646 | serial_omap_clear_fifos(up); | |
647 | ||
648 | /* | |
649 | * Read data port to reset things, and then free the irq | |
650 | */ | |
651 | if (serial_in(up, UART_LSR) & UART_LSR_DR) | |
652 | (void) serial_in(up, UART_RX); | |
fcdca757 | 653 | |
660ac5f4 FB |
654 | pm_runtime_mark_last_busy(up->dev); |
655 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
656 | free_irq(up->port.irq, up); |
657 | } | |
658 | ||
659 | static inline void | |
660 | serial_omap_configure_xonxoff | |
661 | (struct uart_omap_port *up, struct ktermios *termios) | |
662 | { | |
b612633b | 663 | up->lcr = serial_in(up, UART_LCR); |
662b083a | 664 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
665 | up->efr = serial_in(up, UART_EFR); |
666 | serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB); | |
667 | ||
668 | serial_out(up, UART_XON1, termios->c_cc[VSTART]); | |
669 | serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); | |
670 | ||
671 | /* clear SW control mode bits */ | |
c538d20c | 672 | up->efr &= OMAP_UART_SW_CLR; |
b612633b G |
673 | |
674 | /* | |
675 | * IXON Flag: | |
a4f74385 FB |
676 | * Enable XON/XOFF flow control on output. |
677 | * Transmit XON1, XOFF1 | |
b612633b G |
678 | */ |
679 | if (termios->c_iflag & IXON) | |
a4f74385 | 680 | up->efr |= OMAP_UART_SW_TX; |
b612633b G |
681 | |
682 | /* | |
683 | * IXOFF Flag: | |
a4f74385 FB |
684 | * Enable XON/XOFF flow control on input. |
685 | * Receiver compares XON1, XOFF1. | |
b612633b G |
686 | */ |
687 | if (termios->c_iflag & IXOFF) | |
a4f74385 | 688 | up->efr |= OMAP_UART_SW_RX; |
b612633b G |
689 | |
690 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); | |
662b083a | 691 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
692 | |
693 | up->mcr = serial_in(up, UART_MCR); | |
694 | ||
695 | /* | |
696 | * IXANY Flag: | |
697 | * Enable any character to restart output. | |
698 | * Operation resumes after receiving any | |
699 | * character after recognition of the XOFF character | |
700 | */ | |
701 | if (termios->c_iflag & IXANY) | |
702 | up->mcr |= UART_MCR_XONANY; | |
da5d01f2 RK |
703 | else |
704 | up->mcr &= ~UART_MCR_XONANY; | |
b612633b G |
705 | |
706 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); | |
662b083a | 707 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b | 708 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); |
d864c03b | 709 | serial_out(up, UART_EFR, up->efr); |
662b083a | 710 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
711 | serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); |
712 | serial_out(up, UART_LCR, up->lcr); | |
713 | } | |
714 | ||
2fd14964 G |
715 | static void serial_omap_uart_qos_work(struct work_struct *work) |
716 | { | |
717 | struct uart_omap_port *up = container_of(work, struct uart_omap_port, | |
718 | qos_work); | |
719 | ||
720 | pm_qos_update_request(&up->pm_qos_request, up->latency); | |
9574f36f N |
721 | if (gpio_is_valid(up->DTR_gpio)) |
722 | gpio_set_value_cansleep(up->DTR_gpio, | |
723 | up->DTR_active != up->DTR_inverted); | |
2fd14964 G |
724 | } |
725 | ||
b612633b G |
726 | static void |
727 | serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, | |
728 | struct ktermios *old) | |
729 | { | |
c990f351 | 730 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
731 | unsigned char cval = 0; |
732 | unsigned char efr = 0; | |
733 | unsigned long flags = 0; | |
734 | unsigned int baud, quot; | |
735 | ||
736 | switch (termios->c_cflag & CSIZE) { | |
737 | case CS5: | |
738 | cval = UART_LCR_WLEN5; | |
739 | break; | |
740 | case CS6: | |
741 | cval = UART_LCR_WLEN6; | |
742 | break; | |
743 | case CS7: | |
744 | cval = UART_LCR_WLEN7; | |
745 | break; | |
746 | default: | |
747 | case CS8: | |
748 | cval = UART_LCR_WLEN8; | |
749 | break; | |
750 | } | |
751 | ||
752 | if (termios->c_cflag & CSTOPB) | |
753 | cval |= UART_LCR_STOP; | |
754 | if (termios->c_cflag & PARENB) | |
755 | cval |= UART_LCR_PARITY; | |
756 | if (!(termios->c_cflag & PARODD)) | |
757 | cval |= UART_LCR_EPAR; | |
758 | ||
759 | /* | |
760 | * Ask the core to calculate the divisor for us. | |
761 | */ | |
762 | ||
763 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); | |
764 | quot = serial_omap_get_divisor(port, baud); | |
765 | ||
2fd14964 | 766 | /* calculate wakeup latency constraint */ |
19723452 | 767 | up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); |
2fd14964 G |
768 | up->latency = up->calc_latency; |
769 | schedule_work(&up->qos_work); | |
770 | ||
c538d20c G |
771 | up->dll = quot & 0xff; |
772 | up->dlh = quot >> 8; | |
773 | up->mdr1 = UART_OMAP_MDR1_DISABLE; | |
774 | ||
b612633b G |
775 | up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | |
776 | UART_FCR_ENABLE_FIFO; | |
b612633b G |
777 | |
778 | /* | |
779 | * Ok, we're now changing the port state. Do it with | |
780 | * interrupts disabled. | |
781 | */ | |
d8ee4ea6 | 782 | pm_runtime_get_sync(up->dev); |
b612633b G |
783 | spin_lock_irqsave(&up->port.lock, flags); |
784 | ||
785 | /* | |
786 | * Update the per-port timeout. | |
787 | */ | |
788 | uart_update_timeout(port, termios->c_cflag, baud); | |
789 | ||
790 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
791 | if (termios->c_iflag & INPCK) | |
792 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
793 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
794 | up->port.read_status_mask |= UART_LSR_BI; | |
795 | ||
796 | /* | |
797 | * Characters to ignore | |
798 | */ | |
799 | up->port.ignore_status_mask = 0; | |
800 | if (termios->c_iflag & IGNPAR) | |
801 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
802 | if (termios->c_iflag & IGNBRK) { | |
803 | up->port.ignore_status_mask |= UART_LSR_BI; | |
804 | /* | |
805 | * If we're ignoring parity and break indicators, | |
806 | * ignore overruns too (for real raw support). | |
807 | */ | |
808 | if (termios->c_iflag & IGNPAR) | |
809 | up->port.ignore_status_mask |= UART_LSR_OE; | |
810 | } | |
811 | ||
812 | /* | |
813 | * ignore all characters if CREAD is not set | |
814 | */ | |
815 | if ((termios->c_cflag & CREAD) == 0) | |
816 | up->port.ignore_status_mask |= UART_LSR_DR; | |
817 | ||
818 | /* | |
819 | * Modem status interrupts | |
820 | */ | |
821 | up->ier &= ~UART_IER_MSI; | |
822 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
823 | up->ier |= UART_IER_MSI; | |
824 | serial_out(up, UART_IER, up->ier); | |
825 | serial_out(up, UART_LCR, cval); /* reset DLAB */ | |
c538d20c | 826 | up->lcr = cval; |
32212897 | 827 | up->scr = OMAP_UART_SCR_TX_EMPTY; |
b612633b G |
828 | |
829 | /* FIFOs and DMA Settings */ | |
830 | ||
831 | /* FCR can be changed only when the | |
832 | * baud clock is not running | |
833 | * DLL_REG and DLH_REG set to 0. | |
834 | */ | |
662b083a | 835 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
836 | serial_out(up, UART_DLL, 0); |
837 | serial_out(up, UART_DLM, 0); | |
838 | serial_out(up, UART_LCR, 0); | |
839 | ||
662b083a | 840 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
841 | |
842 | up->efr = serial_in(up, UART_EFR); | |
d864c03b | 843 | up->efr &= ~UART_EFR_SCD; |
b612633b G |
844 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); |
845 | ||
662b083a | 846 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
847 | up->mcr = serial_in(up, UART_MCR); |
848 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); | |
849 | /* FIFO ENABLE, DMA MODE */ | |
0ba5f668 PW |
850 | |
851 | up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; | |
b612633b | 852 | |
6721ab7f FB |
853 | /* Set receive FIFO threshold to 16 characters and |
854 | * transmit FIFO threshold to 16 spaces | |
855 | */ | |
49457430 | 856 | up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; |
6721ab7f FB |
857 | up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; |
858 | up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | | |
859 | UART_FCR_ENABLE_FIFO; | |
b612633b | 860 | |
0ba5f668 PW |
861 | serial_out(up, UART_FCR, up->fcr); |
862 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
863 | ||
c538d20c G |
864 | serial_out(up, UART_OMAP_SCR, up->scr); |
865 | ||
b612633b | 866 | serial_out(up, UART_EFR, up->efr); |
662b083a | 867 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
868 | serial_out(up, UART_MCR, up->mcr); |
869 | ||
870 | /* Protocol, Baud Rate, and Interrupt Settings */ | |
871 | ||
94734749 G |
872 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
873 | serial_omap_mdr1_errataset(up, up->mdr1); | |
874 | else | |
875 | serial_out(up, UART_OMAP_MDR1, up->mdr1); | |
876 | ||
662b083a | 877 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
878 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); |
879 | ||
880 | serial_out(up, UART_LCR, 0); | |
881 | serial_out(up, UART_IER, 0); | |
662b083a | 882 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b | 883 | |
c538d20c G |
884 | serial_out(up, UART_DLL, up->dll); /* LS of divisor */ |
885 | serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ | |
b612633b G |
886 | |
887 | serial_out(up, UART_LCR, 0); | |
888 | serial_out(up, UART_IER, up->ier); | |
662b083a | 889 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
890 | |
891 | serial_out(up, UART_EFR, up->efr); | |
892 | serial_out(up, UART_LCR, cval); | |
893 | ||
894 | if (baud > 230400 && baud != 3000000) | |
c538d20c | 895 | up->mdr1 = UART_OMAP_MDR1_13X_MODE; |
b612633b | 896 | else |
c538d20c G |
897 | up->mdr1 = UART_OMAP_MDR1_16X_MODE; |
898 | ||
94734749 G |
899 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
900 | serial_omap_mdr1_errataset(up, up->mdr1); | |
901 | else | |
902 | serial_out(up, UART_OMAP_MDR1, up->mdr1); | |
b612633b G |
903 | |
904 | /* Hardware Flow Control Configuration */ | |
905 | ||
906 | if (termios->c_cflag & CRTSCTS) { | |
907 | efr |= (UART_EFR_CTS | UART_EFR_RTS); | |
662b083a | 908 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
909 | |
910 | up->mcr = serial_in(up, UART_MCR); | |
911 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); | |
912 | ||
662b083a | 913 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
914 | up->efr = serial_in(up, UART_EFR); |
915 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); | |
916 | ||
917 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); | |
918 | serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */ | |
662b083a | 919 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
920 | serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS); |
921 | serial_out(up, UART_LCR, cval); | |
0d5b1663 RK |
922 | } else { |
923 | /* Disable AUTORTS and AUTOCTS */ | |
924 | up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); | |
925 | ||
926 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
927 | serial_out(up, UART_EFR, up->efr); | |
928 | serial_out(up, UART_LCR, cval); | |
b612633b G |
929 | } |
930 | ||
931 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
932 | /* Software Flow Control Configuration */ | |
b280a97d | 933 | serial_omap_configure_xonxoff(up, termios); |
b612633b G |
934 | |
935 | spin_unlock_irqrestore(&up->port.lock, flags); | |
660ac5f4 FB |
936 | pm_runtime_mark_last_busy(up->dev); |
937 | pm_runtime_put_autosuspend(up->dev); | |
ba77433d | 938 | dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); |
b612633b G |
939 | } |
940 | ||
9727faf4 FB |
941 | static int serial_omap_set_wake(struct uart_port *port, unsigned int state) |
942 | { | |
943 | struct uart_omap_port *up = to_uart_omap_port(port); | |
944 | ||
945 | serial_omap_enable_wakeup(up, state); | |
946 | ||
947 | return 0; | |
948 | } | |
949 | ||
b612633b G |
950 | static void |
951 | serial_omap_pm(struct uart_port *port, unsigned int state, | |
952 | unsigned int oldstate) | |
953 | { | |
c990f351 | 954 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
955 | unsigned char efr; |
956 | ||
ba77433d | 957 | dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); |
fcdca757 | 958 | |
d8ee4ea6 | 959 | pm_runtime_get_sync(up->dev); |
662b083a | 960 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
961 | efr = serial_in(up, UART_EFR); |
962 | serial_out(up, UART_EFR, efr | UART_EFR_ECB); | |
963 | serial_out(up, UART_LCR, 0); | |
964 | ||
965 | serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); | |
662b083a | 966 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
967 | serial_out(up, UART_EFR, efr); |
968 | serial_out(up, UART_LCR, 0); | |
fcdca757 | 969 | |
d8ee4ea6 | 970 | if (!device_may_wakeup(up->dev)) { |
fcdca757 | 971 | if (!state) |
d8ee4ea6 | 972 | pm_runtime_forbid(up->dev); |
fcdca757 | 973 | else |
d8ee4ea6 | 974 | pm_runtime_allow(up->dev); |
fcdca757 G |
975 | } |
976 | ||
660ac5f4 FB |
977 | pm_runtime_mark_last_busy(up->dev); |
978 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
979 | } |
980 | ||
981 | static void serial_omap_release_port(struct uart_port *port) | |
982 | { | |
983 | dev_dbg(port->dev, "serial_omap_release_port+\n"); | |
984 | } | |
985 | ||
986 | static int serial_omap_request_port(struct uart_port *port) | |
987 | { | |
988 | dev_dbg(port->dev, "serial_omap_request_port+\n"); | |
989 | return 0; | |
990 | } | |
991 | ||
992 | static void serial_omap_config_port(struct uart_port *port, int flags) | |
993 | { | |
c990f351 | 994 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
995 | |
996 | dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", | |
ba77433d | 997 | up->port.line); |
b612633b G |
998 | up->port.type = PORT_OMAP; |
999 | } | |
1000 | ||
1001 | static int | |
1002 | serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1003 | { | |
1004 | /* we don't want the core code to modify any port params */ | |
1005 | dev_dbg(port->dev, "serial_omap_verify_port+\n"); | |
1006 | return -EINVAL; | |
1007 | } | |
1008 | ||
1009 | static const char * | |
1010 | serial_omap_type(struct uart_port *port) | |
1011 | { | |
c990f351 | 1012 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 1013 | |
ba77433d | 1014 | dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); |
b612633b G |
1015 | return up->name; |
1016 | } | |
1017 | ||
b612633b G |
1018 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
1019 | ||
1020 | static inline void wait_for_xmitr(struct uart_omap_port *up) | |
1021 | { | |
1022 | unsigned int status, tmout = 10000; | |
1023 | ||
1024 | /* Wait up to 10ms for the character(s) to be sent. */ | |
1025 | do { | |
1026 | status = serial_in(up, UART_LSR); | |
1027 | ||
1028 | if (status & UART_LSR_BI) | |
1029 | up->lsr_break_flag = UART_LSR_BI; | |
1030 | ||
1031 | if (--tmout == 0) | |
1032 | break; | |
1033 | udelay(1); | |
1034 | } while ((status & BOTH_EMPTY) != BOTH_EMPTY); | |
1035 | ||
1036 | /* Wait up to 1s for flow control if necessary */ | |
1037 | if (up->port.flags & UPF_CONS_FLOW) { | |
1038 | tmout = 1000000; | |
1039 | for (tmout = 1000000; tmout; tmout--) { | |
1040 | unsigned int msr = serial_in(up, UART_MSR); | |
1041 | ||
1042 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; | |
1043 | if (msr & UART_MSR_CTS) | |
1044 | break; | |
1045 | ||
1046 | udelay(1); | |
1047 | } | |
1048 | } | |
1049 | } | |
1050 | ||
1b41dbc1 CC |
1051 | #ifdef CONFIG_CONSOLE_POLL |
1052 | ||
1053 | static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) | |
1054 | { | |
c990f351 | 1055 | struct uart_omap_port *up = to_uart_omap_port(port); |
fcdca757 | 1056 | |
d8ee4ea6 | 1057 | pm_runtime_get_sync(up->dev); |
1b41dbc1 CC |
1058 | wait_for_xmitr(up); |
1059 | serial_out(up, UART_TX, ch); | |
660ac5f4 FB |
1060 | pm_runtime_mark_last_busy(up->dev); |
1061 | pm_runtime_put_autosuspend(up->dev); | |
1b41dbc1 CC |
1062 | } |
1063 | ||
1064 | static int serial_omap_poll_get_char(struct uart_port *port) | |
1065 | { | |
c990f351 | 1066 | struct uart_omap_port *up = to_uart_omap_port(port); |
fcdca757 | 1067 | unsigned int status; |
1b41dbc1 | 1068 | |
d8ee4ea6 | 1069 | pm_runtime_get_sync(up->dev); |
fcdca757 | 1070 | status = serial_in(up, UART_LSR); |
a6b19c33 FB |
1071 | if (!(status & UART_LSR_DR)) { |
1072 | status = NO_POLL_CHAR; | |
1073 | goto out; | |
1074 | } | |
1b41dbc1 | 1075 | |
fcdca757 | 1076 | status = serial_in(up, UART_RX); |
a6b19c33 FB |
1077 | |
1078 | out: | |
660ac5f4 FB |
1079 | pm_runtime_mark_last_busy(up->dev); |
1080 | pm_runtime_put_autosuspend(up->dev); | |
a6b19c33 | 1081 | |
fcdca757 | 1082 | return status; |
1b41dbc1 CC |
1083 | } |
1084 | ||
1085 | #endif /* CONFIG_CONSOLE_POLL */ | |
1086 | ||
1087 | #ifdef CONFIG_SERIAL_OMAP_CONSOLE | |
1088 | ||
1089 | static struct uart_omap_port *serial_omap_console_ports[4]; | |
1090 | ||
1091 | static struct uart_driver serial_omap_reg; | |
1092 | ||
b612633b G |
1093 | static void serial_omap_console_putchar(struct uart_port *port, int ch) |
1094 | { | |
c990f351 | 1095 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
1096 | |
1097 | wait_for_xmitr(up); | |
1098 | serial_out(up, UART_TX, ch); | |
1099 | } | |
1100 | ||
1101 | static void | |
1102 | serial_omap_console_write(struct console *co, const char *s, | |
1103 | unsigned int count) | |
1104 | { | |
1105 | struct uart_omap_port *up = serial_omap_console_ports[co->index]; | |
1106 | unsigned long flags; | |
1107 | unsigned int ier; | |
1108 | int locked = 1; | |
1109 | ||
d8ee4ea6 | 1110 | pm_runtime_get_sync(up->dev); |
fcdca757 | 1111 | |
b612633b G |
1112 | local_irq_save(flags); |
1113 | if (up->port.sysrq) | |
1114 | locked = 0; | |
1115 | else if (oops_in_progress) | |
1116 | locked = spin_trylock(&up->port.lock); | |
1117 | else | |
1118 | spin_lock(&up->port.lock); | |
1119 | ||
1120 | /* | |
1121 | * First save the IER then disable the interrupts | |
1122 | */ | |
1123 | ier = serial_in(up, UART_IER); | |
1124 | serial_out(up, UART_IER, 0); | |
1125 | ||
1126 | uart_console_write(&up->port, s, count, serial_omap_console_putchar); | |
1127 | ||
1128 | /* | |
1129 | * Finally, wait for transmitter to become empty | |
1130 | * and restore the IER | |
1131 | */ | |
1132 | wait_for_xmitr(up); | |
1133 | serial_out(up, UART_IER, ier); | |
1134 | /* | |
1135 | * The receive handling will happen properly because the | |
1136 | * receive ready bit will still be set; it is not cleared | |
1137 | * on read. However, modem control will not, we must | |
1138 | * call it if we have saved something in the saved flags | |
1139 | * while processing with interrupts off. | |
1140 | */ | |
1141 | if (up->msr_saved_flags) | |
1142 | check_modem_status(up); | |
1143 | ||
d8ee4ea6 FB |
1144 | pm_runtime_mark_last_busy(up->dev); |
1145 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
1146 | if (locked) |
1147 | spin_unlock(&up->port.lock); | |
1148 | local_irq_restore(flags); | |
1149 | } | |
1150 | ||
1151 | static int __init | |
1152 | serial_omap_console_setup(struct console *co, char *options) | |
1153 | { | |
1154 | struct uart_omap_port *up; | |
1155 | int baud = 115200; | |
1156 | int bits = 8; | |
1157 | int parity = 'n'; | |
1158 | int flow = 'n'; | |
1159 | ||
1160 | if (serial_omap_console_ports[co->index] == NULL) | |
1161 | return -ENODEV; | |
1162 | up = serial_omap_console_ports[co->index]; | |
1163 | ||
1164 | if (options) | |
1165 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1166 | ||
1167 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
1168 | } | |
1169 | ||
1170 | static struct console serial_omap_console = { | |
1171 | .name = OMAP_SERIAL_NAME, | |
1172 | .write = serial_omap_console_write, | |
1173 | .device = uart_console_device, | |
1174 | .setup = serial_omap_console_setup, | |
1175 | .flags = CON_PRINTBUFFER, | |
1176 | .index = -1, | |
1177 | .data = &serial_omap_reg, | |
1178 | }; | |
1179 | ||
1180 | static void serial_omap_add_console_port(struct uart_omap_port *up) | |
1181 | { | |
ba77433d | 1182 | serial_omap_console_ports[up->port.line] = up; |
b612633b G |
1183 | } |
1184 | ||
1185 | #define OMAP_CONSOLE (&serial_omap_console) | |
1186 | ||
1187 | #else | |
1188 | ||
1189 | #define OMAP_CONSOLE NULL | |
1190 | ||
1191 | static inline void serial_omap_add_console_port(struct uart_omap_port *up) | |
1192 | {} | |
1193 | ||
1194 | #endif | |
1195 | ||
1196 | static struct uart_ops serial_omap_pops = { | |
1197 | .tx_empty = serial_omap_tx_empty, | |
1198 | .set_mctrl = serial_omap_set_mctrl, | |
1199 | .get_mctrl = serial_omap_get_mctrl, | |
1200 | .stop_tx = serial_omap_stop_tx, | |
1201 | .start_tx = serial_omap_start_tx, | |
1202 | .stop_rx = serial_omap_stop_rx, | |
1203 | .enable_ms = serial_omap_enable_ms, | |
1204 | .break_ctl = serial_omap_break_ctl, | |
1205 | .startup = serial_omap_startup, | |
1206 | .shutdown = serial_omap_shutdown, | |
1207 | .set_termios = serial_omap_set_termios, | |
1208 | .pm = serial_omap_pm, | |
9727faf4 | 1209 | .set_wake = serial_omap_set_wake, |
b612633b G |
1210 | .type = serial_omap_type, |
1211 | .release_port = serial_omap_release_port, | |
1212 | .request_port = serial_omap_request_port, | |
1213 | .config_port = serial_omap_config_port, | |
1214 | .verify_port = serial_omap_verify_port, | |
1b41dbc1 CC |
1215 | #ifdef CONFIG_CONSOLE_POLL |
1216 | .poll_put_char = serial_omap_poll_put_char, | |
1217 | .poll_get_char = serial_omap_poll_get_char, | |
1218 | #endif | |
b612633b G |
1219 | }; |
1220 | ||
1221 | static struct uart_driver serial_omap_reg = { | |
1222 | .owner = THIS_MODULE, | |
1223 | .driver_name = "OMAP-SERIAL", | |
1224 | .dev_name = OMAP_SERIAL_NAME, | |
1225 | .nr = OMAP_MAX_HSUART_PORTS, | |
1226 | .cons = OMAP_CONSOLE, | |
1227 | }; | |
1228 | ||
3bc4f0d8 | 1229 | #ifdef CONFIG_PM_SLEEP |
fcdca757 | 1230 | static int serial_omap_suspend(struct device *dev) |
b612633b | 1231 | { |
fcdca757 | 1232 | struct uart_omap_port *up = dev_get_drvdata(dev); |
b612633b | 1233 | |
ac57e7f3 | 1234 | uart_suspend_port(&serial_omap_reg, &up->port); |
033d9959 | 1235 | flush_work(&up->qos_work); |
2fd14964 | 1236 | |
b612633b G |
1237 | return 0; |
1238 | } | |
1239 | ||
fcdca757 | 1240 | static int serial_omap_resume(struct device *dev) |
b612633b | 1241 | { |
fcdca757 | 1242 | struct uart_omap_port *up = dev_get_drvdata(dev); |
b612633b | 1243 | |
ac57e7f3 SP |
1244 | uart_resume_port(&serial_omap_reg, &up->port); |
1245 | ||
b612633b G |
1246 | return 0; |
1247 | } | |
fcdca757 | 1248 | #endif |
b612633b | 1249 | |
6d608ef3 | 1250 | static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up) |
7c77c8de G |
1251 | { |
1252 | u32 mvr, scheme; | |
1253 | u16 revision, major, minor; | |
1254 | ||
1255 | mvr = serial_in(up, UART_OMAP_MVER); | |
1256 | ||
1257 | /* Check revision register scheme */ | |
1258 | scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; | |
1259 | ||
1260 | switch (scheme) { | |
1261 | case 0: /* Legacy Scheme: OMAP2/3 */ | |
1262 | /* MINOR_REV[0:4], MAJOR_REV[4:7] */ | |
1263 | major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> | |
1264 | OMAP_UART_LEGACY_MVR_MAJ_SHIFT; | |
1265 | minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); | |
1266 | break; | |
1267 | case 1: | |
1268 | /* New Scheme: OMAP4+ */ | |
1269 | /* MINOR_REV[0:5], MAJOR_REV[8:10] */ | |
1270 | major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> | |
1271 | OMAP_UART_MVR_MAJ_SHIFT; | |
1272 | minor = (mvr & OMAP_UART_MVR_MIN_MASK); | |
1273 | break; | |
1274 | default: | |
d8ee4ea6 | 1275 | dev_warn(up->dev, |
7c77c8de G |
1276 | "Unknown %s revision, defaulting to highest\n", |
1277 | up->name); | |
1278 | /* highest possible revision */ | |
1279 | major = 0xff; | |
1280 | minor = 0xff; | |
1281 | } | |
1282 | ||
1283 | /* normalize revision for the driver */ | |
1284 | revision = UART_BUILD_REVISION(major, minor); | |
1285 | ||
1286 | switch (revision) { | |
1287 | case OMAP_UART_REV_46: | |
1288 | up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | | |
1289 | UART_ERRATA_i291_DMA_FORCEIDLE); | |
1290 | break; | |
1291 | case OMAP_UART_REV_52: | |
1292 | up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | | |
1293 | UART_ERRATA_i291_DMA_FORCEIDLE); | |
1294 | break; | |
1295 | case OMAP_UART_REV_63: | |
1296 | up->errata |= UART_ERRATA_i202_MDR1_ACCESS; | |
1297 | break; | |
1298 | default: | |
1299 | break; | |
1300 | } | |
1301 | } | |
1302 | ||
6d608ef3 | 1303 | static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) |
d92b0dfc RN |
1304 | { |
1305 | struct omap_uart_port_info *omap_up_info; | |
1306 | ||
1307 | omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); | |
1308 | if (!omap_up_info) | |
1309 | return NULL; /* out of memory */ | |
1310 | ||
1311 | of_property_read_u32(dev->of_node, "clock-frequency", | |
1312 | &omap_up_info->uartclk); | |
1313 | return omap_up_info; | |
1314 | } | |
1315 | ||
6d608ef3 | 1316 | static int __devinit serial_omap_probe(struct platform_device *pdev) |
b612633b G |
1317 | { |
1318 | struct uart_omap_port *up; | |
49457430 | 1319 | struct resource *mem, *irq; |
b612633b | 1320 | struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; |
9574f36f | 1321 | int ret; |
b612633b | 1322 | |
d92b0dfc RN |
1323 | if (pdev->dev.of_node) |
1324 | omap_up_info = of_get_uart_port_info(&pdev->dev); | |
1325 | ||
b612633b G |
1326 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1327 | if (!mem) { | |
1328 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1329 | return -ENODEV; | |
1330 | } | |
1331 | ||
1332 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1333 | if (!irq) { | |
1334 | dev_err(&pdev->dev, "no irq resource?\n"); | |
1335 | return -ENODEV; | |
1336 | } | |
1337 | ||
388bc262 | 1338 | if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem), |
28f65c11 | 1339 | pdev->dev.driver->name)) { |
b612633b G |
1340 | dev_err(&pdev->dev, "memory region already claimed\n"); |
1341 | return -EBUSY; | |
1342 | } | |
1343 | ||
9574f36f N |
1344 | if (gpio_is_valid(omap_up_info->DTR_gpio) && |
1345 | omap_up_info->DTR_present) { | |
1346 | ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial"); | |
1347 | if (ret < 0) | |
1348 | return ret; | |
1349 | ret = gpio_direction_output(omap_up_info->DTR_gpio, | |
1350 | omap_up_info->DTR_inverted); | |
1351 | if (ret < 0) | |
1352 | return ret; | |
1353 | } | |
1354 | ||
388bc262 S |
1355 | up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); |
1356 | if (!up) | |
1357 | return -ENOMEM; | |
b612633b | 1358 | |
9574f36f N |
1359 | if (gpio_is_valid(omap_up_info->DTR_gpio) && |
1360 | omap_up_info->DTR_present) { | |
1361 | up->DTR_gpio = omap_up_info->DTR_gpio; | |
1362 | up->DTR_inverted = omap_up_info->DTR_inverted; | |
1363 | } else | |
1364 | up->DTR_gpio = -EINVAL; | |
1365 | up->DTR_active = 0; | |
1366 | ||
d8ee4ea6 | 1367 | up->dev = &pdev->dev; |
b612633b G |
1368 | up->port.dev = &pdev->dev; |
1369 | up->port.type = PORT_OMAP; | |
1370 | up->port.iotype = UPIO_MEM; | |
1371 | up->port.irq = irq->start; | |
1372 | ||
1373 | up->port.regshift = 2; | |
1374 | up->port.fifosize = 64; | |
1375 | up->port.ops = &serial_omap_pops; | |
b612633b | 1376 | |
d92b0dfc RN |
1377 | if (pdev->dev.of_node) |
1378 | up->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); | |
1379 | else | |
1380 | up->port.line = pdev->id; | |
1381 | ||
1382 | if (up->port.line < 0) { | |
1383 | dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", | |
1384 | up->port.line); | |
1385 | ret = -ENODEV; | |
388bc262 | 1386 | goto err_port_line; |
d92b0dfc RN |
1387 | } |
1388 | ||
3dbc5ce2 TL |
1389 | up->pins = devm_pinctrl_get_select_default(&pdev->dev); |
1390 | if (IS_ERR(up->pins)) { | |
1391 | dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n", | |
1392 | up->port.line, PTR_ERR(up->pins)); | |
1393 | up->pins = NULL; | |
1394 | } | |
1395 | ||
d92b0dfc | 1396 | sprintf(up->name, "OMAP UART%d", up->port.line); |
edd70ad7 | 1397 | up->port.mapbase = mem->start; |
388bc262 S |
1398 | up->port.membase = devm_ioremap(&pdev->dev, mem->start, |
1399 | resource_size(mem)); | |
edd70ad7 G |
1400 | if (!up->port.membase) { |
1401 | dev_err(&pdev->dev, "can't ioremap UART\n"); | |
1402 | ret = -ENOMEM; | |
388bc262 | 1403 | goto err_ioremap; |
edd70ad7 G |
1404 | } |
1405 | ||
b612633b | 1406 | up->port.flags = omap_up_info->flags; |
b612633b | 1407 | up->port.uartclk = omap_up_info->uartclk; |
8fe789dc RN |
1408 | if (!up->port.uartclk) { |
1409 | up->port.uartclk = DEFAULT_CLK_SPEED; | |
1410 | dev_warn(&pdev->dev, "No clock speed specified: using default:" | |
1411 | "%d\n", DEFAULT_CLK_SPEED); | |
1412 | } | |
b612633b | 1413 | |
2fd14964 G |
1414 | up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
1415 | up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; | |
1416 | pm_qos_add_request(&up->pm_qos_request, | |
1417 | PM_QOS_CPU_DMA_LATENCY, up->latency); | |
1418 | serial_omap_uart_wq = create_singlethread_workqueue(up->name); | |
1419 | INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); | |
1420 | ||
93220dcc | 1421 | platform_set_drvdata(pdev, up); |
856e35bf | 1422 | pm_runtime_enable(&pdev->dev); |
fcdca757 G |
1423 | pm_runtime_use_autosuspend(&pdev->dev); |
1424 | pm_runtime_set_autosuspend_delay(&pdev->dev, | |
c86845db | 1425 | omap_up_info->autosuspend_timeout); |
fcdca757 G |
1426 | |
1427 | pm_runtime_irq_safe(&pdev->dev); | |
fcdca757 G |
1428 | pm_runtime_get_sync(&pdev->dev); |
1429 | ||
7c77c8de G |
1430 | omap_serial_fill_features_erratas(up); |
1431 | ||
ba77433d | 1432 | ui[up->port.line] = up; |
b612633b G |
1433 | serial_omap_add_console_port(up); |
1434 | ||
1435 | ret = uart_add_one_port(&serial_omap_reg, &up->port); | |
1436 | if (ret != 0) | |
388bc262 | 1437 | goto err_add_port; |
b612633b | 1438 | |
660ac5f4 FB |
1439 | pm_runtime_mark_last_busy(up->dev); |
1440 | pm_runtime_put_autosuspend(up->dev); | |
b612633b | 1441 | return 0; |
388bc262 S |
1442 | |
1443 | err_add_port: | |
1444 | pm_runtime_put(&pdev->dev); | |
1445 | pm_runtime_disable(&pdev->dev); | |
1446 | err_ioremap: | |
1447 | err_port_line: | |
b612633b G |
1448 | dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", |
1449 | pdev->id, __func__, ret); | |
b612633b G |
1450 | return ret; |
1451 | } | |
1452 | ||
6d608ef3 | 1453 | static int __devexit serial_omap_remove(struct platform_device *dev) |
b612633b G |
1454 | { |
1455 | struct uart_omap_port *up = platform_get_drvdata(dev); | |
1456 | ||
7e9c8e7d | 1457 | pm_runtime_put_sync(up->dev); |
1b42c8b2 FB |
1458 | pm_runtime_disable(up->dev); |
1459 | uart_remove_one_port(&serial_omap_reg, &up->port); | |
1460 | pm_qos_remove_request(&up->pm_qos_request); | |
fcdca757 | 1461 | |
fcdca757 G |
1462 | return 0; |
1463 | } | |
1464 | ||
94734749 G |
1465 | /* |
1466 | * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) | |
1467 | * The access to uart register after MDR1 Access | |
1468 | * causes UART to corrupt data. | |
1469 | * | |
1470 | * Need a delay = | |
1471 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) | |
1472 | * give 10 times as much | |
1473 | */ | |
1474 | static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) | |
1475 | { | |
1476 | u8 timeout = 255; | |
1477 | ||
1478 | serial_out(up, UART_OMAP_MDR1, mdr1); | |
1479 | udelay(2); | |
1480 | serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | | |
1481 | UART_FCR_CLEAR_RCVR); | |
1482 | /* | |
1483 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and | |
1484 | * TX_FIFO_E bit is 1. | |
1485 | */ | |
1486 | while (UART_LSR_THRE != (serial_in(up, UART_LSR) & | |
1487 | (UART_LSR_THRE | UART_LSR_DR))) { | |
1488 | timeout--; | |
1489 | if (!timeout) { | |
1490 | /* Should *never* happen. we warn and carry on */ | |
d8ee4ea6 | 1491 | dev_crit(up->dev, "Errata i202: timedout %x\n", |
94734749 G |
1492 | serial_in(up, UART_LSR)); |
1493 | break; | |
1494 | } | |
1495 | udelay(1); | |
1496 | } | |
1497 | } | |
1498 | ||
b5148856 | 1499 | #ifdef CONFIG_PM_RUNTIME |
9f9ac1e8 G |
1500 | static void serial_omap_restore_context(struct uart_omap_port *up) |
1501 | { | |
94734749 G |
1502 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
1503 | serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); | |
1504 | else | |
1505 | serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); | |
1506 | ||
9f9ac1e8 G |
1507 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ |
1508 | serial_out(up, UART_EFR, UART_EFR_ECB); | |
1509 | serial_out(up, UART_LCR, 0x0); /* Operational mode */ | |
1510 | serial_out(up, UART_IER, 0x0); | |
1511 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ | |
c538d20c G |
1512 | serial_out(up, UART_DLL, up->dll); |
1513 | serial_out(up, UART_DLM, up->dlh); | |
9f9ac1e8 G |
1514 | serial_out(up, UART_LCR, 0x0); /* Operational mode */ |
1515 | serial_out(up, UART_IER, up->ier); | |
1516 | serial_out(up, UART_FCR, up->fcr); | |
1517 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
1518 | serial_out(up, UART_MCR, up->mcr); | |
1519 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ | |
c538d20c | 1520 | serial_out(up, UART_OMAP_SCR, up->scr); |
9f9ac1e8 G |
1521 | serial_out(up, UART_EFR, up->efr); |
1522 | serial_out(up, UART_LCR, up->lcr); | |
94734749 G |
1523 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
1524 | serial_omap_mdr1_errataset(up, up->mdr1); | |
1525 | else | |
1526 | serial_out(up, UART_OMAP_MDR1, up->mdr1); | |
9f9ac1e8 G |
1527 | } |
1528 | ||
fcdca757 G |
1529 | static int serial_omap_runtime_suspend(struct device *dev) |
1530 | { | |
ec3bebc6 G |
1531 | struct uart_omap_port *up = dev_get_drvdata(dev); |
1532 | struct omap_uart_port_info *pdata = dev->platform_data; | |
1533 | ||
1534 | if (!up) | |
1535 | return -EINVAL; | |
1536 | ||
e5b57c03 | 1537 | if (!pdata) |
62f3ec5f G |
1538 | return 0; |
1539 | ||
e5b57c03 | 1540 | up->context_loss_cnt = serial_omap_get_context_loss_count(up); |
ec3bebc6 | 1541 | |
62f3ec5f G |
1542 | if (device_may_wakeup(dev)) { |
1543 | if (!up->wakeups_enabled) { | |
e5b57c03 | 1544 | serial_omap_enable_wakeup(up, true); |
62f3ec5f G |
1545 | up->wakeups_enabled = true; |
1546 | } | |
1547 | } else { | |
1548 | if (up->wakeups_enabled) { | |
e5b57c03 | 1549 | serial_omap_enable_wakeup(up, false); |
62f3ec5f G |
1550 | up->wakeups_enabled = false; |
1551 | } | |
1552 | } | |
1553 | ||
2fd14964 G |
1554 | up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
1555 | schedule_work(&up->qos_work); | |
1556 | ||
b612633b G |
1557 | return 0; |
1558 | } | |
1559 | ||
fcdca757 G |
1560 | static int serial_omap_runtime_resume(struct device *dev) |
1561 | { | |
9f9ac1e8 G |
1562 | struct uart_omap_port *up = dev_get_drvdata(dev); |
1563 | ||
ac57e7f3 | 1564 | u32 loss_cnt = serial_omap_get_context_loss_count(up); |
ec3bebc6 | 1565 | |
ac57e7f3 SP |
1566 | if (up->context_loss_cnt != loss_cnt) |
1567 | serial_omap_restore_context(up); | |
94734749 | 1568 | |
ac57e7f3 SP |
1569 | up->latency = up->calc_latency; |
1570 | schedule_work(&up->qos_work); | |
9f9ac1e8 | 1571 | |
b612633b G |
1572 | return 0; |
1573 | } | |
fcdca757 G |
1574 | #endif |
1575 | ||
1576 | static const struct dev_pm_ops serial_omap_dev_pm_ops = { | |
1577 | SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) | |
1578 | SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, | |
1579 | serial_omap_runtime_resume, NULL) | |
1580 | }; | |
1581 | ||
d92b0dfc RN |
1582 | #if defined(CONFIG_OF) |
1583 | static const struct of_device_id omap_serial_of_match[] = { | |
1584 | { .compatible = "ti,omap2-uart" }, | |
1585 | { .compatible = "ti,omap3-uart" }, | |
1586 | { .compatible = "ti,omap4-uart" }, | |
1587 | {}, | |
1588 | }; | |
1589 | MODULE_DEVICE_TABLE(of, omap_serial_of_match); | |
1590 | #endif | |
b612633b G |
1591 | |
1592 | static struct platform_driver serial_omap_driver = { | |
1593 | .probe = serial_omap_probe, | |
6d608ef3 | 1594 | .remove = __devexit_p(serial_omap_remove), |
b612633b G |
1595 | .driver = { |
1596 | .name = DRIVER_NAME, | |
fcdca757 | 1597 | .pm = &serial_omap_dev_pm_ops, |
d92b0dfc | 1598 | .of_match_table = of_match_ptr(omap_serial_of_match), |
b612633b G |
1599 | }, |
1600 | }; | |
1601 | ||
1602 | static int __init serial_omap_init(void) | |
1603 | { | |
1604 | int ret; | |
1605 | ||
1606 | ret = uart_register_driver(&serial_omap_reg); | |
1607 | if (ret != 0) | |
1608 | return ret; | |
1609 | ret = platform_driver_register(&serial_omap_driver); | |
1610 | if (ret != 0) | |
1611 | uart_unregister_driver(&serial_omap_reg); | |
1612 | return ret; | |
1613 | } | |
1614 | ||
1615 | static void __exit serial_omap_exit(void) | |
1616 | { | |
1617 | platform_driver_unregister(&serial_omap_driver); | |
1618 | uart_unregister_driver(&serial_omap_reg); | |
1619 | } | |
1620 | ||
1621 | module_init(serial_omap_init); | |
1622 | module_exit(serial_omap_exit); | |
1623 | ||
1624 | MODULE_DESCRIPTION("OMAP High Speed UART driver"); | |
1625 | MODULE_LICENSE("GPL"); | |
1626 | MODULE_AUTHOR("Texas Instruments Inc"); |