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b612633b
G		 1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
25985edc 16 * Note: This driver is made separate from 8250 driver as we cannot
b612633b
G		 17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
364a6ece
TW		 23#if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
b612633b
G		 27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/serial_reg.h>
31#include <linux/delay.h>
32#include <linux/slab.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
d21e4005 35#include <linux/platform_device.h>
b612633b 36#include <linux/io.h>
b612633b
G		 37#include <linux/clk.h>
38#include <linux/serial_core.h>
39#include <linux/irq.h>
fcdca757 40#include <linux/pm_runtime.h>
d92b0dfc 41#include <linux/of.h>
9574f36f 42#include <linux/gpio.h>
d9ba5737 43#include <linux/platform_data/serial-omap.h>
b612633b 44
f91b55ab
RK		 45#define OMAP_MAX_HSUART_PORTS 6
46
7c77c8de
G		 47#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
48
49#define OMAP_UART_REV_42 0x0402
50#define OMAP_UART_REV_46 0x0406
51#define OMAP_UART_REV_52 0x0502
52#define OMAP_UART_REV_63 0x0603
53
f91b55ab
RK		 54#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
55#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
56
8fe789dc
RN		 57#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
58
0ba5f668
PW		 59/* SCR register bitmasks */
60#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
1776fd05 61#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
f91b55ab 62#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
0ba5f668
PW		 63
64/* FCR register bitmasks */
0ba5f668 65#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
6721ab7f 66#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
0ba5f668 67
7c77c8de
G		 68/* MVR register bitmasks */
69#define OMAP_UART_MVR_SCHEME_SHIFT 30
70
71#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
72#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
73#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
74
75#define OMAP_UART_MVR_MAJ_MASK 0x700
76#define OMAP_UART_MVR_MAJ_SHIFT 8
77#define OMAP_UART_MVR_MIN_MASK 0x3f
78
f91b55ab
RK		 79#define OMAP_UART_DMA_CH_FREE -1
80
81#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
82#define OMAP_MODE13X_SPEED 230400
83
84/* WER = 0x7F
85 * Enable module level wakeup in WER reg
86 */
87#define OMAP_UART_WER_MOD_WKUP 0X7F
88
89/* Enable XON/XOFF flow control on output */
3af08bd7 90#define OMAP_UART_SW_TX 0x08
f91b55ab
RK		 91
92/* Enable XON/XOFF flow control on input */
3af08bd7 93#define OMAP_UART_SW_RX 0x02
f91b55ab
RK		 94
95#define OMAP_UART_SW_CLR 0xF0
96
97#define OMAP_UART_TCR_TRIG 0x0F
98
99struct uart_omap_dma {
100 u8 uart_dma_tx;
101 u8 uart_dma_rx;
102 int rx_dma_channel;
103 int tx_dma_channel;
104 dma_addr_t rx_buf_dma_phys;
105 dma_addr_t tx_buf_dma_phys;
106 unsigned int uart_base;
107 /*
108 * Buffer for rx dma.It is not required for tx because the buffer
109 * comes from port structure.
110 */
111 unsigned char *rx_buf;
112 unsigned int prev_rx_dma_pos;
113 int tx_buf_size;
114 int tx_dma_used;
115 int rx_dma_used;
116 spinlock_t tx_lock;
117 spinlock_t rx_lock;
118 /* timer to poll activity on rx dma */
119 struct timer_list rx_timer;
120 unsigned int rx_buf_size;
121 unsigned int rx_poll_rate;
122 unsigned int rx_timeout;
123};
124
d37c6ceb
FB		 125struct uart_omap_port {
126 struct uart_port port;
127 struct uart_omap_dma uart_dma;
128 struct device *dev;
129
130 unsigned char ier;
131 unsigned char lcr;
132 unsigned char mcr;
133 unsigned char fcr;
134 unsigned char efr;
135 unsigned char dll;
136 unsigned char dlh;
137 unsigned char mdr1;
138 unsigned char scr;
139
140 int use_dma;
141 /*
142 * Some bits in registers are cleared on a read, so they must
143 * be saved whenever the register is read but the bits will not
144 * be immediately processed.
145 */
146 unsigned int lsr_break_flag;
147 unsigned char msr_saved_flags;
148 char name[20];
149 unsigned long port_activity;
39aee51d 150 int context_loss_cnt;
d37c6ceb
FB		 151 u32 errata;
152 u8 wakeups_enabled;
d37c6ceb 153
e36851d0
FB		 154 int DTR_gpio;
155 int DTR_inverted;
156 int DTR_active;
157
d37c6ceb
FB		 158 struct pm_qos_request pm_qos_request;
159 u32 latency;
160 u32 calc_latency;
161 struct work_struct qos_work;
ddd85e22 162 bool is_suspending;
d37c6ceb
FB		 163};
164
165#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
166
b612633b
G		 167static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
168
169/* Forward declaration of functions */
94734749 170static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
b612633b 171
2fd14964 172static struct workqueue_struct *serial_omap_uart_wq;
b612633b
G		 173
174static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
175{
176 offset <<= up->port.regshift;
177 return readw(up->port.membase + offset);
178}
179
180static inline void serial_out(struct uart_omap_port *up, int offset, int value)
181{
182 offset <<= up->port.regshift;
183 writew(value, up->port.membase + offset);
184}
185
186static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
187{
188 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
189 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
190 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
191 serial_out(up, UART_FCR, 0);
192}
193
e5b57c03
FB		 194static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
195{
d8ee4ea6 196 struct omap_uart_port_info *pdata = up->dev->platform_data;
e5b57c03 197
ce2f08de 198 if (!pdata || !pdata->get_context_loss_count)
a630fbfb 199 return -EINVAL;
e5b57c03 200
d8ee4ea6 201 return pdata->get_context_loss_count(up->dev);
e5b57c03
FB		 202}
203
e5b57c03
FB		 204static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
205{
d8ee4ea6 206 struct omap_uart_port_info *pdata = up->dev->platform_data;
e5b57c03 207
ce2f08de
FB		 208 if (!pdata || !pdata->enable_wakeup)
209 return;
210
211 pdata->enable_wakeup(up->dev, enable);
e5b57c03
FB		 212}
213
5fe21236
AP		 214/*
215 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
216 * @port: uart port info
217 * @baud: baudrate for which mode needs to be determined
218 *
219 * Returns true if baud rate is MODE16X and false if MODE13X
220 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
221 * and Error Rates" determines modes not for all common baud rates.
222 * E.g. for 1000000 baud rate mode must be 16x, but according to that
223 * table it's determined as 13x.
224 */
225static bool
226serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
227{
228 unsigned int n13 = port->uartclk / (13 * baud);
229 unsigned int n16 = port->uartclk / (16 * baud);
230 int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
231 int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
232 if(baudAbsDiff13 < 0)
233 baudAbsDiff13 = -baudAbsDiff13;
234 if(baudAbsDiff16 < 0)
235 baudAbsDiff16 = -baudAbsDiff16;
236
237 return (baudAbsDiff13 > baudAbsDiff16);
238}
239
b612633b
G		 240/*
241 * serial_omap_get_divisor - calculate divisor value
242 * @port: uart port info
243 * @baud: baudrate for which divisor needs to be calculated.
b612633b
G		 244 */
245static unsigned int
246serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
247{
248 unsigned int divisor;
249
5fe21236 250 if (!serial_omap_baud_is_mode16(port, baud))
b612633b
G		 251 divisor = 13;
252 else
253 divisor = 16;
254 return port->uartclk/(baud * divisor);
255}
256
b612633b
G		 257static void serial_omap_enable_ms(struct uart_port *port)
258{
c990f351 259 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 260
ba77433d 261 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
fcdca757 262
d8ee4ea6 263 pm_runtime_get_sync(up->dev);
b612633b
G		 264 up->ier |= UART_IER_MSI;
265 serial_out(up, UART_IER, up->ier);
660ac5f4
FB		 266 pm_runtime_mark_last_busy(up->dev);
267 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 268}
269
270static void serial_omap_stop_tx(struct uart_port *port)
271{
c990f351 272 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 273
d8ee4ea6 274 pm_runtime_get_sync(up->dev);
b612633b
G		 275 if (up->ier & UART_IER_THRI) {
276 up->ier &= ~UART_IER_THRI;
277 serial_out(up, UART_IER, up->ier);
278 }
fcdca757 279
d8ee4ea6
FB		 280 pm_runtime_mark_last_busy(up->dev);
281 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 282}
283
284static void serial_omap_stop_rx(struct uart_port *port)
285{
c990f351 286 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 287
d8ee4ea6 288 pm_runtime_get_sync(up->dev);
b612633b
G		 289 up->ier &= ~UART_IER_RLSI;
290 up->port.read_status_mask &= ~UART_LSR_DR;
291 serial_out(up, UART_IER, up->ier);
d8ee4ea6
FB		 292 pm_runtime_mark_last_busy(up->dev);
293 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 294}
295
bf63a086 296static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
b612633b
G		 297{
298 struct circ_buf *xmit = &up->port.state->xmit;
299 int count;
300
301 if (up->port.x_char) {
302 serial_out(up, UART_TX, up->port.x_char);
303 up->port.icount.tx++;
304 up->port.x_char = 0;
305 return;
306 }
307 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
308 serial_omap_stop_tx(&up->port);
309 return;
310 }
af681cad 311 count = up->port.fifosize / 4;
b612633b
G		 312 do {
313 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
314 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
315 up->port.icount.tx++;
316 if (uart_circ_empty(xmit))
317 break;
318 } while (--count > 0);
319
0324a821
RK		 320 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
321 spin_unlock(&up->port.lock);
b612633b 322 uart_write_wakeup(&up->port);
0324a821
RK		 323 spin_lock(&up->port.lock);
324 }
b612633b
G		 325
326 if (uart_circ_empty(xmit))
327 serial_omap_stop_tx(&up->port);
328}
329
330static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
331{
332 if (!(up->ier & UART_IER_THRI)) {
333 up->ier |= UART_IER_THRI;
334 serial_out(up, UART_IER, up->ier);
335 }
336}
337
338static void serial_omap_start_tx(struct uart_port *port)
339{
c990f351 340 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 341
49457430
FB		 342 pm_runtime_get_sync(up->dev);
343 serial_omap_enable_ier_thri(up);
49457430
FB		 344 pm_runtime_mark_last_busy(up->dev);
345 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 346}
347
3af08bd7
RK		 348static void serial_omap_throttle(struct uart_port *port)
349{
350 struct uart_omap_port *up = to_uart_omap_port(port);
351 unsigned long flags;
352
353 pm_runtime_get_sync(up->dev);
354 spin_lock_irqsave(&up->port.lock, flags);
355 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
356 serial_out(up, UART_IER, up->ier);
357 spin_unlock_irqrestore(&up->port.lock, flags);
358 pm_runtime_mark_last_busy(up->dev);
359 pm_runtime_put_autosuspend(up->dev);
360}
361
362static void serial_omap_unthrottle(struct uart_port *port)
363{
364 struct uart_omap_port *up = to_uart_omap_port(port);
365 unsigned long flags;
366
367 pm_runtime_get_sync(up->dev);
368 spin_lock_irqsave(&up->port.lock, flags);
369 up->ier |= UART_IER_RLSI | UART_IER_RDI;
370 serial_out(up, UART_IER, up->ier);
371 spin_unlock_irqrestore(&up->port.lock, flags);
372 pm_runtime_mark_last_busy(up->dev);
373 pm_runtime_put_autosuspend(up->dev);
374}
375
b612633b
G		 376static unsigned int check_modem_status(struct uart_omap_port *up)
377{
378 unsigned int status;
379
380 status = serial_in(up, UART_MSR);
381 status |= up->msr_saved_flags;
382 up->msr_saved_flags = 0;
383 if ((status & UART_MSR_ANY_DELTA) == 0)
384 return status;
385
386 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
387 up->port.state != NULL) {
388 if (status & UART_MSR_TERI)
389 up->port.icount.rng++;
390 if (status & UART_MSR_DDSR)
391 up->port.icount.dsr++;
392 if (status & UART_MSR_DDCD)
393 uart_handle_dcd_change
394 (&up->port, status & UART_MSR_DCD);
395 if (status & UART_MSR_DCTS)
396 uart_handle_cts_change
397 (&up->port, status & UART_MSR_CTS);
398 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
399 }
400
401 return status;
402}
403
72256cbd
FB		 404static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
405{
406 unsigned int flag;
9a12fcf8
S		 407 unsigned char ch = 0;
408
409 if (likely(lsr & UART_LSR_DR))
410 ch = serial_in(up, UART_RX);
72256cbd
FB		 411
412 up->port.icount.rx++;
413 flag = TTY_NORMAL;
414
415 if (lsr & UART_LSR_BI) {
416 flag = TTY_BREAK;
417 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
418 up->port.icount.brk++;
419 /*
420 * We do the SysRQ and SAK checking
421 * here because otherwise the break
422 * may get masked by ignore_status_mask
423 * or read_status_mask.
424 */
425 if (uart_handle_break(&up->port))
426 return;
427
428 }
429
430 if (lsr & UART_LSR_PE) {
431 flag = TTY_PARITY;
432 up->port.icount.parity++;
433 }
434
435 if (lsr & UART_LSR_FE) {
436 flag = TTY_FRAME;
437 up->port.icount.frame++;
438 }
439
440 if (lsr & UART_LSR_OE)
441 up->port.icount.overrun++;
442
443#ifdef CONFIG_SERIAL_OMAP_CONSOLE
444 if (up->port.line == up->port.cons->index) {
445 /* Recover the break flag from console xmit */
446 lsr |= up->lsr_break_flag;
447 }
448#endif
449 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
450}
451
452static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
453{
454 unsigned char ch = 0;
455 unsigned int flag;
456
457 if (!(lsr & UART_LSR_DR))
458 return;
459
460 ch = serial_in(up, UART_RX);
461 flag = TTY_NORMAL;
462 up->port.icount.rx++;
463
464 if (uart_handle_sysrq_char(&up->port, ch))
465 return;
466
467 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
468}
469
b612633b
G		 470/**
471 * serial_omap_irq() - This handles the interrupt from one port
472 * @irq: uart port irq number
473 * @dev_id: uart port info
474 */
52c5513d 475static irqreturn_t serial_omap_irq(int irq, void *dev_id)
b612633b
G		 476{
477 struct uart_omap_port *up = dev_id;
478 unsigned int iir, lsr;
81b75aef 479 unsigned int type;
81b75aef 480 irqreturn_t ret = IRQ_NONE;
72256cbd 481 int max_count = 256;
b612633b 482
6c3a30c7 483 spin_lock(&up->port.lock);
d8ee4ea6 484 pm_runtime_get_sync(up->dev);
72256cbd
FB		 485
486 do {
81b75aef 487 iir = serial_in(up, UART_IIR);
72256cbd
FB		 488 if (iir & UART_IIR_NO_INT)
489 break;
490
491 ret = IRQ_HANDLED;
492 lsr = serial_in(up, UART_LSR);
493
494 /* extract IRQ type from IIR register */
495 type = iir & 0x3e;
496
497 switch (type) {
498 case UART_IIR_MSI:
499 check_modem_status(up);
500 break;
501 case UART_IIR_THRI:
bf63a086 502 transmit_chars(up, lsr);
72256cbd
FB		 503 break;
504 case UART_IIR_RX_TIMEOUT:
505 /* FALLTHROUGH */
506 case UART_IIR_RDI:
507 serial_omap_rdi(up, lsr);
508 break;
509 case UART_IIR_RLSI:
510 serial_omap_rlsi(up, lsr);
511 break;
512 case UART_IIR_CTS_RTS_DSR:
513 /* simply try again */
514 break;
515 case UART_IIR_XOFF:
516 /* FALLTHROUGH */
517 default:
518 break;
519 }
520 } while (!(iir & UART_IIR_NO_INT) && max_count--);
b612633b 521
6c3a30c7 522 spin_unlock(&up->port.lock);
72256cbd 523
2e124b4a 524 tty_flip_buffer_push(&up->port.state->port);
72256cbd 525
d8ee4ea6
FB		 526 pm_runtime_mark_last_busy(up->dev);
527 pm_runtime_put_autosuspend(up->dev);
b612633b 528 up->port_activity = jiffies;
81b75aef
FB		 529
530 return ret;
b612633b
G		 531}
532
533static unsigned int serial_omap_tx_empty(struct uart_port *port)
534{
c990f351 535 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 536 unsigned long flags = 0;
537 unsigned int ret = 0;
538
d8ee4ea6 539 pm_runtime_get_sync(up->dev);
ba77433d 540 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
b612633b
G		 541 spin_lock_irqsave(&up->port.lock, flags);
542 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
543 spin_unlock_irqrestore(&up->port.lock, flags);
660ac5f4
FB		 544 pm_runtime_mark_last_busy(up->dev);
545 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 546 return ret;
547}
548
549static unsigned int serial_omap_get_mctrl(struct uart_port *port)
550{
c990f351 551 struct uart_omap_port *up = to_uart_omap_port(port);
514f31d1 552 unsigned int status;
b612633b
G		 553 unsigned int ret = 0;
554
d8ee4ea6 555 pm_runtime_get_sync(up->dev);
b612633b 556 status = check_modem_status(up);
660ac5f4
FB		 557 pm_runtime_mark_last_busy(up->dev);
558 pm_runtime_put_autosuspend(up->dev);
fcdca757 559
ba77433d 560 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
b612633b
G		 561
562 if (status & UART_MSR_DCD)
563 ret |= TIOCM_CAR;
564 if (status & UART_MSR_RI)
565 ret |= TIOCM_RNG;
566 if (status & UART_MSR_DSR)
567 ret |= TIOCM_DSR;
568 if (status & UART_MSR_CTS)
569 ret |= TIOCM_CTS;
570 return ret;
571}
572
573static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
574{
c990f351 575 struct uart_omap_port *up = to_uart_omap_port(port);
9363f8fa 576 unsigned char mcr = 0, old_mcr;
b612633b 577
ba77433d 578 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
b612633b
G		 579 if (mctrl & TIOCM_RTS)
580 mcr |= UART_MCR_RTS;
581 if (mctrl & TIOCM_DTR)
582 mcr |= UART_MCR_DTR;
583 if (mctrl & TIOCM_OUT1)
584 mcr |= UART_MCR_OUT1;
585 if (mctrl & TIOCM_OUT2)
586 mcr |= UART_MCR_OUT2;
587 if (mctrl & TIOCM_LOOP)
588 mcr |= UART_MCR_LOOP;
589
d8ee4ea6 590 pm_runtime_get_sync(up->dev);
9363f8fa
RK		 591 old_mcr = serial_in(up, UART_MCR);
592 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
593 UART_MCR_DTR | UART_MCR_RTS);
594 up->mcr = old_mcr | mcr;
c538d20c 595 serial_out(up, UART_MCR, up->mcr);
660ac5f4
FB		 596 pm_runtime_mark_last_busy(up->dev);
597 pm_runtime_put_autosuspend(up->dev);
9574f36f
N		 598
599 if (gpio_is_valid(up->DTR_gpio) &&
600 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
601 up->DTR_active = !up->DTR_active;
602 if (gpio_cansleep(up->DTR_gpio))
603 schedule_work(&up->qos_work);
604 else
605 gpio_set_value(up->DTR_gpio,
606 up->DTR_active != up->DTR_inverted);
607 }
b612633b
G		 608}
609
610static void serial_omap_break_ctl(struct uart_port *port, int break_state)
611{
c990f351 612 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 613 unsigned long flags = 0;
614
ba77433d 615 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
d8ee4ea6 616 pm_runtime_get_sync(up->dev);
b612633b
G		 617 spin_lock_irqsave(&up->port.lock, flags);
618 if (break_state == -1)
619 up->lcr |= UART_LCR_SBC;
620 else
621 up->lcr &= ~UART_LCR_SBC;
622 serial_out(up, UART_LCR, up->lcr);
623 spin_unlock_irqrestore(&up->port.lock, flags);
660ac5f4
FB		 624 pm_runtime_mark_last_busy(up->dev);
625 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 626}
627
628static int serial_omap_startup(struct uart_port *port)
629{
c990f351 630 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 631 unsigned long flags = 0;
632 int retval;
633
634 /*
635 * Allocate the IRQ
636 */
637 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
638 up->name, up);
639 if (retval)
640 return retval;
641
ba77433d 642 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
b612633b 643
d8ee4ea6 644 pm_runtime_get_sync(up->dev);
b612633b
G		 645 /*
646 * Clear the FIFO buffers and disable them.
647 * (they will be reenabled in set_termios())
648 */
649 serial_omap_clear_fifos(up);
650 /* For Hardware flow control */
651 serial_out(up, UART_MCR, UART_MCR_RTS);
652
653 /*
654 * Clear the interrupt registers.
655 */
656 (void) serial_in(up, UART_LSR);
657 if (serial_in(up, UART_LSR) & UART_LSR_DR)
658 (void) serial_in(up, UART_RX);
659 (void) serial_in(up, UART_IIR);
660 (void) serial_in(up, UART_MSR);
661
662 /*
663 * Now, initialize the UART
664 */
665 serial_out(up, UART_LCR, UART_LCR_WLEN8);
666 spin_lock_irqsave(&up->port.lock, flags);
667 /*
668 * Most PC uarts need OUT2 raised to enable interrupts.
669 */
670 up->port.mctrl |= TIOCM_OUT2;
671 serial_omap_set_mctrl(&up->port, up->port.mctrl);
672 spin_unlock_irqrestore(&up->port.lock, flags);
673
674 up->msr_saved_flags = 0;
b612633b
G		 675 /*
676 * Finally, enable interrupts. Note: Modem status interrupts
677 * are set via set_termios(), which will be occurring imminently
678 * anyway, so we don't enable them here.
679 */
680 up->ier = UART_IER_RLSI | UART_IER_RDI;
681 serial_out(up, UART_IER, up->ier);
682
78841462
JN		 683 /* Enable module level wake up */
684 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
685
d8ee4ea6
FB		 686 pm_runtime_mark_last_busy(up->dev);
687 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 688 up->port_activity = jiffies;
689 return 0;
690}
691
692static void serial_omap_shutdown(struct uart_port *port)
693{
c990f351 694 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 695 unsigned long flags = 0;
696
ba77433d 697 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
fcdca757 698
d8ee4ea6 699 pm_runtime_get_sync(up->dev);
b612633b
G		 700 /*
701 * Disable interrupts from this port
702 */
703 up->ier = 0;
704 serial_out(up, UART_IER, 0);
705
706 spin_lock_irqsave(&up->port.lock, flags);
707 up->port.mctrl &= ~TIOCM_OUT2;
708 serial_omap_set_mctrl(&up->port, up->port.mctrl);
709 spin_unlock_irqrestore(&up->port.lock, flags);
710
711 /*
712 * Disable break condition and FIFOs
713 */
714 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
715 serial_omap_clear_fifos(up);
716
717 /*
718 * Read data port to reset things, and then free the irq
719 */
720 if (serial_in(up, UART_LSR) & UART_LSR_DR)
721 (void) serial_in(up, UART_RX);
fcdca757 722
660ac5f4
FB		 723 pm_runtime_mark_last_busy(up->dev);
724 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 725 free_irq(up->port.irq, up);
726}
727
2fd14964
G		 728static void serial_omap_uart_qos_work(struct work_struct *work)
729{
730 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
731 qos_work);
732
733 pm_qos_update_request(&up->pm_qos_request, up->latency);
9574f36f
N		 734 if (gpio_is_valid(up->DTR_gpio))
735 gpio_set_value_cansleep(up->DTR_gpio,
736 up->DTR_active != up->DTR_inverted);
2fd14964
G		 737}
738
b612633b
G		 739static void
740serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
741 struct ktermios *old)
742{
c990f351 743 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 744 unsigned char cval = 0;
b612633b
G		 745 unsigned long flags = 0;
746 unsigned int baud, quot;
747
748 switch (termios->c_cflag & CSIZE) {
749 case CS5:
750 cval = UART_LCR_WLEN5;
751 break;
752 case CS6:
753 cval = UART_LCR_WLEN6;
754 break;
755 case CS7:
756 cval = UART_LCR_WLEN7;
757 break;
758 default:
759 case CS8:
760 cval = UART_LCR_WLEN8;
761 break;
762 }
763
764 if (termios->c_cflag & CSTOPB)
765 cval |= UART_LCR_STOP;
766 if (termios->c_cflag & PARENB)
767 cval |= UART_LCR_PARITY;
768 if (!(termios->c_cflag & PARODD))
769 cval |= UART_LCR_EPAR;
fdbc7353
EBS		 770 if (termios->c_cflag & CMSPAR)
771 cval |= UART_LCR_SPAR;
b612633b
G		 772
773 /*
774 * Ask the core to calculate the divisor for us.
775 */
776
777 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
778 quot = serial_omap_get_divisor(port, baud);
779
2fd14964 780 /* calculate wakeup latency constraint */
19723452 781 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
2fd14964
G		 782 up->latency = up->calc_latency;
783 schedule_work(&up->qos_work);
784
c538d20c
G		 785 up->dll = quot & 0xff;
786 up->dlh = quot >> 8;
787 up->mdr1 = UART_OMAP_MDR1_DISABLE;
788
b612633b
G		 789 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
790 UART_FCR_ENABLE_FIFO;
b612633b
G		 791
792 /*
793 * Ok, we're now changing the port state. Do it with
794 * interrupts disabled.
795 */
d8ee4ea6 796 pm_runtime_get_sync(up->dev);
b612633b
G		 797 spin_lock_irqsave(&up->port.lock, flags);
798
799 /*
800 * Update the per-port timeout.
801 */
802 uart_update_timeout(port, termios->c_cflag, baud);
803
804 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
805 if (termios->c_iflag & INPCK)
806 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
807 if (termios->c_iflag & (BRKINT | PARMRK))
808 up->port.read_status_mask |= UART_LSR_BI;
809
810 /*
811 * Characters to ignore
812 */
813 up->port.ignore_status_mask = 0;
814 if (termios->c_iflag & IGNPAR)
815 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
816 if (termios->c_iflag & IGNBRK) {
817 up->port.ignore_status_mask |= UART_LSR_BI;
818 /*
819 * If we're ignoring parity and break indicators,
820 * ignore overruns too (for real raw support).
821 */
822 if (termios->c_iflag & IGNPAR)
823 up->port.ignore_status_mask |= UART_LSR_OE;
824 }
825
826 /*
827 * ignore all characters if CREAD is not set
828 */
829 if ((termios->c_cflag & CREAD) == 0)
830 up->port.ignore_status_mask |= UART_LSR_DR;
831
832 /*
833 * Modem status interrupts
834 */
835 up->ier &= ~UART_IER_MSI;
836 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
837 up->ier |= UART_IER_MSI;
838 serial_out(up, UART_IER, up->ier);
839 serial_out(up, UART_LCR, cval); /* reset DLAB */
c538d20c 840 up->lcr = cval;
1776fd05 841 up->scr = 0;
b612633b
G		 842
843 /* FIFOs and DMA Settings */
844
845 /* FCR can be changed only when the
846 * baud clock is not running
847 * DLL_REG and DLH_REG set to 0.
848 */
662b083a 849 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b
G		 850 serial_out(up, UART_DLL, 0);
851 serial_out(up, UART_DLM, 0);
852 serial_out(up, UART_LCR, 0);
853
662b083a 854 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b 855
08bd4903 856 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
d864c03b 857 up->efr &= ~UART_EFR_SCD;
b612633b
G		 858 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
859
662b083a 860 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
08bd4903 861 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
b612633b
G		 862 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
863 /* FIFO ENABLE, DMA MODE */
0ba5f668 864
1f663966
AP		 865 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
866 /*
867 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
868 * sets Enables the granularity of 1 for TRIGGER RX
869 * level. Along with setting RX FIFO trigger level
870 * to 1 (as noted below, 16 characters) and TLR[3:0]
871 * to zero this will result RX FIFO threshold level
872 * to 1 character, instead of 16 as noted in comment
873 * below.
874 */
875
6721ab7f
FB		 876 /* Set receive FIFO threshold to 16 characters and
877 * transmit FIFO threshold to 16 spaces
878 */
49457430 879 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
6721ab7f
FB		 880 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
881 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
882 UART_FCR_ENABLE_FIFO;
b612633b 883
0ba5f668
PW		 884 serial_out(up, UART_FCR, up->fcr);
885 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
886
c538d20c
G		 887 serial_out(up, UART_OMAP_SCR, up->scr);
888
08bd4903 889 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
662b083a 890 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b 891 serial_out(up, UART_MCR, up->mcr);
08bd4903
RK		 892 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
893 serial_out(up, UART_EFR, up->efr);
894 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b
G		 895
896 /* Protocol, Baud Rate, and Interrupt Settings */
897
94734749
G		 898 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
899 serial_omap_mdr1_errataset(up, up->mdr1);
900 else
901 serial_out(up, UART_OMAP_MDR1, up->mdr1);
902
662b083a 903 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 904 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
905
906 serial_out(up, UART_LCR, 0);
907 serial_out(up, UART_IER, 0);
662b083a 908 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b 909
c538d20c
G		 910 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
911 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
b612633b
G		 912
913 serial_out(up, UART_LCR, 0);
914 serial_out(up, UART_IER, up->ier);
662b083a 915 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 916
917 serial_out(up, UART_EFR, up->efr);
918 serial_out(up, UART_LCR, cval);
919
5fe21236 920 if (!serial_omap_baud_is_mode16(port, baud))
c538d20c 921 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
b612633b 922 else
c538d20c
G		 923 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
924
94734749
G		 925 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
926 serial_omap_mdr1_errataset(up, up->mdr1);
927 else
928 serial_out(up, UART_OMAP_MDR1, up->mdr1);
b612633b 929
c533e51b 930 /* Configure flow control */
c7d059ca 931 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
c533e51b
RK		 932
933 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
934 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
935 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
936
937 /* Enable access to TCR/TLR */
c7d059ca
RK		 938 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
939 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
940 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
b612633b 941
c7d059ca 942 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
b612633b 943
c7d059ca 944 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
08bd4903
RK		 945 /* Enable AUTORTS and AUTOCTS */
946 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
947
1fe8aa88
RK		 948 /* Ensure MCR RTS is asserted */
949 up->mcr |= UART_MCR_RTS;
0d5b1663
RK		 950 } else {
951 /* Disable AUTORTS and AUTOCTS */
952 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
b612633b 953 }
b612633b 954
01d70bb3 955 if (up->port.flags & UPF_SOFT_FLOW) {
01d70bb3
RK		 956 /* clear SW control mode bits */
957 up->efr &= OMAP_UART_SW_CLR;
b612633b 958
01d70bb3
RK		 959 /*
960 * IXON Flag:
3af08bd7
RK		 961 * Enable XON/XOFF flow control on input.
962 * Receiver compares XON1, XOFF1.
01d70bb3
RK		 963 */
964 if (termios->c_iflag & IXON)
3af08bd7 965 up->efr |= OMAP_UART_SW_RX;
b612633b 966
01d70bb3
RK		 967 /*
968 * IXOFF Flag:
3af08bd7
RK		 969 * Enable XON/XOFF flow control on output.
970 * Transmit XON1, XOFF1
01d70bb3
RK		 971 */
972 if (termios->c_iflag & IXOFF)
3af08bd7 973 up->efr |= OMAP_UART_SW_TX;
b612633b 974
01d70bb3
RK		 975 /*
976 * IXANY Flag:
977 * Enable any character to restart output.
978 * Operation resumes after receiving any
979 * character after recognition of the XOFF character
980 */
981 if (termios->c_iflag & IXANY)
982 up->mcr |= UART_MCR_XONANY;
983 else
984 up->mcr &= ~UART_MCR_XONANY;
b612633b 985 }
c7d059ca 986 serial_out(up, UART_MCR, up->mcr);
18f360f8
RK		 987 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
988 serial_out(up, UART_EFR, up->efr);
989 serial_out(up, UART_LCR, up->lcr);
b612633b
G		 990
991 serial_omap_set_mctrl(&up->port, up->port.mctrl);
b612633b
G		 992
993 spin_unlock_irqrestore(&up->port.lock, flags);
660ac5f4
FB		 994 pm_runtime_mark_last_busy(up->dev);
995 pm_runtime_put_autosuspend(up->dev);
ba77433d 996 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
b612633b
G		 997}
998
9727faf4
FB		 999static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
1000{
1001 struct uart_omap_port *up = to_uart_omap_port(port);
1002
1003 serial_omap_enable_wakeup(up, state);
1004
1005 return 0;
1006}
1007
b612633b
G		 1008static void
1009serial_omap_pm(struct uart_port *port, unsigned int state,
1010 unsigned int oldstate)
1011{
c990f351 1012 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 1013 unsigned char efr;
1014
ba77433d 1015 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
fcdca757 1016
d8ee4ea6 1017 pm_runtime_get_sync(up->dev);
662b083a 1018 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 1019 efr = serial_in(up, UART_EFR);
1020 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1021 serial_out(up, UART_LCR, 0);
1022
1023 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
662b083a 1024 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 1025 serial_out(up, UART_EFR, efr);
1026 serial_out(up, UART_LCR, 0);
fcdca757 1027
d8ee4ea6 1028 if (!device_may_wakeup(up->dev)) {
fcdca757 1029 if (!state)
d8ee4ea6 1030 pm_runtime_forbid(up->dev);
fcdca757 1031 else
d8ee4ea6 1032 pm_runtime_allow(up->dev);
fcdca757
G		 1033 }
1034
660ac5f4
FB		 1035 pm_runtime_mark_last_busy(up->dev);
1036 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 1037}
1038
1039static void serial_omap_release_port(struct uart_port *port)
1040{
1041 dev_dbg(port->dev, "serial_omap_release_port+\n");
1042}
1043
1044static int serial_omap_request_port(struct uart_port *port)
1045{
1046 dev_dbg(port->dev, "serial_omap_request_port+\n");
1047 return 0;
1048}
1049
1050static void serial_omap_config_port(struct uart_port *port, int flags)
1051{
c990f351 1052 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 1053
1054 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
ba77433d 1055 up->port.line);
b612633b 1056 up->port.type = PORT_OMAP;
3af08bd7 1057 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
b612633b
G		 1058}
1059
1060static int
1061serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1062{
1063 /* we don't want the core code to modify any port params */
1064 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1065 return -EINVAL;
1066}
1067
1068static const char *
1069serial_omap_type(struct uart_port *port)
1070{
c990f351 1071 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 1072
ba77433d 1073 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
b612633b
G		 1074 return up->name;
1075}
1076
b612633b
G		 1077#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1078
1079static inline void wait_for_xmitr(struct uart_omap_port *up)
1080{
1081 unsigned int status, tmout = 10000;
1082
1083 /* Wait up to 10ms for the character(s) to be sent. */
1084 do {
1085 status = serial_in(up, UART_LSR);
1086
1087 if (status & UART_LSR_BI)
1088 up->lsr_break_flag = UART_LSR_BI;
1089
1090 if (--tmout == 0)
1091 break;
1092 udelay(1);
1093 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1094
1095 /* Wait up to 1s for flow control if necessary */
1096 if (up->port.flags & UPF_CONS_FLOW) {
1097 tmout = 1000000;
1098 for (tmout = 1000000; tmout; tmout--) {
1099 unsigned int msr = serial_in(up, UART_MSR);
1100
1101 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1102 if (msr & UART_MSR_CTS)
1103 break;
1104
1105 udelay(1);
1106 }
1107 }
1108}
1109
1b41dbc1
CC		 1110#ifdef CONFIG_CONSOLE_POLL
1111
1112static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1113{
c990f351 1114 struct uart_omap_port *up = to_uart_omap_port(port);
fcdca757 1115
d8ee4ea6 1116 pm_runtime_get_sync(up->dev);
1b41dbc1
CC		 1117 wait_for_xmitr(up);
1118 serial_out(up, UART_TX, ch);
660ac5f4
FB		 1119 pm_runtime_mark_last_busy(up->dev);
1120 pm_runtime_put_autosuspend(up->dev);
1b41dbc1
CC		 1121}
1122
1123static int serial_omap_poll_get_char(struct uart_port *port)
1124{
c990f351 1125 struct uart_omap_port *up = to_uart_omap_port(port);
fcdca757 1126 unsigned int status;
1b41dbc1 1127
d8ee4ea6 1128 pm_runtime_get_sync(up->dev);
fcdca757 1129 status = serial_in(up, UART_LSR);
a6b19c33
FB		 1130 if (!(status & UART_LSR_DR)) {
1131 status = NO_POLL_CHAR;
1132 goto out;
1133 }
1b41dbc1 1134
fcdca757 1135 status = serial_in(up, UART_RX);
a6b19c33
FB		 1136
1137out:
660ac5f4
FB		 1138 pm_runtime_mark_last_busy(up->dev);
1139 pm_runtime_put_autosuspend(up->dev);
a6b19c33 1140
fcdca757 1141 return status;
1b41dbc1
CC		 1142}
1143
1144#endif /* CONFIG_CONSOLE_POLL */
1145
1146#ifdef CONFIG_SERIAL_OMAP_CONSOLE
1147
40477d0e 1148static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1b41dbc1
CC		 1149
1150static struct uart_driver serial_omap_reg;
1151
b612633b
G		 1152static void serial_omap_console_putchar(struct uart_port *port, int ch)
1153{
c990f351 1154 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 1155
1156 wait_for_xmitr(up);
1157 serial_out(up, UART_TX, ch);
1158}
1159
1160static void
1161serial_omap_console_write(struct console *co, const char *s,
1162 unsigned int count)
1163{
1164 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1165 unsigned long flags;
1166 unsigned int ier;
1167 int locked = 1;
1168
d8ee4ea6 1169 pm_runtime_get_sync(up->dev);
fcdca757 1170
b612633b
G		 1171 local_irq_save(flags);
1172 if (up->port.sysrq)
1173 locked = 0;
1174 else if (oops_in_progress)
1175 locked = spin_trylock(&up->port.lock);
1176 else
1177 spin_lock(&up->port.lock);
1178
1179 /*
1180 * First save the IER then disable the interrupts
1181 */
1182 ier = serial_in(up, UART_IER);
1183 serial_out(up, UART_IER, 0);
1184
1185 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1186
1187 /*
1188 * Finally, wait for transmitter to become empty
1189 * and restore the IER
1190 */
1191 wait_for_xmitr(up);
1192 serial_out(up, UART_IER, ier);
1193 /*
1194 * The receive handling will happen properly because the
1195 * receive ready bit will still be set; it is not cleared
1196 * on read. However, modem control will not, we must
1197 * call it if we have saved something in the saved flags
1198 * while processing with interrupts off.
1199 */
1200 if (up->msr_saved_flags)
1201 check_modem_status(up);
1202
d8ee4ea6
FB		 1203 pm_runtime_mark_last_busy(up->dev);
1204 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 1205 if (locked)
1206 spin_unlock(&up->port.lock);
1207 local_irq_restore(flags);
1208}
1209
1210static int __init
1211serial_omap_console_setup(struct console *co, char *options)
1212{
1213 struct uart_omap_port *up;
1214 int baud = 115200;
1215 int bits = 8;
1216 int parity = 'n';
1217 int flow = 'n';
1218
1219 if (serial_omap_console_ports[co->index] == NULL)
1220 return -ENODEV;
1221 up = serial_omap_console_ports[co->index];
1222
1223 if (options)
1224 uart_parse_options(options, &baud, &parity, &bits, &flow);
1225
1226 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1227}
1228
1229static struct console serial_omap_console = {
1230 .name = OMAP_SERIAL_NAME,
1231 .write = serial_omap_console_write,
1232 .device = uart_console_device,
1233 .setup = serial_omap_console_setup,
1234 .flags = CON_PRINTBUFFER,
1235 .index = -1,
1236 .data = &serial_omap_reg,
1237};
1238
1239static void serial_omap_add_console_port(struct uart_omap_port *up)
1240{
ba77433d 1241 serial_omap_console_ports[up->port.line] = up;
b612633b
G		 1242}
1243
1244#define OMAP_CONSOLE (&serial_omap_console)
1245
1246#else
1247
1248#define OMAP_CONSOLE NULL
1249
1250static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1251{}
1252
1253#endif
1254
1255static struct uart_ops serial_omap_pops = {
1256 .tx_empty = serial_omap_tx_empty,
1257 .set_mctrl = serial_omap_set_mctrl,
1258 .get_mctrl = serial_omap_get_mctrl,
1259 .stop_tx = serial_omap_stop_tx,
1260 .start_tx = serial_omap_start_tx,
3af08bd7
RK		 1261 .throttle = serial_omap_throttle,
1262 .unthrottle = serial_omap_unthrottle,
b612633b
G		 1263 .stop_rx = serial_omap_stop_rx,
1264 .enable_ms = serial_omap_enable_ms,
1265 .break_ctl = serial_omap_break_ctl,
1266 .startup = serial_omap_startup,
1267 .shutdown = serial_omap_shutdown,
1268 .set_termios = serial_omap_set_termios,
1269 .pm = serial_omap_pm,
9727faf4 1270 .set_wake = serial_omap_set_wake,
b612633b
G		 1271 .type = serial_omap_type,
1272 .release_port = serial_omap_release_port,
1273 .request_port = serial_omap_request_port,
1274 .config_port = serial_omap_config_port,
1275 .verify_port = serial_omap_verify_port,
1b41dbc1
CC		 1276#ifdef CONFIG_CONSOLE_POLL
1277 .poll_put_char = serial_omap_poll_put_char,
1278 .poll_get_char = serial_omap_poll_get_char,
1279#endif
b612633b
G		 1280};
1281
1282static struct uart_driver serial_omap_reg = {
1283 .owner = THIS_MODULE,
1284 .driver_name = "OMAP-SERIAL",
1285 .dev_name = OMAP_SERIAL_NAME,
1286 .nr = OMAP_MAX_HSUART_PORTS,
1287 .cons = OMAP_CONSOLE,
1288};
1289
3bc4f0d8 1290#ifdef CONFIG_PM_SLEEP
ddd85e22
SP		 1291static int serial_omap_prepare(struct device *dev)
1292{
1293 struct uart_omap_port *up = dev_get_drvdata(dev);
1294
1295 up->is_suspending = true;
1296
1297 return 0;
1298}
1299
1300static void serial_omap_complete(struct device *dev)
1301{
1302 struct uart_omap_port *up = dev_get_drvdata(dev);
1303
1304 up->is_suspending = false;
1305}
1306
fcdca757 1307static int serial_omap_suspend(struct device *dev)
b612633b 1308{
fcdca757 1309 struct uart_omap_port *up = dev_get_drvdata(dev);
b612633b 1310
ac57e7f3 1311 uart_suspend_port(&serial_omap_reg, &up->port);
033d9959 1312 flush_work(&up->qos_work);
2fd14964 1313
b612633b
G		 1314 return 0;
1315}
1316
fcdca757 1317static int serial_omap_resume(struct device *dev)
b612633b 1318{
fcdca757 1319 struct uart_omap_port *up = dev_get_drvdata(dev);
b612633b 1320
ac57e7f3
SP		 1321 uart_resume_port(&serial_omap_reg, &up->port);
1322
b612633b
G		 1323 return 0;
1324}
ddd85e22
SP		 1325#else
1326#define serial_omap_prepare NULL
2cb5a2fa 1327#define serial_omap_complete NULL
ddd85e22 1328#endif /* CONFIG_PM_SLEEP */
b612633b 1329
9671f099 1330static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
7c77c8de
G		 1331{
1332 u32 mvr, scheme;
1333 u16 revision, major, minor;
1334
1335 mvr = serial_in(up, UART_OMAP_MVER);
1336
1337 /* Check revision register scheme */
1338 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1339
1340 switch (scheme) {
1341 case 0: /* Legacy Scheme: OMAP2/3 */
1342 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1343 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1344 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1345 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1346 break;
1347 case 1:
1348 /* New Scheme: OMAP4+ */
1349 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1350 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1351 OMAP_UART_MVR_MAJ_SHIFT;
1352 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1353 break;
1354 default:
d8ee4ea6 1355 dev_warn(up->dev,
7c77c8de
G		 1356 "Unknown %s revision, defaulting to highest\n",
1357 up->name);
1358 /* highest possible revision */
1359 major = 0xff;
1360 minor = 0xff;
1361 }
1362
1363 /* normalize revision for the driver */
1364 revision = UART_BUILD_REVISION(major, minor);
1365
1366 switch (revision) {
1367 case OMAP_UART_REV_46:
1368 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1369 UART_ERRATA_i291_DMA_FORCEIDLE);
1370 break;
1371 case OMAP_UART_REV_52:
1372 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1373 UART_ERRATA_i291_DMA_FORCEIDLE);
1374 break;
1375 case OMAP_UART_REV_63:
1376 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1377 break;
1378 default:
1379 break;
1380 }
1381}
1382
9671f099 1383static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
d92b0dfc
RN		 1384{
1385 struct omap_uart_port_info *omap_up_info;
1386
1387 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1388 if (!omap_up_info)
1389 return NULL; /* out of memory */
1390
1391 of_property_read_u32(dev->of_node, "clock-frequency",
1392 &omap_up_info->uartclk);
1393 return omap_up_info;
1394}
1395
9671f099 1396static int serial_omap_probe(struct platform_device *pdev)
b612633b
G		 1397{
1398 struct uart_omap_port *up;
49457430 1399 struct resource *mem, *irq;
b612633b 1400 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
9574f36f 1401 int ret;
b612633b 1402
d92b0dfc
RN		 1403 if (pdev->dev.of_node)
1404 omap_up_info = of_get_uart_port_info(&pdev->dev);
1405
b612633b
G		 1406 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1407 if (!mem) {
1408 dev_err(&pdev->dev, "no mem resource?\n");
1409 return -ENODEV;
1410 }
1411
1412 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1413 if (!irq) {
1414 dev_err(&pdev->dev, "no irq resource?\n");
1415 return -ENODEV;
1416 }
1417
388bc262 1418 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
28f65c11 1419 pdev->dev.driver->name)) {
b612633b
G		 1420 dev_err(&pdev->dev, "memory region already claimed\n");
1421 return -EBUSY;
1422 }
1423
9574f36f
N		 1424 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1425 omap_up_info->DTR_present) {
1426 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1427 if (ret < 0)
1428 return ret;
1429 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1430 omap_up_info->DTR_inverted);
1431 if (ret < 0)
1432 return ret;
1433 }
1434
388bc262
S		 1435 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1436 if (!up)
1437 return -ENOMEM;
b612633b 1438
9574f36f
N		 1439 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1440 omap_up_info->DTR_present) {
1441 up->DTR_gpio = omap_up_info->DTR_gpio;
1442 up->DTR_inverted = omap_up_info->DTR_inverted;
1443 } else
1444 up->DTR_gpio = -EINVAL;
1445 up->DTR_active = 0;
1446
d8ee4ea6 1447 up->dev = &pdev->dev;
b612633b
G		 1448 up->port.dev = &pdev->dev;
1449 up->port.type = PORT_OMAP;
1450 up->port.iotype = UPIO_MEM;
1451 up->port.irq = irq->start;
1452
1453 up->port.regshift = 2;
1454 up->port.fifosize = 64;
1455 up->port.ops = &serial_omap_pops;
b612633b 1456
d92b0dfc
RN		 1457 if (pdev->dev.of_node)
1458 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1459 else
1460 up->port.line = pdev->id;
1461
1462 if (up->port.line < 0) {
1463 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1464 up->port.line);
1465 ret = -ENODEV;
388bc262 1466 goto err_port_line;
d92b0dfc
RN		 1467 }
1468
1469 sprintf(up->name, "OMAP UART%d", up->port.line);
edd70ad7 1470 up->port.mapbase = mem->start;
388bc262
S		 1471 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1472 resource_size(mem));
edd70ad7
G		 1473 if (!up->port.membase) {
1474 dev_err(&pdev->dev, "can't ioremap UART\n");
1475 ret = -ENOMEM;
388bc262 1476 goto err_ioremap;
edd70ad7
G		 1477 }
1478
b612633b 1479 up->port.flags = omap_up_info->flags;
b612633b 1480 up->port.uartclk = omap_up_info->uartclk;
8fe789dc
RN		 1481 if (!up->port.uartclk) {
1482 up->port.uartclk = DEFAULT_CLK_SPEED;
1483 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1484 "%d\n", DEFAULT_CLK_SPEED);
1485 }
b612633b 1486
2fd14964
G		 1487 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1488 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1489 pm_qos_add_request(&up->pm_qos_request,
1490 PM_QOS_CPU_DMA_LATENCY, up->latency);
1491 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1492 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1493
93220dcc 1494 platform_set_drvdata(pdev, up);
856e35bf 1495 pm_runtime_enable(&pdev->dev);
a630fbfb
TL		 1496 if (omap_up_info->autosuspend_timeout == 0)
1497 omap_up_info->autosuspend_timeout = -1;
1498 device_init_wakeup(up->dev, true);
fcdca757
G		 1499 pm_runtime_use_autosuspend(&pdev->dev);
1500 pm_runtime_set_autosuspend_delay(&pdev->dev,
c86845db 1501 omap_up_info->autosuspend_timeout);
fcdca757
G		 1502
1503 pm_runtime_irq_safe(&pdev->dev);
fcdca757
G		 1504 pm_runtime_get_sync(&pdev->dev);
1505
7c77c8de
G		 1506 omap_serial_fill_features_erratas(up);
1507
ba77433d 1508 ui[up->port.line] = up;
b612633b
G		 1509 serial_omap_add_console_port(up);
1510
1511 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1512 if (ret != 0)
388bc262 1513 goto err_add_port;
b612633b 1514
660ac5f4
FB		 1515 pm_runtime_mark_last_busy(up->dev);
1516 pm_runtime_put_autosuspend(up->dev);
b612633b 1517 return 0;
388bc262
S		 1518
1519err_add_port:
1520 pm_runtime_put(&pdev->dev);
1521 pm_runtime_disable(&pdev->dev);
1522err_ioremap:
1523err_port_line:
b612633b
G		 1524 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1525 pdev->id, __func__, ret);
b612633b
G		 1526 return ret;
1527}
1528
ae8d8a14 1529static int serial_omap_remove(struct platform_device *dev)
b612633b
G		 1530{
1531 struct uart_omap_port *up = platform_get_drvdata(dev);
1532
7e9c8e7d 1533 pm_runtime_put_sync(up->dev);
1b42c8b2
FB		 1534 pm_runtime_disable(up->dev);
1535 uart_remove_one_port(&serial_omap_reg, &up->port);
1536 pm_qos_remove_request(&up->pm_qos_request);
fcdca757 1537
fcdca757
G		 1538 return 0;
1539}
1540
94734749
G		 1541/*
1542 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1543 * The access to uart register after MDR1 Access
1544 * causes UART to corrupt data.
1545 *
1546 * Need a delay =
1547 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1548 * give 10 times as much
1549 */
1550static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1551{
1552 u8 timeout = 255;
1553
1554 serial_out(up, UART_OMAP_MDR1, mdr1);
1555 udelay(2);
1556 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1557 UART_FCR_CLEAR_RCVR);
1558 /*
1559 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1560 * TX_FIFO_E bit is 1.
1561 */
1562 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1563 (UART_LSR_THRE | UART_LSR_DR))) {
1564 timeout--;
1565 if (!timeout) {
1566 /* Should *never* happen. we warn and carry on */
d8ee4ea6 1567 dev_crit(up->dev, "Errata i202: timedout %x\n",
94734749
G		 1568 serial_in(up, UART_LSR));
1569 break;
1570 }
1571 udelay(1);
1572 }
1573}
1574
b5148856 1575#ifdef CONFIG_PM_RUNTIME
9f9ac1e8
G		 1576static void serial_omap_restore_context(struct uart_omap_port *up)
1577{
94734749
G		 1578 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1579 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1580 else
1581 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1582
9f9ac1e8
G		 1583 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1584 serial_out(up, UART_EFR, UART_EFR_ECB);
1585 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1586 serial_out(up, UART_IER, 0x0);
1587 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
c538d20c
G		 1588 serial_out(up, UART_DLL, up->dll);
1589 serial_out(up, UART_DLM, up->dlh);
9f9ac1e8
G		 1590 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1591 serial_out(up, UART_IER, up->ier);
1592 serial_out(up, UART_FCR, up->fcr);
1593 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1594 serial_out(up, UART_MCR, up->mcr);
1595 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
c538d20c 1596 serial_out(up, UART_OMAP_SCR, up->scr);
9f9ac1e8
G		 1597 serial_out(up, UART_EFR, up->efr);
1598 serial_out(up, UART_LCR, up->lcr);
94734749
G		 1599 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1600 serial_omap_mdr1_errataset(up, up->mdr1);
1601 else
1602 serial_out(up, UART_OMAP_MDR1, up->mdr1);
9f9ac1e8
G		 1603}
1604
fcdca757
G		 1605static int serial_omap_runtime_suspend(struct device *dev)
1606{
ec3bebc6 1607 struct uart_omap_port *up = dev_get_drvdata(dev);
ec3bebc6 1608
7f25301d
WY		 1609 if (!up)
1610 return -EINVAL;
1611
ddd85e22
SP		 1612 /*
1613 * When using 'no_console_suspend', the console UART must not be
1614 * suspended. Since driver suspend is managed by runtime suspend,
1615 * preventing runtime suspend (by returning error) will keep device
1616 * active during suspend.
1617 */
1618 if (up->is_suspending && !console_suspend_enabled &&
1619 uart_console(&up->port))
1620 return -EBUSY;
1621
e5b57c03 1622 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
ec3bebc6 1623
62f3ec5f
G		 1624 if (device_may_wakeup(dev)) {
1625 if (!up->wakeups_enabled) {
e5b57c03 1626 serial_omap_enable_wakeup(up, true);
62f3ec5f
G		 1627 up->wakeups_enabled = true;
1628 }
1629 } else {
1630 if (up->wakeups_enabled) {
e5b57c03 1631 serial_omap_enable_wakeup(up, false);
62f3ec5f
G		 1632 up->wakeups_enabled = false;
1633 }
1634 }
1635
2fd14964
G		 1636 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1637 schedule_work(&up->qos_work);
1638
b612633b
G		 1639 return 0;
1640}
1641
fcdca757
G		 1642static int serial_omap_runtime_resume(struct device *dev)
1643{
9f9ac1e8
G		 1644 struct uart_omap_port *up = dev_get_drvdata(dev);
1645
39aee51d 1646 int loss_cnt = serial_omap_get_context_loss_count(up);
ec3bebc6 1647
39aee51d 1648 if (loss_cnt < 0) {
a630fbfb 1649 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
39aee51d 1650 loss_cnt);
ac57e7f3 1651 serial_omap_restore_context(up);
39aee51d
S		 1652 } else if (up->context_loss_cnt != loss_cnt) {
1653 serial_omap_restore_context(up);
1654 }
ac57e7f3
SP		 1655 up->latency = up->calc_latency;
1656 schedule_work(&up->qos_work);
9f9ac1e8 1657
b612633b
G		 1658 return 0;
1659}
fcdca757
G		 1660#endif
1661
1662static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1663 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1664 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1665 serial_omap_runtime_resume, NULL)
ddd85e22
SP		 1666 .prepare = serial_omap_prepare,
1667 .complete = serial_omap_complete,
fcdca757
G		 1668};
1669
d92b0dfc
RN		 1670#if defined(CONFIG_OF)
1671static const struct of_device_id omap_serial_of_match[] = {
1672 { .compatible = "ti,omap2-uart" },
1673 { .compatible = "ti,omap3-uart" },
1674 { .compatible = "ti,omap4-uart" },
1675 {},
1676};
1677MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1678#endif
b612633b
G		 1679
1680static struct platform_driver serial_omap_driver = {
1681 .probe = serial_omap_probe,
2d47b716 1682 .remove = serial_omap_remove,
b612633b
G		 1683 .driver = {
1684 .name = DRIVER_NAME,
fcdca757 1685 .pm = &serial_omap_dev_pm_ops,
d92b0dfc 1686 .of_match_table = of_match_ptr(omap_serial_of_match),
b612633b
G		 1687 },
1688};
1689
1690static int __init serial_omap_init(void)
1691{
1692 int ret;
1693
1694 ret = uart_register_driver(&serial_omap_reg);
1695 if (ret != 0)
1696 return ret;
1697 ret = platform_driver_register(&serial_omap_driver);
1698 if (ret != 0)
1699 uart_unregister_driver(&serial_omap_reg);
1700 return ret;
1701}
1702
1703static void __exit serial_omap_exit(void)
1704{
1705 platform_driver_unregister(&serial_omap_driver);
1706 uart_unregister_driver(&serial_omap_reg);
1707}
1708
1709module_init(serial_omap_init);
1710module_exit(serial_omap_exit);
1711
1712MODULE_DESCRIPTION("OMAP High Speed UART driver");
1713MODULE_LICENSE("GPL");
1714MODULE_AUTHOR("Texas Instruments Inc");
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