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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for PowerMac Z85c30 based ESCC cell found in the |
3 | * "macio" ASICs of various PowerMac models | |
4 | * | |
5 | * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org) | |
6 | * | |
7 | * Derived from drivers/macintosh/macserial.c by Paul Mackerras | |
8 | * and drivers/serial/sunzilog.c by David S. Miller | |
9 | * | |
10 | * Hrm... actually, I ripped most of sunzilog (Thanks David !) and | |
11 | * adapted special tweaks needed for us. I don't think it's worth | |
12 | * merging back those though. The DMA code still has to get in | |
13 | * and once done, I expect that driver to remain fairly stable in | |
14 | * the long term, unless we change the driver model again... | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
29 | * | |
30 | * 2004-08-06 Harald Welte <laforge@gnumonks.org> | |
31 | * - Enable BREAK interrupt | |
32 | * - Add support for sysreq | |
33 | * | |
34 | * TODO: - Add DMA support | |
35 | * - Defer port shutdown to a few seconds after close | |
36 | * - maybe put something right into uap->clk_divisor | |
37 | */ | |
38 | ||
39 | #undef DEBUG | |
40 | #undef DEBUG_HARD | |
41 | #undef USE_CTRL_O_SYSRQ | |
42 | ||
1da177e4 LT |
43 | #include <linux/module.h> |
44 | #include <linux/tty.h> | |
45 | ||
46 | #include <linux/tty_flip.h> | |
47 | #include <linux/major.h> | |
48 | #include <linux/string.h> | |
49 | #include <linux/fcntl.h> | |
50 | #include <linux/mm.h> | |
51 | #include <linux/kernel.h> | |
52 | #include <linux/delay.h> | |
53 | #include <linux/init.h> | |
54 | #include <linux/console.h> | |
1da177e4 LT |
55 | #include <linux/adb.h> |
56 | #include <linux/pmu.h> | |
57 | #include <linux/bitops.h> | |
58 | #include <linux/sysrq.h> | |
f392ecfa | 59 | #include <linux/mutex.h> |
1da177e4 LT |
60 | #include <asm/sections.h> |
61 | #include <asm/io.h> | |
62 | #include <asm/irq.h> | |
ec9cbe09 FT |
63 | |
64 | #ifdef CONFIG_PPC_PMAC | |
1da177e4 LT |
65 | #include <asm/prom.h> |
66 | #include <asm/machdep.h> | |
67 | #include <asm/pmac_feature.h> | |
68 | #include <asm/dbdma.h> | |
69 | #include <asm/macio.h> | |
ec9cbe09 FT |
70 | #else |
71 | #include <linux/platform_device.h> | |
72 | #define of_machine_is_compatible(x) (0) | |
73 | #endif | |
1da177e4 LT |
74 | |
75 | #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
76 | #define SUPPORT_SYSRQ | |
77 | #endif | |
78 | ||
79 | #include <linux/serial.h> | |
80 | #include <linux/serial_core.h> | |
81 | ||
82 | #include "pmac_zilog.h" | |
83 | ||
84 | /* Not yet implemented */ | |
85 | #undef HAS_DBDMA | |
86 | ||
87 | static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)"; | |
88 | MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>"); | |
ec9cbe09 | 89 | MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports."); |
1da177e4 LT |
90 | MODULE_LICENSE("GPL"); |
91 | ||
e4533b24 DW |
92 | #ifdef CONFIG_SERIAL_PMACZILOG_TTYS |
93 | #define PMACZILOG_MAJOR TTY_MAJOR | |
94 | #define PMACZILOG_MINOR 64 | |
95 | #define PMACZILOG_NAME "ttyS" | |
96 | #else | |
97 | #define PMACZILOG_MAJOR 204 | |
98 | #define PMACZILOG_MINOR 192 | |
99 | #define PMACZILOG_NAME "ttyPZ" | |
100 | #endif | |
101 | ||
a79dd5ae BH |
102 | #define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg) |
103 | #define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg) | |
104 | #define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg) | |
1da177e4 LT |
105 | |
106 | /* | |
107 | * For the sake of early serial console, we can do a pre-probe | |
108 | * (optional) of the ports at rather early boot time. | |
109 | */ | |
110 | static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS]; | |
111 | static int pmz_ports_count; | |
1da177e4 LT |
112 | |
113 | static struct uart_driver pmz_uart_reg = { | |
114 | .owner = THIS_MODULE, | |
e4533b24 DW |
115 | .driver_name = PMACZILOG_NAME, |
116 | .dev_name = PMACZILOG_NAME, | |
117 | .major = PMACZILOG_MAJOR, | |
118 | .minor = PMACZILOG_MINOR, | |
1da177e4 LT |
119 | }; |
120 | ||
121 | ||
122 | /* | |
123 | * Load all registers to reprogram the port | |
124 | * This function must only be called when the TX is not busy. The UART | |
125 | * port lock must be held and local interrupts disabled. | |
126 | */ | |
127 | static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) | |
128 | { | |
129 | int i; | |
130 | ||
1da177e4 LT |
131 | /* Let pending transmits finish. */ |
132 | for (i = 0; i < 1000; i++) { | |
133 | unsigned char stat = read_zsreg(uap, R1); | |
134 | if (stat & ALL_SNT) | |
135 | break; | |
136 | udelay(100); | |
137 | } | |
138 | ||
139 | ZS_CLEARERR(uap); | |
140 | zssync(uap); | |
141 | ZS_CLEARFIFO(uap); | |
142 | zssync(uap); | |
143 | ZS_CLEARERR(uap); | |
144 | ||
145 | /* Disable all interrupts. */ | |
146 | write_zsreg(uap, R1, | |
147 | regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); | |
148 | ||
149 | /* Set parity, sync config, stop bits, and clock divisor. */ | |
150 | write_zsreg(uap, R4, regs[R4]); | |
151 | ||
152 | /* Set misc. TX/RX control bits. */ | |
153 | write_zsreg(uap, R10, regs[R10]); | |
154 | ||
155 | /* Set TX/RX controls sans the enable bits. */ | |
1f7b5fff FT |
156 | write_zsreg(uap, R3, regs[R3] & ~RxENABLE); |
157 | write_zsreg(uap, R5, regs[R5] & ~TxENABLE); | |
1da177e4 LT |
158 | |
159 | /* now set R7 "prime" on ESCC */ | |
160 | write_zsreg(uap, R15, regs[R15] | EN85C30); | |
161 | write_zsreg(uap, R7, regs[R7P]); | |
162 | ||
163 | /* make sure we use R7 "non-prime" on ESCC */ | |
164 | write_zsreg(uap, R15, regs[R15] & ~EN85C30); | |
165 | ||
166 | /* Synchronous mode config. */ | |
167 | write_zsreg(uap, R6, regs[R6]); | |
168 | write_zsreg(uap, R7, regs[R7]); | |
169 | ||
170 | /* Disable baud generator. */ | |
171 | write_zsreg(uap, R14, regs[R14] & ~BRENAB); | |
172 | ||
173 | /* Clock mode control. */ | |
174 | write_zsreg(uap, R11, regs[R11]); | |
175 | ||
176 | /* Lower and upper byte of baud rate generator divisor. */ | |
177 | write_zsreg(uap, R12, regs[R12]); | |
178 | write_zsreg(uap, R13, regs[R13]); | |
179 | ||
180 | /* Now rewrite R14, with BRENAB (if set). */ | |
181 | write_zsreg(uap, R14, regs[R14]); | |
182 | ||
183 | /* Reset external status interrupts. */ | |
184 | write_zsreg(uap, R0, RES_EXT_INT); | |
185 | write_zsreg(uap, R0, RES_EXT_INT); | |
186 | ||
187 | /* Rewrite R3/R5, this time without enables masked. */ | |
188 | write_zsreg(uap, R3, regs[R3]); | |
189 | write_zsreg(uap, R5, regs[R5]); | |
190 | ||
191 | /* Rewrite R1, this time without IRQ enabled masked. */ | |
192 | write_zsreg(uap, R1, regs[R1]); | |
193 | ||
194 | /* Enable interrupts */ | |
195 | write_zsreg(uap, R9, regs[R9]); | |
196 | } | |
197 | ||
198 | /* | |
199 | * We do like sunzilog to avoid disrupting pending Tx | |
200 | * Reprogram the Zilog channel HW registers with the copies found in the | |
201 | * software state struct. If the transmitter is busy, we defer this update | |
202 | * until the next TX complete interrupt. Else, we do it right now. | |
203 | * | |
204 | * The UART port lock must be held and local interrupts disabled. | |
205 | */ | |
206 | static void pmz_maybe_update_regs(struct uart_pmac_port *uap) | |
207 | { | |
1f7b5fff | 208 | if (!ZS_REGS_HELD(uap)) { |
1da177e4 LT |
209 | if (ZS_TX_ACTIVE(uap)) { |
210 | uap->flags |= PMACZILOG_FLAG_REGS_HELD; | |
211 | } else { | |
212 | pmz_debug("pmz: maybe_update_regs: updating\n"); | |
213 | pmz_load_zsregs(uap, uap->curregs); | |
214 | } | |
215 | } | |
216 | } | |
217 | ||
7cf82b1b FT |
218 | static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable) |
219 | { | |
220 | if (enable) { | |
221 | uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB; | |
222 | if (!ZS_IS_EXTCLK(uap)) | |
223 | uap->curregs[1] |= EXT_INT_ENAB; | |
224 | } else { | |
225 | uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); | |
226 | } | |
227 | write_zsreg(uap, R1, uap->curregs[1]); | |
228 | } | |
229 | ||
7d12e780 | 230 | static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap) |
1da177e4 LT |
231 | { |
232 | struct tty_struct *tty = NULL; | |
33f0f88f | 233 | unsigned char ch, r1, drop, error, flag; |
1da177e4 LT |
234 | int loops = 0; |
235 | ||
1da177e4 | 236 | /* Sanity check, make sure the old bug is no longer happening */ |
ebd2c8f6 | 237 | if (uap->port.state == NULL || uap->port.state->port.tty == NULL) { |
1da177e4 LT |
238 | WARN_ON(1); |
239 | (void)read_zsdata(uap); | |
240 | return NULL; | |
241 | } | |
ebd2c8f6 | 242 | tty = uap->port.state->port.tty; |
1da177e4 LT |
243 | |
244 | while (1) { | |
245 | error = 0; | |
246 | drop = 0; | |
247 | ||
1da177e4 LT |
248 | r1 = read_zsreg(uap, R1); |
249 | ch = read_zsdata(uap); | |
250 | ||
251 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { | |
252 | write_zsreg(uap, R0, ERR_RES); | |
253 | zssync(uap); | |
254 | } | |
255 | ||
256 | ch &= uap->parity_mask; | |
257 | if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) { | |
258 | uap->flags &= ~PMACZILOG_FLAG_BREAK; | |
259 | } | |
260 | ||
261 | #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE) | |
262 | #ifdef USE_CTRL_O_SYSRQ | |
263 | /* Handle the SysRq ^O Hack */ | |
264 | if (ch == '\x0f') { | |
265 | uap->port.sysrq = jiffies + HZ*5; | |
266 | goto next_char; | |
267 | } | |
268 | #endif /* USE_CTRL_O_SYSRQ */ | |
269 | if (uap->port.sysrq) { | |
270 | int swallow; | |
271 | spin_unlock(&uap->port.lock); | |
7d12e780 | 272 | swallow = uart_handle_sysrq_char(&uap->port, ch); |
1da177e4 LT |
273 | spin_lock(&uap->port.lock); |
274 | if (swallow) | |
275 | goto next_char; | |
1f7b5fff | 276 | } |
1da177e4 LT |
277 | #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */ |
278 | ||
279 | /* A real serial line, record the character and status. */ | |
280 | if (drop) | |
281 | goto next_char; | |
282 | ||
33f0f88f | 283 | flag = TTY_NORMAL; |
1da177e4 LT |
284 | uap->port.icount.rx++; |
285 | ||
286 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) { | |
287 | error = 1; | |
288 | if (r1 & BRK_ABRT) { | |
289 | pmz_debug("pmz: got break !\n"); | |
290 | r1 &= ~(PAR_ERR | CRC_ERR); | |
291 | uap->port.icount.brk++; | |
292 | if (uart_handle_break(&uap->port)) | |
293 | goto next_char; | |
294 | } | |
295 | else if (r1 & PAR_ERR) | |
296 | uap->port.icount.parity++; | |
297 | else if (r1 & CRC_ERR) | |
298 | uap->port.icount.frame++; | |
299 | if (r1 & Rx_OVR) | |
300 | uap->port.icount.overrun++; | |
301 | r1 &= uap->port.read_status_mask; | |
302 | if (r1 & BRK_ABRT) | |
33f0f88f | 303 | flag = TTY_BREAK; |
1da177e4 | 304 | else if (r1 & PAR_ERR) |
33f0f88f | 305 | flag = TTY_PARITY; |
1da177e4 | 306 | else if (r1 & CRC_ERR) |
33f0f88f | 307 | flag = TTY_FRAME; |
1da177e4 LT |
308 | } |
309 | ||
310 | if (uap->port.ignore_status_mask == 0xff || | |
311 | (r1 & uap->port.ignore_status_mask) == 0) { | |
1f7b5fff | 312 | tty_insert_flip_char(tty, ch, flag); |
1da177e4 | 313 | } |
33f0f88f AC |
314 | if (r1 & Rx_OVR) |
315 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
1da177e4 LT |
316 | next_char: |
317 | /* We can get stuck in an infinite loop getting char 0 when the | |
318 | * line is in a wrong HW state, we break that here. | |
319 | * When that happens, I disable the receive side of the driver. | |
320 | * Note that what I've been experiencing is a real irq loop where | |
321 | * I'm getting flooded regardless of the actual port speed. | |
25985edc | 322 | * Something strange is going on with the HW |
1da177e4 LT |
323 | */ |
324 | if ((++loops) > 1000) | |
325 | goto flood; | |
326 | ch = read_zsreg(uap, R0); | |
327 | if (!(ch & Rx_CH_AV)) | |
328 | break; | |
329 | } | |
330 | ||
331 | return tty; | |
332 | flood: | |
7cf82b1b | 333 | pmz_interrupt_control(uap, 0); |
ec9cbe09 | 334 | pmz_error("pmz: rx irq flood !\n"); |
1da177e4 LT |
335 | return tty; |
336 | } | |
337 | ||
7d12e780 | 338 | static void pmz_status_handle(struct uart_pmac_port *uap) |
1da177e4 LT |
339 | { |
340 | unsigned char status; | |
341 | ||
342 | status = read_zsreg(uap, R0); | |
343 | write_zsreg(uap, R0, RES_EXT_INT); | |
344 | zssync(uap); | |
345 | ||
346 | if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) { | |
347 | if (status & SYNC_HUNT) | |
348 | uap->port.icount.dsr++; | |
349 | ||
350 | /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. | |
351 | * But it does not tell us which bit has changed, we have to keep | |
352 | * track of this ourselves. | |
353 | * The CTS input is inverted for some reason. -- paulus | |
354 | */ | |
355 | if ((status ^ uap->prev_status) & DCD) | |
356 | uart_handle_dcd_change(&uap->port, | |
357 | (status & DCD)); | |
358 | if ((status ^ uap->prev_status) & CTS) | |
359 | uart_handle_cts_change(&uap->port, | |
360 | !(status & CTS)); | |
361 | ||
bdc04e31 | 362 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
363 | } |
364 | ||
365 | if (status & BRK_ABRT) | |
366 | uap->flags |= PMACZILOG_FLAG_BREAK; | |
367 | ||
368 | uap->prev_status = status; | |
369 | } | |
370 | ||
371 | static void pmz_transmit_chars(struct uart_pmac_port *uap) | |
372 | { | |
373 | struct circ_buf *xmit; | |
374 | ||
1da177e4 LT |
375 | if (ZS_IS_CONS(uap)) { |
376 | unsigned char status = read_zsreg(uap, R0); | |
377 | ||
378 | /* TX still busy? Just wait for the next TX done interrupt. | |
379 | * | |
380 | * It can occur because of how we do serial console writes. It would | |
381 | * be nice to transmit console writes just like we normally would for | |
382 | * a TTY line. (ie. buffered and TX interrupt driven). That is not | |
383 | * easy because console writes cannot sleep. One solution might be | |
25985edc | 384 | * to poll on enough port->xmit space becoming free. -DaveM |
1da177e4 LT |
385 | */ |
386 | if (!(status & Tx_BUF_EMP)) | |
387 | return; | |
388 | } | |
389 | ||
390 | uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE; | |
391 | ||
392 | if (ZS_REGS_HELD(uap)) { | |
393 | pmz_load_zsregs(uap, uap->curregs); | |
394 | uap->flags &= ~PMACZILOG_FLAG_REGS_HELD; | |
395 | } | |
396 | ||
397 | if (ZS_TX_STOPPED(uap)) { | |
398 | uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; | |
399 | goto ack_tx_int; | |
400 | } | |
401 | ||
02ab8513 BH |
402 | /* Under some circumstances, we see interrupts reported for |
403 | * a closed channel. The interrupt mask in R1 is clear, but | |
404 | * R3 still signals the interrupts and we see them when taking | |
405 | * an interrupt for the other channel (this could be a qemu | |
406 | * bug but since the ESCC doc doesn't specify precsiely whether | |
407 | * R3 interrup status bits are masked by R1 interrupt enable | |
408 | * bits, better safe than sorry). --BenH. | |
409 | */ | |
410 | if (!ZS_IS_OPEN(uap)) | |
411 | goto ack_tx_int; | |
412 | ||
1da177e4 LT |
413 | if (uap->port.x_char) { |
414 | uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; | |
415 | write_zsdata(uap, uap->port.x_char); | |
416 | zssync(uap); | |
417 | uap->port.icount.tx++; | |
418 | uap->port.x_char = 0; | |
419 | return; | |
420 | } | |
421 | ||
ebd2c8f6 | 422 | if (uap->port.state == NULL) |
1da177e4 | 423 | goto ack_tx_int; |
ebd2c8f6 | 424 | xmit = &uap->port.state->xmit; |
1da177e4 LT |
425 | if (uart_circ_empty(xmit)) { |
426 | uart_write_wakeup(&uap->port); | |
427 | goto ack_tx_int; | |
428 | } | |
429 | if (uart_tx_stopped(&uap->port)) | |
430 | goto ack_tx_int; | |
431 | ||
432 | uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; | |
433 | write_zsdata(uap, xmit->buf[xmit->tail]); | |
434 | zssync(uap); | |
435 | ||
436 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
437 | uap->port.icount.tx++; | |
438 | ||
439 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
440 | uart_write_wakeup(&uap->port); | |
441 | ||
442 | return; | |
443 | ||
444 | ack_tx_int: | |
445 | write_zsreg(uap, R0, RES_Tx_P); | |
446 | zssync(uap); | |
447 | } | |
448 | ||
449 | /* Hrm... we register that twice, fixme later.... */ | |
7d12e780 | 450 | static irqreturn_t pmz_interrupt(int irq, void *dev_id) |
1da177e4 LT |
451 | { |
452 | struct uart_pmac_port *uap = dev_id; | |
453 | struct uart_pmac_port *uap_a; | |
454 | struct uart_pmac_port *uap_b; | |
455 | int rc = IRQ_NONE; | |
456 | struct tty_struct *tty; | |
457 | u8 r3; | |
458 | ||
459 | uap_a = pmz_get_port_A(uap); | |
460 | uap_b = uap_a->mate; | |
1f7b5fff FT |
461 | |
462 | spin_lock(&uap_a->port.lock); | |
1da177e4 LT |
463 | r3 = read_zsreg(uap_a, R3); |
464 | ||
465 | #ifdef DEBUG_HARD | |
466 | pmz_debug("irq, r3: %x\n", r3); | |
467 | #endif | |
1f7b5fff | 468 | /* Channel A */ |
1da177e4 | 469 | tty = NULL; |
1f7b5fff | 470 | if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { |
a79dd5ae BH |
471 | if (!ZS_IS_OPEN(uap_a)) { |
472 | pmz_debug("ChanA interrupt while open !\n"); | |
473 | goto skip_a; | |
474 | } | |
1da177e4 LT |
475 | write_zsreg(uap_a, R0, RES_H_IUS); |
476 | zssync(uap_a); | |
1f7b5fff FT |
477 | if (r3 & CHAEXT) |
478 | pmz_status_handle(uap_a); | |
1da177e4 | 479 | if (r3 & CHARxIP) |
7d12e780 | 480 | tty = pmz_receive_chars(uap_a); |
1f7b5fff FT |
481 | if (r3 & CHATxIP) |
482 | pmz_transmit_chars(uap_a); | |
483 | rc = IRQ_HANDLED; | |
484 | } | |
a79dd5ae | 485 | skip_a: |
1f7b5fff | 486 | spin_unlock(&uap_a->port.lock); |
1da177e4 LT |
487 | if (tty != NULL) |
488 | tty_flip_buffer_push(tty); | |
489 | ||
a79dd5ae | 490 | if (!uap_b) |
1da177e4 LT |
491 | goto out; |
492 | ||
1f7b5fff | 493 | spin_lock(&uap_b->port.lock); |
1da177e4 LT |
494 | tty = NULL; |
495 | if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { | |
a79dd5ae BH |
496 | if (!ZS_IS_OPEN(uap_a)) { |
497 | pmz_debug("ChanB interrupt while open !\n"); | |
498 | goto skip_b; | |
499 | } | |
1da177e4 LT |
500 | write_zsreg(uap_b, R0, RES_H_IUS); |
501 | zssync(uap_b); | |
1f7b5fff FT |
502 | if (r3 & CHBEXT) |
503 | pmz_status_handle(uap_b); | |
504 | if (r3 & CHBRxIP) | |
505 | tty = pmz_receive_chars(uap_b); | |
506 | if (r3 & CHBTxIP) | |
507 | pmz_transmit_chars(uap_b); | |
508 | rc = IRQ_HANDLED; | |
509 | } | |
a79dd5ae | 510 | skip_b: |
1f7b5fff | 511 | spin_unlock(&uap_b->port.lock); |
1da177e4 LT |
512 | if (tty != NULL) |
513 | tty_flip_buffer_push(tty); | |
514 | ||
515 | out: | |
1da177e4 LT |
516 | return rc; |
517 | } | |
518 | ||
519 | /* | |
520 | * Peek the status register, lock not held by caller | |
521 | */ | |
522 | static inline u8 pmz_peek_status(struct uart_pmac_port *uap) | |
523 | { | |
524 | unsigned long flags; | |
525 | u8 status; | |
526 | ||
527 | spin_lock_irqsave(&uap->port.lock, flags); | |
528 | status = read_zsreg(uap, R0); | |
529 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
530 | ||
531 | return status; | |
532 | } | |
533 | ||
534 | /* | |
535 | * Check if transmitter is empty | |
536 | * The port lock is not held. | |
537 | */ | |
538 | static unsigned int pmz_tx_empty(struct uart_port *port) | |
539 | { | |
1da177e4 LT |
540 | unsigned char status; |
541 | ||
1da177e4 LT |
542 | status = pmz_peek_status(to_pmz(port)); |
543 | if (status & Tx_BUF_EMP) | |
544 | return TIOCSER_TEMT; | |
545 | return 0; | |
546 | } | |
547 | ||
548 | /* | |
549 | * Set Modem Control (RTS & DTR) bits | |
550 | * The port lock is held and interrupts are disabled. | |
551 | * Note: Shall we really filter out RTS on external ports or | |
552 | * should that be dealt at higher level only ? | |
553 | */ | |
554 | static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
555 | { | |
556 | struct uart_pmac_port *uap = to_pmz(port); | |
557 | unsigned char set_bits, clear_bits; | |
558 | ||
559 | /* Do nothing for irda for now... */ | |
560 | if (ZS_IS_IRDA(uap)) | |
561 | return; | |
562 | /* We get called during boot with a port not up yet */ | |
a79dd5ae | 563 | if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap))) |
1da177e4 LT |
564 | return; |
565 | ||
566 | set_bits = clear_bits = 0; | |
567 | ||
568 | if (ZS_IS_INTMODEM(uap)) { | |
569 | if (mctrl & TIOCM_RTS) | |
570 | set_bits |= RTS; | |
571 | else | |
572 | clear_bits |= RTS; | |
573 | } | |
574 | if (mctrl & TIOCM_DTR) | |
575 | set_bits |= DTR; | |
576 | else | |
577 | clear_bits |= DTR; | |
578 | ||
579 | /* NOTE: Not subject to 'transmitter active' rule. */ | |
580 | uap->curregs[R5] |= set_bits; | |
581 | uap->curregs[R5] &= ~clear_bits; | |
a79dd5ae | 582 | |
1da177e4 LT |
583 | write_zsreg(uap, R5, uap->curregs[R5]); |
584 | pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n", | |
585 | set_bits, clear_bits, uap->curregs[R5]); | |
586 | zssync(uap); | |
587 | } | |
588 | ||
589 | /* | |
590 | * Get Modem Control bits (only the input ones, the core will | |
591 | * or that with a cached value of the control ones) | |
c5f4644e | 592 | * The port lock is held and interrupts are disabled. |
1da177e4 LT |
593 | */ |
594 | static unsigned int pmz_get_mctrl(struct uart_port *port) | |
595 | { | |
596 | struct uart_pmac_port *uap = to_pmz(port); | |
597 | unsigned char status; | |
598 | unsigned int ret; | |
599 | ||
c5f4644e | 600 | status = read_zsreg(uap, R0); |
1da177e4 LT |
601 | |
602 | ret = 0; | |
603 | if (status & DCD) | |
604 | ret |= TIOCM_CAR; | |
605 | if (status & SYNC_HUNT) | |
606 | ret |= TIOCM_DSR; | |
607 | if (!(status & CTS)) | |
608 | ret |= TIOCM_CTS; | |
609 | ||
610 | return ret; | |
611 | } | |
612 | ||
613 | /* | |
614 | * Stop TX side. Dealt like sunzilog at next Tx interrupt, | |
b129a8cc | 615 | * though for DMA, we will have to do a bit more. |
1da177e4 LT |
616 | * The port lock is held and interrupts are disabled. |
617 | */ | |
b129a8cc | 618 | static void pmz_stop_tx(struct uart_port *port) |
1da177e4 LT |
619 | { |
620 | to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED; | |
621 | } | |
622 | ||
623 | /* | |
624 | * Kick the Tx side. | |
625 | * The port lock is held and interrupts are disabled. | |
626 | */ | |
b129a8cc | 627 | static void pmz_start_tx(struct uart_port *port) |
1da177e4 LT |
628 | { |
629 | struct uart_pmac_port *uap = to_pmz(port); | |
630 | unsigned char status; | |
631 | ||
632 | pmz_debug("pmz: start_tx()\n"); | |
633 | ||
634 | uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; | |
635 | uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; | |
636 | ||
1da177e4 LT |
637 | status = read_zsreg(uap, R0); |
638 | ||
639 | /* TX busy? Just wait for the TX done interrupt. */ | |
640 | if (!(status & Tx_BUF_EMP)) | |
641 | return; | |
642 | ||
643 | /* Send the first character to jump-start the TX done | |
644 | * IRQ sending engine. | |
645 | */ | |
646 | if (port->x_char) { | |
647 | write_zsdata(uap, port->x_char); | |
648 | zssync(uap); | |
649 | port->icount.tx++; | |
650 | port->x_char = 0; | |
651 | } else { | |
ebd2c8f6 | 652 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 LT |
653 | |
654 | write_zsdata(uap, xmit->buf[xmit->tail]); | |
655 | zssync(uap); | |
656 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
657 | port->icount.tx++; | |
658 | ||
659 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
660 | uart_write_wakeup(&uap->port); | |
661 | } | |
662 | pmz_debug("pmz: start_tx() done.\n"); | |
663 | } | |
664 | ||
665 | /* | |
666 | * Stop Rx side, basically disable emitting of | |
667 | * Rx interrupts on the port. We don't disable the rx | |
668 | * side of the chip proper though | |
669 | * The port lock is held. | |
670 | */ | |
671 | static void pmz_stop_rx(struct uart_port *port) | |
672 | { | |
673 | struct uart_pmac_port *uap = to_pmz(port); | |
674 | ||
1da177e4 LT |
675 | pmz_debug("pmz: stop_rx()()\n"); |
676 | ||
677 | /* Disable all RX interrupts. */ | |
678 | uap->curregs[R1] &= ~RxINT_MASK; | |
679 | pmz_maybe_update_regs(uap); | |
680 | ||
681 | pmz_debug("pmz: stop_rx() done.\n"); | |
682 | } | |
683 | ||
684 | /* | |
685 | * Enable modem status change interrupts | |
686 | * The port lock is held. | |
687 | */ | |
688 | static void pmz_enable_ms(struct uart_port *port) | |
689 | { | |
690 | struct uart_pmac_port *uap = to_pmz(port); | |
691 | unsigned char new_reg; | |
692 | ||
a79dd5ae | 693 | if (ZS_IS_IRDA(uap)) |
1da177e4 LT |
694 | return; |
695 | new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); | |
696 | if (new_reg != uap->curregs[R15]) { | |
697 | uap->curregs[R15] = new_reg; | |
698 | ||
1f7b5fff | 699 | /* NOTE: Not subject to 'transmitter active' rule. */ |
1da177e4 LT |
700 | write_zsreg(uap, R15, uap->curregs[R15]); |
701 | } | |
702 | } | |
703 | ||
704 | /* | |
705 | * Control break state emission | |
706 | * The port lock is not held. | |
707 | */ | |
708 | static void pmz_break_ctl(struct uart_port *port, int break_state) | |
709 | { | |
710 | struct uart_pmac_port *uap = to_pmz(port); | |
711 | unsigned char set_bits, clear_bits, new_reg; | |
712 | unsigned long flags; | |
713 | ||
1da177e4 LT |
714 | set_bits = clear_bits = 0; |
715 | ||
716 | if (break_state) | |
717 | set_bits |= SND_BRK; | |
718 | else | |
719 | clear_bits |= SND_BRK; | |
720 | ||
721 | spin_lock_irqsave(&port->lock, flags); | |
722 | ||
723 | new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; | |
724 | if (new_reg != uap->curregs[R5]) { | |
725 | uap->curregs[R5] = new_reg; | |
1da177e4 LT |
726 | write_zsreg(uap, R5, uap->curregs[R5]); |
727 | } | |
728 | ||
729 | spin_unlock_irqrestore(&port->lock, flags); | |
730 | } | |
731 | ||
ec9cbe09 FT |
732 | #ifdef CONFIG_PPC_PMAC |
733 | ||
1da177e4 LT |
734 | /* |
735 | * Turn power on or off to the SCC and associated stuff | |
736 | * (port drivers, modem, IR port, etc.) | |
737 | * Returns the number of milliseconds we should wait before | |
738 | * trying to use the port. | |
739 | */ | |
740 | static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) | |
741 | { | |
742 | int delay = 0; | |
743 | int rc; | |
744 | ||
745 | if (state) { | |
746 | rc = pmac_call_feature( | |
747 | PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1); | |
748 | pmz_debug("port power on result: %d\n", rc); | |
749 | if (ZS_IS_INTMODEM(uap)) { | |
750 | rc = pmac_call_feature( | |
751 | PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1); | |
752 | delay = 2500; /* wait for 2.5s before using */ | |
753 | pmz_debug("modem power result: %d\n", rc); | |
754 | } | |
755 | } else { | |
756 | /* TODO: Make that depend on a timer, don't power down | |
757 | * immediately | |
758 | */ | |
759 | if (ZS_IS_INTMODEM(uap)) { | |
760 | rc = pmac_call_feature( | |
761 | PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0); | |
762 | pmz_debug("port power off result: %d\n", rc); | |
763 | } | |
764 | pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0); | |
765 | } | |
766 | return delay; | |
767 | } | |
768 | ||
ec9cbe09 FT |
769 | #else |
770 | ||
771 | static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) | |
772 | { | |
773 | return 0; | |
774 | } | |
775 | ||
776 | #endif /* !CONFIG_PPC_PMAC */ | |
777 | ||
1da177e4 | 778 | /* |
25985edc | 779 | * FixZeroBug....Works around a bug in the SCC receiving channel. |
1da177e4 LT |
780 | * Inspired from Darwin code, 15 Sept. 2000 -DanM |
781 | * | |
782 | * The following sequence prevents a problem that is seen with O'Hare ASICs | |
783 | * (most versions -- also with some Heathrow and Hydra ASICs) where a zero | |
784 | * at the input to the receiver becomes 'stuck' and locks up the receiver. | |
785 | * This problem can occur as a result of a zero bit at the receiver input | |
786 | * coincident with any of the following events: | |
787 | * | |
788 | * The SCC is initialized (hardware or software). | |
789 | * A framing error is detected. | |
790 | * The clocking option changes from synchronous or X1 asynchronous | |
791 | * clocking to X16, X32, or X64 asynchronous clocking. | |
792 | * The decoding mode is changed among NRZ, NRZI, FM0, or FM1. | |
793 | * | |
794 | * This workaround attempts to recover from the lockup condition by placing | |
795 | * the SCC in synchronous loopback mode with a fast clock before programming | |
796 | * any of the asynchronous modes. | |
797 | */ | |
798 | static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap) | |
799 | { | |
800 | write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); | |
801 | zssync(uap); | |
802 | udelay(10); | |
803 | write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV); | |
804 | zssync(uap); | |
805 | ||
806 | write_zsreg(uap, 4, X1CLK | MONSYNC); | |
807 | write_zsreg(uap, 3, Rx8); | |
808 | write_zsreg(uap, 5, Tx8 | RTS); | |
809 | write_zsreg(uap, 9, NV); /* Didn't we already do this? */ | |
810 | write_zsreg(uap, 11, RCBR | TCBR); | |
811 | write_zsreg(uap, 12, 0); | |
812 | write_zsreg(uap, 13, 0); | |
813 | write_zsreg(uap, 14, (LOOPBAK | BRSRC)); | |
814 | write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB)); | |
815 | write_zsreg(uap, 3, Rx8 | RxENABLE); | |
816 | write_zsreg(uap, 0, RES_EXT_INT); | |
817 | write_zsreg(uap, 0, RES_EXT_INT); | |
818 | write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */ | |
819 | ||
820 | /* The channel should be OK now, but it is probably receiving | |
821 | * loopback garbage. | |
822 | * Switch to asynchronous mode, disable the receiver, | |
823 | * and discard everything in the receive buffer. | |
824 | */ | |
825 | write_zsreg(uap, 9, NV); | |
826 | write_zsreg(uap, 4, X16CLK | SB_MASK); | |
827 | write_zsreg(uap, 3, Rx8); | |
828 | ||
829 | while (read_zsreg(uap, 0) & Rx_CH_AV) { | |
830 | (void)read_zsreg(uap, 8); | |
831 | write_zsreg(uap, 0, RES_EXT_INT); | |
832 | write_zsreg(uap, 0, ERR_RES); | |
833 | } | |
834 | } | |
835 | ||
836 | /* | |
837 | * Real startup routine, powers up the hardware and sets up | |
838 | * the SCC. Returns a delay in ms where you need to wait before | |
839 | * actually using the port, this is typically the internal modem | |
840 | * powerup delay. This routine expect the lock to be taken. | |
841 | */ | |
842 | static int __pmz_startup(struct uart_pmac_port *uap) | |
843 | { | |
844 | int pwr_delay = 0; | |
845 | ||
846 | memset(&uap->curregs, 0, sizeof(uap->curregs)); | |
847 | ||
848 | /* Power up the SCC & underlying hardware (modem/irda) */ | |
849 | pwr_delay = pmz_set_scc_power(uap, 1); | |
850 | ||
851 | /* Nice buggy HW ... */ | |
852 | pmz_fix_zero_bug_scc(uap); | |
853 | ||
854 | /* Reset the channel */ | |
855 | uap->curregs[R9] = 0; | |
856 | write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); | |
857 | zssync(uap); | |
858 | udelay(10); | |
859 | write_zsreg(uap, 9, 0); | |
860 | zssync(uap); | |
861 | ||
862 | /* Clear the interrupt registers */ | |
863 | write_zsreg(uap, R1, 0); | |
864 | write_zsreg(uap, R0, ERR_RES); | |
865 | write_zsreg(uap, R0, ERR_RES); | |
866 | write_zsreg(uap, R0, RES_H_IUS); | |
867 | write_zsreg(uap, R0, RES_H_IUS); | |
868 | ||
869 | /* Setup some valid baud rate */ | |
870 | uap->curregs[R4] = X16CLK | SB1; | |
871 | uap->curregs[R3] = Rx8; | |
872 | uap->curregs[R5] = Tx8 | RTS; | |
873 | if (!ZS_IS_IRDA(uap)) | |
874 | uap->curregs[R5] |= DTR; | |
875 | uap->curregs[R12] = 0; | |
876 | uap->curregs[R13] = 0; | |
877 | uap->curregs[R14] = BRENAB; | |
878 | ||
879 | /* Clear handshaking, enable BREAK interrupts */ | |
880 | uap->curregs[R15] = BRKIE; | |
881 | ||
882 | /* Master interrupt enable */ | |
883 | uap->curregs[R9] |= NV | MIE; | |
884 | ||
885 | pmz_load_zsregs(uap, uap->curregs); | |
886 | ||
887 | /* Enable receiver and transmitter. */ | |
888 | write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE); | |
889 | write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); | |
890 | ||
891 | /* Remember status for DCD/CTS changes */ | |
892 | uap->prev_status = read_zsreg(uap, R0); | |
893 | ||
1da177e4 LT |
894 | return pwr_delay; |
895 | } | |
896 | ||
897 | static void pmz_irda_reset(struct uart_pmac_port *uap) | |
898 | { | |
a79dd5ae BH |
899 | unsigned long flags; |
900 | ||
901 | spin_lock_irqsave(&uap->port.lock, flags); | |
1da177e4 LT |
902 | uap->curregs[R5] |= DTR; |
903 | write_zsreg(uap, R5, uap->curregs[R5]); | |
904 | zssync(uap); | |
a79dd5ae BH |
905 | spin_unlock_irqrestore(&uap->port.lock, flags); |
906 | msleep(110); | |
907 | ||
908 | spin_lock_irqsave(&uap->port.lock, flags); | |
1da177e4 LT |
909 | uap->curregs[R5] &= ~DTR; |
910 | write_zsreg(uap, R5, uap->curregs[R5]); | |
911 | zssync(uap); | |
a79dd5ae BH |
912 | spin_unlock_irqrestore(&uap->port.lock, flags); |
913 | msleep(10); | |
1da177e4 LT |
914 | } |
915 | ||
916 | /* | |
917 | * This is the "normal" startup routine, using the above one | |
918 | * wrapped with the lock and doing a schedule delay | |
919 | */ | |
920 | static int pmz_startup(struct uart_port *port) | |
921 | { | |
922 | struct uart_pmac_port *uap = to_pmz(port); | |
923 | unsigned long flags; | |
924 | int pwr_delay = 0; | |
925 | ||
926 | pmz_debug("pmz: startup()\n"); | |
927 | ||
1da177e4 LT |
928 | uap->flags |= PMACZILOG_FLAG_IS_OPEN; |
929 | ||
930 | /* A console is never powered down. Else, power up and | |
931 | * initialize the chip | |
932 | */ | |
933 | if (!ZS_IS_CONS(uap)) { | |
934 | spin_lock_irqsave(&port->lock, flags); | |
935 | pwr_delay = __pmz_startup(uap); | |
936 | spin_unlock_irqrestore(&port->lock, flags); | |
937 | } | |
a79dd5ae | 938 | sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line); |
ec9cbe09 | 939 | if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, |
a79dd5ae | 940 | uap->irq_name, uap)) { |
ec9cbe09 | 941 | pmz_error("Unable to register zs interrupt handler.\n"); |
1da177e4 | 942 | pmz_set_scc_power(uap, 0); |
1da177e4 LT |
943 | return -ENXIO; |
944 | } | |
945 | ||
1da177e4 LT |
946 | /* Right now, we deal with delay by blocking here, I'll be |
947 | * smarter later on | |
948 | */ | |
949 | if (pwr_delay != 0) { | |
950 | pmz_debug("pmz: delaying %d ms\n", pwr_delay); | |
951 | msleep(pwr_delay); | |
952 | } | |
953 | ||
954 | /* IrDA reset is done now */ | |
955 | if (ZS_IS_IRDA(uap)) | |
956 | pmz_irda_reset(uap); | |
957 | ||
7cf82b1b | 958 | /* Enable interrupt requests for the channel */ |
1da177e4 | 959 | spin_lock_irqsave(&port->lock, flags); |
7cf82b1b | 960 | pmz_interrupt_control(uap, 1); |
1f7b5fff | 961 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
962 | |
963 | pmz_debug("pmz: startup() done.\n"); | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
968 | static void pmz_shutdown(struct uart_port *port) | |
969 | { | |
970 | struct uart_pmac_port *uap = to_pmz(port); | |
971 | unsigned long flags; | |
972 | ||
973 | pmz_debug("pmz: shutdown()\n"); | |
974 | ||
7cf82b1b FT |
975 | spin_lock_irqsave(&port->lock, flags); |
976 | ||
a79dd5ae BH |
977 | /* Disable interrupt requests for the channel */ |
978 | pmz_interrupt_control(uap, 0); | |
7cf82b1b | 979 | |
a79dd5ae BH |
980 | if (!ZS_IS_CONS(uap)) { |
981 | /* Disable receiver and transmitter */ | |
982 | uap->curregs[R3] &= ~RxENABLE; | |
983 | uap->curregs[R5] &= ~TxENABLE; | |
7cf82b1b | 984 | |
a79dd5ae BH |
985 | /* Disable break assertion */ |
986 | uap->curregs[R5] &= ~SND_BRK; | |
987 | pmz_maybe_update_regs(uap); | |
7cf82b1b FT |
988 | } |
989 | ||
990 | spin_unlock_irqrestore(&port->lock, flags); | |
991 | ||
1da177e4 | 992 | /* Release interrupt handler */ |
1f7b5fff | 993 | free_irq(uap->port.irq, uap); |
1da177e4 LT |
994 | |
995 | spin_lock_irqsave(&port->lock, flags); | |
996 | ||
997 | uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; | |
998 | ||
a79dd5ae | 999 | if (!ZS_IS_CONS(uap)) |
7cf82b1b | 1000 | pmz_set_scc_power(uap, 0); /* Shut the chip down */ |
1da177e4 LT |
1001 | |
1002 | spin_unlock_irqrestore(&port->lock, flags); | |
1003 | ||
1da177e4 LT |
1004 | pmz_debug("pmz: shutdown() done.\n"); |
1005 | } | |
1006 | ||
1007 | /* Shared by TTY driver and serial console setup. The port lock is held | |
1008 | * and local interrupts are disabled. | |
1009 | */ | |
1010 | static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, | |
1011 | unsigned int iflag, unsigned long baud) | |
1012 | { | |
1013 | int brg; | |
1014 | ||
1da177e4 LT |
1015 | /* Switch to external clocking for IrDA high clock rates. That |
1016 | * code could be re-used for Midi interfaces with different | |
1017 | * multipliers | |
1018 | */ | |
1019 | if (baud >= 115200 && ZS_IS_IRDA(uap)) { | |
1020 | uap->curregs[R4] = X1CLK; | |
1021 | uap->curregs[R11] = RCTRxCP | TCTRxCP; | |
1022 | uap->curregs[R14] = 0; /* BRG off */ | |
1023 | uap->curregs[R12] = 0; | |
1024 | uap->curregs[R13] = 0; | |
1025 | uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; | |
1026 | } else { | |
1027 | switch (baud) { | |
1028 | case ZS_CLOCK/16: /* 230400 */ | |
1029 | uap->curregs[R4] = X16CLK; | |
1030 | uap->curregs[R11] = 0; | |
1031 | uap->curregs[R14] = 0; | |
1032 | break; | |
1033 | case ZS_CLOCK/32: /* 115200 */ | |
1034 | uap->curregs[R4] = X32CLK; | |
1035 | uap->curregs[R11] = 0; | |
1036 | uap->curregs[R14] = 0; | |
1037 | break; | |
1038 | default: | |
1039 | uap->curregs[R4] = X16CLK; | |
1040 | uap->curregs[R11] = TCBR | RCBR; | |
1041 | brg = BPS_TO_BRG(baud, ZS_CLOCK / 16); | |
1042 | uap->curregs[R12] = (brg & 255); | |
1043 | uap->curregs[R13] = ((brg >> 8) & 255); | |
1044 | uap->curregs[R14] = BRENAB; | |
1045 | } | |
1046 | uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; | |
1047 | } | |
1048 | ||
1049 | /* Character size, stop bits, and parity. */ | |
1050 | uap->curregs[3] &= ~RxN_MASK; | |
1051 | uap->curregs[5] &= ~TxN_MASK; | |
1052 | ||
1053 | switch (cflag & CSIZE) { | |
1054 | case CS5: | |
1055 | uap->curregs[3] |= Rx5; | |
1056 | uap->curregs[5] |= Tx5; | |
1057 | uap->parity_mask = 0x1f; | |
1058 | break; | |
1059 | case CS6: | |
1060 | uap->curregs[3] |= Rx6; | |
1061 | uap->curregs[5] |= Tx6; | |
1062 | uap->parity_mask = 0x3f; | |
1063 | break; | |
1064 | case CS7: | |
1065 | uap->curregs[3] |= Rx7; | |
1066 | uap->curregs[5] |= Tx7; | |
1067 | uap->parity_mask = 0x7f; | |
1068 | break; | |
1069 | case CS8: | |
1070 | default: | |
1071 | uap->curregs[3] |= Rx8; | |
1072 | uap->curregs[5] |= Tx8; | |
1073 | uap->parity_mask = 0xff; | |
1074 | break; | |
1075 | }; | |
1076 | uap->curregs[4] &= ~(SB_MASK); | |
1077 | if (cflag & CSTOPB) | |
1078 | uap->curregs[4] |= SB2; | |
1079 | else | |
1080 | uap->curregs[4] |= SB1; | |
1081 | if (cflag & PARENB) | |
1082 | uap->curregs[4] |= PAR_ENAB; | |
1083 | else | |
1084 | uap->curregs[4] &= ~PAR_ENAB; | |
1085 | if (!(cflag & PARODD)) | |
1086 | uap->curregs[4] |= PAR_EVEN; | |
1087 | else | |
1088 | uap->curregs[4] &= ~PAR_EVEN; | |
1089 | ||
1090 | uap->port.read_status_mask = Rx_OVR; | |
1091 | if (iflag & INPCK) | |
1092 | uap->port.read_status_mask |= CRC_ERR | PAR_ERR; | |
1093 | if (iflag & (BRKINT | PARMRK)) | |
1094 | uap->port.read_status_mask |= BRK_ABRT; | |
1095 | ||
1096 | uap->port.ignore_status_mask = 0; | |
1097 | if (iflag & IGNPAR) | |
1098 | uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; | |
1099 | if (iflag & IGNBRK) { | |
1100 | uap->port.ignore_status_mask |= BRK_ABRT; | |
1101 | if (iflag & IGNPAR) | |
1102 | uap->port.ignore_status_mask |= Rx_OVR; | |
1103 | } | |
1104 | ||
1105 | if ((cflag & CREAD) == 0) | |
1106 | uap->port.ignore_status_mask = 0xff; | |
1107 | } | |
1108 | ||
1109 | ||
1110 | /* | |
1111 | * Set the irda codec on the imac to the specified baud rate. | |
1112 | */ | |
1113 | static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) | |
1114 | { | |
1115 | u8 cmdbyte; | |
1116 | int t, version; | |
1117 | ||
1118 | switch (*baud) { | |
1119 | /* SIR modes */ | |
1120 | case 2400: | |
1121 | cmdbyte = 0x53; | |
1122 | break; | |
1123 | case 4800: | |
1124 | cmdbyte = 0x52; | |
1125 | break; | |
1126 | case 9600: | |
1127 | cmdbyte = 0x51; | |
1128 | break; | |
1129 | case 19200: | |
1130 | cmdbyte = 0x50; | |
1131 | break; | |
1132 | case 38400: | |
1133 | cmdbyte = 0x4f; | |
1134 | break; | |
1135 | case 57600: | |
1136 | cmdbyte = 0x4e; | |
1137 | break; | |
1138 | case 115200: | |
1139 | cmdbyte = 0x4d; | |
1140 | break; | |
1141 | /* The FIR modes aren't really supported at this point, how | |
1142 | * do we select the speed ? via the FCR on KeyLargo ? | |
1143 | */ | |
1144 | case 1152000: | |
1145 | cmdbyte = 0; | |
1146 | break; | |
1147 | case 4000000: | |
1148 | cmdbyte = 0; | |
1149 | break; | |
1150 | default: /* 9600 */ | |
1151 | cmdbyte = 0x51; | |
1152 | *baud = 9600; | |
1153 | break; | |
1154 | } | |
1155 | ||
1156 | /* Wait for transmitter to drain */ | |
1157 | t = 10000; | |
1158 | while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0 | |
1159 | || (read_zsreg(uap, R1) & ALL_SNT) == 0) { | |
1160 | if (--t <= 0) { | |
ec9cbe09 | 1161 | pmz_error("transmitter didn't drain\n"); |
1da177e4 LT |
1162 | return; |
1163 | } | |
1164 | udelay(10); | |
1165 | } | |
1166 | ||
1167 | /* Drain the receiver too */ | |
1168 | t = 100; | |
1169 | (void)read_zsdata(uap); | |
1170 | (void)read_zsdata(uap); | |
1171 | (void)read_zsdata(uap); | |
1172 | mdelay(10); | |
1173 | while (read_zsreg(uap, R0) & Rx_CH_AV) { | |
1174 | read_zsdata(uap); | |
1175 | mdelay(10); | |
1176 | if (--t <= 0) { | |
ec9cbe09 | 1177 | pmz_error("receiver didn't drain\n"); |
1da177e4 LT |
1178 | return; |
1179 | } | |
1180 | } | |
1181 | ||
1182 | /* Switch to command mode */ | |
1183 | uap->curregs[R5] |= DTR; | |
1184 | write_zsreg(uap, R5, uap->curregs[R5]); | |
1185 | zssync(uap); | |
1f7b5fff | 1186 | mdelay(1); |
1da177e4 LT |
1187 | |
1188 | /* Switch SCC to 19200 */ | |
1189 | pmz_convert_to_zs(uap, CS8, 0, 19200); | |
1190 | pmz_load_zsregs(uap, uap->curregs); | |
1f7b5fff | 1191 | mdelay(1); |
1da177e4 LT |
1192 | |
1193 | /* Write get_version command byte */ | |
1194 | write_zsdata(uap, 1); | |
1195 | t = 5000; | |
1196 | while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { | |
1197 | if (--t <= 0) { | |
ec9cbe09 | 1198 | pmz_error("irda_setup timed out on get_version byte\n"); |
1da177e4 LT |
1199 | goto out; |
1200 | } | |
1201 | udelay(10); | |
1202 | } | |
1203 | version = read_zsdata(uap); | |
1204 | ||
1205 | if (version < 4) { | |
ec9cbe09 | 1206 | pmz_info("IrDA: dongle version %d not supported\n", version); |
1da177e4 LT |
1207 | goto out; |
1208 | } | |
1209 | ||
1210 | /* Send speed mode */ | |
1211 | write_zsdata(uap, cmdbyte); | |
1212 | t = 5000; | |
1213 | while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { | |
1214 | if (--t <= 0) { | |
ec9cbe09 | 1215 | pmz_error("irda_setup timed out on speed mode byte\n"); |
1da177e4 LT |
1216 | goto out; |
1217 | } | |
1218 | udelay(10); | |
1219 | } | |
1220 | t = read_zsdata(uap); | |
1221 | if (t != cmdbyte) | |
ec9cbe09 | 1222 | pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte); |
1da177e4 | 1223 | |
ec9cbe09 | 1224 | pmz_info("IrDA setup for %ld bps, dongle version: %d\n", |
1da177e4 LT |
1225 | *baud, version); |
1226 | ||
1227 | (void)read_zsdata(uap); | |
1228 | (void)read_zsdata(uap); | |
1229 | (void)read_zsdata(uap); | |
1230 | ||
1231 | out: | |
1232 | /* Switch back to data mode */ | |
1233 | uap->curregs[R5] &= ~DTR; | |
1234 | write_zsreg(uap, R5, uap->curregs[R5]); | |
1235 | zssync(uap); | |
1236 | ||
1237 | (void)read_zsdata(uap); | |
1238 | (void)read_zsdata(uap); | |
1239 | (void)read_zsdata(uap); | |
1240 | } | |
1241 | ||
1242 | ||
606d099c AC |
1243 | static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios, |
1244 | struct ktermios *old) | |
1da177e4 LT |
1245 | { |
1246 | struct uart_pmac_port *uap = to_pmz(port); | |
1247 | unsigned long baud; | |
1248 | ||
1249 | pmz_debug("pmz: set_termios()\n"); | |
1250 | ||
606d099c | 1251 | memcpy(&uap->termios_cache, termios, sizeof(struct ktermios)); |
1da177e4 LT |
1252 | |
1253 | /* XXX Check which revs of machines actually allow 1 and 4Mb speeds | |
1254 | * on the IR dongle. Note that the IRTTY driver currently doesn't know | |
1255 | * about the FIR mode and high speed modes. So these are unused. For | |
1256 | * implementing proper support for these, we should probably add some | |
1257 | * DMA as well, at least on the Rx side, which isn't a simple thing | |
1258 | * at this point. | |
1259 | */ | |
1260 | if (ZS_IS_IRDA(uap)) { | |
1261 | /* Calc baud rate */ | |
1262 | baud = uart_get_baud_rate(port, termios, old, 1200, 4000000); | |
1263 | pmz_debug("pmz: switch IRDA to %ld bauds\n", baud); | |
1264 | /* Cet the irda codec to the right rate */ | |
1265 | pmz_irda_setup(uap, &baud); | |
1266 | /* Set final baud rate */ | |
1267 | pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); | |
1268 | pmz_load_zsregs(uap, uap->curregs); | |
1269 | zssync(uap); | |
1270 | } else { | |
1271 | baud = uart_get_baud_rate(port, termios, old, 1200, 230400); | |
1272 | pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); | |
1273 | /* Make sure modem status interrupts are correctly configured */ | |
1274 | if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) { | |
1275 | uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE; | |
1276 | uap->flags |= PMACZILOG_FLAG_MODEM_STATUS; | |
1277 | } else { | |
1278 | uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE); | |
1279 | uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS; | |
1280 | } | |
1281 | ||
1282 | /* Load registers to the chip */ | |
1283 | pmz_maybe_update_regs(uap); | |
1284 | } | |
1285 | uart_update_timeout(port, termios->c_cflag, baud); | |
1286 | ||
1287 | pmz_debug("pmz: set_termios() done.\n"); | |
1288 | } | |
1289 | ||
1290 | /* The port lock is not held. */ | |
606d099c AC |
1291 | static void pmz_set_termios(struct uart_port *port, struct ktermios *termios, |
1292 | struct ktermios *old) | |
1da177e4 LT |
1293 | { |
1294 | struct uart_pmac_port *uap = to_pmz(port); | |
1295 | unsigned long flags; | |
1296 | ||
1297 | spin_lock_irqsave(&port->lock, flags); | |
1298 | ||
1299 | /* Disable IRQs on the port */ | |
7cf82b1b | 1300 | pmz_interrupt_control(uap, 0); |
1da177e4 LT |
1301 | |
1302 | /* Setup new port configuration */ | |
1303 | __pmz_set_termios(port, termios, old); | |
1304 | ||
1305 | /* Re-enable IRQs on the port */ | |
7cf82b1b FT |
1306 | if (ZS_IS_OPEN(uap)) |
1307 | pmz_interrupt_control(uap, 1); | |
1308 | ||
1da177e4 LT |
1309 | spin_unlock_irqrestore(&port->lock, flags); |
1310 | } | |
1311 | ||
1312 | static const char *pmz_type(struct uart_port *port) | |
1313 | { | |
1314 | struct uart_pmac_port *uap = to_pmz(port); | |
1315 | ||
1316 | if (ZS_IS_IRDA(uap)) | |
1317 | return "Z85c30 ESCC - Infrared port"; | |
1318 | else if (ZS_IS_INTMODEM(uap)) | |
1319 | return "Z85c30 ESCC - Internal modem"; | |
1320 | return "Z85c30 ESCC - Serial port"; | |
1321 | } | |
1322 | ||
1323 | /* We do not request/release mappings of the registers here, this | |
1324 | * happens at early serial probe time. | |
1325 | */ | |
1326 | static void pmz_release_port(struct uart_port *port) | |
1327 | { | |
1328 | } | |
1329 | ||
1330 | static int pmz_request_port(struct uart_port *port) | |
1331 | { | |
1332 | return 0; | |
1333 | } | |
1334 | ||
1335 | /* These do not need to do anything interesting either. */ | |
1336 | static void pmz_config_port(struct uart_port *port, int flags) | |
1337 | { | |
1338 | } | |
1339 | ||
1340 | /* We do not support letting the user mess with the divisor, IRQ, etc. */ | |
1341 | static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1342 | { | |
1343 | return -EINVAL; | |
1344 | } | |
1345 | ||
8c653186 CA |
1346 | #ifdef CONFIG_CONSOLE_POLL |
1347 | ||
1348 | static int pmz_poll_get_char(struct uart_port *port) | |
1349 | { | |
1350 | struct uart_pmac_port *uap = (struct uart_pmac_port *)port; | |
1351 | ||
1352 | while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) | |
1353 | udelay(5); | |
1354 | return read_zsdata(uap); | |
1355 | } | |
1356 | ||
1357 | static void pmz_poll_put_char(struct uart_port *port, unsigned char c) | |
1358 | { | |
1359 | struct uart_pmac_port *uap = (struct uart_pmac_port *)port; | |
1360 | ||
1361 | /* Wait for the transmit buffer to empty. */ | |
1362 | while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) | |
1363 | udelay(5); | |
1364 | write_zsdata(uap, c); | |
1365 | } | |
1366 | ||
ec9cbe09 | 1367 | #endif /* CONFIG_CONSOLE_POLL */ |
8c653186 | 1368 | |
1da177e4 LT |
1369 | static struct uart_ops pmz_pops = { |
1370 | .tx_empty = pmz_tx_empty, | |
1371 | .set_mctrl = pmz_set_mctrl, | |
1372 | .get_mctrl = pmz_get_mctrl, | |
1373 | .stop_tx = pmz_stop_tx, | |
1374 | .start_tx = pmz_start_tx, | |
1375 | .stop_rx = pmz_stop_rx, | |
1376 | .enable_ms = pmz_enable_ms, | |
1377 | .break_ctl = pmz_break_ctl, | |
1378 | .startup = pmz_startup, | |
1379 | .shutdown = pmz_shutdown, | |
1380 | .set_termios = pmz_set_termios, | |
1381 | .type = pmz_type, | |
1382 | .release_port = pmz_release_port, | |
1383 | .request_port = pmz_request_port, | |
1384 | .config_port = pmz_config_port, | |
1385 | .verify_port = pmz_verify_port, | |
8c653186 CA |
1386 | #ifdef CONFIG_CONSOLE_POLL |
1387 | .poll_get_char = pmz_poll_get_char, | |
1388 | .poll_put_char = pmz_poll_put_char, | |
1389 | #endif | |
1da177e4 LT |
1390 | }; |
1391 | ||
ec9cbe09 FT |
1392 | #ifdef CONFIG_PPC_PMAC |
1393 | ||
1da177e4 LT |
1394 | /* |
1395 | * Setup one port structure after probing, HW is down at this point, | |
1396 | * Unlike sunzilog, we don't need to pre-init the spinlock as we don't | |
1397 | * register our console before uart_add_one_port() is called | |
1398 | */ | |
1399 | static int __init pmz_init_port(struct uart_pmac_port *uap) | |
1400 | { | |
1401 | struct device_node *np = uap->node; | |
018a3d1d JK |
1402 | const char *conn; |
1403 | const struct slot_names_prop { | |
1da177e4 LT |
1404 | int count; |
1405 | char name[1]; | |
1406 | } *slots; | |
1407 | int len; | |
cc5d0189 | 1408 | struct resource r_ports, r_rxdma, r_txdma; |
1da177e4 LT |
1409 | |
1410 | /* | |
1411 | * Request & map chip registers | |
1412 | */ | |
cc5d0189 BH |
1413 | if (of_address_to_resource(np, 0, &r_ports)) |
1414 | return -ENODEV; | |
1415 | uap->port.mapbase = r_ports.start; | |
1da177e4 | 1416 | uap->port.membase = ioremap(uap->port.mapbase, 0x1000); |
1f7b5fff | 1417 | |
1da177e4 LT |
1418 | uap->control_reg = uap->port.membase; |
1419 | uap->data_reg = uap->control_reg + 0x10; | |
1420 | ||
1421 | /* | |
1422 | * Request & map DBDMA registers | |
1423 | */ | |
1424 | #ifdef HAS_DBDMA | |
cc5d0189 BH |
1425 | if (of_address_to_resource(np, 1, &r_txdma) == 0 && |
1426 | of_address_to_resource(np, 2, &r_rxdma) == 0) | |
1da177e4 | 1427 | uap->flags |= PMACZILOG_FLAG_HAS_DMA; |
cc5d0189 BH |
1428 | #else |
1429 | memset(&r_txdma, 0, sizeof(struct resource)); | |
1430 | memset(&r_rxdma, 0, sizeof(struct resource)); | |
1da177e4 LT |
1431 | #endif |
1432 | if (ZS_HAS_DMA(uap)) { | |
cc5d0189 | 1433 | uap->tx_dma_regs = ioremap(r_txdma.start, 0x100); |
1da177e4 LT |
1434 | if (uap->tx_dma_regs == NULL) { |
1435 | uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; | |
1436 | goto no_dma; | |
1437 | } | |
cc5d0189 | 1438 | uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100); |
1da177e4 LT |
1439 | if (uap->rx_dma_regs == NULL) { |
1440 | iounmap(uap->tx_dma_regs); | |
1441 | uap->tx_dma_regs = NULL; | |
1442 | uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; | |
1443 | goto no_dma; | |
1444 | } | |
0ebfff14 BH |
1445 | uap->tx_dma_irq = irq_of_parse_and_map(np, 1); |
1446 | uap->rx_dma_irq = irq_of_parse_and_map(np, 2); | |
1da177e4 LT |
1447 | } |
1448 | no_dma: | |
1449 | ||
1450 | /* | |
1451 | * Detect port type | |
1452 | */ | |
55b61fec | 1453 | if (of_device_is_compatible(np, "cobalt")) |
1da177e4 | 1454 | uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; |
40cd3a45 | 1455 | conn = of_get_property(np, "AAPL,connector", &len); |
1da177e4 LT |
1456 | if (conn && (strcmp(conn, "infrared") == 0)) |
1457 | uap->flags |= PMACZILOG_FLAG_IS_IRDA; | |
1458 | uap->port_type = PMAC_SCC_ASYNC; | |
1459 | /* 1999 Powerbook G3 has slot-names property instead */ | |
40cd3a45 | 1460 | slots = of_get_property(np, "slot-names", &len); |
1da177e4 LT |
1461 | if (slots && slots->count > 0) { |
1462 | if (strcmp(slots->name, "IrDA") == 0) | |
1463 | uap->flags |= PMACZILOG_FLAG_IS_IRDA; | |
1464 | else if (strcmp(slots->name, "Modem") == 0) | |
1465 | uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; | |
1466 | } | |
1467 | if (ZS_IS_IRDA(uap)) | |
1468 | uap->port_type = PMAC_SCC_IRDA; | |
1469 | if (ZS_IS_INTMODEM(uap)) { | |
30686ba6 SR |
1470 | struct device_node* i2c_modem = |
1471 | of_find_node_by_name(NULL, "i2c-modem"); | |
1da177e4 | 1472 | if (i2c_modem) { |
018a3d1d | 1473 | const char* mid = |
40cd3a45 | 1474 | of_get_property(i2c_modem, "modem-id", NULL); |
1da177e4 LT |
1475 | if (mid) switch(*mid) { |
1476 | case 0x04 : | |
1477 | case 0x05 : | |
1478 | case 0x07 : | |
1479 | case 0x08 : | |
1480 | case 0x0b : | |
1481 | case 0x0c : | |
1482 | uap->port_type = PMAC_SCC_I2S1; | |
1483 | } | |
1484 | printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n", | |
1485 | mid ? (*mid) : 0); | |
30686ba6 | 1486 | of_node_put(i2c_modem); |
1da177e4 LT |
1487 | } else { |
1488 | printk(KERN_INFO "pmac_zilog: serial modem detected\n"); | |
1489 | } | |
1490 | } | |
1491 | ||
1492 | /* | |
1493 | * Init remaining bits of "port" structure | |
1494 | */ | |
9b4a1617 | 1495 | uap->port.iotype = UPIO_MEM; |
0ebfff14 | 1496 | uap->port.irq = irq_of_parse_and_map(np, 0); |
1da177e4 LT |
1497 | uap->port.uartclk = ZS_CLOCK; |
1498 | uap->port.fifosize = 1; | |
1499 | uap->port.ops = &pmz_pops; | |
1500 | uap->port.type = PORT_PMAC_ZILOG; | |
1501 | uap->port.flags = 0; | |
1502 | ||
f08b7e9f BH |
1503 | /* |
1504 | * Fixup for the port on Gatwick for which the device-tree has | |
1505 | * missing interrupts. Normally, the macio_dev would contain | |
1506 | * fixed up interrupt info, but we use the device-tree directly | |
1507 | * here due to early probing so we need the fixup too. | |
1508 | */ | |
1509 | if (uap->port.irq == NO_IRQ && | |
1510 | np->parent && np->parent->parent && | |
1511 | of_device_is_compatible(np->parent->parent, "gatwick")) { | |
1512 | /* IRQs on gatwick are offset by 64 */ | |
1513 | uap->port.irq = irq_create_mapping(NULL, 64 + 15); | |
1514 | uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4); | |
1515 | uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5); | |
1516 | } | |
1517 | ||
1da177e4 LT |
1518 | /* Setup some valid baud rate information in the register |
1519 | * shadows so we don't write crap there before baud rate is | |
1520 | * first initialized. | |
1521 | */ | |
1522 | pmz_convert_to_zs(uap, CS8, 0, 9600); | |
1523 | ||
1524 | return 0; | |
1525 | } | |
1526 | ||
1527 | /* | |
1528 | * Get rid of a port on module removal | |
1529 | */ | |
1530 | static void pmz_dispose_port(struct uart_pmac_port *uap) | |
1531 | { | |
1532 | struct device_node *np; | |
1533 | ||
1534 | np = uap->node; | |
1535 | iounmap(uap->rx_dma_regs); | |
1536 | iounmap(uap->tx_dma_regs); | |
1537 | iounmap(uap->control_reg); | |
1538 | uap->node = NULL; | |
1539 | of_node_put(np); | |
1540 | memset(uap, 0, sizeof(struct uart_pmac_port)); | |
1541 | } | |
1542 | ||
1543 | /* | |
1f7b5fff | 1544 | * Called upon match with an escc node in the device-tree. |
1da177e4 | 1545 | */ |
5e655772 | 1546 | static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match) |
1da177e4 | 1547 | { |
a79dd5ae | 1548 | struct uart_pmac_port *uap; |
1da177e4 LT |
1549 | int i; |
1550 | ||
1551 | /* Iterate the pmz_ports array to find a matching entry | |
1552 | */ | |
1553 | for (i = 0; i < MAX_ZS_PORTS; i++) | |
a79dd5ae BH |
1554 | if (pmz_ports[i].node == mdev->ofdev.dev.of_node) |
1555 | break; | |
1556 | if (i >= MAX_ZS_PORTS) | |
1557 | return -ENODEV; | |
1558 | ||
1559 | ||
1560 | uap = &pmz_ports[i]; | |
1561 | uap->dev = mdev; | |
1562 | uap->port.dev = &mdev->ofdev.dev; | |
1563 | dev_set_drvdata(&mdev->ofdev.dev, uap); | |
1564 | ||
1565 | /* We still activate the port even when failing to request resources | |
1566 | * to work around bugs in ancient Apple device-trees | |
1567 | */ | |
1568 | if (macio_request_resources(uap->dev, "pmac_zilog")) | |
1569 | printk(KERN_WARNING "%s: Failed to request resource" | |
1570 | ", port still active\n", | |
1571 | uap->node->name); | |
1572 | else | |
1573 | uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; | |
1574 | ||
1575 | return uart_add_one_port(&pmz_uart_reg, &uap->port); | |
1da177e4 LT |
1576 | } |
1577 | ||
1578 | /* | |
1579 | * That one should not be called, macio isn't really a hotswap device, | |
1580 | * we don't expect one of those serial ports to go away... | |
1581 | */ | |
1582 | static int pmz_detach(struct macio_dev *mdev) | |
1583 | { | |
1584 | struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); | |
1585 | ||
1586 | if (!uap) | |
1587 | return -ENODEV; | |
1588 | ||
a79dd5ae BH |
1589 | uart_remove_one_port(&pmz_uart_reg, &uap->port); |
1590 | ||
1da177e4 LT |
1591 | if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { |
1592 | macio_release_resources(uap->dev); | |
1593 | uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; | |
1594 | } | |
1595 | dev_set_drvdata(&mdev->ofdev.dev, NULL); | |
1596 | uap->dev = NULL; | |
a79dd5ae | 1597 | uap->port.dev = NULL; |
1da177e4 LT |
1598 | |
1599 | return 0; | |
1600 | } | |
1601 | ||
1602 | ||
0370affe | 1603 | static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state) |
1da177e4 LT |
1604 | { |
1605 | struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); | |
1da177e4 LT |
1606 | |
1607 | if (uap == NULL) { | |
1608 | printk("HRM... pmz_suspend with NULL uap\n"); | |
1609 | return 0; | |
1610 | } | |
1611 | ||
a79dd5ae | 1612 | uart_suspend_port(&pmz_uart_reg, &uap->port); |
1da177e4 LT |
1613 | |
1614 | return 0; | |
1615 | } | |
1616 | ||
1617 | ||
1618 | static int pmz_resume(struct macio_dev *mdev) | |
1619 | { | |
1620 | struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); | |
1da177e4 LT |
1621 | |
1622 | if (uap == NULL) | |
1623 | return 0; | |
1624 | ||
a79dd5ae | 1625 | uart_resume_port(&pmz_uart_reg, &uap->port); |
1da177e4 LT |
1626 | |
1627 | return 0; | |
1628 | } | |
1629 | ||
1630 | /* | |
1631 | * Probe all ports in the system and build the ports array, we register | |
a79dd5ae BH |
1632 | * with the serial layer later, so we get a proper struct device which |
1633 | * allows the tty to attach properly. This is later than it used to be | |
1634 | * but the tty layer really wants it that way. | |
1da177e4 LT |
1635 | */ |
1636 | static int __init pmz_probe(void) | |
1637 | { | |
1638 | struct device_node *node_p, *node_a, *node_b, *np; | |
1639 | int count = 0; | |
1640 | int rc; | |
1641 | ||
1642 | /* | |
1643 | * Find all escc chips in the system | |
1644 | */ | |
1645 | node_p = of_find_node_by_name(NULL, "escc"); | |
1646 | while (node_p) { | |
1647 | /* | |
1648 | * First get channel A/B node pointers | |
1649 | * | |
1650 | * TODO: Add routines with proper locking to do that... | |
1651 | */ | |
1652 | node_a = node_b = NULL; | |
1653 | for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) { | |
1654 | if (strncmp(np->name, "ch-a", 4) == 0) | |
1655 | node_a = of_node_get(np); | |
1656 | else if (strncmp(np->name, "ch-b", 4) == 0) | |
1657 | node_b = of_node_get(np); | |
1658 | } | |
1659 | if (!node_a && !node_b) { | |
1660 | of_node_put(node_a); | |
1661 | of_node_put(node_b); | |
1662 | printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n", | |
1663 | (!node_a) ? 'a' : 'b', node_p->full_name); | |
1664 | goto next; | |
1665 | } | |
1666 | ||
1667 | /* | |
1668 | * Fill basic fields in the port structures | |
1669 | */ | |
a79dd5ae BH |
1670 | if (node_b != NULL) { |
1671 | pmz_ports[count].mate = &pmz_ports[count+1]; | |
1672 | pmz_ports[count+1].mate = &pmz_ports[count]; | |
1673 | } | |
1da177e4 LT |
1674 | pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A; |
1675 | pmz_ports[count].node = node_a; | |
1676 | pmz_ports[count+1].node = node_b; | |
1677 | pmz_ports[count].port.line = count; | |
1f7b5fff | 1678 | pmz_ports[count+1].port.line = count+1; |
1da177e4 LT |
1679 | |
1680 | /* | |
1681 | * Setup the ports for real | |
1682 | */ | |
1683 | rc = pmz_init_port(&pmz_ports[count]); | |
1684 | if (rc == 0 && node_b != NULL) | |
1685 | rc = pmz_init_port(&pmz_ports[count+1]); | |
1686 | if (rc != 0) { | |
1687 | of_node_put(node_a); | |
1688 | of_node_put(node_b); | |
1689 | memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port)); | |
1690 | memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port)); | |
1691 | goto next; | |
1692 | } | |
1693 | count += 2; | |
1694 | next: | |
1695 | node_p = of_find_node_by_name(node_p, "escc"); | |
1696 | } | |
1697 | pmz_ports_count = count; | |
1698 | ||
1699 | return 0; | |
1700 | } | |
1701 | ||
ec9cbe09 FT |
1702 | #else |
1703 | ||
1704 | extern struct platform_device scc_a_pdev, scc_b_pdev; | |
1705 | ||
1706 | static int __init pmz_init_port(struct uart_pmac_port *uap) | |
1707 | { | |
1708 | struct resource *r_ports; | |
1709 | int irq; | |
1710 | ||
a79dd5ae BH |
1711 | r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0); |
1712 | irq = platform_get_irq(uap->pdev, 0); | |
ec9cbe09 FT |
1713 | if (!r_ports || !irq) |
1714 | return -ENODEV; | |
1715 | ||
1716 | uap->port.mapbase = r_ports->start; | |
1717 | uap->port.membase = (unsigned char __iomem *) r_ports->start; | |
1718 | uap->port.iotype = UPIO_MEM; | |
1719 | uap->port.irq = irq; | |
1720 | uap->port.uartclk = ZS_CLOCK; | |
1721 | uap->port.fifosize = 1; | |
1722 | uap->port.ops = &pmz_pops; | |
1723 | uap->port.type = PORT_PMAC_ZILOG; | |
1724 | uap->port.flags = 0; | |
1725 | ||
1726 | uap->control_reg = uap->port.membase; | |
1727 | uap->data_reg = uap->control_reg + 4; | |
1728 | uap->port_type = 0; | |
1729 | ||
1730 | pmz_convert_to_zs(uap, CS8, 0, 9600); | |
1731 | ||
1732 | return 0; | |
1733 | } | |
1734 | ||
1735 | static int __init pmz_probe(void) | |
1736 | { | |
1737 | int err; | |
1738 | ||
1739 | pmz_ports_count = 0; | |
1740 | ||
ec9cbe09 FT |
1741 | pmz_ports[0].port.line = 0; |
1742 | pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A; | |
a79dd5ae | 1743 | pmz_ports[0].pdev = &scc_a_pdev; |
ec9cbe09 FT |
1744 | err = pmz_init_port(&pmz_ports[0]); |
1745 | if (err) | |
1746 | return err; | |
1747 | pmz_ports_count++; | |
1748 | ||
a79dd5ae | 1749 | pmz_ports[0].mate = &pmz_ports[1]; |
ec9cbe09 FT |
1750 | pmz_ports[1].mate = &pmz_ports[0]; |
1751 | pmz_ports[1].port.line = 1; | |
1752 | pmz_ports[1].flags = 0; | |
a79dd5ae | 1753 | pmz_ports[1].pdev = &scc_b_pdev; |
ec9cbe09 FT |
1754 | err = pmz_init_port(&pmz_ports[1]); |
1755 | if (err) | |
1756 | return err; | |
1757 | pmz_ports_count++; | |
1758 | ||
1759 | return 0; | |
1760 | } | |
1761 | ||
1762 | static void pmz_dispose_port(struct uart_pmac_port *uap) | |
1763 | { | |
1764 | memset(uap, 0, sizeof(struct uart_pmac_port)); | |
1765 | } | |
1766 | ||
1767 | static int __init pmz_attach(struct platform_device *pdev) | |
1768 | { | |
a79dd5ae | 1769 | struct uart_pmac_port *uap; |
ec9cbe09 FT |
1770 | int i; |
1771 | ||
a79dd5ae | 1772 | /* Iterate the pmz_ports array to find a matching entry */ |
ec9cbe09 | 1773 | for (i = 0; i < pmz_ports_count; i++) |
a79dd5ae BH |
1774 | if (pmz_ports[i].pdev == pdev) |
1775 | break; | |
1776 | if (i >= pmz_ports_count) | |
1777 | return -ENODEV; | |
1778 | ||
1779 | uap = &pmz_ports[i]; | |
1780 | uap->port.dev = &pdev->dev; | |
1781 | platform_set_drvdata(pdev, uap); | |
1782 | ||
1783 | return uart_add_one_port(&pmz_uart_reg, &uap->port); | |
ec9cbe09 FT |
1784 | } |
1785 | ||
1786 | static int __exit pmz_detach(struct platform_device *pdev) | |
1787 | { | |
a79dd5ae BH |
1788 | struct uart_pmac_port *uap = platform_get_drvdata(pdev); |
1789 | ||
1790 | if (!uap) | |
1791 | return -ENODEV; | |
1792 | ||
1793 | uart_remove_one_port(&pmz_uart_reg, &uap->port); | |
1794 | ||
1795 | platform_set_drvdata(pdev, NULL); | |
1796 | uap->port.dev = NULL; | |
1797 | ||
ec9cbe09 FT |
1798 | return 0; |
1799 | } | |
1800 | ||
1801 | #endif /* !CONFIG_PPC_PMAC */ | |
1802 | ||
1da177e4 LT |
1803 | #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE |
1804 | ||
1805 | static void pmz_console_write(struct console *con, const char *s, unsigned int count); | |
1806 | static int __init pmz_console_setup(struct console *co, char *options); | |
1807 | ||
1808 | static struct console pmz_console = { | |
e4533b24 | 1809 | .name = PMACZILOG_NAME, |
1da177e4 LT |
1810 | .write = pmz_console_write, |
1811 | .device = uart_console_device, | |
1812 | .setup = pmz_console_setup, | |
1813 | .flags = CON_PRINTBUFFER, | |
1814 | .index = -1, | |
1815 | .data = &pmz_uart_reg, | |
1816 | }; | |
1817 | ||
1818 | #define PMACZILOG_CONSOLE &pmz_console | |
1819 | #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ | |
1820 | #define PMACZILOG_CONSOLE (NULL) | |
1821 | #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ | |
1822 | ||
1823 | /* | |
1824 | * Register the driver, console driver and ports with the serial | |
1825 | * core | |
1826 | */ | |
1827 | static int __init pmz_register(void) | |
1828 | { | |
1da177e4 LT |
1829 | pmz_uart_reg.nr = pmz_ports_count; |
1830 | pmz_uart_reg.cons = PMACZILOG_CONSOLE; | |
1da177e4 LT |
1831 | |
1832 | /* | |
1833 | * Register this driver with the serial core | |
1834 | */ | |
a79dd5ae | 1835 | return uart_register_driver(&pmz_uart_reg); |
1da177e4 LT |
1836 | } |
1837 | ||
ec9cbe09 FT |
1838 | #ifdef CONFIG_PPC_PMAC |
1839 | ||
5e655772 | 1840 | static struct of_device_id pmz_match[] = |
1da177e4 LT |
1841 | { |
1842 | { | |
1f7b5fff | 1843 | .name = "ch-a", |
1da177e4 LT |
1844 | }, |
1845 | { | |
1f7b5fff | 1846 | .name = "ch-b", |
1da177e4 LT |
1847 | }, |
1848 | {}, | |
1849 | }; | |
5e655772 | 1850 | MODULE_DEVICE_TABLE (of, pmz_match); |
1da177e4 | 1851 | |
1f7b5fff | 1852 | static struct macio_driver pmz_driver = { |
c2cdf6ab BH |
1853 | .driver = { |
1854 | .name = "pmac_zilog", | |
1855 | .owner = THIS_MODULE, | |
1856 | .of_match_table = pmz_match, | |
1857 | }, | |
1da177e4 LT |
1858 | .probe = pmz_attach, |
1859 | .remove = pmz_detach, | |
1860 | .suspend = pmz_suspend, | |
1f7b5fff | 1861 | .resume = pmz_resume, |
1da177e4 LT |
1862 | }; |
1863 | ||
ec9cbe09 FT |
1864 | #else |
1865 | ||
1866 | static struct platform_driver pmz_driver = { | |
1867 | .remove = __exit_p(pmz_detach), | |
1868 | .driver = { | |
1869 | .name = "scc", | |
1870 | .owner = THIS_MODULE, | |
1871 | }, | |
1872 | }; | |
1873 | ||
1874 | #endif /* !CONFIG_PPC_PMAC */ | |
1875 | ||
1da177e4 LT |
1876 | static int __init init_pmz(void) |
1877 | { | |
1878 | int rc, i; | |
1879 | printk(KERN_INFO "%s\n", version); | |
1880 | ||
1881 | /* | |
1882 | * First, we need to do a direct OF-based probe pass. We | |
1883 | * do that because we want serial console up before the | |
1884 | * macio stuffs calls us back, and since that makes it | |
1885 | * easier to pass the proper number of channels to | |
1886 | * uart_register_driver() | |
1887 | */ | |
1888 | if (pmz_ports_count == 0) | |
1889 | pmz_probe(); | |
1890 | ||
1891 | /* | |
1892 | * Bail early if no port found | |
1893 | */ | |
1894 | if (pmz_ports_count == 0) | |
1895 | return -ENODEV; | |
1896 | ||
1897 | /* | |
1898 | * Now we register with the serial layer | |
1899 | */ | |
1900 | rc = pmz_register(); | |
1901 | if (rc) { | |
1902 | printk(KERN_ERR | |
1903 | "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n" | |
1904 | "pmac_zilog: Did another serial driver already claim the minors?\n"); | |
1905 | /* effectively "pmz_unprobe()" */ | |
1906 | for (i=0; i < pmz_ports_count; i++) | |
1907 | pmz_dispose_port(&pmz_ports[i]); | |
1908 | return rc; | |
1909 | } | |
1f7b5fff | 1910 | |
1da177e4 LT |
1911 | /* |
1912 | * Then we register the macio driver itself | |
1913 | */ | |
ec9cbe09 | 1914 | #ifdef CONFIG_PPC_PMAC |
1da177e4 | 1915 | return macio_register_driver(&pmz_driver); |
ec9cbe09 FT |
1916 | #else |
1917 | return platform_driver_probe(&pmz_driver, pmz_attach); | |
1918 | #endif | |
1da177e4 LT |
1919 | } |
1920 | ||
1921 | static void __exit exit_pmz(void) | |
1922 | { | |
1923 | int i; | |
1924 | ||
ec9cbe09 | 1925 | #ifdef CONFIG_PPC_PMAC |
1da177e4 LT |
1926 | /* Get rid of macio-driver (detach from macio) */ |
1927 | macio_unregister_driver(&pmz_driver); | |
ec9cbe09 FT |
1928 | #else |
1929 | platform_driver_unregister(&pmz_driver); | |
1930 | #endif | |
1da177e4 LT |
1931 | |
1932 | for (i = 0; i < pmz_ports_count; i++) { | |
1933 | struct uart_pmac_port *uport = &pmz_ports[i]; | |
a79dd5ae BH |
1934 | #ifdef CONFIG_PPC_PMAC |
1935 | if (uport->node != NULL) | |
1da177e4 | 1936 | pmz_dispose_port(uport); |
a79dd5ae BH |
1937 | #else |
1938 | if (uport->pdev != NULL) | |
1939 | pmz_dispose_port(uport); | |
1940 | #endif | |
1da177e4 LT |
1941 | } |
1942 | /* Unregister UART driver */ | |
1943 | uart_unregister_driver(&pmz_uart_reg); | |
1944 | } | |
1945 | ||
1946 | #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE | |
1947 | ||
d358788f RK |
1948 | static void pmz_console_putchar(struct uart_port *port, int ch) |
1949 | { | |
1950 | struct uart_pmac_port *uap = (struct uart_pmac_port *)port; | |
1951 | ||
1952 | /* Wait for the transmit buffer to empty. */ | |
1953 | while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) | |
1954 | udelay(5); | |
1955 | write_zsdata(uap, ch); | |
1956 | } | |
1957 | ||
1da177e4 LT |
1958 | /* |
1959 | * Print a string to the serial port trying not to disturb | |
1960 | * any possible real use of the port... | |
1961 | */ | |
1962 | static void pmz_console_write(struct console *con, const char *s, unsigned int count) | |
1963 | { | |
1964 | struct uart_pmac_port *uap = &pmz_ports[con->index]; | |
1965 | unsigned long flags; | |
1da177e4 | 1966 | |
1da177e4 LT |
1967 | spin_lock_irqsave(&uap->port.lock, flags); |
1968 | ||
1969 | /* Turn of interrupts and enable the transmitter. */ | |
1970 | write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); | |
1971 | write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); | |
1972 | ||
d358788f | 1973 | uart_console_write(&uap->port, s, count, pmz_console_putchar); |
1da177e4 LT |
1974 | |
1975 | /* Restore the values in the registers. */ | |
1976 | write_zsreg(uap, R1, uap->curregs[1]); | |
1977 | /* Don't disable the transmitter. */ | |
1978 | ||
1979 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
1980 | } | |
1981 | ||
1982 | /* | |
1983 | * Setup the serial console | |
1984 | */ | |
1985 | static int __init pmz_console_setup(struct console *co, char *options) | |
1986 | { | |
1987 | struct uart_pmac_port *uap; | |
1988 | struct uart_port *port; | |
1989 | int baud = 38400; | |
1990 | int bits = 8; | |
1991 | int parity = 'n'; | |
1992 | int flow = 'n'; | |
1993 | unsigned long pwr_delay; | |
1994 | ||
1995 | /* | |
1996 | * XServe's default to 57600 bps | |
1997 | */ | |
71a157e8 GL |
1998 | if (of_machine_is_compatible("RackMac1,1") |
1999 | || of_machine_is_compatible("RackMac1,2") | |
2000 | || of_machine_is_compatible("MacRISC4")) | |
1f7b5fff | 2001 | baud = 57600; |
1da177e4 LT |
2002 | |
2003 | /* | |
2004 | * Check whether an invalid uart number has been specified, and | |
2005 | * if so, search for the first available port that does have | |
2006 | * console support. | |
2007 | */ | |
2008 | if (co->index >= pmz_ports_count) | |
2009 | co->index = 0; | |
2010 | uap = &pmz_ports[co->index]; | |
a79dd5ae | 2011 | #ifdef CONFIG_PPC_PMAC |
1da177e4 LT |
2012 | if (uap->node == NULL) |
2013 | return -ENODEV; | |
a79dd5ae BH |
2014 | #else |
2015 | if (uap->pdev == NULL) | |
2016 | return -ENODEV; | |
2017 | #endif | |
1da177e4 LT |
2018 | port = &uap->port; |
2019 | ||
2020 | /* | |
2021 | * Mark port as beeing a console | |
2022 | */ | |
2023 | uap->flags |= PMACZILOG_FLAG_IS_CONS; | |
2024 | ||
2025 | /* | |
2026 | * Temporary fix for uart layer who didn't setup the spinlock yet | |
2027 | */ | |
2028 | spin_lock_init(&port->lock); | |
2029 | ||
2030 | /* | |
2031 | * Enable the hardware | |
2032 | */ | |
2033 | pwr_delay = __pmz_startup(uap); | |
2034 | if (pwr_delay) | |
2035 | mdelay(pwr_delay); | |
2036 | ||
2037 | if (options) | |
2038 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2039 | ||
2040 | return uart_set_options(port, co, baud, parity, bits, flow); | |
2041 | } | |
2042 | ||
2043 | static int __init pmz_console_init(void) | |
2044 | { | |
2045 | /* Probe ports */ | |
2046 | pmz_probe(); | |
2047 | ||
2048 | /* TODO: Autoprobe console based on OF */ | |
2049 | /* pmz_console.index = i; */ | |
2050 | register_console(&pmz_console); | |
2051 | ||
2052 | return 0; | |
2053 | ||
2054 | } | |
2055 | console_initcall(pmz_console_init); | |
2056 | #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ | |
2057 | ||
2058 | module_init(init_pmz); | |
2059 | module_exit(exit_pmz); |