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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Based on drivers/serial/8250.c by Russell King. |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Feb 20, 2003 | |
6 | * Copyright: (C) 2003 Monta Vista Software, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * Note 1: This driver is made separate from the already too overloaded | |
14 | * 8250.c because it needs some kirks of its own and that'll make it | |
15 | * easier to add DMA support. | |
16 | * | |
17 | * Note 2: I'm too sick of device allocation policies for serial ports. | |
18 | * If someone else wants to request an "official" allocation of major/minor | |
19 | * for this driver please be my guest. And don't forget that new hardware | |
20 | * to come from Intel might have more than 3 or 4 of those UARTs. Let's | |
21 | * hope for a better port registration and dynamic device allocation scheme | |
22 | * with the serial core maintainer satisfaction to appear soon. | |
23 | */ | |
24 | ||
1da177e4 LT |
25 | |
26 | #if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
27 | #define SUPPORT_SYSRQ | |
28 | #endif | |
29 | ||
30 | #include <linux/module.h> | |
31 | #include <linux/ioport.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/console.h> | |
34 | #include <linux/sysrq.h> | |
35 | #include <linux/serial_reg.h> | |
36 | #include <linux/circ_buf.h> | |
37 | #include <linux/delay.h> | |
38 | #include <linux/interrupt.h> | |
699c20f3 | 39 | #include <linux/of.h> |
d052d1be | 40 | #include <linux/platform_device.h> |
1da177e4 LT |
41 | #include <linux/tty.h> |
42 | #include <linux/tty_flip.h> | |
43 | #include <linux/serial_core.h> | |
b049bd9d | 44 | #include <linux/clk.h> |
290a5589 | 45 | #include <linux/io.h> |
5a0e3ad6 | 46 | #include <linux/slab.h> |
1da177e4 | 47 | |
699c20f3 HZ |
48 | #define PXA_NAME_LEN 8 |
49 | ||
1da177e4 LT |
50 | struct uart_pxa_port { |
51 | struct uart_port port; | |
52 | unsigned char ier; | |
53 | unsigned char lcr; | |
54 | unsigned char mcr; | |
55 | unsigned int lsr_break_flag; | |
b049bd9d | 56 | struct clk *clk; |
699c20f3 | 57 | char name[PXA_NAME_LEN]; |
1da177e4 LT |
58 | }; |
59 | ||
60 | static inline unsigned int serial_in(struct uart_pxa_port *up, int offset) | |
61 | { | |
62 | offset <<= 2; | |
63 | return readl(up->port.membase + offset); | |
64 | } | |
65 | ||
66 | static inline void serial_out(struct uart_pxa_port *up, int offset, int value) | |
67 | { | |
68 | offset <<= 2; | |
69 | writel(value, up->port.membase + offset); | |
70 | } | |
71 | ||
72 | static void serial_pxa_enable_ms(struct uart_port *port) | |
73 | { | |
74 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
75 | ||
76 | up->ier |= UART_IER_MSI; | |
77 | serial_out(up, UART_IER, up->ier); | |
78 | } | |
79 | ||
b129a8cc | 80 | static void serial_pxa_stop_tx(struct uart_port *port) |
1da177e4 LT |
81 | { |
82 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
83 | ||
84 | if (up->ier & UART_IER_THRI) { | |
85 | up->ier &= ~UART_IER_THRI; | |
86 | serial_out(up, UART_IER, up->ier); | |
87 | } | |
88 | } | |
89 | ||
90 | static void serial_pxa_stop_rx(struct uart_port *port) | |
91 | { | |
92 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
93 | ||
94 | up->ier &= ~UART_IER_RLSI; | |
95 | up->port.read_status_mask &= ~UART_LSR_DR; | |
96 | serial_out(up, UART_IER, up->ier); | |
97 | } | |
98 | ||
7d12e780 | 99 | static inline void receive_chars(struct uart_pxa_port *up, int *status) |
1da177e4 | 100 | { |
1da177e4 LT |
101 | unsigned int ch, flag; |
102 | int max_count = 256; | |
103 | ||
104 | do { | |
e44aabd6 MF |
105 | /* work around Errata #20 according to |
106 | * Intel(R) PXA27x Processor Family | |
107 | * Specification Update (May 2005) | |
108 | * | |
109 | * Step 2 | |
110 | * Disable the Reciever Time Out Interrupt via IER[RTOEI] | |
111 | */ | |
112 | up->ier &= ~UART_IER_RTOIE; | |
113 | serial_out(up, UART_IER, up->ier); | |
114 | ||
1da177e4 LT |
115 | ch = serial_in(up, UART_RX); |
116 | flag = TTY_NORMAL; | |
117 | up->port.icount.rx++; | |
118 | ||
119 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | | |
120 | UART_LSR_FE | UART_LSR_OE))) { | |
121 | /* | |
122 | * For statistics only | |
123 | */ | |
124 | if (*status & UART_LSR_BI) { | |
125 | *status &= ~(UART_LSR_FE | UART_LSR_PE); | |
126 | up->port.icount.brk++; | |
127 | /* | |
128 | * We do the SysRQ and SAK checking | |
129 | * here because otherwise the break | |
130 | * may get masked by ignore_status_mask | |
131 | * or read_status_mask. | |
132 | */ | |
133 | if (uart_handle_break(&up->port)) | |
134 | goto ignore_char; | |
135 | } else if (*status & UART_LSR_PE) | |
136 | up->port.icount.parity++; | |
137 | else if (*status & UART_LSR_FE) | |
138 | up->port.icount.frame++; | |
139 | if (*status & UART_LSR_OE) | |
140 | up->port.icount.overrun++; | |
141 | ||
142 | /* | |
143 | * Mask off conditions which should be ignored. | |
144 | */ | |
145 | *status &= up->port.read_status_mask; | |
146 | ||
147 | #ifdef CONFIG_SERIAL_PXA_CONSOLE | |
148 | if (up->port.line == up->port.cons->index) { | |
149 | /* Recover the break flag from console xmit */ | |
150 | *status |= up->lsr_break_flag; | |
151 | up->lsr_break_flag = 0; | |
152 | } | |
153 | #endif | |
154 | if (*status & UART_LSR_BI) { | |
155 | flag = TTY_BREAK; | |
156 | } else if (*status & UART_LSR_PE) | |
157 | flag = TTY_PARITY; | |
158 | else if (*status & UART_LSR_FE) | |
159 | flag = TTY_FRAME; | |
160 | } | |
05ab3014 | 161 | |
7d12e780 | 162 | if (uart_handle_sysrq_char(&up->port, ch)) |
1da177e4 | 163 | goto ignore_char; |
05ab3014 RK |
164 | |
165 | uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag); | |
166 | ||
1da177e4 LT |
167 | ignore_char: |
168 | *status = serial_in(up, UART_LSR); | |
169 | } while ((*status & UART_LSR_DR) && (max_count-- > 0)); | |
2e124b4a | 170 | tty_flip_buffer_push(&up->port.state->port); |
e44aabd6 MF |
171 | |
172 | /* work around Errata #20 according to | |
173 | * Intel(R) PXA27x Processor Family | |
174 | * Specification Update (May 2005) | |
175 | * | |
176 | * Step 6: | |
177 | * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE] | |
178 | */ | |
179 | up->ier |= UART_IER_RTOIE; | |
180 | serial_out(up, UART_IER, up->ier); | |
1da177e4 LT |
181 | } |
182 | ||
183 | static void transmit_chars(struct uart_pxa_port *up) | |
184 | { | |
ebd2c8f6 | 185 | struct circ_buf *xmit = &up->port.state->xmit; |
1da177e4 LT |
186 | int count; |
187 | ||
188 | if (up->port.x_char) { | |
189 | serial_out(up, UART_TX, up->port.x_char); | |
190 | up->port.icount.tx++; | |
191 | up->port.x_char = 0; | |
192 | return; | |
193 | } | |
194 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
b129a8cc | 195 | serial_pxa_stop_tx(&up->port); |
1da177e4 LT |
196 | return; |
197 | } | |
198 | ||
199 | count = up->port.fifosize / 2; | |
200 | do { | |
201 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
202 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
203 | up->port.icount.tx++; | |
204 | if (uart_circ_empty(xmit)) | |
205 | break; | |
206 | } while (--count > 0); | |
207 | ||
208 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
209 | uart_write_wakeup(&up->port); | |
210 | ||
211 | ||
212 | if (uart_circ_empty(xmit)) | |
b129a8cc | 213 | serial_pxa_stop_tx(&up->port); |
1da177e4 LT |
214 | } |
215 | ||
b129a8cc | 216 | static void serial_pxa_start_tx(struct uart_port *port) |
1da177e4 LT |
217 | { |
218 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
219 | ||
220 | if (!(up->ier & UART_IER_THRI)) { | |
221 | up->ier |= UART_IER_THRI; | |
222 | serial_out(up, UART_IER, up->ier); | |
223 | } | |
224 | } | |
225 | ||
50d1e7d1 | 226 | /* should hold up->port.lock */ |
1da177e4 LT |
227 | static inline void check_modem_status(struct uart_pxa_port *up) |
228 | { | |
229 | int status; | |
230 | ||
231 | status = serial_in(up, UART_MSR); | |
232 | ||
233 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
234 | return; | |
235 | ||
236 | if (status & UART_MSR_TERI) | |
237 | up->port.icount.rng++; | |
238 | if (status & UART_MSR_DDSR) | |
239 | up->port.icount.dsr++; | |
240 | if (status & UART_MSR_DDCD) | |
241 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | |
242 | if (status & UART_MSR_DCTS) | |
243 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | |
244 | ||
bdc04e31 | 245 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); |
1da177e4 LT |
246 | } |
247 | ||
248 | /* | |
249 | * This handles the interrupt from one port. | |
250 | */ | |
7d12e780 | 251 | static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id) |
1da177e4 | 252 | { |
c7bec5ab | 253 | struct uart_pxa_port *up = dev_id; |
1da177e4 LT |
254 | unsigned int iir, lsr; |
255 | ||
256 | iir = serial_in(up, UART_IIR); | |
257 | if (iir & UART_IIR_NO_INT) | |
258 | return IRQ_NONE; | |
50d1e7d1 | 259 | spin_lock(&up->port.lock); |
1da177e4 LT |
260 | lsr = serial_in(up, UART_LSR); |
261 | if (lsr & UART_LSR_DR) | |
7d12e780 | 262 | receive_chars(up, &lsr); |
1da177e4 LT |
263 | check_modem_status(up); |
264 | if (lsr & UART_LSR_THRE) | |
265 | transmit_chars(up); | |
50d1e7d1 | 266 | spin_unlock(&up->port.lock); |
1da177e4 LT |
267 | return IRQ_HANDLED; |
268 | } | |
269 | ||
270 | static unsigned int serial_pxa_tx_empty(struct uart_port *port) | |
271 | { | |
272 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
273 | unsigned long flags; | |
274 | unsigned int ret; | |
275 | ||
276 | spin_lock_irqsave(&up->port.lock, flags); | |
277 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
278 | spin_unlock_irqrestore(&up->port.lock, flags); | |
279 | ||
280 | return ret; | |
281 | } | |
282 | ||
283 | static unsigned int serial_pxa_get_mctrl(struct uart_port *port) | |
284 | { | |
285 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
1da177e4 LT |
286 | unsigned char status; |
287 | unsigned int ret; | |
288 | ||
1da177e4 | 289 | status = serial_in(up, UART_MSR); |
1da177e4 LT |
290 | |
291 | ret = 0; | |
292 | if (status & UART_MSR_DCD) | |
293 | ret |= TIOCM_CAR; | |
294 | if (status & UART_MSR_RI) | |
295 | ret |= TIOCM_RNG; | |
296 | if (status & UART_MSR_DSR) | |
297 | ret |= TIOCM_DSR; | |
298 | if (status & UART_MSR_CTS) | |
299 | ret |= TIOCM_CTS; | |
300 | return ret; | |
301 | } | |
302 | ||
303 | static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
304 | { | |
305 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
306 | unsigned char mcr = 0; | |
307 | ||
308 | if (mctrl & TIOCM_RTS) | |
309 | mcr |= UART_MCR_RTS; | |
310 | if (mctrl & TIOCM_DTR) | |
311 | mcr |= UART_MCR_DTR; | |
312 | if (mctrl & TIOCM_OUT1) | |
313 | mcr |= UART_MCR_OUT1; | |
314 | if (mctrl & TIOCM_OUT2) | |
315 | mcr |= UART_MCR_OUT2; | |
316 | if (mctrl & TIOCM_LOOP) | |
317 | mcr |= UART_MCR_LOOP; | |
318 | ||
319 | mcr |= up->mcr; | |
320 | ||
321 | serial_out(up, UART_MCR, mcr); | |
322 | } | |
323 | ||
324 | static void serial_pxa_break_ctl(struct uart_port *port, int break_state) | |
325 | { | |
326 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
327 | unsigned long flags; | |
328 | ||
329 | spin_lock_irqsave(&up->port.lock, flags); | |
330 | if (break_state == -1) | |
331 | up->lcr |= UART_LCR_SBC; | |
332 | else | |
333 | up->lcr &= ~UART_LCR_SBC; | |
334 | serial_out(up, UART_LCR, up->lcr); | |
335 | spin_unlock_irqrestore(&up->port.lock, flags); | |
336 | } | |
337 | ||
1da177e4 LT |
338 | static int serial_pxa_startup(struct uart_port *port) |
339 | { | |
340 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
341 | unsigned long flags; | |
342 | int retval; | |
343 | ||
d9e29649 MR |
344 | if (port->line == 3) /* HWUART */ |
345 | up->mcr |= UART_MCR_AFE; | |
346 | else | |
f02aa3f9 | 347 | up->mcr = 0; |
1da177e4 | 348 | |
b049bd9d RK |
349 | up->port.uartclk = clk_get_rate(up->clk); |
350 | ||
1da177e4 LT |
351 | /* |
352 | * Allocate the IRQ | |
353 | */ | |
354 | retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up); | |
355 | if (retval) | |
356 | return retval; | |
357 | ||
358 | /* | |
359 | * Clear the FIFO buffers and disable them. | |
360 | * (they will be reenabled in set_termios()) | |
361 | */ | |
362 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
363 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
364 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
365 | serial_out(up, UART_FCR, 0); | |
366 | ||
367 | /* | |
368 | * Clear the interrupt registers. | |
369 | */ | |
370 | (void) serial_in(up, UART_LSR); | |
371 | (void) serial_in(up, UART_RX); | |
372 | (void) serial_in(up, UART_IIR); | |
373 | (void) serial_in(up, UART_MSR); | |
374 | ||
375 | /* | |
376 | * Now, initialize the UART | |
377 | */ | |
378 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
379 | ||
380 | spin_lock_irqsave(&up->port.lock, flags); | |
381 | up->port.mctrl |= TIOCM_OUT2; | |
382 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
383 | spin_unlock_irqrestore(&up->port.lock, flags); | |
384 | ||
385 | /* | |
386 | * Finally, enable interrupts. Note: Modem status interrupts | |
80f7228b | 387 | * are set via set_termios(), which will be occurring imminently |
1da177e4 LT |
388 | * anyway, so we don't enable them here. |
389 | */ | |
390 | up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE; | |
391 | serial_out(up, UART_IER, up->ier); | |
392 | ||
393 | /* | |
394 | * And clear the interrupt registers again for luck. | |
395 | */ | |
396 | (void) serial_in(up, UART_LSR); | |
397 | (void) serial_in(up, UART_RX); | |
398 | (void) serial_in(up, UART_IIR); | |
399 | (void) serial_in(up, UART_MSR); | |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
404 | static void serial_pxa_shutdown(struct uart_port *port) | |
405 | { | |
406 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
407 | unsigned long flags; | |
408 | ||
409 | free_irq(up->port.irq, up); | |
410 | ||
411 | /* | |
412 | * Disable interrupts from this port | |
413 | */ | |
414 | up->ier = 0; | |
415 | serial_out(up, UART_IER, 0); | |
416 | ||
417 | spin_lock_irqsave(&up->port.lock, flags); | |
418 | up->port.mctrl &= ~TIOCM_OUT2; | |
419 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
420 | spin_unlock_irqrestore(&up->port.lock, flags); | |
421 | ||
422 | /* | |
423 | * Disable break condition and FIFOs | |
424 | */ | |
425 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | |
426 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
427 | UART_FCR_CLEAR_RCVR | | |
428 | UART_FCR_CLEAR_XMIT); | |
429 | serial_out(up, UART_FCR, 0); | |
430 | } | |
431 | ||
432 | static void | |
606d099c AC |
433 | serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios, |
434 | struct ktermios *old) | |
1da177e4 LT |
435 | { |
436 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
437 | unsigned char cval, fcr = 0; | |
438 | unsigned long flags; | |
439 | unsigned int baud, quot; | |
c934878c | 440 | unsigned int dll; |
1da177e4 LT |
441 | |
442 | switch (termios->c_cflag & CSIZE) { | |
443 | case CS5: | |
0a8b80c5 | 444 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
445 | break; |
446 | case CS6: | |
0a8b80c5 | 447 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
448 | break; |
449 | case CS7: | |
0a8b80c5 | 450 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
451 | break; |
452 | default: | |
453 | case CS8: | |
0a8b80c5 | 454 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
455 | break; |
456 | } | |
457 | ||
458 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 459 | cval |= UART_LCR_STOP; |
1da177e4 LT |
460 | if (termios->c_cflag & PARENB) |
461 | cval |= UART_LCR_PARITY; | |
462 | if (!(termios->c_cflag & PARODD)) | |
463 | cval |= UART_LCR_EPAR; | |
464 | ||
465 | /* | |
466 | * Ask the core to calculate the divisor for us. | |
467 | */ | |
468 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
469 | quot = uart_get_divisor(port, baud); | |
470 | ||
471 | if ((up->port.uartclk / quot) < (2400 * 16)) | |
472 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1; | |
d9e29649 | 473 | else if ((up->port.uartclk / quot) < (230400 * 16)) |
1da177e4 | 474 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8; |
d9e29649 MR |
475 | else |
476 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32; | |
1da177e4 LT |
477 | |
478 | /* | |
479 | * Ok, we're now changing the port state. Do it with | |
480 | * interrupts disabled. | |
481 | */ | |
482 | spin_lock_irqsave(&up->port.lock, flags); | |
483 | ||
484 | /* | |
485 | * Ensure the port will be enabled. | |
486 | * This is required especially for serial console. | |
487 | */ | |
290a5589 | 488 | up->ier |= UART_IER_UUE; |
1da177e4 LT |
489 | |
490 | /* | |
491 | * Update the per-port timeout. | |
492 | */ | |
e6158b4a | 493 | uart_update_timeout(port, termios->c_cflag, baud); |
1da177e4 LT |
494 | |
495 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
496 | if (termios->c_iflag & INPCK) | |
497 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
ef8b9ddc | 498 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
1da177e4 LT |
499 | up->port.read_status_mask |= UART_LSR_BI; |
500 | ||
501 | /* | |
502 | * Characters to ignore | |
503 | */ | |
504 | up->port.ignore_status_mask = 0; | |
505 | if (termios->c_iflag & IGNPAR) | |
506 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
507 | if (termios->c_iflag & IGNBRK) { | |
508 | up->port.ignore_status_mask |= UART_LSR_BI; | |
509 | /* | |
510 | * If we're ignoring parity and break indicators, | |
511 | * ignore overruns too (for real raw support). | |
512 | */ | |
513 | if (termios->c_iflag & IGNPAR) | |
514 | up->port.ignore_status_mask |= UART_LSR_OE; | |
515 | } | |
516 | ||
517 | /* | |
518 | * ignore all characters if CREAD is not set | |
519 | */ | |
520 | if ((termios->c_cflag & CREAD) == 0) | |
521 | up->port.ignore_status_mask |= UART_LSR_DR; | |
522 | ||
523 | /* | |
524 | * CTS flow control flag and modem status interrupts | |
525 | */ | |
526 | up->ier &= ~UART_IER_MSI; | |
527 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
528 | up->ier |= UART_IER_MSI; | |
529 | ||
530 | serial_out(up, UART_IER, up->ier); | |
531 | ||
2276f03b RJ |
532 | if (termios->c_cflag & CRTSCTS) |
533 | up->mcr |= UART_MCR_AFE; | |
534 | else | |
535 | up->mcr &= ~UART_MCR_AFE; | |
536 | ||
c934878c | 537 | serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ |
1da177e4 | 538 | serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ |
c934878c UKK |
539 | |
540 | /* | |
541 | * work around Errata #75 according to Intel(R) PXA27x Processor Family | |
542 | * Specification Update (Nov 2005) | |
543 | */ | |
544 | dll = serial_in(up, UART_DLL); | |
545 | WARN_ON(dll != (quot & 0xff)); | |
546 | ||
1da177e4 | 547 | serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ |
c934878c | 548 | serial_out(up, UART_LCR, cval); /* reset DLAB */ |
1da177e4 LT |
549 | up->lcr = cval; /* Save LCR */ |
550 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
551 | serial_out(up, UART_FCR, fcr); | |
552 | spin_unlock_irqrestore(&up->port.lock, flags); | |
553 | } | |
554 | ||
555 | static void | |
556 | serial_pxa_pm(struct uart_port *port, unsigned int state, | |
557 | unsigned int oldstate) | |
558 | { | |
559 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
b049bd9d | 560 | |
1da177e4 | 561 | if (!state) |
fb8ebec0 | 562 | clk_prepare_enable(up->clk); |
b049bd9d | 563 | else |
fb8ebec0 | 564 | clk_disable_unprepare(up->clk); |
1da177e4 LT |
565 | } |
566 | ||
567 | static void serial_pxa_release_port(struct uart_port *port) | |
568 | { | |
569 | } | |
570 | ||
571 | static int serial_pxa_request_port(struct uart_port *port) | |
572 | { | |
573 | return 0; | |
574 | } | |
575 | ||
576 | static void serial_pxa_config_port(struct uart_port *port, int flags) | |
577 | { | |
578 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
579 | up->port.type = PORT_PXA; | |
580 | } | |
581 | ||
582 | static int | |
583 | serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser) | |
584 | { | |
585 | /* we don't want the core code to modify any port params */ | |
586 | return -EINVAL; | |
587 | } | |
588 | ||
589 | static const char * | |
590 | serial_pxa_type(struct uart_port *port) | |
591 | { | |
592 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
593 | return up->name; | |
594 | } | |
595 | ||
e259a3ae | 596 | static struct uart_pxa_port *serial_pxa_ports[4]; |
2d93486c | 597 | static struct uart_driver serial_pxa_reg; |
1da177e4 | 598 | |
fa7f1518 PZ |
599 | #ifdef CONFIG_SERIAL_PXA_CONSOLE |
600 | ||
1da177e4 LT |
601 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
602 | ||
603 | /* | |
604 | * Wait for transmitter & holding register to empty | |
605 | */ | |
be9ae5d9 | 606 | static void wait_for_xmitr(struct uart_pxa_port *up) |
1da177e4 LT |
607 | { |
608 | unsigned int status, tmout = 10000; | |
609 | ||
610 | /* Wait up to 10ms for the character(s) to be sent. */ | |
611 | do { | |
612 | status = serial_in(up, UART_LSR); | |
613 | ||
614 | if (status & UART_LSR_BI) | |
615 | up->lsr_break_flag = UART_LSR_BI; | |
616 | ||
617 | if (--tmout == 0) | |
618 | break; | |
619 | udelay(1); | |
620 | } while ((status & BOTH_EMPTY) != BOTH_EMPTY); | |
621 | ||
622 | /* Wait up to 1s for flow control if necessary */ | |
623 | if (up->port.flags & UPF_CONS_FLOW) { | |
624 | tmout = 1000000; | |
625 | while (--tmout && | |
626 | ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) | |
627 | udelay(1); | |
628 | } | |
629 | } | |
630 | ||
d358788f RK |
631 | static void serial_pxa_console_putchar(struct uart_port *port, int ch) |
632 | { | |
633 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
634 | ||
635 | wait_for_xmitr(up); | |
636 | serial_out(up, UART_TX, ch); | |
637 | } | |
638 | ||
1da177e4 LT |
639 | /* |
640 | * Print a string to the serial port trying not to disturb | |
641 | * any possible real use of the port... | |
642 | * | |
643 | * The console_lock must be held when we get here. | |
644 | */ | |
645 | static void | |
646 | serial_pxa_console_write(struct console *co, const char *s, unsigned int count) | |
647 | { | |
e259a3ae | 648 | struct uart_pxa_port *up = serial_pxa_ports[co->index]; |
1da177e4 | 649 | unsigned int ier; |
cfe275c2 CX |
650 | unsigned long flags; |
651 | int locked = 1; | |
1da177e4 | 652 | |
9429ccbf | 653 | clk_enable(up->clk); |
cfe275c2 CX |
654 | local_irq_save(flags); |
655 | if (up->port.sysrq) | |
656 | locked = 0; | |
657 | else if (oops_in_progress) | |
658 | locked = spin_trylock(&up->port.lock); | |
659 | else | |
660 | spin_lock(&up->port.lock); | |
661 | ||
1da177e4 | 662 | /* |
f02aa3f9 | 663 | * First save the IER then disable the interrupts |
1da177e4 LT |
664 | */ |
665 | ier = serial_in(up, UART_IER); | |
666 | serial_out(up, UART_IER, UART_IER_UUE); | |
667 | ||
d358788f | 668 | uart_console_write(&up->port, s, count, serial_pxa_console_putchar); |
1da177e4 LT |
669 | |
670 | /* | |
671 | * Finally, wait for transmitter to become empty | |
672 | * and restore the IER | |
673 | */ | |
674 | wait_for_xmitr(up); | |
675 | serial_out(up, UART_IER, ier); | |
b049bd9d | 676 | |
cfe275c2 CX |
677 | if (locked) |
678 | spin_unlock(&up->port.lock); | |
679 | local_irq_restore(flags); | |
9429ccbf | 680 | clk_disable(up->clk); |
cfe275c2 | 681 | |
1da177e4 LT |
682 | } |
683 | ||
e1a9c179 DL |
684 | #ifdef CONFIG_CONSOLE_POLL |
685 | /* | |
686 | * Console polling routines for writing and reading from the uart while | |
687 | * in an interrupt or debug context. | |
688 | */ | |
689 | ||
690 | static int serial_pxa_get_poll_char(struct uart_port *port) | |
691 | { | |
692 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
693 | unsigned char lsr = serial_in(up, UART_LSR); | |
694 | ||
695 | while (!(lsr & UART_LSR_DR)) | |
696 | lsr = serial_in(up, UART_LSR); | |
697 | ||
698 | return serial_in(up, UART_RX); | |
699 | } | |
700 | ||
701 | ||
702 | static void serial_pxa_put_poll_char(struct uart_port *port, | |
703 | unsigned char c) | |
704 | { | |
705 | unsigned int ier; | |
706 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
707 | ||
708 | /* | |
709 | * First save the IER then disable the interrupts | |
710 | */ | |
711 | ier = serial_in(up, UART_IER); | |
712 | serial_out(up, UART_IER, UART_IER_UUE); | |
713 | ||
714 | wait_for_xmitr(up); | |
715 | /* | |
716 | * Send the character out. | |
e1a9c179 DL |
717 | */ |
718 | serial_out(up, UART_TX, c); | |
e1a9c179 DL |
719 | |
720 | /* | |
721 | * Finally, wait for transmitter to become empty | |
722 | * and restore the IER | |
723 | */ | |
724 | wait_for_xmitr(up); | |
725 | serial_out(up, UART_IER, ier); | |
726 | } | |
727 | ||
728 | #endif /* CONFIG_CONSOLE_POLL */ | |
729 | ||
1da177e4 LT |
730 | static int __init |
731 | serial_pxa_console_setup(struct console *co, char *options) | |
732 | { | |
733 | struct uart_pxa_port *up; | |
734 | int baud = 9600; | |
735 | int bits = 8; | |
736 | int parity = 'n'; | |
737 | int flow = 'n'; | |
738 | ||
739 | if (co->index == -1 || co->index >= serial_pxa_reg.nr) | |
740 | co->index = 0; | |
e259a3ae RK |
741 | up = serial_pxa_ports[co->index]; |
742 | if (!up) | |
743 | return -ENODEV; | |
1da177e4 LT |
744 | |
745 | if (options) | |
746 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
747 | ||
748 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
749 | } | |
750 | ||
751 | static struct console serial_pxa_console = { | |
752 | .name = "ttyS", | |
753 | .write = serial_pxa_console_write, | |
754 | .device = uart_console_device, | |
755 | .setup = serial_pxa_console_setup, | |
756 | .flags = CON_PRINTBUFFER, | |
757 | .index = -1, | |
758 | .data = &serial_pxa_reg, | |
759 | }; | |
760 | ||
1da177e4 LT |
761 | #define PXA_CONSOLE &serial_pxa_console |
762 | #else | |
763 | #define PXA_CONSOLE NULL | |
764 | #endif | |
765 | ||
6c62cc0d | 766 | static struct uart_ops serial_pxa_pops = { |
1da177e4 LT |
767 | .tx_empty = serial_pxa_tx_empty, |
768 | .set_mctrl = serial_pxa_set_mctrl, | |
769 | .get_mctrl = serial_pxa_get_mctrl, | |
770 | .stop_tx = serial_pxa_stop_tx, | |
771 | .start_tx = serial_pxa_start_tx, | |
772 | .stop_rx = serial_pxa_stop_rx, | |
773 | .enable_ms = serial_pxa_enable_ms, | |
774 | .break_ctl = serial_pxa_break_ctl, | |
775 | .startup = serial_pxa_startup, | |
776 | .shutdown = serial_pxa_shutdown, | |
777 | .set_termios = serial_pxa_set_termios, | |
778 | .pm = serial_pxa_pm, | |
779 | .type = serial_pxa_type, | |
780 | .release_port = serial_pxa_release_port, | |
781 | .request_port = serial_pxa_request_port, | |
782 | .config_port = serial_pxa_config_port, | |
783 | .verify_port = serial_pxa_verify_port, | |
2ee881b7 | 784 | #if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE) |
e1a9c179 DL |
785 | .poll_get_char = serial_pxa_get_poll_char, |
786 | .poll_put_char = serial_pxa_put_poll_char, | |
787 | #endif | |
1da177e4 LT |
788 | }; |
789 | ||
1da177e4 LT |
790 | static struct uart_driver serial_pxa_reg = { |
791 | .owner = THIS_MODULE, | |
792 | .driver_name = "PXA serial", | |
1da177e4 LT |
793 | .dev_name = "ttyS", |
794 | .major = TTY_MAJOR, | |
795 | .minor = 64, | |
e259a3ae | 796 | .nr = 4, |
1da177e4 LT |
797 | .cons = PXA_CONSOLE, |
798 | }; | |
799 | ||
bf56c751 MR |
800 | #ifdef CONFIG_PM |
801 | static int serial_pxa_suspend(struct device *dev) | |
1da177e4 | 802 | { |
bf56c751 | 803 | struct uart_pxa_port *sport = dev_get_drvdata(dev); |
1da177e4 | 804 | |
9480e307 | 805 | if (sport) |
1da177e4 LT |
806 | uart_suspend_port(&serial_pxa_reg, &sport->port); |
807 | ||
808 | return 0; | |
809 | } | |
810 | ||
bf56c751 | 811 | static int serial_pxa_resume(struct device *dev) |
1da177e4 | 812 | { |
bf56c751 | 813 | struct uart_pxa_port *sport = dev_get_drvdata(dev); |
1da177e4 | 814 | |
9480e307 | 815 | if (sport) |
1da177e4 LT |
816 | uart_resume_port(&serial_pxa_reg, &sport->port); |
817 | ||
818 | return 0; | |
819 | } | |
820 | ||
47145210 | 821 | static const struct dev_pm_ops serial_pxa_pm_ops = { |
bf56c751 MR |
822 | .suspend = serial_pxa_suspend, |
823 | .resume = serial_pxa_resume, | |
824 | }; | |
825 | #endif | |
826 | ||
ed0bb232 | 827 | static const struct of_device_id serial_pxa_dt_ids[] = { |
699c20f3 HZ |
828 | { .compatible = "mrvl,pxa-uart", }, |
829 | { .compatible = "mrvl,mmp-uart", }, | |
830 | {} | |
831 | }; | |
832 | MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids); | |
833 | ||
834 | static int serial_pxa_probe_dt(struct platform_device *pdev, | |
835 | struct uart_pxa_port *sport) | |
836 | { | |
837 | struct device_node *np = pdev->dev.of_node; | |
838 | int ret; | |
839 | ||
840 | if (!np) | |
841 | return 1; | |
842 | ||
843 | ret = of_alias_get_id(np, "serial"); | |
844 | if (ret < 0) { | |
845 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); | |
846 | return ret; | |
847 | } | |
848 | sport->port.line = ret; | |
849 | return 0; | |
850 | } | |
851 | ||
3ae5eaec | 852 | static int serial_pxa_probe(struct platform_device *dev) |
1da177e4 | 853 | { |
e259a3ae RK |
854 | struct uart_pxa_port *sport; |
855 | struct resource *mmres, *irqres; | |
856 | int ret; | |
857 | ||
858 | mmres = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
859 | irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0); | |
860 | if (!mmres || !irqres) | |
861 | return -ENODEV; | |
862 | ||
863 | sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL); | |
864 | if (!sport) | |
865 | return -ENOMEM; | |
866 | ||
e0d8b13a | 867 | sport->clk = clk_get(&dev->dev, NULL); |
b049bd9d RK |
868 | if (IS_ERR(sport->clk)) { |
869 | ret = PTR_ERR(sport->clk); | |
870 | goto err_free; | |
871 | } | |
872 | ||
9429ccbf YZ |
873 | ret = clk_prepare(sport->clk); |
874 | if (ret) { | |
875 | clk_put(sport->clk); | |
876 | goto err_free; | |
877 | } | |
878 | ||
e259a3ae RK |
879 | sport->port.type = PORT_PXA; |
880 | sport->port.iotype = UPIO_MEM; | |
881 | sport->port.mapbase = mmres->start; | |
882 | sport->port.irq = irqres->start; | |
883 | sport->port.fifosize = 64; | |
884 | sport->port.ops = &serial_pxa_pops; | |
e259a3ae RK |
885 | sport->port.dev = &dev->dev; |
886 | sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; | |
b049bd9d | 887 | sport->port.uartclk = clk_get_rate(sport->clk); |
e259a3ae | 888 | |
699c20f3 HZ |
889 | ret = serial_pxa_probe_dt(dev, sport); |
890 | if (ret > 0) | |
891 | sport->port.line = dev->id; | |
892 | else if (ret < 0) | |
893 | goto err_clk; | |
894 | snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1); | |
e259a3ae | 895 | |
28f65c11 | 896 | sport->port.membase = ioremap(mmres->start, resource_size(mmres)); |
e259a3ae RK |
897 | if (!sport->port.membase) { |
898 | ret = -ENOMEM; | |
b049bd9d | 899 | goto err_clk; |
e259a3ae RK |
900 | } |
901 | ||
699c20f3 | 902 | serial_pxa_ports[sport->port.line] = sport; |
e259a3ae RK |
903 | |
904 | uart_add_one_port(&serial_pxa_reg, &sport->port); | |
905 | platform_set_drvdata(dev, sport); | |
906 | ||
1da177e4 | 907 | return 0; |
e259a3ae | 908 | |
b049bd9d | 909 | err_clk: |
9429ccbf | 910 | clk_unprepare(sport->clk); |
b049bd9d | 911 | clk_put(sport->clk); |
e259a3ae RK |
912 | err_free: |
913 | kfree(sport); | |
914 | return ret; | |
1da177e4 LT |
915 | } |
916 | ||
3ae5eaec | 917 | static int serial_pxa_remove(struct platform_device *dev) |
1da177e4 | 918 | { |
3ae5eaec | 919 | struct uart_pxa_port *sport = platform_get_drvdata(dev); |
1da177e4 | 920 | |
e259a3ae | 921 | uart_remove_one_port(&serial_pxa_reg, &sport->port); |
9429ccbf YZ |
922 | |
923 | clk_unprepare(sport->clk); | |
b049bd9d | 924 | clk_put(sport->clk); |
e259a3ae | 925 | kfree(sport); |
1da177e4 LT |
926 | |
927 | return 0; | |
928 | } | |
929 | ||
3ae5eaec | 930 | static struct platform_driver serial_pxa_driver = { |
1da177e4 LT |
931 | .probe = serial_pxa_probe, |
932 | .remove = serial_pxa_remove, | |
933 | ||
3ae5eaec RK |
934 | .driver = { |
935 | .name = "pxa2xx-uart", | |
bf56c751 MR |
936 | #ifdef CONFIG_PM |
937 | .pm = &serial_pxa_pm_ops, | |
938 | #endif | |
699c20f3 | 939 | .of_match_table = serial_pxa_dt_ids, |
3ae5eaec | 940 | }, |
1da177e4 LT |
941 | }; |
942 | ||
6c62cc0d | 943 | static int __init serial_pxa_init(void) |
1da177e4 LT |
944 | { |
945 | int ret; | |
946 | ||
947 | ret = uart_register_driver(&serial_pxa_reg); | |
948 | if (ret != 0) | |
949 | return ret; | |
950 | ||
3ae5eaec | 951 | ret = platform_driver_register(&serial_pxa_driver); |
1da177e4 LT |
952 | if (ret != 0) |
953 | uart_unregister_driver(&serial_pxa_reg); | |
954 | ||
955 | return ret; | |
956 | } | |
957 | ||
6c62cc0d | 958 | static void __exit serial_pxa_exit(void) |
1da177e4 | 959 | { |
3ae5eaec | 960 | platform_driver_unregister(&serial_pxa_driver); |
1da177e4 LT |
961 | uart_unregister_driver(&serial_pxa_reg); |
962 | } | |
963 | ||
964 | module_init(serial_pxa_init); | |
965 | module_exit(serial_pxa_exit); | |
966 | ||
967 | MODULE_LICENSE("GPL"); | |
e169c139 | 968 | MODULE_ALIAS("platform:pxa2xx-uart"); |