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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Based on drivers/serial/8250.c by Russell King. |
3 | * | |
4 | * Author: Nicolas Pitre | |
5 | * Created: Feb 20, 2003 | |
6 | * Copyright: (C) 2003 Monta Vista Software, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * Note 1: This driver is made separate from the already too overloaded | |
14 | * 8250.c because it needs some kirks of its own and that'll make it | |
15 | * easier to add DMA support. | |
16 | * | |
17 | * Note 2: I'm too sick of device allocation policies for serial ports. | |
18 | * If someone else wants to request an "official" allocation of major/minor | |
19 | * for this driver please be my guest. And don't forget that new hardware | |
20 | * to come from Intel might have more than 3 or 4 of those UARTs. Let's | |
21 | * hope for a better port registration and dynamic device allocation scheme | |
22 | * with the serial core maintainer satisfaction to appear soon. | |
23 | */ | |
24 | ||
1da177e4 LT |
25 | |
26 | #if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
27 | #define SUPPORT_SYSRQ | |
28 | #endif | |
29 | ||
30 | #include <linux/module.h> | |
31 | #include <linux/ioport.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/console.h> | |
34 | #include <linux/sysrq.h> | |
35 | #include <linux/serial_reg.h> | |
36 | #include <linux/circ_buf.h> | |
37 | #include <linux/delay.h> | |
38 | #include <linux/interrupt.h> | |
699c20f3 | 39 | #include <linux/of.h> |
d052d1be | 40 | #include <linux/platform_device.h> |
1da177e4 LT |
41 | #include <linux/tty.h> |
42 | #include <linux/tty_flip.h> | |
43 | #include <linux/serial_core.h> | |
b049bd9d | 44 | #include <linux/clk.h> |
290a5589 | 45 | #include <linux/io.h> |
5a0e3ad6 | 46 | #include <linux/slab.h> |
1da177e4 | 47 | |
699c20f3 HZ |
48 | #define PXA_NAME_LEN 8 |
49 | ||
1da177e4 LT |
50 | struct uart_pxa_port { |
51 | struct uart_port port; | |
52 | unsigned char ier; | |
53 | unsigned char lcr; | |
54 | unsigned char mcr; | |
55 | unsigned int lsr_break_flag; | |
b049bd9d | 56 | struct clk *clk; |
699c20f3 | 57 | char name[PXA_NAME_LEN]; |
1da177e4 LT |
58 | }; |
59 | ||
60 | static inline unsigned int serial_in(struct uart_pxa_port *up, int offset) | |
61 | { | |
62 | offset <<= 2; | |
63 | return readl(up->port.membase + offset); | |
64 | } | |
65 | ||
66 | static inline void serial_out(struct uart_pxa_port *up, int offset, int value) | |
67 | { | |
68 | offset <<= 2; | |
69 | writel(value, up->port.membase + offset); | |
70 | } | |
71 | ||
72 | static void serial_pxa_enable_ms(struct uart_port *port) | |
73 | { | |
74 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
75 | ||
76 | up->ier |= UART_IER_MSI; | |
77 | serial_out(up, UART_IER, up->ier); | |
78 | } | |
79 | ||
b129a8cc | 80 | static void serial_pxa_stop_tx(struct uart_port *port) |
1da177e4 LT |
81 | { |
82 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
83 | ||
84 | if (up->ier & UART_IER_THRI) { | |
85 | up->ier &= ~UART_IER_THRI; | |
86 | serial_out(up, UART_IER, up->ier); | |
87 | } | |
88 | } | |
89 | ||
90 | static void serial_pxa_stop_rx(struct uart_port *port) | |
91 | { | |
92 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
93 | ||
94 | up->ier &= ~UART_IER_RLSI; | |
95 | up->port.read_status_mask &= ~UART_LSR_DR; | |
96 | serial_out(up, UART_IER, up->ier); | |
97 | } | |
98 | ||
7d12e780 | 99 | static inline void receive_chars(struct uart_pxa_port *up, int *status) |
1da177e4 | 100 | { |
1da177e4 LT |
101 | unsigned int ch, flag; |
102 | int max_count = 256; | |
103 | ||
104 | do { | |
e44aabd6 MF |
105 | /* work around Errata #20 according to |
106 | * Intel(R) PXA27x Processor Family | |
107 | * Specification Update (May 2005) | |
108 | * | |
109 | * Step 2 | |
110 | * Disable the Reciever Time Out Interrupt via IER[RTOEI] | |
111 | */ | |
112 | up->ier &= ~UART_IER_RTOIE; | |
113 | serial_out(up, UART_IER, up->ier); | |
114 | ||
1da177e4 LT |
115 | ch = serial_in(up, UART_RX); |
116 | flag = TTY_NORMAL; | |
117 | up->port.icount.rx++; | |
118 | ||
119 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | | |
120 | UART_LSR_FE | UART_LSR_OE))) { | |
121 | /* | |
122 | * For statistics only | |
123 | */ | |
124 | if (*status & UART_LSR_BI) { | |
125 | *status &= ~(UART_LSR_FE | UART_LSR_PE); | |
126 | up->port.icount.brk++; | |
127 | /* | |
128 | * We do the SysRQ and SAK checking | |
129 | * here because otherwise the break | |
130 | * may get masked by ignore_status_mask | |
131 | * or read_status_mask. | |
132 | */ | |
133 | if (uart_handle_break(&up->port)) | |
134 | goto ignore_char; | |
135 | } else if (*status & UART_LSR_PE) | |
136 | up->port.icount.parity++; | |
137 | else if (*status & UART_LSR_FE) | |
138 | up->port.icount.frame++; | |
139 | if (*status & UART_LSR_OE) | |
140 | up->port.icount.overrun++; | |
141 | ||
142 | /* | |
143 | * Mask off conditions which should be ignored. | |
144 | */ | |
145 | *status &= up->port.read_status_mask; | |
146 | ||
147 | #ifdef CONFIG_SERIAL_PXA_CONSOLE | |
148 | if (up->port.line == up->port.cons->index) { | |
149 | /* Recover the break flag from console xmit */ | |
150 | *status |= up->lsr_break_flag; | |
151 | up->lsr_break_flag = 0; | |
152 | } | |
153 | #endif | |
154 | if (*status & UART_LSR_BI) { | |
155 | flag = TTY_BREAK; | |
156 | } else if (*status & UART_LSR_PE) | |
157 | flag = TTY_PARITY; | |
158 | else if (*status & UART_LSR_FE) | |
159 | flag = TTY_FRAME; | |
160 | } | |
05ab3014 | 161 | |
7d12e780 | 162 | if (uart_handle_sysrq_char(&up->port, ch)) |
1da177e4 | 163 | goto ignore_char; |
05ab3014 RK |
164 | |
165 | uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag); | |
166 | ||
1da177e4 LT |
167 | ignore_char: |
168 | *status = serial_in(up, UART_LSR); | |
169 | } while ((*status & UART_LSR_DR) && (max_count-- > 0)); | |
2e124b4a | 170 | tty_flip_buffer_push(&up->port.state->port); |
e44aabd6 MF |
171 | |
172 | /* work around Errata #20 according to | |
173 | * Intel(R) PXA27x Processor Family | |
174 | * Specification Update (May 2005) | |
175 | * | |
176 | * Step 6: | |
177 | * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE] | |
178 | */ | |
179 | up->ier |= UART_IER_RTOIE; | |
180 | serial_out(up, UART_IER, up->ier); | |
1da177e4 LT |
181 | } |
182 | ||
183 | static void transmit_chars(struct uart_pxa_port *up) | |
184 | { | |
ebd2c8f6 | 185 | struct circ_buf *xmit = &up->port.state->xmit; |
1da177e4 LT |
186 | int count; |
187 | ||
188 | if (up->port.x_char) { | |
189 | serial_out(up, UART_TX, up->port.x_char); | |
190 | up->port.icount.tx++; | |
191 | up->port.x_char = 0; | |
192 | return; | |
193 | } | |
194 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
b129a8cc | 195 | serial_pxa_stop_tx(&up->port); |
1da177e4 LT |
196 | return; |
197 | } | |
198 | ||
199 | count = up->port.fifosize / 2; | |
200 | do { | |
201 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
202 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
203 | up->port.icount.tx++; | |
204 | if (uart_circ_empty(xmit)) | |
205 | break; | |
206 | } while (--count > 0); | |
207 | ||
208 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
209 | uart_write_wakeup(&up->port); | |
210 | ||
211 | ||
212 | if (uart_circ_empty(xmit)) | |
b129a8cc | 213 | serial_pxa_stop_tx(&up->port); |
1da177e4 LT |
214 | } |
215 | ||
b129a8cc | 216 | static void serial_pxa_start_tx(struct uart_port *port) |
1da177e4 LT |
217 | { |
218 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
219 | ||
220 | if (!(up->ier & UART_IER_THRI)) { | |
221 | up->ier |= UART_IER_THRI; | |
222 | serial_out(up, UART_IER, up->ier); | |
223 | } | |
224 | } | |
225 | ||
226 | static inline void check_modem_status(struct uart_pxa_port *up) | |
227 | { | |
228 | int status; | |
229 | ||
230 | status = serial_in(up, UART_MSR); | |
231 | ||
232 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
233 | return; | |
234 | ||
235 | if (status & UART_MSR_TERI) | |
236 | up->port.icount.rng++; | |
237 | if (status & UART_MSR_DDSR) | |
238 | up->port.icount.dsr++; | |
239 | if (status & UART_MSR_DDCD) | |
240 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | |
241 | if (status & UART_MSR_DCTS) | |
242 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | |
243 | ||
bdc04e31 | 244 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); |
1da177e4 LT |
245 | } |
246 | ||
247 | /* | |
248 | * This handles the interrupt from one port. | |
249 | */ | |
7d12e780 | 250 | static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id) |
1da177e4 | 251 | { |
c7bec5ab | 252 | struct uart_pxa_port *up = dev_id; |
1da177e4 LT |
253 | unsigned int iir, lsr; |
254 | ||
255 | iir = serial_in(up, UART_IIR); | |
256 | if (iir & UART_IIR_NO_INT) | |
257 | return IRQ_NONE; | |
258 | lsr = serial_in(up, UART_LSR); | |
259 | if (lsr & UART_LSR_DR) | |
7d12e780 | 260 | receive_chars(up, &lsr); |
1da177e4 LT |
261 | check_modem_status(up); |
262 | if (lsr & UART_LSR_THRE) | |
263 | transmit_chars(up); | |
264 | return IRQ_HANDLED; | |
265 | } | |
266 | ||
267 | static unsigned int serial_pxa_tx_empty(struct uart_port *port) | |
268 | { | |
269 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
270 | unsigned long flags; | |
271 | unsigned int ret; | |
272 | ||
273 | spin_lock_irqsave(&up->port.lock, flags); | |
274 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
275 | spin_unlock_irqrestore(&up->port.lock, flags); | |
276 | ||
277 | return ret; | |
278 | } | |
279 | ||
280 | static unsigned int serial_pxa_get_mctrl(struct uart_port *port) | |
281 | { | |
282 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
1da177e4 LT |
283 | unsigned char status; |
284 | unsigned int ret; | |
285 | ||
1da177e4 | 286 | status = serial_in(up, UART_MSR); |
1da177e4 LT |
287 | |
288 | ret = 0; | |
289 | if (status & UART_MSR_DCD) | |
290 | ret |= TIOCM_CAR; | |
291 | if (status & UART_MSR_RI) | |
292 | ret |= TIOCM_RNG; | |
293 | if (status & UART_MSR_DSR) | |
294 | ret |= TIOCM_DSR; | |
295 | if (status & UART_MSR_CTS) | |
296 | ret |= TIOCM_CTS; | |
297 | return ret; | |
298 | } | |
299 | ||
300 | static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
301 | { | |
302 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
303 | unsigned char mcr = 0; | |
304 | ||
305 | if (mctrl & TIOCM_RTS) | |
306 | mcr |= UART_MCR_RTS; | |
307 | if (mctrl & TIOCM_DTR) | |
308 | mcr |= UART_MCR_DTR; | |
309 | if (mctrl & TIOCM_OUT1) | |
310 | mcr |= UART_MCR_OUT1; | |
311 | if (mctrl & TIOCM_OUT2) | |
312 | mcr |= UART_MCR_OUT2; | |
313 | if (mctrl & TIOCM_LOOP) | |
314 | mcr |= UART_MCR_LOOP; | |
315 | ||
316 | mcr |= up->mcr; | |
317 | ||
318 | serial_out(up, UART_MCR, mcr); | |
319 | } | |
320 | ||
321 | static void serial_pxa_break_ctl(struct uart_port *port, int break_state) | |
322 | { | |
323 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
324 | unsigned long flags; | |
325 | ||
326 | spin_lock_irqsave(&up->port.lock, flags); | |
327 | if (break_state == -1) | |
328 | up->lcr |= UART_LCR_SBC; | |
329 | else | |
330 | up->lcr &= ~UART_LCR_SBC; | |
331 | serial_out(up, UART_LCR, up->lcr); | |
332 | spin_unlock_irqrestore(&up->port.lock, flags); | |
333 | } | |
334 | ||
1da177e4 LT |
335 | static int serial_pxa_startup(struct uart_port *port) |
336 | { | |
337 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
338 | unsigned long flags; | |
339 | int retval; | |
340 | ||
d9e29649 MR |
341 | if (port->line == 3) /* HWUART */ |
342 | up->mcr |= UART_MCR_AFE; | |
343 | else | |
f02aa3f9 | 344 | up->mcr = 0; |
1da177e4 | 345 | |
b049bd9d RK |
346 | up->port.uartclk = clk_get_rate(up->clk); |
347 | ||
1da177e4 LT |
348 | /* |
349 | * Allocate the IRQ | |
350 | */ | |
351 | retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up); | |
352 | if (retval) | |
353 | return retval; | |
354 | ||
355 | /* | |
356 | * Clear the FIFO buffers and disable them. | |
357 | * (they will be reenabled in set_termios()) | |
358 | */ | |
359 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
360 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
361 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
362 | serial_out(up, UART_FCR, 0); | |
363 | ||
364 | /* | |
365 | * Clear the interrupt registers. | |
366 | */ | |
367 | (void) serial_in(up, UART_LSR); | |
368 | (void) serial_in(up, UART_RX); | |
369 | (void) serial_in(up, UART_IIR); | |
370 | (void) serial_in(up, UART_MSR); | |
371 | ||
372 | /* | |
373 | * Now, initialize the UART | |
374 | */ | |
375 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
376 | ||
377 | spin_lock_irqsave(&up->port.lock, flags); | |
378 | up->port.mctrl |= TIOCM_OUT2; | |
379 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
380 | spin_unlock_irqrestore(&up->port.lock, flags); | |
381 | ||
382 | /* | |
383 | * Finally, enable interrupts. Note: Modem status interrupts | |
80f7228b | 384 | * are set via set_termios(), which will be occurring imminently |
1da177e4 LT |
385 | * anyway, so we don't enable them here. |
386 | */ | |
387 | up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE; | |
388 | serial_out(up, UART_IER, up->ier); | |
389 | ||
390 | /* | |
391 | * And clear the interrupt registers again for luck. | |
392 | */ | |
393 | (void) serial_in(up, UART_LSR); | |
394 | (void) serial_in(up, UART_RX); | |
395 | (void) serial_in(up, UART_IIR); | |
396 | (void) serial_in(up, UART_MSR); | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | static void serial_pxa_shutdown(struct uart_port *port) | |
402 | { | |
403 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
404 | unsigned long flags; | |
405 | ||
406 | free_irq(up->port.irq, up); | |
407 | ||
408 | /* | |
409 | * Disable interrupts from this port | |
410 | */ | |
411 | up->ier = 0; | |
412 | serial_out(up, UART_IER, 0); | |
413 | ||
414 | spin_lock_irqsave(&up->port.lock, flags); | |
415 | up->port.mctrl &= ~TIOCM_OUT2; | |
416 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
417 | spin_unlock_irqrestore(&up->port.lock, flags); | |
418 | ||
419 | /* | |
420 | * Disable break condition and FIFOs | |
421 | */ | |
422 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | |
423 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
424 | UART_FCR_CLEAR_RCVR | | |
425 | UART_FCR_CLEAR_XMIT); | |
426 | serial_out(up, UART_FCR, 0); | |
427 | } | |
428 | ||
429 | static void | |
606d099c AC |
430 | serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios, |
431 | struct ktermios *old) | |
1da177e4 LT |
432 | { |
433 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
434 | unsigned char cval, fcr = 0; | |
435 | unsigned long flags; | |
436 | unsigned int baud, quot; | |
c934878c | 437 | unsigned int dll; |
1da177e4 LT |
438 | |
439 | switch (termios->c_cflag & CSIZE) { | |
440 | case CS5: | |
0a8b80c5 | 441 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
442 | break; |
443 | case CS6: | |
0a8b80c5 | 444 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
445 | break; |
446 | case CS7: | |
0a8b80c5 | 447 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
448 | break; |
449 | default: | |
450 | case CS8: | |
0a8b80c5 | 451 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
452 | break; |
453 | } | |
454 | ||
455 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 456 | cval |= UART_LCR_STOP; |
1da177e4 LT |
457 | if (termios->c_cflag & PARENB) |
458 | cval |= UART_LCR_PARITY; | |
459 | if (!(termios->c_cflag & PARODD)) | |
460 | cval |= UART_LCR_EPAR; | |
461 | ||
462 | /* | |
463 | * Ask the core to calculate the divisor for us. | |
464 | */ | |
465 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
466 | quot = uart_get_divisor(port, baud); | |
467 | ||
468 | if ((up->port.uartclk / quot) < (2400 * 16)) | |
469 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1; | |
d9e29649 | 470 | else if ((up->port.uartclk / quot) < (230400 * 16)) |
1da177e4 | 471 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8; |
d9e29649 MR |
472 | else |
473 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32; | |
1da177e4 LT |
474 | |
475 | /* | |
476 | * Ok, we're now changing the port state. Do it with | |
477 | * interrupts disabled. | |
478 | */ | |
479 | spin_lock_irqsave(&up->port.lock, flags); | |
480 | ||
481 | /* | |
482 | * Ensure the port will be enabled. | |
483 | * This is required especially for serial console. | |
484 | */ | |
290a5589 | 485 | up->ier |= UART_IER_UUE; |
1da177e4 LT |
486 | |
487 | /* | |
488 | * Update the per-port timeout. | |
489 | */ | |
e6158b4a | 490 | uart_update_timeout(port, termios->c_cflag, baud); |
1da177e4 LT |
491 | |
492 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
493 | if (termios->c_iflag & INPCK) | |
494 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
495 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
496 | up->port.read_status_mask |= UART_LSR_BI; | |
497 | ||
498 | /* | |
499 | * Characters to ignore | |
500 | */ | |
501 | up->port.ignore_status_mask = 0; | |
502 | if (termios->c_iflag & IGNPAR) | |
503 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
504 | if (termios->c_iflag & IGNBRK) { | |
505 | up->port.ignore_status_mask |= UART_LSR_BI; | |
506 | /* | |
507 | * If we're ignoring parity and break indicators, | |
508 | * ignore overruns too (for real raw support). | |
509 | */ | |
510 | if (termios->c_iflag & IGNPAR) | |
511 | up->port.ignore_status_mask |= UART_LSR_OE; | |
512 | } | |
513 | ||
514 | /* | |
515 | * ignore all characters if CREAD is not set | |
516 | */ | |
517 | if ((termios->c_cflag & CREAD) == 0) | |
518 | up->port.ignore_status_mask |= UART_LSR_DR; | |
519 | ||
520 | /* | |
521 | * CTS flow control flag and modem status interrupts | |
522 | */ | |
523 | up->ier &= ~UART_IER_MSI; | |
524 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
525 | up->ier |= UART_IER_MSI; | |
526 | ||
527 | serial_out(up, UART_IER, up->ier); | |
528 | ||
2276f03b RJ |
529 | if (termios->c_cflag & CRTSCTS) |
530 | up->mcr |= UART_MCR_AFE; | |
531 | else | |
532 | up->mcr &= ~UART_MCR_AFE; | |
533 | ||
c934878c | 534 | serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ |
1da177e4 | 535 | serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ |
c934878c UKK |
536 | |
537 | /* | |
538 | * work around Errata #75 according to Intel(R) PXA27x Processor Family | |
539 | * Specification Update (Nov 2005) | |
540 | */ | |
541 | dll = serial_in(up, UART_DLL); | |
542 | WARN_ON(dll != (quot & 0xff)); | |
543 | ||
1da177e4 | 544 | serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ |
c934878c | 545 | serial_out(up, UART_LCR, cval); /* reset DLAB */ |
1da177e4 LT |
546 | up->lcr = cval; /* Save LCR */ |
547 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
548 | serial_out(up, UART_FCR, fcr); | |
549 | spin_unlock_irqrestore(&up->port.lock, flags); | |
550 | } | |
551 | ||
552 | static void | |
553 | serial_pxa_pm(struct uart_port *port, unsigned int state, | |
554 | unsigned int oldstate) | |
555 | { | |
556 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
b049bd9d | 557 | |
1da177e4 | 558 | if (!state) |
fb8ebec0 | 559 | clk_prepare_enable(up->clk); |
b049bd9d | 560 | else |
fb8ebec0 | 561 | clk_disable_unprepare(up->clk); |
1da177e4 LT |
562 | } |
563 | ||
564 | static void serial_pxa_release_port(struct uart_port *port) | |
565 | { | |
566 | } | |
567 | ||
568 | static int serial_pxa_request_port(struct uart_port *port) | |
569 | { | |
570 | return 0; | |
571 | } | |
572 | ||
573 | static void serial_pxa_config_port(struct uart_port *port, int flags) | |
574 | { | |
575 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
576 | up->port.type = PORT_PXA; | |
577 | } | |
578 | ||
579 | static int | |
580 | serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser) | |
581 | { | |
582 | /* we don't want the core code to modify any port params */ | |
583 | return -EINVAL; | |
584 | } | |
585 | ||
586 | static const char * | |
587 | serial_pxa_type(struct uart_port *port) | |
588 | { | |
589 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
590 | return up->name; | |
591 | } | |
592 | ||
e259a3ae | 593 | static struct uart_pxa_port *serial_pxa_ports[4]; |
2d93486c | 594 | static struct uart_driver serial_pxa_reg; |
1da177e4 | 595 | |
fa7f1518 PZ |
596 | #ifdef CONFIG_SERIAL_PXA_CONSOLE |
597 | ||
1da177e4 LT |
598 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
599 | ||
600 | /* | |
601 | * Wait for transmitter & holding register to empty | |
602 | */ | |
603 | static inline void wait_for_xmitr(struct uart_pxa_port *up) | |
604 | { | |
605 | unsigned int status, tmout = 10000; | |
606 | ||
607 | /* Wait up to 10ms for the character(s) to be sent. */ | |
608 | do { | |
609 | status = serial_in(up, UART_LSR); | |
610 | ||
611 | if (status & UART_LSR_BI) | |
612 | up->lsr_break_flag = UART_LSR_BI; | |
613 | ||
614 | if (--tmout == 0) | |
615 | break; | |
616 | udelay(1); | |
617 | } while ((status & BOTH_EMPTY) != BOTH_EMPTY); | |
618 | ||
619 | /* Wait up to 1s for flow control if necessary */ | |
620 | if (up->port.flags & UPF_CONS_FLOW) { | |
621 | tmout = 1000000; | |
622 | while (--tmout && | |
623 | ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) | |
624 | udelay(1); | |
625 | } | |
626 | } | |
627 | ||
d358788f RK |
628 | static void serial_pxa_console_putchar(struct uart_port *port, int ch) |
629 | { | |
630 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
631 | ||
632 | wait_for_xmitr(up); | |
633 | serial_out(up, UART_TX, ch); | |
634 | } | |
635 | ||
1da177e4 LT |
636 | /* |
637 | * Print a string to the serial port trying not to disturb | |
638 | * any possible real use of the port... | |
639 | * | |
640 | * The console_lock must be held when we get here. | |
641 | */ | |
642 | static void | |
643 | serial_pxa_console_write(struct console *co, const char *s, unsigned int count) | |
644 | { | |
e259a3ae | 645 | struct uart_pxa_port *up = serial_pxa_ports[co->index]; |
1da177e4 | 646 | unsigned int ier; |
cfe275c2 CX |
647 | unsigned long flags; |
648 | int locked = 1; | |
1da177e4 | 649 | |
9429ccbf | 650 | clk_enable(up->clk); |
cfe275c2 CX |
651 | local_irq_save(flags); |
652 | if (up->port.sysrq) | |
653 | locked = 0; | |
654 | else if (oops_in_progress) | |
655 | locked = spin_trylock(&up->port.lock); | |
656 | else | |
657 | spin_lock(&up->port.lock); | |
658 | ||
1da177e4 | 659 | /* |
f02aa3f9 | 660 | * First save the IER then disable the interrupts |
1da177e4 LT |
661 | */ |
662 | ier = serial_in(up, UART_IER); | |
663 | serial_out(up, UART_IER, UART_IER_UUE); | |
664 | ||
d358788f | 665 | uart_console_write(&up->port, s, count, serial_pxa_console_putchar); |
1da177e4 LT |
666 | |
667 | /* | |
668 | * Finally, wait for transmitter to become empty | |
669 | * and restore the IER | |
670 | */ | |
671 | wait_for_xmitr(up); | |
672 | serial_out(up, UART_IER, ier); | |
b049bd9d | 673 | |
cfe275c2 CX |
674 | if (locked) |
675 | spin_unlock(&up->port.lock); | |
676 | local_irq_restore(flags); | |
9429ccbf | 677 | clk_disable(up->clk); |
cfe275c2 | 678 | |
1da177e4 LT |
679 | } |
680 | ||
e1a9c179 DL |
681 | #ifdef CONFIG_CONSOLE_POLL |
682 | /* | |
683 | * Console polling routines for writing and reading from the uart while | |
684 | * in an interrupt or debug context. | |
685 | */ | |
686 | ||
687 | static int serial_pxa_get_poll_char(struct uart_port *port) | |
688 | { | |
689 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
690 | unsigned char lsr = serial_in(up, UART_LSR); | |
691 | ||
692 | while (!(lsr & UART_LSR_DR)) | |
693 | lsr = serial_in(up, UART_LSR); | |
694 | ||
695 | return serial_in(up, UART_RX); | |
696 | } | |
697 | ||
698 | ||
699 | static void serial_pxa_put_poll_char(struct uart_port *port, | |
700 | unsigned char c) | |
701 | { | |
702 | unsigned int ier; | |
703 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
704 | ||
705 | /* | |
706 | * First save the IER then disable the interrupts | |
707 | */ | |
708 | ier = serial_in(up, UART_IER); | |
709 | serial_out(up, UART_IER, UART_IER_UUE); | |
710 | ||
711 | wait_for_xmitr(up); | |
712 | /* | |
713 | * Send the character out. | |
714 | * If a LF, also do CR... | |
715 | */ | |
716 | serial_out(up, UART_TX, c); | |
717 | if (c == 10) { | |
718 | wait_for_xmitr(up); | |
719 | serial_out(up, UART_TX, 13); | |
720 | } | |
721 | ||
722 | /* | |
723 | * Finally, wait for transmitter to become empty | |
724 | * and restore the IER | |
725 | */ | |
726 | wait_for_xmitr(up); | |
727 | serial_out(up, UART_IER, ier); | |
728 | } | |
729 | ||
730 | #endif /* CONFIG_CONSOLE_POLL */ | |
731 | ||
1da177e4 LT |
732 | static int __init |
733 | serial_pxa_console_setup(struct console *co, char *options) | |
734 | { | |
735 | struct uart_pxa_port *up; | |
736 | int baud = 9600; | |
737 | int bits = 8; | |
738 | int parity = 'n'; | |
739 | int flow = 'n'; | |
740 | ||
741 | if (co->index == -1 || co->index >= serial_pxa_reg.nr) | |
742 | co->index = 0; | |
e259a3ae RK |
743 | up = serial_pxa_ports[co->index]; |
744 | if (!up) | |
745 | return -ENODEV; | |
1da177e4 LT |
746 | |
747 | if (options) | |
748 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
749 | ||
750 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
751 | } | |
752 | ||
753 | static struct console serial_pxa_console = { | |
754 | .name = "ttyS", | |
755 | .write = serial_pxa_console_write, | |
756 | .device = uart_console_device, | |
757 | .setup = serial_pxa_console_setup, | |
758 | .flags = CON_PRINTBUFFER, | |
759 | .index = -1, | |
760 | .data = &serial_pxa_reg, | |
761 | }; | |
762 | ||
1da177e4 LT |
763 | #define PXA_CONSOLE &serial_pxa_console |
764 | #else | |
765 | #define PXA_CONSOLE NULL | |
766 | #endif | |
767 | ||
6c62cc0d | 768 | static struct uart_ops serial_pxa_pops = { |
1da177e4 LT |
769 | .tx_empty = serial_pxa_tx_empty, |
770 | .set_mctrl = serial_pxa_set_mctrl, | |
771 | .get_mctrl = serial_pxa_get_mctrl, | |
772 | .stop_tx = serial_pxa_stop_tx, | |
773 | .start_tx = serial_pxa_start_tx, | |
774 | .stop_rx = serial_pxa_stop_rx, | |
775 | .enable_ms = serial_pxa_enable_ms, | |
776 | .break_ctl = serial_pxa_break_ctl, | |
777 | .startup = serial_pxa_startup, | |
778 | .shutdown = serial_pxa_shutdown, | |
779 | .set_termios = serial_pxa_set_termios, | |
780 | .pm = serial_pxa_pm, | |
781 | .type = serial_pxa_type, | |
782 | .release_port = serial_pxa_release_port, | |
783 | .request_port = serial_pxa_request_port, | |
784 | .config_port = serial_pxa_config_port, | |
785 | .verify_port = serial_pxa_verify_port, | |
e1a9c179 DL |
786 | #ifdef CONFIG_CONSOLE_POLL |
787 | .poll_get_char = serial_pxa_get_poll_char, | |
788 | .poll_put_char = serial_pxa_put_poll_char, | |
789 | #endif | |
1da177e4 LT |
790 | }; |
791 | ||
1da177e4 LT |
792 | static struct uart_driver serial_pxa_reg = { |
793 | .owner = THIS_MODULE, | |
794 | .driver_name = "PXA serial", | |
1da177e4 LT |
795 | .dev_name = "ttyS", |
796 | .major = TTY_MAJOR, | |
797 | .minor = 64, | |
e259a3ae | 798 | .nr = 4, |
1da177e4 LT |
799 | .cons = PXA_CONSOLE, |
800 | }; | |
801 | ||
bf56c751 MR |
802 | #ifdef CONFIG_PM |
803 | static int serial_pxa_suspend(struct device *dev) | |
1da177e4 | 804 | { |
bf56c751 | 805 | struct uart_pxa_port *sport = dev_get_drvdata(dev); |
1da177e4 | 806 | |
9480e307 | 807 | if (sport) |
1da177e4 LT |
808 | uart_suspend_port(&serial_pxa_reg, &sport->port); |
809 | ||
810 | return 0; | |
811 | } | |
812 | ||
bf56c751 | 813 | static int serial_pxa_resume(struct device *dev) |
1da177e4 | 814 | { |
bf56c751 | 815 | struct uart_pxa_port *sport = dev_get_drvdata(dev); |
1da177e4 | 816 | |
9480e307 | 817 | if (sport) |
1da177e4 LT |
818 | uart_resume_port(&serial_pxa_reg, &sport->port); |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
47145210 | 823 | static const struct dev_pm_ops serial_pxa_pm_ops = { |
bf56c751 MR |
824 | .suspend = serial_pxa_suspend, |
825 | .resume = serial_pxa_resume, | |
826 | }; | |
827 | #endif | |
828 | ||
699c20f3 HZ |
829 | static struct of_device_id serial_pxa_dt_ids[] = { |
830 | { .compatible = "mrvl,pxa-uart", }, | |
831 | { .compatible = "mrvl,mmp-uart", }, | |
832 | {} | |
833 | }; | |
834 | MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids); | |
835 | ||
836 | static int serial_pxa_probe_dt(struct platform_device *pdev, | |
837 | struct uart_pxa_port *sport) | |
838 | { | |
839 | struct device_node *np = pdev->dev.of_node; | |
840 | int ret; | |
841 | ||
842 | if (!np) | |
843 | return 1; | |
844 | ||
845 | ret = of_alias_get_id(np, "serial"); | |
846 | if (ret < 0) { | |
847 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); | |
848 | return ret; | |
849 | } | |
850 | sport->port.line = ret; | |
851 | return 0; | |
852 | } | |
853 | ||
3ae5eaec | 854 | static int serial_pxa_probe(struct platform_device *dev) |
1da177e4 | 855 | { |
e259a3ae RK |
856 | struct uart_pxa_port *sport; |
857 | struct resource *mmres, *irqres; | |
858 | int ret; | |
859 | ||
860 | mmres = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
861 | irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0); | |
862 | if (!mmres || !irqres) | |
863 | return -ENODEV; | |
864 | ||
865 | sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL); | |
866 | if (!sport) | |
867 | return -ENOMEM; | |
868 | ||
e0d8b13a | 869 | sport->clk = clk_get(&dev->dev, NULL); |
b049bd9d RK |
870 | if (IS_ERR(sport->clk)) { |
871 | ret = PTR_ERR(sport->clk); | |
872 | goto err_free; | |
873 | } | |
874 | ||
9429ccbf YZ |
875 | ret = clk_prepare(sport->clk); |
876 | if (ret) { | |
877 | clk_put(sport->clk); | |
878 | goto err_free; | |
879 | } | |
880 | ||
e259a3ae RK |
881 | sport->port.type = PORT_PXA; |
882 | sport->port.iotype = UPIO_MEM; | |
883 | sport->port.mapbase = mmres->start; | |
884 | sport->port.irq = irqres->start; | |
885 | sport->port.fifosize = 64; | |
886 | sport->port.ops = &serial_pxa_pops; | |
e259a3ae RK |
887 | sport->port.dev = &dev->dev; |
888 | sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; | |
b049bd9d | 889 | sport->port.uartclk = clk_get_rate(sport->clk); |
e259a3ae | 890 | |
699c20f3 HZ |
891 | ret = serial_pxa_probe_dt(dev, sport); |
892 | if (ret > 0) | |
893 | sport->port.line = dev->id; | |
894 | else if (ret < 0) | |
895 | goto err_clk; | |
896 | snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1); | |
e259a3ae | 897 | |
28f65c11 | 898 | sport->port.membase = ioremap(mmres->start, resource_size(mmres)); |
e259a3ae RK |
899 | if (!sport->port.membase) { |
900 | ret = -ENOMEM; | |
b049bd9d | 901 | goto err_clk; |
e259a3ae RK |
902 | } |
903 | ||
699c20f3 | 904 | serial_pxa_ports[sport->port.line] = sport; |
e259a3ae RK |
905 | |
906 | uart_add_one_port(&serial_pxa_reg, &sport->port); | |
907 | platform_set_drvdata(dev, sport); | |
908 | ||
1da177e4 | 909 | return 0; |
e259a3ae | 910 | |
b049bd9d | 911 | err_clk: |
9429ccbf | 912 | clk_unprepare(sport->clk); |
b049bd9d | 913 | clk_put(sport->clk); |
e259a3ae RK |
914 | err_free: |
915 | kfree(sport); | |
916 | return ret; | |
1da177e4 LT |
917 | } |
918 | ||
3ae5eaec | 919 | static int serial_pxa_remove(struct platform_device *dev) |
1da177e4 | 920 | { |
3ae5eaec | 921 | struct uart_pxa_port *sport = platform_get_drvdata(dev); |
1da177e4 | 922 | |
e259a3ae | 923 | uart_remove_one_port(&serial_pxa_reg, &sport->port); |
9429ccbf YZ |
924 | |
925 | clk_unprepare(sport->clk); | |
b049bd9d | 926 | clk_put(sport->clk); |
e259a3ae | 927 | kfree(sport); |
1da177e4 LT |
928 | |
929 | return 0; | |
930 | } | |
931 | ||
3ae5eaec | 932 | static struct platform_driver serial_pxa_driver = { |
1da177e4 LT |
933 | .probe = serial_pxa_probe, |
934 | .remove = serial_pxa_remove, | |
935 | ||
3ae5eaec RK |
936 | .driver = { |
937 | .name = "pxa2xx-uart", | |
e169c139 | 938 | .owner = THIS_MODULE, |
bf56c751 MR |
939 | #ifdef CONFIG_PM |
940 | .pm = &serial_pxa_pm_ops, | |
941 | #endif | |
699c20f3 | 942 | .of_match_table = serial_pxa_dt_ids, |
3ae5eaec | 943 | }, |
1da177e4 LT |
944 | }; |
945 | ||
6c62cc0d | 946 | static int __init serial_pxa_init(void) |
1da177e4 LT |
947 | { |
948 | int ret; | |
949 | ||
950 | ret = uart_register_driver(&serial_pxa_reg); | |
951 | if (ret != 0) | |
952 | return ret; | |
953 | ||
3ae5eaec | 954 | ret = platform_driver_register(&serial_pxa_driver); |
1da177e4 LT |
955 | if (ret != 0) |
956 | uart_unregister_driver(&serial_pxa_reg); | |
957 | ||
958 | return ret; | |
959 | } | |
960 | ||
6c62cc0d | 961 | static void __exit serial_pxa_exit(void) |
1da177e4 | 962 | { |
3ae5eaec | 963 | platform_driver_unregister(&serial_pxa_driver); |
1da177e4 LT |
964 | uart_unregister_driver(&serial_pxa_reg); |
965 | } | |
966 | ||
967 | module_init(serial_pxa_init); | |
968 | module_exit(serial_pxa_exit); | |
969 | ||
970 | MODULE_LICENSE("GPL"); | |
e169c139 | 971 | MODULE_ALIAS("platform:pxa2xx-uart"); |