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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for SA11x0 serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 | 21 | */ |
1da177e4 LT |
22 | |
23 | #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
24 | #define SUPPORT_SYSRQ | |
25 | #endif | |
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/console.h> | |
31 | #include <linux/sysrq.h> | |
6920b5a7 | 32 | #include <linux/platform_data/sa11x0-serial.h> |
d052d1be | 33 | #include <linux/platform_device.h> |
1da177e4 LT |
34 | #include <linux/tty.h> |
35 | #include <linux/tty_flip.h> | |
36 | #include <linux/serial_core.h> | |
37 | #include <linux/serial.h> | |
99730225 | 38 | #include <linux/io.h> |
1da177e4 | 39 | |
1da177e4 | 40 | #include <asm/irq.h> |
a09e64fb | 41 | #include <mach/hardware.h> |
f314f33b | 42 | #include <mach/irqs.h> |
1da177e4 LT |
43 | |
44 | /* We've been assigned a range on the "Low-density serial ports" major */ | |
45 | #define SERIAL_SA1100_MAJOR 204 | |
46 | #define MINOR_START 5 | |
47 | ||
48 | #define NR_PORTS 3 | |
49 | ||
50 | #define SA1100_ISR_PASS_LIMIT 256 | |
51 | ||
52 | /* | |
53 | * Convert from ignore_status_mask or read_status_mask to UTSR[01] | |
54 | */ | |
55 | #define SM_TO_UTSR0(x) ((x) & 0xff) | |
56 | #define SM_TO_UTSR1(x) ((x) >> 8) | |
57 | #define UTSR0_TO_SM(x) ((x)) | |
58 | #define UTSR1_TO_SM(x) ((x) << 8) | |
59 | ||
60 | #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0) | |
61 | #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1) | |
62 | #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2) | |
63 | #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3) | |
64 | #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0) | |
65 | #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1) | |
66 | #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR) | |
67 | ||
68 | #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0) | |
69 | #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1) | |
70 | #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2) | |
71 | #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3) | |
72 | #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0) | |
73 | #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1) | |
74 | #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR) | |
75 | ||
76 | /* | |
77 | * This is the size of our serial port register set. | |
78 | */ | |
79 | #define UART_PORT_SIZE 0x24 | |
80 | ||
81 | /* | |
82 | * This determines how often we check the modem status signals | |
83 | * for any change. They generally aren't connected to an IRQ | |
84 | * so we have to poll them. We also check immediately before | |
85 | * filling the TX fifo incase CTS has been dropped. | |
86 | */ | |
87 | #define MCTRL_TIMEOUT (250*HZ/1000) | |
88 | ||
89 | struct sa1100_port { | |
90 | struct uart_port port; | |
91 | struct timer_list timer; | |
92 | unsigned int old_status; | |
93 | }; | |
94 | ||
95 | /* | |
96 | * Handle any change of modem status signal since we were last called. | |
97 | */ | |
98 | static void sa1100_mctrl_check(struct sa1100_port *sport) | |
99 | { | |
100 | unsigned int status, changed; | |
101 | ||
102 | status = sport->port.ops->get_mctrl(&sport->port); | |
103 | changed = status ^ sport->old_status; | |
104 | ||
105 | if (changed == 0) | |
106 | return; | |
107 | ||
108 | sport->old_status = status; | |
109 | ||
110 | if (changed & TIOCM_RI) | |
111 | sport->port.icount.rng++; | |
112 | if (changed & TIOCM_DSR) | |
113 | sport->port.icount.dsr++; | |
114 | if (changed & TIOCM_CAR) | |
115 | uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); | |
116 | if (changed & TIOCM_CTS) | |
117 | uart_handle_cts_change(&sport->port, status & TIOCM_CTS); | |
118 | ||
bdc04e31 | 119 | wake_up_interruptible(&sport->port.state->port.delta_msr_wait); |
1da177e4 LT |
120 | } |
121 | ||
122 | /* | |
123 | * This is our per-port timeout handler, for checking the | |
124 | * modem status signals. | |
125 | */ | |
126 | static void sa1100_timeout(unsigned long data) | |
127 | { | |
128 | struct sa1100_port *sport = (struct sa1100_port *)data; | |
129 | unsigned long flags; | |
130 | ||
ebd2c8f6 | 131 | if (sport->port.state) { |
1da177e4 LT |
132 | spin_lock_irqsave(&sport->port.lock, flags); |
133 | sa1100_mctrl_check(sport); | |
134 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
135 | ||
136 | mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); | |
137 | } | |
138 | } | |
139 | ||
140 | /* | |
141 | * interrupts disabled on entry | |
142 | */ | |
b129a8cc | 143 | static void sa1100_stop_tx(struct uart_port *port) |
1da177e4 | 144 | { |
c9db776b FF |
145 | struct sa1100_port *sport = |
146 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
147 | u32 utcr3; |
148 | ||
149 | utcr3 = UART_GET_UTCR3(sport); | |
150 | UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE); | |
151 | sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS); | |
152 | } | |
153 | ||
154 | /* | |
270c7a72 | 155 | * port locked and interrupts disabled |
1da177e4 | 156 | */ |
b129a8cc | 157 | static void sa1100_start_tx(struct uart_port *port) |
1da177e4 | 158 | { |
c9db776b FF |
159 | struct sa1100_port *sport = |
160 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
161 | u32 utcr3; |
162 | ||
1da177e4 LT |
163 | utcr3 = UART_GET_UTCR3(sport); |
164 | sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS); | |
165 | UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE); | |
1da177e4 LT |
166 | } |
167 | ||
168 | /* | |
169 | * Interrupts enabled | |
170 | */ | |
171 | static void sa1100_stop_rx(struct uart_port *port) | |
172 | { | |
c9db776b FF |
173 | struct sa1100_port *sport = |
174 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
175 | u32 utcr3; |
176 | ||
177 | utcr3 = UART_GET_UTCR3(sport); | |
178 | UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE); | |
179 | } | |
180 | ||
181 | /* | |
182 | * Set the modem control timer to fire immediately. | |
183 | */ | |
184 | static void sa1100_enable_ms(struct uart_port *port) | |
185 | { | |
c9db776b FF |
186 | struct sa1100_port *sport = |
187 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
188 | |
189 | mod_timer(&sport->timer, jiffies); | |
190 | } | |
191 | ||
192 | static void | |
7d12e780 | 193 | sa1100_rx_chars(struct sa1100_port *sport) |
1da177e4 | 194 | { |
ff39bc77 | 195 | unsigned int status, ch, flg; |
1da177e4 LT |
196 | |
197 | status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) | | |
198 | UTSR0_TO_SM(UART_GET_UTSR0(sport)); | |
199 | while (status & UTSR1_TO_SM(UTSR1_RNE)) { | |
200 | ch = UART_GET_CHAR(sport); | |
201 | ||
1da177e4 LT |
202 | sport->port.icount.rx++; |
203 | ||
204 | flg = TTY_NORMAL; | |
205 | ||
206 | /* | |
207 | * note that the error handling code is | |
208 | * out of the main execution path | |
209 | */ | |
2a9604b8 RK |
210 | if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) { |
211 | if (status & UTSR1_TO_SM(UTSR1_PRE)) | |
212 | sport->port.icount.parity++; | |
213 | else if (status & UTSR1_TO_SM(UTSR1_FRE)) | |
214 | sport->port.icount.frame++; | |
215 | if (status & UTSR1_TO_SM(UTSR1_ROR)) | |
216 | sport->port.icount.overrun++; | |
217 | ||
218 | status &= sport->port.read_status_mask; | |
219 | ||
220 | if (status & UTSR1_TO_SM(UTSR1_PRE)) | |
221 | flg = TTY_PARITY; | |
222 | else if (status & UTSR1_TO_SM(UTSR1_FRE)) | |
223 | flg = TTY_FRAME; | |
224 | ||
225 | #ifdef SUPPORT_SYSRQ | |
226 | sport->port.sysrq = 0; | |
227 | #endif | |
228 | } | |
1da177e4 | 229 | |
7d12e780 | 230 | if (uart_handle_sysrq_char(&sport->port, ch)) |
1da177e4 LT |
231 | goto ignore_char; |
232 | ||
05ab3014 | 233 | uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg); |
2a9604b8 | 234 | |
1da177e4 LT |
235 | ignore_char: |
236 | status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) | | |
237 | UTSR0_TO_SM(UART_GET_UTSR0(sport)); | |
238 | } | |
53e0e670 VK |
239 | |
240 | spin_unlock(&sport->port.lock); | |
2e124b4a | 241 | tty_flip_buffer_push(&sport->port.state->port); |
53e0e670 | 242 | spin_lock(&sport->port.lock); |
1da177e4 LT |
243 | } |
244 | ||
245 | static void sa1100_tx_chars(struct sa1100_port *sport) | |
246 | { | |
ebd2c8f6 | 247 | struct circ_buf *xmit = &sport->port.state->xmit; |
1da177e4 LT |
248 | |
249 | if (sport->port.x_char) { | |
250 | UART_PUT_CHAR(sport, sport->port.x_char); | |
251 | sport->port.icount.tx++; | |
252 | sport->port.x_char = 0; | |
253 | return; | |
254 | } | |
255 | ||
256 | /* | |
257 | * Check the modem control lines before | |
258 | * transmitting anything. | |
259 | */ | |
260 | sa1100_mctrl_check(sport); | |
261 | ||
262 | if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { | |
b129a8cc | 263 | sa1100_stop_tx(&sport->port); |
1da177e4 LT |
264 | return; |
265 | } | |
266 | ||
267 | /* | |
268 | * Tried using FIFO (not checking TNF) for fifo fill: | |
269 | * still had the '4 bytes repeated' problem. | |
270 | */ | |
271 | while (UART_GET_UTSR1(sport) & UTSR1_TNF) { | |
272 | UART_PUT_CHAR(sport, xmit->buf[xmit->tail]); | |
273 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
274 | sport->port.icount.tx++; | |
275 | if (uart_circ_empty(xmit)) | |
276 | break; | |
277 | } | |
278 | ||
279 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
280 | uart_write_wakeup(&sport->port); | |
281 | ||
282 | if (uart_circ_empty(xmit)) | |
b129a8cc | 283 | sa1100_stop_tx(&sport->port); |
1da177e4 LT |
284 | } |
285 | ||
7d12e780 | 286 | static irqreturn_t sa1100_int(int irq, void *dev_id) |
1da177e4 LT |
287 | { |
288 | struct sa1100_port *sport = dev_id; | |
289 | unsigned int status, pass_counter = 0; | |
290 | ||
291 | spin_lock(&sport->port.lock); | |
292 | status = UART_GET_UTSR0(sport); | |
293 | status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS; | |
294 | do { | |
295 | if (status & (UTSR0_RFS | UTSR0_RID)) { | |
296 | /* Clear the receiver idle bit, if set */ | |
297 | if (status & UTSR0_RID) | |
298 | UART_PUT_UTSR0(sport, UTSR0_RID); | |
7d12e780 | 299 | sa1100_rx_chars(sport); |
1da177e4 LT |
300 | } |
301 | ||
302 | /* Clear the relevant break bits */ | |
303 | if (status & (UTSR0_RBB | UTSR0_REB)) | |
304 | UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB)); | |
305 | ||
306 | if (status & UTSR0_RBB) | |
307 | sport->port.icount.brk++; | |
308 | ||
309 | if (status & UTSR0_REB) | |
310 | uart_handle_break(&sport->port); | |
311 | ||
312 | if (status & UTSR0_TFS) | |
313 | sa1100_tx_chars(sport); | |
314 | if (pass_counter++ > SA1100_ISR_PASS_LIMIT) | |
315 | break; | |
316 | status = UART_GET_UTSR0(sport); | |
317 | status &= SM_TO_UTSR0(sport->port.read_status_mask) | | |
318 | ~UTSR0_TFS; | |
319 | } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID)); | |
320 | spin_unlock(&sport->port.lock); | |
321 | ||
322 | return IRQ_HANDLED; | |
323 | } | |
324 | ||
325 | /* | |
326 | * Return TIOCSER_TEMT when transmitter is not busy. | |
327 | */ | |
328 | static unsigned int sa1100_tx_empty(struct uart_port *port) | |
329 | { | |
c9db776b FF |
330 | struct sa1100_port *sport = |
331 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
332 | |
333 | return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT; | |
334 | } | |
335 | ||
336 | static unsigned int sa1100_get_mctrl(struct uart_port *port) | |
337 | { | |
338 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
339 | } | |
340 | ||
341 | static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
342 | { | |
343 | } | |
344 | ||
345 | /* | |
346 | * Interrupts always disabled. | |
347 | */ | |
348 | static void sa1100_break_ctl(struct uart_port *port, int break_state) | |
349 | { | |
c9db776b FF |
350 | struct sa1100_port *sport = |
351 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
352 | unsigned long flags; |
353 | unsigned int utcr3; | |
354 | ||
355 | spin_lock_irqsave(&sport->port.lock, flags); | |
356 | utcr3 = UART_GET_UTCR3(sport); | |
357 | if (break_state == -1) | |
358 | utcr3 |= UTCR3_BRK; | |
359 | else | |
360 | utcr3 &= ~UTCR3_BRK; | |
361 | UART_PUT_UTCR3(sport, utcr3); | |
362 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
363 | } | |
364 | ||
365 | static int sa1100_startup(struct uart_port *port) | |
366 | { | |
c9db776b FF |
367 | struct sa1100_port *sport = |
368 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
369 | int retval; |
370 | ||
371 | /* | |
372 | * Allocate the IRQ | |
373 | */ | |
374 | retval = request_irq(sport->port.irq, sa1100_int, 0, | |
375 | "sa11x0-uart", sport); | |
376 | if (retval) | |
377 | return retval; | |
378 | ||
379 | /* | |
380 | * Finally, clear and enable interrupts | |
381 | */ | |
382 | UART_PUT_UTSR0(sport, -1); | |
383 | UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE); | |
384 | ||
385 | /* | |
386 | * Enable modem status interrupts | |
387 | */ | |
388 | spin_lock_irq(&sport->port.lock); | |
389 | sa1100_enable_ms(&sport->port); | |
390 | spin_unlock_irq(&sport->port.lock); | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
395 | static void sa1100_shutdown(struct uart_port *port) | |
396 | { | |
c9db776b FF |
397 | struct sa1100_port *sport = |
398 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
399 | |
400 | /* | |
401 | * Stop our timer. | |
402 | */ | |
403 | del_timer_sync(&sport->timer); | |
404 | ||
405 | /* | |
406 | * Free the interrupt | |
407 | */ | |
408 | free_irq(sport->port.irq, sport); | |
409 | ||
410 | /* | |
411 | * Disable all interrupts, port and break condition. | |
412 | */ | |
413 | UART_PUT_UTCR3(sport, 0); | |
414 | } | |
415 | ||
416 | static void | |
606d099c AC |
417 | sa1100_set_termios(struct uart_port *port, struct ktermios *termios, |
418 | struct ktermios *old) | |
1da177e4 | 419 | { |
c9db776b FF |
420 | struct sa1100_port *sport = |
421 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
422 | unsigned long flags; |
423 | unsigned int utcr0, old_utcr3, baud, quot; | |
424 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
425 | ||
426 | /* | |
427 | * We only support CS7 and CS8. | |
428 | */ | |
429 | while ((termios->c_cflag & CSIZE) != CS7 && | |
430 | (termios->c_cflag & CSIZE) != CS8) { | |
431 | termios->c_cflag &= ~CSIZE; | |
432 | termios->c_cflag |= old_csize; | |
433 | old_csize = CS8; | |
434 | } | |
435 | ||
436 | if ((termios->c_cflag & CSIZE) == CS8) | |
437 | utcr0 = UTCR0_DSS; | |
438 | else | |
439 | utcr0 = 0; | |
440 | ||
441 | if (termios->c_cflag & CSTOPB) | |
442 | utcr0 |= UTCR0_SBS; | |
443 | if (termios->c_cflag & PARENB) { | |
444 | utcr0 |= UTCR0_PE; | |
445 | if (!(termios->c_cflag & PARODD)) | |
446 | utcr0 |= UTCR0_OES; | |
447 | } | |
448 | ||
449 | /* | |
450 | * Ask the core to calculate the divisor for us. | |
451 | */ | |
452 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
453 | quot = uart_get_divisor(port, baud); | |
454 | ||
455 | spin_lock_irqsave(&sport->port.lock, flags); | |
456 | ||
457 | sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS); | |
458 | sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR); | |
459 | if (termios->c_iflag & INPCK) | |
460 | sport->port.read_status_mask |= | |
461 | UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE); | |
462 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
463 | sport->port.read_status_mask |= | |
464 | UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB); | |
465 | ||
466 | /* | |
467 | * Characters to ignore | |
468 | */ | |
469 | sport->port.ignore_status_mask = 0; | |
470 | if (termios->c_iflag & IGNPAR) | |
471 | sport->port.ignore_status_mask |= | |
472 | UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE); | |
473 | if (termios->c_iflag & IGNBRK) { | |
474 | sport->port.ignore_status_mask |= | |
475 | UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB); | |
476 | /* | |
477 | * If we're ignoring parity and break indicators, | |
478 | * ignore overruns too (for real raw support). | |
479 | */ | |
480 | if (termios->c_iflag & IGNPAR) | |
481 | sport->port.ignore_status_mask |= | |
482 | UTSR1_TO_SM(UTSR1_ROR); | |
483 | } | |
484 | ||
485 | del_timer_sync(&sport->timer); | |
486 | ||
487 | /* | |
488 | * Update the per-port timeout. | |
489 | */ | |
490 | uart_update_timeout(port, termios->c_cflag, baud); | |
491 | ||
492 | /* | |
493 | * disable interrupts and drain transmitter | |
494 | */ | |
495 | old_utcr3 = UART_GET_UTCR3(sport); | |
496 | UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)); | |
497 | ||
498 | while (UART_GET_UTSR1(sport) & UTSR1_TBY) | |
499 | barrier(); | |
500 | ||
501 | /* then, disable everything */ | |
502 | UART_PUT_UTCR3(sport, 0); | |
503 | ||
504 | /* set the parity, stop bits and data size */ | |
505 | UART_PUT_UTCR0(sport, utcr0); | |
506 | ||
507 | /* set the baud rate */ | |
508 | quot -= 1; | |
509 | UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8)); | |
510 | UART_PUT_UTCR2(sport, (quot & 0xff)); | |
511 | ||
512 | UART_PUT_UTSR0(sport, -1); | |
513 | ||
514 | UART_PUT_UTCR3(sport, old_utcr3); | |
515 | ||
516 | if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) | |
517 | sa1100_enable_ms(&sport->port); | |
518 | ||
519 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
520 | } | |
521 | ||
522 | static const char *sa1100_type(struct uart_port *port) | |
523 | { | |
c9db776b FF |
524 | struct sa1100_port *sport = |
525 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
526 | |
527 | return sport->port.type == PORT_SA1100 ? "SA1100" : NULL; | |
528 | } | |
529 | ||
530 | /* | |
531 | * Release the memory region(s) being used by 'port'. | |
532 | */ | |
533 | static void sa1100_release_port(struct uart_port *port) | |
534 | { | |
c9db776b FF |
535 | struct sa1100_port *sport = |
536 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
537 | |
538 | release_mem_region(sport->port.mapbase, UART_PORT_SIZE); | |
539 | } | |
540 | ||
541 | /* | |
542 | * Request the memory region(s) being used by 'port'. | |
543 | */ | |
544 | static int sa1100_request_port(struct uart_port *port) | |
545 | { | |
c9db776b FF |
546 | struct sa1100_port *sport = |
547 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
548 | |
549 | return request_mem_region(sport->port.mapbase, UART_PORT_SIZE, | |
550 | "sa11x0-uart") != NULL ? 0 : -EBUSY; | |
551 | } | |
552 | ||
553 | /* | |
554 | * Configure/autoconfigure the port. | |
555 | */ | |
556 | static void sa1100_config_port(struct uart_port *port, int flags) | |
557 | { | |
c9db776b FF |
558 | struct sa1100_port *sport = |
559 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
560 | |
561 | if (flags & UART_CONFIG_TYPE && | |
562 | sa1100_request_port(&sport->port) == 0) | |
563 | sport->port.type = PORT_SA1100; | |
564 | } | |
565 | ||
566 | /* | |
567 | * Verify the new serial_struct (for TIOCSSERIAL). | |
568 | * The only change we allow are to the flags and type, and | |
569 | * even then only between PORT_SA1100 and PORT_UNKNOWN | |
570 | */ | |
571 | static int | |
572 | sa1100_verify_port(struct uart_port *port, struct serial_struct *ser) | |
573 | { | |
c9db776b FF |
574 | struct sa1100_port *sport = |
575 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
576 | int ret = 0; |
577 | ||
578 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100) | |
579 | ret = -EINVAL; | |
580 | if (sport->port.irq != ser->irq) | |
581 | ret = -EINVAL; | |
582 | if (ser->io_type != SERIAL_IO_MEM) | |
583 | ret = -EINVAL; | |
584 | if (sport->port.uartclk / 16 != ser->baud_base) | |
585 | ret = -EINVAL; | |
586 | if ((void *)sport->port.mapbase != ser->iomem_base) | |
587 | ret = -EINVAL; | |
588 | if (sport->port.iobase != ser->port) | |
589 | ret = -EINVAL; | |
590 | if (ser->hub6 != 0) | |
591 | ret = -EINVAL; | |
592 | return ret; | |
593 | } | |
594 | ||
595 | static struct uart_ops sa1100_pops = { | |
596 | .tx_empty = sa1100_tx_empty, | |
597 | .set_mctrl = sa1100_set_mctrl, | |
598 | .get_mctrl = sa1100_get_mctrl, | |
599 | .stop_tx = sa1100_stop_tx, | |
600 | .start_tx = sa1100_start_tx, | |
601 | .stop_rx = sa1100_stop_rx, | |
602 | .enable_ms = sa1100_enable_ms, | |
603 | .break_ctl = sa1100_break_ctl, | |
604 | .startup = sa1100_startup, | |
605 | .shutdown = sa1100_shutdown, | |
606 | .set_termios = sa1100_set_termios, | |
607 | .type = sa1100_type, | |
608 | .release_port = sa1100_release_port, | |
609 | .request_port = sa1100_request_port, | |
610 | .config_port = sa1100_config_port, | |
611 | .verify_port = sa1100_verify_port, | |
612 | }; | |
613 | ||
614 | static struct sa1100_port sa1100_ports[NR_PORTS]; | |
615 | ||
616 | /* | |
617 | * Setup the SA1100 serial ports. Note that we don't include the IrDA | |
618 | * port here since we have our own SIR/FIR driver (see drivers/net/irda) | |
619 | * | |
620 | * Note also that we support "console=ttySAx" where "x" is either 0 or 1. | |
621 | * Which serial port this ends up being depends on the machine you're | |
622 | * running this kernel on. I'm not convinced that this is a good idea, | |
623 | * but that's the way it traditionally works. | |
624 | * | |
625 | * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer | |
626 | * used here. | |
627 | */ | |
628 | static void __init sa1100_init_ports(void) | |
629 | { | |
630 | static int first = 1; | |
631 | int i; | |
632 | ||
633 | if (!first) | |
634 | return; | |
635 | first = 0; | |
636 | ||
637 | for (i = 0; i < NR_PORTS; i++) { | |
638 | sa1100_ports[i].port.uartclk = 3686400; | |
639 | sa1100_ports[i].port.ops = &sa1100_pops; | |
640 | sa1100_ports[i].port.fifosize = 8; | |
641 | sa1100_ports[i].port.line = i; | |
9b4a1617 | 642 | sa1100_ports[i].port.iotype = UPIO_MEM; |
1da177e4 LT |
643 | init_timer(&sa1100_ports[i].timer); |
644 | sa1100_ports[i].timer.function = sa1100_timeout; | |
645 | sa1100_ports[i].timer.data = (unsigned long)&sa1100_ports[i]; | |
646 | } | |
647 | ||
648 | /* | |
649 | * make transmit lines outputs, so that when the port | |
650 | * is closed, the output is in the MARK state. | |
651 | */ | |
652 | PPDR |= PPC_TXD1 | PPC_TXD3; | |
653 | PPSR |= PPC_TXD1 | PPC_TXD3; | |
654 | } | |
655 | ||
9671f099 | 656 | void sa1100_register_uart_fns(struct sa1100_port_fns *fns) |
1da177e4 LT |
657 | { |
658 | if (fns->get_mctrl) | |
659 | sa1100_pops.get_mctrl = fns->get_mctrl; | |
660 | if (fns->set_mctrl) | |
661 | sa1100_pops.set_mctrl = fns->set_mctrl; | |
662 | ||
663 | sa1100_pops.pm = fns->pm; | |
adedb750 LW |
664 | /* |
665 | * FIXME: fns->set_wake is unused - this should be called from | |
666 | * the suspend() callback if device_may_wakeup(dev)) is set. | |
667 | */ | |
1da177e4 LT |
668 | } |
669 | ||
670 | void __init sa1100_register_uart(int idx, int port) | |
671 | { | |
672 | if (idx >= NR_PORTS) { | |
71cc2c21 | 673 | printk(KERN_ERR "%s: bad index number %d\n", __func__, idx); |
1da177e4 LT |
674 | return; |
675 | } | |
676 | ||
677 | switch (port) { | |
678 | case 1: | |
679 | sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0; | |
680 | sa1100_ports[idx].port.mapbase = _Ser1UTCR0; | |
681 | sa1100_ports[idx].port.irq = IRQ_Ser1UART; | |
ce8337cb | 682 | sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; |
1da177e4 LT |
683 | break; |
684 | ||
685 | case 2: | |
686 | sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0; | |
687 | sa1100_ports[idx].port.mapbase = _Ser2UTCR0; | |
688 | sa1100_ports[idx].port.irq = IRQ_Ser2ICP; | |
ce8337cb | 689 | sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; |
1da177e4 LT |
690 | break; |
691 | ||
692 | case 3: | |
693 | sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0; | |
694 | sa1100_ports[idx].port.mapbase = _Ser3UTCR0; | |
695 | sa1100_ports[idx].port.irq = IRQ_Ser3UART; | |
ce8337cb | 696 | sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; |
1da177e4 LT |
697 | break; |
698 | ||
699 | default: | |
71cc2c21 | 700 | printk(KERN_ERR "%s: bad port number %d\n", __func__, port); |
1da177e4 LT |
701 | } |
702 | } | |
703 | ||
704 | ||
705 | #ifdef CONFIG_SERIAL_SA1100_CONSOLE | |
d358788f RK |
706 | static void sa1100_console_putchar(struct uart_port *port, int ch) |
707 | { | |
c9db776b FF |
708 | struct sa1100_port *sport = |
709 | container_of(port, struct sa1100_port, port); | |
d358788f RK |
710 | |
711 | while (!(UART_GET_UTSR1(sport) & UTSR1_TNF)) | |
712 | barrier(); | |
713 | UART_PUT_CHAR(sport, ch); | |
714 | } | |
1da177e4 LT |
715 | |
716 | /* | |
717 | * Interrupts are disabled on entering | |
718 | */ | |
719 | static void | |
720 | sa1100_console_write(struct console *co, const char *s, unsigned int count) | |
721 | { | |
722 | struct sa1100_port *sport = &sa1100_ports[co->index]; | |
d358788f | 723 | unsigned int old_utcr3, status; |
1da177e4 LT |
724 | |
725 | /* | |
726 | * First, save UTCR3 and then disable interrupts | |
727 | */ | |
728 | old_utcr3 = UART_GET_UTCR3(sport); | |
729 | UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) | | |
730 | UTCR3_TXE); | |
731 | ||
d358788f | 732 | uart_console_write(&sport->port, s, count, sa1100_console_putchar); |
1da177e4 LT |
733 | |
734 | /* | |
735 | * Finally, wait for transmitter to become empty | |
736 | * and restore UTCR3 | |
737 | */ | |
738 | do { | |
739 | status = UART_GET_UTSR1(sport); | |
740 | } while (status & UTSR1_TBY); | |
741 | UART_PUT_UTCR3(sport, old_utcr3); | |
742 | } | |
743 | ||
744 | /* | |
745 | * If the port was already initialised (eg, by a boot loader), | |
746 | * try to determine the current setup. | |
747 | */ | |
748 | static void __init | |
749 | sa1100_console_get_options(struct sa1100_port *sport, int *baud, | |
750 | int *parity, int *bits) | |
751 | { | |
752 | unsigned int utcr3; | |
753 | ||
754 | utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE); | |
755 | if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) { | |
756 | /* ok, the port was enabled */ | |
757 | unsigned int utcr0, quot; | |
758 | ||
759 | utcr0 = UART_GET_UTCR0(sport); | |
760 | ||
761 | *parity = 'n'; | |
762 | if (utcr0 & UTCR0_PE) { | |
763 | if (utcr0 & UTCR0_OES) | |
764 | *parity = 'e'; | |
765 | else | |
766 | *parity = 'o'; | |
767 | } | |
768 | ||
769 | if (utcr0 & UTCR0_DSS) | |
770 | *bits = 8; | |
771 | else | |
772 | *bits = 7; | |
773 | ||
774 | quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8; | |
775 | quot &= 0xfff; | |
776 | *baud = sport->port.uartclk / (16 * (quot + 1)); | |
777 | } | |
778 | } | |
779 | ||
780 | static int __init | |
781 | sa1100_console_setup(struct console *co, char *options) | |
782 | { | |
783 | struct sa1100_port *sport; | |
784 | int baud = 9600; | |
785 | int bits = 8; | |
786 | int parity = 'n'; | |
787 | int flow = 'n'; | |
788 | ||
789 | /* | |
790 | * Check whether an invalid uart number has been specified, and | |
791 | * if so, search for the first available port that does have | |
792 | * console support. | |
793 | */ | |
794 | if (co->index == -1 || co->index >= NR_PORTS) | |
795 | co->index = 0; | |
796 | sport = &sa1100_ports[co->index]; | |
797 | ||
798 | if (options) | |
799 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
800 | else | |
801 | sa1100_console_get_options(sport, &baud, &parity, &bits); | |
802 | ||
803 | return uart_set_options(&sport->port, co, baud, parity, bits, flow); | |
804 | } | |
805 | ||
2d93486c | 806 | static struct uart_driver sa1100_reg; |
1da177e4 LT |
807 | static struct console sa1100_console = { |
808 | .name = "ttySA", | |
809 | .write = sa1100_console_write, | |
810 | .device = uart_console_device, | |
811 | .setup = sa1100_console_setup, | |
812 | .flags = CON_PRINTBUFFER, | |
813 | .index = -1, | |
814 | .data = &sa1100_reg, | |
815 | }; | |
816 | ||
817 | static int __init sa1100_rs_console_init(void) | |
818 | { | |
819 | sa1100_init_ports(); | |
820 | register_console(&sa1100_console); | |
821 | return 0; | |
822 | } | |
823 | console_initcall(sa1100_rs_console_init); | |
824 | ||
825 | #define SA1100_CONSOLE &sa1100_console | |
826 | #else | |
827 | #define SA1100_CONSOLE NULL | |
828 | #endif | |
829 | ||
830 | static struct uart_driver sa1100_reg = { | |
831 | .owner = THIS_MODULE, | |
832 | .driver_name = "ttySA", | |
833 | .dev_name = "ttySA", | |
1da177e4 LT |
834 | .major = SERIAL_SA1100_MAJOR, |
835 | .minor = MINOR_START, | |
836 | .nr = NR_PORTS, | |
837 | .cons = SA1100_CONSOLE, | |
838 | }; | |
839 | ||
3ae5eaec | 840 | static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 841 | { |
3ae5eaec | 842 | struct sa1100_port *sport = platform_get_drvdata(dev); |
1da177e4 | 843 | |
9480e307 | 844 | if (sport) |
1da177e4 LT |
845 | uart_suspend_port(&sa1100_reg, &sport->port); |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
3ae5eaec | 850 | static int sa1100_serial_resume(struct platform_device *dev) |
1da177e4 | 851 | { |
3ae5eaec | 852 | struct sa1100_port *sport = platform_get_drvdata(dev); |
1da177e4 | 853 | |
9480e307 | 854 | if (sport) |
1da177e4 LT |
855 | uart_resume_port(&sa1100_reg, &sport->port); |
856 | ||
857 | return 0; | |
858 | } | |
859 | ||
3ae5eaec | 860 | static int sa1100_serial_probe(struct platform_device *dev) |
1da177e4 | 861 | { |
1da177e4 LT |
862 | struct resource *res = dev->resource; |
863 | int i; | |
864 | ||
865 | for (i = 0; i < dev->num_resources; i++, res++) | |
866 | if (res->flags & IORESOURCE_MEM) | |
867 | break; | |
868 | ||
869 | if (i < dev->num_resources) { | |
870 | for (i = 0; i < NR_PORTS; i++) { | |
871 | if (sa1100_ports[i].port.mapbase != res->start) | |
872 | continue; | |
873 | ||
3ae5eaec | 874 | sa1100_ports[i].port.dev = &dev->dev; |
1da177e4 | 875 | uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port); |
3ae5eaec | 876 | platform_set_drvdata(dev, &sa1100_ports[i]); |
1da177e4 LT |
877 | break; |
878 | } | |
879 | } | |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
3ae5eaec | 884 | static int sa1100_serial_remove(struct platform_device *pdev) |
1da177e4 | 885 | { |
3ae5eaec | 886 | struct sa1100_port *sport = platform_get_drvdata(pdev); |
1da177e4 | 887 | |
1da177e4 LT |
888 | if (sport) |
889 | uart_remove_one_port(&sa1100_reg, &sport->port); | |
890 | ||
891 | return 0; | |
892 | } | |
893 | ||
3ae5eaec | 894 | static struct platform_driver sa11x0_serial_driver = { |
1da177e4 LT |
895 | .probe = sa1100_serial_probe, |
896 | .remove = sa1100_serial_remove, | |
897 | .suspend = sa1100_serial_suspend, | |
898 | .resume = sa1100_serial_resume, | |
3ae5eaec RK |
899 | .driver = { |
900 | .name = "sa11x0-uart", | |
901 | }, | |
1da177e4 LT |
902 | }; |
903 | ||
904 | static int __init sa1100_serial_init(void) | |
905 | { | |
906 | int ret; | |
907 | ||
d87a6d95 | 908 | printk(KERN_INFO "Serial: SA11x0 driver\n"); |
1da177e4 LT |
909 | |
910 | sa1100_init_ports(); | |
911 | ||
912 | ret = uart_register_driver(&sa1100_reg); | |
913 | if (ret == 0) { | |
3ae5eaec | 914 | ret = platform_driver_register(&sa11x0_serial_driver); |
1da177e4 LT |
915 | if (ret) |
916 | uart_unregister_driver(&sa1100_reg); | |
917 | } | |
918 | return ret; | |
919 | } | |
920 | ||
921 | static void __exit sa1100_serial_exit(void) | |
922 | { | |
3ae5eaec | 923 | platform_driver_unregister(&sa11x0_serial_driver); |
1da177e4 LT |
924 | uart_unregister_driver(&sa1100_reg); |
925 | } | |
926 | ||
927 | module_init(sa1100_serial_init); | |
928 | module_exit(sa1100_serial_exit); | |
929 | ||
930 | MODULE_AUTHOR("Deep Blue Solutions Ltd"); | |
d87a6d95 | 931 | MODULE_DESCRIPTION("SA1100 generic serial port driver"); |
1da177e4 LT |
932 | MODULE_LICENSE("GPL"); |
933 | MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR); | |
e169c139 | 934 | MODULE_ALIAS("platform:sa11x0-uart"); |