]>
Commit | Line | Data |
---|---|---|
99edb3d1 | 1 | /* |
b497549a BD |
2 | * Driver core for Samsung SoC onboard UARTs. |
3 | * | |
ccae941e | 4 | * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics |
b497549a BD |
5 | * http://armlinux.simtec.co.uk/ |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | /* Hote on 2410 error handling | |
13 | * | |
14 | * The s3c2410 manual has a love/hate affair with the contents of the | |
15 | * UERSTAT register in the UART blocks, and keeps marking some of the | |
16 | * error bits as reserved. Having checked with the s3c2410x01, | |
17 | * it copes with BREAKs properly, so I am happy to ignore the RESERVED | |
18 | * feature from the latter versions of the manual. | |
19 | * | |
20 | * If it becomes aparrent that latter versions of the 2410 remove these | |
21 | * bits, then action will have to be taken to differentiate the versions | |
22 | * and change the policy on BREAK | |
23 | * | |
24 | * BJD, 04-Nov-2004 | |
25 | */ | |
26 | ||
27 | #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
28 | #define SUPPORT_SYSRQ | |
29 | #endif | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/io.h> | |
34 | #include <linux/platform_device.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/sysrq.h> | |
37 | #include <linux/console.h> | |
38 | #include <linux/tty.h> | |
39 | #include <linux/tty_flip.h> | |
40 | #include <linux/serial_core.h> | |
41 | #include <linux/serial.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/clk.h> | |
30555476 | 44 | #include <linux/cpufreq.h> |
26c919e1 | 45 | #include <linux/of.h> |
b497549a BD |
46 | |
47 | #include <asm/irq.h> | |
48 | ||
a09e64fb | 49 | #include <mach/hardware.h> |
b497549a | 50 | |
a2b7ba9c | 51 | #include <plat/regs-serial.h> |
5f5a7a55 | 52 | #include <plat/clock.h> |
b497549a BD |
53 | |
54 | #include "samsung.h" | |
55 | ||
56 | /* UART name and device definitions */ | |
57 | ||
58 | #define S3C24XX_SERIAL_NAME "ttySAC" | |
59 | #define S3C24XX_SERIAL_MAJOR 204 | |
60 | #define S3C24XX_SERIAL_MINOR 64 | |
61 | ||
b497549a BD |
62 | /* macros to change one thing to another */ |
63 | ||
64 | #define tx_enabled(port) ((port)->unused[0]) | |
65 | #define rx_enabled(port) ((port)->unused[1]) | |
66 | ||
25985edc | 67 | /* flag to ignore all characters coming in */ |
b497549a BD |
68 | #define RXSTAT_DUMMY_READ (0x10000000) |
69 | ||
70 | static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) | |
71 | { | |
72 | return container_of(port, struct s3c24xx_uart_port, port); | |
73 | } | |
74 | ||
75 | /* translate a port to the device name */ | |
76 | ||
77 | static inline const char *s3c24xx_serial_portname(struct uart_port *port) | |
78 | { | |
79 | return to_platform_device(port->dev)->name; | |
80 | } | |
81 | ||
82 | static int s3c24xx_serial_txempty_nofifo(struct uart_port *port) | |
83 | { | |
9303ac15 | 84 | return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE; |
b497549a BD |
85 | } |
86 | ||
88bb4ea1 TA |
87 | /* |
88 | * s3c64xx and later SoC's include the interrupt mask and status registers in | |
89 | * the controller itself, unlike the s3c24xx SoC's which have these registers | |
90 | * in the interrupt controller. Check if the port type is s3c64xx or higher. | |
91 | */ | |
92 | static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port) | |
93 | { | |
94 | return to_ourport(port)->info->type == PORT_S3C6400; | |
95 | } | |
96 | ||
b497549a BD |
97 | static void s3c24xx_serial_rx_enable(struct uart_port *port) |
98 | { | |
99 | unsigned long flags; | |
100 | unsigned int ucon, ufcon; | |
101 | int count = 10000; | |
102 | ||
103 | spin_lock_irqsave(&port->lock, flags); | |
104 | ||
105 | while (--count && !s3c24xx_serial_txempty_nofifo(port)) | |
106 | udelay(100); | |
107 | ||
108 | ufcon = rd_regl(port, S3C2410_UFCON); | |
109 | ufcon |= S3C2410_UFCON_RESETRX; | |
110 | wr_regl(port, S3C2410_UFCON, ufcon); | |
111 | ||
112 | ucon = rd_regl(port, S3C2410_UCON); | |
113 | ucon |= S3C2410_UCON_RXIRQMODE; | |
114 | wr_regl(port, S3C2410_UCON, ucon); | |
115 | ||
116 | rx_enabled(port) = 1; | |
117 | spin_unlock_irqrestore(&port->lock, flags); | |
118 | } | |
119 | ||
120 | static void s3c24xx_serial_rx_disable(struct uart_port *port) | |
121 | { | |
122 | unsigned long flags; | |
123 | unsigned int ucon; | |
124 | ||
125 | spin_lock_irqsave(&port->lock, flags); | |
126 | ||
127 | ucon = rd_regl(port, S3C2410_UCON); | |
128 | ucon &= ~S3C2410_UCON_RXIRQMODE; | |
129 | wr_regl(port, S3C2410_UCON, ucon); | |
130 | ||
131 | rx_enabled(port) = 0; | |
132 | spin_unlock_irqrestore(&port->lock, flags); | |
133 | } | |
134 | ||
135 | static void s3c24xx_serial_stop_tx(struct uart_port *port) | |
136 | { | |
b73c289c BD |
137 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
138 | ||
b497549a | 139 | if (tx_enabled(port)) { |
88bb4ea1 TA |
140 | if (s3c24xx_serial_has_interrupt_mask(port)) |
141 | __set_bit(S3C64XX_UINTM_TXD, | |
142 | portaddrl(port, S3C64XX_UINTM)); | |
143 | else | |
144 | disable_irq_nosync(ourport->tx_irq); | |
b497549a BD |
145 | tx_enabled(port) = 0; |
146 | if (port->flags & UPF_CONS_FLOW) | |
147 | s3c24xx_serial_rx_enable(port); | |
148 | } | |
149 | } | |
150 | ||
151 | static void s3c24xx_serial_start_tx(struct uart_port *port) | |
152 | { | |
b73c289c BD |
153 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
154 | ||
b497549a BD |
155 | if (!tx_enabled(port)) { |
156 | if (port->flags & UPF_CONS_FLOW) | |
157 | s3c24xx_serial_rx_disable(port); | |
158 | ||
88bb4ea1 TA |
159 | if (s3c24xx_serial_has_interrupt_mask(port)) |
160 | __clear_bit(S3C64XX_UINTM_TXD, | |
161 | portaddrl(port, S3C64XX_UINTM)); | |
162 | else | |
163 | enable_irq(ourport->tx_irq); | |
b497549a BD |
164 | tx_enabled(port) = 1; |
165 | } | |
166 | } | |
167 | ||
b497549a BD |
168 | static void s3c24xx_serial_stop_rx(struct uart_port *port) |
169 | { | |
b73c289c BD |
170 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
171 | ||
b497549a BD |
172 | if (rx_enabled(port)) { |
173 | dbg("s3c24xx_serial_stop_rx: port=%p\n", port); | |
88bb4ea1 TA |
174 | if (s3c24xx_serial_has_interrupt_mask(port)) |
175 | __set_bit(S3C64XX_UINTM_RXD, | |
176 | portaddrl(port, S3C64XX_UINTM)); | |
177 | else | |
178 | disable_irq_nosync(ourport->rx_irq); | |
b497549a BD |
179 | rx_enabled(port) = 0; |
180 | } | |
181 | } | |
182 | ||
183 | static void s3c24xx_serial_enable_ms(struct uart_port *port) | |
184 | { | |
185 | } | |
186 | ||
187 | static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port) | |
188 | { | |
189 | return to_ourport(port)->info; | |
190 | } | |
191 | ||
192 | static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port) | |
193 | { | |
4d84e970 TA |
194 | struct s3c24xx_uart_port *ourport; |
195 | ||
b497549a BD |
196 | if (port->dev == NULL) |
197 | return NULL; | |
198 | ||
4d84e970 TA |
199 | ourport = container_of(port, struct s3c24xx_uart_port, port); |
200 | return ourport->cfg; | |
b497549a BD |
201 | } |
202 | ||
203 | static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport, | |
204 | unsigned long ufstat) | |
205 | { | |
206 | struct s3c24xx_uart_info *info = ourport->info; | |
207 | ||
208 | if (ufstat & info->rx_fifofull) | |
da121506 | 209 | return ourport->port.fifosize; |
b497549a BD |
210 | |
211 | return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; | |
212 | } | |
213 | ||
214 | ||
215 | /* ? - where has parity gone?? */ | |
216 | #define S3C2410_UERSTAT_PARITY (0x1000) | |
217 | ||
218 | static irqreturn_t | |
219 | s3c24xx_serial_rx_chars(int irq, void *dev_id) | |
220 | { | |
221 | struct s3c24xx_uart_port *ourport = dev_id; | |
222 | struct uart_port *port = &ourport->port; | |
b497549a | 223 | unsigned int ufcon, ch, flag, ufstat, uerstat; |
c15c3747 | 224 | unsigned long flags; |
b497549a BD |
225 | int max_count = 64; |
226 | ||
c15c3747 TA |
227 | spin_lock_irqsave(&port->lock, flags); |
228 | ||
b497549a BD |
229 | while (max_count-- > 0) { |
230 | ufcon = rd_regl(port, S3C2410_UFCON); | |
231 | ufstat = rd_regl(port, S3C2410_UFSTAT); | |
232 | ||
233 | if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) | |
234 | break; | |
235 | ||
236 | uerstat = rd_regl(port, S3C2410_UERSTAT); | |
237 | ch = rd_regb(port, S3C2410_URXH); | |
238 | ||
239 | if (port->flags & UPF_CONS_FLOW) { | |
240 | int txe = s3c24xx_serial_txempty_nofifo(port); | |
241 | ||
242 | if (rx_enabled(port)) { | |
243 | if (!txe) { | |
244 | rx_enabled(port) = 0; | |
245 | continue; | |
246 | } | |
247 | } else { | |
248 | if (txe) { | |
249 | ufcon |= S3C2410_UFCON_RESETRX; | |
250 | wr_regl(port, S3C2410_UFCON, ufcon); | |
251 | rx_enabled(port) = 1; | |
252 | goto out; | |
253 | } | |
254 | continue; | |
255 | } | |
256 | } | |
257 | ||
258 | /* insert the character into the buffer */ | |
259 | ||
260 | flag = TTY_NORMAL; | |
261 | port->icount.rx++; | |
262 | ||
263 | if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { | |
264 | dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n", | |
265 | ch, uerstat); | |
266 | ||
267 | /* check for break */ | |
268 | if (uerstat & S3C2410_UERSTAT_BREAK) { | |
269 | dbg("break!\n"); | |
270 | port->icount.brk++; | |
271 | if (uart_handle_break(port)) | |
9303ac15 | 272 | goto ignore_char; |
b497549a BD |
273 | } |
274 | ||
275 | if (uerstat & S3C2410_UERSTAT_FRAME) | |
276 | port->icount.frame++; | |
277 | if (uerstat & S3C2410_UERSTAT_OVERRUN) | |
278 | port->icount.overrun++; | |
279 | ||
280 | uerstat &= port->read_status_mask; | |
281 | ||
282 | if (uerstat & S3C2410_UERSTAT_BREAK) | |
283 | flag = TTY_BREAK; | |
284 | else if (uerstat & S3C2410_UERSTAT_PARITY) | |
285 | flag = TTY_PARITY; | |
286 | else if (uerstat & (S3C2410_UERSTAT_FRAME | | |
287 | S3C2410_UERSTAT_OVERRUN)) | |
288 | flag = TTY_FRAME; | |
289 | } | |
290 | ||
291 | if (uart_handle_sysrq_char(port, ch)) | |
292 | goto ignore_char; | |
293 | ||
294 | uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, | |
295 | ch, flag); | |
296 | ||
297 | ignore_char: | |
298 | continue; | |
299 | } | |
2e124b4a | 300 | tty_flip_buffer_push(&port->state->port); |
b497549a BD |
301 | |
302 | out: | |
c15c3747 | 303 | spin_unlock_irqrestore(&port->lock, flags); |
b497549a BD |
304 | return IRQ_HANDLED; |
305 | } | |
306 | ||
307 | static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) | |
308 | { | |
309 | struct s3c24xx_uart_port *ourport = id; | |
310 | struct uart_port *port = &ourport->port; | |
ebd2c8f6 | 311 | struct circ_buf *xmit = &port->state->xmit; |
c15c3747 | 312 | unsigned long flags; |
b497549a BD |
313 | int count = 256; |
314 | ||
c15c3747 TA |
315 | spin_lock_irqsave(&port->lock, flags); |
316 | ||
b497549a BD |
317 | if (port->x_char) { |
318 | wr_regb(port, S3C2410_UTXH, port->x_char); | |
319 | port->icount.tx++; | |
320 | port->x_char = 0; | |
321 | goto out; | |
322 | } | |
323 | ||
25985edc | 324 | /* if there isn't anything more to transmit, or the uart is now |
b497549a BD |
325 | * stopped, disable the uart and exit |
326 | */ | |
327 | ||
328 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
329 | s3c24xx_serial_stop_tx(port); | |
330 | goto out; | |
331 | } | |
332 | ||
333 | /* try and drain the buffer... */ | |
334 | ||
335 | while (!uart_circ_empty(xmit) && count-- > 0) { | |
336 | if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) | |
337 | break; | |
338 | ||
339 | wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); | |
340 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
341 | port->icount.tx++; | |
342 | } | |
343 | ||
c15c3747 TA |
344 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { |
345 | spin_unlock(&port->lock); | |
b497549a | 346 | uart_write_wakeup(port); |
c15c3747 TA |
347 | spin_lock(&port->lock); |
348 | } | |
b497549a BD |
349 | |
350 | if (uart_circ_empty(xmit)) | |
351 | s3c24xx_serial_stop_tx(port); | |
352 | ||
353 | out: | |
c15c3747 | 354 | spin_unlock_irqrestore(&port->lock, flags); |
b497549a BD |
355 | return IRQ_HANDLED; |
356 | } | |
357 | ||
88bb4ea1 TA |
358 | /* interrupt handler for s3c64xx and later SoC's.*/ |
359 | static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id) | |
360 | { | |
361 | struct s3c24xx_uart_port *ourport = id; | |
362 | struct uart_port *port = &ourport->port; | |
363 | unsigned int pend = rd_regl(port, S3C64XX_UINTP); | |
88bb4ea1 TA |
364 | irqreturn_t ret = IRQ_HANDLED; |
365 | ||
88bb4ea1 TA |
366 | if (pend & S3C64XX_UINTM_RXD_MSK) { |
367 | ret = s3c24xx_serial_rx_chars(irq, id); | |
368 | wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); | |
369 | } | |
370 | if (pend & S3C64XX_UINTM_TXD_MSK) { | |
371 | ret = s3c24xx_serial_tx_chars(irq, id); | |
372 | wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); | |
373 | } | |
88bb4ea1 TA |
374 | return ret; |
375 | } | |
376 | ||
b497549a BD |
377 | static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) |
378 | { | |
379 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
380 | unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT); | |
381 | unsigned long ufcon = rd_regl(port, S3C2410_UFCON); | |
382 | ||
383 | if (ufcon & S3C2410_UFCON_FIFOMODE) { | |
384 | if ((ufstat & info->tx_fifomask) != 0 || | |
385 | (ufstat & info->tx_fifofull)) | |
386 | return 0; | |
387 | ||
388 | return 1; | |
389 | } | |
390 | ||
391 | return s3c24xx_serial_txempty_nofifo(port); | |
392 | } | |
393 | ||
394 | /* no modem control lines */ | |
395 | static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) | |
396 | { | |
397 | unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); | |
398 | ||
399 | if (umstat & S3C2410_UMSTAT_CTS) | |
400 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; | |
401 | else | |
402 | return TIOCM_CAR | TIOCM_DSR; | |
403 | } | |
404 | ||
405 | static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
406 | { | |
407 | /* todo - possibly remove AFC and do manual CTS */ | |
408 | } | |
409 | ||
410 | static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) | |
411 | { | |
412 | unsigned long flags; | |
413 | unsigned int ucon; | |
414 | ||
415 | spin_lock_irqsave(&port->lock, flags); | |
416 | ||
417 | ucon = rd_regl(port, S3C2410_UCON); | |
418 | ||
419 | if (break_state) | |
420 | ucon |= S3C2410_UCON_SBREAK; | |
421 | else | |
422 | ucon &= ~S3C2410_UCON_SBREAK; | |
423 | ||
424 | wr_regl(port, S3C2410_UCON, ucon); | |
425 | ||
426 | spin_unlock_irqrestore(&port->lock, flags); | |
427 | } | |
428 | ||
429 | static void s3c24xx_serial_shutdown(struct uart_port *port) | |
430 | { | |
431 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
432 | ||
433 | if (ourport->tx_claimed) { | |
88bb4ea1 TA |
434 | if (!s3c24xx_serial_has_interrupt_mask(port)) |
435 | free_irq(ourport->tx_irq, ourport); | |
b497549a BD |
436 | tx_enabled(port) = 0; |
437 | ourport->tx_claimed = 0; | |
438 | } | |
439 | ||
440 | if (ourport->rx_claimed) { | |
88bb4ea1 TA |
441 | if (!s3c24xx_serial_has_interrupt_mask(port)) |
442 | free_irq(ourport->rx_irq, ourport); | |
b497549a BD |
443 | ourport->rx_claimed = 0; |
444 | rx_enabled(port) = 0; | |
445 | } | |
b497549a | 446 | |
88bb4ea1 TA |
447 | /* Clear pending interrupts and mask all interrupts */ |
448 | if (s3c24xx_serial_has_interrupt_mask(port)) { | |
449 | wr_regl(port, S3C64XX_UINTP, 0xf); | |
450 | wr_regl(port, S3C64XX_UINTM, 0xf); | |
451 | } | |
452 | } | |
b497549a BD |
453 | |
454 | static int s3c24xx_serial_startup(struct uart_port *port) | |
455 | { | |
456 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
457 | int ret; | |
458 | ||
459 | dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n", | |
460 | port->mapbase, port->membase); | |
461 | ||
462 | rx_enabled(port) = 1; | |
463 | ||
b73c289c | 464 | ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0, |
b497549a BD |
465 | s3c24xx_serial_portname(port), ourport); |
466 | ||
467 | if (ret != 0) { | |
d20925e1 | 468 | dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq); |
b497549a BD |
469 | return ret; |
470 | } | |
471 | ||
472 | ourport->rx_claimed = 1; | |
473 | ||
474 | dbg("requesting tx irq...\n"); | |
475 | ||
476 | tx_enabled(port) = 1; | |
477 | ||
b73c289c | 478 | ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0, |
b497549a BD |
479 | s3c24xx_serial_portname(port), ourport); |
480 | ||
481 | if (ret) { | |
d20925e1 | 482 | dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq); |
b497549a BD |
483 | goto err; |
484 | } | |
485 | ||
486 | ourport->tx_claimed = 1; | |
487 | ||
488 | dbg("s3c24xx_serial_startup ok\n"); | |
489 | ||
490 | /* the port reset code should have done the correct | |
491 | * register setup for the port controls */ | |
492 | ||
493 | return ret; | |
494 | ||
495 | err: | |
496 | s3c24xx_serial_shutdown(port); | |
497 | return ret; | |
498 | } | |
499 | ||
88bb4ea1 TA |
500 | static int s3c64xx_serial_startup(struct uart_port *port) |
501 | { | |
502 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
503 | int ret; | |
504 | ||
505 | dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n", | |
506 | port->mapbase, port->membase); | |
507 | ||
508 | ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED, | |
509 | s3c24xx_serial_portname(port), ourport); | |
510 | if (ret) { | |
d20925e1 | 511 | dev_err(port->dev, "cannot get irq %d\n", port->irq); |
88bb4ea1 TA |
512 | return ret; |
513 | } | |
514 | ||
515 | /* For compatibility with s3c24xx Soc's */ | |
516 | rx_enabled(port) = 1; | |
517 | ourport->rx_claimed = 1; | |
518 | tx_enabled(port) = 0; | |
519 | ourport->tx_claimed = 1; | |
520 | ||
521 | /* Enable Rx Interrupt */ | |
522 | __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM)); | |
523 | dbg("s3c64xx_serial_startup ok\n"); | |
524 | return ret; | |
525 | } | |
526 | ||
b497549a BD |
527 | /* power power management control */ |
528 | ||
529 | static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, | |
530 | unsigned int old) | |
531 | { | |
532 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
533 | ||
30555476 BD |
534 | ourport->pm_level = level; |
535 | ||
b497549a BD |
536 | switch (level) { |
537 | case 3: | |
7cd88831 | 538 | if (!IS_ERR(ourport->baudclk)) |
9484b009 | 539 | clk_disable_unprepare(ourport->baudclk); |
b497549a | 540 | |
9484b009 | 541 | clk_disable_unprepare(ourport->clk); |
b497549a BD |
542 | break; |
543 | ||
544 | case 0: | |
9484b009 | 545 | clk_prepare_enable(ourport->clk); |
b497549a | 546 | |
7cd88831 | 547 | if (!IS_ERR(ourport->baudclk)) |
9484b009 | 548 | clk_prepare_enable(ourport->baudclk); |
b497549a BD |
549 | |
550 | break; | |
551 | default: | |
d20925e1 | 552 | dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); |
b497549a BD |
553 | } |
554 | } | |
555 | ||
556 | /* baud rate calculation | |
557 | * | |
558 | * The UARTs on the S3C2410/S3C2440 can take their clocks from a number | |
559 | * of different sources, including the peripheral clock ("pclk") and an | |
560 | * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") | |
561 | * with a programmable extra divisor. | |
562 | * | |
563 | * The following code goes through the clock sources, and calculates the | |
564 | * baud clocks (and the resultant actual baud rates) and then tries to | |
565 | * pick the closest one and select that. | |
566 | * | |
567 | */ | |
568 | ||
5f5a7a55 | 569 | #define MAX_CLK_NAME_LENGTH 15 |
b497549a | 570 | |
5f5a7a55 | 571 | static inline int s3c24xx_serial_getsource(struct uart_port *port) |
b497549a BD |
572 | { |
573 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
5f5a7a55 | 574 | unsigned int ucon; |
b497549a | 575 | |
5f5a7a55 TA |
576 | if (info->num_clks == 1) |
577 | return 0; | |
b497549a | 578 | |
5f5a7a55 TA |
579 | ucon = rd_regl(port, S3C2410_UCON); |
580 | ucon &= info->clksel_mask; | |
581 | return ucon >> info->clksel_shift; | |
b497549a BD |
582 | } |
583 | ||
5f5a7a55 TA |
584 | static void s3c24xx_serial_setsource(struct uart_port *port, |
585 | unsigned int clk_sel) | |
b497549a | 586 | { |
5f5a7a55 TA |
587 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); |
588 | unsigned int ucon; | |
b497549a | 589 | |
5f5a7a55 TA |
590 | if (info->num_clks == 1) |
591 | return; | |
090f848d | 592 | |
5f5a7a55 TA |
593 | ucon = rd_regl(port, S3C2410_UCON); |
594 | if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel) | |
595 | return; | |
b497549a | 596 | |
5f5a7a55 TA |
597 | ucon &= ~info->clksel_mask; |
598 | ucon |= clk_sel << info->clksel_shift; | |
599 | wr_regl(port, S3C2410_UCON, ucon); | |
b497549a BD |
600 | } |
601 | ||
5f5a7a55 TA |
602 | static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, |
603 | unsigned int req_baud, struct clk **best_clk, | |
604 | unsigned int *clk_num) | |
b497549a | 605 | { |
5f5a7a55 TA |
606 | struct s3c24xx_uart_info *info = ourport->info; |
607 | struct clk *clk; | |
608 | unsigned long rate; | |
609 | unsigned int cnt, baud, quot, clk_sel, best_quot = 0; | |
610 | char clkname[MAX_CLK_NAME_LENGTH]; | |
611 | int calc_deviation, deviation = (1 << 30) - 1; | |
612 | ||
5f5a7a55 TA |
613 | clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel : |
614 | ourport->info->def_clk_sel; | |
615 | for (cnt = 0; cnt < info->num_clks; cnt++) { | |
616 | if (!(clk_sel & (1 << cnt))) | |
617 | continue; | |
618 | ||
619 | sprintf(clkname, "clk_uart_baud%d", cnt); | |
620 | clk = clk_get(ourport->port.dev, clkname); | |
7cd88831 | 621 | if (IS_ERR(clk)) |
5f5a7a55 TA |
622 | continue; |
623 | ||
624 | rate = clk_get_rate(clk); | |
625 | if (!rate) | |
626 | continue; | |
627 | ||
628 | if (ourport->info->has_divslot) { | |
629 | unsigned long div = rate / req_baud; | |
630 | ||
631 | /* The UDIVSLOT register on the newer UARTs allows us to | |
632 | * get a divisor adjustment of 1/16th on the baud clock. | |
633 | * | |
634 | * We don't keep the UDIVSLOT value (the 16ths we | |
635 | * calculated by not multiplying the baud by 16) as it | |
636 | * is easy enough to recalculate. | |
637 | */ | |
638 | ||
639 | quot = div / 16; | |
640 | baud = rate / div; | |
641 | } else { | |
642 | quot = (rate + (8 * req_baud)) / (16 * req_baud); | |
643 | baud = rate / (quot * 16); | |
b497549a | 644 | } |
5f5a7a55 | 645 | quot--; |
b497549a | 646 | |
5f5a7a55 TA |
647 | calc_deviation = req_baud - baud; |
648 | if (calc_deviation < 0) | |
649 | calc_deviation = -calc_deviation; | |
b497549a | 650 | |
5f5a7a55 TA |
651 | if (calc_deviation < deviation) { |
652 | *best_clk = clk; | |
653 | best_quot = quot; | |
654 | *clk_num = cnt; | |
655 | deviation = calc_deviation; | |
b497549a BD |
656 | } |
657 | } | |
658 | ||
5f5a7a55 | 659 | return best_quot; |
b497549a BD |
660 | } |
661 | ||
090f848d BD |
662 | /* udivslot_table[] |
663 | * | |
664 | * This table takes the fractional value of the baud divisor and gives | |
665 | * the recommended setting for the UDIVSLOT register. | |
666 | */ | |
667 | static u16 udivslot_table[16] = { | |
668 | [0] = 0x0000, | |
669 | [1] = 0x0080, | |
670 | [2] = 0x0808, | |
671 | [3] = 0x0888, | |
672 | [4] = 0x2222, | |
673 | [5] = 0x4924, | |
674 | [6] = 0x4A52, | |
675 | [7] = 0x54AA, | |
676 | [8] = 0x5555, | |
677 | [9] = 0xD555, | |
678 | [10] = 0xD5D5, | |
679 | [11] = 0xDDD5, | |
680 | [12] = 0xDDDD, | |
681 | [13] = 0xDFDD, | |
682 | [14] = 0xDFDF, | |
683 | [15] = 0xFFDF, | |
684 | }; | |
685 | ||
b497549a BD |
686 | static void s3c24xx_serial_set_termios(struct uart_port *port, |
687 | struct ktermios *termios, | |
688 | struct ktermios *old) | |
689 | { | |
690 | struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); | |
691 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
7cd88831 | 692 | struct clk *clk = ERR_PTR(-EINVAL); |
b497549a | 693 | unsigned long flags; |
5f5a7a55 | 694 | unsigned int baud, quot, clk_sel = 0; |
b497549a BD |
695 | unsigned int ulcon; |
696 | unsigned int umcon; | |
090f848d | 697 | unsigned int udivslot = 0; |
b497549a BD |
698 | |
699 | /* | |
700 | * We don't support modem control lines. | |
701 | */ | |
702 | termios->c_cflag &= ~(HUPCL | CMSPAR); | |
703 | termios->c_cflag |= CLOCAL; | |
704 | ||
705 | /* | |
706 | * Ask the core to calculate the divisor for us. | |
707 | */ | |
708 | ||
709 | baud = uart_get_baud_rate(port, termios, old, 0, 115200*8); | |
5f5a7a55 | 710 | quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); |
b497549a BD |
711 | if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) |
712 | quot = port->custom_divisor; | |
7cd88831 | 713 | if (IS_ERR(clk)) |
5f5a7a55 | 714 | return; |
b497549a BD |
715 | |
716 | /* check to see if we need to change clock source */ | |
717 | ||
5f5a7a55 TA |
718 | if (ourport->baudclk != clk) { |
719 | s3c24xx_serial_setsource(port, clk_sel); | |
b497549a | 720 | |
7cd88831 | 721 | if (!IS_ERR(ourport->baudclk)) { |
9484b009 | 722 | clk_disable_unprepare(ourport->baudclk); |
7cd88831 | 723 | ourport->baudclk = ERR_PTR(-EINVAL); |
b497549a BD |
724 | } |
725 | ||
9484b009 | 726 | clk_prepare_enable(clk); |
b497549a | 727 | |
b497549a | 728 | ourport->baudclk = clk; |
30555476 | 729 | ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; |
b497549a BD |
730 | } |
731 | ||
090f848d BD |
732 | if (ourport->info->has_divslot) { |
733 | unsigned int div = ourport->baudclk_rate / baud; | |
734 | ||
8b526ae4 JL |
735 | if (cfg->has_fracval) { |
736 | udivslot = (div & 15); | |
737 | dbg("fracval = %04x\n", udivslot); | |
738 | } else { | |
739 | udivslot = udivslot_table[div & 15]; | |
740 | dbg("udivslot = %04x (div %d)\n", udivslot, div & 15); | |
741 | } | |
090f848d BD |
742 | } |
743 | ||
b497549a BD |
744 | switch (termios->c_cflag & CSIZE) { |
745 | case CS5: | |
746 | dbg("config: 5bits/char\n"); | |
747 | ulcon = S3C2410_LCON_CS5; | |
748 | break; | |
749 | case CS6: | |
750 | dbg("config: 6bits/char\n"); | |
751 | ulcon = S3C2410_LCON_CS6; | |
752 | break; | |
753 | case CS7: | |
754 | dbg("config: 7bits/char\n"); | |
755 | ulcon = S3C2410_LCON_CS7; | |
756 | break; | |
757 | case CS8: | |
758 | default: | |
759 | dbg("config: 8bits/char\n"); | |
760 | ulcon = S3C2410_LCON_CS8; | |
761 | break; | |
762 | } | |
763 | ||
764 | /* preserve original lcon IR settings */ | |
765 | ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); | |
766 | ||
767 | if (termios->c_cflag & CSTOPB) | |
768 | ulcon |= S3C2410_LCON_STOPB; | |
769 | ||
770 | umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0; | |
771 | ||
772 | if (termios->c_cflag & PARENB) { | |
773 | if (termios->c_cflag & PARODD) | |
774 | ulcon |= S3C2410_LCON_PODD; | |
775 | else | |
776 | ulcon |= S3C2410_LCON_PEVEN; | |
777 | } else { | |
778 | ulcon |= S3C2410_LCON_PNONE; | |
779 | } | |
780 | ||
781 | spin_lock_irqsave(&port->lock, flags); | |
782 | ||
090f848d BD |
783 | dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n", |
784 | ulcon, quot, udivslot); | |
b497549a BD |
785 | |
786 | wr_regl(port, S3C2410_ULCON, ulcon); | |
787 | wr_regl(port, S3C2410_UBRDIV, quot); | |
788 | wr_regl(port, S3C2410_UMCON, umcon); | |
789 | ||
090f848d BD |
790 | if (ourport->info->has_divslot) |
791 | wr_regl(port, S3C2443_DIVSLOT, udivslot); | |
792 | ||
b497549a BD |
793 | dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", |
794 | rd_regl(port, S3C2410_ULCON), | |
795 | rd_regl(port, S3C2410_UCON), | |
796 | rd_regl(port, S3C2410_UFCON)); | |
797 | ||
798 | /* | |
799 | * Update the per-port timeout. | |
800 | */ | |
801 | uart_update_timeout(port, termios->c_cflag, baud); | |
802 | ||
803 | /* | |
804 | * Which character status flags are we interested in? | |
805 | */ | |
806 | port->read_status_mask = S3C2410_UERSTAT_OVERRUN; | |
807 | if (termios->c_iflag & INPCK) | |
808 | port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY; | |
809 | ||
810 | /* | |
811 | * Which character status flags should we ignore? | |
812 | */ | |
813 | port->ignore_status_mask = 0; | |
814 | if (termios->c_iflag & IGNPAR) | |
815 | port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; | |
816 | if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) | |
817 | port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; | |
818 | ||
819 | /* | |
820 | * Ignore all characters if CREAD is not set. | |
821 | */ | |
822 | if ((termios->c_cflag & CREAD) == 0) | |
823 | port->ignore_status_mask |= RXSTAT_DUMMY_READ; | |
824 | ||
825 | spin_unlock_irqrestore(&port->lock, flags); | |
826 | } | |
827 | ||
828 | static const char *s3c24xx_serial_type(struct uart_port *port) | |
829 | { | |
830 | switch (port->type) { | |
831 | case PORT_S3C2410: | |
832 | return "S3C2410"; | |
833 | case PORT_S3C2440: | |
834 | return "S3C2440"; | |
835 | case PORT_S3C2412: | |
836 | return "S3C2412"; | |
b690ace5 BD |
837 | case PORT_S3C6400: |
838 | return "S3C6400/10"; | |
b497549a BD |
839 | default: |
840 | return NULL; | |
841 | } | |
842 | } | |
843 | ||
844 | #define MAP_SIZE (0x100) | |
845 | ||
846 | static void s3c24xx_serial_release_port(struct uart_port *port) | |
847 | { | |
848 | release_mem_region(port->mapbase, MAP_SIZE); | |
849 | } | |
850 | ||
851 | static int s3c24xx_serial_request_port(struct uart_port *port) | |
852 | { | |
853 | const char *name = s3c24xx_serial_portname(port); | |
854 | return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY; | |
855 | } | |
856 | ||
857 | static void s3c24xx_serial_config_port(struct uart_port *port, int flags) | |
858 | { | |
859 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
860 | ||
861 | if (flags & UART_CONFIG_TYPE && | |
862 | s3c24xx_serial_request_port(port) == 0) | |
863 | port->type = info->type; | |
864 | } | |
865 | ||
866 | /* | |
867 | * verify the new serial_struct (for TIOCSSERIAL). | |
868 | */ | |
869 | static int | |
870 | s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
871 | { | |
872 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
873 | ||
874 | if (ser->type != PORT_UNKNOWN && ser->type != info->type) | |
875 | return -EINVAL; | |
876 | ||
877 | return 0; | |
878 | } | |
879 | ||
880 | ||
881 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE | |
882 | ||
883 | static struct console s3c24xx_serial_console; | |
884 | ||
93b5c032 JP |
885 | static int __init s3c24xx_serial_console_init(void) |
886 | { | |
887 | register_console(&s3c24xx_serial_console); | |
888 | return 0; | |
889 | } | |
890 | console_initcall(s3c24xx_serial_console_init); | |
891 | ||
b497549a BD |
892 | #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console |
893 | #else | |
894 | #define S3C24XX_SERIAL_CONSOLE NULL | |
895 | #endif | |
896 | ||
93b5c032 JP |
897 | #ifdef CONFIG_CONSOLE_POLL |
898 | static int s3c24xx_serial_get_poll_char(struct uart_port *port); | |
899 | static void s3c24xx_serial_put_poll_char(struct uart_port *port, | |
900 | unsigned char c); | |
901 | #endif | |
902 | ||
b497549a BD |
903 | static struct uart_ops s3c24xx_serial_ops = { |
904 | .pm = s3c24xx_serial_pm, | |
905 | .tx_empty = s3c24xx_serial_tx_empty, | |
906 | .get_mctrl = s3c24xx_serial_get_mctrl, | |
907 | .set_mctrl = s3c24xx_serial_set_mctrl, | |
908 | .stop_tx = s3c24xx_serial_stop_tx, | |
909 | .start_tx = s3c24xx_serial_start_tx, | |
910 | .stop_rx = s3c24xx_serial_stop_rx, | |
911 | .enable_ms = s3c24xx_serial_enable_ms, | |
912 | .break_ctl = s3c24xx_serial_break_ctl, | |
913 | .startup = s3c24xx_serial_startup, | |
914 | .shutdown = s3c24xx_serial_shutdown, | |
915 | .set_termios = s3c24xx_serial_set_termios, | |
916 | .type = s3c24xx_serial_type, | |
917 | .release_port = s3c24xx_serial_release_port, | |
918 | .request_port = s3c24xx_serial_request_port, | |
919 | .config_port = s3c24xx_serial_config_port, | |
920 | .verify_port = s3c24xx_serial_verify_port, | |
93b5c032 JP |
921 | #ifdef CONFIG_CONSOLE_POLL |
922 | .poll_get_char = s3c24xx_serial_get_poll_char, | |
923 | .poll_put_char = s3c24xx_serial_put_poll_char, | |
924 | #endif | |
b497549a BD |
925 | }; |
926 | ||
b497549a BD |
927 | static struct uart_driver s3c24xx_uart_drv = { |
928 | .owner = THIS_MODULE, | |
2cf0c58e | 929 | .driver_name = "s3c2410_serial", |
bdd4915a | 930 | .nr = CONFIG_SERIAL_SAMSUNG_UARTS, |
b497549a | 931 | .cons = S3C24XX_SERIAL_CONSOLE, |
2cf0c58e | 932 | .dev_name = S3C24XX_SERIAL_NAME, |
b497549a BD |
933 | .major = S3C24XX_SERIAL_MAJOR, |
934 | .minor = S3C24XX_SERIAL_MINOR, | |
935 | }; | |
936 | ||
03d5e77b | 937 | static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = { |
b497549a BD |
938 | [0] = { |
939 | .port = { | |
940 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock), | |
941 | .iotype = UPIO_MEM, | |
b497549a BD |
942 | .uartclk = 0, |
943 | .fifosize = 16, | |
944 | .ops = &s3c24xx_serial_ops, | |
945 | .flags = UPF_BOOT_AUTOCONF, | |
946 | .line = 0, | |
947 | } | |
948 | }, | |
949 | [1] = { | |
950 | .port = { | |
951 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock), | |
952 | .iotype = UPIO_MEM, | |
b497549a BD |
953 | .uartclk = 0, |
954 | .fifosize = 16, | |
955 | .ops = &s3c24xx_serial_ops, | |
956 | .flags = UPF_BOOT_AUTOCONF, | |
957 | .line = 1, | |
958 | } | |
959 | }, | |
03d5e77b | 960 | #if CONFIG_SERIAL_SAMSUNG_UARTS > 2 |
b497549a BD |
961 | |
962 | [2] = { | |
963 | .port = { | |
964 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock), | |
965 | .iotype = UPIO_MEM, | |
b497549a BD |
966 | .uartclk = 0, |
967 | .fifosize = 16, | |
968 | .ops = &s3c24xx_serial_ops, | |
969 | .flags = UPF_BOOT_AUTOCONF, | |
970 | .line = 2, | |
971 | } | |
03d5e77b BD |
972 | }, |
973 | #endif | |
974 | #if CONFIG_SERIAL_SAMSUNG_UARTS > 3 | |
975 | [3] = { | |
976 | .port = { | |
977 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock), | |
978 | .iotype = UPIO_MEM, | |
03d5e77b BD |
979 | .uartclk = 0, |
980 | .fifosize = 16, | |
981 | .ops = &s3c24xx_serial_ops, | |
982 | .flags = UPF_BOOT_AUTOCONF, | |
983 | .line = 3, | |
984 | } | |
b497549a BD |
985 | } |
986 | #endif | |
987 | }; | |
988 | ||
989 | /* s3c24xx_serial_resetport | |
990 | * | |
0dfb3b41 | 991 | * reset the fifos and other the settings. |
b497549a BD |
992 | */ |
993 | ||
0dfb3b41 TA |
994 | static void s3c24xx_serial_resetport(struct uart_port *port, |
995 | struct s3c2410_uartcfg *cfg) | |
b497549a BD |
996 | { |
997 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
0dfb3b41 TA |
998 | unsigned long ucon = rd_regl(port, S3C2410_UCON); |
999 | unsigned int ucon_mask; | |
b497549a | 1000 | |
0dfb3b41 TA |
1001 | ucon_mask = info->clksel_mask; |
1002 | if (info->type == PORT_S3C2440) | |
1003 | ucon_mask |= S3C2440_UCON0_DIVMASK; | |
1004 | ||
1005 | ucon &= ucon_mask; | |
1006 | wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); | |
7b246a1d | 1007 | wr_regl(port, S3C2410_ULCON, cfg->ulcon); |
0dfb3b41 TA |
1008 | |
1009 | /* reset both fifos */ | |
1010 | wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); | |
1011 | wr_regl(port, S3C2410_UFCON, cfg->ufcon); | |
1012 | ||
1013 | /* some delay is required after fifo reset */ | |
1014 | udelay(1); | |
b497549a BD |
1015 | } |
1016 | ||
30555476 BD |
1017 | |
1018 | #ifdef CONFIG_CPU_FREQ | |
1019 | ||
1020 | static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb, | |
1021 | unsigned long val, void *data) | |
1022 | { | |
1023 | struct s3c24xx_uart_port *port; | |
1024 | struct uart_port *uport; | |
1025 | ||
1026 | port = container_of(nb, struct s3c24xx_uart_port, freq_transition); | |
1027 | uport = &port->port; | |
1028 | ||
1029 | /* check to see if port is enabled */ | |
1030 | ||
1031 | if (port->pm_level != 0) | |
1032 | return 0; | |
1033 | ||
1034 | /* try and work out if the baudrate is changing, we can detect | |
1035 | * a change in rate, but we do not have support for detecting | |
1036 | * a disturbance in the clock-rate over the change. | |
1037 | */ | |
1038 | ||
25f04ad4 | 1039 | if (IS_ERR(port->baudclk)) |
30555476 BD |
1040 | goto exit; |
1041 | ||
25f04ad4 | 1042 | if (port->baudclk_rate == clk_get_rate(port->baudclk)) |
30555476 BD |
1043 | goto exit; |
1044 | ||
1045 | if (val == CPUFREQ_PRECHANGE) { | |
1046 | /* we should really shut the port down whilst the | |
1047 | * frequency change is in progress. */ | |
1048 | ||
1049 | } else if (val == CPUFREQ_POSTCHANGE) { | |
1050 | struct ktermios *termios; | |
1051 | struct tty_struct *tty; | |
1052 | ||
ebd2c8f6 | 1053 | if (uport->state == NULL) |
30555476 | 1054 | goto exit; |
30555476 | 1055 | |
ebd2c8f6 | 1056 | tty = uport->state->port.tty; |
30555476 | 1057 | |
7de40c21 | 1058 | if (tty == NULL) |
30555476 | 1059 | goto exit; |
30555476 | 1060 | |
adc8d746 | 1061 | termios = &tty->termios; |
30555476 BD |
1062 | |
1063 | if (termios == NULL) { | |
d20925e1 | 1064 | dev_warn(uport->dev, "%s: no termios?\n", __func__); |
30555476 BD |
1065 | goto exit; |
1066 | } | |
1067 | ||
1068 | s3c24xx_serial_set_termios(uport, termios, NULL); | |
1069 | } | |
1070 | ||
1071 | exit: | |
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) | |
1076 | { | |
1077 | port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition; | |
1078 | ||
1079 | return cpufreq_register_notifier(&port->freq_transition, | |
1080 | CPUFREQ_TRANSITION_NOTIFIER); | |
1081 | } | |
1082 | ||
1083 | static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) | |
1084 | { | |
1085 | cpufreq_unregister_notifier(&port->freq_transition, | |
1086 | CPUFREQ_TRANSITION_NOTIFIER); | |
1087 | } | |
1088 | ||
1089 | #else | |
1090 | static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) | |
1091 | { | |
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) | |
1096 | { | |
1097 | } | |
1098 | #endif | |
1099 | ||
b497549a BD |
1100 | /* s3c24xx_serial_init_port |
1101 | * | |
1102 | * initialise a single serial port from the platform device given | |
1103 | */ | |
1104 | ||
1105 | static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, | |
b497549a BD |
1106 | struct platform_device *platdev) |
1107 | { | |
1108 | struct uart_port *port = &ourport->port; | |
da121506 | 1109 | struct s3c2410_uartcfg *cfg = ourport->cfg; |
b497549a BD |
1110 | struct resource *res; |
1111 | int ret; | |
1112 | ||
1113 | dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev); | |
1114 | ||
1115 | if (platdev == NULL) | |
1116 | return -ENODEV; | |
1117 | ||
b497549a BD |
1118 | if (port->mapbase != 0) |
1119 | return 0; | |
1120 | ||
b497549a BD |
1121 | /* setup info for port */ |
1122 | port->dev = &platdev->dev; | |
b497549a | 1123 | |
88bb4ea1 TA |
1124 | /* Startup sequence is different for s3c64xx and higher SoC's */ |
1125 | if (s3c24xx_serial_has_interrupt_mask(port)) | |
1126 | s3c24xx_serial_ops.startup = s3c64xx_serial_startup; | |
1127 | ||
b497549a BD |
1128 | port->uartclk = 1; |
1129 | ||
1130 | if (cfg->uart_flags & UPF_CONS_FLOW) { | |
1131 | dbg("s3c24xx_serial_init_port: enabling flow control\n"); | |
1132 | port->flags |= UPF_CONS_FLOW; | |
1133 | } | |
1134 | ||
1135 | /* sort our the physical and virtual addresses for each UART */ | |
1136 | ||
1137 | res = platform_get_resource(platdev, IORESOURCE_MEM, 0); | |
1138 | if (res == NULL) { | |
d20925e1 | 1139 | dev_err(port->dev, "failed to find memory resource for uart\n"); |
b497549a BD |
1140 | return -EINVAL; |
1141 | } | |
1142 | ||
1143 | dbg("resource %p (%lx..%lx)\n", res, res->start, res->end); | |
1144 | ||
41147bfd TA |
1145 | port->membase = devm_ioremap(port->dev, res->start, resource_size(res)); |
1146 | if (!port->membase) { | |
1147 | dev_err(port->dev, "failed to remap controller address\n"); | |
1148 | return -EBUSY; | |
1149 | } | |
1150 | ||
b690ace5 | 1151 | port->mapbase = res->start; |
b497549a BD |
1152 | ret = platform_get_irq(platdev, 0); |
1153 | if (ret < 0) | |
1154 | port->irq = 0; | |
b73c289c | 1155 | else { |
b497549a | 1156 | port->irq = ret; |
b73c289c BD |
1157 | ourport->rx_irq = ret; |
1158 | ourport->tx_irq = ret + 1; | |
1159 | } | |
9303ac15 | 1160 | |
b73c289c BD |
1161 | ret = platform_get_irq(platdev, 1); |
1162 | if (ret > 0) | |
1163 | ourport->tx_irq = ret; | |
b497549a BD |
1164 | |
1165 | ourport->clk = clk_get(&platdev->dev, "uart"); | |
1166 | ||
88bb4ea1 TA |
1167 | /* Keep all interrupts masked and cleared */ |
1168 | if (s3c24xx_serial_has_interrupt_mask(port)) { | |
1169 | wr_regl(port, S3C64XX_UINTM, 0xf); | |
1170 | wr_regl(port, S3C64XX_UINTP, 0xf); | |
1171 | wr_regl(port, S3C64XX_UINTSP, 0xf); | |
1172 | } | |
1173 | ||
b73c289c BD |
1174 | dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n", |
1175 | port->mapbase, port->membase, port->irq, | |
1176 | ourport->rx_irq, ourport->tx_irq, port->uartclk); | |
b497549a BD |
1177 | |
1178 | /* reset the fifos (and setup the uart) */ | |
1179 | s3c24xx_serial_resetport(port, cfg); | |
1180 | return 0; | |
1181 | } | |
1182 | ||
1183 | static ssize_t s3c24xx_serial_show_clksrc(struct device *dev, | |
1184 | struct device_attribute *attr, | |
1185 | char *buf) | |
1186 | { | |
1187 | struct uart_port *port = s3c24xx_dev_to_port(dev); | |
1188 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
1189 | ||
7cd88831 KK |
1190 | if (IS_ERR(ourport->baudclk)) |
1191 | return -EINVAL; | |
1192 | ||
7b15e1d9 KP |
1193 | return snprintf(buf, PAGE_SIZE, "* %s\n", |
1194 | ourport->baudclk->name ?: "(null)"); | |
b497549a BD |
1195 | } |
1196 | ||
1197 | static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL); | |
1198 | ||
26c919e1 | 1199 | |
b497549a BD |
1200 | /* Device driver serial port probe */ |
1201 | ||
26c919e1 | 1202 | static const struct of_device_id s3c24xx_uart_dt_match[]; |
b497549a BD |
1203 | static int probe_index; |
1204 | ||
26c919e1 TA |
1205 | static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data( |
1206 | struct platform_device *pdev) | |
1207 | { | |
1208 | #ifdef CONFIG_OF | |
1209 | if (pdev->dev.of_node) { | |
1210 | const struct of_device_id *match; | |
1211 | match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node); | |
1212 | return (struct s3c24xx_serial_drv_data *)match->data; | |
1213 | } | |
1214 | #endif | |
1215 | return (struct s3c24xx_serial_drv_data *) | |
1216 | platform_get_device_id(pdev)->driver_data; | |
1217 | } | |
1218 | ||
da121506 | 1219 | static int s3c24xx_serial_probe(struct platform_device *pdev) |
b497549a BD |
1220 | { |
1221 | struct s3c24xx_uart_port *ourport; | |
1222 | int ret; | |
1223 | ||
da121506 | 1224 | dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index); |
b497549a BD |
1225 | |
1226 | ourport = &s3c24xx_serial_ports[probe_index]; | |
da121506 | 1227 | |
26c919e1 TA |
1228 | ourport->drv_data = s3c24xx_get_driver_data(pdev); |
1229 | if (!ourport->drv_data) { | |
1230 | dev_err(&pdev->dev, "could not find driver data\n"); | |
1231 | return -ENODEV; | |
1232 | } | |
da121506 | 1233 | |
7cd88831 | 1234 | ourport->baudclk = ERR_PTR(-EINVAL); |
da121506 TA |
1235 | ourport->info = ourport->drv_data->info; |
1236 | ourport->cfg = (pdev->dev.platform_data) ? | |
1237 | (struct s3c2410_uartcfg *)pdev->dev.platform_data : | |
1238 | ourport->drv_data->def_cfg; | |
1239 | ||
1240 | ourport->port.fifosize = (ourport->info->fifosize) ? | |
1241 | ourport->info->fifosize : | |
1242 | ourport->drv_data->fifosize[probe_index]; | |
1243 | ||
b497549a BD |
1244 | probe_index++; |
1245 | ||
1246 | dbg("%s: initialising port %p...\n", __func__, ourport); | |
1247 | ||
da121506 | 1248 | ret = s3c24xx_serial_init_port(ourport, pdev); |
b497549a BD |
1249 | if (ret < 0) |
1250 | goto probe_err; | |
1251 | ||
1252 | dbg("%s: adding port\n", __func__); | |
1253 | uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); | |
da121506 | 1254 | platform_set_drvdata(pdev, &ourport->port); |
b497549a | 1255 | |
da121506 | 1256 | ret = device_create_file(&pdev->dev, &dev_attr_clock_source); |
b497549a | 1257 | if (ret < 0) |
da121506 | 1258 | dev_err(&pdev->dev, "failed to add clock source attr.\n"); |
b497549a | 1259 | |
30555476 BD |
1260 | ret = s3c24xx_serial_cpufreq_register(ourport); |
1261 | if (ret < 0) | |
da121506 | 1262 | dev_err(&pdev->dev, "failed to add cpufreq notifier\n"); |
30555476 | 1263 | |
b497549a BD |
1264 | return 0; |
1265 | ||
1266 | probe_err: | |
1267 | return ret; | |
1268 | } | |
1269 | ||
ae8d8a14 | 1270 | static int s3c24xx_serial_remove(struct platform_device *dev) |
b497549a BD |
1271 | { |
1272 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); | |
1273 | ||
1274 | if (port) { | |
30555476 | 1275 | s3c24xx_serial_cpufreq_deregister(to_ourport(port)); |
b497549a BD |
1276 | device_remove_file(&dev->dev, &dev_attr_clock_source); |
1277 | uart_remove_one_port(&s3c24xx_uart_drv, port); | |
1278 | } | |
1279 | ||
1280 | return 0; | |
1281 | } | |
1282 | ||
b497549a | 1283 | /* UART power management code */ |
aef7fe52 MH |
1284 | #ifdef CONFIG_PM_SLEEP |
1285 | static int s3c24xx_serial_suspend(struct device *dev) | |
b497549a | 1286 | { |
aef7fe52 | 1287 | struct uart_port *port = s3c24xx_dev_to_port(dev); |
b497549a BD |
1288 | |
1289 | if (port) | |
1290 | uart_suspend_port(&s3c24xx_uart_drv, port); | |
1291 | ||
1292 | return 0; | |
1293 | } | |
1294 | ||
aef7fe52 | 1295 | static int s3c24xx_serial_resume(struct device *dev) |
b497549a | 1296 | { |
aef7fe52 | 1297 | struct uart_port *port = s3c24xx_dev_to_port(dev); |
b497549a BD |
1298 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
1299 | ||
1300 | if (port) { | |
9484b009 | 1301 | clk_prepare_enable(ourport->clk); |
b497549a | 1302 | s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); |
9484b009 | 1303 | clk_disable_unprepare(ourport->clk); |
b497549a BD |
1304 | |
1305 | uart_resume_port(&s3c24xx_uart_drv, port); | |
1306 | } | |
1307 | ||
1308 | return 0; | |
1309 | } | |
aef7fe52 MH |
1310 | |
1311 | static const struct dev_pm_ops s3c24xx_serial_pm_ops = { | |
1312 | .suspend = s3c24xx_serial_suspend, | |
1313 | .resume = s3c24xx_serial_resume, | |
1314 | }; | |
b882fc1b KK |
1315 | #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops) |
1316 | ||
aef7fe52 | 1317 | #else /* !CONFIG_PM_SLEEP */ |
b882fc1b KK |
1318 | |
1319 | #define SERIAL_SAMSUNG_PM_OPS NULL | |
aef7fe52 | 1320 | #endif /* CONFIG_PM_SLEEP */ |
b497549a | 1321 | |
b497549a BD |
1322 | /* Console code */ |
1323 | ||
1324 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE | |
1325 | ||
1326 | static struct uart_port *cons_uart; | |
1327 | ||
1328 | static int | |
1329 | s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon) | |
1330 | { | |
1331 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
1332 | unsigned long ufstat, utrstat; | |
1333 | ||
1334 | if (ufcon & S3C2410_UFCON_FIFOMODE) { | |
9ddc5b6f | 1335 | /* fifo mode - check amount of data in fifo registers... */ |
b497549a BD |
1336 | |
1337 | ufstat = rd_regl(port, S3C2410_UFSTAT); | |
1338 | return (ufstat & info->tx_fifofull) ? 0 : 1; | |
1339 | } | |
1340 | ||
1341 | /* in non-fifo mode, we go and use the tx buffer empty */ | |
1342 | ||
1343 | utrstat = rd_regl(port, S3C2410_UTRSTAT); | |
1344 | return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0; | |
1345 | } | |
1346 | ||
93b5c032 JP |
1347 | #ifdef CONFIG_CONSOLE_POLL |
1348 | /* | |
1349 | * Console polling routines for writing and reading from the uart while | |
1350 | * in an interrupt or debug context. | |
1351 | */ | |
1352 | ||
1353 | static int s3c24xx_serial_get_poll_char(struct uart_port *port) | |
1354 | { | |
1355 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
1356 | unsigned int ufstat; | |
1357 | ||
1358 | ufstat = rd_regl(port, S3C2410_UFSTAT); | |
1359 | if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) | |
1360 | return NO_POLL_CHAR; | |
1361 | ||
1362 | return rd_regb(port, S3C2410_URXH); | |
1363 | } | |
1364 | ||
1365 | static void s3c24xx_serial_put_poll_char(struct uart_port *port, | |
1366 | unsigned char c) | |
1367 | { | |
1368 | unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON); | |
1369 | ||
1370 | while (!s3c24xx_serial_console_txrdy(port, ufcon)) | |
1371 | cpu_relax(); | |
1372 | wr_regb(cons_uart, S3C2410_UTXH, c); | |
1373 | } | |
1374 | ||
1375 | #endif /* CONFIG_CONSOLE_POLL */ | |
1376 | ||
b497549a BD |
1377 | static void |
1378 | s3c24xx_serial_console_putchar(struct uart_port *port, int ch) | |
1379 | { | |
1380 | unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON); | |
1381 | while (!s3c24xx_serial_console_txrdy(port, ufcon)) | |
1382 | barrier(); | |
1383 | wr_regb(cons_uart, S3C2410_UTXH, ch); | |
1384 | } | |
1385 | ||
1386 | static void | |
1387 | s3c24xx_serial_console_write(struct console *co, const char *s, | |
1388 | unsigned int count) | |
1389 | { | |
1390 | uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); | |
1391 | } | |
1392 | ||
1393 | static void __init | |
1394 | s3c24xx_serial_get_options(struct uart_port *port, int *baud, | |
1395 | int *parity, int *bits) | |
1396 | { | |
b497549a BD |
1397 | struct clk *clk; |
1398 | unsigned int ulcon; | |
1399 | unsigned int ucon; | |
1400 | unsigned int ubrdiv; | |
1401 | unsigned long rate; | |
5f5a7a55 TA |
1402 | unsigned int clk_sel; |
1403 | char clk_name[MAX_CLK_NAME_LENGTH]; | |
b497549a BD |
1404 | |
1405 | ulcon = rd_regl(port, S3C2410_ULCON); | |
1406 | ucon = rd_regl(port, S3C2410_UCON); | |
1407 | ubrdiv = rd_regl(port, S3C2410_UBRDIV); | |
1408 | ||
1409 | dbg("s3c24xx_serial_get_options: port=%p\n" | |
1410 | "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n", | |
1411 | port, ulcon, ucon, ubrdiv); | |
1412 | ||
1413 | if ((ucon & 0xf) != 0) { | |
1414 | /* consider the serial port configured if the tx/rx mode set */ | |
1415 | ||
1416 | switch (ulcon & S3C2410_LCON_CSMASK) { | |
1417 | case S3C2410_LCON_CS5: | |
1418 | *bits = 5; | |
1419 | break; | |
1420 | case S3C2410_LCON_CS6: | |
1421 | *bits = 6; | |
1422 | break; | |
1423 | case S3C2410_LCON_CS7: | |
1424 | *bits = 7; | |
1425 | break; | |
1426 | default: | |
1427 | case S3C2410_LCON_CS8: | |
1428 | *bits = 8; | |
1429 | break; | |
1430 | } | |
1431 | ||
1432 | switch (ulcon & S3C2410_LCON_PMASK) { | |
1433 | case S3C2410_LCON_PEVEN: | |
1434 | *parity = 'e'; | |
1435 | break; | |
1436 | ||
1437 | case S3C2410_LCON_PODD: | |
1438 | *parity = 'o'; | |
1439 | break; | |
1440 | ||
1441 | case S3C2410_LCON_PNONE: | |
1442 | default: | |
1443 | *parity = 'n'; | |
1444 | } | |
1445 | ||
1446 | /* now calculate the baud rate */ | |
1447 | ||
5f5a7a55 TA |
1448 | clk_sel = s3c24xx_serial_getsource(port); |
1449 | sprintf(clk_name, "clk_uart_baud%d", clk_sel); | |
b497549a | 1450 | |
5f5a7a55 | 1451 | clk = clk_get(port->dev, clk_name); |
7cd88831 | 1452 | if (!IS_ERR(clk)) |
5f5a7a55 | 1453 | rate = clk_get_rate(clk); |
b497549a BD |
1454 | else |
1455 | rate = 1; | |
1456 | ||
b497549a BD |
1457 | *baud = rate / (16 * (ubrdiv + 1)); |
1458 | dbg("calculated baud %d\n", *baud); | |
1459 | } | |
1460 | ||
1461 | } | |
1462 | ||
b497549a BD |
1463 | static int __init |
1464 | s3c24xx_serial_console_setup(struct console *co, char *options) | |
1465 | { | |
1466 | struct uart_port *port; | |
1467 | int baud = 9600; | |
1468 | int bits = 8; | |
1469 | int parity = 'n'; | |
1470 | int flow = 'n'; | |
1471 | ||
1472 | dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n", | |
1473 | co, co->index, options); | |
1474 | ||
1475 | /* is this a valid port */ | |
1476 | ||
03d5e77b | 1477 | if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS) |
b497549a BD |
1478 | co->index = 0; |
1479 | ||
1480 | port = &s3c24xx_serial_ports[co->index].port; | |
1481 | ||
1482 | /* is the port configured? */ | |
1483 | ||
ee430f16 TA |
1484 | if (port->mapbase == 0x0) |
1485 | return -ENODEV; | |
b497549a BD |
1486 | |
1487 | cons_uart = port; | |
1488 | ||
1489 | dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index); | |
1490 | ||
1491 | /* | |
1492 | * Check whether an invalid uart number has been specified, and | |
1493 | * if so, search for the first available port that does have | |
1494 | * console support. | |
1495 | */ | |
1496 | if (options) | |
1497 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1498 | else | |
1499 | s3c24xx_serial_get_options(port, &baud, &parity, &bits); | |
1500 | ||
1501 | dbg("s3c24xx_serial_console_setup: baud %d\n", baud); | |
1502 | ||
1503 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1504 | } | |
1505 | ||
b497549a BD |
1506 | static struct console s3c24xx_serial_console = { |
1507 | .name = S3C24XX_SERIAL_NAME, | |
1508 | .device = uart_console_device, | |
1509 | .flags = CON_PRINTBUFFER, | |
1510 | .index = -1, | |
1511 | .write = s3c24xx_serial_console_write, | |
5822a5df TA |
1512 | .setup = s3c24xx_serial_console_setup, |
1513 | .data = &s3c24xx_uart_drv, | |
b497549a | 1514 | }; |
da121506 TA |
1515 | #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ |
1516 | ||
1517 | #ifdef CONFIG_CPU_S3C2410 | |
1518 | static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = { | |
1519 | .info = &(struct s3c24xx_uart_info) { | |
1520 | .name = "Samsung S3C2410 UART", | |
1521 | .type = PORT_S3C2410, | |
1522 | .fifosize = 16, | |
1523 | .rx_fifomask = S3C2410_UFSTAT_RXMASK, | |
1524 | .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, | |
1525 | .rx_fifofull = S3C2410_UFSTAT_RXFULL, | |
1526 | .tx_fifofull = S3C2410_UFSTAT_TXFULL, | |
1527 | .tx_fifomask = S3C2410_UFSTAT_TXMASK, | |
1528 | .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, | |
1529 | .def_clk_sel = S3C2410_UCON_CLKSEL0, | |
1530 | .num_clks = 2, | |
1531 | .clksel_mask = S3C2410_UCON_CLKMASK, | |
1532 | .clksel_shift = S3C2410_UCON_CLKSHIFT, | |
1533 | }, | |
1534 | .def_cfg = &(struct s3c2410_uartcfg) { | |
1535 | .ucon = S3C2410_UCON_DEFAULT, | |
1536 | .ufcon = S3C2410_UFCON_DEFAULT, | |
1537 | }, | |
1538 | }; | |
1539 | #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data) | |
1540 | #else | |
1541 | #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
1542 | #endif | |
b497549a | 1543 | |
da121506 TA |
1544 | #ifdef CONFIG_CPU_S3C2412 |
1545 | static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = { | |
1546 | .info = &(struct s3c24xx_uart_info) { | |
1547 | .name = "Samsung S3C2412 UART", | |
1548 | .type = PORT_S3C2412, | |
1549 | .fifosize = 64, | |
1550 | .has_divslot = 1, | |
1551 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | |
1552 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | |
1553 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | |
1554 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | |
1555 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | |
1556 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | |
1557 | .def_clk_sel = S3C2410_UCON_CLKSEL2, | |
1558 | .num_clks = 4, | |
1559 | .clksel_mask = S3C2412_UCON_CLKMASK, | |
1560 | .clksel_shift = S3C2412_UCON_CLKSHIFT, | |
1561 | }, | |
1562 | .def_cfg = &(struct s3c2410_uartcfg) { | |
1563 | .ucon = S3C2410_UCON_DEFAULT, | |
1564 | .ufcon = S3C2410_UFCON_DEFAULT, | |
1565 | }, | |
1566 | }; | |
1567 | #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data) | |
1568 | #else | |
1569 | #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
1570 | #endif | |
b497549a | 1571 | |
da121506 | 1572 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \ |
b26469a8 | 1573 | defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442) |
da121506 TA |
1574 | static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = { |
1575 | .info = &(struct s3c24xx_uart_info) { | |
1576 | .name = "Samsung S3C2440 UART", | |
1577 | .type = PORT_S3C2440, | |
1578 | .fifosize = 64, | |
1579 | .has_divslot = 1, | |
1580 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | |
1581 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | |
1582 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | |
1583 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | |
1584 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | |
1585 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | |
1586 | .def_clk_sel = S3C2410_UCON_CLKSEL2, | |
1587 | .num_clks = 4, | |
1588 | .clksel_mask = S3C2412_UCON_CLKMASK, | |
1589 | .clksel_shift = S3C2412_UCON_CLKSHIFT, | |
1590 | }, | |
1591 | .def_cfg = &(struct s3c2410_uartcfg) { | |
1592 | .ucon = S3C2410_UCON_DEFAULT, | |
1593 | .ufcon = S3C2410_UFCON_DEFAULT, | |
1594 | }, | |
1595 | }; | |
1596 | #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data) | |
1597 | #else | |
1598 | #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
1599 | #endif | |
b497549a | 1600 | |
da121506 TA |
1601 | #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \ |
1602 | defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \ | |
1603 | defined(CONFIG_CPU_S5PC100) | |
1604 | static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { | |
1605 | .info = &(struct s3c24xx_uart_info) { | |
1606 | .name = "Samsung S3C6400 UART", | |
1607 | .type = PORT_S3C6400, | |
1608 | .fifosize = 64, | |
1609 | .has_divslot = 1, | |
1610 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | |
1611 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | |
1612 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | |
1613 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | |
1614 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | |
1615 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | |
1616 | .def_clk_sel = S3C2410_UCON_CLKSEL2, | |
1617 | .num_clks = 4, | |
1618 | .clksel_mask = S3C6400_UCON_CLKMASK, | |
1619 | .clksel_shift = S3C6400_UCON_CLKSHIFT, | |
1620 | }, | |
1621 | .def_cfg = &(struct s3c2410_uartcfg) { | |
1622 | .ucon = S3C2410_UCON_DEFAULT, | |
1623 | .ufcon = S3C2410_UFCON_DEFAULT, | |
1624 | }, | |
1625 | }; | |
1626 | #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data) | |
1627 | #else | |
1628 | #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
1629 | #endif | |
b497549a | 1630 | |
da121506 TA |
1631 | #ifdef CONFIG_CPU_S5PV210 |
1632 | static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { | |
1633 | .info = &(struct s3c24xx_uart_info) { | |
1634 | .name = "Samsung S5PV210 UART", | |
1635 | .type = PORT_S3C6400, | |
1636 | .has_divslot = 1, | |
1637 | .rx_fifomask = S5PV210_UFSTAT_RXMASK, | |
1638 | .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, | |
1639 | .rx_fifofull = S5PV210_UFSTAT_RXFULL, | |
1640 | .tx_fifofull = S5PV210_UFSTAT_TXFULL, | |
1641 | .tx_fifomask = S5PV210_UFSTAT_TXMASK, | |
1642 | .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, | |
1643 | .def_clk_sel = S3C2410_UCON_CLKSEL0, | |
1644 | .num_clks = 2, | |
1645 | .clksel_mask = S5PV210_UCON_CLKMASK, | |
1646 | .clksel_shift = S5PV210_UCON_CLKSHIFT, | |
1647 | }, | |
1648 | .def_cfg = &(struct s3c2410_uartcfg) { | |
1649 | .ucon = S5PV210_UCON_DEFAULT, | |
1650 | .ufcon = S5PV210_UFCON_DEFAULT, | |
1651 | }, | |
1652 | .fifosize = { 256, 64, 16, 16 }, | |
1653 | }; | |
1654 | #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data) | |
1655 | #else | |
1656 | #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
1657 | #endif | |
b497549a | 1658 | |
5f7b6d19 | 1659 | #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \ |
2edb36c4 KK |
1660 | defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \ |
1661 | defined(CONFIG_SOC_EXYNOS5440) | |
da121506 TA |
1662 | static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { |
1663 | .info = &(struct s3c24xx_uart_info) { | |
1664 | .name = "Samsung Exynos4 UART", | |
1665 | .type = PORT_S3C6400, | |
1666 | .has_divslot = 1, | |
1667 | .rx_fifomask = S5PV210_UFSTAT_RXMASK, | |
1668 | .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, | |
1669 | .rx_fifofull = S5PV210_UFSTAT_RXFULL, | |
1670 | .tx_fifofull = S5PV210_UFSTAT_TXFULL, | |
1671 | .tx_fifomask = S5PV210_UFSTAT_TXMASK, | |
1672 | .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, | |
1673 | .def_clk_sel = S3C2410_UCON_CLKSEL0, | |
1674 | .num_clks = 1, | |
1675 | .clksel_mask = 0, | |
1676 | .clksel_shift = 0, | |
1677 | }, | |
1678 | .def_cfg = &(struct s3c2410_uartcfg) { | |
1679 | .ucon = S5PV210_UCON_DEFAULT, | |
1680 | .ufcon = S5PV210_UFCON_DEFAULT, | |
1681 | .has_fracval = 1, | |
1682 | }, | |
1683 | .fifosize = { 256, 64, 16, 16 }, | |
1684 | }; | |
1685 | #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) | |
1686 | #else | |
1687 | #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
1688 | #endif | |
b497549a | 1689 | |
da121506 TA |
1690 | static struct platform_device_id s3c24xx_serial_driver_ids[] = { |
1691 | { | |
1692 | .name = "s3c2410-uart", | |
1693 | .driver_data = S3C2410_SERIAL_DRV_DATA, | |
1694 | }, { | |
1695 | .name = "s3c2412-uart", | |
1696 | .driver_data = S3C2412_SERIAL_DRV_DATA, | |
1697 | }, { | |
1698 | .name = "s3c2440-uart", | |
1699 | .driver_data = S3C2440_SERIAL_DRV_DATA, | |
1700 | }, { | |
1701 | .name = "s3c6400-uart", | |
1702 | .driver_data = S3C6400_SERIAL_DRV_DATA, | |
1703 | }, { | |
1704 | .name = "s5pv210-uart", | |
1705 | .driver_data = S5PV210_SERIAL_DRV_DATA, | |
1706 | }, { | |
1707 | .name = "exynos4210-uart", | |
1708 | .driver_data = EXYNOS4210_SERIAL_DRV_DATA, | |
1709 | }, | |
1710 | { }, | |
1711 | }; | |
1712 | MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids); | |
1713 | ||
26c919e1 TA |
1714 | #ifdef CONFIG_OF |
1715 | static const struct of_device_id s3c24xx_uart_dt_match[] = { | |
666ca0b9 HS |
1716 | { .compatible = "samsung,s3c2410-uart", |
1717 | .data = (void *)S3C2410_SERIAL_DRV_DATA }, | |
1718 | { .compatible = "samsung,s3c2412-uart", | |
1719 | .data = (void *)S3C2412_SERIAL_DRV_DATA }, | |
1720 | { .compatible = "samsung,s3c2440-uart", | |
1721 | .data = (void *)S3C2440_SERIAL_DRV_DATA }, | |
1722 | { .compatible = "samsung,s3c6400-uart", | |
1723 | .data = (void *)S3C6400_SERIAL_DRV_DATA }, | |
1724 | { .compatible = "samsung,s5pv210-uart", | |
1725 | .data = (void *)S5PV210_SERIAL_DRV_DATA }, | |
26c919e1 | 1726 | { .compatible = "samsung,exynos4210-uart", |
a169a888 | 1727 | .data = (void *)EXYNOS4210_SERIAL_DRV_DATA }, |
26c919e1 TA |
1728 | {}, |
1729 | }; | |
1730 | MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); | |
26c919e1 TA |
1731 | #endif |
1732 | ||
da121506 TA |
1733 | static struct platform_driver samsung_serial_driver = { |
1734 | .probe = s3c24xx_serial_probe, | |
2d47b716 | 1735 | .remove = s3c24xx_serial_remove, |
da121506 TA |
1736 | .id_table = s3c24xx_serial_driver_ids, |
1737 | .driver = { | |
1738 | .name = "samsung-uart", | |
1739 | .owner = THIS_MODULE, | |
1740 | .pm = SERIAL_SAMSUNG_PM_OPS, | |
905f4ba2 | 1741 | .of_match_table = of_match_ptr(s3c24xx_uart_dt_match), |
da121506 TA |
1742 | }, |
1743 | }; | |
b497549a | 1744 | |
da121506 | 1745 | /* module initialisation code */ |
b497549a | 1746 | |
da121506 TA |
1747 | static int __init s3c24xx_serial_modinit(void) |
1748 | { | |
1749 | int ret; | |
1750 | ||
1751 | ret = uart_register_driver(&s3c24xx_uart_drv); | |
1752 | if (ret < 0) { | |
d20925e1 | 1753 | pr_err("Failed to register Samsung UART driver\n"); |
e740d8f1 | 1754 | return ret; |
da121506 TA |
1755 | } |
1756 | ||
1757 | return platform_driver_register(&samsung_serial_driver); | |
b497549a BD |
1758 | } |
1759 | ||
da121506 TA |
1760 | static void __exit s3c24xx_serial_modexit(void) |
1761 | { | |
1762 | uart_unregister_driver(&s3c24xx_uart_drv); | |
1763 | } | |
1764 | ||
1765 | module_init(s3c24xx_serial_modinit); | |
1766 | module_exit(s3c24xx_serial_modexit); | |
b497549a | 1767 | |
da121506 | 1768 | MODULE_ALIAS("platform:samsung-uart"); |
b497549a BD |
1769 | MODULE_DESCRIPTION("Samsung SoC Serial port driver"); |
1770 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
1771 | MODULE_LICENSE("GPL v2"); |