[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / samsung.h

// SPDX-License-Identifier: GPL-2.0
#ifndef __SAMSUNG_H
#define __SAMSUNG_H

/*
 * Driver for Samsung SoC onboard UARTs.
 *
 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/dmaengine.h>

struct s3c24xx_uart_info {
	char			*name;
	unsigned int		type;
	unsigned int		fifosize;
	unsigned long		rx_fifomask;
	unsigned long		rx_fifoshift;
	unsigned long		rx_fifofull;
	unsigned long		tx_fifomask;
	unsigned long		tx_fifoshift;
	unsigned long		tx_fifofull;
	unsigned int		def_clk_sel;
	unsigned long		num_clks;
	unsigned long		clksel_mask;
	unsigned long		clksel_shift;

	/* uart port features */

	unsigned int		has_divslot:1;

	/* uart controls */
	int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
};

struct s3c24xx_serial_drv_data {
	struct s3c24xx_uart_info	*info;
	struct s3c2410_uartcfg		*def_cfg;
	unsigned int			fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
};

struct s3c24xx_uart_dma {
	unsigned int			rx_chan_id;
	unsigned int			tx_chan_id;

	struct dma_slave_config		rx_conf;
	struct dma_slave_config		tx_conf;

	struct dma_chan			*rx_chan;
	struct dma_chan			*tx_chan;

	dma_addr_t			rx_addr;
	dma_addr_t			tx_addr;

	dma_cookie_t			rx_cookie;
	dma_cookie_t			tx_cookie;

	char				*rx_buf;

	dma_addr_t			tx_transfer_addr;

	size_t				rx_size;
	size_t				tx_size;

	struct dma_async_tx_descriptor	*tx_desc;
	struct dma_async_tx_descriptor	*rx_desc;

	int				tx_bytes_requested;
	int				rx_bytes_requested;
};

struct s3c24xx_uart_port {
	unsigned char			rx_claimed;
	unsigned char			tx_claimed;
	unsigned int			pm_level;
	unsigned long			baudclk_rate;
	unsigned int			min_dma_size;

	unsigned int			rx_irq;
	unsigned int			tx_irq;

	unsigned int			tx_in_progress;
	unsigned int			tx_mode;
	unsigned int			rx_mode;

	struct s3c24xx_uart_info	*info;
	struct clk			*clk;
	struct clk			*baudclk;
	struct uart_port		port;
	struct s3c24xx_serial_drv_data	*drv_data;

	/* reference to platform data */
	struct s3c2410_uartcfg		*cfg;

	struct s3c24xx_uart_dma		*dma;

#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
	struct notifier_block		freq_transition;
#endif
};

/* conversion functions */

#define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)

/* register access controls */

#define portaddr(port, reg) ((port)->membase + (reg))
#define portaddrl(port, reg) \
	((unsigned long *)(unsigned long)((port)->membase + (reg)))

#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg)))
#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))

#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))

/* Byte-order aware bit setting/clearing functions. */

static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
				   unsigned int reg)
{
	unsigned long flags;
	u32 val;

	local_irq_save(flags);
	val = rd_regl(port, reg);
	val |= (1 << idx);
	wr_regl(port, reg, val);
	local_irq_restore(flags);
}

static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
				     unsigned int reg)
{
	unsigned long flags;
	u32 val;

	local_irq_save(flags);
	val = rd_regl(port, reg);
	val &= ~(1 << idx);
	wr_regl(port, reg, val);
	local_irq_restore(flags);
}

#endif
Commit	Line	Data
e3b3d0f5	1	// SPDX-License-Identifier: GPL-2.0
e4ac92df JP	2	#ifndef __SAMSUNG_H
	3	#define __SAMSUNG_H
	4
99edb3d1	5	/*
b497549a BD	6	* Driver for Samsung SoC onboard UARTs.
b497549a BD	7	*
ccae941e	8	* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a BD	9	* http://armlinux.simtec.co.uk/
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
7bb6b2f6 RB	16	#include <linux/dmaengine.h>
7bb6b2f6 RB	17
b497549a BD	18	struct s3c24xx_uart_info {
	19	char *name;
	20	unsigned int type;
	21	unsigned int fifosize;
	22	unsigned long rx_fifomask;
	23	unsigned long rx_fifoshift;
	24	unsigned long rx_fifofull;
	25	unsigned long tx_fifomask;
	26	unsigned long tx_fifoshift;
	27	unsigned long tx_fifofull;
5f5a7a55 TA	28	unsigned int def_clk_sel;
	29	unsigned long num_clks;
	30	unsigned long clksel_mask;
	31	unsigned long clksel_shift;
b497549a	32
090f848d BD	33	/* uart port features */
	34
	35	unsigned int has_divslot:1;
	36
b497549a BD	37	/* uart controls */
	38	int (reset_port)(struct uart_port , struct s3c2410_uartcfg *);
	39	};
	40
da121506 TA	41	struct s3c24xx_serial_drv_data {
	42	struct s3c24xx_uart_info *info;
	43	struct s3c2410_uartcfg *def_cfg;
	44	unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
	45	};
	46
7bb6b2f6	47	struct s3c24xx_uart_dma {
7bb6b2f6 RB	48	unsigned int rx_chan_id;
	49	unsigned int tx_chan_id;
	50
	51	struct dma_slave_config rx_conf;
	52	struct dma_slave_config tx_conf;
	53
	54	struct dma_chan *rx_chan;
	55	struct dma_chan *tx_chan;
	56
	57	dma_addr_t rx_addr;
	58	dma_addr_t tx_addr;
	59
	60	dma_cookie_t rx_cookie;
	61	dma_cookie_t tx_cookie;
	62
	63	char *rx_buf;
	64
	65	dma_addr_t tx_transfer_addr;
	66
	67	size_t rx_size;
	68	size_t tx_size;
	69
	70	struct dma_async_tx_descriptor *tx_desc;
	71	struct dma_async_tx_descriptor *rx_desc;
	72
	73	int tx_bytes_requested;
	74	int rx_bytes_requested;
	75	};
	76
b497549a BD	77	struct s3c24xx_uart_port {
	78	unsigned char rx_claimed;
	79	unsigned char tx_claimed;
30555476 BD	80	unsigned int pm_level;
30555476 BD	81	unsigned long baudclk_rate;
81ccb2a6	82	unsigned int min_dma_size;
b497549a	83
b73c289c BD	84	unsigned int rx_irq;
	85	unsigned int tx_irq;
	86
29bef799 RB	87	unsigned int tx_in_progress;
29bef799 RB	88	unsigned int tx_mode;
b543c301	89	unsigned int rx_mode;
29bef799	90
b497549a	91	struct s3c24xx_uart_info *info;
b497549a BD	92	struct clk *clk;
	93	struct clk *baudclk;
	94	struct uart_port port;
da121506	95	struct s3c24xx_serial_drv_data *drv_data;
30555476	96
4d84e970 TA	97	/* reference to platform data */
	98	struct s3c2410_uartcfg *cfg;
	99
7bb6b2f6 RB	100	struct s3c24xx_uart_dma *dma;
7bb6b2f6 RB	101
ebaa81c7	102	#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
30555476 BD	103	struct notifier_block freq_transition;
30555476 BD	104	#endif
b497549a BD	105	};
	106
	107	/* conversion functions */
	108
d4aab206	109	#define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
b497549a BD	110
	111	/* register access controls */
	112
	113	#define portaddr(port, reg) ((port)->membase + (reg))
9fdedf5d JH	114	#define portaddrl(port, reg) \
9fdedf5d JH	115	((unsigned long *)(unsigned long)((port)->membase + (reg)))
b497549a	116
e37697b3 ML	117	#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg)))
e37697b3 ML	118	#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
b497549a	119
e37697b3 ML	120	#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
e37697b3 ML	121	#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
b497549a	122
bbb5ff91 ML	123	/* Byte-order aware bit setting/clearing functions. */
	124
	125	static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
	126	unsigned int reg)
	127	{
	128	unsigned long flags;
	129	u32 val;
	130
	131	local_irq_save(flags);
	132	val = rd_regl(port, reg);
	133	val \|= (1 << idx);
	134	wr_regl(port, reg, val);
	135	local_irq_restore(flags);
	136	}
	137
	138	static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
	139	unsigned int reg)
	140	{
	141	unsigned long flags;
	142	u32 val;
	143
	144	local_irq_save(flags);
	145	val = rd_regl(port, reg);
	146	val &= ~(1 << idx);
	147	wr_regl(port, reg, val);
	148	local_irq_restore(flags);
	149	}
	150
b497549a	151	#endif