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e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
b45d5279 2/*
b45d5279
MR		 3 * Support for the asynchronous serial interface (DUART) included
4 * in the BCM1250 and derived System-On-a-Chip (SOC) devices.
5 *
6 * Copyright (c) 2007 Maciej W. Rozycki
7 *
8 * Derived from drivers/char/sb1250_duart.c for which the following
9 * copyright applies:
10 *
11 * Copyright (c) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation
12 *
b45d5279
MR		 13 * References:
14 *
15 * "BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation
16 */
17
18#if defined(CONFIG_SERIAL_SB1250_DUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
21
86d0004a 22#include <linux/compiler.h>
b45d5279
MR		 23#include <linux/console.h>
24#include <linux/delay.h>
25#include <linux/errno.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29#include <linux/kernel.h>
346f81a9 30#include <linux/module.h>
b45d5279
MR		 31#include <linux/major.h>
32#include <linux/serial.h>
33#include <linux/serial_core.h>
34#include <linux/spinlock.h>
35#include <linux/sysrq.h>
36#include <linux/tty.h>
ee160a38 37#include <linux/tty_flip.h>
b45d5279
MR		 38#include <linux/types.h>
39
22a33651 40#include <linux/refcount.h>
b45d5279
MR		 41#include <asm/io.h>
42#include <asm/war.h>
43
44#include <asm/sibyte/sb1250.h>
45#include <asm/sibyte/sb1250_uart.h>
46#include <asm/sibyte/swarm.h>
47
48
49#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
50#include <asm/sibyte/bcm1480_regs.h>
51#include <asm/sibyte/bcm1480_int.h>
52
53#define SBD_CHANREGS(line) A_BCM1480_DUART_CHANREG((line), 0)
54#define SBD_CTRLREGS(line) A_BCM1480_DUART_CTRLREG((line), 0)
55#define SBD_INT(line) (K_BCM1480_INT_UART_0 + (line))
56
719b6f29
TS		 57#define DUART_CHANREG_SPACING BCM1480_DUART_CHANREG_SPACING
58
59#define R_DUART_IMRREG(line) R_BCM1480_DUART_IMRREG(line)
60#define R_DUART_INCHREG(line) R_BCM1480_DUART_INCHREG(line)
61#define R_DUART_ISRREG(line) R_BCM1480_DUART_ISRREG(line)
62
b45d5279
MR		 63#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
64#include <asm/sibyte/sb1250_regs.h>
65#include <asm/sibyte/sb1250_int.h>
66
67#define SBD_CHANREGS(line) A_DUART_CHANREG((line), 0)
68#define SBD_CTRLREGS(line) A_DUART_CTRLREG(0)
69#define SBD_INT(line) (K_INT_UART_0 + (line))
70
71#else
72#error invalid SB1250 UART configuration
73
74#endif
75
76
77MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
78MODULE_DESCRIPTION("BCM1xxx on-chip DUART serial driver");
79MODULE_LICENSE("GPL");
80
81
82#define DUART_MAX_CHIP 2
83#define DUART_MAX_SIDE 2
84
85/*
86 * Per-port state.
87 */
88struct sbd_port {
89 struct sbd_duart *duart;
90 struct uart_port port;
91 unsigned char __iomem *memctrl;
92 int tx_stopped;
93 int initialised;
94};
95
96/*
97 * Per-DUART state for the shared register space.
98 */
99struct sbd_duart {
100 struct sbd_port sport[2];
101 unsigned long mapctrl;
22a33651 102 refcount_t map_guard;
b45d5279
MR		 103};
104
105#define to_sport(uport) container_of(uport, struct sbd_port, port)
106
107static struct sbd_duart sbd_duarts[DUART_MAX_CHIP];
108
b45d5279
MR		 109
110/*
111 * Reading and writing SB1250 DUART registers.
112 *
113 * There are three register spaces: two per-channel ones and
114 * a shared one. We have to define accessors appropriately.
115 * All registers are 64-bit and all but the Baud Rate Clock
116 * registers only define 8 least significant bits. There is
117 * also a workaround to take into account. Raw accessors use
118 * the full register width, but cooked ones truncate it
119 * intentionally so that the rest of the driver does not care.
120 */
121static u64 __read_sbdchn(struct sbd_port *sport, int reg)
122{
123 void __iomem *csr = sport->port.membase + reg;
124
125 return __raw_readq(csr);
126}
127
128static u64 __read_sbdshr(struct sbd_port *sport, int reg)
129{
130 void __iomem *csr = sport->memctrl + reg;
131
132 return __raw_readq(csr);
133}
134
135static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value)
136{
137 void __iomem *csr = sport->port.membase + reg;
138
139 __raw_writeq(value, csr);
140}
141
142static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value)
143{
144 void __iomem *csr = sport->memctrl + reg;
145
146 __raw_writeq(value, csr);
147}
148
149/*
150 * In bug 1956, we get glitches that can mess up uart registers. This
151 * "read-mode-reg after any register access" is an accepted workaround.
152 */
153static void __war_sbd1956(struct sbd_port *sport)
154{
155 __read_sbdchn(sport, R_DUART_MODE_REG_1);
156 __read_sbdchn(sport, R_DUART_MODE_REG_2);
157}
158
159static unsigned char read_sbdchn(struct sbd_port *sport, int reg)
160{
161 unsigned char retval;
162
163 retval = __read_sbdchn(sport, reg);
164 if (SIBYTE_1956_WAR)
165 __war_sbd1956(sport);
166 return retval;
167}
168
169static unsigned char read_sbdshr(struct sbd_port *sport, int reg)
170{
171 unsigned char retval;
172
173 retval = __read_sbdshr(sport, reg);
174 if (SIBYTE_1956_WAR)
175 __war_sbd1956(sport);
176 return retval;
177}
178
179static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value)
180{
181 __write_sbdchn(sport, reg, value);
182 if (SIBYTE_1956_WAR)
183 __war_sbd1956(sport);
184}
185
186static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value)
187{
188 __write_sbdshr(sport, reg, value);
189 if (SIBYTE_1956_WAR)
190 __war_sbd1956(sport);
191}
192
193
194static int sbd_receive_ready(struct sbd_port *sport)
195{
196 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_RX_RDY;
197}
198
199static int sbd_receive_drain(struct sbd_port *sport)
200{
201 int loops = 10000;
202
52e3632e 203 while (sbd_receive_ready(sport) && --loops)
b45d5279
MR		 204 read_sbdchn(sport, R_DUART_RX_HOLD);
205 return loops;
206}
207
86d0004a 208static int __maybe_unused sbd_transmit_ready(struct sbd_port *sport)
b45d5279
MR		 209{
210 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_RDY;
211}
212
86d0004a 213static int __maybe_unused sbd_transmit_drain(struct sbd_port *sport)
b45d5279
MR		 214{
215 int loops = 10000;
216
52e3632e 217 while (!sbd_transmit_ready(sport) && --loops)
b45d5279
MR		 218 udelay(2);
219 return loops;
220}
221
222static int sbd_transmit_empty(struct sbd_port *sport)
223{
224 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_EMT;
225}
226
227static int sbd_line_drain(struct sbd_port *sport)
228{
229 int loops = 10000;
230
52e3632e 231 while (!sbd_transmit_empty(sport) && --loops)
b45d5279
MR		 232 udelay(2);
233 return loops;
234}
235
236
237static unsigned int sbd_tx_empty(struct uart_port *uport)
238{
239 struct sbd_port *sport = to_sport(uport);
240
241 return sbd_transmit_empty(sport) ? TIOCSER_TEMT : 0;
242}
243
244static unsigned int sbd_get_mctrl(struct uart_port *uport)
245{
246 struct sbd_port *sport = to_sport(uport);
247 unsigned int mctrl, status;
248
249 status = read_sbdshr(sport, R_DUART_IN_PORT);
250 status >>= (uport->line) % 2;
251 mctrl = (!(status & M_DUART_IN_PIN0_VAL) ? TIOCM_CTS : 0) |
252 (!(status & M_DUART_IN_PIN4_VAL) ? TIOCM_CAR : 0) |
253 (!(status & M_DUART_RIN0_PIN) ? TIOCM_RNG : 0) |
254 (!(status & M_DUART_IN_PIN2_VAL) ? TIOCM_DSR : 0);
255 return mctrl;
256}
257
258static void sbd_set_mctrl(struct uart_port *uport, unsigned int mctrl)
259{
260 struct sbd_port *sport = to_sport(uport);
261 unsigned int clr = 0, set = 0, mode2;
262
263 if (mctrl & TIOCM_DTR)
264 set |= M_DUART_SET_OPR2;
265 else
266 clr |= M_DUART_CLR_OPR2;
267 if (mctrl & TIOCM_RTS)
268 set |= M_DUART_SET_OPR0;
269 else
270 clr |= M_DUART_CLR_OPR0;
271 clr <<= (uport->line) % 2;
272 set <<= (uport->line) % 2;
273
274 mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2);
275 mode2 &= ~M_DUART_CHAN_MODE;
276 if (mctrl & TIOCM_LOOP)
277 mode2 |= V_DUART_CHAN_MODE_LCL_LOOP;
278 else
279 mode2 |= V_DUART_CHAN_MODE_NORMAL;
280
281 write_sbdshr(sport, R_DUART_CLEAR_OPR, clr);
282 write_sbdshr(sport, R_DUART_SET_OPR, set);
283 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2);
284}
285
286static void sbd_stop_tx(struct uart_port *uport)
287{
288 struct sbd_port *sport = to_sport(uport);
289
290 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
291 sport->tx_stopped = 1;
292};
293
294static void sbd_start_tx(struct uart_port *uport)
295{
296 struct sbd_port *sport = to_sport(uport);
297 unsigned int mask;
298
299 /* Enable tx interrupts. */
300 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
301 mask |= M_DUART_IMR_TX;
302 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
303
304 /* Go!, go!, go!... */
305 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
306 sport->tx_stopped = 0;
307};
308
309static void sbd_stop_rx(struct uart_port *uport)
310{
311 struct sbd_port *sport = to_sport(uport);
312
313 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
314};
315
316static void sbd_enable_ms(struct uart_port *uport)
317{
318 struct sbd_port *sport = to_sport(uport);
319
320 write_sbdchn(sport, R_DUART_AUXCTL_X,
321 M_DUART_CIN_CHNG_ENA | M_DUART_CTS_CHNG_ENA);
322}
323
324static void sbd_break_ctl(struct uart_port *uport, int break_state)
325{
326 struct sbd_port *sport = to_sport(uport);
327
328 if (break_state == -1)
329 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_START_BREAK);
330 else
331 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_STOP_BREAK);
332}
333
334
335static void sbd_receive_chars(struct sbd_port *sport)
336{
337 struct uart_port *uport = &sport->port;
338 struct uart_icount *icount;
339 unsigned int status, ch, flag;
340 int count;
341
342 for (count = 16; count; count--) {
343 status = read_sbdchn(sport, R_DUART_STATUS);
344 if (!(status & M_DUART_RX_RDY))
345 break;
346
347 ch = read_sbdchn(sport, R_DUART_RX_HOLD);
348
349 flag = TTY_NORMAL;
350
351 icount = &uport->icount;
352 icount->rx++;
353
354 if (unlikely(status &
355 (M_DUART_RCVD_BRK | M_DUART_FRM_ERR |
356 M_DUART_PARITY_ERR | M_DUART_OVRUN_ERR))) {
357 if (status & M_DUART_RCVD_BRK) {
358 icount->brk++;
359 if (uart_handle_break(uport))
360 continue;
361 } else if (status & M_DUART_FRM_ERR)
362 icount->frame++;
363 else if (status & M_DUART_PARITY_ERR)
364 icount->parity++;
365 if (status & M_DUART_OVRUN_ERR)
366 icount->overrun++;
367
368 status &= uport->read_status_mask;
369 if (status & M_DUART_RCVD_BRK)
370 flag = TTY_BREAK;
371 else if (status & M_DUART_FRM_ERR)
372 flag = TTY_FRAME;
373 else if (status & M_DUART_PARITY_ERR)
374 flag = TTY_PARITY;
375 }
376
377 if (uart_handle_sysrq_char(uport, ch))
378 continue;
379
380 uart_insert_char(uport, status, M_DUART_OVRUN_ERR, ch, flag);
381 }
382
2e124b4a 383 tty_flip_buffer_push(&uport->state->port);
b45d5279
MR		 384}
385
386static void sbd_transmit_chars(struct sbd_port *sport)
387{
388 struct uart_port *uport = &sport->port;
ebd2c8f6 389 struct circ_buf *xmit = &sport->port.state->xmit;
b45d5279
MR		 390 unsigned int mask;
391 int stop_tx;
392
393 /* XON/XOFF chars. */
394 if (sport->port.x_char) {
395 write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char);
396 sport->port.icount.tx++;
397 sport->port.x_char = 0;
398 return;
399 }
400
401 /* If nothing to do or stopped or hardware stopped. */
402 stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port));
403
404 /* Send char. */
405 if (!stop_tx) {
406 write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]);
407 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
408 sport->port.icount.tx++;
409
410 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
411 uart_write_wakeup(&sport->port);
412 }
413
414 /* Are we are done? */
415 if (stop_tx || uart_circ_empty(xmit)) {
416 /* Disable tx interrupts. */
417 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
418 mask &= ~M_DUART_IMR_TX;
419 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
420 }
421}
422
423static void sbd_status_handle(struct sbd_port *sport)
424{
425 struct uart_port *uport = &sport->port;
426 unsigned int delta;
427
428 delta = read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
429 delta >>= (uport->line) % 2;
430
431 if (delta & (M_DUART_IN_PIN0_VAL << S_DUART_IN_PIN_CHNG))
432 uart_handle_cts_change(uport, !(delta & M_DUART_IN_PIN0_VAL));
433
434 if (delta & (M_DUART_IN_PIN2_VAL << S_DUART_IN_PIN_CHNG))
435 uport->icount.dsr++;
436
437 if (delta & ((M_DUART_IN_PIN2_VAL | M_DUART_IN_PIN0_VAL) <<
438 S_DUART_IN_PIN_CHNG))
bdc04e31 439 wake_up_interruptible(&uport->state->port.delta_msr_wait);
b45d5279
MR		 440}
441
442static irqreturn_t sbd_interrupt(int irq, void *dev_id)
443{
444 struct sbd_port *sport = dev_id;
445 struct uart_port *uport = &sport->port;
446 irqreturn_t status = IRQ_NONE;
447 unsigned int intstat;
448 int count;
449
450 for (count = 16; count; count--) {
451 intstat = read_sbdshr(sport,
452 R_DUART_ISRREG((uport->line) % 2));
453 intstat &= read_sbdshr(sport,
454 R_DUART_IMRREG((uport->line) % 2));
455 intstat &= M_DUART_ISR_ALL;
456 if (!intstat)
457 break;
458
459 if (intstat & M_DUART_ISR_RX)
460 sbd_receive_chars(sport);
461 if (intstat & M_DUART_ISR_IN)
462 sbd_status_handle(sport);
463 if (intstat & M_DUART_ISR_TX)
464 sbd_transmit_chars(sport);
465
466 status = IRQ_HANDLED;
467 }
468
469 return status;
470}
471
472
473static int sbd_startup(struct uart_port *uport)
474{
475 struct sbd_port *sport = to_sport(uport);
476 unsigned int mode1;
477 int ret;
478
479 ret = request_irq(sport->port.irq, sbd_interrupt,
480 IRQF_SHARED, "sb1250-duart", sport);
481 if (ret)
482 return ret;
483
484 /* Clear the receive FIFO. */
485 sbd_receive_drain(sport);
486
487 /* Clear the interrupt registers. */
488 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT);
489 read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
490
491 /* Set rx/tx interrupt to FIFO available. */
492 mode1 = read_sbdchn(sport, R_DUART_MODE_REG_1);
493 mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | M_DUART_TX_IRQ_SEL_TXEMPT);
494 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1);
495
496 /* Disable tx, enable rx. */
497 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_EN);
498 sport->tx_stopped = 1;
499
500 /* Enable interrupts. */
501 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
502 M_DUART_IMR_IN | M_DUART_IMR_RX);
503
504 return 0;
505}
506
507static void sbd_shutdown(struct uart_port *uport)
508{
509 struct sbd_port *sport = to_sport(uport);
510
511 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
512 sport->tx_stopped = 1;
513 free_irq(sport->port.irq, sport);
514}
515
516
517static void sbd_init_port(struct sbd_port *sport)
518{
519 struct uart_port *uport = &sport->port;
520
521 if (sport->initialised)
522 return;
523
524 /* There is no DUART reset feature, so just set some sane defaults. */
525 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_TX);
526 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_RX);
527 write_sbdchn(sport, R_DUART_MODE_REG_1, V_DUART_BITS_PER_CHAR_8);
528 write_sbdchn(sport, R_DUART_MODE_REG_2, 0);
529 write_sbdchn(sport, R_DUART_FULL_CTL,
530 V_DUART_INT_TIME(0) | V_DUART_SIG_FULL(15));
531 write_sbdchn(sport, R_DUART_OPCR_X, 0);
532 write_sbdchn(sport, R_DUART_AUXCTL_X, 0);
533 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
534
535 sport->initialised = 1;
536}
537
538static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios,
539 struct ktermios *old_termios)
540{
541 struct sbd_port *sport = to_sport(uport);
542 unsigned int mode1 = 0, mode2 = 0, aux = 0;
543 unsigned int mode1mask = 0, mode2mask = 0, auxmask = 0;
544 unsigned int oldmode1, oldmode2, oldaux;
545 unsigned int baud, brg;
546 unsigned int command;
547
548 mode1mask |= ~(M_DUART_PARITY_MODE | M_DUART_PARITY_TYPE_ODD |
549 M_DUART_BITS_PER_CHAR);
550 mode2mask |= ~M_DUART_STOP_BIT_LEN_2;
551 auxmask |= ~M_DUART_CTS_CHNG_ENA;
552
553 /* Byte size. */
554 switch (termios->c_cflag & CSIZE) {
555 case CS5:
556 case CS6:
557 /* Unsupported, leave unchanged. */
558 mode1mask |= M_DUART_PARITY_MODE;
559 break;
560 case CS7:
561 mode1 |= V_DUART_BITS_PER_CHAR_7;
562 break;
563 case CS8:
564 default:
565 mode1 |= V_DUART_BITS_PER_CHAR_8;
566 break;
567 }
568
569 /* Parity and stop bits. */
570 if (termios->c_cflag & CSTOPB)
571 mode2 |= M_DUART_STOP_BIT_LEN_2;
572 else
573 mode2 |= M_DUART_STOP_BIT_LEN_1;
574 if (termios->c_cflag & PARENB)
575 mode1 |= V_DUART_PARITY_MODE_ADD;
576 else
577 mode1 |= V_DUART_PARITY_MODE_NONE;
578 if (termios->c_cflag & PARODD)
579 mode1 |= M_DUART_PARITY_TYPE_ODD;
580 else
581 mode1 |= M_DUART_PARITY_TYPE_EVEN;
582
583 baud = uart_get_baud_rate(uport, termios, old_termios, 1200, 5000000);
584 brg = V_DUART_BAUD_RATE(baud);
585 /* The actual lower bound is 1221bps, so compensate. */
586 if (brg > M_DUART_CLK_COUNTER)
587 brg = M_DUART_CLK_COUNTER;
588
589 uart_update_timeout(uport, termios->c_cflag, baud);
590
591 uport->read_status_mask = M_DUART_OVRUN_ERR;
592 if (termios->c_iflag & INPCK)
593 uport->read_status_mask |= M_DUART_FRM_ERR |
594 M_DUART_PARITY_ERR;
ef8b9ddc 595 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
b45d5279
MR		 596 uport->read_status_mask |= M_DUART_RCVD_BRK;
597
598 uport->ignore_status_mask = 0;
599 if (termios->c_iflag & IGNPAR)
600 uport->ignore_status_mask |= M_DUART_FRM_ERR |
601 M_DUART_PARITY_ERR;
602 if (termios->c_iflag & IGNBRK) {
603 uport->ignore_status_mask |= M_DUART_RCVD_BRK;
604 if (termios->c_iflag & IGNPAR)
605 uport->ignore_status_mask |= M_DUART_OVRUN_ERR;
606 }
607
608 if (termios->c_cflag & CREAD)
609 command = M_DUART_RX_EN;
610 else
611 command = M_DUART_RX_DIS;
612
613 if (termios->c_cflag & CRTSCTS)
614 aux |= M_DUART_CTS_CHNG_ENA;
615 else
616 aux &= ~M_DUART_CTS_CHNG_ENA;
617
618 spin_lock(&uport->lock);
619
620 if (sport->tx_stopped)
621 command |= M_DUART_TX_DIS;
622 else
623 command |= M_DUART_TX_EN;
624
625 oldmode1 = read_sbdchn(sport, R_DUART_MODE_REG_1) & mode1mask;
626 oldmode2 = read_sbdchn(sport, R_DUART_MODE_REG_2) & mode2mask;
627 oldaux = read_sbdchn(sport, R_DUART_AUXCTL_X) & auxmask;
628
629 if (!sport->tx_stopped)
630 sbd_line_drain(sport);
631 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
632
633 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1 | oldmode1);
634 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode2);
635 write_sbdchn(sport, R_DUART_CLK_SEL, brg);
636 write_sbdchn(sport, R_DUART_AUXCTL_X, aux | oldaux);
637
638 write_sbdchn(sport, R_DUART_CMD, command);
639
640 spin_unlock(&uport->lock);
641}
642
643
644static const char *sbd_type(struct uart_port *uport)
645{
646 return "SB1250 DUART";
647}
648
649static void sbd_release_port(struct uart_port *uport)
650{
651 struct sbd_port *sport = to_sport(uport);
652 struct sbd_duart *duart = sport->duart;
b45d5279
MR		 653
654 iounmap(sport->memctrl);
655 sport->memctrl = NULL;
656 iounmap(uport->membase);
657 uport->membase = NULL;
658
22a33651 659 if(refcount_dec_and_test(&duart->map_guard))
b45d5279
MR		 660 release_mem_region(duart->mapctrl, DUART_CHANREG_SPACING);
661 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
662}
663
664static int sbd_map_port(struct uart_port *uport)
665{
86d0004a 666 const char *err = KERN_ERR "sbd: Cannot map MMIO\n";
b45d5279
MR		 667 struct sbd_port *sport = to_sport(uport);
668 struct sbd_duart *duart = sport->duart;
669
670 if (!uport->membase)
671 uport->membase = ioremap_nocache(uport->mapbase,
672 DUART_CHANREG_SPACING);
673 if (!uport->membase) {
674 printk(err);
675 return -ENOMEM;
676 }
677
678 if (!sport->memctrl)
679 sport->memctrl = ioremap_nocache(duart->mapctrl,
680 DUART_CHANREG_SPACING);
681 if (!sport->memctrl) {
682 printk(err);
683 iounmap(uport->membase);
684 uport->membase = NULL;
685 return -ENOMEM;
686 }
687
688 return 0;
689}
690
691static int sbd_request_port(struct uart_port *uport)
692{
86d0004a 693 const char *err = KERN_ERR "sbd: Unable to reserve MMIO resource\n";
b45d5279 694 struct sbd_duart *duart = to_sport(uport)->duart;
b45d5279
MR		 695 int ret = 0;
696
697 if (!request_mem_region(uport->mapbase, DUART_CHANREG_SPACING,
698 "sb1250-duart")) {
699 printk(err);
700 return -EBUSY;
701 }
22a33651
ER		 702 refcount_inc(&duart->map_guard);
703 if (refcount_read(&duart->map_guard) == 1) {
b45d5279
MR		 704 if (!request_mem_region(duart->mapctrl, DUART_CHANREG_SPACING,
705 "sb1250-duart")) {
22a33651 706 refcount_dec(&duart->map_guard);
b45d5279
MR		 707 printk(err);
708 ret = -EBUSY;
709 }
710 }
711 if (!ret) {
712 ret = sbd_map_port(uport);
713 if (ret) {
22a33651 714 if (refcount_dec_and_test(&duart->map_guard))
b45d5279
MR		 715 release_mem_region(duart->mapctrl,
716 DUART_CHANREG_SPACING);
717 }
718 }
719 if (ret) {
720 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
721 return ret;
722 }
723 return 0;
724}
725
726static void sbd_config_port(struct uart_port *uport, int flags)
727{
728 struct sbd_port *sport = to_sport(uport);
729
730 if (flags & UART_CONFIG_TYPE) {
731 if (sbd_request_port(uport))
732 return;
733
734 uport->type = PORT_SB1250_DUART;
735
736 sbd_init_port(sport);
737 }
738}
739
740static int sbd_verify_port(struct uart_port *uport, struct serial_struct *ser)
741{
742 int ret = 0;
743
744 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SB1250_DUART)
745 ret = -EINVAL;
746 if (ser->irq != uport->irq)
747 ret = -EINVAL;
748 if (ser->baud_base != uport->uartclk / 16)
749 ret = -EINVAL;
750 return ret;
751}
752
753
86d0004a 754static const struct uart_ops sbd_ops = {
b45d5279
MR		 755 .tx_empty = sbd_tx_empty,
756 .set_mctrl = sbd_set_mctrl,
757 .get_mctrl = sbd_get_mctrl,
758 .stop_tx = sbd_stop_tx,
759 .start_tx = sbd_start_tx,
760 .stop_rx = sbd_stop_rx,
761 .enable_ms = sbd_enable_ms,
762 .break_ctl = sbd_break_ctl,
763 .startup = sbd_startup,
764 .shutdown = sbd_shutdown,
765 .set_termios = sbd_set_termios,
766 .type = sbd_type,
767 .release_port = sbd_release_port,
768 .request_port = sbd_request_port,
769 .config_port = sbd_config_port,
770 .verify_port = sbd_verify_port,
771};
772
773/* Initialize SB1250 DUART port structures. */
774static void __init sbd_probe_duarts(void)
775{
776 static int probed;
777 int chip, side;
778 int max_lines, line;
779
780 if (probed)
781 return;
782
783 /* Set the number of available units based on the SOC type. */
784 switch (soc_type) {
785 case K_SYS_SOC_TYPE_BCM1x55:
786 case K_SYS_SOC_TYPE_BCM1x80:
787 max_lines = 4;
788 break;
789 default:
790 /* Assume at least two serial ports at the normal address. */
791 max_lines = 2;
792 break;
793 }
794
795 probed = 1;
796
797 for (chip = 0, line = 0; chip < DUART_MAX_CHIP && line < max_lines;
798 chip++) {
799 sbd_duarts[chip].mapctrl = SBD_CTRLREGS(line);
800
801 for (side = 0; side < DUART_MAX_SIDE && line < max_lines;
802 side++, line++) {
803 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
804 struct uart_port *uport = &sport->port;
805
806 sport->duart = &sbd_duarts[chip];
807
808 uport->irq = SBD_INT(line);
809 uport->uartclk = 100000000 / 20 * 16;
810 uport->fifosize = 16;
811 uport->iotype = UPIO_MEM;
812 uport->flags = UPF_BOOT_AUTOCONF;
813 uport->ops = &sbd_ops;
814 uport->line = line;
815 uport->mapbase = SBD_CHANREGS(line);
816 }
817 }
818}
819
820
821#ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE
822/*
823 * Serial console stuff. Very basic, polling driver for doing serial
ac751efa 824 * console output. The console_lock is held by the caller, so we
b45d5279
MR		 825 * shouldn't be interrupted for more console activity.
826 */
827static void sbd_console_putchar(struct uart_port *uport, int ch)
828{
829 struct sbd_port *sport = to_sport(uport);
830
831 sbd_transmit_drain(sport);
832 write_sbdchn(sport, R_DUART_TX_HOLD, ch);
833}
834
835static void sbd_console_write(struct console *co, const char *s,
836 unsigned int count)
837{
838 int chip = co->index / DUART_MAX_SIDE;
839 int side = co->index % DUART_MAX_SIDE;
840 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
841 struct uart_port *uport = &sport->port;
842 unsigned long flags;
843 unsigned int mask;
844
845 /* Disable transmit interrupts and enable the transmitter. */
846 spin_lock_irqsave(&uport->lock, flags);
847 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
848 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
849 mask & ~M_DUART_IMR_TX);
850 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
851 spin_unlock_irqrestore(&uport->lock, flags);
852
853 uart_console_write(&sport->port, s, count, sbd_console_putchar);
854
855 /* Restore transmit interrupts and the transmitter enable. */
856 spin_lock_irqsave(&uport->lock, flags);
857 sbd_line_drain(sport);
858 if (sport->tx_stopped)
859 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
860 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
861 spin_unlock_irqrestore(&uport->lock, flags);
862}
863
864static int __init sbd_console_setup(struct console *co, char *options)
865{
866 int chip = co->index / DUART_MAX_SIDE;
867 int side = co->index % DUART_MAX_SIDE;
868 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
869 struct uart_port *uport = &sport->port;
870 int baud = 115200;
871 int bits = 8;
872 int parity = 'n';
873 int flow = 'n';
874 int ret;
875
876 if (!sport->duart)
877 return -ENXIO;
878
879 ret = sbd_map_port(uport);
880 if (ret)
881 return ret;
882
883 sbd_init_port(sport);
884
885 if (options)
886 uart_parse_options(options, &baud, &parity, &bits, &flow);
887 return uart_set_options(uport, co, baud, parity, bits, flow);
888}
889
890static struct uart_driver sbd_reg;
891static struct console sbd_console = {
892 .name = "duart",
893 .write = sbd_console_write,
894 .device = uart_console_device,
895 .setup = sbd_console_setup,
896 .flags = CON_PRINTBUFFER,
897 .index = -1,
898 .data = &sbd_reg
899};
900
901static int __init sbd_serial_console_init(void)
902{
903 sbd_probe_duarts();
904 register_console(&sbd_console);
905
906 return 0;
907}
908
909console_initcall(sbd_serial_console_init);
910
911#define SERIAL_SB1250_DUART_CONSOLE &sbd_console
912#else
913#define SERIAL_SB1250_DUART_CONSOLE NULL
914#endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE */
915
916
917static struct uart_driver sbd_reg = {
918 .owner = THIS_MODULE,
4feead71 919 .driver_name = "sb1250_duart",
b45d5279
MR		 920 .dev_name = "duart",
921 .major = TTY_MAJOR,
922 .minor = SB1250_DUART_MINOR_BASE,
923 .nr = DUART_MAX_CHIP * DUART_MAX_SIDE,
924 .cons = SERIAL_SB1250_DUART_CONSOLE,
925};
926
927/* Set up the driver and register it. */
928static int __init sbd_init(void)
929{
930 int i, ret;
931
932 sbd_probe_duarts();
933
934 ret = uart_register_driver(&sbd_reg);
935 if (ret)
936 return ret;
937
938 for (i = 0; i < DUART_MAX_CHIP * DUART_MAX_SIDE; i++) {
939 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
940 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
941 struct uart_port *uport = &sport->port;
942
943 if (sport->duart)
944 uart_add_one_port(&sbd_reg, uport);
945 }
946
947 return 0;
948}
949
950/* Unload the driver. Unregister stuff, get ready to go away. */
951static void __exit sbd_exit(void)
952{
953 int i;
954
955 for (i = DUART_MAX_CHIP * DUART_MAX_SIDE - 1; i >= 0; i--) {
956 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
957 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
958 struct uart_port *uport = &sport->port;
959
960 if (sport->duart)
961 uart_remove_one_port(&sbd_reg, uport);
962 }
963
964 uart_unregister_driver(&sbd_reg);
965}
966
967module_init(sbd_init);
968module_exit(sbd_exit);
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