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1d65c0b1 AS |
1 | /* |
2 | * NXP (Philips) SCC+++(SCN+++) serial driver | |
3 | * | |
4 | * Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru> | |
5 | * | |
6 | * Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de) | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
15 | #define SUPPORT_SYSRQ | |
16 | #endif | |
17 | ||
90efa75f | 18 | #include <linux/clk.h> |
eb612fa0 | 19 | #include <linux/err.h> |
1d65c0b1 AS |
20 | #include <linux/module.h> |
21 | #include <linux/device.h> | |
d83b5425 | 22 | #include <linux/console.h> |
1d65c0b1 AS |
23 | #include <linux/serial_core.h> |
24 | #include <linux/serial.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/tty.h> | |
27 | #include <linux/tty_flip.h> | |
ec063899 | 28 | #include <linux/spinlock.h> |
1d65c0b1 | 29 | #include <linux/platform_device.h> |
463dcc42 | 30 | #include <linux/platform_data/serial-sccnxp.h> |
31815c08 | 31 | #include <linux/regulator/consumer.h> |
1d65c0b1 AS |
32 | |
33 | #define SCCNXP_NAME "uart-sccnxp" | |
34 | #define SCCNXP_MAJOR 204 | |
35 | #define SCCNXP_MINOR 205 | |
36 | ||
37 | #define SCCNXP_MR_REG (0x00) | |
38 | # define MR0_BAUD_NORMAL (0 << 0) | |
39 | # define MR0_BAUD_EXT1 (1 << 0) | |
40 | # define MR0_BAUD_EXT2 (5 << 0) | |
41 | # define MR0_FIFO (1 << 3) | |
42 | # define MR0_TXLVL (1 << 4) | |
43 | # define MR1_BITS_5 (0 << 0) | |
44 | # define MR1_BITS_6 (1 << 0) | |
45 | # define MR1_BITS_7 (2 << 0) | |
46 | # define MR1_BITS_8 (3 << 0) | |
47 | # define MR1_PAR_EVN (0 << 2) | |
48 | # define MR1_PAR_ODD (1 << 2) | |
49 | # define MR1_PAR_NO (4 << 2) | |
50 | # define MR2_STOP1 (7 << 0) | |
51 | # define MR2_STOP2 (0xf << 0) | |
52 | #define SCCNXP_SR_REG (0x01) | |
53 | #define SCCNXP_CSR_REG SCCNXP_SR_REG | |
54 | # define SR_RXRDY (1 << 0) | |
55 | # define SR_FULL (1 << 1) | |
56 | # define SR_TXRDY (1 << 2) | |
57 | # define SR_TXEMT (1 << 3) | |
58 | # define SR_OVR (1 << 4) | |
59 | # define SR_PE (1 << 5) | |
60 | # define SR_FE (1 << 6) | |
61 | # define SR_BRK (1 << 7) | |
62 | #define SCCNXP_CR_REG (0x02) | |
63 | # define CR_RX_ENABLE (1 << 0) | |
64 | # define CR_RX_DISABLE (1 << 1) | |
65 | # define CR_TX_ENABLE (1 << 2) | |
66 | # define CR_TX_DISABLE (1 << 3) | |
67 | # define CR_CMD_MRPTR1 (0x01 << 4) | |
68 | # define CR_CMD_RX_RESET (0x02 << 4) | |
69 | # define CR_CMD_TX_RESET (0x03 << 4) | |
70 | # define CR_CMD_STATUS_RESET (0x04 << 4) | |
71 | # define CR_CMD_BREAK_RESET (0x05 << 4) | |
72 | # define CR_CMD_START_BREAK (0x06 << 4) | |
73 | # define CR_CMD_STOP_BREAK (0x07 << 4) | |
74 | # define CR_CMD_MRPTR0 (0x0b << 4) | |
75 | #define SCCNXP_RHR_REG (0x03) | |
76 | #define SCCNXP_THR_REG SCCNXP_RHR_REG | |
77 | #define SCCNXP_IPCR_REG (0x04) | |
78 | #define SCCNXP_ACR_REG SCCNXP_IPCR_REG | |
79 | # define ACR_BAUD0 (0 << 7) | |
80 | # define ACR_BAUD1 (1 << 7) | |
81 | # define ACR_TIMER_MODE (6 << 4) | |
82 | #define SCCNXP_ISR_REG (0x05) | |
83 | #define SCCNXP_IMR_REG SCCNXP_ISR_REG | |
84 | # define IMR_TXRDY (1 << 0) | |
85 | # define IMR_RXRDY (1 << 1) | |
86 | # define ISR_TXRDY(x) (1 << ((x * 4) + 0)) | |
87 | # define ISR_RXRDY(x) (1 << ((x * 4) + 1)) | |
88 | #define SCCNXP_IPR_REG (0x0d) | |
89 | #define SCCNXP_OPCR_REG SCCNXP_IPR_REG | |
90 | #define SCCNXP_SOP_REG (0x0e) | |
91 | #define SCCNXP_ROP_REG (0x0f) | |
92 | ||
93 | /* Route helpers */ | |
94 | #define MCTRL_MASK(sig) (0xf << (sig)) | |
95 | #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) | |
96 | #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) | |
97 | ||
ea4c39be AS |
98 | #define SCCNXP_HAVE_IO 0x00000001 |
99 | #define SCCNXP_HAVE_MR0 0x00000002 | |
100 | ||
101 | struct sccnxp_chip { | |
102 | const char *name; | |
103 | unsigned int nr; | |
104 | unsigned long freq_min; | |
105 | unsigned long freq_std; | |
106 | unsigned long freq_max; | |
107 | unsigned int flags; | |
108 | unsigned int fifosize; | |
1d65c0b1 AS |
109 | }; |
110 | ||
111 | struct sccnxp_port { | |
112 | struct uart_driver uart; | |
113 | struct uart_port port[SCCNXP_MAX_UARTS]; | |
ec063899 | 114 | bool opened[SCCNXP_MAX_UARTS]; |
1d65c0b1 | 115 | |
1d65c0b1 | 116 | int irq; |
1d65c0b1 | 117 | u8 imr; |
1d65c0b1 | 118 | |
ea4c39be | 119 | struct sccnxp_chip *chip; |
1d65c0b1 AS |
120 | |
121 | #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE | |
122 | struct console console; | |
123 | #endif | |
124 | ||
ec063899 AS |
125 | spinlock_t lock; |
126 | ||
127 | bool poll; | |
128 | struct timer_list timer; | |
1d65c0b1 AS |
129 | |
130 | struct sccnxp_pdata pdata; | |
31815c08 AS |
131 | |
132 | struct regulator *regulator; | |
1d65c0b1 AS |
133 | }; |
134 | ||
ea4c39be AS |
135 | static const struct sccnxp_chip sc2681 = { |
136 | .name = "SC2681", | |
137 | .nr = 2, | |
138 | .freq_min = 1000000, | |
139 | .freq_std = 3686400, | |
140 | .freq_max = 4000000, | |
141 | .flags = SCCNXP_HAVE_IO, | |
142 | .fifosize = 3, | |
143 | }; | |
1d65c0b1 | 144 | |
ea4c39be AS |
145 | static const struct sccnxp_chip sc2691 = { |
146 | .name = "SC2691", | |
147 | .nr = 1, | |
148 | .freq_min = 1000000, | |
149 | .freq_std = 3686400, | |
150 | .freq_max = 4000000, | |
151 | .flags = 0, | |
152 | .fifosize = 3, | |
153 | }; | |
154 | ||
155 | static const struct sccnxp_chip sc2692 = { | |
156 | .name = "SC2692", | |
157 | .nr = 2, | |
158 | .freq_min = 1000000, | |
159 | .freq_std = 3686400, | |
160 | .freq_max = 4000000, | |
161 | .flags = SCCNXP_HAVE_IO, | |
162 | .fifosize = 3, | |
163 | }; | |
164 | ||
165 | static const struct sccnxp_chip sc2891 = { | |
166 | .name = "SC2891", | |
167 | .nr = 1, | |
168 | .freq_min = 100000, | |
169 | .freq_std = 3686400, | |
170 | .freq_max = 8000000, | |
171 | .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, | |
172 | .fifosize = 16, | |
173 | }; | |
174 | ||
175 | static const struct sccnxp_chip sc2892 = { | |
176 | .name = "SC2892", | |
177 | .nr = 2, | |
178 | .freq_min = 100000, | |
179 | .freq_std = 3686400, | |
180 | .freq_max = 8000000, | |
181 | .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, | |
182 | .fifosize = 16, | |
183 | }; | |
184 | ||
185 | static const struct sccnxp_chip sc28202 = { | |
186 | .name = "SC28202", | |
187 | .nr = 2, | |
188 | .freq_min = 1000000, | |
189 | .freq_std = 14745600, | |
190 | .freq_max = 50000000, | |
191 | .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0, | |
192 | .fifosize = 256, | |
193 | }; | |
194 | ||
195 | static const struct sccnxp_chip sc68681 = { | |
196 | .name = "SC68681", | |
197 | .nr = 2, | |
198 | .freq_min = 1000000, | |
199 | .freq_std = 3686400, | |
200 | .freq_max = 4000000, | |
201 | .flags = SCCNXP_HAVE_IO, | |
202 | .fifosize = 3, | |
203 | }; | |
204 | ||
205 | static const struct sccnxp_chip sc68692 = { | |
206 | .name = "SC68692", | |
207 | .nr = 2, | |
208 | .freq_min = 1000000, | |
209 | .freq_std = 3686400, | |
210 | .freq_max = 4000000, | |
211 | .flags = SCCNXP_HAVE_IO, | |
212 | .fifosize = 3, | |
213 | }; | |
1d65c0b1 AS |
214 | |
215 | static inline u8 sccnxp_read(struct uart_port *port, u8 reg) | |
216 | { | |
ea4c39be | 217 | return readb(port->membase + (reg << port->regshift)); |
1d65c0b1 AS |
218 | } |
219 | ||
220 | static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v) | |
221 | { | |
ea4c39be | 222 | writeb(v, port->membase + (reg << port->regshift)); |
1d65c0b1 AS |
223 | } |
224 | ||
225 | static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg) | |
226 | { | |
227 | return sccnxp_read(port, (port->line << 3) + reg); | |
228 | } | |
229 | ||
230 | static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v) | |
231 | { | |
232 | sccnxp_write(port, (port->line << 3) + reg, v); | |
233 | } | |
234 | ||
235 | static int sccnxp_update_best_err(int a, int b, int *besterr) | |
236 | { | |
237 | int err = abs(a - b); | |
238 | ||
239 | if ((*besterr < 0) || (*besterr > err)) { | |
240 | *besterr = err; | |
241 | return 0; | |
242 | } | |
243 | ||
244 | return 1; | |
245 | } | |
246 | ||
4bbed6bc | 247 | static const struct { |
1d65c0b1 AS |
248 | u8 csr; |
249 | u8 acr; | |
250 | u8 mr0; | |
251 | int baud; | |
4bbed6bc | 252 | } baud_std[] = { |
1d65c0b1 AS |
253 | { 0, ACR_BAUD0, MR0_BAUD_NORMAL, 50, }, |
254 | { 0, ACR_BAUD1, MR0_BAUD_NORMAL, 75, }, | |
255 | { 1, ACR_BAUD0, MR0_BAUD_NORMAL, 110, }, | |
256 | { 2, ACR_BAUD0, MR0_BAUD_NORMAL, 134, }, | |
257 | { 3, ACR_BAUD1, MR0_BAUD_NORMAL, 150, }, | |
258 | { 3, ACR_BAUD0, MR0_BAUD_NORMAL, 200, }, | |
259 | { 4, ACR_BAUD0, MR0_BAUD_NORMAL, 300, }, | |
260 | { 0, ACR_BAUD1, MR0_BAUD_EXT1, 450, }, | |
261 | { 1, ACR_BAUD0, MR0_BAUD_EXT2, 880, }, | |
262 | { 3, ACR_BAUD1, MR0_BAUD_EXT1, 900, }, | |
263 | { 5, ACR_BAUD0, MR0_BAUD_NORMAL, 600, }, | |
264 | { 7, ACR_BAUD0, MR0_BAUD_NORMAL, 1050, }, | |
265 | { 2, ACR_BAUD0, MR0_BAUD_EXT2, 1076, }, | |
266 | { 6, ACR_BAUD0, MR0_BAUD_NORMAL, 1200, }, | |
267 | { 10, ACR_BAUD1, MR0_BAUD_NORMAL, 1800, }, | |
268 | { 7, ACR_BAUD1, MR0_BAUD_NORMAL, 2000, }, | |
269 | { 8, ACR_BAUD0, MR0_BAUD_NORMAL, 2400, }, | |
270 | { 5, ACR_BAUD1, MR0_BAUD_EXT1, 3600, }, | |
271 | { 9, ACR_BAUD0, MR0_BAUD_NORMAL, 4800, }, | |
272 | { 10, ACR_BAUD0, MR0_BAUD_NORMAL, 7200, }, | |
273 | { 11, ACR_BAUD0, MR0_BAUD_NORMAL, 9600, }, | |
274 | { 8, ACR_BAUD0, MR0_BAUD_EXT1, 14400, }, | |
275 | { 12, ACR_BAUD1, MR0_BAUD_NORMAL, 19200, }, | |
276 | { 9, ACR_BAUD0, MR0_BAUD_EXT1, 28800, }, | |
277 | { 12, ACR_BAUD0, MR0_BAUD_NORMAL, 38400, }, | |
278 | { 11, ACR_BAUD0, MR0_BAUD_EXT1, 57600, }, | |
279 | { 12, ACR_BAUD1, MR0_BAUD_EXT1, 115200, }, | |
280 | { 12, ACR_BAUD0, MR0_BAUD_EXT1, 230400, }, | |
281 | { 0, 0, 0, 0 } | |
282 | }; | |
283 | ||
1685118f | 284 | static int sccnxp_set_baud(struct uart_port *port, int baud) |
1d65c0b1 AS |
285 | { |
286 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
287 | int div_std, tmp_baud, bestbaud = baud, besterr = -1; | |
ea4c39be | 288 | struct sccnxp_chip *chip = s->chip; |
1d65c0b1 AS |
289 | u8 i, acr = 0, csr = 0, mr0 = 0; |
290 | ||
291 | /* Find best baud from table */ | |
292 | for (i = 0; baud_std[i].baud && besterr; i++) { | |
ea4c39be | 293 | if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0)) |
1d65c0b1 | 294 | continue; |
ea4c39be | 295 | div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud); |
1d65c0b1 AS |
296 | tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); |
297 | if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { | |
298 | acr = baud_std[i].acr; | |
299 | csr = baud_std[i].csr; | |
300 | mr0 = baud_std[i].mr0; | |
301 | bestbaud = tmp_baud; | |
302 | } | |
303 | } | |
304 | ||
ea4c39be | 305 | if (chip->flags & SCCNXP_HAVE_MR0) { |
1d65c0b1 AS |
306 | /* Enable FIFO, set half level for TX */ |
307 | mr0 |= MR0_FIFO | MR0_TXLVL; | |
308 | /* Update MR0 */ | |
309 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0); | |
310 | sccnxp_port_write(port, SCCNXP_MR_REG, mr0); | |
311 | } | |
312 | ||
313 | sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE); | |
314 | sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr); | |
315 | ||
1685118f AS |
316 | if (baud != bestbaud) |
317 | dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n", | |
318 | baud, bestbaud); | |
319 | ||
320 | return bestbaud; | |
1d65c0b1 AS |
321 | } |
322 | ||
323 | static void sccnxp_enable_irq(struct uart_port *port, int mask) | |
324 | { | |
325 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
326 | ||
327 | s->imr |= mask << (port->line * 4); | |
328 | sccnxp_write(port, SCCNXP_IMR_REG, s->imr); | |
329 | } | |
330 | ||
331 | static void sccnxp_disable_irq(struct uart_port *port, int mask) | |
332 | { | |
333 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
334 | ||
335 | s->imr &= ~(mask << (port->line * 4)); | |
336 | sccnxp_write(port, SCCNXP_IMR_REG, s->imr); | |
337 | } | |
338 | ||
339 | static void sccnxp_set_bit(struct uart_port *port, int sig, int state) | |
340 | { | |
341 | u8 bitmask; | |
342 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
343 | ||
344 | if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) { | |
345 | bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig); | |
346 | if (state) | |
347 | sccnxp_write(port, SCCNXP_SOP_REG, bitmask); | |
348 | else | |
349 | sccnxp_write(port, SCCNXP_ROP_REG, bitmask); | |
350 | } | |
351 | } | |
352 | ||
353 | static void sccnxp_handle_rx(struct uart_port *port) | |
354 | { | |
355 | u8 sr; | |
356 | unsigned int ch, flag; | |
1d65c0b1 AS |
357 | |
358 | for (;;) { | |
359 | sr = sccnxp_port_read(port, SCCNXP_SR_REG); | |
360 | if (!(sr & SR_RXRDY)) | |
361 | break; | |
362 | sr &= SR_PE | SR_FE | SR_OVR | SR_BRK; | |
363 | ||
364 | ch = sccnxp_port_read(port, SCCNXP_RHR_REG); | |
365 | ||
366 | port->icount.rx++; | |
367 | flag = TTY_NORMAL; | |
368 | ||
369 | if (unlikely(sr)) { | |
370 | if (sr & SR_BRK) { | |
371 | port->icount.brk++; | |
f548b96d AS |
372 | sccnxp_port_write(port, SCCNXP_CR_REG, |
373 | CR_CMD_BREAK_RESET); | |
1d65c0b1 AS |
374 | if (uart_handle_break(port)) |
375 | continue; | |
376 | } else if (sr & SR_PE) | |
377 | port->icount.parity++; | |
378 | else if (sr & SR_FE) | |
379 | port->icount.frame++; | |
f548b96d | 380 | else if (sr & SR_OVR) { |
1d65c0b1 | 381 | port->icount.overrun++; |
f548b96d AS |
382 | sccnxp_port_write(port, SCCNXP_CR_REG, |
383 | CR_CMD_STATUS_RESET); | |
384 | } | |
1d65c0b1 AS |
385 | |
386 | sr &= port->read_status_mask; | |
387 | if (sr & SR_BRK) | |
388 | flag = TTY_BREAK; | |
389 | else if (sr & SR_PE) | |
390 | flag = TTY_PARITY; | |
391 | else if (sr & SR_FE) | |
392 | flag = TTY_FRAME; | |
393 | else if (sr & SR_OVR) | |
394 | flag = TTY_OVERRUN; | |
395 | } | |
396 | ||
397 | if (uart_handle_sysrq_char(port, ch)) | |
398 | continue; | |
399 | ||
400 | if (sr & port->ignore_status_mask) | |
401 | continue; | |
402 | ||
403 | uart_insert_char(port, sr, SR_OVR, ch, flag); | |
404 | } | |
405 | ||
2e124b4a | 406 | tty_flip_buffer_push(&port->state->port); |
1d65c0b1 AS |
407 | } |
408 | ||
409 | static void sccnxp_handle_tx(struct uart_port *port) | |
410 | { | |
411 | u8 sr; | |
412 | struct circ_buf *xmit = &port->state->xmit; | |
413 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
414 | ||
415 | if (unlikely(port->x_char)) { | |
416 | sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char); | |
417 | port->icount.tx++; | |
418 | port->x_char = 0; | |
419 | return; | |
420 | } | |
421 | ||
422 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
423 | /* Disable TX if FIFO is empty */ | |
424 | if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) { | |
425 | sccnxp_disable_irq(port, IMR_TXRDY); | |
426 | ||
427 | /* Set direction to input */ | |
ea4c39be | 428 | if (s->chip->flags & SCCNXP_HAVE_IO) |
1d65c0b1 AS |
429 | sccnxp_set_bit(port, DIR_OP, 0); |
430 | } | |
431 | return; | |
432 | } | |
433 | ||
434 | while (!uart_circ_empty(xmit)) { | |
435 | sr = sccnxp_port_read(port, SCCNXP_SR_REG); | |
436 | if (!(sr & SR_TXRDY)) | |
437 | break; | |
438 | ||
439 | sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]); | |
440 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
441 | port->icount.tx++; | |
442 | } | |
443 | ||
444 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
445 | uart_write_wakeup(port); | |
446 | } | |
447 | ||
ec063899 | 448 | static void sccnxp_handle_events(struct sccnxp_port *s) |
1d65c0b1 AS |
449 | { |
450 | int i; | |
451 | u8 isr; | |
1d65c0b1 | 452 | |
ec063899 | 453 | do { |
1d65c0b1 AS |
454 | isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG); |
455 | isr &= s->imr; | |
456 | if (!isr) | |
457 | break; | |
458 | ||
1d65c0b1 | 459 | for (i = 0; i < s->uart.nr; i++) { |
ec063899 | 460 | if (s->opened[i] && (isr & ISR_RXRDY(i))) |
1d65c0b1 | 461 | sccnxp_handle_rx(&s->port[i]); |
ec063899 | 462 | if (s->opened[i] && (isr & ISR_TXRDY(i))) |
1d65c0b1 AS |
463 | sccnxp_handle_tx(&s->port[i]); |
464 | } | |
ec063899 AS |
465 | } while (1); |
466 | } | |
467 | ||
468 | static void sccnxp_timer(unsigned long data) | |
469 | { | |
470 | struct sccnxp_port *s = (struct sccnxp_port *)data; | |
471 | unsigned long flags; | |
1d65c0b1 | 472 | |
ec063899 AS |
473 | spin_lock_irqsave(&s->lock, flags); |
474 | sccnxp_handle_events(s); | |
475 | spin_unlock_irqrestore(&s->lock, flags); | |
476 | ||
477 | if (!timer_pending(&s->timer)) | |
478 | mod_timer(&s->timer, jiffies + | |
479 | usecs_to_jiffies(s->pdata.poll_time_us)); | |
480 | } | |
481 | ||
482 | static irqreturn_t sccnxp_ist(int irq, void *dev_id) | |
483 | { | |
484 | struct sccnxp_port *s = (struct sccnxp_port *)dev_id; | |
485 | unsigned long flags; | |
486 | ||
487 | spin_lock_irqsave(&s->lock, flags); | |
488 | sccnxp_handle_events(s); | |
489 | spin_unlock_irqrestore(&s->lock, flags); | |
1d65c0b1 AS |
490 | |
491 | return IRQ_HANDLED; | |
492 | } | |
493 | ||
494 | static void sccnxp_start_tx(struct uart_port *port) | |
495 | { | |
496 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
ec063899 | 497 | unsigned long flags; |
1d65c0b1 | 498 | |
ec063899 | 499 | spin_lock_irqsave(&s->lock, flags); |
1d65c0b1 AS |
500 | |
501 | /* Set direction to output */ | |
ea4c39be | 502 | if (s->chip->flags & SCCNXP_HAVE_IO) |
1d65c0b1 AS |
503 | sccnxp_set_bit(port, DIR_OP, 1); |
504 | ||
505 | sccnxp_enable_irq(port, IMR_TXRDY); | |
506 | ||
ec063899 | 507 | spin_unlock_irqrestore(&s->lock, flags); |
1d65c0b1 AS |
508 | } |
509 | ||
510 | static void sccnxp_stop_tx(struct uart_port *port) | |
511 | { | |
512 | /* Do nothing */ | |
513 | } | |
514 | ||
515 | static void sccnxp_stop_rx(struct uart_port *port) | |
516 | { | |
517 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
ec063899 | 518 | unsigned long flags; |
1d65c0b1 | 519 | |
ec063899 | 520 | spin_lock_irqsave(&s->lock, flags); |
1d65c0b1 | 521 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE); |
ec063899 | 522 | spin_unlock_irqrestore(&s->lock, flags); |
1d65c0b1 AS |
523 | } |
524 | ||
525 | static unsigned int sccnxp_tx_empty(struct uart_port *port) | |
526 | { | |
527 | u8 val; | |
ec063899 | 528 | unsigned long flags; |
1d65c0b1 AS |
529 | struct sccnxp_port *s = dev_get_drvdata(port->dev); |
530 | ||
ec063899 | 531 | spin_lock_irqsave(&s->lock, flags); |
1d65c0b1 | 532 | val = sccnxp_port_read(port, SCCNXP_SR_REG); |
ec063899 | 533 | spin_unlock_irqrestore(&s->lock, flags); |
1d65c0b1 AS |
534 | |
535 | return (val & SR_TXEMT) ? TIOCSER_TEMT : 0; | |
536 | } | |
537 | ||
538 | static void sccnxp_enable_ms(struct uart_port *port) | |
539 | { | |
540 | /* Do nothing */ | |
541 | } | |
542 | ||
543 | static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
544 | { | |
545 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
ec063899 | 546 | unsigned long flags; |
1d65c0b1 | 547 | |
ea4c39be | 548 | if (!(s->chip->flags & SCCNXP_HAVE_IO)) |
1d65c0b1 AS |
549 | return; |
550 | ||
ec063899 | 551 | spin_lock_irqsave(&s->lock, flags); |
1d65c0b1 AS |
552 | |
553 | sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR); | |
554 | sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS); | |
555 | ||
ec063899 | 556 | spin_unlock_irqrestore(&s->lock, flags); |
1d65c0b1 AS |
557 | } |
558 | ||
559 | static unsigned int sccnxp_get_mctrl(struct uart_port *port) | |
560 | { | |
561 | u8 bitmask, ipr; | |
ec063899 | 562 | unsigned long flags; |
1d65c0b1 AS |
563 | struct sccnxp_port *s = dev_get_drvdata(port->dev); |
564 | unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; | |
565 | ||
ea4c39be | 566 | if (!(s->chip->flags & SCCNXP_HAVE_IO)) |
1d65c0b1 AS |
567 | return mctrl; |
568 | ||
ec063899 | 569 | spin_lock_irqsave(&s->lock, flags); |
1d65c0b1 AS |
570 | |
571 | ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG); | |
572 | ||
573 | if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) { | |
574 | bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], | |
575 | DSR_IP); | |
576 | mctrl &= ~TIOCM_DSR; | |
577 | mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0; | |
578 | } | |
579 | if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) { | |
580 | bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], | |
581 | CTS_IP); | |
582 | mctrl &= ~TIOCM_CTS; | |
583 | mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0; | |
584 | } | |
585 | if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) { | |
586 | bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], | |
587 | DCD_IP); | |
588 | mctrl &= ~TIOCM_CAR; | |
589 | mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0; | |
590 | } | |
591 | if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) { | |
592 | bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line], | |
593 | RNG_IP); | |
594 | mctrl &= ~TIOCM_RNG; | |
595 | mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0; | |
596 | } | |
597 | ||
ec063899 | 598 | spin_unlock_irqrestore(&s->lock, flags); |
1d65c0b1 AS |
599 | |
600 | return mctrl; | |
601 | } | |
602 | ||
603 | static void sccnxp_break_ctl(struct uart_port *port, int break_state) | |
604 | { | |
605 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
ec063899 | 606 | unsigned long flags; |
1d65c0b1 | 607 | |
ec063899 | 608 | spin_lock_irqsave(&s->lock, flags); |
1d65c0b1 AS |
609 | sccnxp_port_write(port, SCCNXP_CR_REG, break_state ? |
610 | CR_CMD_START_BREAK : CR_CMD_STOP_BREAK); | |
ec063899 | 611 | spin_unlock_irqrestore(&s->lock, flags); |
1d65c0b1 AS |
612 | } |
613 | ||
614 | static void sccnxp_set_termios(struct uart_port *port, | |
615 | struct ktermios *termios, struct ktermios *old) | |
616 | { | |
617 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
ec063899 | 618 | unsigned long flags; |
1d65c0b1 AS |
619 | u8 mr1, mr2; |
620 | int baud; | |
621 | ||
ec063899 | 622 | spin_lock_irqsave(&s->lock, flags); |
1d65c0b1 AS |
623 | |
624 | /* Mask termios capabilities we don't support */ | |
625 | termios->c_cflag &= ~CMSPAR; | |
1d65c0b1 AS |
626 | |
627 | /* Disable RX & TX, reset break condition, status and FIFOs */ | |
628 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET | | |
629 | CR_RX_DISABLE | CR_TX_DISABLE); | |
630 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); | |
631 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); | |
632 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); | |
633 | ||
634 | /* Word size */ | |
635 | switch (termios->c_cflag & CSIZE) { | |
636 | case CS5: | |
637 | mr1 = MR1_BITS_5; | |
638 | break; | |
639 | case CS6: | |
640 | mr1 = MR1_BITS_6; | |
641 | break; | |
642 | case CS7: | |
643 | mr1 = MR1_BITS_7; | |
644 | break; | |
1d65c0b1 | 645 | case CS8: |
91f61ce2 | 646 | default: |
1d65c0b1 AS |
647 | mr1 = MR1_BITS_8; |
648 | break; | |
649 | } | |
650 | ||
651 | /* Parity */ | |
652 | if (termios->c_cflag & PARENB) { | |
653 | if (termios->c_cflag & PARODD) | |
654 | mr1 |= MR1_PAR_ODD; | |
655 | } else | |
656 | mr1 |= MR1_PAR_NO; | |
657 | ||
658 | /* Stop bits */ | |
659 | mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1; | |
660 | ||
661 | /* Update desired format */ | |
662 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1); | |
663 | sccnxp_port_write(port, SCCNXP_MR_REG, mr1); | |
664 | sccnxp_port_write(port, SCCNXP_MR_REG, mr2); | |
665 | ||
666 | /* Set read status mask */ | |
667 | port->read_status_mask = SR_OVR; | |
668 | if (termios->c_iflag & INPCK) | |
669 | port->read_status_mask |= SR_PE | SR_FE; | |
670 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
671 | port->read_status_mask |= SR_BRK; | |
672 | ||
673 | /* Set status ignore mask */ | |
674 | port->ignore_status_mask = 0; | |
675 | if (termios->c_iflag & IGNBRK) | |
676 | port->ignore_status_mask |= SR_BRK; | |
677 | if (!(termios->c_cflag & CREAD)) | |
678 | port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK; | |
679 | ||
680 | /* Setup baudrate */ | |
681 | baud = uart_get_baud_rate(port, termios, old, 50, | |
ea4c39be | 682 | (s->chip->flags & SCCNXP_HAVE_MR0) ? |
1d65c0b1 | 683 | 230400 : 38400); |
1685118f | 684 | baud = sccnxp_set_baud(port, baud); |
1d65c0b1 AS |
685 | |
686 | /* Update timeout according to new baud rate */ | |
687 | uart_update_timeout(port, termios->c_cflag, baud); | |
688 | ||
ec063899 | 689 | /* Report actual baudrate back to core */ |
1685118f AS |
690 | if (tty_termios_baud_rate(termios)) |
691 | tty_termios_encode_baud_rate(termios, baud, baud); | |
692 | ||
1d65c0b1 AS |
693 | /* Enable RX & TX */ |
694 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); | |
695 | ||
ec063899 | 696 | spin_unlock_irqrestore(&s->lock, flags); |
1d65c0b1 AS |
697 | } |
698 | ||
699 | static int sccnxp_startup(struct uart_port *port) | |
700 | { | |
701 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
ec063899 | 702 | unsigned long flags; |
1d65c0b1 | 703 | |
ec063899 | 704 | spin_lock_irqsave(&s->lock, flags); |
1d65c0b1 | 705 | |
ea4c39be | 706 | if (s->chip->flags & SCCNXP_HAVE_IO) { |
1d65c0b1 AS |
707 | /* Outputs are controlled manually */ |
708 | sccnxp_write(port, SCCNXP_OPCR_REG, 0); | |
709 | } | |
710 | ||
711 | /* Reset break condition, status and FIFOs */ | |
712 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET); | |
713 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET); | |
714 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET); | |
715 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET); | |
716 | ||
717 | /* Enable RX & TX */ | |
718 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE); | |
719 | ||
720 | /* Enable RX interrupt */ | |
721 | sccnxp_enable_irq(port, IMR_RXRDY); | |
722 | ||
ec063899 AS |
723 | s->opened[port->line] = 1; |
724 | ||
725 | spin_unlock_irqrestore(&s->lock, flags); | |
1d65c0b1 AS |
726 | |
727 | return 0; | |
728 | } | |
729 | ||
730 | static void sccnxp_shutdown(struct uart_port *port) | |
731 | { | |
732 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
ec063899 | 733 | unsigned long flags; |
1d65c0b1 | 734 | |
ec063899 | 735 | spin_lock_irqsave(&s->lock, flags); |
1d65c0b1 | 736 | |
ec063899 | 737 | s->opened[port->line] = 0; |
1d65c0b1 AS |
738 | |
739 | /* Disable interrupts */ | |
740 | sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY); | |
741 | ||
742 | /* Disable TX & RX */ | |
743 | sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); | |
744 | ||
745 | /* Leave direction to input */ | |
ea4c39be | 746 | if (s->chip->flags & SCCNXP_HAVE_IO) |
1d65c0b1 AS |
747 | sccnxp_set_bit(port, DIR_OP, 0); |
748 | ||
ec063899 | 749 | spin_unlock_irqrestore(&s->lock, flags); |
1d65c0b1 AS |
750 | } |
751 | ||
752 | static const char *sccnxp_type(struct uart_port *port) | |
753 | { | |
754 | struct sccnxp_port *s = dev_get_drvdata(port->dev); | |
755 | ||
ea4c39be | 756 | return (port->type == PORT_SC26XX) ? s->chip->name : NULL; |
1d65c0b1 AS |
757 | } |
758 | ||
759 | static void sccnxp_release_port(struct uart_port *port) | |
760 | { | |
761 | /* Do nothing */ | |
762 | } | |
763 | ||
764 | static int sccnxp_request_port(struct uart_port *port) | |
765 | { | |
766 | /* Do nothing */ | |
767 | return 0; | |
768 | } | |
769 | ||
770 | static void sccnxp_config_port(struct uart_port *port, int flags) | |
771 | { | |
772 | if (flags & UART_CONFIG_TYPE) | |
773 | port->type = PORT_SC26XX; | |
774 | } | |
775 | ||
776 | static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s) | |
777 | { | |
778 | if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX)) | |
779 | return 0; | |
780 | if (s->irq == port->irq) | |
781 | return 0; | |
782 | ||
783 | return -EINVAL; | |
784 | } | |
785 | ||
786 | static const struct uart_ops sccnxp_ops = { | |
787 | .tx_empty = sccnxp_tx_empty, | |
788 | .set_mctrl = sccnxp_set_mctrl, | |
789 | .get_mctrl = sccnxp_get_mctrl, | |
790 | .stop_tx = sccnxp_stop_tx, | |
791 | .start_tx = sccnxp_start_tx, | |
792 | .stop_rx = sccnxp_stop_rx, | |
793 | .enable_ms = sccnxp_enable_ms, | |
794 | .break_ctl = sccnxp_break_ctl, | |
795 | .startup = sccnxp_startup, | |
796 | .shutdown = sccnxp_shutdown, | |
797 | .set_termios = sccnxp_set_termios, | |
798 | .type = sccnxp_type, | |
799 | .release_port = sccnxp_release_port, | |
800 | .request_port = sccnxp_request_port, | |
801 | .config_port = sccnxp_config_port, | |
802 | .verify_port = sccnxp_verify_port, | |
803 | }; | |
804 | ||
805 | #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE | |
806 | static void sccnxp_console_putchar(struct uart_port *port, int c) | |
807 | { | |
808 | int tryes = 100000; | |
809 | ||
810 | while (tryes--) { | |
811 | if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) { | |
812 | sccnxp_port_write(port, SCCNXP_THR_REG, c); | |
813 | break; | |
814 | } | |
815 | barrier(); | |
816 | } | |
817 | } | |
818 | ||
819 | static void sccnxp_console_write(struct console *co, const char *c, unsigned n) | |
820 | { | |
821 | struct sccnxp_port *s = (struct sccnxp_port *)co->data; | |
822 | struct uart_port *port = &s->port[co->index]; | |
ec063899 | 823 | unsigned long flags; |
1d65c0b1 | 824 | |
ec063899 | 825 | spin_lock_irqsave(&s->lock, flags); |
1d65c0b1 | 826 | uart_console_write(port, c, n, sccnxp_console_putchar); |
ec063899 | 827 | spin_unlock_irqrestore(&s->lock, flags); |
1d65c0b1 AS |
828 | } |
829 | ||
830 | static int sccnxp_console_setup(struct console *co, char *options) | |
831 | { | |
832 | struct sccnxp_port *s = (struct sccnxp_port *)co->data; | |
833 | struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0]; | |
834 | int baud = 9600, bits = 8, parity = 'n', flow = 'n'; | |
835 | ||
836 | if (options) | |
837 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
838 | ||
839 | return uart_set_options(port, co, baud, parity, bits, flow); | |
840 | } | |
841 | #endif | |
842 | ||
ea4c39be AS |
843 | static const struct platform_device_id sccnxp_id_table[] = { |
844 | { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, }, | |
845 | { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, }, | |
846 | { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, }, | |
847 | { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, }, | |
848 | { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, }, | |
849 | { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, }, | |
850 | { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, }, | |
851 | { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, }, | |
852 | { } | |
853 | }; | |
854 | MODULE_DEVICE_TABLE(platform, sccnxp_id_table); | |
855 | ||
9671f099 | 856 | static int sccnxp_probe(struct platform_device *pdev) |
1d65c0b1 AS |
857 | { |
858 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1d65c0b1 | 859 | struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); |
ea4c39be | 860 | int i, ret, uartclk; |
1d65c0b1 AS |
861 | struct sccnxp_port *s; |
862 | void __iomem *membase; | |
90efa75f | 863 | struct clk *clk; |
1d65c0b1 | 864 | |
e087ab74 AS |
865 | membase = devm_ioremap_resource(&pdev->dev, res); |
866 | if (IS_ERR(membase)) | |
867 | return PTR_ERR(membase); | |
1d65c0b1 | 868 | |
1d65c0b1 AS |
869 | s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL); |
870 | if (!s) { | |
871 | dev_err(&pdev->dev, "Error allocating port structure\n"); | |
872 | return -ENOMEM; | |
873 | } | |
874 | platform_set_drvdata(pdev, s); | |
875 | ||
ec063899 | 876 | spin_lock_init(&s->lock); |
1d65c0b1 | 877 | |
461a8ecb | 878 | s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data; |
1d65c0b1 | 879 | |
e087ab74 AS |
880 | s->regulator = devm_regulator_get(&pdev->dev, "vcc"); |
881 | if (!IS_ERR(s->regulator)) { | |
882 | ret = regulator_enable(s->regulator); | |
883 | if (ret) { | |
884 | dev_err(&pdev->dev, | |
885 | "Failed to enable regulator: %i\n", ret); | |
886 | return ret; | |
887 | } | |
888 | } else if (PTR_ERR(s->regulator) == -EPROBE_DEFER) | |
889 | return -EPROBE_DEFER; | |
890 | ||
90efa75f AS |
891 | clk = devm_clk_get(&pdev->dev, NULL); |
892 | if (IS_ERR(clk)) { | |
893 | if (PTR_ERR(clk) == -EPROBE_DEFER) { | |
894 | ret = -EPROBE_DEFER; | |
895 | goto err_out; | |
896 | } | |
897 | dev_notice(&pdev->dev, "Using default clock frequency\n"); | |
ea4c39be | 898 | uartclk = s->chip->freq_std; |
1d65c0b1 | 899 | } else |
90efa75f AS |
900 | uartclk = clk_get_rate(clk); |
901 | ||
902 | /* Check input frequency */ | |
ea4c39be | 903 | if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) { |
90efa75f AS |
904 | dev_err(&pdev->dev, "Frequency out of bounds\n"); |
905 | ret = -EINVAL; | |
906 | goto err_out; | |
907 | } | |
908 | ||
461a8ecb GKH |
909 | if (pdata) |
910 | memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata)); | |
911 | ||
b786337d | 912 | if (s->pdata.poll_time_us) { |
ec063899 | 913 | dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n", |
b786337d | 914 | s->pdata.poll_time_us); |
ec063899 | 915 | s->poll = 1; |
461a8ecb GKH |
916 | } |
917 | ||
918 | if (!s->poll) { | |
ec063899 AS |
919 | s->irq = platform_get_irq(pdev, 0); |
920 | if (s->irq < 0) { | |
921 | dev_err(&pdev->dev, "Missing irq resource data\n"); | |
922 | ret = -ENXIO; | |
923 | goto err_out; | |
924 | } | |
1d65c0b1 AS |
925 | } |
926 | ||
1d65c0b1 AS |
927 | s->uart.owner = THIS_MODULE; |
928 | s->uart.dev_name = "ttySC"; | |
929 | s->uart.major = SCCNXP_MAJOR; | |
930 | s->uart.minor = SCCNXP_MINOR; | |
ea4c39be | 931 | s->uart.nr = s->chip->nr; |
1d65c0b1 AS |
932 | #ifdef CONFIG_SERIAL_SCCNXP_CONSOLE |
933 | s->uart.cons = &s->console; | |
934 | s->uart.cons->device = uart_console_device; | |
935 | s->uart.cons->write = sccnxp_console_write; | |
936 | s->uart.cons->setup = sccnxp_console_setup; | |
937 | s->uart.cons->flags = CON_PRINTBUFFER; | |
938 | s->uart.cons->index = -1; | |
939 | s->uart.cons->data = s; | |
940 | strcpy(s->uart.cons->name, "ttySC"); | |
941 | #endif | |
942 | ret = uart_register_driver(&s->uart); | |
943 | if (ret) { | |
944 | dev_err(&pdev->dev, "Registering UART driver failed\n"); | |
945 | goto err_out; | |
946 | } | |
947 | ||
948 | for (i = 0; i < s->uart.nr; i++) { | |
949 | s->port[i].line = i; | |
950 | s->port[i].dev = &pdev->dev; | |
951 | s->port[i].irq = s->irq; | |
952 | s->port[i].type = PORT_SC26XX; | |
ea4c39be | 953 | s->port[i].fifosize = s->chip->fifosize; |
1d65c0b1 AS |
954 | s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; |
955 | s->port[i].iotype = UPIO_MEM; | |
956 | s->port[i].mapbase = res->start; | |
957 | s->port[i].membase = membase; | |
958 | s->port[i].regshift = s->pdata.reg_shift; | |
90efa75f | 959 | s->port[i].uartclk = uartclk; |
1d65c0b1 AS |
960 | s->port[i].ops = &sccnxp_ops; |
961 | uart_add_one_port(&s->uart, &s->port[i]); | |
962 | /* Set direction to input */ | |
ea4c39be | 963 | if (s->chip->flags & SCCNXP_HAVE_IO) |
1d65c0b1 AS |
964 | sccnxp_set_bit(&s->port[i], DIR_OP, 0); |
965 | } | |
966 | ||
967 | /* Disable interrupts */ | |
968 | s->imr = 0; | |
969 | sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0); | |
970 | ||
ec063899 AS |
971 | if (!s->poll) { |
972 | ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL, | |
973 | sccnxp_ist, | |
974 | IRQF_TRIGGER_FALLING | | |
975 | IRQF_ONESHOT, | |
976 | dev_name(&pdev->dev), s); | |
977 | if (!ret) | |
978 | return 0; | |
979 | ||
980 | dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq); | |
981 | } else { | |
982 | init_timer(&s->timer); | |
983 | setup_timer(&s->timer, sccnxp_timer, (unsigned long)s); | |
984 | mod_timer(&s->timer, jiffies + | |
985 | usecs_to_jiffies(s->pdata.poll_time_us)); | |
1d65c0b1 | 986 | return 0; |
ec063899 | 987 | } |
1d65c0b1 | 988 | |
7a95b815 | 989 | uart_unregister_driver(&s->uart); |
1d65c0b1 | 990 | err_out: |
e087ab74 AS |
991 | if (!IS_ERR(s->regulator)) |
992 | return regulator_disable(s->regulator); | |
993 | ||
1d65c0b1 AS |
994 | return ret; |
995 | } | |
996 | ||
ae8d8a14 | 997 | static int sccnxp_remove(struct platform_device *pdev) |
1d65c0b1 AS |
998 | { |
999 | int i; | |
1000 | struct sccnxp_port *s = platform_get_drvdata(pdev); | |
1001 | ||
ec063899 AS |
1002 | if (!s->poll) |
1003 | devm_free_irq(&pdev->dev, s->irq, s); | |
1004 | else | |
1005 | del_timer_sync(&s->timer); | |
1d65c0b1 AS |
1006 | |
1007 | for (i = 0; i < s->uart.nr; i++) | |
1008 | uart_remove_one_port(&s->uart, &s->port[i]); | |
1009 | ||
1010 | uart_unregister_driver(&s->uart); | |
1d65c0b1 | 1011 | |
31815c08 AS |
1012 | if (!IS_ERR(s->regulator)) |
1013 | return regulator_disable(s->regulator); | |
1d65c0b1 AS |
1014 | |
1015 | return 0; | |
1016 | } | |
1017 | ||
1d65c0b1 AS |
1018 | static struct platform_driver sccnxp_uart_driver = { |
1019 | .driver = { | |
461a8ecb GKH |
1020 | .name = SCCNXP_NAME, |
1021 | .owner = THIS_MODULE, | |
1d65c0b1 AS |
1022 | }, |
1023 | .probe = sccnxp_probe, | |
2d47b716 | 1024 | .remove = sccnxp_remove, |
1d65c0b1 AS |
1025 | .id_table = sccnxp_id_table, |
1026 | }; | |
1027 | module_platform_driver(sccnxp_uart_driver); | |
1028 | ||
1029 | MODULE_LICENSE("GPL v2"); | |
1030 | MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); | |
1031 | MODULE_DESCRIPTION("SCCNXP serial driver"); |