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1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
f4998e55 5 * Copyright (C) 2015 Glider bvba
3ea6bc3d 6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 15 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
0b3d4ef6
PM		 21#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
1da177e4
LT		 24
25#undef DEBUG
26
8fb9631c
LP		 27#include <linux/clk.h>
28#include <linux/console.h>
29#include <linux/ctype.h>
30#include <linux/cpufreq.h>
31#include <linux/delay.h>
32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/err.h>
1da177e4 35#include <linux/errno.h>
8fb9631c 36#include <linux/init.h>
1da177e4 37#include <linux/interrupt.h>
1da177e4 38#include <linux/ioport.h>
8fb9631c
LP		 39#include <linux/major.h>
40#include <linux/module.h>
1da177e4 41#include <linux/mm.h>
20bdcab8 42#include <linux/of.h>
6e605a01 43#include <linux/of_device.h>
8fb9631c 44#include <linux/platform_device.h>
5e50d2d6 45#include <linux/pm_runtime.h>
73a19e4c 46#include <linux/scatterlist.h>
8fb9631c
LP		 47#include <linux/serial.h>
48#include <linux/serial_sci.h>
49#include <linux/sh_dma.h>
5a0e3ad6 50#include <linux/slab.h>
8fb9631c
LP		 51#include <linux/string.h>
52#include <linux/sysrq.h>
53#include <linux/timer.h>
54#include <linux/tty.h>
55#include <linux/tty_flip.h>
85f094ec
PM		 56
57#ifdef CONFIG_SUPERH
1da177e4
LT		 58#include <asm/sh_bios.h>
59#endif
60
f907c9ea 61#include "serial_mctrl_gpio.h"
1da177e4
LT		 62#include "sh-sci.h"
63
89b5c1ab
LP		 64/* Offsets into the sci_port->irqs array */
65enum {
66 SCIx_ERI_IRQ,
67 SCIx_RXI_IRQ,
68 SCIx_TXI_IRQ,
69 SCIx_BRI_IRQ,
70 SCIx_NR_IRQS,
71
72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73};
74
75#define SCIx_IRQ_IS_MUXED(port) \
76 ((port)->irqs[SCIx_ERI_IRQ] == \
77 (port)->irqs[SCIx_RXI_IRQ]) || \
78 ((port)->irqs[SCIx_ERI_IRQ] && \
79 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80
f4998e55
GU		 81enum SCI_CLKS {
82 SCI_FCK, /* Functional Clock */
6af27bf2 83 SCI_SCK, /* Optional External Clock */
1270f865
GU		 84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
f4998e55
GU		 86 SCI_NUM_CLKS
87};
88
69eee8e9
GU		 89/* Bit x set means sampling rate x + 1 is supported */
90#define SCI_SR(x) BIT((x) - 1)
91#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92
92a05748
GU		 93#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
95 SCI_SR(19) | SCI_SR(27)
96
69eee8e9
GU		 97#define min_sr(_port) ffs((_port)->sampling_rate_mask)
98#define max_sr(_port) fls((_port)->sampling_rate_mask)
99
100/* Iterate over all supported sampling rates, from high to low */
101#define for_each_sr(_sr, _port) \
102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
103 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104
e095ee6b
LP		 105struct plat_sci_reg {
106 u8 offset, size;
107};
108
109struct sci_port_params {
110 const struct plat_sci_reg regs[SCIx_NR_REGS];
b2f20ed9
LP		 111 unsigned int fifosize;
112 unsigned int overrun_reg;
113 unsigned int overrun_mask;
114 unsigned int sampling_rate_mask;
115 unsigned int error_mask;
116 unsigned int error_clear;
e095ee6b
LP		 117};
118
e108b2ca
PM		 119struct sci_port {
120 struct uart_port port;
121
ce6738b6 122 /* Platform configuration */
e095ee6b 123 const struct sci_port_params *params;
daf5a895 124 const struct plat_sci_port *cfg;
69eee8e9 125 unsigned int sampling_rate_mask;
e4d6f911 126 resource_size_t reg_size;
f907c9ea 127 struct mctrl_gpios *gpios;
e108b2ca 128
f4998e55
GU		 129 /* Clocks */
130 struct clk *clks[SCI_NUM_CLKS];
131 unsigned long clk_rates[SCI_NUM_CLKS];
edad1f20 132
1fcc91a6 133 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 134 char *irqstr[SCIx_NR_IRQS];
135
73a19e4c
GL		 136 struct dma_chan *chan_tx;
137 struct dma_chan *chan_rx;
f43dc23d 138
73a19e4c 139#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 140 dma_cookie_t cookie_tx;
141 dma_cookie_t cookie_rx[2];
142 dma_cookie_t active_rx;
79904420
GU		 143 dma_addr_t tx_dma_addr;
144 unsigned int tx_dma_len;
73a19e4c 145 struct scatterlist sg_rx[2];
7b39d901 146 void *rx_buf[2];
73a19e4c 147 size_t buf_len_rx;
73a19e4c 148 struct work_struct work_tx;
73a19e4c 149 struct timer_list rx_timer;
3089f381 150 unsigned int rx_timeout;
73a19e4c 151#endif
03940376 152 unsigned int rx_frame;
18e8cf15 153 int rx_trigger;
03940376
UH		 154 struct timer_list rx_fifo_timer;
155 int rx_fifo_timeout;
fa2abb03 156 u16 hscif_tot;
33f50ffc 157
97ed9790 158 bool has_rtscts;
33f50ffc 159 bool autorts;
e108b2ca
PM		 160};
161
e108b2ca 162#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 163
e108b2ca
PM		 164static struct sci_port sci_ports[SCI_NPORTS];
165static struct uart_driver sci_uart_driver;
1da177e4 166
e7c98dc7
MT		 167static inline struct sci_port *
168to_sci_port(struct uart_port *uart)
169{
170 return container_of(uart, struct sci_port, port);
171}
172
e095ee6b 173static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
61a6976b
PM		 174 /*
175 * Common SCI definitions, dependent on the port's regshift
176 * value.
177 */
178 [SCIx_SCI_REGTYPE] = {
e095ee6b
LP		 179 .regs = {
180 [SCSMR] = { 0x00, 8 },
181 [SCBRR] = { 0x01, 8 },
182 [SCSCR] = { 0x02, 8 },
183 [SCxTDR] = { 0x03, 8 },
184 [SCxSR] = { 0x04, 8 },
185 [SCxRDR] = { 0x05, 8 },
186 },
b2f20ed9
LP		 187 .fifosize = 1,
188 .overrun_reg = SCxSR,
189 .overrun_mask = SCI_ORER,
190 .sampling_rate_mask = SCI_SR(32),
191 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
192 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 193 },
194
195 /*
a752ba18 196 * Common definitions for legacy IrDA ports.
61a6976b
PM		 197 */
198 [SCIx_IRDA_REGTYPE] = {
e095ee6b
LP		 199 .regs = {
200 [SCSMR] = { 0x00, 8 },
201 [SCBRR] = { 0x02, 8 },
202 [SCSCR] = { 0x04, 8 },
203 [SCxTDR] = { 0x06, 8 },
204 [SCxSR] = { 0x08, 16 },
205 [SCxRDR] = { 0x0a, 8 },
206 [SCFCR] = { 0x0c, 8 },
207 [SCFDR] = { 0x0e, 16 },
208 },
b2f20ed9
LP		 209 .fifosize = 1,
210 .overrun_reg = SCxSR,
211 .overrun_mask = SCI_ORER,
212 .sampling_rate_mask = SCI_SR(32),
213 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
214 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 215 },
216
217 /*
218 * Common SCIFA definitions.
219 */
220 [SCIx_SCIFA_REGTYPE] = {
e095ee6b
LP		 221 .regs = {
222 [SCSMR] = { 0x00, 16 },
223 [SCBRR] = { 0x04, 8 },
224 [SCSCR] = { 0x08, 16 },
225 [SCxTDR] = { 0x20, 8 },
226 [SCxSR] = { 0x14, 16 },
227 [SCxRDR] = { 0x24, 8 },
228 [SCFCR] = { 0x18, 16 },
229 [SCFDR] = { 0x1c, 16 },
230 [SCPCR] = { 0x30, 16 },
231 [SCPDR] = { 0x34, 16 },
232 },
b2f20ed9
LP		 233 .fifosize = 64,
234 .overrun_reg = SCxSR,
235 .overrun_mask = SCIFA_ORER,
236 .sampling_rate_mask = SCI_SR_SCIFAB,
237 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
238 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 239 },
240
241 /*
242 * Common SCIFB definitions.
243 */
244 [SCIx_SCIFB_REGTYPE] = {
e095ee6b
LP		 245 .regs = {
246 [SCSMR] = { 0x00, 16 },
247 [SCBRR] = { 0x04, 8 },
248 [SCSCR] = { 0x08, 16 },
249 [SCxTDR] = { 0x40, 8 },
250 [SCxSR] = { 0x14, 16 },
251 [SCxRDR] = { 0x60, 8 },
252 [SCFCR] = { 0x18, 16 },
253 [SCTFDR] = { 0x38, 16 },
254 [SCRFDR] = { 0x3c, 16 },
255 [SCPCR] = { 0x30, 16 },
256 [SCPDR] = { 0x34, 16 },
257 },
b2f20ed9
LP		 258 .fifosize = 256,
259 .overrun_reg = SCxSR,
260 .overrun_mask = SCIFA_ORER,
261 .sampling_rate_mask = SCI_SR_SCIFAB,
262 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
263 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 264 },
265
3af1f8a4
PE		 266 /*
267 * Common SH-2(A) SCIF definitions for ports with FIFO data
268 * count registers.
269 */
270 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 271 .regs = {
272 [SCSMR] = { 0x00, 16 },
273 [SCBRR] = { 0x04, 8 },
274 [SCSCR] = { 0x08, 16 },
275 [SCxTDR] = { 0x0c, 8 },
276 [SCxSR] = { 0x10, 16 },
277 [SCxRDR] = { 0x14, 8 },
278 [SCFCR] = { 0x18, 16 },
279 [SCFDR] = { 0x1c, 16 },
280 [SCSPTR] = { 0x20, 16 },
281 [SCLSR] = { 0x24, 16 },
282 },
b2f20ed9
LP		 283 .fifosize = 16,
284 .overrun_reg = SCLSR,
285 .overrun_mask = SCLSR_ORER,
286 .sampling_rate_mask = SCI_SR(32),
287 .error_mask = SCIF_DEFAULT_ERROR_MASK,
288 .error_clear = SCIF_ERROR_CLEAR,
3af1f8a4
PE		 289 },
290
61a6976b
PM		 291 /*
292 * Common SH-3 SCIF definitions.
293 */
294 [SCIx_SH3_SCIF_REGTYPE] = {
e095ee6b
LP		 295 .regs = {
296 [SCSMR] = { 0x00, 8 },
297 [SCBRR] = { 0x02, 8 },
298 [SCSCR] = { 0x04, 8 },
299 [SCxTDR] = { 0x06, 8 },
300 [SCxSR] = { 0x08, 16 },
301 [SCxRDR] = { 0x0a, 8 },
302 [SCFCR] = { 0x0c, 8 },
303 [SCFDR] = { 0x0e, 16 },
304 },
b2f20ed9
LP		 305 .fifosize = 16,
306 .overrun_reg = SCLSR,
307 .overrun_mask = SCLSR_ORER,
308 .sampling_rate_mask = SCI_SR(32),
309 .error_mask = SCIF_DEFAULT_ERROR_MASK,
310 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 311 },
312
313 /*
314 * Common SH-4(A) SCIF(B) definitions.
315 */
316 [SCIx_SH4_SCIF_REGTYPE] = {
e095ee6b
LP		 317 .regs = {
318 [SCSMR] = { 0x00, 16 },
319 [SCBRR] = { 0x04, 8 },
320 [SCSCR] = { 0x08, 16 },
321 [SCxTDR] = { 0x0c, 8 },
322 [SCxSR] = { 0x10, 16 },
323 [SCxRDR] = { 0x14, 8 },
324 [SCFCR] = { 0x18, 16 },
325 [SCFDR] = { 0x1c, 16 },
326 [SCSPTR] = { 0x20, 16 },
327 [SCLSR] = { 0x24, 16 },
328 },
b2f20ed9
LP		 329 .fifosize = 16,
330 .overrun_reg = SCLSR,
331 .overrun_mask = SCLSR_ORER,
332 .sampling_rate_mask = SCI_SR(32),
333 .error_mask = SCIF_DEFAULT_ERROR_MASK,
334 .error_clear = SCIF_ERROR_CLEAR,
b8bbd6b2
GU		 335 },
336
337 /*
338 * Common SCIF definitions for ports with a Baud Rate Generator for
339 * External Clock (BRG).
340 */
341 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
e095ee6b
LP		 342 .regs = {
343 [SCSMR] = { 0x00, 16 },
344 [SCBRR] = { 0x04, 8 },
345 [SCSCR] = { 0x08, 16 },
346 [SCxTDR] = { 0x0c, 8 },
347 [SCxSR] = { 0x10, 16 },
348 [SCxRDR] = { 0x14, 8 },
349 [SCFCR] = { 0x18, 16 },
350 [SCFDR] = { 0x1c, 16 },
351 [SCSPTR] = { 0x20, 16 },
352 [SCLSR] = { 0x24, 16 },
353 [SCDL] = { 0x30, 16 },
354 [SCCKS] = { 0x34, 16 },
355 },
b2f20ed9
LP		 356 .fifosize = 16,
357 .overrun_reg = SCLSR,
358 .overrun_mask = SCLSR_ORER,
359 .sampling_rate_mask = SCI_SR(32),
360 .error_mask = SCIF_DEFAULT_ERROR_MASK,
361 .error_clear = SCIF_ERROR_CLEAR,
f303b364
UH		 362 },
363
364 /*
365 * Common HSCIF definitions.
366 */
367 [SCIx_HSCIF_REGTYPE] = {
e095ee6b
LP		 368 .regs = {
369 [SCSMR] = { 0x00, 16 },
370 [SCBRR] = { 0x04, 8 },
371 [SCSCR] = { 0x08, 16 },
372 [SCxTDR] = { 0x0c, 8 },
373 [SCxSR] = { 0x10, 16 },
374 [SCxRDR] = { 0x14, 8 },
375 [SCFCR] = { 0x18, 16 },
376 [SCFDR] = { 0x1c, 16 },
377 [SCSPTR] = { 0x20, 16 },
378 [SCLSR] = { 0x24, 16 },
379 [HSSRR] = { 0x40, 16 },
380 [SCDL] = { 0x30, 16 },
381 [SCCKS] = { 0x34, 16 },
54e14ae2
UH		 382 [HSRTRGR] = { 0x54, 16 },
383 [HSTTRGR] = { 0x58, 16 },
e095ee6b 384 },
b2f20ed9
LP		 385 .fifosize = 128,
386 .overrun_reg = SCLSR,
387 .overrun_mask = SCLSR_ORER,
388 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
389 .error_mask = SCIF_DEFAULT_ERROR_MASK,
390 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 391 },
392
393 /*
394 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
395 * register.
396 */
397 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
e095ee6b
LP		 398 .regs = {
399 [SCSMR] = { 0x00, 16 },
400 [SCBRR] = { 0x04, 8 },
401 [SCSCR] = { 0x08, 16 },
402 [SCxTDR] = { 0x0c, 8 },
403 [SCxSR] = { 0x10, 16 },
404 [SCxRDR] = { 0x14, 8 },
405 [SCFCR] = { 0x18, 16 },
406 [SCFDR] = { 0x1c, 16 },
407 [SCLSR] = { 0x24, 16 },
408 },
b2f20ed9
LP		 409 .fifosize = 16,
410 .overrun_reg = SCLSR,
411 .overrun_mask = SCLSR_ORER,
412 .sampling_rate_mask = SCI_SR(32),
413 .error_mask = SCIF_DEFAULT_ERROR_MASK,
414 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 415 },
416
417 /*
418 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
419 * count registers.
420 */
421 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 422 .regs = {
423 [SCSMR] = { 0x00, 16 },
424 [SCBRR] = { 0x04, 8 },
425 [SCSCR] = { 0x08, 16 },
426 [SCxTDR] = { 0x0c, 8 },
427 [SCxSR] = { 0x10, 16 },
428 [SCxRDR] = { 0x14, 8 },
429 [SCFCR] = { 0x18, 16 },
430 [SCFDR] = { 0x1c, 16 },
431 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
432 [SCRFDR] = { 0x20, 16 },
433 [SCSPTR] = { 0x24, 16 },
434 [SCLSR] = { 0x28, 16 },
435 },
b2f20ed9
LP		 436 .fifosize = 16,
437 .overrun_reg = SCLSR,
438 .overrun_mask = SCLSR_ORER,
439 .sampling_rate_mask = SCI_SR(32),
440 .error_mask = SCIF_DEFAULT_ERROR_MASK,
441 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 442 },
443
444 /*
445 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
446 * registers.
447 */
448 [SCIx_SH7705_SCIF_REGTYPE] = {
e095ee6b
LP		 449 .regs = {
450 [SCSMR] = { 0x00, 16 },
451 [SCBRR] = { 0x04, 8 },
452 [SCSCR] = { 0x08, 16 },
453 [SCxTDR] = { 0x20, 8 },
454 [SCxSR] = { 0x14, 16 },
455 [SCxRDR] = { 0x24, 8 },
456 [SCFCR] = { 0x18, 16 },
457 [SCFDR] = { 0x1c, 16 },
458 },
18e8cf15 459 .fifosize = 64,
b2f20ed9
LP		 460 .overrun_reg = SCxSR,
461 .overrun_mask = SCIFA_ORER,
462 .sampling_rate_mask = SCI_SR(16),
463 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
464 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 465 },
466};
467
e095ee6b 468#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
72b294cf 469
61a6976b
PM		 470/*
471 * The "offset" here is rather misleading, in that it refers to an enum
472 * value relative to the port mapping rather than the fixed offset
473 * itself, which needs to be manually retrieved from the platform's
474 * register map for the given port.
475 */
476static unsigned int sci_serial_in(struct uart_port *p, int offset)
477{
d3184e68 478 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 479
480 if (reg->size == 8)
481 return ioread8(p->membase + (reg->offset << p->regshift));
482 else if (reg->size == 16)
483 return ioread16(p->membase + (reg->offset << p->regshift));
484 else
485 WARN(1, "Invalid register access\n");
486
487 return 0;
488}
489
490static void sci_serial_out(struct uart_port *p, int offset, int value)
491{
d3184e68 492 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 493
494 if (reg->size == 8)
495 iowrite8(value, p->membase + (reg->offset << p->regshift));
496 else if (reg->size == 16)
497 iowrite16(value, p->membase + (reg->offset << p->regshift));
498 else
499 WARN(1, "Invalid register access\n");
500}
501
23241d43
PM		 502static void sci_port_enable(struct sci_port *sci_port)
503{
f4998e55
GU		 504 unsigned int i;
505
23241d43
PM		 506 if (!sci_port->port.dev)
507 return;
508
509 pm_runtime_get_sync(sci_port->port.dev);
510
f4998e55
GU		 511 for (i = 0; i < SCI_NUM_CLKS; i++) {
512 clk_prepare_enable(sci_port->clks[i]);
513 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
514 }
515 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
23241d43
PM		 516}
517
518static void sci_port_disable(struct sci_port *sci_port)
519{
f4998e55
GU		 520 unsigned int i;
521
23241d43
PM		 522 if (!sci_port->port.dev)
523 return;
524
f4998e55
GU		 525 for (i = SCI_NUM_CLKS; i-- > 0; )
526 clk_disable_unprepare(sci_port->clks[i]);
23241d43
PM		 527
528 pm_runtime_put_sync(sci_port->port.dev);
529}
530
e1910fcd
GU		 531static inline unsigned long port_rx_irq_mask(struct uart_port *port)
532{
533 /*
534 * Not all ports (such as SCIFA) will support REIE. Rather than
535 * special-casing the port type, we check the port initialization
536 * IRQ enable mask to see whether the IRQ is desired at all. If
537 * it's unset, it's logically inferred that there's no point in
538 * testing for it.
539 */
540 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
541}
542
543static void sci_start_tx(struct uart_port *port)
544{
545 struct sci_port *s = to_sci_port(port);
546 unsigned short ctrl;
547
548#ifdef CONFIG_SERIAL_SH_SCI_DMA
549 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
550 u16 new, scr = serial_port_in(port, SCSCR);
551 if (s->chan_tx)
552 new = scr | SCSCR_TDRQE;
553 else
554 new = scr & ~SCSCR_TDRQE;
555 if (new != scr)
556 serial_port_out(port, SCSCR, new);
557 }
558
559 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
560 dma_submit_error(s->cookie_tx)) {
561 s->cookie_tx = 0;
562 schedule_work(&s->work_tx);
563 }
564#endif
565
566 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
567 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
568 ctrl = serial_port_in(port, SCSCR);
569 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
570 }
571}
572
573static void sci_stop_tx(struct uart_port *port)
574{
575 unsigned short ctrl;
576
577 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
578 ctrl = serial_port_in(port, SCSCR);
579
580 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
581 ctrl &= ~SCSCR_TDRQE;
582
583 ctrl &= ~SCSCR_TIE;
584
585 serial_port_out(port, SCSCR, ctrl);
586}
587
588static void sci_start_rx(struct uart_port *port)
589{
590 unsigned short ctrl;
591
592 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
593
594 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
595 ctrl &= ~SCSCR_RDRQE;
596
597 serial_port_out(port, SCSCR, ctrl);
598}
599
600static void sci_stop_rx(struct uart_port *port)
601{
602 unsigned short ctrl;
603
604 ctrl = serial_port_in(port, SCSCR);
605
606 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
607 ctrl &= ~SCSCR_RDRQE;
608
609 ctrl &= ~port_rx_irq_mask(port);
610
611 serial_port_out(port, SCSCR, ctrl);
612}
613
a1b5b43f
GU		 614static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
615{
616 if (port->type == PORT_SCI) {
617 /* Just store the mask */
618 serial_port_out(port, SCxSR, mask);
b2f20ed9 619 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
a1b5b43f
GU		 620 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
621 /* Only clear the status bits we want to clear */
622 serial_port_out(port, SCxSR,
623 serial_port_in(port, SCxSR) & mask);
624 } else {
625 /* Store the mask, clear parity/framing errors */
626 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
627 }
628}
629
0b0cced1
YS		 630#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
631 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
1f6fd5c9
PM		 632
633#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 634static int sci_poll_get_char(struct uart_port *port)
1da177e4 635{
1da177e4
LT		 636 unsigned short status;
637 int c;
638
e108b2ca 639 do {
b12bb29f 640 status = serial_port_in(port, SCxSR);
1da177e4 641 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 642 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 643 continue;
644 }
3f255eb3
JW		 645 break;
646 } while (1);
647
648 if (!(status & SCxSR_RDxF(port)))
649 return NO_POLL_CHAR;
07d2a1a1 650
b12bb29f 651 c = serial_port_in(port, SCxRDR);
07d2a1a1 652
e7c98dc7 653 /* Dummy read */
b12bb29f 654 serial_port_in(port, SCxSR);
a1b5b43f 655 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 656
657 return c;
658}
1f6fd5c9 659#endif
1da177e4 660
07d2a1a1 661static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 662{
1da177e4
LT		 663 unsigned short status;
664
1da177e4 665 do {
b12bb29f 666 status = serial_port_in(port, SCxSR);
1da177e4
LT		 667 } while (!(status & SCxSR_TDxE(port)));
668
b12bb29f 669 serial_port_out(port, SCxTDR, c);
a1b5b43f 670 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 671}
0b0cced1
YS		 672#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
673 CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 674
61a6976b 675static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 676{
61a6976b 677 struct sci_port *s = to_sci_port(port);
1da177e4 678
61a6976b
PM		 679 /*
680 * Use port-specific handler if provided.
681 */
682 if (s->cfg->ops && s->cfg->ops->init_pins) {
683 s->cfg->ops->init_pins(port, cflag);
684 return;
1da177e4 685 }
41504c39 686
e9d7a45a 687 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
cfa6eb23 688 u16 data = serial_port_in(port, SCPDR);
e9d7a45a
GU		 689 u16 ctrl = serial_port_in(port, SCPCR);
690
691 /* Enable RXD and TXD pin functions */
692 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
97ed9790 693 if (to_sci_port(port)->has_rtscts) {
cfa6eb23
GU		 694 /* RTS# is output, active low, unless autorts */
695 if (!(port->mctrl & TIOCM_RTS)) {
696 ctrl |= SCPCR_RTSC;
697 data |= SCPDR_RTSD;
698 } else if (!s->autorts) {
699 ctrl |= SCPCR_RTSC;
700 data &= ~SCPDR_RTSD;
701 } else {
702 /* Enable RTS# pin function */
703 ctrl &= ~SCPCR_RTSC;
704 }
e9d7a45a
GU		 705 /* Enable CTS# pin function */
706 ctrl &= ~SCPCR_CTSC;
707 }
cfa6eb23 708 serial_port_out(port, SCPDR, data);
e9d7a45a
GU		 709 serial_port_out(port, SCPCR, ctrl);
710 } else if (sci_getreg(port, SCSPTR)->size) {
d2b9775d
GU		 711 u16 status = serial_port_in(port, SCSPTR);
712
cfa6eb23
GU		 713 /* RTS# is always output; and active low, unless autorts */
714 status |= SCSPTR_RTSIO;
715 if (!(port->mctrl & TIOCM_RTS))
716 status |= SCSPTR_RTSDT;
717 else if (!s->autorts)
718 status &= ~SCSPTR_RTSDT;
d2b9775d
GU		 719 /* CTS# and SCK are inputs */
720 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
721 serial_port_out(port, SCSPTR, status);
faf02f8f 722 }
d5701647 723}
e108b2ca 724
72b294cf 725static int sci_txfill(struct uart_port *port)
e108b2ca 726{
b2f20ed9
LP		 727 struct sci_port *s = to_sci_port(port);
728 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 729 const struct plat_sci_reg *reg;
e108b2ca 730
72b294cf
PM		 731 reg = sci_getreg(port, SCTFDR);
732 if (reg->size)
b2f20ed9 733 return serial_port_in(port, SCTFDR) & fifo_mask;
c63847a3 734
72b294cf
PM		 735 reg = sci_getreg(port, SCFDR);
736 if (reg->size)
b12bb29f 737 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 738
b12bb29f 739 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 740}
741
73a19e4c
GL		 742static int sci_txroom(struct uart_port *port)
743{
72b294cf 744 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 745}
746
747static int sci_rxfill(struct uart_port *port)
e108b2ca 748{
b2f20ed9
LP		 749 struct sci_port *s = to_sci_port(port);
750 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 751 const struct plat_sci_reg *reg;
72b294cf
PM		 752
753 reg = sci_getreg(port, SCRFDR);
754 if (reg->size)
b2f20ed9 755 return serial_port_in(port, SCRFDR) & fifo_mask;
72b294cf
PM		 756
757 reg = sci_getreg(port, SCFDR);
758 if (reg->size)
b2f20ed9 759 return serial_port_in(port, SCFDR) & fifo_mask;
72b294cf 760
b12bb29f 761 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 762}
763
1da177e4
LT		 764/* ********************************************************************** *
765 * the interrupt related routines *
766 * ********************************************************************** */
767
768static void sci_transmit_chars(struct uart_port *port)
769{
ebd2c8f6 770 struct circ_buf *xmit = &port->state->xmit;
1da177e4 771 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 772 unsigned short status;
773 unsigned short ctrl;
e108b2ca 774 int count;
1da177e4 775
b12bb29f 776 status = serial_port_in(port, SCxSR);
1da177e4 777 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 778 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 779 if (uart_circ_empty(xmit))
8e698614 780 ctrl &= ~SCSCR_TIE;
e7c98dc7 781 else
8e698614 782 ctrl |= SCSCR_TIE;
b12bb29f 783 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 784 return;
785 }
786
72b294cf 787 count = sci_txroom(port);
1da177e4
LT		 788
789 do {
790 unsigned char c;
791
792 if (port->x_char) {
793 c = port->x_char;
794 port->x_char = 0;
795 } else if (!uart_circ_empty(xmit) && !stopped) {
796 c = xmit->buf[xmit->tail];
797 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
798 } else {
799 break;
800 }
801
b12bb29f 802 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 803
804 port->icount.tx++;
805 } while (--count > 0);
806
a1b5b43f 807 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 808
809 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
810 uart_write_wakeup(port);
811 if (uart_circ_empty(xmit)) {
b129a8cc 812 sci_stop_tx(port);
1da177e4 813 } else {
b12bb29f 814 ctrl = serial_port_in(port, SCSCR);
1da177e4 815
1a22f08d 816 if (port->type != PORT_SCI) {
b12bb29f 817 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 818 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 819 }
1da177e4 820
8e698614 821 ctrl |= SCSCR_TIE;
b12bb29f 822 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 823 }
824}
825
826/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 827#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 828
94c8b6db 829static void sci_receive_chars(struct uart_port *port)
1da177e4 830{
227434f8 831 struct tty_port *tport = &port->state->port;
1da177e4
LT		 832 int i, count, copied = 0;
833 unsigned short status;
33f0f88f 834 unsigned char flag;
1da177e4 835
b12bb29f 836 status = serial_port_in(port, SCxSR);
1da177e4
LT		 837 if (!(status & SCxSR_RDxF(port)))
838 return;
839
840 while (1) {
1da177e4 841 /* Don't copy more bytes than there is room for in the buffer */
227434f8 842 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 843
844 /* If for any reason we can't copy more data, we're done! */
845 if (count == 0)
846 break;
847
848 if (port->type == PORT_SCI) {
b12bb29f 849 char c = serial_port_in(port, SCxRDR);
d5cb1319 850 if (uart_handle_sysrq_char(port, c))
1da177e4 851 count = 0;
e7c98dc7 852 else
92a19f9c 853 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 854 } else {
e7c98dc7 855 for (i = 0; i < count; i++) {
b12bb29f 856 char c = serial_port_in(port, SCxRDR);
d97fbbed 857
b12bb29f 858 status = serial_port_in(port, SCxSR);
7d12e780 859 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 860 count--; i--;
861 continue;
862 }
863
864 /* Store data and status */
73a19e4c 865 if (status & SCxSR_FER(port)) {
33f0f88f 866 flag = TTY_FRAME;
d97fbbed 867 port->icount.frame++;
762c69e3 868 dev_notice(port->dev, "frame error\n");
73a19e4c 869 } else if (status & SCxSR_PER(port)) {
33f0f88f 870 flag = TTY_PARITY;
d97fbbed 871 port->icount.parity++;
762c69e3 872 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 873 } else
874 flag = TTY_NORMAL;
762c69e3 875
92a19f9c 876 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 877 }
878 }
879
b12bb29f 880 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 881 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 882
1da177e4
LT		 883 copied += count;
884 port->icount.rx += count;
885 }
886
887 if (copied) {
888 /* Tell the rest of the system the news. New characters! */
2e124b4a 889 tty_flip_buffer_push(tport);
1da177e4 890 } else {
b12bb29f 891 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 892 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 893 }
894}
895
94c8b6db 896static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 897{
898 int copied = 0;
b12bb29f 899 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 900 struct tty_port *tport = &port->state->port;
debf9507 901 struct sci_port *s = to_sci_port(port);
1da177e4 902
3ae988d9 903 /* Handle overruns */
b2f20ed9 904 if (status & s->params->overrun_mask) {
3ae988d9 905 port->icount.overrun++;
d97fbbed 906
3ae988d9
LP		 907 /* overrun error */
908 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
909 copied++;
762c69e3 910
9b971cd2 911 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 912 }
913
e108b2ca 914 if (status & SCxSR_FER(port)) {
d5cb1319
LP		 915 /* frame error */
916 port->icount.frame++;
d97fbbed 917
d5cb1319
LP		 918 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
919 copied++;
762c69e3 920
d5cb1319 921 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 922 }
923
e108b2ca 924 if (status & SCxSR_PER(port)) {
1da177e4 925 /* parity error */
d97fbbed
PM		 926 port->icount.parity++;
927
92a19f9c 928 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 929 copied++;
762c69e3 930
9b971cd2 931 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 932 }
933
33f0f88f 934 if (copied)
2e124b4a 935 tty_flip_buffer_push(tport);
1da177e4
LT		 936
937 return copied;
938}
939
94c8b6db 940static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 941{
92a19f9c 942 struct tty_port *tport = &port->state->port;
debf9507 943 struct sci_port *s = to_sci_port(port);
d3184e68 944 const struct plat_sci_reg *reg;
2e0842a1 945 int copied = 0;
75c249fd 946 u16 status;
d830fa45 947
b2f20ed9 948 reg = sci_getreg(port, s->params->overrun_reg);
4b8c59a3 949 if (!reg->size)
d830fa45
PM		 950 return 0;
951
b2f20ed9
LP		 952 status = serial_port_in(port, s->params->overrun_reg);
953 if (status & s->params->overrun_mask) {
954 status &= ~s->params->overrun_mask;
955 serial_port_out(port, s->params->overrun_reg, status);
d830fa45 956
d97fbbed
PM		 957 port->icount.overrun++;
958
92a19f9c 959 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 960 tty_flip_buffer_push(tport);
d830fa45 961
51b31f1c 962 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 963 copied++;
964 }
965
966 return copied;
967}
968
94c8b6db 969static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 970{
971 int copied = 0;
b12bb29f 972 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 973 struct tty_port *tport = &port->state->port;
1da177e4 974
0b3d4ef6
PM		 975 if (uart_handle_break(port))
976 return 0;
977
d5cb1319 978 if (status & SCxSR_BRK(port)) {
d97fbbed
PM		 979 port->icount.brk++;
980
1da177e4 981 /* Notify of BREAK */
92a19f9c 982 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 983 copied++;
762c69e3
PM		 984
985 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 986 }
987
33f0f88f 988 if (copied)
2e124b4a 989 tty_flip_buffer_push(tport);
e108b2ca 990
d830fa45
PM		 991 copied += sci_handle_fifo_overrun(port);
992
1da177e4
LT		 993 return copied;
994}
995
a380ed46
UH		 996static int scif_set_rtrg(struct uart_port *port, int rx_trig)
997{
998 unsigned int bits;
999
1000 if (rx_trig < 1)
1001 rx_trig = 1;
1002 if (rx_trig >= port->fifosize)
1003 rx_trig = port->fifosize;
1004
1005 /* HSCIF can be set to an arbitrary level. */
1006 if (sci_getreg(port, HSRTRGR)->size) {
1007 serial_port_out(port, HSRTRGR, rx_trig);
1008 return rx_trig;
1009 }
1010
1011 switch (port->type) {
1012 case PORT_SCIF:
1013 if (rx_trig < 4) {
1014 bits = 0;
1015 rx_trig = 1;
1016 } else if (rx_trig < 8) {
1017 bits = SCFCR_RTRG0;
1018 rx_trig = 4;
1019 } else if (rx_trig < 14) {
1020 bits = SCFCR_RTRG1;
1021 rx_trig = 8;
1022 } else {
1023 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1024 rx_trig = 14;
1025 }
1026 break;
1027 case PORT_SCIFA:
1028 case PORT_SCIFB:
1029 if (rx_trig < 16) {
1030 bits = 0;
1031 rx_trig = 1;
1032 } else if (rx_trig < 32) {
1033 bits = SCFCR_RTRG0;
1034 rx_trig = 16;
1035 } else if (rx_trig < 48) {
1036 bits = SCFCR_RTRG1;
1037 rx_trig = 32;
1038 } else {
1039 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1040 rx_trig = 48;
1041 }
1042 break;
1043 default:
1044 WARN(1, "unknown FIFO configuration");
1045 return 1;
1046 }
1047
1048 serial_port_out(port, SCFCR,
1049 (serial_port_in(port, SCFCR) &
1050 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1051
1052 return rx_trig;
1053}
1054
03940376
UH		 1055static int scif_rtrg_enabled(struct uart_port *port)
1056{
1057 if (sci_getreg(port, HSRTRGR)->size)
1058 return serial_port_in(port, HSRTRGR) != 0;
1059 else
1060 return (serial_port_in(port, SCFCR) &
1061 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1062}
1063
1064static void rx_fifo_timer_fn(unsigned long arg)
1065{
1066 struct sci_port *s = (struct sci_port *)arg;
1067 struct uart_port *port = &s->port;
1068
1069 dev_dbg(port->dev, "Rx timed out\n");
1070 scif_set_rtrg(port, 1);
1071}
1072
5d23188a
UH		 1073static ssize_t rx_trigger_show(struct device *dev,
1074 struct device_attribute *attr,
1075 char *buf)
1076{
1077 struct uart_port *port = dev_get_drvdata(dev);
1078 struct sci_port *sci = to_sci_port(port);
1079
1080 return sprintf(buf, "%d\n", sci->rx_trigger);
1081}
1082
1083static ssize_t rx_trigger_store(struct device *dev,
1084 struct device_attribute *attr,
1085 const char *buf,
1086 size_t count)
1087{
1088 struct uart_port *port = dev_get_drvdata(dev);
1089 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1090 int ret;
5d23188a
UH		 1091 long r;
1092
4ab3c51e
DC		 1093 ret = kstrtol(buf, 0, &r);
1094 if (ret)
1095 return ret;
90afa525 1096
5d23188a 1097 sci->rx_trigger = scif_set_rtrg(port, r);
90afa525
UH		 1098 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1099 scif_set_rtrg(port, 1);
1100
5d23188a
UH		 1101 return count;
1102}
1103
1104static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1105
1106static ssize_t rx_fifo_timeout_show(struct device *dev,
1107 struct device_attribute *attr,
1108 char *buf)
1109{
1110 struct uart_port *port = dev_get_drvdata(dev);
1111 struct sci_port *sci = to_sci_port(port);
fa2abb03 1112 int v;
5d23188a 1113
fa2abb03
UH		 1114 if (port->type == PORT_HSCIF)
1115 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1116 else
1117 v = sci->rx_fifo_timeout;
1118
1119 return sprintf(buf, "%d\n", v);
5d23188a
UH		 1120}
1121
1122static ssize_t rx_fifo_timeout_store(struct device *dev,
1123 struct device_attribute *attr,
1124 const char *buf,
1125 size_t count)
1126{
1127 struct uart_port *port = dev_get_drvdata(dev);
1128 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1129 int ret;
5d23188a
UH		 1130 long r;
1131
4ab3c51e
DC		 1132 ret = kstrtol(buf, 0, &r);
1133 if (ret)
1134 return ret;
fa2abb03
UH		 1135
1136 if (port->type == PORT_HSCIF) {
1137 if (r < 0 || r > 3)
1138 return -EINVAL;
1139 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1140 } else {
1141 sci->rx_fifo_timeout = r;
1142 scif_set_rtrg(port, 1);
1143 if (r > 0)
1144 setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn,
1145 (unsigned long)sci);
1146 }
1147
5d23188a
UH		 1148 return count;
1149}
1150
1151static DEVICE_ATTR(rx_fifo_timeout, 0644, rx_fifo_timeout_show, rx_fifo_timeout_store);
1152
1153
73a19e4c 1154#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1155static void sci_dma_tx_complete(void *arg)
1156{
1157 struct sci_port *s = arg;
1158 struct uart_port *port = &s->port;
1159 struct circ_buf *xmit = &port->state->xmit;
1160 unsigned long flags;
73a19e4c 1161
e1910fcd 1162 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1163
e1910fcd 1164 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1165
e1910fcd
GU		 1166 xmit->tail += s->tx_dma_len;
1167 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1168
e1910fcd 1169 port->icount.tx += s->tx_dma_len;
1da177e4 1170
e1910fcd
GU		 1171 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1172 uart_write_wakeup(port);
1da177e4 1173
e1910fcd
GU		 1174 if (!uart_circ_empty(xmit)) {
1175 s->cookie_tx = 0;
1176 schedule_work(&s->work_tx);
1177 } else {
1178 s->cookie_tx = -EINVAL;
1179 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1180 u16 ctrl = serial_port_in(port, SCSCR);
1181 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1182 }
1183 }
1da177e4 1184
fd78a76a 1185 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1186}
1187
e1910fcd
GU		 1188/* Locking: called with port lock held */
1189static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1190{
e1910fcd
GU		 1191 struct uart_port *port = &s->port;
1192 struct tty_port *tport = &port->state->port;
1193 int copied;
1da177e4 1194
e1910fcd 1195 copied = tty_insert_flip_string(tport, buf, count);
6fc5a520 1196 if (copied < count)
e1910fcd 1197 port->icount.buf_overrun++;
1da177e4 1198
e1910fcd 1199 port->icount.rx += copied;
1da177e4 1200
e1910fcd 1201 return copied;
1da177e4
LT		 1202}
1203
e1910fcd 1204static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1205{
e1910fcd 1206 unsigned int i;
1da177e4 1207
e1910fcd
GU		 1208 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1209 if (s->active_rx == s->cookie_rx[i])
1210 return i;
1da177e4 1211
e1910fcd 1212 return -1;
1da177e4
LT		 1213}
1214
e1910fcd 1215static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1216{
e1910fcd
GU		 1217 struct dma_chan *chan = s->chan_rx;
1218 struct uart_port *port = &s->port;
1219 unsigned long flags;
1220
1221 spin_lock_irqsave(&port->lock, flags);
1222 s->chan_rx = NULL;
1223 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1224 spin_unlock_irqrestore(&port->lock, flags);
1225 dmaengine_terminate_all(chan);
1226 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1227 sg_dma_address(&s->sg_rx[0]));
1228 dma_release_channel(chan);
1be22663
TA		 1229 if (enable_pio) {
1230 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1231 sci_start_rx(port);
1be22663
TA		 1232 spin_unlock_irqrestore(&port->lock, flags);
1233 }
f43dc23d
PM		 1234}
1235
e1910fcd 1236static void sci_dma_rx_complete(void *arg)
1da177e4 1237{
e1910fcd 1238 struct sci_port *s = arg;
1d3db608 1239 struct dma_chan *chan = s->chan_rx;
e1910fcd 1240 struct uart_port *port = &s->port;
67f462b0 1241 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1242 unsigned long flags;
1243 int active, count = 0;
1da177e4 1244
e1910fcd
GU		 1245 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1246 s->active_rx);
cb772fe7 1247
e1910fcd 1248 spin_lock_irqsave(&port->lock, flags);
1da177e4 1249
e1910fcd
GU		 1250 active = sci_dma_rx_find_active(s);
1251 if (active >= 0)
1252 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1253
e1910fcd 1254 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1255
e1910fcd
GU		 1256 if (count)
1257 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1258
67f462b0
GU		 1259 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1260 DMA_DEV_TO_MEM,
1261 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1262 if (!desc)
1263 goto fail;
1264
1265 desc->callback = sci_dma_rx_complete;
1266 desc->callback_param = s;
1267 s->cookie_rx[active] = dmaengine_submit(desc);
1268 if (dma_submit_error(s->cookie_rx[active]))
1269 goto fail;
1270
1271 s->active_rx = s->cookie_rx[!active];
1272
1d3db608
MHF		 1273 dma_async_issue_pending(chan);
1274
6fc5a520 1275 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1276 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1277 __func__, s->cookie_rx[active], active, s->active_rx);
67f462b0
GU		 1278 return;
1279
1280fail:
1281 spin_unlock_irqrestore(&port->lock, flags);
1282 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1283 sci_rx_dma_release(s, true);
1da177e4
LT		 1284}
1285
e1910fcd 1286static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1287{
e1910fcd
GU		 1288 struct dma_chan *chan = s->chan_tx;
1289 struct uart_port *port = &s->port;
e552de24 1290 unsigned long flags;
1da177e4 1291
e1910fcd
GU		 1292 spin_lock_irqsave(&port->lock, flags);
1293 s->chan_tx = NULL;
1294 s->cookie_tx = -EINVAL;
1295 spin_unlock_irqrestore(&port->lock, flags);
1296 dmaengine_terminate_all(chan);
1297 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1298 DMA_TO_DEVICE);
1299 dma_release_channel(chan);
1be22663
TA		 1300 if (enable_pio) {
1301 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1302 sci_start_tx(port);
1be22663
TA		 1303 spin_unlock_irqrestore(&port->lock, flags);
1304 }
e1910fcd 1305}
d535a230 1306
e1910fcd
GU		 1307static void sci_submit_rx(struct sci_port *s)
1308{
1309 struct dma_chan *chan = s->chan_rx;
1310 int i;
073e84c9 1311
e1910fcd
GU		 1312 for (i = 0; i < 2; i++) {
1313 struct scatterlist *sg = &s->sg_rx[i];
1314 struct dma_async_tx_descriptor *desc;
1da177e4 1315
e1910fcd
GU		 1316 desc = dmaengine_prep_slave_sg(chan,
1317 sg, 1, DMA_DEV_TO_MEM,
1318 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1319 if (!desc)
1320 goto fail;
501b825d 1321
e1910fcd
GU		 1322 desc->callback = sci_dma_rx_complete;
1323 desc->callback_param = s;
1324 s->cookie_rx[i] = dmaengine_submit(desc);
1325 if (dma_submit_error(s->cookie_rx[i]))
1326 goto fail;
9174fc8f 1327
e1910fcd 1328 }
9174fc8f 1329
e1910fcd 1330 s->active_rx = s->cookie_rx[0];
9174fc8f 1331
e1910fcd
GU		 1332 dma_async_issue_pending(chan);
1333 return;
9174fc8f 1334
e1910fcd
GU		 1335fail:
1336 if (i)
1337 dmaengine_terminate_all(chan);
1338 for (i = 0; i < 2; i++)
1339 s->cookie_rx[i] = -EINVAL;
1340 s->active_rx = -EINVAL;
e1910fcd
GU		 1341 sci_rx_dma_release(s, true);
1342}
9174fc8f 1343
e1910fcd 1344static void work_fn_tx(struct work_struct *work)
1da177e4 1345{
e1910fcd
GU		 1346 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1347 struct dma_async_tx_descriptor *desc;
1348 struct dma_chan *chan = s->chan_tx;
1349 struct uart_port *port = &s->port;
1350 struct circ_buf *xmit = &port->state->xmit;
1351 dma_addr_t buf;
1da177e4 1352
9174fc8f 1353 /*
e1910fcd
GU		 1354 * DMA is idle now.
1355 * Port xmit buffer is already mapped, and it is one page... Just adjust
1356 * offsets and lengths. Since it is a circular buffer, we have to
1357 * transmit till the end, and then the rest. Take the port lock to get a
1358 * consistent xmit buffer state.
9174fc8f 1359 */
e1910fcd
GU		 1360 spin_lock_irq(&port->lock);
1361 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1362 s->tx_dma_len = min_t(unsigned int,
1363 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1364 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1365 spin_unlock_irq(&port->lock);
0e8963de 1366
e1910fcd
GU		 1367 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1368 DMA_MEM_TO_DEV,
1369 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1370 if (!desc) {
1371 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1372 /* switch to PIO */
1373 sci_tx_dma_release(s, true);
1374 return;
1375 }
0e8963de 1376
e1910fcd
GU		 1377 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1378 DMA_TO_DEVICE);
1da177e4 1379
e1910fcd
GU		 1380 spin_lock_irq(&port->lock);
1381 desc->callback = sci_dma_tx_complete;
1382 desc->callback_param = s;
1383 spin_unlock_irq(&port->lock);
1384 s->cookie_tx = dmaengine_submit(desc);
1385 if (dma_submit_error(s->cookie_tx)) {
1386 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1387 /* switch to PIO */
1388 sci_tx_dma_release(s, true);
1389 return;
1da177e4 1390 }
1da177e4 1391
e1910fcd
GU		 1392 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1393 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1394
e1910fcd 1395 dma_async_issue_pending(chan);
1da177e4
LT		 1396}
1397
e1910fcd 1398static void rx_timer_fn(unsigned long arg)
1da177e4 1399{
e1910fcd 1400 struct sci_port *s = (struct sci_port *)arg;
e7327c09 1401 struct dma_chan *chan = s->chan_rx;
e1910fcd 1402 struct uart_port *port = &s->port;
67f462b0
GU		 1403 struct dma_tx_state state;
1404 enum dma_status status;
1405 unsigned long flags;
1406 unsigned int read;
1407 int active, count;
1408 u16 scr;
1409
67f462b0 1410 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0 1411
6fc5a520
TA		 1412 spin_lock_irqsave(&port->lock, flags);
1413
67f462b0
GU		 1414 active = sci_dma_rx_find_active(s);
1415 if (active < 0) {
1416 spin_unlock_irqrestore(&port->lock, flags);
1417 return;
1418 }
1419
1420 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1421 if (status == DMA_COMPLETE) {
6fc5a520 1422 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1423 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1424 s->active_rx, active);
3b963042
MHF		 1425
1426 /* Let packet complete handler take care of the packet */
1427 return;
1428 }
67f462b0 1429
e7327c09
MHF		 1430 dmaengine_pause(chan);
1431
1432 /*
1433 * sometimes DMA transfer doesn't stop even if it is stopped and
1434 * data keeps on coming until transaction is complete so check
1435 * for DMA_COMPLETE again
1436 * Let packet complete handler take care of the packet
1437 */
1438 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1439 if (status == DMA_COMPLETE) {
1440 spin_unlock_irqrestore(&port->lock, flags);
1441 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1442 return;
1443 }
1444
67f462b0
GU		 1445 /* Handle incomplete DMA receive */
1446 dmaengine_terminate_all(s->chan_rx);
1447 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
67f462b0
GU		 1448
1449 if (read) {
1450 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1451 if (count)
1452 tty_flip_buffer_push(&port->state->port);
1453 }
1454
756981be
GU		 1455 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1456 sci_submit_rx(s);
371cfed3
MHF		 1457
1458 /* Direct new serial port interrupts back to CPU */
1459 scr = serial_port_in(port, SCSCR);
1460 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1461 scr &= ~SCSCR_RDRQE;
1462 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1463 }
1464 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1465
1466 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1467}
1468
ff441129 1469static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
219fb0c1 1470 enum dma_transfer_direction dir)
ff441129 1471{
ff441129
GU		 1472 struct dma_chan *chan;
1473 struct dma_slave_config cfg;
1474 int ret;
1475
219fb0c1
LP		 1476 chan = dma_request_slave_channel(port->dev,
1477 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
ff441129 1478 if (!chan) {
9b7becf1 1479 dev_warn(port->dev, "dma_request_slave_channel failed\n");
ff441129
GU		 1480 return NULL;
1481 }
1482
1483 memset(&cfg, 0, sizeof(cfg));
1484 cfg.direction = dir;
1485 if (dir == DMA_MEM_TO_DEV) {
1486 cfg.dst_addr = port->mapbase +
1487 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1488 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1489 } else {
1490 cfg.src_addr = port->mapbase +
1491 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1492 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1493 }
1494
1495 ret = dmaengine_slave_config(chan, &cfg);
1496 if (ret) {
1497 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1498 dma_release_channel(chan);
1499 return NULL;
1500 }
1501
1502 return chan;
1503}
1504
e1910fcd 1505static void sci_request_dma(struct uart_port *port)
73a19e4c 1506{
e1910fcd 1507 struct sci_port *s = to_sci_port(port);
e1910fcd 1508 struct dma_chan *chan;
73a19e4c 1509
e1910fcd 1510 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1511
219fb0c1 1512 if (!port->dev->of_node)
e1910fcd 1513 return;
73a19e4c 1514
e1910fcd 1515 s->cookie_tx = -EINVAL;
7464779f
AL		 1516
1517 /*
1518 * Don't request a dma channel if no channel was specified
1519 * in the device tree.
1520 */
1521 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1522 return;
1523
219fb0c1 1524 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
e1910fcd
GU		 1525 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1526 if (chan) {
1527 s->chan_tx = chan;
1528 /* UART circular tx buffer is an aligned page. */
1529 s->tx_dma_addr = dma_map_single(chan->device->dev,
1530 port->state->xmit.buf,
1531 UART_XMIT_SIZE,
1532 DMA_TO_DEVICE);
1533 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1534 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1535 dma_release_channel(chan);
1536 s->chan_tx = NULL;
1537 } else {
1538 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1539 __func__, UART_XMIT_SIZE,
1540 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1541 }
e1910fcd
GU		 1542
1543 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1544 }
1545
219fb0c1 1546 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
e1910fcd
GU		 1547 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1548 if (chan) {
1549 unsigned int i;
1550 dma_addr_t dma;
1551 void *buf;
73a19e4c 1552
e1910fcd 1553 s->chan_rx = chan;
73a19e4c 1554
e1910fcd
GU		 1555 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1556 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1557 &dma, GFP_KERNEL);
1558 if (!buf) {
1559 dev_warn(port->dev,
1560 "Failed to allocate Rx dma buffer, using PIO\n");
1561 dma_release_channel(chan);
1562 s->chan_rx = NULL;
e1910fcd
GU		 1563 return;
1564 }
73a19e4c 1565
e1910fcd
GU		 1566 for (i = 0; i < 2; i++) {
1567 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1568
e1910fcd
GU		 1569 sg_init_table(sg, 1);
1570 s->rx_buf[i] = buf;
1571 sg_dma_address(sg) = dma;
d09959e7 1572 sg_dma_len(sg) = s->buf_len_rx;
0533502d 1573
e1910fcd
GU		 1574 buf += s->buf_len_rx;
1575 dma += s->buf_len_rx;
1576 }
1577
e1910fcd
GU		 1578 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1579
756981be
GU		 1580 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1581 sci_submit_rx(s);
e1910fcd 1582 }
0533502d
GU		 1583}
1584
e1910fcd 1585static void sci_free_dma(struct uart_port *port)
73a19e4c 1586{
e1910fcd 1587 struct sci_port *s = to_sci_port(port);
73a19e4c 1588
e1910fcd
GU		 1589 if (s->chan_tx)
1590 sci_tx_dma_release(s, false);
1591 if (s->chan_rx)
1592 sci_rx_dma_release(s, false);
1593}
1cf4a7ef
GU		 1594
1595static void sci_flush_buffer(struct uart_port *port)
1596{
1597 /*
1598 * In uart_flush_buffer(), the xmit circular buffer has just been
1599 * cleared, so we have to reset tx_dma_len accordingly.
1600 */
1601 to_sci_port(port)->tx_dma_len = 0;
1602}
1603#else /* !CONFIG_SERIAL_SH_SCI_DMA */
e1910fcd
GU		 1604static inline void sci_request_dma(struct uart_port *port)
1605{
1606}
73a19e4c 1607
e1910fcd
GU		 1608static inline void sci_free_dma(struct uart_port *port)
1609{
1610}
1cf4a7ef
GU		 1611
1612#define sci_flush_buffer NULL
1613#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
73a19e4c 1614
e1910fcd
GU		 1615static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1616{
e1910fcd
GU		 1617 struct uart_port *port = ptr;
1618 struct sci_port *s = to_sci_port(port);
73a19e4c 1619
03940376 1620#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1621 if (s->chan_rx) {
1622 u16 scr = serial_port_in(port, SCSCR);
1623 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1624
e1910fcd
GU		 1625 /* Disable future Rx interrupts */
1626 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1627 disable_irq_nosync(irq);
1628 scr |= SCSCR_RDRQE;
1629 } else {
1630 scr &= ~SCSCR_RIE;
756981be 1631 sci_submit_rx(s);
e1910fcd
GU		 1632 }
1633 serial_port_out(port, SCSCR, scr);
1634 /* Clear current interrupt */
1635 serial_port_out(port, SCxSR,
1636 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1637 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1638 jiffies, s->rx_timeout);
1639 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1640
e1910fcd
GU		 1641 return IRQ_HANDLED;
1642 }
1643#endif
73a19e4c 1644
03940376
UH		 1645 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1646 if (!scif_rtrg_enabled(port))
1647 scif_set_rtrg(port, s->rx_trigger);
1648
1649 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1650 s->rx_frame * s->rx_fifo_timeout, 1000));
1651 }
1652
e1910fcd
GU		 1653 /* I think sci_receive_chars has to be called irrespective
1654 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1655 * to be disabled?
1656 */
1657 sci_receive_chars(ptr);
1658
1659 return IRQ_HANDLED;
73a19e4c
GL		 1660}
1661
e1910fcd 1662static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1663{
e1910fcd 1664 struct uart_port *port = ptr;
04928b79 1665 unsigned long flags;
73a19e4c 1666
04928b79 1667 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1668 sci_transmit_chars(port);
04928b79 1669 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1670
1671 return IRQ_HANDLED;
73a19e4c
GL		 1672}
1673
e1910fcd 1674static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1675{
e1910fcd
GU		 1676 struct uart_port *port = ptr;
1677 struct sci_port *s = to_sci_port(port);
73a19e4c 1678
e1910fcd
GU		 1679 /* Handle errors */
1680 if (port->type == PORT_SCI) {
1681 if (sci_handle_errors(port)) {
1682 /* discard character in rx buffer */
1683 serial_port_in(port, SCxSR);
1684 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1685 }
1686 } else {
1687 sci_handle_fifo_overrun(port);
1688 if (!s->chan_rx)
1689 sci_receive_chars(ptr);
1690 }
1691
1692 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1693
1694 /* Kick the transmission */
1695 if (!s->chan_tx)
1696 sci_tx_interrupt(irq, ptr);
1697
1698 return IRQ_HANDLED;
73a19e4c
GL		 1699}
1700
e1910fcd 1701static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1702{
e1910fcd 1703 struct uart_port *port = ptr;
73a19e4c 1704
e1910fcd
GU		 1705 /* Handle BREAKs */
1706 sci_handle_breaks(port);
1707 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1708
e1910fcd
GU		 1709 return IRQ_HANDLED;
1710}
73a19e4c 1711
e1910fcd
GU		 1712static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1713{
1714 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1715 struct uart_port *port = ptr;
1716 struct sci_port *s = to_sci_port(port);
1717 irqreturn_t ret = IRQ_NONE;
73a19e4c 1718
e1910fcd
GU		 1719 ssr_status = serial_port_in(port, SCxSR);
1720 scr_status = serial_port_in(port, SCSCR);
b2f20ed9 1721 if (s->params->overrun_reg == SCxSR)
e1910fcd 1722 orer_status = ssr_status;
b2f20ed9
LP		 1723 else if (sci_getreg(port, s->params->overrun_reg)->size)
1724 orer_status = serial_port_in(port, s->params->overrun_reg);
73a19e4c 1725
e1910fcd 1726 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1727
e1910fcd
GU		 1728 /* Tx Interrupt */
1729 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1730 !s->chan_tx)
1731 ret = sci_tx_interrupt(irq, ptr);
658daa95 1732
e1910fcd
GU		 1733 /*
1734 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1735 * DR flags
1736 */
1737 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1738 (scr_status & SCSCR_RIE))
1739 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1740
e1910fcd
GU		 1741 /* Error Interrupt */
1742 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1743 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1744
e1910fcd
GU		 1745 /* Break Interrupt */
1746 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1747 ret = sci_br_interrupt(irq, ptr);
1748
1749 /* Overrun Interrupt */
b2f20ed9 1750 if (orer_status & s->params->overrun_mask) {
e1910fcd
GU		 1751 sci_handle_fifo_overrun(port);
1752 ret = IRQ_HANDLED;
73a19e4c 1753 }
73a19e4c 1754
e1910fcd
GU		 1755 return ret;
1756}
73a19e4c 1757
e1910fcd
GU		 1758static const struct sci_irq_desc {
1759 const char *desc;
1760 irq_handler_t handler;
1761} sci_irq_desc[] = {
1762 /*
1763 * Split out handlers, the default case.
1764 */
1765 [SCIx_ERI_IRQ] = {
1766 .desc = "rx err",
1767 .handler = sci_er_interrupt,
1768 },
3089f381 1769
e1910fcd
GU		 1770 [SCIx_RXI_IRQ] = {
1771 .desc = "rx full",
1772 .handler = sci_rx_interrupt,
1773 },
47aceb92 1774
e1910fcd
GU		 1775 [SCIx_TXI_IRQ] = {
1776 .desc = "tx empty",
1777 .handler = sci_tx_interrupt,
1778 },
73a19e4c 1779
e1910fcd
GU		 1780 [SCIx_BRI_IRQ] = {
1781 .desc = "break",
1782 .handler = sci_br_interrupt,
1783 },
73a19e4c
GL		 1784
1785 /*
e1910fcd 1786 * Special muxed handler.
73a19e4c 1787 */
e1910fcd
GU		 1788 [SCIx_MUX_IRQ] = {
1789 .desc = "mux",
1790 .handler = sci_mpxed_interrupt,
1791 },
1792};
73a19e4c 1793
e1910fcd
GU		 1794static int sci_request_irq(struct sci_port *port)
1795{
1796 struct uart_port *up = &port->port;
1797 int i, j, ret = 0;
73a19e4c 1798
e1910fcd
GU		 1799 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1800 const struct sci_irq_desc *desc;
1801 int irq;
73a19e4c 1802
e1910fcd
GU		 1803 if (SCIx_IRQ_IS_MUXED(port)) {
1804 i = SCIx_MUX_IRQ;
1805 irq = up->irq;
1806 } else {
1807 irq = port->irqs[i];
1808
1809 /*
1810 * Certain port types won't support all of the
1811 * available interrupt sources.
1812 */
1813 if (unlikely(irq < 0))
1814 continue;
1815 }
1816
1817 desc = sci_irq_desc + i;
1818 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1819 dev_name(up->dev), desc->desc);
623ac1d4
PB		 1820 if (!port->irqstr[j]) {
1821 ret = -ENOMEM;
e1910fcd 1822 goto out_nomem;
623ac1d4 1823 }
e1910fcd
GU		 1824
1825 ret = request_irq(irq, desc->handler, up->irqflags,
1826 port->irqstr[j], port);
1827 if (unlikely(ret)) {
1828 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1829 goto out_noirq;
1830 }
73a19e4c
GL		 1831 }
1832
e1910fcd 1833 return 0;
1da177e4 1834
e1910fcd
GU		 1835out_noirq:
1836 while (--i >= 0)
1837 free_irq(port->irqs[i], port);
f43dc23d 1838
e1910fcd
GU		 1839out_nomem:
1840 while (--j >= 0)
1841 kfree(port->irqstr[j]);
f43dc23d 1842
e1910fcd 1843 return ret;
1da177e4
LT		 1844}
1845
e1910fcd 1846static void sci_free_irq(struct sci_port *port)
1da177e4 1847{
e1910fcd 1848 int i;
1da177e4 1849
e1910fcd
GU		 1850 /*
1851 * Intentionally in reverse order so we iterate over the muxed
1852 * IRQ first.
1853 */
1854 for (i = 0; i < SCIx_NR_IRQS; i++) {
1855 int irq = port->irqs[i];
f43dc23d 1856
e1910fcd
GU		 1857 /*
1858 * Certain port types won't support all of the available
1859 * interrupt sources.
1860 */
1861 if (unlikely(irq < 0))
1862 continue;
f43dc23d 1863
e1910fcd
GU		 1864 free_irq(port->irqs[i], port);
1865 kfree(port->irqstr[i]);
f43dc23d 1866
e1910fcd
GU		 1867 if (SCIx_IRQ_IS_MUXED(port)) {
1868 /* If there's only one IRQ, we're done. */
1869 return;
1870 }
1871 }
1da177e4
LT		 1872}
1873
e1910fcd 1874static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1875{
e1910fcd
GU		 1876 unsigned short status = serial_port_in(port, SCxSR);
1877 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1878
e1910fcd 1879 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1880}
1881
33f50ffc
GU		 1882static void sci_set_rts(struct uart_port *port, bool state)
1883{
1884 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1885 u16 data = serial_port_in(port, SCPDR);
1886
1887 /* Active low */
1888 if (state)
1889 data &= ~SCPDR_RTSD;
1890 else
1891 data |= SCPDR_RTSD;
1892 serial_port_out(port, SCPDR, data);
1893
1894 /* RTS# is output */
1895 serial_port_out(port, SCPCR,
1896 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1897 } else if (sci_getreg(port, SCSPTR)->size) {
1898 u16 ctrl = serial_port_in(port, SCSPTR);
1899
1900 /* Active low */
1901 if (state)
1902 ctrl &= ~SCSPTR_RTSDT;
1903 else
1904 ctrl |= SCSPTR_RTSDT;
1905 serial_port_out(port, SCSPTR, ctrl);
1906 }
1907}
1908
1909static bool sci_get_cts(struct uart_port *port)
1910{
1911 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1912 /* Active low */
1913 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1914 } else if (sci_getreg(port, SCSPTR)->size) {
1915 /* Active low */
1916 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1917 }
1918
1919 return true;
1920}
1921
e1910fcd
GU		 1922/*
1923 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1924 * CTS/RTS is supported in hardware by at least one port and controlled
1925 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1926 * handled via the ->init_pins() op, which is a bit of a one-way street,
1927 * lacking any ability to defer pin control -- this will later be
1928 * converted over to the GPIO framework).
1929 *
1930 * Other modes (such as loopback) are supported generically on certain
1931 * port types, but not others. For these it's sufficient to test for the
1932 * existence of the support register and simply ignore the port type.
1933 */
1934static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1935{
f907c9ea
GU		 1936 struct sci_port *s = to_sci_port(port);
1937
e1910fcd
GU		 1938 if (mctrl & TIOCM_LOOP) {
1939 const struct plat_sci_reg *reg;
f43dc23d 1940
e1910fcd
GU		 1941 /*
1942 * Standard loopback mode for SCFCR ports.
1943 */
1944 reg = sci_getreg(port, SCFCR);
1945 if (reg->size)
1946 serial_port_out(port, SCFCR,
1947 serial_port_in(port, SCFCR) |
1948 SCFCR_LOOP);
1949 }
f907c9ea
GU		 1950
1951 mctrl_gpio_set(s->gpios, mctrl);
33f50ffc 1952
97ed9790 1953 if (!s->has_rtscts)
33f50ffc
GU		 1954 return;
1955
1956 if (!(mctrl & TIOCM_RTS)) {
1957 /* Disable Auto RTS */
1958 serial_port_out(port, SCFCR,
1959 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1960
1961 /* Clear RTS */
1962 sci_set_rts(port, 0);
1963 } else if (s->autorts) {
1964 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1965 /* Enable RTS# pin function */
1966 serial_port_out(port, SCPCR,
1967 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1968 }
1969
1970 /* Enable Auto RTS */
1971 serial_port_out(port, SCFCR,
1972 serial_port_in(port, SCFCR) | SCFCR_MCE);
1973 } else {
1974 /* Set RTS */
1975 sci_set_rts(port, 1);
1976 }
e1910fcd 1977}
f43dc23d 1978
e1910fcd
GU		 1979static unsigned int sci_get_mctrl(struct uart_port *port)
1980{
f907c9ea
GU		 1981 struct sci_port *s = to_sci_port(port);
1982 struct mctrl_gpios *gpios = s->gpios;
1983 unsigned int mctrl = 0;
1984
1985 mctrl_gpio_get(gpios, &mctrl);
1986
e1910fcd
GU		 1987 /*
1988 * CTS/RTS is handled in hardware when supported, while nothing
33f50ffc 1989 * else is wired up.
e1910fcd 1990 */
33f50ffc
GU		 1991 if (s->autorts) {
1992 if (sci_get_cts(port))
1993 mctrl |= TIOCM_CTS;
1994 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
f907c9ea 1995 mctrl |= TIOCM_CTS;
33f50ffc 1996 }
f907c9ea
GU		 1997 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1998 mctrl |= TIOCM_DSR;
1999 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2000 mctrl |= TIOCM_CAR;
2001
2002 return mctrl;
2003}
2004
2005static void sci_enable_ms(struct uart_port *port)
2006{
2007 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1da177e4
LT		 2008}
2009
1da177e4
LT		 2010static void sci_break_ctl(struct uart_port *port, int break_state)
2011{
bbb4ce50 2012 unsigned short scscr, scsptr;
1be22663 2013 unsigned long flags;
bbb4ce50 2014
a4e02f6d 2015 /* check wheter the port has SCSPTR */
abbf121f 2016 if (!sci_getreg(port, SCSPTR)->size) {
bbb4ce50
SY		 2017 /*
2018 * Not supported by hardware. Most parts couple break and rx
2019 * interrupts together, with break detection always enabled.
2020 */
a4e02f6d 2021 return;
bbb4ce50 2022 }
a4e02f6d 2023
1be22663 2024 spin_lock_irqsave(&port->lock, flags);
a4e02f6d
SY		 2025 scsptr = serial_port_in(port, SCSPTR);
2026 scscr = serial_port_in(port, SCSCR);
2027
2028 if (break_state == -1) {
2029 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2030 scscr &= ~SCSCR_TE;
2031 } else {
2032 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2033 scscr |= SCSCR_TE;
2034 }
2035
2036 serial_port_out(port, SCSPTR, scsptr);
2037 serial_port_out(port, SCSCR, scscr);
1be22663 2038 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2039}
2040
2041static int sci_startup(struct uart_port *port)
2042{
a5660ada 2043 struct sci_port *s = to_sci_port(port);
073e84c9 2044 int ret;
1da177e4 2045
73a19e4c
GL		 2046 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2047
3c910176
TA		 2048 sci_request_dma(port);
2049
073e84c9 2050 ret = sci_request_irq(s);
3c910176
TA		 2051 if (unlikely(ret < 0)) {
2052 sci_free_dma(port);
073e84c9 2053 return ret;
3c910176 2054 }
073e84c9 2055
1da177e4
LT		 2056 return 0;
2057}
2058
2059static void sci_shutdown(struct uart_port *port)
2060{
a5660ada 2061 struct sci_port *s = to_sci_port(port);
33b48e16 2062 unsigned long flags;
5fd2b6ee 2063 u16 scr;
1da177e4 2064
73a19e4c
GL		 2065 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2066
33f50ffc 2067 s->autorts = false;
f907c9ea
GU		 2068 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2069
33b48e16 2070 spin_lock_irqsave(&port->lock, flags);
1da177e4 2071 sci_stop_rx(port);
b129a8cc 2072 sci_stop_tx(port);
fa2abb03
UH		 2073 /*
2074 * Stop RX and TX, disable related interrupts, keep clock source
2075 * and HSCIF TOT bits
2076 */
5fd2b6ee 2077 scr = serial_port_in(port, SCSCR);
fa2abb03
UH		 2078 serial_port_out(port, SCSCR, scr &
2079 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
33b48e16 2080 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 2081
9ab76556
AM		 2082#ifdef CONFIG_SERIAL_SH_SCI_DMA
2083 if (s->chan_rx) {
2084 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2085 port->line);
2086 del_timer_sync(&s->rx_timer);
2087 }
2088#endif
2089
1da177e4 2090 sci_free_irq(s);
3c910176 2091 sci_free_dma(port);
1da177e4
LT		 2092}
2093
6af27bf2
GU		 2094static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2095 unsigned int *srr)
26c92f37 2096{
6af27bf2 2097 unsigned long freq = s->clk_rates[SCI_SCK];
6af27bf2 2098 int err, min_err = INT_MAX;
69eee8e9 2099 unsigned int sr;
6af27bf2 2100
7b5c0c08
GU		 2101 if (s->port.type != PORT_HSCIF)
2102 freq *= 2;
6af27bf2 2103
69eee8e9 2104 for_each_sr(sr, s) {
6af27bf2
GU		 2105 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2106 if (abs(err) >= abs(min_err))
2107 continue;
2108
2109 min_err = err;
2110 *srr = sr - 1;
ec09c5eb 2111
6af27bf2
GU		 2112 if (!err)
2113 break;
2114 }
e8183a6c 2115
6af27bf2
GU		 2116 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2117 *srr + 1);
2118 return min_err;
26c92f37
PM		 2119}
2120
1270f865
GU		 2121static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2122 unsigned long freq, unsigned int *dlr,
2123 unsigned int *srr)
730c4e78 2124{
1270f865 2125 int err, min_err = INT_MAX;
69eee8e9 2126 unsigned int sr, dl;
730c4e78 2127
7b5c0c08
GU		 2128 if (s->port.type != PORT_HSCIF)
2129 freq *= 2;
730c4e78 2130
69eee8e9 2131 for_each_sr(sr, s) {
1270f865
GU		 2132 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2133 dl = clamp(dl, 1U, 65535U);
2134
2135 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2136 if (abs(err) >= abs(min_err))
2137 continue;
2138
2139 min_err = err;
2140 *dlr = dl;
2141 *srr = sr - 1;
2142
2143 if (!err)
2144 break;
2145 }
730c4e78 2146
1270f865
GU		 2147 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2148 min_err, *dlr, *srr + 1);
2149 return min_err;
2150}
730c4e78 2151
b4a5c459 2152/* calculate sample rate, BRR, and clock select */
f4998e55
GU		 2153static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2154 unsigned int *brr, unsigned int *srr,
2155 unsigned int *cks)
f303b364 2156{
f4998e55 2157 unsigned long freq = s->clk_rates[SCI_FCK];
69eee8e9 2158 unsigned int sr, br, prediv, scrate, c;
6c51332d 2159 int err, min_err = INT_MAX;
f303b364 2160
7b5c0c08
GU		 2161 if (s->port.type != PORT_HSCIF)
2162 freq *= 2;
b4a5c459 2163
6c51332d
GU		 2164 /*
2165 * Find the combination of sample rate and clock select with the
2166 * smallest deviation from the desired baud rate.
2167 * Prefer high sample rates to maximise the receive margin.
2168 *
2169 * M: Receive margin (%)
2170 * N: Ratio of bit rate to clock (N = sampling rate)
2171 * D: Clock duty (D = 0 to 1.0)
2172 * L: Frame length (L = 9 to 12)
2173 * F: Absolute value of clock frequency deviation
2174 *
2175 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2176 * (|D - 0.5| / N * (1 + F))|
2177 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2178 */
69eee8e9 2179 for_each_sr(sr, s) {
f303b364
UH		 2180 for (c = 0; c <= 3; c++) {
2181 /* integerized formulas from HSCIF documentation */
7b5c0c08 2182 prediv = sr * (1 << (2 * c + 1));
de01e6cd
GU		 2183
2184 /*
2185 * We need to calculate:
2186 *
2187 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 2188 * err = freq / (br * prediv) - bps
730c4e78 2189 *
de01e6cd
GU		 2190 * Watch out for overflow when calculating the desired
2191 * sampling clock rate!
730c4e78 2192 */
de01e6cd
GU		 2193 if (bps > UINT_MAX / prediv)
2194 break;
2195
2196 scrate = prediv * bps;
2197 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 2198 br = clamp(br, 1U, 256U);
6c51332d 2199
881a7489 2200 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 2201 if (abs(err) >= abs(min_err))
730c4e78
NI		 2202 continue;
2203
6c51332d 2204 min_err = err;
95a2703e 2205 *brr = br - 1;
730c4e78
NI		 2206 *srr = sr - 1;
2207 *cks = c;
6c51332d
GU		 2208
2209 if (!err)
2210 goto found;
f303b364
UH		 2211 }
2212 }
2213
6c51332d 2214found:
881a7489
GU		 2215 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2216 min_err, *brr, *srr + 1, *cks);
f4998e55 2217 return min_err;
f303b364
UH		 2218}
2219
1ba76220
MD		 2220static void sci_reset(struct uart_port *port)
2221{
d3184e68 2222 const struct plat_sci_reg *reg;
1ba76220 2223 unsigned int status;
18e8cf15 2224 struct sci_port *s = to_sci_port(port);
1ba76220 2225
fa2abb03 2226 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
1ba76220 2227
0979e0e6
PM		 2228 reg = sci_getreg(port, SCFCR);
2229 if (reg->size)
b12bb29f 2230 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2768cf42
GU		 2231
2232 sci_clear_SCxSR(port,
2233 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2234 SCxSR_BREAK_CLEAR(port));
fc2af334
GU		 2235 if (sci_getreg(port, SCLSR)->size) {
2236 status = serial_port_in(port, SCLSR);
2237 status &= ~(SCLSR_TO | SCLSR_ORER);
2238 serial_port_out(port, SCLSR, status);
2239 }
18e8cf15 2240
03940376
UH		 2241 if (s->rx_trigger > 1) {
2242 if (s->rx_fifo_timeout) {
2243 scif_set_rtrg(port, 1);
2244 setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn,
2245 (unsigned long)s);
2246 } else {
90afa525
UH		 2247 if (port->type == PORT_SCIFA ||
2248 port->type == PORT_SCIFB)
2249 scif_set_rtrg(port, 1);
2250 else
2251 scif_set_rtrg(port, s->rx_trigger);
03940376
UH		 2252 }
2253 }
1ba76220
MD		 2254}
2255
606d099c
AC		 2256static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2257 struct ktermios *old)
1da177e4 2258{
03940376 2259 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
1270f865
GU		 2260 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2261 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
00b9de9c 2262 struct sci_port *s = to_sci_port(port);
d3184e68 2263 const struct plat_sci_reg *reg;
f4998e55
GU		 2264 int min_err = INT_MAX, err;
2265 unsigned long max_freq = 0;
2266 int best_clk = -1;
1be22663 2267 unsigned long flags;
1da177e4 2268
730c4e78
NI		 2269 if ((termios->c_cflag & CSIZE) == CS7)
2270 smr_val |= SCSMR_CHR;
2271 if (termios->c_cflag & PARENB)
2272 smr_val |= SCSMR_PE;
2273 if (termios->c_cflag & PARODD)
2274 smr_val |= SCSMR_PE | SCSMR_ODD;
2275 if (termios->c_cflag & CSTOPB)
2276 smr_val |= SCSMR_STOP;
2277
154280fd
MD		 2278 /*
2279 * earlyprintk comes here early on with port->uartclk set to zero.
2280 * the clock framework is not up and running at this point so here
2281 * we assume that 115200 is the maximum baud rate. please note that
2282 * the baud rate is not programmed during earlyprintk - it is assumed
2283 * that the previous boot loader has enabled required clocks and
2284 * setup the baud rate generator hardware for us already.
2285 */
f4998e55
GU		 2286 if (!port->uartclk) {
2287 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2288 goto done;
2289 }
1da177e4 2290
f4998e55
GU		 2291 for (i = 0; i < SCI_NUM_CLKS; i++)
2292 max_freq = max(max_freq, s->clk_rates[i]);
2293
69eee8e9 2294 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
f4998e55
GU		 2295 if (!baud)
2296 goto done;
2297
2298 /*
2299 * There can be multiple sources for the sampling clock. Find the one
2300 * that gives us the smallest deviation from the desired baud rate.
2301 */
2302
6af27bf2
GU		 2303 /* Optional Undivided External Clock */
2304 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2305 port->type != PORT_SCIFB) {
2306 err = sci_sck_calc(s, baud, &srr1);
2307 if (abs(err) < abs(min_err)) {
2308 best_clk = SCI_SCK;
2309 scr_val = SCSCR_CKE1;
2310 sccks = SCCKS_CKS;
2311 min_err = err;
2312 srr = srr1;
2313 if (!err)
2314 goto done;
2315 }
2316 }
2317
1270f865
GU		 2318 /* Optional BRG Frequency Divided External Clock */
2319 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2320 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2321 &srr1);
2322 if (abs(err) < abs(min_err)) {
2323 best_clk = SCI_SCIF_CLK;
2324 scr_val = SCSCR_CKE1;
2325 sccks = 0;
2326 min_err = err;
2327 dl = dl1;
2328 srr = srr1;
2329 if (!err)
2330 goto done;
2331 }
2332 }
2333
2334 /* Optional BRG Frequency Divided Internal Clock */
2335 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2336 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2337 &srr1);
2338 if (abs(err) < abs(min_err)) {
2339 best_clk = SCI_BRG_INT;
2340 scr_val = SCSCR_CKE1;
2341 sccks = SCCKS_XIN;
2342 min_err = err;
2343 dl = dl1;
2344 srr = srr1;
2345 if (!min_err)
2346 goto done;
f303b364
UH		 2347 }
2348 }
e108b2ca 2349
f4998e55
GU		 2350 /* Divided Functional Clock using standard Bit Rate Register */
2351 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2352 if (abs(err) < abs(min_err)) {
2353 best_clk = SCI_FCK;
6af27bf2 2354 scr_val = 0;
f4998e55
GU		 2355 min_err = err;
2356 brr = brr1;
2357 srr = srr1;
2358 cks = cks1;
2359 }
2360
2361done:
2362 if (best_clk >= 0)
2363 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2364 s->clks[best_clk], baud, min_err);
e108b2ca 2365
23241d43 2366 sci_port_enable(s);
36003386 2367
6af27bf2
GU		 2368 /*
2369 * Program the optional External Baud Rate Generator (BRG) first.
2370 * It controls the mux to select (H)SCK or frequency divided clock.
2371 */
1270f865
GU		 2372 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2373 serial_port_out(port, SCDL, dl);
6af27bf2 2374 serial_port_out(port, SCCKS, sccks);
1270f865 2375 }
1da177e4 2376
1be22663
TA		 2377 spin_lock_irqsave(&port->lock, flags);
2378
1ba76220 2379 sci_reset(port);
1da177e4
LT		 2380
2381 uart_update_timeout(port, termios->c_cflag, baud);
2382
f4998e55 2383 if (best_clk >= 0) {
92a05748
GU		 2384 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2385 switch (srr + 1) {
2386 case 5: smr_val |= SCSMR_SRC_5; break;
2387 case 7: smr_val |= SCSMR_SRC_7; break;
2388 case 11: smr_val |= SCSMR_SRC_11; break;
2389 case 13: smr_val |= SCSMR_SRC_13; break;
2390 case 16: smr_val |= SCSMR_SRC_16; break;
2391 case 17: smr_val |= SCSMR_SRC_17; break;
2392 case 19: smr_val |= SCSMR_SRC_19; break;
2393 case 27: smr_val |= SCSMR_SRC_27; break;
2394 }
f4998e55 2395 smr_val |= cks;
fa2abb03 2396 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
f4998e55
GU		 2397 serial_port_out(port, SCSMR, smr_val);
2398 serial_port_out(port, SCBRR, brr);
2399 if (sci_getreg(port, HSSRR)->size)
f303b364 2400 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
f4998e55
GU		 2401
2402 /* Wait one bit interval */
2403 udelay((1000000 + (baud - 1)) / baud);
2404 } else {
2405 /* Don't touch the bit rate configuration */
2406 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
3a964abe
GU		 2407 smr_val |= serial_port_in(port, SCSMR) &
2408 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
fa2abb03 2409 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
9d482cc3 2410 serial_port_out(port, SCSMR, smr_val);
f4998e55 2411 }
1da177e4 2412
d5701647 2413 sci_init_pins(port, termios->c_cflag);
0979e0e6 2414
33f50ffc
GU		 2415 port->status &= ~UPSTAT_AUTOCTS;
2416 s->autorts = false;
73c3d53f
PM		 2417 reg = sci_getreg(port, SCFCR);
2418 if (reg->size) {
b12bb29f 2419 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2420
33f50ffc
GU		 2421 if ((port->flags & UPF_HARD_FLOW) &&
2422 (termios->c_cflag & CRTSCTS)) {
2423 /* There is no CTS interrupt to restart the hardware */
2424 port->status |= UPSTAT_AUTOCTS;
2425 /* MCE is enabled when RTS is raised */
2426 s->autorts = true;
faf02f8f 2427 }
73c3d53f
PM		 2428
2429 /*
2430 * As we've done a sci_reset() above, ensure we don't
2431 * interfere with the FIFOs while toggling MCE. As the
2432 * reset values could still be set, simply mask them out.
2433 */
2434 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2435
b12bb29f 2436 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2437 }
5f76895e
GU		 2438 if (port->flags & UPF_HARD_FLOW) {
2439 /* Refresh (Auto) RTS */
2440 sci_set_mctrl(port, port->mctrl);
2441 }
b7a76e4b 2442
9f8325b3
LP		 2443 scr_val |= SCSCR_RE | SCSCR_TE |
2444 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 2445 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
92a05748
GU		 2446 if ((srr + 1 == 5) &&
2447 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2448 /*
2449 * In asynchronous mode, when the sampling rate is 1/5, first
2450 * received data may become invalid on some SCIFA and SCIFB.
2451 * To avoid this problem wait more than 1 serial data time (1
2452 * bit time x serial data number) after setting SCSCR.RE = 1.
2453 */
2454 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2455 }
1da177e4 2456
3089f381 2457 /*
5f6d8515 2458 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2459 * See serial_core.c::uart_update_timeout().
2460 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2461 * function calculates 1 jiffie for the data plus 5 jiffies for the
2462 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2463 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2464 * value obtained by this formula is too small. Therefore, if the value
2465 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381 2466 */
03940376
UH		 2467 /* byte size and parity */
2468 switch (termios->c_cflag & CSIZE) {
2469 case CS5:
2470 bits = 7;
2471 break;
2472 case CS6:
2473 bits = 8;
2474 break;
2475 case CS7:
2476 bits = 9;
2477 break;
2478 default:
2479 bits = 10;
2480 break;
2481 }
5f6d8515 2482
03940376
UH		 2483 if (termios->c_cflag & CSTOPB)
2484 bits++;
2485 if (termios->c_cflag & PARENB)
2486 bits++;
5f6d8515 2487
03940376
UH		 2488 s->rx_frame = (100 * bits * HZ) / (baud / 10);
2489#ifdef CONFIG_SERIAL_SH_SCI_DMA
2490 s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000);
03940376
UH		 2491 if (s->rx_timeout < msecs_to_jiffies(20))
2492 s->rx_timeout = msecs_to_jiffies(20);
3089f381
GL		 2493#endif
2494
1da177e4 2495 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2496 sci_start_rx(port);
36003386 2497
1be22663
TA		 2498 spin_unlock_irqrestore(&port->lock, flags);
2499
23241d43 2500 sci_port_disable(s);
f907c9ea
GU		 2501
2502 if (UART_ENABLE_MS(port, termios->c_cflag))
2503 sci_enable_ms(port);
1da177e4
LT		 2504}
2505
0174e5ca
TK		 2506static void sci_pm(struct uart_port *port, unsigned int state,
2507 unsigned int oldstate)
2508{
2509 struct sci_port *sci_port = to_sci_port(port);
2510
2511 switch (state) {
d3dfe5d9 2512 case UART_PM_STATE_OFF:
0174e5ca
TK		 2513 sci_port_disable(sci_port);
2514 break;
2515 default:
2516 sci_port_enable(sci_port);
2517 break;
2518 }
2519}
2520
1da177e4
LT		 2521static const char *sci_type(struct uart_port *port)
2522{
2523 switch (port->type) {
e7c98dc7
MT		 2524 case PORT_IRDA:
2525 return "irda";
2526 case PORT_SCI:
2527 return "sci";
2528 case PORT_SCIF:
2529 return "scif";
2530 case PORT_SCIFA:
2531 return "scifa";
d1d4b10c
GL		 2532 case PORT_SCIFB:
2533 return "scifb";
f303b364
UH		 2534 case PORT_HSCIF:
2535 return "hscif";
1da177e4
LT		 2536 }
2537
fa43972f 2538 return NULL;
1da177e4
LT		 2539}
2540
f6e9495d
PM		 2541static int sci_remap_port(struct uart_port *port)
2542{
e4d6f911 2543 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2544
2545 /*
2546 * Nothing to do if there's already an established membase.
2547 */
2548 if (port->membase)
2549 return 0;
2550
3d73f32b 2551 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e4d6f911 2552 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2553 if (unlikely(!port->membase)) {
2554 dev_err(port->dev, "can't remap port#%d\n", port->line);
2555 return -ENXIO;
2556 }
2557 } else {
2558 /*
2559 * For the simple (and majority of) cases where we don't
2560 * need to do any remapping, just cast the cookie
2561 * directly.
2562 */
3af4e960 2563 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2564 }
2565
2566 return 0;
2567}
2568
e2651647 2569static void sci_release_port(struct uart_port *port)
1da177e4 2570{
e4d6f911
YS		 2571 struct sci_port *sport = to_sci_port(port);
2572
3d73f32b 2573 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e2651647
PM		 2574 iounmap(port->membase);
2575 port->membase = NULL;
2576 }
2577
e4d6f911 2578 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2579}
2580
e2651647 2581static int sci_request_port(struct uart_port *port)
1da177e4 2582{
e2651647 2583 struct resource *res;
e4d6f911 2584 struct sci_port *sport = to_sci_port(port);
f6e9495d 2585 int ret;
1da177e4 2586
e4d6f911
YS		 2587 res = request_mem_region(port->mapbase, sport->reg_size,
2588 dev_name(port->dev));
2589 if (unlikely(res == NULL)) {
2590 dev_err(port->dev, "request_mem_region failed.");
e2651647 2591 return -EBUSY;
e4d6f911 2592 }
1da177e4 2593
f6e9495d
PM		 2594 ret = sci_remap_port(port);
2595 if (unlikely(ret != 0)) {
2596 release_resource(res);
2597 return ret;
7ff731ae 2598 }
e2651647
PM		 2599
2600 return 0;
2601}
2602
2603static void sci_config_port(struct uart_port *port, int flags)
2604{
2605 if (flags & UART_CONFIG_TYPE) {
2606 struct sci_port *sport = to_sci_port(port);
2607
2608 port->type = sport->cfg->type;
2609 sci_request_port(port);
2610 }
1da177e4
LT		 2611}
2612
2613static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2614{
1da177e4
LT		 2615 if (ser->baud_base < 2400)
2616 /* No paper tape reader for Mitch.. */
2617 return -EINVAL;
2618
2619 return 0;
2620}
2621
069a47e5 2622static const struct uart_ops sci_uart_ops = {
1da177e4
LT		 2623 .tx_empty = sci_tx_empty,
2624 .set_mctrl = sci_set_mctrl,
2625 .get_mctrl = sci_get_mctrl,
2626 .start_tx = sci_start_tx,
2627 .stop_tx = sci_stop_tx,
2628 .stop_rx = sci_stop_rx,
f907c9ea 2629 .enable_ms = sci_enable_ms,
1da177e4
LT		 2630 .break_ctl = sci_break_ctl,
2631 .startup = sci_startup,
2632 .shutdown = sci_shutdown,
1cf4a7ef 2633 .flush_buffer = sci_flush_buffer,
1da177e4 2634 .set_termios = sci_set_termios,
0174e5ca 2635 .pm = sci_pm,
1da177e4
LT		 2636 .type = sci_type,
2637 .release_port = sci_release_port,
2638 .request_port = sci_request_port,
2639 .config_port = sci_config_port,
2640 .verify_port = sci_verify_port,
07d2a1a1
PM		 2641#ifdef CONFIG_CONSOLE_POLL
2642 .poll_get_char = sci_poll_get_char,
2643 .poll_put_char = sci_poll_put_char,
2644#endif
1da177e4
LT		 2645};
2646
a9ec81f4
LP		 2647static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2648{
f4998e55
GU		 2649 const char *clk_names[] = {
2650 [SCI_FCK] = "fck",
6af27bf2 2651 [SCI_SCK] = "sck",
1270f865
GU		 2652 [SCI_BRG_INT] = "brg_int",
2653 [SCI_SCIF_CLK] = "scif_clk",
f4998e55
GU		 2654 };
2655 struct clk *clk;
2656 unsigned int i;
a9ec81f4 2657
6af27bf2
GU		 2658 if (sci_port->cfg->type == PORT_HSCIF)
2659 clk_names[SCI_SCK] = "hsck";
2660
f4998e55
GU		 2661 for (i = 0; i < SCI_NUM_CLKS; i++) {
2662 clk = devm_clk_get(dev, clk_names[i]);
2663 if (PTR_ERR(clk) == -EPROBE_DEFER)
2664 return -EPROBE_DEFER;
a9ec81f4 2665
f4998e55
GU		 2666 if (IS_ERR(clk) && i == SCI_FCK) {
2667 /*
2668 * "fck" used to be called "sci_ick", and we need to
2669 * maintain DT backward compatibility.
2670 */
2671 clk = devm_clk_get(dev, "sci_ick");
2672 if (PTR_ERR(clk) == -EPROBE_DEFER)
2673 return -EPROBE_DEFER;
a9ec81f4 2674
f4998e55
GU		 2675 if (!IS_ERR(clk))
2676 goto found;
a9ec81f4 2677
f4998e55
GU		 2678 /*
2679 * Not all SH platforms declare a clock lookup entry
2680 * for SCI devices, in which case we need to get the
2681 * global "peripheral_clk" clock.
2682 */
2683 clk = devm_clk_get(dev, "peripheral_clk");
2684 if (!IS_ERR(clk))
2685 goto found;
2686
2687 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2688 PTR_ERR(clk));
2689 return PTR_ERR(clk);
2690 }
2691
2692found:
2693 if (IS_ERR(clk))
2694 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2695 PTR_ERR(clk));
2696 else
2697 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2698 clk, clk);
2699 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2700 }
2701 return 0;
a9ec81f4
LP		 2702}
2703
daf5a895
LP		 2704static const struct sci_port_params *
2705sci_probe_regmap(const struct plat_sci_port *cfg)
2706{
2707 unsigned int regtype;
2708
2709 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2710 return &sci_port_params[cfg->regtype];
2711
2712 switch (cfg->type) {
2713 case PORT_SCI:
2714 regtype = SCIx_SCI_REGTYPE;
2715 break;
2716 case PORT_IRDA:
2717 regtype = SCIx_IRDA_REGTYPE;
2718 break;
2719 case PORT_SCIFA:
2720 regtype = SCIx_SCIFA_REGTYPE;
2721 break;
2722 case PORT_SCIFB:
2723 regtype = SCIx_SCIFB_REGTYPE;
2724 break;
2725 case PORT_SCIF:
2726 /*
2727 * The SH-4 is a bit of a misnomer here, although that's
2728 * where this particular port layout originated. This
2729 * configuration (or some slight variation thereof)
2730 * remains the dominant model for all SCIFs.
2731 */
2732 regtype = SCIx_SH4_SCIF_REGTYPE;
2733 break;
2734 case PORT_HSCIF:
2735 regtype = SCIx_HSCIF_REGTYPE;
2736 break;
2737 default:
2738 pr_err("Can't probe register map for given port\n");
2739 return NULL;
2740 }
2741
2742 return &sci_port_params[regtype];
2743}
2744
9671f099 2745static int sci_init_single(struct platform_device *dev,
1fcc91a6 2746 struct sci_port *sci_port, unsigned int index,
daf5a895 2747 const struct plat_sci_port *p, bool early)
e108b2ca 2748{
73a19e4c 2749 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2750 const struct resource *res;
2751 unsigned int i;
3127c6b2 2752 int ret;
e108b2ca 2753
50f0959a
PM		 2754 sci_port->cfg = p;
2755
73a19e4c
GL		 2756 port->ops = &sci_uart_ops;
2757 port->iotype = UPIO_MEM;
2758 port->line = index;
75136d48 2759
89b5c1ab
LP		 2760 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2761 if (res == NULL)
2762 return -ENOMEM;
1fcc91a6 2763
89b5c1ab 2764 port->mapbase = res->start;
e4d6f911 2765 sci_port->reg_size = resource_size(res);
1fcc91a6 2766
89b5c1ab
LP		 2767 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2768 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2769
89b5c1ab
LP		 2770 /* The SCI generates several interrupts. They can be muxed together or
2771 * connected to different interrupt lines. In the muxed case only one
2772 * interrupt resource is specified. In the non-muxed case three or four
2773 * interrupt resources are specified, as the BRI interrupt is optional.
2774 */
2775 if (sci_port->irqs[0] < 0)
2776 return -ENXIO;
1fcc91a6 2777
89b5c1ab
LP		 2778 if (sci_port->irqs[1] < 0) {
2779 sci_port->irqs[1] = sci_port->irqs[0];
2780 sci_port->irqs[2] = sci_port->irqs[0];
2781 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2782 }
2783
daf5a895
LP		 2784 sci_port->params = sci_probe_regmap(p);
2785 if (unlikely(sci_port->params == NULL))
2786 return -EINVAL;
e095ee6b 2787
18e8cf15
UH		 2788 switch (p->type) {
2789 case PORT_SCIFB:
2790 sci_port->rx_trigger = 48;
2791 break;
2792 case PORT_HSCIF:
2793 sci_port->rx_trigger = 64;
2794 break;
2795 case PORT_SCIFA:
2796 sci_port->rx_trigger = 32;
2797 break;
2798 case PORT_SCIF:
2799 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2800 /* RX triggering not implemented for this IP */
2801 sci_port->rx_trigger = 1;
2802 else
2803 sci_port->rx_trigger = 8;
2804 break;
2805 default:
2806 sci_port->rx_trigger = 1;
2807 break;
2808 }
2809
03940376 2810 sci_port->rx_fifo_timeout = 0;
fa2abb03 2811 sci_port->hscif_tot = 0;
03940376 2812
878fbb91
LP		 2813 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2814 * match the SoC datasheet, this should be investigated. Let platform
2815 * data override the sampling rate for now.
ec09c5eb 2816 */
b2f20ed9
LP		 2817 sci_port->sampling_rate_mask = p->sampling_rate
2818 ? SCI_SR(p->sampling_rate)
2819 : sci_port->params->sampling_rate_mask;
ec09c5eb 2820
1fcc91a6 2821 if (!early) {
a9ec81f4
LP		 2822 ret = sci_init_clocks(sci_port, &dev->dev);
2823 if (ret < 0)
2824 return ret;
c7ed1ab3 2825
73a19e4c 2826 port->dev = &dev->dev;
5e50d2d6
MD		 2827
2828 pm_runtime_enable(&dev->dev);
7b6fd3bf 2829 }
e108b2ca 2830
ce6738b6 2831 port->type = p->type;
3d73f32b 2832 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
b2f20ed9 2833 port->fifosize = sci_port->params->fifosize;
73a19e4c 2834
dfc80387
LP		 2835 if (port->type == PORT_SCI) {
2836 if (sci_port->reg_size >= 0x20)
2837 port->regshift = 2;
2838 else
2839 port->regshift = 1;
2840 }
2841
ce6738b6 2842 /*
61a6976b 2843 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2844 * for the multi-IRQ ports, which is where we are primarily
2845 * concerned with the shutdown path synchronization.
2846 *
2847 * For the muxed case there's nothing more to do.
2848 */
1fcc91a6 2849 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2850 port->irqflags = 0;
73a19e4c 2851
61a6976b
PM		 2852 port->serial_in = sci_serial_in;
2853 port->serial_out = sci_serial_out;
2854
c7ed1ab3 2855 return 0;
e108b2ca
PM		 2856}
2857
6dae1421
LP		 2858static void sci_cleanup_single(struct sci_port *port)
2859{
6dae1421
LP		 2860 pm_runtime_disable(port->port.dev);
2861}
2862
0b0cced1
YS		 2863#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2864 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
dc8e6f5b
MD		 2865static void serial_console_putchar(struct uart_port *port, int ch)
2866{
2867 sci_poll_put_char(port, ch);
2868}
2869
1da177e4
LT		 2870/*
2871 * Print a string to the serial port trying not to disturb
2872 * any possible real use of the port...
2873 */
2874static void serial_console_write(struct console *co, const char *s,
2875 unsigned count)
2876{
906b17dc
PM		 2877 struct sci_port *sci_port = &sci_ports[co->index];
2878 struct uart_port *port = &sci_port->port;
a67969b5 2879 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2880 unsigned long flags;
2881 int locked = 1;
2882
2883 local_irq_save(flags);
0b0cced1 2884#if defined(SUPPORT_SYSRQ)
40f70c03
SK		 2885 if (port->sysrq)
2886 locked = 0;
0b0cced1
YS		 2887 else
2888#endif
2889 if (oops_in_progress)
40f70c03
SK		 2890 locked = spin_trylock(&port->lock);
2891 else
2892 spin_lock(&port->lock);
2893
a67969b5 2894 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2895 ctrl = serial_port_in(port, SCSCR);
9f8325b3
LP		 2896 ctrl_temp = SCSCR_RE | SCSCR_TE |
2897 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
a67969b5 2898 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 2899 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
07d2a1a1 2900
501b825d 2901 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2902
2903 /* wait until fifo is empty and last bit has been transmitted */
2904 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2905 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2906 cpu_relax();
40f70c03
SK		 2907
2908 /* restore the SCSCR */
2909 serial_port_out(port, SCSCR, ctrl);
2910
2911 if (locked)
2912 spin_unlock(&port->lock);
2913 local_irq_restore(flags);
1da177e4
LT		 2914}
2915
9671f099 2916static int serial_console_setup(struct console *co, char *options)
1da177e4 2917{
dc8e6f5b 2918 struct sci_port *sci_port;
1da177e4
LT		 2919 struct uart_port *port;
2920 int baud = 115200;
2921 int bits = 8;
2922 int parity = 'n';
2923 int flow = 'n';
2924 int ret;
2925
e108b2ca 2926 /*
906b17dc 2927 * Refuse to handle any bogus ports.
1da177e4 2928 */
906b17dc 2929 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2930 return -ENODEV;
e108b2ca 2931
906b17dc
PM		 2932 sci_port = &sci_ports[co->index];
2933 port = &sci_port->port;
2934
b2267a6b
AC		 2935 /*
2936 * Refuse to handle uninitialized ports.
2937 */
2938 if (!port->ops)
2939 return -ENODEV;
2940
f6e9495d
PM		 2941 ret = sci_remap_port(port);
2942 if (unlikely(ret != 0))
2943 return ret;
e108b2ca 2944
1da177e4
LT		 2945 if (options)
2946 uart_parse_options(options, &baud, &parity, &bits, &flow);
2947
ab7cfb55 2948 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2949}
2950
2951static struct console serial_console = {
2952 .name = "ttySC",
906b17dc 2953 .device = uart_console_device,
1da177e4
LT		 2954 .write = serial_console_write,
2955 .setup = serial_console_setup,
fa5da2f7 2956 .flags = CON_PRINTBUFFER,
1da177e4 2957 .index = -1,
906b17dc 2958 .data = &sci_uart_driver,
1da177e4
LT		 2959};
2960
7b6fd3bf
MD		 2961static struct console early_serial_console = {
2962 .name = "early_ttySC",
2963 .write = serial_console_write,
2964 .flags = CON_PRINTBUFFER,
906b17dc 2965 .index = -1,
7b6fd3bf 2966};
ecdf8a46 2967
7b6fd3bf
MD		 2968static char early_serial_buf[32];
2969
9671f099 2970static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2971{
daf5a895 2972 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2973
2974 if (early_serial_console.data)
2975 return -EEXIST;
2976
2977 early_serial_console.index = pdev->id;
ecdf8a46 2978
1fcc91a6 2979 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2980
2981 serial_console_setup(&early_serial_console, early_serial_buf);
2982
2983 if (!strstr(early_serial_buf, "keep"))
2984 early_serial_console.flags |= CON_BOOT;
2985
2986 register_console(&early_serial_console);
2987 return 0;
2988}
6a8c9799
NI		 2989
2990#define SCI_CONSOLE (&serial_console)
2991
ecdf8a46 2992#else
9671f099 2993static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2994{
2995 return -EINVAL;
2996}
1da177e4 2997
6a8c9799
NI		 2998#define SCI_CONSOLE NULL
2999
0b0cced1 3000#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 3001
6c13d5d2 3002static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4 3003
352b9266 3004static DEFINE_MUTEX(sci_uart_registration_lock);
1da177e4
LT		 3005static struct uart_driver sci_uart_driver = {
3006 .owner = THIS_MODULE,
3007 .driver_name = "sci",
1da177e4
LT		 3008 .dev_name = "ttySC",
3009 .major = SCI_MAJOR,
3010 .minor = SCI_MINOR_START,
e108b2ca 3011 .nr = SCI_NPORTS,
1da177e4
LT		 3012 .cons = SCI_CONSOLE,
3013};
3014
54507f6e 3015static int sci_remove(struct platform_device *dev)
e552de24 3016{
d535a230 3017 struct sci_port *port = platform_get_drvdata(dev);
e552de24 3018
d535a230
PM		 3019 uart_remove_one_port(&sci_uart_driver, &port->port);
3020
6dae1421 3021 sci_cleanup_single(port);
e552de24 3022
5d23188a
UH		 3023 if (port->port.fifosize > 1) {
3024 sysfs_remove_file(&dev->dev.kobj,
3025 &dev_attr_rx_fifo_trigger.attr);
3026 }
fa2abb03
UH		 3027 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
3028 port->port.type == PORT_HSCIF) {
5d23188a
UH		 3029 sysfs_remove_file(&dev->dev.kobj,
3030 &dev_attr_rx_fifo_timeout.attr);
3031 }
3032
e552de24
MD		 3033 return 0;
3034}
3035
bd2238fb
GU		 3036
3037#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3038#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3039#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
20bdcab8
BH		 3040
3041static const struct of_device_id of_sci_match[] = {
f443ff80
GU		 3042 /* SoC-specific types */
3043 {
3044 .compatible = "renesas,scif-r7s72100",
3045 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3046 },
9ed44bb2
GU		 3047 /* Family-specific types */
3048 {
3049 .compatible = "renesas,rcar-gen1-scif",
3050 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3051 }, {
3052 .compatible = "renesas,rcar-gen2-scif",
3053 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3054 }, {
3055 .compatible = "renesas,rcar-gen3-scif",
3056 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3057 },
f443ff80 3058 /* Generic types */
20bdcab8
BH		 3059 {
3060 .compatible = "renesas,scif",
bd2238fb 3061 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
20bdcab8
BH		 3062 }, {
3063 .compatible = "renesas,scifa",
bd2238fb 3064 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
20bdcab8
BH		 3065 }, {
3066 .compatible = "renesas,scifb",
bd2238fb 3067 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
20bdcab8
BH		 3068 }, {
3069 .compatible = "renesas,hscif",
bd2238fb 3070 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
e1d0be61
YS		 3071 }, {
3072 .compatible = "renesas,sci",
bd2238fb 3073 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
20bdcab8
BH		 3074 }, {
3075 /* Terminator */
3076 },
3077};
3078MODULE_DEVICE_TABLE(of, of_sci_match);
3079
54b12c48
GU		 3080static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3081 unsigned int *dev_id)
20bdcab8
BH		 3082{
3083 struct device_node *np = pdev->dev.of_node;
20bdcab8 3084 struct plat_sci_port *p;
97ed9790 3085 struct sci_port *sp;
6e605a01 3086 const void *data;
20bdcab8
BH		 3087 int id;
3088
3089 if (!IS_ENABLED(CONFIG_OF) || !np)
3090 return NULL;
3091
6e605a01 3092 data = of_device_get_match_data(&pdev->dev);
20bdcab8 3093
20bdcab8 3094 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 3095 if (!p)
20bdcab8 3096 return NULL;
20bdcab8 3097
2095fc76 3098 /* Get the line number from the aliases node. */
20bdcab8
BH		 3099 id = of_alias_get_id(np, "serial");
3100 if (id < 0) {
3101 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3102 return NULL;
3103 }
3104
97ed9790 3105 sp = &sci_ports[id];
20bdcab8
BH		 3106 *dev_id = id;
3107
6e605a01
GU		 3108 p->type = SCI_OF_TYPE(data);
3109 p->regtype = SCI_OF_REGTYPE(data);
20bdcab8 3110
43c61286 3111 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
861a70ab 3112
20bdcab8
BH		 3113 return p;
3114}
3115
9671f099 3116static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 3117 unsigned int index,
3118 struct plat_sci_port *p,
3119 struct sci_port *sciport)
3120{
0ee70712
MD		 3121 int ret;
3122
3123 /* Sanity check */
3124 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 3125 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 3126 index+1, SCI_NPORTS);
9b971cd2 3127 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 3128 return -EINVAL;
0ee70712
MD		 3129 }
3130
352b9266
SS		 3131 mutex_lock(&sci_uart_registration_lock);
3132 if (!sci_uart_driver.state) {
3133 ret = uart_register_driver(&sci_uart_driver);
3134 if (ret) {
3135 mutex_unlock(&sci_uart_registration_lock);
3136 return ret;
3137 }
3138 }
3139 mutex_unlock(&sci_uart_registration_lock);
3140
1fcc91a6 3141 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 3142 if (ret)
3143 return ret;
0ee70712 3144
f907c9ea
GU		 3145 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3146 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3147 return PTR_ERR(sciport->gpios);
3148
97ed9790 3149 if (sciport->has_rtscts) {
f907c9ea
GU		 3150 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3151 UART_GPIO_CTS)) ||
3152 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3153 UART_GPIO_RTS))) {
3154 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3155 return -EINVAL;
3156 }
33f50ffc 3157 sciport->port.flags |= UPF_HARD_FLOW;
f907c9ea
GU		 3158 }
3159
6dae1421
LP		 3160 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3161 if (ret) {
3162 sci_cleanup_single(sciport);
3163 return ret;
3164 }
3165
3166 return 0;
0ee70712
MD		 3167}
3168
9671f099 3169static int sci_probe(struct platform_device *dev)
1da177e4 3170{
20bdcab8
BH		 3171 struct plat_sci_port *p;
3172 struct sci_port *sp;
3173 unsigned int dev_id;
ecdf8a46 3174 int ret;
d535a230 3175
ecdf8a46
PM		 3176 /*
3177 * If we've come here via earlyprintk initialization, head off to
3178 * the special early probe. We don't have sufficient device state
3179 * to make it beyond this yet.
3180 */
3181 if (is_early_platform_device(dev))
3182 return sci_probe_earlyprintk(dev);
7b6fd3bf 3183
20bdcab8
BH		 3184 if (dev->dev.of_node) {
3185 p = sci_parse_dt(dev, &dev_id);
3186 if (p == NULL)
3187 return -EINVAL;
3188 } else {
3189 p = dev->dev.platform_data;
3190 if (p == NULL) {
3191 dev_err(&dev->dev, "no platform data supplied\n");
3192 return -EINVAL;
3193 }
3194
3195 dev_id = dev->id;
3196 }
3197
3198 sp = &sci_ports[dev_id];
d535a230 3199 platform_set_drvdata(dev, sp);
e552de24 3200
20bdcab8 3201 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 3202 if (ret)
6dae1421 3203 return ret;
e552de24 3204
5d23188a
UH		 3205 if (sp->port.fifosize > 1) {
3206 ret = sysfs_create_file(&dev->dev.kobj,
3207 &dev_attr_rx_fifo_trigger.attr);
3208 if (ret)
3209 return ret;
3210 }
fa2abb03
UH		 3211 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3212 sp->port.type == PORT_HSCIF) {
5d23188a
UH		 3213 ret = sysfs_create_file(&dev->dev.kobj,
3214 &dev_attr_rx_fifo_timeout.attr);
3215 if (ret) {
3216 if (sp->port.fifosize > 1) {
3217 sysfs_remove_file(&dev->dev.kobj,
3218 &dev_attr_rx_fifo_trigger.attr);
3219 }
3220 return ret;
3221 }
3222 }
3223
1da177e4
LT		 3224#ifdef CONFIG_SH_STANDARD_BIOS
3225 sh_bios_gdb_detach();
3226#endif
3227
e108b2ca 3228 return 0;
1da177e4
LT		 3229}
3230
cb876341 3231static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 3232{
d535a230 3233 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3234
d535a230
PM		 3235 if (sport)
3236 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 3237
e108b2ca
PM		 3238 return 0;
3239}
1da177e4 3240
cb876341 3241static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 3242{
d535a230 3243 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3244
d535a230
PM		 3245 if (sport)
3246 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 3247
3248 return 0;
3249}
3250
cb876341 3251static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 3252
e108b2ca
PM		 3253static struct platform_driver sci_driver = {
3254 .probe = sci_probe,
b9e39c89 3255 .remove = sci_remove,
e108b2ca
PM		 3256 .driver = {
3257 .name = "sh-sci",
6daa79b3 3258 .pm = &sci_dev_pm_ops,
20bdcab8 3259 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 3260 },
3261};
3262
3263static int __init sci_init(void)
3264{
6c13d5d2 3265 pr_info("%s\n", banner);
e108b2ca 3266
352b9266 3267 return platform_driver_register(&sci_driver);
e108b2ca
PM		 3268}
3269
3270static void __exit sci_exit(void)
3271{
3272 platform_driver_unregister(&sci_driver);
352b9266
SS		 3273
3274 if (sci_uart_driver.state)
3275 uart_unregister_driver(&sci_uart_driver);
1da177e4
LT		 3276}
3277
7b6fd3bf
MD		 3278#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3279early_platform_init_buffer("earlyprintk", &sci_driver,
3280 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3281#endif
0b0cced1 3282#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
dd076cff 3283static struct plat_sci_port port_cfg __initdata;
0b0cced1
YS		 3284
3285static int __init early_console_setup(struct earlycon_device *device,
3286 int type)
3287{
3288 if (!device->port.membase)
3289 return -ENODEV;
3290
3291 device->port.serial_in = sci_serial_in;
3292 device->port.serial_out = sci_serial_out;
3293 device->port.type = type;
3294 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
daf5a895 3295 port_cfg.type = type;
0b0cced1 3296 sci_ports[0].cfg = &port_cfg;
daf5a895 3297 sci_ports[0].params = sci_probe_regmap(&port_cfg);
9f8325b3
LP		 3298 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3299 sci_serial_out(&sci_ports[0].port, SCSCR,
3300 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
0b0cced1
YS		 3301
3302 device->con->write = serial_console_write;
3303 return 0;
3304}
3305static int __init sci_early_console_setup(struct earlycon_device *device,
3306 const char *opt)
3307{
3308 return early_console_setup(device, PORT_SCI);
3309}
3310static int __init scif_early_console_setup(struct earlycon_device *device,
3311 const char *opt)
3312{
3313 return early_console_setup(device, PORT_SCIF);
3314}
3315static int __init scifa_early_console_setup(struct earlycon_device *device,
3316 const char *opt)
3317{
3318 return early_console_setup(device, PORT_SCIFA);
3319}
3320static int __init scifb_early_console_setup(struct earlycon_device *device,
3321 const char *opt)
3322{
3323 return early_console_setup(device, PORT_SCIFB);
3324}
3325static int __init hscif_early_console_setup(struct earlycon_device *device,
3326 const char *opt)
3327{
3328 return early_console_setup(device, PORT_HSCIF);
3329}
3330
0b0cced1 3331OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
0b0cced1 3332OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
0b0cced1 3333OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
0b0cced1 3334OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
0b0cced1
YS		 3335OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3336#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3337
1da177e4
LT		 3338module_init(sci_init);
3339module_exit(sci_exit);
3340
e108b2ca 3341MODULE_LICENSE("GPL");
e169c139 3342MODULE_ALIAS("platform:sh-sci");
7f405f9c 3343MODULE_AUTHOR("Paul Mundt");
f303b364 3344MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
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