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TTY: convert more flipping functions
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
1da177e4
LT		 26#include <linux/module.h>
27#include <linux/errno.h>
4dc4c516 28#include <linux/sh_dma.h>
1da177e4
LT		 29#include <linux/timer.h>
30#include <linux/interrupt.h>
31#include <linux/tty.h>
32#include <linux/tty_flip.h>
33#include <linux/serial.h>
34#include <linux/major.h>
35#include <linux/string.h>
36#include <linux/sysrq.h>
1da177e4
LT		 37#include <linux/ioport.h>
38#include <linux/mm.h>
1da177e4
LT		 39#include <linux/init.h>
40#include <linux/delay.h>
41#include <linux/console.h>
e108b2ca 42#include <linux/platform_device.h>
96de1a8f 43#include <linux/serial_sci.h>
1da177e4 44#include <linux/notifier.h>
5e50d2d6 45#include <linux/pm_runtime.h>
1da177e4 46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
73a19e4c 50#include <linux/dmaengine.h>
5beabc7f 51#include <linux/dma-mapping.h>
73a19e4c 52#include <linux/scatterlist.h>
5a0e3ad6 53#include <linux/slab.h>
50f0959a 54#include <linux/gpio.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
e108b2ca
PM		 62struct sci_port {
63 struct uart_port port;
64
ce6738b6
PM		 65 /* Platform configuration */
66 struct plat_sci_port *cfg;
e108b2ca 67
e108b2ca
PM		 68 /* Break timer */
69 struct timer_list break_timer;
70 int break_flag;
1534a3b3 71
501b825d
MD		 72 /* Interface clock */
73 struct clk *iclk;
c7ed1ab3
PM		 74 /* Function clock */
75 struct clk *fclk;
edad1f20 76
9174fc8f 77 char *irqstr[SCIx_NR_IRQS];
50f0959a 78 char *gpiostr[SCIx_NR_FNS];
9174fc8f 79
73a19e4c
GL		 80 struct dma_chan *chan_tx;
81 struct dma_chan *chan_rx;
f43dc23d 82
73a19e4c 83#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 84 struct dma_async_tx_descriptor *desc_tx;
85 struct dma_async_tx_descriptor *desc_rx[2];
86 dma_cookie_t cookie_tx;
87 dma_cookie_t cookie_rx[2];
88 dma_cookie_t active_rx;
89 struct scatterlist sg_tx;
90 unsigned int sg_len_tx;
91 struct scatterlist sg_rx[2];
92 size_t buf_len_rx;
93 struct sh_dmae_slave param_tx;
94 struct sh_dmae_slave param_rx;
95 struct work_struct work_tx;
96 struct work_struct work_rx;
97 struct timer_list rx_timer;
3089f381 98 unsigned int rx_timeout;
73a19e4c 99#endif
e552de24 100
d535a230 101 struct notifier_block freq_transition;
e108b2ca
PM		 102};
103
1da177e4 104/* Function prototypes */
d535a230 105static void sci_start_tx(struct uart_port *port);
b129a8cc 106static void sci_stop_tx(struct uart_port *port);
d535a230 107static void sci_start_rx(struct uart_port *port);
1da177e4 108
e108b2ca 109#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 110
e108b2ca
PM		 111static struct sci_port sci_ports[SCI_NPORTS];
112static struct uart_driver sci_uart_driver;
1da177e4 113
e7c98dc7
MT		 114static inline struct sci_port *
115to_sci_port(struct uart_port *uart)
116{
117 return container_of(uart, struct sci_port, port);
118}
119
61a6976b
PM		 120struct plat_sci_reg {
121 u8 offset, size;
122};
123
124/* Helper for invalidating specific entries of an inherited map. */
125#define sci_reg_invalid { .offset = 0, .size = 0 }
126
127static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
128 [SCIx_PROBE_REGTYPE] = {
129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
130 },
131
132 /*
133 * Common SCI definitions, dependent on the port's regshift
134 * value.
135 */
136 [SCIx_SCI_REGTYPE] = {
137 [SCSMR] = { 0x00, 8 },
138 [SCBRR] = { 0x01, 8 },
139 [SCSCR] = { 0x02, 8 },
140 [SCxTDR] = { 0x03, 8 },
141 [SCxSR] = { 0x04, 8 },
142 [SCxRDR] = { 0x05, 8 },
143 [SCFCR] = sci_reg_invalid,
144 [SCFDR] = sci_reg_invalid,
145 [SCTFDR] = sci_reg_invalid,
146 [SCRFDR] = sci_reg_invalid,
147 [SCSPTR] = sci_reg_invalid,
148 [SCLSR] = sci_reg_invalid,
149 },
150
151 /*
152 * Common definitions for legacy IrDA ports, dependent on
153 * regshift value.
154 */
155 [SCIx_IRDA_REGTYPE] = {
156 [SCSMR] = { 0x00, 8 },
157 [SCBRR] = { 0x01, 8 },
158 [SCSCR] = { 0x02, 8 },
159 [SCxTDR] = { 0x03, 8 },
160 [SCxSR] = { 0x04, 8 },
161 [SCxRDR] = { 0x05, 8 },
162 [SCFCR] = { 0x06, 8 },
163 [SCFDR] = { 0x07, 16 },
164 [SCTFDR] = sci_reg_invalid,
165 [SCRFDR] = sci_reg_invalid,
166 [SCSPTR] = sci_reg_invalid,
167 [SCLSR] = sci_reg_invalid,
168 },
169
170 /*
171 * Common SCIFA definitions.
172 */
173 [SCIx_SCIFA_REGTYPE] = {
174 [SCSMR] = { 0x00, 16 },
175 [SCBRR] = { 0x04, 8 },
176 [SCSCR] = { 0x08, 16 },
177 [SCxTDR] = { 0x20, 8 },
178 [SCxSR] = { 0x14, 16 },
179 [SCxRDR] = { 0x24, 8 },
180 [SCFCR] = { 0x18, 16 },
181 [SCFDR] = { 0x1c, 16 },
182 [SCTFDR] = sci_reg_invalid,
183 [SCRFDR] = sci_reg_invalid,
184 [SCSPTR] = sci_reg_invalid,
185 [SCLSR] = sci_reg_invalid,
186 },
187
188 /*
189 * Common SCIFB definitions.
190 */
191 [SCIx_SCIFB_REGTYPE] = {
192 [SCSMR] = { 0x00, 16 },
193 [SCBRR] = { 0x04, 8 },
194 [SCSCR] = { 0x08, 16 },
195 [SCxTDR] = { 0x40, 8 },
196 [SCxSR] = { 0x14, 16 },
197 [SCxRDR] = { 0x60, 8 },
198 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 199 [SCFDR] = sci_reg_invalid,
200 [SCTFDR] = { 0x38, 16 },
201 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 202 [SCSPTR] = sci_reg_invalid,
203 [SCLSR] = sci_reg_invalid,
204 },
205
3af1f8a4
PE		 206 /*
207 * Common SH-2(A) SCIF definitions for ports with FIFO data
208 * count registers.
209 */
210 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
211 [SCSMR] = { 0x00, 16 },
212 [SCBRR] = { 0x04, 8 },
213 [SCSCR] = { 0x08, 16 },
214 [SCxTDR] = { 0x0c, 8 },
215 [SCxSR] = { 0x10, 16 },
216 [SCxRDR] = { 0x14, 8 },
217 [SCFCR] = { 0x18, 16 },
218 [SCFDR] = { 0x1c, 16 },
219 [SCTFDR] = sci_reg_invalid,
220 [SCRFDR] = sci_reg_invalid,
221 [SCSPTR] = { 0x20, 16 },
222 [SCLSR] = { 0x24, 16 },
223 },
224
61a6976b
PM		 225 /*
226 * Common SH-3 SCIF definitions.
227 */
228 [SCIx_SH3_SCIF_REGTYPE] = {
229 [SCSMR] = { 0x00, 8 },
230 [SCBRR] = { 0x02, 8 },
231 [SCSCR] = { 0x04, 8 },
232 [SCxTDR] = { 0x06, 8 },
233 [SCxSR] = { 0x08, 16 },
234 [SCxRDR] = { 0x0a, 8 },
235 [SCFCR] = { 0x0c, 8 },
236 [SCFDR] = { 0x0e, 16 },
237 [SCTFDR] = sci_reg_invalid,
238 [SCRFDR] = sci_reg_invalid,
239 [SCSPTR] = sci_reg_invalid,
240 [SCLSR] = sci_reg_invalid,
241 },
242
243 /*
244 * Common SH-4(A) SCIF(B) definitions.
245 */
246 [SCIx_SH4_SCIF_REGTYPE] = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x0c, 8 },
251 [SCxSR] = { 0x10, 16 },
252 [SCxRDR] = { 0x14, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCFDR] = { 0x1c, 16 },
255 [SCTFDR] = sci_reg_invalid,
256 [SCRFDR] = sci_reg_invalid,
257 [SCSPTR] = { 0x20, 16 },
258 [SCLSR] = { 0x24, 16 },
259 },
260
261 /*
262 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
263 * register.
264 */
265 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
266 [SCSMR] = { 0x00, 16 },
267 [SCBRR] = { 0x04, 8 },
268 [SCSCR] = { 0x08, 16 },
269 [SCxTDR] = { 0x0c, 8 },
270 [SCxSR] = { 0x10, 16 },
271 [SCxRDR] = { 0x14, 8 },
272 [SCFCR] = { 0x18, 16 },
273 [SCFDR] = { 0x1c, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = sci_reg_invalid,
277 [SCLSR] = { 0x24, 16 },
278 },
279
280 /*
281 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
282 * count registers.
283 */
284 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
285 [SCSMR] = { 0x00, 16 },
286 [SCBRR] = { 0x04, 8 },
287 [SCSCR] = { 0x08, 16 },
288 [SCxTDR] = { 0x0c, 8 },
289 [SCxSR] = { 0x10, 16 },
290 [SCxRDR] = { 0x14, 8 },
291 [SCFCR] = { 0x18, 16 },
292 [SCFDR] = { 0x1c, 16 },
293 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
294 [SCRFDR] = { 0x20, 16 },
295 [SCSPTR] = { 0x24, 16 },
296 [SCLSR] = { 0x28, 16 },
297 },
298
299 /*
300 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
301 * registers.
302 */
303 [SCIx_SH7705_SCIF_REGTYPE] = {
304 [SCSMR] = { 0x00, 16 },
305 [SCBRR] = { 0x04, 8 },
306 [SCSCR] = { 0x08, 16 },
307 [SCxTDR] = { 0x20, 8 },
308 [SCxSR] = { 0x14, 16 },
309 [SCxRDR] = { 0x24, 8 },
310 [SCFCR] = { 0x18, 16 },
311 [SCFDR] = { 0x1c, 16 },
312 [SCTFDR] = sci_reg_invalid,
313 [SCRFDR] = sci_reg_invalid,
314 [SCSPTR] = sci_reg_invalid,
315 [SCLSR] = sci_reg_invalid,
316 },
317};
318
72b294cf
PM		 319#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
320
61a6976b
PM		 321/*
322 * The "offset" here is rather misleading, in that it refers to an enum
323 * value relative to the port mapping rather than the fixed offset
324 * itself, which needs to be manually retrieved from the platform's
325 * register map for the given port.
326 */
327static unsigned int sci_serial_in(struct uart_port *p, int offset)
328{
72b294cf 329 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 330
331 if (reg->size == 8)
332 return ioread8(p->membase + (reg->offset << p->regshift));
333 else if (reg->size == 16)
334 return ioread16(p->membase + (reg->offset << p->regshift));
335 else
336 WARN(1, "Invalid register access\n");
337
338 return 0;
339}
340
341static void sci_serial_out(struct uart_port *p, int offset, int value)
342{
72b294cf 343 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 344
345 if (reg->size == 8)
346 iowrite8(value, p->membase + (reg->offset << p->regshift));
347 else if (reg->size == 16)
348 iowrite16(value, p->membase + (reg->offset << p->regshift));
349 else
350 WARN(1, "Invalid register access\n");
351}
352
61a6976b
PM		 353static int sci_probe_regmap(struct plat_sci_port *cfg)
354{
355 switch (cfg->type) {
356 case PORT_SCI:
357 cfg->regtype = SCIx_SCI_REGTYPE;
358 break;
359 case PORT_IRDA:
360 cfg->regtype = SCIx_IRDA_REGTYPE;
361 break;
362 case PORT_SCIFA:
363 cfg->regtype = SCIx_SCIFA_REGTYPE;
364 break;
365 case PORT_SCIFB:
366 cfg->regtype = SCIx_SCIFB_REGTYPE;
367 break;
368 case PORT_SCIF:
369 /*
370 * The SH-4 is a bit of a misnomer here, although that's
371 * where this particular port layout originated. This
372 * configuration (or some slight variation thereof)
373 * remains the dominant model for all SCIFs.
374 */
375 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
376 break;
377 default:
378 printk(KERN_ERR "Can't probe register map for given port\n");
379 return -EINVAL;
380 }
381
382 return 0;
383}
384
23241d43
PM		 385static void sci_port_enable(struct sci_port *sci_port)
386{
387 if (!sci_port->port.dev)
388 return;
389
390 pm_runtime_get_sync(sci_port->port.dev);
391
392 clk_enable(sci_port->iclk);
393 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
394 clk_enable(sci_port->fclk);
395}
396
397static void sci_port_disable(struct sci_port *sci_port)
398{
399 if (!sci_port->port.dev)
400 return;
401
402 clk_disable(sci_port->fclk);
403 clk_disable(sci_port->iclk);
404
405 pm_runtime_put_sync(sci_port->port.dev);
406}
407
07d2a1a1 408#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 409
410#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 411static int sci_poll_get_char(struct uart_port *port)
1da177e4 412{
1da177e4
LT		 413 unsigned short status;
414 int c;
415
e108b2ca 416 do {
b12bb29f 417 status = serial_port_in(port, SCxSR);
1da177e4 418 if (status & SCxSR_ERRORS(port)) {
b12bb29f 419 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 420 continue;
421 }
3f255eb3
JW		 422 break;
423 } while (1);
424
425 if (!(status & SCxSR_RDxF(port)))
426 return NO_POLL_CHAR;
07d2a1a1 427
b12bb29f 428 c = serial_port_in(port, SCxRDR);
07d2a1a1 429
e7c98dc7 430 /* Dummy read */
b12bb29f
PM		 431 serial_port_in(port, SCxSR);
432 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 433
434 return c;
435}
1f6fd5c9 436#endif
1da177e4 437
07d2a1a1 438static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 439{
1da177e4
LT		 440 unsigned short status;
441
1da177e4 442 do {
b12bb29f 443 status = serial_port_in(port, SCxSR);
1da177e4
LT		 444 } while (!(status & SCxSR_TDxE(port)));
445
b12bb29f
PM		 446 serial_port_out(port, SCxTDR, c);
447 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 448}
07d2a1a1 449#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 450
61a6976b 451static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 452{
61a6976b
PM		 453 struct sci_port *s = to_sci_port(port);
454 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 455
61a6976b
PM		 456 /*
457 * Use port-specific handler if provided.
458 */
459 if (s->cfg->ops && s->cfg->ops->init_pins) {
460 s->cfg->ops->init_pins(port, cflag);
461 return;
1da177e4 462 }
41504c39 463
61a6976b
PM		 464 /*
465 * For the generic path SCSPTR is necessary. Bail out if that's
466 * unavailable, too.
467 */
468 if (!reg->size)
469 return;
41504c39 470
faf02f8f
PM		 471 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
472 ((!(cflag & CRTSCTS)))) {
473 unsigned short status;
474
b12bb29f 475 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 476 status &= ~SCSPTR_CTSIO;
477 status |= SCSPTR_RTSIO;
b12bb29f 478 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 479 }
d5701647 480}
e108b2ca 481
72b294cf 482static int sci_txfill(struct uart_port *port)
e108b2ca 483{
72b294cf 484 struct plat_sci_reg *reg;
e108b2ca 485
72b294cf
PM		 486 reg = sci_getreg(port, SCTFDR);
487 if (reg->size)
63f7ad11 488 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 489
72b294cf
PM		 490 reg = sci_getreg(port, SCFDR);
491 if (reg->size)
b12bb29f 492 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 493
b12bb29f 494 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 495}
496
73a19e4c
GL		 497static int sci_txroom(struct uart_port *port)
498{
72b294cf 499 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 500}
501
502static int sci_rxfill(struct uart_port *port)
e108b2ca 503{
72b294cf
PM		 504 struct plat_sci_reg *reg;
505
506 reg = sci_getreg(port, SCRFDR);
507 if (reg->size)
63f7ad11 508 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 509
510 reg = sci_getreg(port, SCFDR);
511 if (reg->size)
b12bb29f 512 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 513
b12bb29f 514 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 515}
516
514820eb
PM		 517/*
518 * SCI helper for checking the state of the muxed port/RXD pins.
519 */
520static inline int sci_rxd_in(struct uart_port *port)
521{
522 struct sci_port *s = to_sci_port(port);
523
524 if (s->cfg->port_reg <= 0)
525 return 1;
526
0dd4d5cb
PM		 527 /* Cast for ARM damage */
528 return !!__raw_readb((void __iomem *)s->cfg->port_reg);
514820eb
PM		 529}
530
1da177e4
LT		 531/* ********************************************************************** *
532 * the interrupt related routines *
533 * ********************************************************************** */
534
535static void sci_transmit_chars(struct uart_port *port)
536{
ebd2c8f6 537 struct circ_buf *xmit = &port->state->xmit;
1da177e4 538 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 539 unsigned short status;
540 unsigned short ctrl;
e108b2ca 541 int count;
1da177e4 542
b12bb29f 543 status = serial_port_in(port, SCxSR);
1da177e4 544 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 545 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 546 if (uart_circ_empty(xmit))
8e698614 547 ctrl &= ~SCSCR_TIE;
e7c98dc7 548 else
8e698614 549 ctrl |= SCSCR_TIE;
b12bb29f 550 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 551 return;
552 }
553
72b294cf 554 count = sci_txroom(port);
1da177e4
LT		 555
556 do {
557 unsigned char c;
558
559 if (port->x_char) {
560 c = port->x_char;
561 port->x_char = 0;
562 } else if (!uart_circ_empty(xmit) && !stopped) {
563 c = xmit->buf[xmit->tail];
564 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
565 } else {
566 break;
567 }
568
b12bb29f 569 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 570
571 port->icount.tx++;
572 } while (--count > 0);
573
b12bb29f 574 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 575
576 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
577 uart_write_wakeup(port);
578 if (uart_circ_empty(xmit)) {
b129a8cc 579 sci_stop_tx(port);
1da177e4 580 } else {
b12bb29f 581 ctrl = serial_port_in(port, SCSCR);
1da177e4 582
1a22f08d 583 if (port->type != PORT_SCI) {
b12bb29f
PM		 584 serial_port_in(port, SCxSR); /* Dummy read */
585 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4 586 }
1da177e4 587
8e698614 588 ctrl |= SCSCR_TIE;
b12bb29f 589 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 590 }
591}
592
593/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 594#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 595
94c8b6db 596static void sci_receive_chars(struct uart_port *port)
1da177e4 597{
e7c98dc7 598 struct sci_port *sci_port = to_sci_port(port);
227434f8
JS		 599 struct tty_port *tport = &port->state->port;
600 struct tty_struct *tty = tport->tty;
1da177e4
LT		 601 int i, count, copied = 0;
602 unsigned short status;
33f0f88f 603 unsigned char flag;
1da177e4 604
b12bb29f 605 status = serial_port_in(port, SCxSR);
1da177e4
LT		 606 if (!(status & SCxSR_RDxF(port)))
607 return;
608
609 while (1) {
1da177e4 610 /* Don't copy more bytes than there is room for in the buffer */
227434f8 611 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 612
613 /* If for any reason we can't copy more data, we're done! */
614 if (count == 0)
615 break;
616
617 if (port->type == PORT_SCI) {
b12bb29f 618 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 619 if (uart_handle_sysrq_char(port, c) ||
620 sci_port->break_flag)
1da177e4 621 count = 0;
e7c98dc7 622 else
e108b2ca 623 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 624 } else {
e7c98dc7 625 for (i = 0; i < count; i++) {
b12bb29f 626 char c = serial_port_in(port, SCxRDR);
d97fbbed 627
b12bb29f 628 status = serial_port_in(port, SCxSR);
1da177e4
LT		 629#if defined(CONFIG_CPU_SH3)
630 /* Skip "chars" during break */
e108b2ca 631 if (sci_port->break_flag) {
1da177e4
LT		 632 if ((c == 0) &&
633 (status & SCxSR_FER(port))) {
634 count--; i--;
635 continue;
636 }
e108b2ca 637
1da177e4 638 /* Nonzero => end-of-break */
762c69e3 639 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 640 sci_port->break_flag = 0;
641
1da177e4
LT		 642 if (STEPFN(c)) {
643 count--; i--;
644 continue;
645 }
646 }
647#endif /* CONFIG_CPU_SH3 */
7d12e780 648 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 649 count--; i--;
650 continue;
651 }
652
653 /* Store data and status */
73a19e4c 654 if (status & SCxSR_FER(port)) {
33f0f88f 655 flag = TTY_FRAME;
d97fbbed 656 port->icount.frame++;
762c69e3 657 dev_notice(port->dev, "frame error\n");
73a19e4c 658 } else if (status & SCxSR_PER(port)) {
33f0f88f 659 flag = TTY_PARITY;
d97fbbed 660 port->icount.parity++;
762c69e3 661 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 662 } else
663 flag = TTY_NORMAL;
762c69e3 664
33f0f88f 665 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 666 }
667 }
668
b12bb29f
PM		 669 serial_port_in(port, SCxSR); /* dummy read */
670 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4 671
1da177e4
LT		 672 copied += count;
673 port->icount.rx += count;
674 }
675
676 if (copied) {
677 /* Tell the rest of the system the news. New characters! */
678 tty_flip_buffer_push(tty);
679 } else {
b12bb29f
PM		 680 serial_port_in(port, SCxSR); /* dummy read */
681 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 682 }
683}
684
685#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 686
687/*
688 * The sci generates interrupts during the break,
1da177e4
LT		 689 * 1 per millisecond or so during the break period, for 9600 baud.
690 * So dont bother disabling interrupts.
691 * But dont want more than 1 break event.
692 * Use a kernel timer to periodically poll the rx line until
693 * the break is finished.
694 */
94c8b6db 695static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 696{
bc9b3f5c 697 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 698}
94c8b6db 699
1da177e4
LT		 700/* Ensure that two consecutive samples find the break over. */
701static void sci_break_timer(unsigned long data)
702{
e108b2ca
PM		 703 struct sci_port *port = (struct sci_port *)data;
704
23241d43 705 sci_port_enable(port);
5e50d2d6 706
e108b2ca 707 if (sci_rxd_in(&port->port) == 0) {
1da177e4 708 port->break_flag = 1;
e108b2ca
PM		 709 sci_schedule_break_timer(port);
710 } else if (port->break_flag == 1) {
1da177e4
LT		 711 /* break is over. */
712 port->break_flag = 2;
e108b2ca
PM		 713 sci_schedule_break_timer(port);
714 } else
715 port->break_flag = 0;
5e50d2d6 716
23241d43 717 sci_port_disable(port);
1da177e4
LT		 718}
719
94c8b6db 720static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 721{
722 int copied = 0;
b12bb29f 723 unsigned short status = serial_port_in(port, SCxSR);
ebd2c8f6 724 struct tty_struct *tty = port->state->port.tty;
debf9507 725 struct sci_port *s = to_sci_port(port);
1da177e4 726
debf9507
PM		 727 /*
728 * Handle overruns, if supported.
729 */
730 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
731 if (status & (1 << s->cfg->overrun_bit)) {
d97fbbed
PM		 732 port->icount.overrun++;
733
debf9507
PM		 734 /* overrun error */
735 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
736 copied++;
762c69e3 737
debf9507
PM		 738 dev_notice(port->dev, "overrun error");
739 }
1da177e4
LT		 740 }
741
e108b2ca 742 if (status & SCxSR_FER(port)) {
1da177e4
LT		 743 if (sci_rxd_in(port) == 0) {
744 /* Notify of BREAK */
e7c98dc7 745 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 746
747 if (!sci_port->break_flag) {
d97fbbed
PM		 748 port->icount.brk++;
749
e108b2ca
PM		 750 sci_port->break_flag = 1;
751 sci_schedule_break_timer(sci_port);
752
1da177e4 753 /* Do sysrq handling. */
e108b2ca 754 if (uart_handle_break(port))
1da177e4 755 return 0;
762c69e3
PM		 756
757 dev_dbg(port->dev, "BREAK detected\n");
758
e108b2ca 759 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 760 copied++;
761 }
762
e108b2ca 763 } else {
1da177e4 764 /* frame error */
d97fbbed
PM		 765 port->icount.frame++;
766
e108b2ca 767 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 768 copied++;
762c69e3
PM		 769
770 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 771 }
772 }
773
e108b2ca 774 if (status & SCxSR_PER(port)) {
1da177e4 775 /* parity error */
d97fbbed
PM		 776 port->icount.parity++;
777
e108b2ca
PM		 778 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
779 copied++;
762c69e3
PM		 780
781 dev_notice(port->dev, "parity error");
1da177e4
LT		 782 }
783
33f0f88f 784 if (copied)
1da177e4 785 tty_flip_buffer_push(tty);
1da177e4
LT		 786
787 return copied;
788}
789
94c8b6db 790static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 791{
ebd2c8f6 792 struct tty_struct *tty = port->state->port.tty;
debf9507 793 struct sci_port *s = to_sci_port(port);
4b8c59a3 794 struct plat_sci_reg *reg;
d830fa45
PM		 795 int copied = 0;
796
4b8c59a3
PM		 797 reg = sci_getreg(port, SCLSR);
798 if (!reg->size)
d830fa45
PM		 799 return 0;
800
b12bb29f
PM		 801 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
802 serial_port_out(port, SCLSR, 0);
d830fa45 803
d97fbbed
PM		 804 port->icount.overrun++;
805
d830fa45
PM		 806 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
807 tty_flip_buffer_push(tty);
808
809 dev_notice(port->dev, "overrun error\n");
810 copied++;
811 }
812
813 return copied;
814}
815
94c8b6db 816static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 817{
818 int copied = 0;
b12bb29f 819 unsigned short status = serial_port_in(port, SCxSR);
ebd2c8f6 820 struct tty_struct *tty = port->state->port.tty;
a5660ada 821 struct sci_port *s = to_sci_port(port);
1da177e4 822
0b3d4ef6
PM		 823 if (uart_handle_break(port))
824 return 0;
825
b7a76e4b 826 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 827#if defined(CONFIG_CPU_SH3)
828 /* Debounce break */
829 s->break_flag = 1;
830#endif
d97fbbed
PM		 831
832 port->icount.brk++;
833
1da177e4 834 /* Notify of BREAK */
e108b2ca 835 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 836 copied++;
762c69e3
PM		 837
838 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 839 }
840
33f0f88f 841 if (copied)
1da177e4 842 tty_flip_buffer_push(tty);
e108b2ca 843
d830fa45
PM		 844 copied += sci_handle_fifo_overrun(port);
845
1da177e4
LT		 846 return copied;
847}
848
73a19e4c 849static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 850{
73a19e4c
GL		 851#ifdef CONFIG_SERIAL_SH_SCI_DMA
852 struct uart_port *port = ptr;
853 struct sci_port *s = to_sci_port(port);
854
855 if (s->chan_rx) {
b12bb29f
PM		 856 u16 scr = serial_port_in(port, SCSCR);
857 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 858
859 /* Disable future Rx interrupts */
d1d4b10c 860 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 861 disable_irq_nosync(irq);
862 scr |= 0x4000;
863 } else {
f43dc23d 864 scr &= ~SCSCR_RIE;
3089f381 865 }
b12bb29f 866 serial_port_out(port, SCSCR, scr);
73a19e4c 867 /* Clear current interrupt */
b12bb29f 868 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 869 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
870 jiffies, s->rx_timeout);
871 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 872
873 return IRQ_HANDLED;
874 }
875#endif
876
1da177e4
LT		 877 /* I think sci_receive_chars has to be called irrespective
878 * of whether the I_IXOFF is set, otherwise, how is the interrupt
879 * to be disabled?
880 */
73a19e4c 881 sci_receive_chars(ptr);
1da177e4
LT		 882
883 return IRQ_HANDLED;
884}
885
7d12e780 886static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 887{
888 struct uart_port *port = ptr;
fd78a76a 889 unsigned long flags;
1da177e4 890
fd78a76a 891 spin_lock_irqsave(&port->lock, flags);
1da177e4 892 sci_transmit_chars(port);
fd78a76a 893 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 894
895 return IRQ_HANDLED;
896}
897
7d12e780 898static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 899{
900 struct uart_port *port = ptr;
901
902 /* Handle errors */
903 if (port->type == PORT_SCI) {
904 if (sci_handle_errors(port)) {
905 /* discard character in rx buffer */
b12bb29f
PM		 906 serial_port_in(port, SCxSR);
907 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 908 }
909 } else {
d830fa45 910 sci_handle_fifo_overrun(port);
7d12e780 911 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 912 }
913
b12bb29f 914 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 915
916 /* Kick the transmission */
7d12e780 917 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 918
919 return IRQ_HANDLED;
920}
921
7d12e780 922static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 923{
924 struct uart_port *port = ptr;
925
926 /* Handle BREAKs */
927 sci_handle_breaks(port);
b12bb29f 928 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 929
930 return IRQ_HANDLED;
931}
932
f43dc23d
PM		 933static inline unsigned long port_rx_irq_mask(struct uart_port *port)
934{
935 /*
936 * Not all ports (such as SCIFA) will support REIE. Rather than
937 * special-casing the port type, we check the port initialization
938 * IRQ enable mask to see whether the IRQ is desired at all. If
939 * it's unset, it's logically inferred that there's no point in
940 * testing for it.
941 */
ce6738b6 942 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 943}
944
7d12e780 945static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 946{
44e18e9e 947 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 948 struct uart_port *port = ptr;
73a19e4c 949 struct sci_port *s = to_sci_port(port);
a8884e34 950 irqreturn_t ret = IRQ_NONE;
1da177e4 951
b12bb29f
PM		 952 ssr_status = serial_port_in(port, SCxSR);
953 scr_status = serial_port_in(port, SCSCR);
f43dc23d 954 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 955
956 /* Tx Interrupt */
f43dc23d 957 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 958 !s->chan_tx)
a8884e34 959 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 960
73a19e4c
GL		 961 /*
962 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
963 * DR flags
964 */
965 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 966 (scr_status & SCSCR_RIE))
a8884e34 967 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 968
1da177e4 969 /* Error Interrupt */
dd4da3a5 970 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 971 ret = sci_er_interrupt(irq, ptr);
f43dc23d 972
1da177e4 973 /* Break Interrupt */
dd4da3a5 974 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 975 ret = sci_br_interrupt(irq, ptr);
1da177e4 976
a8884e34 977 return ret;
1da177e4
LT		 978}
979
1da177e4 980/*
25985edc 981 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 982 * ports' baud rate when the peripheral clock changes.
983 */
e108b2ca
PM		 984static int sci_notifier(struct notifier_block *self,
985 unsigned long phase, void *p)
1da177e4 986{
e552de24
MD		 987 struct sci_port *sci_port;
988 unsigned long flags;
1da177e4 989
d535a230
PM		 990 sci_port = container_of(self, struct sci_port, freq_transition);
991
1da177e4 992 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 993 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 994 struct uart_port *port = &sci_port->port;
073e84c9 995
d535a230
PM		 996 spin_lock_irqsave(&port->lock, flags);
997 port->uartclk = clk_get_rate(sci_port->iclk);
998 spin_unlock_irqrestore(&port->lock, flags);
e552de24 999 }
1da177e4 1000
1da177e4
LT		 1001 return NOTIFY_OK;
1002}
501b825d 1003
9174fc8f
PM		 1004static struct sci_irq_desc {
1005 const char *desc;
1006 irq_handler_t handler;
1007} sci_irq_desc[] = {
1008 /*
1009 * Split out handlers, the default case.
1010 */
1011 [SCIx_ERI_IRQ] = {
1012 .desc = "rx err",
1013 .handler = sci_er_interrupt,
1014 },
1015
1016 [SCIx_RXI_IRQ] = {
1017 .desc = "rx full",
1018 .handler = sci_rx_interrupt,
1019 },
1020
1021 [SCIx_TXI_IRQ] = {
1022 .desc = "tx empty",
1023 .handler = sci_tx_interrupt,
1024 },
1025
1026 [SCIx_BRI_IRQ] = {
1027 .desc = "break",
1028 .handler = sci_br_interrupt,
1029 },
1030
1031 /*
1032 * Special muxed handler.
1033 */
1034 [SCIx_MUX_IRQ] = {
1035 .desc = "mux",
1036 .handler = sci_mpxed_interrupt,
1037 },
1038};
1039
1da177e4
LT		 1040static int sci_request_irq(struct sci_port *port)
1041{
9174fc8f
PM		 1042 struct uart_port *up = &port->port;
1043 int i, j, ret = 0;
1044
1045 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1046 struct sci_irq_desc *desc;
1047 unsigned int irq;
1048
1049 if (SCIx_IRQ_IS_MUXED(port)) {
1050 i = SCIx_MUX_IRQ;
1051 irq = up->irq;
0e8963de 1052 } else {
9174fc8f
PM		 1053 irq = port->cfg->irqs[i];
1054
0e8963de
PM		 1055 /*
1056 * Certain port types won't support all of the
1057 * available interrupt sources.
1058 */
1059 if (unlikely(!irq))
1060 continue;
1061 }
1062
9174fc8f
PM		 1063 desc = sci_irq_desc + i;
1064 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1065 dev_name(up->dev), desc->desc);
1066 if (!port->irqstr[j]) {
1067 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1068 desc->desc);
1069 goto out_nomem;
1da177e4 1070 }
9174fc8f
PM		 1071
1072 ret = request_irq(irq, desc->handler, up->irqflags,
1073 port->irqstr[j], port);
1074 if (unlikely(ret)) {
1075 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1076 goto out_noirq;
1da177e4
LT		 1077 }
1078 }
1079
1080 return 0;
9174fc8f
PM		 1081
1082out_noirq:
1083 while (--i >= 0)
1084 free_irq(port->cfg->irqs[i], port);
1085
1086out_nomem:
1087 while (--j >= 0)
1088 kfree(port->irqstr[j]);
1089
1090 return ret;
1da177e4
LT		 1091}
1092
1093static void sci_free_irq(struct sci_port *port)
1094{
1095 int i;
1096
9174fc8f
PM		 1097 /*
1098 * Intentionally in reverse order so we iterate over the muxed
1099 * IRQ first.
1100 */
1101 for (i = 0; i < SCIx_NR_IRQS; i++) {
0e8963de
PM		 1102 unsigned int irq = port->cfg->irqs[i];
1103
1104 /*
1105 * Certain port types won't support all of the available
1106 * interrupt sources.
1107 */
1108 if (unlikely(!irq))
1109 continue;
1110
9174fc8f
PM		 1111 free_irq(port->cfg->irqs[i], port);
1112 kfree(port->irqstr[i]);
1da177e4 1113
9174fc8f
PM		 1114 if (SCIx_IRQ_IS_MUXED(port)) {
1115 /* If there's only one IRQ, we're done. */
1116 return;
1da177e4
LT		 1117 }
1118 }
1119}
1120
50f0959a
PM		 1121static const char *sci_gpio_names[SCIx_NR_FNS] = {
1122 "sck", "rxd", "txd", "cts", "rts",
1123};
1124
1125static const char *sci_gpio_str(unsigned int index)
1126{
1127 return sci_gpio_names[index];
1128}
1129
9671f099 1130static void sci_init_gpios(struct sci_port *port)
50f0959a
PM		 1131{
1132 struct uart_port *up = &port->port;
1133 int i;
1134
1135 if (!port->cfg)
1136 return;
1137
1138 for (i = 0; i < SCIx_NR_FNS; i++) {
1139 const char *desc;
1140 int ret;
1141
1142 if (!port->cfg->gpios[i])
1143 continue;
1144
1145 desc = sci_gpio_str(i);
1146
1147 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1148 dev_name(up->dev), desc);
1149
1150 /*
1151 * If we've failed the allocation, we can still continue
1152 * on with a NULL string.
1153 */
1154 if (!port->gpiostr[i])
1155 dev_notice(up->dev, "%s string allocation failure\n",
1156 desc);
1157
1158 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1159 if (unlikely(ret != 0)) {
1160 dev_notice(up->dev, "failed %s gpio request\n", desc);
1161
1162 /*
1163 * If we can't get the GPIO for whatever reason,
1164 * no point in keeping the verbose string around.
1165 */
1166 kfree(port->gpiostr[i]);
1167 }
1168 }
1169}
1170
1171static void sci_free_gpios(struct sci_port *port)
1172{
1173 int i;
1174
1175 for (i = 0; i < SCIx_NR_FNS; i++)
1176 if (port->cfg->gpios[i]) {
1177 gpio_free(port->cfg->gpios[i]);
1178 kfree(port->gpiostr[i]);
1179 }
1180}
1181
1da177e4
LT		 1182static unsigned int sci_tx_empty(struct uart_port *port)
1183{
b12bb29f 1184 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1185 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1186
1187 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1188}
1189
cdf7c42f
PM		 1190/*
1191 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1192 * CTS/RTS is supported in hardware by at least one port and controlled
1193 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1194 * handled via the ->init_pins() op, which is a bit of a one-way street,
1195 * lacking any ability to defer pin control -- this will later be
1196 * converted over to the GPIO framework).
dc7e3ef7
PM		 1197 *
1198 * Other modes (such as loopback) are supported generically on certain
1199 * port types, but not others. For these it's sufficient to test for the
1200 * existence of the support register and simply ignore the port type.
cdf7c42f 1201 */
1da177e4
LT		 1202static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1203{
dc7e3ef7
PM		 1204 if (mctrl & TIOCM_LOOP) {
1205 struct plat_sci_reg *reg;
1206
1207 /*
1208 * Standard loopback mode for SCFCR ports.
1209 */
1210 reg = sci_getreg(port, SCFCR);
1211 if (reg->size)
b12bb29f 1212 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
dc7e3ef7 1213 }
1da177e4
LT		 1214}
1215
1216static unsigned int sci_get_mctrl(struct uart_port *port)
1217{
cdf7c42f
PM		 1218 /*
1219 * CTS/RTS is handled in hardware when supported, while nothing
1220 * else is wired up. Keep it simple and simply assert DSR/CAR.
1221 */
1222 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1223}
1224
73a19e4c
GL		 1225#ifdef CONFIG_SERIAL_SH_SCI_DMA
1226static void sci_dma_tx_complete(void *arg)
1227{
1228 struct sci_port *s = arg;
1229 struct uart_port *port = &s->port;
1230 struct circ_buf *xmit = &port->state->xmit;
1231 unsigned long flags;
1232
1233 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1234
1235 spin_lock_irqsave(&port->lock, flags);
1236
f354a381 1237 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1238 xmit->tail &= UART_XMIT_SIZE - 1;
1239
f354a381 1240 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1241
1242 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1243 s->desc_tx = NULL;
1244
73a19e4c
GL		 1245 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1246 uart_write_wakeup(port);
1247
3089f381 1248 if (!uart_circ_empty(xmit)) {
49d4bcad 1249 s->cookie_tx = 0;
73a19e4c 1250 schedule_work(&s->work_tx);
49d4bcad
TY		 1251 } else {
1252 s->cookie_tx = -EINVAL;
1253 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1254 u16 ctrl = serial_port_in(port, SCSCR);
1255 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1256 }
3089f381
GL		 1257 }
1258
1259 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1260}
1261
1262/* Locking: called with port lock held */
1263static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1264 size_t count)
1265{
1266 struct uart_port *port = &s->port;
227434f8 1267 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1268 int i, active, room;
1269
227434f8 1270 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1271
1272 if (s->active_rx == s->cookie_rx[0]) {
1273 active = 0;
1274 } else if (s->active_rx == s->cookie_rx[1]) {
1275 active = 1;
1276 } else {
1277 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1278 return 0;
1279 }
1280
1281 if (room < count)
1282 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1283 count - room);
1284 if (!room)
1285 return room;
1286
1287 for (i = 0; i < room; i++)
1288 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1289 TTY_NORMAL);
1290
1291 port->icount.rx += room;
1292
1293 return room;
1294}
1295
1296static void sci_dma_rx_complete(void *arg)
1297{
1298 struct sci_port *s = arg;
1299 struct uart_port *port = &s->port;
1300 struct tty_struct *tty = port->state->port.tty;
1301 unsigned long flags;
1302 int count;
1303
3089f381 1304 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1305
1306 spin_lock_irqsave(&port->lock, flags);
1307
1308 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1309
3089f381 1310 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1311
1312 spin_unlock_irqrestore(&port->lock, flags);
1313
1314 if (count)
1315 tty_flip_buffer_push(tty);
1316
1317 schedule_work(&s->work_rx);
1318}
1319
73a19e4c
GL		 1320static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1321{
1322 struct dma_chan *chan = s->chan_rx;
1323 struct uart_port *port = &s->port;
73a19e4c
GL		 1324
1325 s->chan_rx = NULL;
1326 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1327 dma_release_channel(chan);
85b8e3ff
GL		 1328 if (sg_dma_address(&s->sg_rx[0]))
1329 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1330 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1331 if (enable_pio)
1332 sci_start_rx(port);
1333}
1334
1335static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1336{
1337 struct dma_chan *chan = s->chan_tx;
1338 struct uart_port *port = &s->port;
73a19e4c
GL		 1339
1340 s->chan_tx = NULL;
1341 s->cookie_tx = -EINVAL;
1342 dma_release_channel(chan);
1343 if (enable_pio)
1344 sci_start_tx(port);
1345}
1346
1347static void sci_submit_rx(struct sci_port *s)
1348{
1349 struct dma_chan *chan = s->chan_rx;
1350 int i;
1351
1352 for (i = 0; i < 2; i++) {
1353 struct scatterlist *sg = &s->sg_rx[i];
1354 struct dma_async_tx_descriptor *desc;
1355
16052827 1356 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1357 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1358
1359 if (desc) {
1360 s->desc_rx[i] = desc;
1361 desc->callback = sci_dma_rx_complete;
1362 desc->callback_param = s;
1363 s->cookie_rx[i] = desc->tx_submit(desc);
1364 }
1365
1366 if (!desc || s->cookie_rx[i] < 0) {
1367 if (i) {
1368 async_tx_ack(s->desc_rx[0]);
1369 s->cookie_rx[0] = -EINVAL;
1370 }
1371 if (desc) {
1372 async_tx_ack(desc);
1373 s->cookie_rx[i] = -EINVAL;
1374 }
1375 dev_warn(s->port.dev,
1376 "failed to re-start DMA, using PIO\n");
1377 sci_rx_dma_release(s, true);
1378 return;
1379 }
3089f381
GL		 1380 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1381 s->cookie_rx[i], i);
73a19e4c
GL		 1382 }
1383
1384 s->active_rx = s->cookie_rx[0];
1385
1386 dma_async_issue_pending(chan);
1387}
1388
1389static void work_fn_rx(struct work_struct *work)
1390{
1391 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1392 struct uart_port *port = &s->port;
1393 struct dma_async_tx_descriptor *desc;
1394 int new;
1395
1396 if (s->active_rx == s->cookie_rx[0]) {
1397 new = 0;
1398 } else if (s->active_rx == s->cookie_rx[1]) {
1399 new = 1;
1400 } else {
1401 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1402 return;
1403 }
1404 desc = s->desc_rx[new];
1405
1406 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1407 DMA_SUCCESS) {
1408 /* Handle incomplete DMA receive */
1409 struct tty_struct *tty = port->state->port.tty;
1410 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1411 struct shdma_desc *sh_desc = container_of(desc,
1412 struct shdma_desc, async_tx);
73a19e4c
GL		 1413 unsigned long flags;
1414 int count;
1415
05827630 1416 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1417 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1418 sh_desc->partial, sh_desc->cookie);
1419
1420 spin_lock_irqsave(&port->lock, flags);
1421 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1422 spin_unlock_irqrestore(&port->lock, flags);
1423
1424 if (count)
1425 tty_flip_buffer_push(tty);
1426
1427 sci_submit_rx(s);
1428
1429 return;
1430 }
1431
1432 s->cookie_rx[new] = desc->tx_submit(desc);
1433 if (s->cookie_rx[new] < 0) {
1434 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1435 sci_rx_dma_release(s, true);
1436 return;
1437 }
1438
73a19e4c 1439 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1440
1441 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1442 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1443}
1444
1445static void work_fn_tx(struct work_struct *work)
1446{
1447 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1448 struct dma_async_tx_descriptor *desc;
1449 struct dma_chan *chan = s->chan_tx;
1450 struct uart_port *port = &s->port;
1451 struct circ_buf *xmit = &port->state->xmit;
1452 struct scatterlist *sg = &s->sg_tx;
1453
1454 /*
1455 * DMA is idle now.
1456 * Port xmit buffer is already mapped, and it is one page... Just adjust
1457 * offsets and lengths. Since it is a circular buffer, we have to
1458 * transmit till the end, and then the rest. Take the port lock to get a
1459 * consistent xmit buffer state.
1460 */
1461 spin_lock_irq(&port->lock);
1462 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1463 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1464 sg->offset;
f354a381 1465 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1466 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1467 spin_unlock_irq(&port->lock);
1468
f354a381 1469 BUG_ON(!sg_dma_len(sg));
73a19e4c 1470
16052827 1471 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1472 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1473 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1474 if (!desc) {
1475 /* switch to PIO */
1476 sci_tx_dma_release(s, true);
1477 return;
1478 }
1479
1480 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1481
1482 spin_lock_irq(&port->lock);
1483 s->desc_tx = desc;
1484 desc->callback = sci_dma_tx_complete;
1485 desc->callback_param = s;
1486 spin_unlock_irq(&port->lock);
1487 s->cookie_tx = desc->tx_submit(desc);
1488 if (s->cookie_tx < 0) {
1489 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1490 /* switch to PIO */
1491 sci_tx_dma_release(s, true);
1492 return;
1493 }
1494
1495 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1496 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1497
1498 dma_async_issue_pending(chan);
1499}
1500#endif
1501
b129a8cc 1502static void sci_start_tx(struct uart_port *port)
1da177e4 1503{
3089f381 1504 struct sci_port *s = to_sci_port(port);
e108b2ca 1505 unsigned short ctrl;
1da177e4 1506
73a19e4c 1507#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1508 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1509 u16 new, scr = serial_port_in(port, SCSCR);
3089f381
GL		 1510 if (s->chan_tx)
1511 new = scr | 0x8000;
1512 else
1513 new = scr & ~0x8000;
1514 if (new != scr)
b12bb29f 1515 serial_port_out(port, SCSCR, new);
73a19e4c 1516 }
f43dc23d 1517
3089f381 1518 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
TY		 1519 s->cookie_tx < 0) {
1520 s->cookie_tx = 0;
3089f381 1521 schedule_work(&s->work_tx);
49d4bcad 1522 }
73a19e4c 1523#endif
f43dc23d 1524
d1d4b10c 1525 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1526 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1527 ctrl = serial_port_in(port, SCSCR);
1528 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1529 }
1da177e4
LT		 1530}
1531
b129a8cc 1532static void sci_stop_tx(struct uart_port *port)
1da177e4 1533{
1da177e4
LT		 1534 unsigned short ctrl;
1535
1536 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1537 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1538
d1d4b10c 1539 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1540 ctrl &= ~0x8000;
f43dc23d 1541
8e698614 1542 ctrl &= ~SCSCR_TIE;
f43dc23d 1543
b12bb29f 1544 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1545}
1546
73a19e4c 1547static void sci_start_rx(struct uart_port *port)
1da177e4 1548{
1da177e4
LT		 1549 unsigned short ctrl;
1550
b12bb29f 1551 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1552
d1d4b10c 1553 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1554 ctrl &= ~0x4000;
f43dc23d 1555
b12bb29f 1556 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1557}
1558
1559static void sci_stop_rx(struct uart_port *port)
1560{
1da177e4
LT		 1561 unsigned short ctrl;
1562
b12bb29f 1563 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1564
d1d4b10c 1565 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1566 ctrl &= ~0x4000;
f43dc23d
PM		 1567
1568 ctrl &= ~port_rx_irq_mask(port);
1569
b12bb29f 1570 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1571}
1572
1573static void sci_enable_ms(struct uart_port *port)
1574{
d39ec6ce
PM		 1575 /*
1576 * Not supported by hardware, always a nop.
1577 */
1da177e4
LT		 1578}
1579
1580static void sci_break_ctl(struct uart_port *port, int break_state)
1581{
bbb4ce50 1582 struct sci_port *s = to_sci_port(port);
a4e02f6d 1583 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1584 unsigned short scscr, scsptr;
1585
a4e02f6d
SY		 1586 /* check wheter the port has SCSPTR */
1587 if (!reg->size) {
bbb4ce50
SY		 1588 /*
1589 * Not supported by hardware. Most parts couple break and rx
1590 * interrupts together, with break detection always enabled.
1591 */
a4e02f6d 1592 return;
bbb4ce50 1593 }
a4e02f6d
SY		 1594
1595 scsptr = serial_port_in(port, SCSPTR);
1596 scscr = serial_port_in(port, SCSCR);
1597
1598 if (break_state == -1) {
1599 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1600 scscr &= ~SCSCR_TE;
1601 } else {
1602 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1603 scscr |= SCSCR_TE;
1604 }
1605
1606 serial_port_out(port, SCSPTR, scsptr);
1607 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1608}
1609
73a19e4c
GL		 1610#ifdef CONFIG_SERIAL_SH_SCI_DMA
1611static bool filter(struct dma_chan *chan, void *slave)
1612{
1613 struct sh_dmae_slave *param = slave;
1614
1615 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
d6fa5a4e 1616 param->shdma_slave.slave_id);
73a19e4c 1617
d6fa5a4e 1618 chan->private = &param->shdma_slave;
937bb6e4 1619 return true;
73a19e4c
GL		 1620}
1621
1622static void rx_timer_fn(unsigned long arg)
1623{
1624 struct sci_port *s = (struct sci_port *)arg;
1625 struct uart_port *port = &s->port;
b12bb29f 1626 u16 scr = serial_port_in(port, SCSCR);
3089f381 1627
d1d4b10c 1628 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1629 scr &= ~0x4000;
ce6738b6 1630 enable_irq(s->cfg->irqs[1]);
3089f381 1631 }
b12bb29f 1632 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1633 dev_dbg(port->dev, "DMA Rx timed out\n");
1634 schedule_work(&s->work_rx);
1635}
1636
1637static void sci_request_dma(struct uart_port *port)
1638{
1639 struct sci_port *s = to_sci_port(port);
1640 struct sh_dmae_slave *param;
1641 struct dma_chan *chan;
1642 dma_cap_mask_t mask;
1643 int nent;
1644
937bb6e4
GL		 1645 dev_dbg(port->dev, "%s: port %d\n", __func__,
1646 port->line);
73a19e4c 1647
937bb6e4 1648 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1649 return;
1650
1651 dma_cap_zero(mask);
1652 dma_cap_set(DMA_SLAVE, mask);
1653
1654 param = &s->param_tx;
1655
1656 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1657 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1658
1659 s->cookie_tx = -EINVAL;
1660 chan = dma_request_channel(mask, filter, param);
1661 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1662 if (chan) {
1663 s->chan_tx = chan;
1664 sg_init_table(&s->sg_tx, 1);
1665 /* UART circular tx buffer is an aligned page. */
1666 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1667 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1668 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1669 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1670 if (!nent)
1671 sci_tx_dma_release(s, false);
1672 else
1673 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1674 sg_dma_len(&s->sg_tx),
1675 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1676
1677 s->sg_len_tx = nent;
1678
1679 INIT_WORK(&s->work_tx, work_fn_tx);
1680 }
1681
1682 param = &s->param_rx;
1683
1684 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1685 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1686
1687 chan = dma_request_channel(mask, filter, param);
1688 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1689 if (chan) {
1690 dma_addr_t dma[2];
1691 void *buf[2];
1692 int i;
1693
1694 s->chan_rx = chan;
1695
1696 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1697 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1698 &dma[0], GFP_KERNEL);
1699
1700 if (!buf[0]) {
1701 dev_warn(port->dev,
1702 "failed to allocate dma buffer, using PIO\n");
1703 sci_rx_dma_release(s, true);
1704 return;
1705 }
1706
1707 buf[1] = buf[0] + s->buf_len_rx;
1708 dma[1] = dma[0] + s->buf_len_rx;
1709
1710 for (i = 0; i < 2; i++) {
1711 struct scatterlist *sg = &s->sg_rx[i];
1712
1713 sg_init_table(sg, 1);
1714 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1715 (int)buf[i] & ~PAGE_MASK);
f354a381 1716 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1717 }
1718
1719 INIT_WORK(&s->work_rx, work_fn_rx);
1720 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1721
1722 sci_submit_rx(s);
1723 }
1724}
1725
1726static void sci_free_dma(struct uart_port *port)
1727{
1728 struct sci_port *s = to_sci_port(port);
1729
73a19e4c
GL		 1730 if (s->chan_tx)
1731 sci_tx_dma_release(s, false);
1732 if (s->chan_rx)
1733 sci_rx_dma_release(s, false);
1734}
27bd1075
PM		 1735#else
1736static inline void sci_request_dma(struct uart_port *port)
1737{
1738}
1739
1740static inline void sci_free_dma(struct uart_port *port)
1741{
1742}
73a19e4c
GL		 1743#endif
1744
1da177e4
LT		 1745static int sci_startup(struct uart_port *port)
1746{
a5660ada 1747 struct sci_port *s = to_sci_port(port);
33b48e16 1748 unsigned long flags;
073e84c9 1749 int ret;
1da177e4 1750
73a19e4c
GL		 1751 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1752
073e84c9
PM		 1753 ret = sci_request_irq(s);
1754 if (unlikely(ret < 0))
1755 return ret;
1756
73a19e4c 1757 sci_request_dma(port);
073e84c9 1758
33b48e16 1759 spin_lock_irqsave(&port->lock, flags);
d656901b 1760 sci_start_tx(port);
73a19e4c 1761 sci_start_rx(port);
33b48e16 1762 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1763
1764 return 0;
1765}
1766
1767static void sci_shutdown(struct uart_port *port)
1768{
a5660ada 1769 struct sci_port *s = to_sci_port(port);
33b48e16 1770 unsigned long flags;
1da177e4 1771
73a19e4c
GL		 1772 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1773
33b48e16 1774 spin_lock_irqsave(&port->lock, flags);
1da177e4 1775 sci_stop_rx(port);
b129a8cc 1776 sci_stop_tx(port);
33b48e16 1777 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1778
73a19e4c 1779 sci_free_dma(port);
1da177e4 1780 sci_free_irq(s);
1da177e4
LT		 1781}
1782
26c92f37
PM		 1783static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1784 unsigned long freq)
1785{
1786 switch (algo_id) {
1787 case SCBRR_ALGO_1:
1788 return ((freq + 16 * bps) / (16 * bps) - 1);
1789 case SCBRR_ALGO_2:
1790 return ((freq + 16 * bps) / (32 * bps) - 1);
1791 case SCBRR_ALGO_3:
1792 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1793 case SCBRR_ALGO_4:
1794 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1795 case SCBRR_ALGO_5:
1796 return (((freq * 1000 / 32) / bps) - 1);
1797 }
1798
1799 /* Warn, but use a safe default */
1800 WARN_ON(1);
e8183a6c 1801
26c92f37
PM		 1802 return ((freq + 16 * bps) / (32 * bps) - 1);
1803}
1804
1ba76220
MD		 1805static void sci_reset(struct uart_port *port)
1806{
0979e0e6 1807 struct plat_sci_reg *reg;
1ba76220
MD		 1808 unsigned int status;
1809
1810 do {
b12bb29f 1811 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1812 } while (!(status & SCxSR_TEND(port)));
1813
b12bb29f 1814 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1815
0979e0e6
PM		 1816 reg = sci_getreg(port, SCFCR);
1817 if (reg->size)
b12bb29f 1818 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1819}
1820
606d099c
AC		 1821static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1822 struct ktermios *old)
1da177e4 1823{
00b9de9c 1824 struct sci_port *s = to_sci_port(port);
0979e0e6 1825 struct plat_sci_reg *reg;
9d482cc3 1826 unsigned int baud, smr_val, max_baud, cks;
a2159b52 1827 int t = -1;
1da177e4 1828
154280fd
MD		 1829 /*
1830 * earlyprintk comes here early on with port->uartclk set to zero.
1831 * the clock framework is not up and running at this point so here
1832 * we assume that 115200 is the maximum baud rate. please note that
1833 * the baud rate is not programmed during earlyprintk - it is assumed
1834 * that the previous boot loader has enabled required clocks and
1835 * setup the baud rate generator hardware for us already.
1836 */
1837 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1838
154280fd
MD		 1839 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1840 if (likely(baud && port->uartclk))
ce6738b6 1841 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1842
23241d43 1843 sci_port_enable(s);
36003386 1844
1ba76220 1845 sci_reset(port);
1da177e4 1846
b12bb29f 1847 smr_val = serial_port_in(port, SCSMR) & 3;
e8183a6c 1848
1da177e4
LT		 1849 if ((termios->c_cflag & CSIZE) == CS7)
1850 smr_val |= 0x40;
1851 if (termios->c_cflag & PARENB)
1852 smr_val |= 0x20;
1853 if (termios->c_cflag & PARODD)
1854 smr_val |= 0x30;
1855 if (termios->c_cflag & CSTOPB)
1856 smr_val |= 0x08;
1857
1858 uart_update_timeout(port, termios->c_cflag, baud);
1859
9d482cc3
TY		 1860 for (cks = 0; t >= 256 && cks <= 3; cks++)
1861 t >>= 2;
1da177e4 1862
9d482cc3
TY		 1863 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1864 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1865
4ffc3cdb 1866 if (t >= 0) {
9d482cc3 1867 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
b12bb29f 1868 serial_port_out(port, SCBRR, t);
1da177e4 1869 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1870 } else
1871 serial_port_out(port, SCSMR, smr_val);
1da177e4 1872
d5701647 1873 sci_init_pins(port, termios->c_cflag);
0979e0e6 1874
73c3d53f
PM		 1875 reg = sci_getreg(port, SCFCR);
1876 if (reg->size) {
b12bb29f 1877 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1878
73c3d53f 1879 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1880 if (termios->c_cflag & CRTSCTS)
1881 ctrl |= SCFCR_MCE;
1882 else
1883 ctrl &= ~SCFCR_MCE;
faf02f8f 1884 }
73c3d53f
PM		 1885
1886 /*
1887 * As we've done a sci_reset() above, ensure we don't
1888 * interfere with the FIFOs while toggling MCE. As the
1889 * reset values could still be set, simply mask them out.
1890 */
1891 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1892
b12bb29f 1893 serial_port_out(port, SCFCR, ctrl);
0979e0e6 1894 }
b7a76e4b 1895
b12bb29f 1896 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 1897
3089f381
GL		 1898#ifdef CONFIG_SERIAL_SH_SCI_DMA
1899 /*
1900 * Calculate delay for 1.5 DMA buffers: see
1901 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1902 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1903 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1904 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1905 * sizes), but it has been found out experimentally, that this is not
1906 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1907 * as a minimum seem to work perfectly.
1908 */
1909 if (s->chan_rx) {
1910 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1911 port->fifosize / 2;
1912 dev_dbg(port->dev,
1913 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1914 s->rx_timeout * 1000 / HZ, port->timeout);
1915 if (s->rx_timeout < msecs_to_jiffies(20))
1916 s->rx_timeout = msecs_to_jiffies(20);
1917 }
1918#endif
1919
1da177e4 1920 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1921 sci_start_rx(port);
36003386 1922
23241d43 1923 sci_port_disable(s);
1da177e4
LT		 1924}
1925
0174e5ca
TK		 1926static void sci_pm(struct uart_port *port, unsigned int state,
1927 unsigned int oldstate)
1928{
1929 struct sci_port *sci_port = to_sci_port(port);
1930
1931 switch (state) {
1932 case 3:
1933 sci_port_disable(sci_port);
1934 break;
1935 default:
1936 sci_port_enable(sci_port);
1937 break;
1938 }
1939}
1940
1da177e4
LT		 1941static const char *sci_type(struct uart_port *port)
1942{
1943 switch (port->type) {
e7c98dc7
MT		 1944 case PORT_IRDA:
1945 return "irda";
1946 case PORT_SCI:
1947 return "sci";
1948 case PORT_SCIF:
1949 return "scif";
1950 case PORT_SCIFA:
1951 return "scifa";
d1d4b10c
GL		 1952 case PORT_SCIFB:
1953 return "scifb";
1da177e4
LT		 1954 }
1955
fa43972f 1956 return NULL;
1da177e4
LT		 1957}
1958
e2651647 1959static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1960{
e2651647
PM		 1961 /*
1962 * Pick an arbitrary size that encapsulates all of the base
1963 * registers by default. This can be optimized later, or derived
1964 * from platform resource data at such a time that ports begin to
1965 * behave more erratically.
1966 */
1967 return 64;
1da177e4
LT		 1968}
1969
f6e9495d
PM		 1970static int sci_remap_port(struct uart_port *port)
1971{
1972 unsigned long size = sci_port_size(port);
1973
1974 /*
1975 * Nothing to do if there's already an established membase.
1976 */
1977 if (port->membase)
1978 return 0;
1979
1980 if (port->flags & UPF_IOREMAP) {
1981 port->membase = ioremap_nocache(port->mapbase, size);
1982 if (unlikely(!port->membase)) {
1983 dev_err(port->dev, "can't remap port#%d\n", port->line);
1984 return -ENXIO;
1985 }
1986 } else {
1987 /*
1988 * For the simple (and majority of) cases where we don't
1989 * need to do any remapping, just cast the cookie
1990 * directly.
1991 */
1992 port->membase = (void __iomem *)port->mapbase;
1993 }
1994
1995 return 0;
1996}
1997
e2651647 1998static void sci_release_port(struct uart_port *port)
1da177e4 1999{
e2651647
PM		 2000 if (port->flags & UPF_IOREMAP) {
2001 iounmap(port->membase);
2002 port->membase = NULL;
2003 }
2004
2005 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 2006}
2007
e2651647 2008static int sci_request_port(struct uart_port *port)
1da177e4 2009{
e2651647
PM		 2010 unsigned long size = sci_port_size(port);
2011 struct resource *res;
f6e9495d 2012 int ret;
1da177e4 2013
1020520e 2014 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 2015 if (unlikely(res == NULL))
2016 return -EBUSY;
1da177e4 2017
f6e9495d
PM		 2018 ret = sci_remap_port(port);
2019 if (unlikely(ret != 0)) {
2020 release_resource(res);
2021 return ret;
7ff731ae 2022 }
e2651647
PM		 2023
2024 return 0;
2025}
2026
2027static void sci_config_port(struct uart_port *port, int flags)
2028{
2029 if (flags & UART_CONFIG_TYPE) {
2030 struct sci_port *sport = to_sci_port(port);
2031
2032 port->type = sport->cfg->type;
2033 sci_request_port(port);
2034 }
1da177e4
LT		 2035}
2036
2037static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2038{
a5660ada 2039 struct sci_port *s = to_sci_port(port);
1da177e4 2040
ce6738b6 2041 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 2042 return -EINVAL;
2043 if (ser->baud_base < 2400)
2044 /* No paper tape reader for Mitch.. */
2045 return -EINVAL;
2046
2047 return 0;
2048}
2049
2050static struct uart_ops sci_uart_ops = {
2051 .tx_empty = sci_tx_empty,
2052 .set_mctrl = sci_set_mctrl,
2053 .get_mctrl = sci_get_mctrl,
2054 .start_tx = sci_start_tx,
2055 .stop_tx = sci_stop_tx,
2056 .stop_rx = sci_stop_rx,
2057 .enable_ms = sci_enable_ms,
2058 .break_ctl = sci_break_ctl,
2059 .startup = sci_startup,
2060 .shutdown = sci_shutdown,
2061 .set_termios = sci_set_termios,
0174e5ca 2062 .pm = sci_pm,
1da177e4
LT		 2063 .type = sci_type,
2064 .release_port = sci_release_port,
2065 .request_port = sci_request_port,
2066 .config_port = sci_config_port,
2067 .verify_port = sci_verify_port,
07d2a1a1
PM		 2068#ifdef CONFIG_CONSOLE_POLL
2069 .poll_get_char = sci_poll_get_char,
2070 .poll_put_char = sci_poll_put_char,
2071#endif
1da177e4
LT		 2072};
2073
9671f099 2074static int sci_init_single(struct platform_device *dev,
c7ed1ab3
PM		 2075 struct sci_port *sci_port,
2076 unsigned int index,
2077 struct plat_sci_port *p)
e108b2ca 2078{
73a19e4c 2079 struct uart_port *port = &sci_port->port;
3127c6b2 2080 int ret;
e108b2ca 2081
50f0959a
PM		 2082 sci_port->cfg = p;
2083
73a19e4c
GL		 2084 port->ops = &sci_uart_ops;
2085 port->iotype = UPIO_MEM;
2086 port->line = index;
75136d48
MP		 2087
2088 switch (p->type) {
d1d4b10c
GL		 2089 case PORT_SCIFB:
2090 port->fifosize = 256;
2091 break;
75136d48 2092 case PORT_SCIFA:
73a19e4c 2093 port->fifosize = 64;
75136d48
MP		 2094 break;
2095 case PORT_SCIF:
73a19e4c 2096 port->fifosize = 16;
75136d48
MP		 2097 break;
2098 default:
73a19e4c 2099 port->fifosize = 1;
75136d48
MP		 2100 break;
2101 }
7b6fd3bf 2102
3127c6b2
PM		 2103 if (p->regtype == SCIx_PROBE_REGTYPE) {
2104 ret = sci_probe_regmap(p);
fc97114b 2105 if (unlikely(ret))
3127c6b2
PM		 2106 return ret;
2107 }
61a6976b 2108
7b6fd3bf 2109 if (dev) {
c7ed1ab3
PM		 2110 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2111 if (IS_ERR(sci_port->iclk)) {
2112 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2113 if (IS_ERR(sci_port->iclk)) {
2114 dev_err(&dev->dev, "can't get iclk\n");
2115 return PTR_ERR(sci_port->iclk);
2116 }
2117 }
2118
2119 /*
2120 * The function clock is optional, ignore it if we can't
2121 * find it.
2122 */
2123 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2124 if (IS_ERR(sci_port->fclk))
2125 sci_port->fclk = NULL;
2126
73a19e4c 2127 port->dev = &dev->dev;
5e50d2d6 2128
50f0959a
PM		 2129 sci_init_gpios(sci_port);
2130
5e50d2d6 2131 pm_runtime_enable(&dev->dev);
7b6fd3bf 2132 }
e108b2ca 2133
7ed7e071
MD		 2134 sci_port->break_timer.data = (unsigned long)sci_port;
2135 sci_port->break_timer.function = sci_break_timer;
2136 init_timer(&sci_port->break_timer);
2137
debf9507
PM		 2138 /*
2139 * Establish some sensible defaults for the error detection.
2140 */
2141 if (!p->error_mask)
2142 p->error_mask = (p->type == PORT_SCI) ?
2143 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2144
2145 /*
2146 * Establish sensible defaults for the overrun detection, unless
2147 * the part has explicitly disabled support for it.
2148 */
2149 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2150 if (p->type == PORT_SCI)
2151 p->overrun_bit = 5;
2152 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2153 p->overrun_bit = 9;
2154 else
2155 p->overrun_bit = 0;
2156
2157 /*
2158 * Make the error mask inclusive of overrun detection, if
2159 * supported.
2160 */
2161 p->error_mask |= (1 << p->overrun_bit);
2162 }
2163
ce6738b6
PM		 2164 port->mapbase = p->mapbase;
2165 port->type = p->type;
f43dc23d 2166 port->flags = p->flags;
61a6976b 2167 port->regshift = p->regshift;
73a19e4c 2168
ce6738b6 2169 /*
61a6976b 2170 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2171 * for the multi-IRQ ports, which is where we are primarily
2172 * concerned with the shutdown path synchronization.
2173 *
2174 * For the muxed case there's nothing more to do.
2175 */
54aa89ea 2176 port->irq = p->irqs[SCIx_RXI_IRQ];
9cfb5c05 2177 port->irqflags = 0;
73a19e4c 2178
61a6976b
PM		 2179 port->serial_in = sci_serial_in;
2180 port->serial_out = sci_serial_out;
2181
937bb6e4
GL		 2182 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2183 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2184 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2185
c7ed1ab3 2186 return 0;
e108b2ca
PM		 2187}
2188
6dae1421
LP		 2189static void sci_cleanup_single(struct sci_port *port)
2190{
2191 sci_free_gpios(port);
2192
2193 clk_put(port->iclk);
2194 clk_put(port->fclk);
2195
2196 pm_runtime_disable(port->port.dev);
2197}
2198
1da177e4 2199#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2200static void serial_console_putchar(struct uart_port *port, int ch)
2201{
2202 sci_poll_put_char(port, ch);
2203}
2204
1da177e4
LT		 2205/*
2206 * Print a string to the serial port trying not to disturb
2207 * any possible real use of the port...
2208 */
2209static void serial_console_write(struct console *co, const char *s,
2210 unsigned count)
2211{
906b17dc
PM		 2212 struct sci_port *sci_port = &sci_ports[co->index];
2213 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2214 unsigned short bits, ctrl;
2215 unsigned long flags;
2216 int locked = 1;
2217
2218 local_irq_save(flags);
2219 if (port->sysrq)
2220 locked = 0;
2221 else if (oops_in_progress)
2222 locked = spin_trylock(&port->lock);
2223 else
2224 spin_lock(&port->lock);
2225
2226 /* first save the SCSCR then disable the interrupts */
2227 ctrl = serial_port_in(port, SCSCR);
2228 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2229
501b825d 2230 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2231
2232 /* wait until fifo is empty and last bit has been transmitted */
2233 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2234 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2235 cpu_relax();
40f70c03
SK		 2236
2237 /* restore the SCSCR */
2238 serial_port_out(port, SCSCR, ctrl);
2239
2240 if (locked)
2241 spin_unlock(&port->lock);
2242 local_irq_restore(flags);
1da177e4
LT		 2243}
2244
9671f099 2245static int serial_console_setup(struct console *co, char *options)
1da177e4 2246{
dc8e6f5b 2247 struct sci_port *sci_port;
1da177e4
LT		 2248 struct uart_port *port;
2249 int baud = 115200;
2250 int bits = 8;
2251 int parity = 'n';
2252 int flow = 'n';
2253 int ret;
2254
e108b2ca 2255 /*
906b17dc 2256 * Refuse to handle any bogus ports.
1da177e4 2257 */
906b17dc 2258 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2259 return -ENODEV;
e108b2ca 2260
906b17dc
PM		 2261 sci_port = &sci_ports[co->index];
2262 port = &sci_port->port;
2263
b2267a6b
AC		 2264 /*
2265 * Refuse to handle uninitialized ports.
2266 */
2267 if (!port->ops)
2268 return -ENODEV;
2269
f6e9495d
PM		 2270 ret = sci_remap_port(port);
2271 if (unlikely(ret != 0))
2272 return ret;
e108b2ca 2273
1da177e4
LT		 2274 if (options)
2275 uart_parse_options(options, &baud, &parity, &bits, &flow);
2276
ab7cfb55 2277 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2278}
2279
2280static struct console serial_console = {
2281 .name = "ttySC",
906b17dc 2282 .device = uart_console_device,
1da177e4
LT		 2283 .write = serial_console_write,
2284 .setup = serial_console_setup,
fa5da2f7 2285 .flags = CON_PRINTBUFFER,
1da177e4 2286 .index = -1,
906b17dc 2287 .data = &sci_uart_driver,
1da177e4
LT		 2288};
2289
7b6fd3bf
MD		 2290static struct console early_serial_console = {
2291 .name = "early_ttySC",
2292 .write = serial_console_write,
2293 .flags = CON_PRINTBUFFER,
906b17dc 2294 .index = -1,
7b6fd3bf 2295};
ecdf8a46 2296
7b6fd3bf
MD		 2297static char early_serial_buf[32];
2298
9671f099 2299static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2300{
2301 struct plat_sci_port *cfg = pdev->dev.platform_data;
2302
2303 if (early_serial_console.data)
2304 return -EEXIST;
2305
2306 early_serial_console.index = pdev->id;
ecdf8a46 2307
906b17dc 2308 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 2309
2310 serial_console_setup(&early_serial_console, early_serial_buf);
2311
2312 if (!strstr(early_serial_buf, "keep"))
2313 early_serial_console.flags |= CON_BOOT;
2314
2315 register_console(&early_serial_console);
2316 return 0;
2317}
6a8c9799
NI		 2318
2319#define SCI_CONSOLE (&serial_console)
2320
ecdf8a46 2321#else
9671f099 2322static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2323{
2324 return -EINVAL;
2325}
1da177e4 2326
6a8c9799
NI		 2327#define SCI_CONSOLE NULL
2328
2329#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2330
2331static char banner[] __initdata =
2332 KERN_INFO "SuperH SCI(F) driver initialized\n";
2333
2334static struct uart_driver sci_uart_driver = {
2335 .owner = THIS_MODULE,
2336 .driver_name = "sci",
1da177e4
LT		 2337 .dev_name = "ttySC",
2338 .major = SCI_MAJOR,
2339 .minor = SCI_MINOR_START,
e108b2ca 2340 .nr = SCI_NPORTS,
1da177e4
LT		 2341 .cons = SCI_CONSOLE,
2342};
2343
54507f6e 2344static int sci_remove(struct platform_device *dev)
e552de24 2345{
d535a230 2346 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2347
d535a230
PM		 2348 cpufreq_unregister_notifier(&port->freq_transition,
2349 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2350
d535a230
PM		 2351 uart_remove_one_port(&sci_uart_driver, &port->port);
2352
6dae1421 2353 sci_cleanup_single(port);
e552de24 2354
e552de24
MD		 2355 return 0;
2356}
2357
9671f099 2358static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2359 unsigned int index,
2360 struct plat_sci_port *p,
2361 struct sci_port *sciport)
2362{
0ee70712
MD		 2363 int ret;
2364
2365 /* Sanity check */
2366 if (unlikely(index >= SCI_NPORTS)) {
2367 dev_notice(&dev->dev, "Attempting to register port "
2368 "%d when only %d are available.\n",
2369 index+1, SCI_NPORTS);
2370 dev_notice(&dev->dev, "Consider bumping "
2371 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2372 return -EINVAL;
0ee70712
MD		 2373 }
2374
c7ed1ab3
PM		 2375 ret = sci_init_single(dev, sciport, index, p);
2376 if (ret)
2377 return ret;
0ee70712 2378
6dae1421
LP		 2379 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2380 if (ret) {
2381 sci_cleanup_single(sciport);
2382 return ret;
2383 }
2384
2385 return 0;
0ee70712
MD		 2386}
2387
9671f099 2388static int sci_probe(struct platform_device *dev)
1da177e4 2389{
e108b2ca 2390 struct plat_sci_port *p = dev->dev.platform_data;
d535a230 2391 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2392 int ret;
d535a230 2393
ecdf8a46
PM		 2394 /*
2395 * If we've come here via earlyprintk initialization, head off to
2396 * the special early probe. We don't have sufficient device state
2397 * to make it beyond this yet.
2398 */
2399 if (is_early_platform_device(dev))
2400 return sci_probe_earlyprintk(dev);
7b6fd3bf 2401
d535a230 2402 platform_set_drvdata(dev, sp);
e552de24 2403
906b17dc 2404 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230 2405 if (ret)
6dae1421 2406 return ret;
e552de24 2407
d535a230 2408 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2409
d535a230
PM		 2410 ret = cpufreq_register_notifier(&sp->freq_transition,
2411 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421
LP		 2412 if (unlikely(ret < 0)) {
2413 sci_cleanup_single(sp);
2414 return ret;
2415 }
1da177e4
LT		 2416
2417#ifdef CONFIG_SH_STANDARD_BIOS
2418 sh_bios_gdb_detach();
2419#endif
2420
e108b2ca 2421 return 0;
1da177e4
LT		 2422}
2423
6daa79b3 2424static int sci_suspend(struct device *dev)
1da177e4 2425{
d535a230 2426 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2427
d535a230
PM		 2428 if (sport)
2429 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2430
e108b2ca
PM		 2431 return 0;
2432}
1da177e4 2433
6daa79b3 2434static int sci_resume(struct device *dev)
e108b2ca 2435{
d535a230 2436 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2437
d535a230
PM		 2438 if (sport)
2439 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2440
2441 return 0;
2442}
2443
47145210 2444static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2445 .suspend = sci_suspend,
2446 .resume = sci_resume,
2447};
2448
e108b2ca
PM		 2449static struct platform_driver sci_driver = {
2450 .probe = sci_probe,
b9e39c89 2451 .remove = sci_remove,
e108b2ca
PM		 2452 .driver = {
2453 .name = "sh-sci",
2454 .owner = THIS_MODULE,
6daa79b3 2455 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2456 },
2457};
2458
2459static int __init sci_init(void)
2460{
2461 int ret;
2462
2463 printk(banner);
2464
e108b2ca
PM		 2465 ret = uart_register_driver(&sci_uart_driver);
2466 if (likely(ret == 0)) {
2467 ret = platform_driver_register(&sci_driver);
2468 if (unlikely(ret))
2469 uart_unregister_driver(&sci_uart_driver);
2470 }
2471
2472 return ret;
2473}
2474
2475static void __exit sci_exit(void)
2476{
2477 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2478 uart_unregister_driver(&sci_uart_driver);
2479}
2480
7b6fd3bf
MD		 2481#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2482early_platform_init_buffer("earlyprintk", &sci_driver,
2483 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2484#endif
1da177e4
LT		 2485module_init(sci_init);
2486module_exit(sci_exit);
2487
e108b2ca 2488MODULE_LICENSE("GPL");
e169c139 2489MODULE_ALIAS("platform:sh-sci");
7f405f9c
PM		 2490MODULE_AUTHOR("Paul Mundt");
2491MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
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