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serial: sh-sci: Get rid of the workqueue to handle receive DMA requests
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
2e0842a1 84 unsigned int overrun_reg;
75c249fd 85 unsigned int overrun_mask;
3ae988d9 86 unsigned int error_mask;
5da0f468 87 unsigned int error_clear;
ec09c5eb 88 unsigned int sampling_rate;
e4d6f911 89 resource_size_t reg_size;
e108b2ca 90
e108b2ca
PM		 91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
1534a3b3 94
501b825d
MD		 95 /* Interface clock */
96 struct clk *iclk;
c7ed1ab3
PM		 97 /* Function clock */
98 struct clk *fclk;
edad1f20 99
1fcc91a6 100 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 101 char *irqstr[SCIx_NR_IRQS];
102
73a19e4c
GL		 103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
f43dc23d 105
73a19e4c 106#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
79904420
GU		 110 dma_addr_t tx_dma_addr;
111 unsigned int tx_dma_len;
73a19e4c 112 struct scatterlist sg_rx[2];
7b39d901 113 void *rx_buf[2];
73a19e4c
GL		 114 size_t buf_len_rx;
115 struct sh_dmae_slave param_tx;
116 struct sh_dmae_slave param_rx;
117 struct work_struct work_tx;
73a19e4c 118 struct timer_list rx_timer;
3089f381 119 unsigned int rx_timeout;
73a19e4c 120#endif
e552de24 121
d535a230 122 struct notifier_block freq_transition;
e108b2ca
PM		 123};
124
e108b2ca 125#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 126
e108b2ca
PM		 127static struct sci_port sci_ports[SCI_NPORTS];
128static struct uart_driver sci_uart_driver;
1da177e4 129
e7c98dc7
MT		 130static inline struct sci_port *
131to_sci_port(struct uart_port *uart)
132{
133 return container_of(uart, struct sci_port, port);
134}
135
61a6976b
PM		 136struct plat_sci_reg {
137 u8 offset, size;
138};
139
140/* Helper for invalidating specific entries of an inherited map. */
141#define sci_reg_invalid { .offset = 0, .size = 0 }
142
d3184e68 143static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 144 [SCIx_PROBE_REGTYPE] = {
145 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
146 },
147
148 /*
149 * Common SCI definitions, dependent on the port's regshift
150 * value.
151 */
152 [SCIx_SCI_REGTYPE] = {
153 [SCSMR] = { 0x00, 8 },
154 [SCBRR] = { 0x01, 8 },
155 [SCSCR] = { 0x02, 8 },
156 [SCxTDR] = { 0x03, 8 },
157 [SCxSR] = { 0x04, 8 },
158 [SCxRDR] = { 0x05, 8 },
159 [SCFCR] = sci_reg_invalid,
160 [SCFDR] = sci_reg_invalid,
161 [SCTFDR] = sci_reg_invalid,
162 [SCRFDR] = sci_reg_invalid,
163 [SCSPTR] = sci_reg_invalid,
164 [SCLSR] = sci_reg_invalid,
f303b364 165 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 166 [SCPCR] = sci_reg_invalid,
167 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 168 },
169
170 /*
171 * Common definitions for legacy IrDA ports, dependent on
172 * regshift value.
173 */
174 [SCIx_IRDA_REGTYPE] = {
175 [SCSMR] = { 0x00, 8 },
176 [SCBRR] = { 0x01, 8 },
177 [SCSCR] = { 0x02, 8 },
178 [SCxTDR] = { 0x03, 8 },
179 [SCxSR] = { 0x04, 8 },
180 [SCxRDR] = { 0x05, 8 },
181 [SCFCR] = { 0x06, 8 },
182 [SCFDR] = { 0x07, 16 },
183 [SCTFDR] = sci_reg_invalid,
184 [SCRFDR] = sci_reg_invalid,
185 [SCSPTR] = sci_reg_invalid,
186 [SCLSR] = sci_reg_invalid,
f303b364 187 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 188 [SCPCR] = sci_reg_invalid,
189 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 190 },
191
192 /*
193 * Common SCIFA definitions.
194 */
195 [SCIx_SCIFA_REGTYPE] = {
196 [SCSMR] = { 0x00, 16 },
197 [SCBRR] = { 0x04, 8 },
198 [SCSCR] = { 0x08, 16 },
199 [SCxTDR] = { 0x20, 8 },
200 [SCxSR] = { 0x14, 16 },
201 [SCxRDR] = { 0x24, 8 },
202 [SCFCR] = { 0x18, 16 },
203 [SCFDR] = { 0x1c, 16 },
204 [SCTFDR] = sci_reg_invalid,
205 [SCRFDR] = sci_reg_invalid,
206 [SCSPTR] = sci_reg_invalid,
207 [SCLSR] = sci_reg_invalid,
f303b364 208 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 209 [SCPCR] = { 0x30, 16 },
210 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 211 },
212
213 /*
214 * Common SCIFB definitions.
215 */
216 [SCIx_SCIFB_REGTYPE] = {
217 [SCSMR] = { 0x00, 16 },
218 [SCBRR] = { 0x04, 8 },
219 [SCSCR] = { 0x08, 16 },
220 [SCxTDR] = { 0x40, 8 },
221 [SCxSR] = { 0x14, 16 },
222 [SCxRDR] = { 0x60, 8 },
223 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 224 [SCFDR] = sci_reg_invalid,
225 [SCTFDR] = { 0x38, 16 },
226 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 227 [SCSPTR] = sci_reg_invalid,
228 [SCLSR] = sci_reg_invalid,
f303b364 229 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 230 [SCPCR] = { 0x30, 16 },
231 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 232 },
233
3af1f8a4
PE		 234 /*
235 * Common SH-2(A) SCIF definitions for ports with FIFO data
236 * count registers.
237 */
238 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
239 [SCSMR] = { 0x00, 16 },
240 [SCBRR] = { 0x04, 8 },
241 [SCSCR] = { 0x08, 16 },
242 [SCxTDR] = { 0x0c, 8 },
243 [SCxSR] = { 0x10, 16 },
244 [SCxRDR] = { 0x14, 8 },
245 [SCFCR] = { 0x18, 16 },
246 [SCFDR] = { 0x1c, 16 },
247 [SCTFDR] = sci_reg_invalid,
248 [SCRFDR] = sci_reg_invalid,
249 [SCSPTR] = { 0x20, 16 },
250 [SCLSR] = { 0x24, 16 },
f303b364 251 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 252 [SCPCR] = sci_reg_invalid,
253 [SCPDR] = sci_reg_invalid,
3af1f8a4
PE		 254 },
255
61a6976b
PM		 256 /*
257 * Common SH-3 SCIF definitions.
258 */
259 [SCIx_SH3_SCIF_REGTYPE] = {
260 [SCSMR] = { 0x00, 8 },
261 [SCBRR] = { 0x02, 8 },
262 [SCSCR] = { 0x04, 8 },
263 [SCxTDR] = { 0x06, 8 },
264 [SCxSR] = { 0x08, 16 },
265 [SCxRDR] = { 0x0a, 8 },
266 [SCFCR] = { 0x0c, 8 },
267 [SCFDR] = { 0x0e, 16 },
268 [SCTFDR] = sci_reg_invalid,
269 [SCRFDR] = sci_reg_invalid,
270 [SCSPTR] = sci_reg_invalid,
271 [SCLSR] = sci_reg_invalid,
f303b364 272 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 273 [SCPCR] = sci_reg_invalid,
274 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 275 },
276
277 /*
278 * Common SH-4(A) SCIF(B) definitions.
279 */
280 [SCIx_SH4_SCIF_REGTYPE] = {
281 [SCSMR] = { 0x00, 16 },
282 [SCBRR] = { 0x04, 8 },
283 [SCSCR] = { 0x08, 16 },
284 [SCxTDR] = { 0x0c, 8 },
285 [SCxSR] = { 0x10, 16 },
286 [SCxRDR] = { 0x14, 8 },
287 [SCFCR] = { 0x18, 16 },
288 [SCFDR] = { 0x1c, 16 },
289 [SCTFDR] = sci_reg_invalid,
290 [SCRFDR] = sci_reg_invalid,
291 [SCSPTR] = { 0x20, 16 },
292 [SCLSR] = { 0x24, 16 },
f303b364 293 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 294 [SCPCR] = sci_reg_invalid,
295 [SCPDR] = sci_reg_invalid,
f303b364
UH		 296 },
297
298 /*
299 * Common HSCIF definitions.
300 */
301 [SCIx_HSCIF_REGTYPE] = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x04, 8 },
304 [SCSCR] = { 0x08, 16 },
305 [SCxTDR] = { 0x0c, 8 },
306 [SCxSR] = { 0x10, 16 },
307 [SCxRDR] = { 0x14, 8 },
308 [SCFCR] = { 0x18, 16 },
309 [SCFDR] = { 0x1c, 16 },
310 [SCTFDR] = sci_reg_invalid,
311 [SCRFDR] = sci_reg_invalid,
312 [SCSPTR] = { 0x20, 16 },
313 [SCLSR] = { 0x24, 16 },
314 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 315 [SCPCR] = sci_reg_invalid,
316 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 317 },
318
319 /*
320 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
321 * register.
322 */
323 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
324 [SCSMR] = { 0x00, 16 },
325 [SCBRR] = { 0x04, 8 },
326 [SCSCR] = { 0x08, 16 },
327 [SCxTDR] = { 0x0c, 8 },
328 [SCxSR] = { 0x10, 16 },
329 [SCxRDR] = { 0x14, 8 },
330 [SCFCR] = { 0x18, 16 },
331 [SCFDR] = { 0x1c, 16 },
332 [SCTFDR] = sci_reg_invalid,
333 [SCRFDR] = sci_reg_invalid,
334 [SCSPTR] = sci_reg_invalid,
335 [SCLSR] = { 0x24, 16 },
f303b364 336 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 337 [SCPCR] = sci_reg_invalid,
338 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 339 },
340
341 /*
342 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
343 * count registers.
344 */
345 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
346 [SCSMR] = { 0x00, 16 },
347 [SCBRR] = { 0x04, 8 },
348 [SCSCR] = { 0x08, 16 },
349 [SCxTDR] = { 0x0c, 8 },
350 [SCxSR] = { 0x10, 16 },
351 [SCxRDR] = { 0x14, 8 },
352 [SCFCR] = { 0x18, 16 },
353 [SCFDR] = { 0x1c, 16 },
354 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
355 [SCRFDR] = { 0x20, 16 },
356 [SCSPTR] = { 0x24, 16 },
357 [SCLSR] = { 0x28, 16 },
f303b364 358 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 359 [SCPCR] = sci_reg_invalid,
360 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 361 },
362
363 /*
364 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
365 * registers.
366 */
367 [SCIx_SH7705_SCIF_REGTYPE] = {
368 [SCSMR] = { 0x00, 16 },
369 [SCBRR] = { 0x04, 8 },
370 [SCSCR] = { 0x08, 16 },
371 [SCxTDR] = { 0x20, 8 },
372 [SCxSR] = { 0x14, 16 },
373 [SCxRDR] = { 0x24, 8 },
374 [SCFCR] = { 0x18, 16 },
375 [SCFDR] = { 0x1c, 16 },
376 [SCTFDR] = sci_reg_invalid,
377 [SCRFDR] = sci_reg_invalid,
378 [SCSPTR] = sci_reg_invalid,
379 [SCLSR] = sci_reg_invalid,
f303b364 380 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 381 [SCPCR] = sci_reg_invalid,
382 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 383 },
384};
385
72b294cf
PM		 386#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
387
61a6976b
PM		 388/*
389 * The "offset" here is rather misleading, in that it refers to an enum
390 * value relative to the port mapping rather than the fixed offset
391 * itself, which needs to be manually retrieved from the platform's
392 * register map for the given port.
393 */
394static unsigned int sci_serial_in(struct uart_port *p, int offset)
395{
d3184e68 396 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 397
398 if (reg->size == 8)
399 return ioread8(p->membase + (reg->offset << p->regshift));
400 else if (reg->size == 16)
401 return ioread16(p->membase + (reg->offset << p->regshift));
402 else
403 WARN(1, "Invalid register access\n");
404
405 return 0;
406}
407
408static void sci_serial_out(struct uart_port *p, int offset, int value)
409{
d3184e68 410 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 411
412 if (reg->size == 8)
413 iowrite8(value, p->membase + (reg->offset << p->regshift));
414 else if (reg->size == 16)
415 iowrite16(value, p->membase + (reg->offset << p->regshift));
416 else
417 WARN(1, "Invalid register access\n");
418}
419
61a6976b
PM		 420static int sci_probe_regmap(struct plat_sci_port *cfg)
421{
422 switch (cfg->type) {
423 case PORT_SCI:
424 cfg->regtype = SCIx_SCI_REGTYPE;
425 break;
426 case PORT_IRDA:
427 cfg->regtype = SCIx_IRDA_REGTYPE;
428 break;
429 case PORT_SCIFA:
430 cfg->regtype = SCIx_SCIFA_REGTYPE;
431 break;
432 case PORT_SCIFB:
433 cfg->regtype = SCIx_SCIFB_REGTYPE;
434 break;
435 case PORT_SCIF:
436 /*
437 * The SH-4 is a bit of a misnomer here, although that's
438 * where this particular port layout originated. This
439 * configuration (or some slight variation thereof)
440 * remains the dominant model for all SCIFs.
441 */
442 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
443 break;
f303b364
UH		 444 case PORT_HSCIF:
445 cfg->regtype = SCIx_HSCIF_REGTYPE;
446 break;
61a6976b 447 default:
6c13d5d2 448 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 449 return -EINVAL;
450 }
451
452 return 0;
453}
454
23241d43
PM		 455static void sci_port_enable(struct sci_port *sci_port)
456{
457 if (!sci_port->port.dev)
458 return;
459
460 pm_runtime_get_sync(sci_port->port.dev);
461
b016b646 462 clk_prepare_enable(sci_port->iclk);
23241d43 463 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 464 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 465}
466
467static void sci_port_disable(struct sci_port *sci_port)
468{
469 if (!sci_port->port.dev)
470 return;
471
caec7038
LP		 472 /* Cancel the break timer to ensure that the timer handler will not try
473 * to access the hardware with clocks and power disabled. Reset the
474 * break flag to make the break debouncing state machine ready for the
475 * next break.
476 */
477 del_timer_sync(&sci_port->break_timer);
478 sci_port->break_flag = 0;
479
b016b646
LP		 480 clk_disable_unprepare(sci_port->fclk);
481 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 482
483 pm_runtime_put_sync(sci_port->port.dev);
484}
485
e1910fcd
GU		 486static inline unsigned long port_rx_irq_mask(struct uart_port *port)
487{
488 /*
489 * Not all ports (such as SCIFA) will support REIE. Rather than
490 * special-casing the port type, we check the port initialization
491 * IRQ enable mask to see whether the IRQ is desired at all. If
492 * it's unset, it's logically inferred that there's no point in
493 * testing for it.
494 */
495 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
496}
497
498static void sci_start_tx(struct uart_port *port)
499{
500 struct sci_port *s = to_sci_port(port);
501 unsigned short ctrl;
502
503#ifdef CONFIG_SERIAL_SH_SCI_DMA
504 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
505 u16 new, scr = serial_port_in(port, SCSCR);
506 if (s->chan_tx)
507 new = scr | SCSCR_TDRQE;
508 else
509 new = scr & ~SCSCR_TDRQE;
510 if (new != scr)
511 serial_port_out(port, SCSCR, new);
512 }
513
514 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
515 dma_submit_error(s->cookie_tx)) {
516 s->cookie_tx = 0;
517 schedule_work(&s->work_tx);
518 }
519#endif
520
521 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
522 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
523 ctrl = serial_port_in(port, SCSCR);
524 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
525 }
526}
527
528static void sci_stop_tx(struct uart_port *port)
529{
530 unsigned short ctrl;
531
532 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
533 ctrl = serial_port_in(port, SCSCR);
534
535 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
536 ctrl &= ~SCSCR_TDRQE;
537
538 ctrl &= ~SCSCR_TIE;
539
540 serial_port_out(port, SCSCR, ctrl);
541}
542
543static void sci_start_rx(struct uart_port *port)
544{
545 unsigned short ctrl;
546
547 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
548
549 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
550 ctrl &= ~SCSCR_RDRQE;
551
552 serial_port_out(port, SCSCR, ctrl);
553}
554
555static void sci_stop_rx(struct uart_port *port)
556{
557 unsigned short ctrl;
558
559 ctrl = serial_port_in(port, SCSCR);
560
561 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
562 ctrl &= ~SCSCR_RDRQE;
563
564 ctrl &= ~port_rx_irq_mask(port);
565
566 serial_port_out(port, SCSCR, ctrl);
567}
568
a1b5b43f
GU		 569static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
570{
571 if (port->type == PORT_SCI) {
572 /* Just store the mask */
573 serial_port_out(port, SCxSR, mask);
574 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
575 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
576 /* Only clear the status bits we want to clear */
577 serial_port_out(port, SCxSR,
578 serial_port_in(port, SCxSR) & mask);
579 } else {
580 /* Store the mask, clear parity/framing errors */
581 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
582 }
583}
584
07d2a1a1 585#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 586
587#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 588static int sci_poll_get_char(struct uart_port *port)
1da177e4 589{
1da177e4
LT		 590 unsigned short status;
591 int c;
592
e108b2ca 593 do {
b12bb29f 594 status = serial_port_in(port, SCxSR);
1da177e4 595 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 596 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 597 continue;
598 }
3f255eb3
JW		 599 break;
600 } while (1);
601
602 if (!(status & SCxSR_RDxF(port)))
603 return NO_POLL_CHAR;
07d2a1a1 604
b12bb29f 605 c = serial_port_in(port, SCxRDR);
07d2a1a1 606
e7c98dc7 607 /* Dummy read */
b12bb29f 608 serial_port_in(port, SCxSR);
a1b5b43f 609 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 610
611 return c;
612}
1f6fd5c9 613#endif
1da177e4 614
07d2a1a1 615static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 616{
1da177e4
LT		 617 unsigned short status;
618
1da177e4 619 do {
b12bb29f 620 status = serial_port_in(port, SCxSR);
1da177e4
LT		 621 } while (!(status & SCxSR_TDxE(port)));
622
b12bb29f 623 serial_port_out(port, SCxTDR, c);
a1b5b43f 624 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 625}
07d2a1a1 626#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 627
61a6976b 628static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 629{
61a6976b 630 struct sci_port *s = to_sci_port(port);
d3184e68 631 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 632
61a6976b
PM		 633 /*
634 * Use port-specific handler if provided.
635 */
636 if (s->cfg->ops && s->cfg->ops->init_pins) {
637 s->cfg->ops->init_pins(port, cflag);
638 return;
1da177e4 639 }
41504c39 640
61a6976b
PM		 641 /*
642 * For the generic path SCSPTR is necessary. Bail out if that's
643 * unavailable, too.
644 */
645 if (!reg->size)
646 return;
41504c39 647
faf02f8f
PM		 648 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
649 ((!(cflag & CRTSCTS)))) {
650 unsigned short status;
651
b12bb29f 652 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 653 status &= ~SCSPTR_CTSIO;
654 status |= SCSPTR_RTSIO;
b12bb29f 655 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 656 }
d5701647 657}
e108b2ca 658
72b294cf 659static int sci_txfill(struct uart_port *port)
e108b2ca 660{
d3184e68 661 const struct plat_sci_reg *reg;
e108b2ca 662
72b294cf
PM		 663 reg = sci_getreg(port, SCTFDR);
664 if (reg->size)
63f7ad11 665 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 666
72b294cf
PM		 667 reg = sci_getreg(port, SCFDR);
668 if (reg->size)
b12bb29f 669 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 670
b12bb29f 671 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 672}
673
73a19e4c
GL		 674static int sci_txroom(struct uart_port *port)
675{
72b294cf 676 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 677}
678
679static int sci_rxfill(struct uart_port *port)
e108b2ca 680{
d3184e68 681 const struct plat_sci_reg *reg;
72b294cf
PM		 682
683 reg = sci_getreg(port, SCRFDR);
684 if (reg->size)
63f7ad11 685 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 686
687 reg = sci_getreg(port, SCFDR);
688 if (reg->size)
b12bb29f 689 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 690
b12bb29f 691 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 692}
693
514820eb
PM		 694/*
695 * SCI helper for checking the state of the muxed port/RXD pins.
696 */
697static inline int sci_rxd_in(struct uart_port *port)
698{
699 struct sci_port *s = to_sci_port(port);
700
701 if (s->cfg->port_reg <= 0)
702 return 1;
703
0dd4d5cb 704 /* Cast for ARM damage */
e2afca69 705 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 706}
707
1da177e4
LT		 708/* ********************************************************************** *
709 * the interrupt related routines *
710 * ********************************************************************** */
711
712static void sci_transmit_chars(struct uart_port *port)
713{
ebd2c8f6 714 struct circ_buf *xmit = &port->state->xmit;
1da177e4 715 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 716 unsigned short status;
717 unsigned short ctrl;
e108b2ca 718 int count;
1da177e4 719
b12bb29f 720 status = serial_port_in(port, SCxSR);
1da177e4 721 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 722 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 723 if (uart_circ_empty(xmit))
8e698614 724 ctrl &= ~SCSCR_TIE;
e7c98dc7 725 else
8e698614 726 ctrl |= SCSCR_TIE;
b12bb29f 727 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 728 return;
729 }
730
72b294cf 731 count = sci_txroom(port);
1da177e4
LT		 732
733 do {
734 unsigned char c;
735
736 if (port->x_char) {
737 c = port->x_char;
738 port->x_char = 0;
739 } else if (!uart_circ_empty(xmit) && !stopped) {
740 c = xmit->buf[xmit->tail];
741 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
742 } else {
743 break;
744 }
745
b12bb29f 746 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 747
748 port->icount.tx++;
749 } while (--count > 0);
750
a1b5b43f 751 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 752
753 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
754 uart_write_wakeup(port);
755 if (uart_circ_empty(xmit)) {
b129a8cc 756 sci_stop_tx(port);
1da177e4 757 } else {
b12bb29f 758 ctrl = serial_port_in(port, SCSCR);
1da177e4 759
1a22f08d 760 if (port->type != PORT_SCI) {
b12bb29f 761 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 762 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 763 }
1da177e4 764
8e698614 765 ctrl |= SCSCR_TIE;
b12bb29f 766 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 767 }
768}
769
770/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 771#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 772
94c8b6db 773static void sci_receive_chars(struct uart_port *port)
1da177e4 774{
e7c98dc7 775 struct sci_port *sci_port = to_sci_port(port);
227434f8 776 struct tty_port *tport = &port->state->port;
1da177e4
LT		 777 int i, count, copied = 0;
778 unsigned short status;
33f0f88f 779 unsigned char flag;
1da177e4 780
b12bb29f 781 status = serial_port_in(port, SCxSR);
1da177e4
LT		 782 if (!(status & SCxSR_RDxF(port)))
783 return;
784
785 while (1) {
1da177e4 786 /* Don't copy more bytes than there is room for in the buffer */
227434f8 787 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 788
789 /* If for any reason we can't copy more data, we're done! */
790 if (count == 0)
791 break;
792
793 if (port->type == PORT_SCI) {
b12bb29f 794 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 795 if (uart_handle_sysrq_char(port, c) ||
796 sci_port->break_flag)
1da177e4 797 count = 0;
e7c98dc7 798 else
92a19f9c 799 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 800 } else {
e7c98dc7 801 for (i = 0; i < count; i++) {
b12bb29f 802 char c = serial_port_in(port, SCxRDR);
d97fbbed 803
b12bb29f 804 status = serial_port_in(port, SCxSR);
1da177e4
LT		 805#if defined(CONFIG_CPU_SH3)
806 /* Skip "chars" during break */
e108b2ca 807 if (sci_port->break_flag) {
1da177e4
LT		 808 if ((c == 0) &&
809 (status & SCxSR_FER(port))) {
810 count--; i--;
811 continue;
812 }
e108b2ca 813
1da177e4 814 /* Nonzero => end-of-break */
762c69e3 815 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 816 sci_port->break_flag = 0;
817
1da177e4
LT		 818 if (STEPFN(c)) {
819 count--; i--;
820 continue;
821 }
822 }
823#endif /* CONFIG_CPU_SH3 */
7d12e780 824 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 825 count--; i--;
826 continue;
827 }
828
829 /* Store data and status */
73a19e4c 830 if (status & SCxSR_FER(port)) {
33f0f88f 831 flag = TTY_FRAME;
d97fbbed 832 port->icount.frame++;
762c69e3 833 dev_notice(port->dev, "frame error\n");
73a19e4c 834 } else if (status & SCxSR_PER(port)) {
33f0f88f 835 flag = TTY_PARITY;
d97fbbed 836 port->icount.parity++;
762c69e3 837 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 838 } else
839 flag = TTY_NORMAL;
762c69e3 840
92a19f9c 841 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 842 }
843 }
844
b12bb29f 845 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 846 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 847
1da177e4
LT		 848 copied += count;
849 port->icount.rx += count;
850 }
851
852 if (copied) {
853 /* Tell the rest of the system the news. New characters! */
2e124b4a 854 tty_flip_buffer_push(tport);
1da177e4 855 } else {
b12bb29f 856 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 857 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 858 }
859}
860
861#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 862
863/*
864 * The sci generates interrupts during the break,
1da177e4
LT		 865 * 1 per millisecond or so during the break period, for 9600 baud.
866 * So dont bother disabling interrupts.
867 * But dont want more than 1 break event.
868 * Use a kernel timer to periodically poll the rx line until
869 * the break is finished.
870 */
94c8b6db 871static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 872{
bc9b3f5c 873 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 874}
94c8b6db 875
1da177e4
LT		 876/* Ensure that two consecutive samples find the break over. */
877static void sci_break_timer(unsigned long data)
878{
e108b2ca
PM		 879 struct sci_port *port = (struct sci_port *)data;
880
881 if (sci_rxd_in(&port->port) == 0) {
1da177e4 882 port->break_flag = 1;
e108b2ca
PM		 883 sci_schedule_break_timer(port);
884 } else if (port->break_flag == 1) {
1da177e4
LT		 885 /* break is over. */
886 port->break_flag = 2;
e108b2ca
PM		 887 sci_schedule_break_timer(port);
888 } else
889 port->break_flag = 0;
1da177e4
LT		 890}
891
94c8b6db 892static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 893{
894 int copied = 0;
b12bb29f 895 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 896 struct tty_port *tport = &port->state->port;
debf9507 897 struct sci_port *s = to_sci_port(port);
1da177e4 898
3ae988d9 899 /* Handle overruns */
75c249fd 900 if (status & s->overrun_mask) {
3ae988d9 901 port->icount.overrun++;
d97fbbed 902
3ae988d9
LP		 903 /* overrun error */
904 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
905 copied++;
762c69e3 906
9b971cd2 907 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 908 }
909
e108b2ca 910 if (status & SCxSR_FER(port)) {
1da177e4
LT		 911 if (sci_rxd_in(port) == 0) {
912 /* Notify of BREAK */
e7c98dc7 913 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 914
915 if (!sci_port->break_flag) {
d97fbbed
PM		 916 port->icount.brk++;
917
e108b2ca
PM		 918 sci_port->break_flag = 1;
919 sci_schedule_break_timer(sci_port);
920
1da177e4 921 /* Do sysrq handling. */
e108b2ca 922 if (uart_handle_break(port))
1da177e4 923 return 0;
762c69e3
PM		 924
925 dev_dbg(port->dev, "BREAK detected\n");
926
92a19f9c 927 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 928 copied++;
929 }
930
e108b2ca 931 } else {
1da177e4 932 /* frame error */
d97fbbed
PM		 933 port->icount.frame++;
934
92a19f9c 935 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 936 copied++;
762c69e3
PM		 937
938 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 939 }
940 }
941
e108b2ca 942 if (status & SCxSR_PER(port)) {
1da177e4 943 /* parity error */
d97fbbed
PM		 944 port->icount.parity++;
945
92a19f9c 946 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 947 copied++;
762c69e3 948
9b971cd2 949 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 950 }
951
33f0f88f 952 if (copied)
2e124b4a 953 tty_flip_buffer_push(tport);
1da177e4
LT		 954
955 return copied;
956}
957
94c8b6db 958static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 959{
92a19f9c 960 struct tty_port *tport = &port->state->port;
debf9507 961 struct sci_port *s = to_sci_port(port);
d3184e68 962 const struct plat_sci_reg *reg;
2e0842a1 963 int copied = 0;
75c249fd 964 u16 status;
d830fa45 965
2e0842a1 966 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 967 if (!reg->size)
d830fa45
PM		 968 return 0;
969
2e0842a1 970 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 971 if (status & s->overrun_mask) {
972 status &= ~s->overrun_mask;
2e0842a1 973 serial_port_out(port, s->overrun_reg, status);
d830fa45 974
d97fbbed
PM		 975 port->icount.overrun++;
976
92a19f9c 977 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 978 tty_flip_buffer_push(tport);
d830fa45 979
51b31f1c 980 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 981 copied++;
982 }
983
984 return copied;
985}
986
94c8b6db 987static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 988{
989 int copied = 0;
b12bb29f 990 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 991 struct tty_port *tport = &port->state->port;
a5660ada 992 struct sci_port *s = to_sci_port(port);
1da177e4 993
0b3d4ef6
PM		 994 if (uart_handle_break(port))
995 return 0;
996
b7a76e4b 997 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 998#if defined(CONFIG_CPU_SH3)
999 /* Debounce break */
1000 s->break_flag = 1;
1001#endif
d97fbbed
PM		 1002
1003 port->icount.brk++;
1004
1da177e4 1005 /* Notify of BREAK */
92a19f9c 1006 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 1007 copied++;
762c69e3
PM		 1008
1009 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 1010 }
1011
33f0f88f 1012 if (copied)
2e124b4a 1013 tty_flip_buffer_push(tport);
e108b2ca 1014
d830fa45
PM		 1015 copied += sci_handle_fifo_overrun(port);
1016
1da177e4
LT		 1017 return copied;
1018}
1019
73a19e4c 1020#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1021static void sci_dma_tx_complete(void *arg)
1022{
1023 struct sci_port *s = arg;
1024 struct uart_port *port = &s->port;
1025 struct circ_buf *xmit = &port->state->xmit;
1026 unsigned long flags;
73a19e4c 1027
e1910fcd 1028 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1029
e1910fcd 1030 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1031
e1910fcd
GU		 1032 xmit->tail += s->tx_dma_len;
1033 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1034
e1910fcd 1035 port->icount.tx += s->tx_dma_len;
1da177e4 1036
e1910fcd
GU		 1037 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1038 uart_write_wakeup(port);
1da177e4 1039
e1910fcd
GU		 1040 if (!uart_circ_empty(xmit)) {
1041 s->cookie_tx = 0;
1042 schedule_work(&s->work_tx);
1043 } else {
1044 s->cookie_tx = -EINVAL;
1045 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1046 u16 ctrl = serial_port_in(port, SCSCR);
1047 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1048 }
1049 }
1da177e4 1050
fd78a76a 1051 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1052}
1053
e1910fcd
GU		 1054/* Locking: called with port lock held */
1055static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1056{
e1910fcd
GU		 1057 struct uart_port *port = &s->port;
1058 struct tty_port *tport = &port->state->port;
1059 int copied;
1da177e4 1060
e1910fcd
GU		 1061 copied = tty_insert_flip_string(tport, buf, count);
1062 if (copied < count) {
1063 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1064 count - copied);
1065 port->icount.buf_overrun++;
1da177e4
LT		 1066 }
1067
e1910fcd 1068 port->icount.rx += copied;
1da177e4 1069
e1910fcd 1070 return copied;
1da177e4
LT		 1071}
1072
e1910fcd 1073static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1074{
e1910fcd 1075 unsigned int i;
1da177e4 1076
e1910fcd
GU		 1077 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1078 if (s->active_rx == s->cookie_rx[i])
1079 return i;
1da177e4 1080
e1910fcd
GU		 1081 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1082 s->active_rx);
1083 return -1;
1da177e4
LT		 1084}
1085
e1910fcd 1086static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1087{
e1910fcd
GU		 1088 struct dma_chan *chan = s->chan_rx;
1089 struct uart_port *port = &s->port;
1090 unsigned long flags;
1091
1092 spin_lock_irqsave(&port->lock, flags);
1093 s->chan_rx = NULL;
1094 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1095 spin_unlock_irqrestore(&port->lock, flags);
1096 dmaengine_terminate_all(chan);
1097 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1098 sg_dma_address(&s->sg_rx[0]));
1099 dma_release_channel(chan);
1100 if (enable_pio)
1101 sci_start_rx(port);
f43dc23d
PM		 1102}
1103
e1910fcd 1104static void sci_dma_rx_complete(void *arg)
1da177e4 1105{
e1910fcd
GU		 1106 struct sci_port *s = arg;
1107 struct uart_port *port = &s->port;
67f462b0 1108 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1109 unsigned long flags;
1110 int active, count = 0;
1da177e4 1111
e1910fcd
GU		 1112 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1113 s->active_rx);
cb772fe7 1114
e1910fcd 1115 spin_lock_irqsave(&port->lock, flags);
1da177e4 1116
e1910fcd
GU		 1117 active = sci_dma_rx_find_active(s);
1118 if (active >= 0)
1119 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1120
e1910fcd 1121 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1122
e1910fcd
GU		 1123 if (count)
1124 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1125
67f462b0
GU		 1126 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1127 DMA_DEV_TO_MEM,
1128 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1129 if (!desc)
1130 goto fail;
1131
1132 desc->callback = sci_dma_rx_complete;
1133 desc->callback_param = s;
1134 s->cookie_rx[active] = dmaengine_submit(desc);
1135 if (dma_submit_error(s->cookie_rx[active]))
1136 goto fail;
1137
1138 s->active_rx = s->cookie_rx[!active];
1139
1140 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1141 __func__, s->cookie_rx[active], active, s->active_rx);
1142 spin_unlock_irqrestore(&port->lock, flags);
1143 return;
1144
1145fail:
1146 spin_unlock_irqrestore(&port->lock, flags);
1147 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1148 sci_rx_dma_release(s, true);
1da177e4
LT		 1149}
1150
e1910fcd 1151static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1152{
e1910fcd
GU		 1153 struct dma_chan *chan = s->chan_tx;
1154 struct uart_port *port = &s->port;
e552de24 1155 unsigned long flags;
1da177e4 1156
e1910fcd
GU		 1157 spin_lock_irqsave(&port->lock, flags);
1158 s->chan_tx = NULL;
1159 s->cookie_tx = -EINVAL;
1160 spin_unlock_irqrestore(&port->lock, flags);
1161 dmaengine_terminate_all(chan);
1162 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1163 DMA_TO_DEVICE);
1164 dma_release_channel(chan);
1165 if (enable_pio)
1166 sci_start_tx(port);
1167}
d535a230 1168
e1910fcd
GU		 1169static void sci_submit_rx(struct sci_port *s)
1170{
1171 struct dma_chan *chan = s->chan_rx;
1172 int i;
073e84c9 1173
e1910fcd
GU		 1174 for (i = 0; i < 2; i++) {
1175 struct scatterlist *sg = &s->sg_rx[i];
1176 struct dma_async_tx_descriptor *desc;
1da177e4 1177
e1910fcd
GU		 1178 desc = dmaengine_prep_slave_sg(chan,
1179 sg, 1, DMA_DEV_TO_MEM,
1180 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1181 if (!desc)
1182 goto fail;
501b825d 1183
e1910fcd
GU		 1184 desc->callback = sci_dma_rx_complete;
1185 desc->callback_param = s;
1186 s->cookie_rx[i] = dmaengine_submit(desc);
1187 if (dma_submit_error(s->cookie_rx[i]))
1188 goto fail;
9174fc8f 1189
e1910fcd
GU		 1190 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1191 s->cookie_rx[i], i);
1192 }
9174fc8f 1193
e1910fcd 1194 s->active_rx = s->cookie_rx[0];
9174fc8f 1195
e1910fcd
GU		 1196 dma_async_issue_pending(chan);
1197 return;
9174fc8f 1198
e1910fcd
GU		 1199fail:
1200 if (i)
1201 dmaengine_terminate_all(chan);
1202 for (i = 0; i < 2; i++)
1203 s->cookie_rx[i] = -EINVAL;
1204 s->active_rx = -EINVAL;
1205 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1206 sci_rx_dma_release(s, true);
1207}
9174fc8f 1208
e1910fcd 1209static void work_fn_tx(struct work_struct *work)
1da177e4 1210{
e1910fcd
GU		 1211 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1212 struct dma_async_tx_descriptor *desc;
1213 struct dma_chan *chan = s->chan_tx;
1214 struct uart_port *port = &s->port;
1215 struct circ_buf *xmit = &port->state->xmit;
1216 dma_addr_t buf;
1da177e4 1217
9174fc8f 1218 /*
e1910fcd
GU		 1219 * DMA is idle now.
1220 * Port xmit buffer is already mapped, and it is one page... Just adjust
1221 * offsets and lengths. Since it is a circular buffer, we have to
1222 * transmit till the end, and then the rest. Take the port lock to get a
1223 * consistent xmit buffer state.
9174fc8f 1224 */
e1910fcd
GU		 1225 spin_lock_irq(&port->lock);
1226 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1227 s->tx_dma_len = min_t(unsigned int,
1228 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1229 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1230 spin_unlock_irq(&port->lock);
0e8963de 1231
e1910fcd
GU		 1232 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1233 DMA_MEM_TO_DEV,
1234 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1235 if (!desc) {
1236 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1237 /* switch to PIO */
1238 sci_tx_dma_release(s, true);
1239 return;
1240 }
0e8963de 1241
e1910fcd
GU		 1242 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1243 DMA_TO_DEVICE);
1da177e4 1244
e1910fcd
GU		 1245 spin_lock_irq(&port->lock);
1246 desc->callback = sci_dma_tx_complete;
1247 desc->callback_param = s;
1248 spin_unlock_irq(&port->lock);
1249 s->cookie_tx = dmaengine_submit(desc);
1250 if (dma_submit_error(s->cookie_tx)) {
1251 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1252 /* switch to PIO */
1253 sci_tx_dma_release(s, true);
1254 return;
1da177e4 1255 }
1da177e4 1256
e1910fcd
GU		 1257 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1258 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1259
e1910fcd 1260 dma_async_issue_pending(chan);
1da177e4
LT		 1261}
1262
e1910fcd 1263static bool filter(struct dma_chan *chan, void *slave)
1da177e4 1264{
e1910fcd 1265 struct sh_dmae_slave *param = slave;
dc7e3ef7 1266
e1910fcd
GU		 1267 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1268 __func__, param->shdma_slave.slave_id);
1269
1270 chan->private = &param->shdma_slave;
1271 return true;
1da177e4
LT		 1272}
1273
e1910fcd 1274static void rx_timer_fn(unsigned long arg)
1da177e4 1275{
e1910fcd
GU		 1276 struct sci_port *s = (struct sci_port *)arg;
1277 struct uart_port *port = &s->port;
67f462b0
GU		 1278 struct dma_tx_state state;
1279 enum dma_status status;
1280 unsigned long flags;
1281 unsigned int read;
1282 int active, count;
1283 u16 scr;
1284
1285 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1286
67f462b0
GU		 1287 dev_dbg(port->dev, "DMA Rx timed out\n");
1288 scr = serial_port_in(port, SCSCR);
e1910fcd
GU		 1289 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1290 scr &= ~SCSCR_RDRQE;
1291 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1292 }
1293 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
67f462b0
GU		 1294
1295 active = sci_dma_rx_find_active(s);
1296 if (active < 0) {
1297 spin_unlock_irqrestore(&port->lock, flags);
1298 return;
1299 }
1300
1301 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1302 if (status == DMA_COMPLETE)
1303 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1304 s->active_rx, active);
1305
1306 /* Handle incomplete DMA receive */
1307 dmaengine_terminate_all(s->chan_rx);
1308 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1309 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1310 s->active_rx);
1311
1312 if (read) {
1313 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1314 if (count)
1315 tty_flip_buffer_push(&port->state->port);
1316 }
1317
1318 spin_unlock_irqrestore(&port->lock, flags);
1319
1320 sci_submit_rx(s);
1da177e4
LT		 1321}
1322
e1910fcd 1323static void sci_request_dma(struct uart_port *port)
73a19e4c 1324{
e1910fcd
GU		 1325 struct sci_port *s = to_sci_port(port);
1326 struct sh_dmae_slave *param;
1327 struct dma_chan *chan;
1328 dma_cap_mask_t mask;
73a19e4c 1329
e1910fcd 1330 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1331
e1910fcd
GU		 1332 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1333 return;
73a19e4c 1334
e1910fcd
GU		 1335 dma_cap_zero(mask);
1336 dma_cap_set(DMA_SLAVE, mask);
73a19e4c 1337
e1910fcd 1338 param = &s->param_tx;
73a19e4c 1339
e1910fcd
GU		 1340 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1341 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c 1342
e1910fcd
GU		 1343 s->cookie_tx = -EINVAL;
1344 chan = dma_request_channel(mask, filter, param);
1345 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1346 if (chan) {
1347 s->chan_tx = chan;
1348 /* UART circular tx buffer is an aligned page. */
1349 s->tx_dma_addr = dma_map_single(chan->device->dev,
1350 port->state->xmit.buf,
1351 UART_XMIT_SIZE,
1352 DMA_TO_DEVICE);
1353 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1354 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1355 dma_release_channel(chan);
1356 s->chan_tx = NULL;
1357 } else {
1358 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1359 __func__, UART_XMIT_SIZE,
1360 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1361 }
e1910fcd
GU		 1362
1363 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1364 }
1365
e1910fcd 1366 param = &s->param_rx;
73a19e4c 1367
e1910fcd
GU		 1368 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1369 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c 1370
e1910fcd
GU		 1371 chan = dma_request_channel(mask, filter, param);
1372 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1373 if (chan) {
1374 unsigned int i;
1375 dma_addr_t dma;
1376 void *buf;
73a19e4c 1377
e1910fcd 1378 s->chan_rx = chan;
73a19e4c 1379
e1910fcd
GU		 1380 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1381 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1382 &dma, GFP_KERNEL);
1383 if (!buf) {
1384 dev_warn(port->dev,
1385 "Failed to allocate Rx dma buffer, using PIO\n");
1386 dma_release_channel(chan);
1387 s->chan_rx = NULL;
1388 sci_start_rx(port);
1389 return;
1390 }
73a19e4c 1391
e1910fcd
GU		 1392 for (i = 0; i < 2; i++) {
1393 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1394
e1910fcd
GU		 1395 sg_init_table(sg, 1);
1396 s->rx_buf[i] = buf;
1397 sg_dma_address(sg) = dma;
1398 sg->length = s->buf_len_rx;
0533502d 1399
e1910fcd
GU		 1400 buf += s->buf_len_rx;
1401 dma += s->buf_len_rx;
1402 }
1403
e1910fcd
GU		 1404 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1405
1406 sci_submit_rx(s);
1407 }
0533502d
GU		 1408}
1409
e1910fcd 1410static void sci_free_dma(struct uart_port *port)
73a19e4c 1411{
e1910fcd 1412 struct sci_port *s = to_sci_port(port);
73a19e4c 1413
e1910fcd
GU		 1414 if (s->chan_tx)
1415 sci_tx_dma_release(s, false);
1416 if (s->chan_rx)
1417 sci_rx_dma_release(s, false);
1418}
1419#else
1420static inline void sci_request_dma(struct uart_port *port)
1421{
1422}
73a19e4c 1423
e1910fcd
GU		 1424static inline void sci_free_dma(struct uart_port *port)
1425{
1426}
1427#endif
73a19e4c 1428
e1910fcd
GU		 1429static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1430{
1431#ifdef CONFIG_SERIAL_SH_SCI_DMA
1432 struct uart_port *port = ptr;
1433 struct sci_port *s = to_sci_port(port);
73a19e4c 1434
e1910fcd
GU		 1435 if (s->chan_rx) {
1436 u16 scr = serial_port_in(port, SCSCR);
1437 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1438
e1910fcd
GU		 1439 /* Disable future Rx interrupts */
1440 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1441 disable_irq_nosync(irq);
1442 scr |= SCSCR_RDRQE;
1443 } else {
1444 scr &= ~SCSCR_RIE;
1445 }
1446 serial_port_out(port, SCSCR, scr);
1447 /* Clear current interrupt */
1448 serial_port_out(port, SCxSR,
1449 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1450 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1451 jiffies, s->rx_timeout);
1452 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1453
e1910fcd
GU		 1454 return IRQ_HANDLED;
1455 }
1456#endif
73a19e4c 1457
e1910fcd
GU		 1458 /* I think sci_receive_chars has to be called irrespective
1459 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1460 * to be disabled?
1461 */
1462 sci_receive_chars(ptr);
1463
1464 return IRQ_HANDLED;
73a19e4c
GL		 1465}
1466
e1910fcd 1467static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1468{
e1910fcd 1469 struct uart_port *port = ptr;
04928b79 1470 unsigned long flags;
73a19e4c 1471
04928b79 1472 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1473 sci_transmit_chars(port);
04928b79 1474 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1475
1476 return IRQ_HANDLED;
73a19e4c
GL		 1477}
1478
e1910fcd 1479static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1480{
e1910fcd
GU		 1481 struct uart_port *port = ptr;
1482 struct sci_port *s = to_sci_port(port);
73a19e4c 1483
e1910fcd
GU		 1484 /* Handle errors */
1485 if (port->type == PORT_SCI) {
1486 if (sci_handle_errors(port)) {
1487 /* discard character in rx buffer */
1488 serial_port_in(port, SCxSR);
1489 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1490 }
1491 } else {
1492 sci_handle_fifo_overrun(port);
1493 if (!s->chan_rx)
1494 sci_receive_chars(ptr);
1495 }
1496
1497 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1498
1499 /* Kick the transmission */
1500 if (!s->chan_tx)
1501 sci_tx_interrupt(irq, ptr);
1502
1503 return IRQ_HANDLED;
73a19e4c
GL		 1504}
1505
e1910fcd 1506static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1507{
e1910fcd 1508 struct uart_port *port = ptr;
73a19e4c 1509
e1910fcd
GU		 1510 /* Handle BREAKs */
1511 sci_handle_breaks(port);
1512 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1513
e1910fcd
GU		 1514 return IRQ_HANDLED;
1515}
73a19e4c 1516
e1910fcd
GU		 1517static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1518{
1519 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1520 struct uart_port *port = ptr;
1521 struct sci_port *s = to_sci_port(port);
1522 irqreturn_t ret = IRQ_NONE;
73a19e4c 1523
e1910fcd
GU		 1524 ssr_status = serial_port_in(port, SCxSR);
1525 scr_status = serial_port_in(port, SCSCR);
1526 if (s->overrun_reg == SCxSR)
1527 orer_status = ssr_status;
1528 else {
1529 if (sci_getreg(port, s->overrun_reg)->size)
1530 orer_status = serial_port_in(port, s->overrun_reg);
73a19e4c
GL		 1531 }
1532
e1910fcd 1533 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1534
e1910fcd
GU		 1535 /* Tx Interrupt */
1536 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1537 !s->chan_tx)
1538 ret = sci_tx_interrupt(irq, ptr);
658daa95 1539
e1910fcd
GU		 1540 /*
1541 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1542 * DR flags
1543 */
1544 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1545 (scr_status & SCSCR_RIE))
1546 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1547
e1910fcd
GU		 1548 /* Error Interrupt */
1549 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1550 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1551
e1910fcd
GU		 1552 /* Break Interrupt */
1553 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1554 ret = sci_br_interrupt(irq, ptr);
1555
1556 /* Overrun Interrupt */
1557 if (orer_status & s->overrun_mask) {
1558 sci_handle_fifo_overrun(port);
1559 ret = IRQ_HANDLED;
73a19e4c 1560 }
73a19e4c 1561
e1910fcd
GU		 1562 return ret;
1563}
73a19e4c 1564
e1910fcd
GU		 1565/*
1566 * Here we define a transition notifier so that we can update all of our
1567 * ports' baud rate when the peripheral clock changes.
1568 */
1569static int sci_notifier(struct notifier_block *self,
1570 unsigned long phase, void *p)
1571{
1572 struct sci_port *sci_port;
1573 unsigned long flags;
73a19e4c 1574
e1910fcd 1575 sci_port = container_of(self, struct sci_port, freq_transition);
73a19e4c 1576
e1910fcd
GU		 1577 if (phase == CPUFREQ_POSTCHANGE) {
1578 struct uart_port *port = &sci_port->port;
73a19e4c 1579
e1910fcd
GU		 1580 spin_lock_irqsave(&port->lock, flags);
1581 port->uartclk = clk_get_rate(sci_port->iclk);
1582 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1583 }
1584
e1910fcd
GU		 1585 return NOTIFY_OK;
1586}
73a19e4c 1587
e1910fcd
GU		 1588static const struct sci_irq_desc {
1589 const char *desc;
1590 irq_handler_t handler;
1591} sci_irq_desc[] = {
1592 /*
1593 * Split out handlers, the default case.
1594 */
1595 [SCIx_ERI_IRQ] = {
1596 .desc = "rx err",
1597 .handler = sci_er_interrupt,
1598 },
3089f381 1599
e1910fcd
GU		 1600 [SCIx_RXI_IRQ] = {
1601 .desc = "rx full",
1602 .handler = sci_rx_interrupt,
1603 },
47aceb92 1604
e1910fcd
GU		 1605 [SCIx_TXI_IRQ] = {
1606 .desc = "tx empty",
1607 .handler = sci_tx_interrupt,
1608 },
73a19e4c 1609
e1910fcd
GU		 1610 [SCIx_BRI_IRQ] = {
1611 .desc = "break",
1612 .handler = sci_br_interrupt,
1613 },
73a19e4c
GL		 1614
1615 /*
e1910fcd 1616 * Special muxed handler.
73a19e4c 1617 */
e1910fcd
GU		 1618 [SCIx_MUX_IRQ] = {
1619 .desc = "mux",
1620 .handler = sci_mpxed_interrupt,
1621 },
1622};
73a19e4c 1623
e1910fcd
GU		 1624static int sci_request_irq(struct sci_port *port)
1625{
1626 struct uart_port *up = &port->port;
1627 int i, j, ret = 0;
73a19e4c 1628
e1910fcd
GU		 1629 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1630 const struct sci_irq_desc *desc;
1631 int irq;
73a19e4c 1632
e1910fcd
GU		 1633 if (SCIx_IRQ_IS_MUXED(port)) {
1634 i = SCIx_MUX_IRQ;
1635 irq = up->irq;
1636 } else {
1637 irq = port->irqs[i];
1638
1639 /*
1640 * Certain port types won't support all of the
1641 * available interrupt sources.
1642 */
1643 if (unlikely(irq < 0))
1644 continue;
1645 }
1646
1647 desc = sci_irq_desc + i;
1648 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1649 dev_name(up->dev), desc->desc);
1650 if (!port->irqstr[j])
1651 goto out_nomem;
1652
1653 ret = request_irq(irq, desc->handler, up->irqflags,
1654 port->irqstr[j], port);
1655 if (unlikely(ret)) {
1656 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1657 goto out_noirq;
1658 }
73a19e4c
GL		 1659 }
1660
e1910fcd 1661 return 0;
1da177e4 1662
e1910fcd
GU		 1663out_noirq:
1664 while (--i >= 0)
1665 free_irq(port->irqs[i], port);
f43dc23d 1666
e1910fcd
GU		 1667out_nomem:
1668 while (--j >= 0)
1669 kfree(port->irqstr[j]);
f43dc23d 1670
e1910fcd 1671 return ret;
1da177e4
LT		 1672}
1673
e1910fcd 1674static void sci_free_irq(struct sci_port *port)
1da177e4 1675{
e1910fcd 1676 int i;
1da177e4 1677
e1910fcd
GU		 1678 /*
1679 * Intentionally in reverse order so we iterate over the muxed
1680 * IRQ first.
1681 */
1682 for (i = 0; i < SCIx_NR_IRQS; i++) {
1683 int irq = port->irqs[i];
f43dc23d 1684
e1910fcd
GU		 1685 /*
1686 * Certain port types won't support all of the available
1687 * interrupt sources.
1688 */
1689 if (unlikely(irq < 0))
1690 continue;
f43dc23d 1691
e1910fcd
GU		 1692 free_irq(port->irqs[i], port);
1693 kfree(port->irqstr[i]);
f43dc23d 1694
e1910fcd
GU		 1695 if (SCIx_IRQ_IS_MUXED(port)) {
1696 /* If there's only one IRQ, we're done. */
1697 return;
1698 }
1699 }
1da177e4
LT		 1700}
1701
e1910fcd 1702static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1703{
e1910fcd
GU		 1704 unsigned short status = serial_port_in(port, SCxSR);
1705 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1706
e1910fcd 1707 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1708}
1709
e1910fcd
GU		 1710/*
1711 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1712 * CTS/RTS is supported in hardware by at least one port and controlled
1713 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1714 * handled via the ->init_pins() op, which is a bit of a one-way street,
1715 * lacking any ability to defer pin control -- this will later be
1716 * converted over to the GPIO framework).
1717 *
1718 * Other modes (such as loopback) are supported generically on certain
1719 * port types, but not others. For these it's sufficient to test for the
1720 * existence of the support register and simply ignore the port type.
1721 */
1722static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1723{
e1910fcd
GU		 1724 if (mctrl & TIOCM_LOOP) {
1725 const struct plat_sci_reg *reg;
f43dc23d 1726
e1910fcd
GU		 1727 /*
1728 * Standard loopback mode for SCFCR ports.
1729 */
1730 reg = sci_getreg(port, SCFCR);
1731 if (reg->size)
1732 serial_port_out(port, SCFCR,
1733 serial_port_in(port, SCFCR) |
1734 SCFCR_LOOP);
1735 }
1736}
f43dc23d 1737
e1910fcd
GU		 1738static unsigned int sci_get_mctrl(struct uart_port *port)
1739{
1740 /*
1741 * CTS/RTS is handled in hardware when supported, while nothing
1742 * else is wired up. Keep it simple and simply assert DSR/CAR.
1743 */
1744 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1745}
1746
1da177e4
LT		 1747static void sci_break_ctl(struct uart_port *port, int break_state)
1748{
bbb4ce50 1749 struct sci_port *s = to_sci_port(port);
d3184e68 1750 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1751 unsigned short scscr, scsptr;
1752
a4e02f6d
SY		 1753 /* check wheter the port has SCSPTR */
1754 if (!reg->size) {
bbb4ce50
SY		 1755 /*
1756 * Not supported by hardware. Most parts couple break and rx
1757 * interrupts together, with break detection always enabled.
1758 */
a4e02f6d 1759 return;
bbb4ce50 1760 }
a4e02f6d
SY		 1761
1762 scsptr = serial_port_in(port, SCSPTR);
1763 scscr = serial_port_in(port, SCSCR);
1764
1765 if (break_state == -1) {
1766 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1767 scscr &= ~SCSCR_TE;
1768 } else {
1769 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1770 scscr |= SCSCR_TE;
1771 }
1772
1773 serial_port_out(port, SCSPTR, scsptr);
1774 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1775}
1776
1777static int sci_startup(struct uart_port *port)
1778{
a5660ada 1779 struct sci_port *s = to_sci_port(port);
33b48e16 1780 unsigned long flags;
073e84c9 1781 int ret;
1da177e4 1782
73a19e4c
GL		 1783 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1784
073e84c9
PM		 1785 ret = sci_request_irq(s);
1786 if (unlikely(ret < 0))
1787 return ret;
1788
73a19e4c 1789 sci_request_dma(port);
073e84c9 1790
33b48e16 1791 spin_lock_irqsave(&port->lock, flags);
d656901b 1792 sci_start_tx(port);
73a19e4c 1793 sci_start_rx(port);
33b48e16 1794 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1795
1796 return 0;
1797}
1798
1799static void sci_shutdown(struct uart_port *port)
1800{
a5660ada 1801 struct sci_port *s = to_sci_port(port);
33b48e16 1802 unsigned long flags;
1da177e4 1803
73a19e4c
GL		 1804 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1805
33b48e16 1806 spin_lock_irqsave(&port->lock, flags);
1da177e4 1807 sci_stop_rx(port);
b129a8cc 1808 sci_stop_tx(port);
33b48e16 1809 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1810
73a19e4c 1811 sci_free_dma(port);
1da177e4 1812 sci_free_irq(s);
1da177e4
LT		 1813}
1814
ec09c5eb 1815static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1816 unsigned long freq)
1817{
ec09c5eb
LP		 1818 if (s->sampling_rate)
1819 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1820
26c92f37
PM		 1821 /* Warn, but use a safe default */
1822 WARN_ON(1);
e8183a6c 1823
26c92f37
PM		 1824 return ((freq + 16 * bps) / (32 * bps) - 1);
1825}
1826
730c4e78
NI		 1827/* calculate frame length from SMR */
1828static int sci_baud_calc_frame_len(unsigned int smr_val)
1829{
1830 int len = 10;
1831
1832 if (smr_val & SCSMR_CHR)
1833 len--;
1834 if (smr_val & SCSMR_PE)
1835 len++;
1836 if (smr_val & SCSMR_STOP)
1837 len++;
1838
1839 return len;
1840}
1841
1842
f303b364
UH		 1843/* calculate sample rate, BRR, and clock select for HSCIF */
1844static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1845 int *brr, unsigned int *srr,
730c4e78 1846 unsigned int *cks, int frame_len)
f303b364 1847{
730c4e78 1848 int sr, c, br, err, recv_margin;
f303b364 1849 int min_err = 1000; /* 100% */
730c4e78 1850 int recv_max_margin = 0;
f303b364
UH		 1851
1852 /* Find the combination of sample rate and clock select with the
1853 smallest deviation from the desired baud rate. */
1854 for (sr = 8; sr <= 32; sr++) {
1855 for (c = 0; c <= 3; c++) {
1856 /* integerized formulas from HSCIF documentation */
b7d66397
NI		 1857 br = DIV_ROUND_CLOSEST(freq, (sr *
1858 (1 << (2 * c + 1)) * bps)) - 1;
bcb9973a 1859 br = clamp(br, 0, 255);
b7d66397
NI		 1860 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1861 (1 << (2 * c + 1)) / 1000)) -
1862 1000;
730c4e78
NI		 1863 /* Calc recv margin
1864 * M: Receive margin (%)
1865 * N: Ratio of bit rate to clock (N = sampling rate)
1866 * D: Clock duty (D = 0 to 1.0)
1867 * L: Frame length (L = 9 to 12)
1868 * F: Absolute value of clock frequency deviation
1869 *
1870 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1871 * (|D - 0.5| / N * (1 + F))|
1872 * NOTE: Usually, treat D for 0.5, F is 0 by this
1873 * calculation.
1874 */
1875 recv_margin = abs((500 -
1876 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
f53297fb 1877 if (abs(min_err) > abs(err)) {
f303b364 1878 min_err = err;
730c4e78
NI		 1879 recv_max_margin = recv_margin;
1880 } else if ((min_err == err) &&
1881 (recv_margin > recv_max_margin))
1882 recv_max_margin = recv_margin;
1883 else
1884 continue;
1885
1886 *brr = br;
1887 *srr = sr - 1;
1888 *cks = c;
f303b364
UH		 1889 }
1890 }
1891
1892 if (min_err == 1000) {
1893 WARN_ON(1);
1894 /* use defaults */
1895 *brr = 255;
1896 *srr = 15;
1897 *cks = 0;
1898 }
1899}
1900
1ba76220
MD		 1901static void sci_reset(struct uart_port *port)
1902{
d3184e68 1903 const struct plat_sci_reg *reg;
1ba76220
MD		 1904 unsigned int status;
1905
1906 do {
b12bb29f 1907 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1908 } while (!(status & SCxSR_TEND(port)));
1909
b12bb29f 1910 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1911
0979e0e6
PM		 1912 reg = sci_getreg(port, SCFCR);
1913 if (reg->size)
b12bb29f 1914 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1915}
1916
606d099c
AC		 1917static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1918 struct ktermios *old)
1da177e4 1919{
00b9de9c 1920 struct sci_port *s = to_sci_port(port);
d3184e68 1921 const struct plat_sci_reg *reg;
730c4e78 1922 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 1923 int t = -1;
d4759ded 1924 unsigned int srr = 15;
1da177e4 1925
730c4e78
NI		 1926 if ((termios->c_cflag & CSIZE) == CS7)
1927 smr_val |= SCSMR_CHR;
1928 if (termios->c_cflag & PARENB)
1929 smr_val |= SCSMR_PE;
1930 if (termios->c_cflag & PARODD)
1931 smr_val |= SCSMR_PE | SCSMR_ODD;
1932 if (termios->c_cflag & CSTOPB)
1933 smr_val |= SCSMR_STOP;
1934
154280fd
MD		 1935 /*
1936 * earlyprintk comes here early on with port->uartclk set to zero.
1937 * the clock framework is not up and running at this point so here
1938 * we assume that 115200 is the maximum baud rate. please note that
1939 * the baud rate is not programmed during earlyprintk - it is assumed
1940 * that the previous boot loader has enabled required clocks and
1941 * setup the baud rate generator hardware for us already.
1942 */
1943 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1944
154280fd 1945 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1946 if (likely(baud && port->uartclk)) {
ec09c5eb 1947 if (s->cfg->type == PORT_HSCIF) {
730c4e78 1948 int frame_len = sci_baud_calc_frame_len(smr_val);
f303b364 1949 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
730c4e78 1950 &cks, frame_len);
f303b364 1951 } else {
ec09c5eb 1952 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 1953 for (cks = 0; t >= 256 && cks <= 3; cks++)
1954 t >>= 2;
1955 }
1956 }
e108b2ca 1957
23241d43 1958 sci_port_enable(s);
36003386 1959
1ba76220 1960 sci_reset(port);
1da177e4 1961
2944a331 1962 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1da177e4
LT		 1963
1964 uart_update_timeout(port, termios->c_cflag, baud);
1965
9d482cc3
TY		 1966 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1967 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1968
4ffc3cdb 1969 if (t >= 0) {
26de4f1b 1970 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 1971 serial_port_out(port, SCBRR, t);
f303b364
UH		 1972 reg = sci_getreg(port, HSSRR);
1973 if (reg->size)
1974 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1975 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1976 } else
1977 serial_port_out(port, SCSMR, smr_val);
1da177e4 1978
d5701647 1979 sci_init_pins(port, termios->c_cflag);
0979e0e6 1980
73c3d53f
PM		 1981 reg = sci_getreg(port, SCFCR);
1982 if (reg->size) {
b12bb29f 1983 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1984
73c3d53f 1985 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1986 if (termios->c_cflag & CRTSCTS)
1987 ctrl |= SCFCR_MCE;
1988 else
1989 ctrl &= ~SCFCR_MCE;
faf02f8f 1990 }
73c3d53f
PM		 1991
1992 /*
1993 * As we've done a sci_reset() above, ensure we don't
1994 * interfere with the FIFOs while toggling MCE. As the
1995 * reset values could still be set, simply mask them out.
1996 */
1997 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1998
b12bb29f 1999 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2000 }
b7a76e4b 2001
b12bb29f 2002 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 2003
3089f381
GL		 2004#ifdef CONFIG_SERIAL_SH_SCI_DMA
2005 /*
5f6d8515 2006 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2007 * See serial_core.c::uart_update_timeout().
2008 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2009 * function calculates 1 jiffie for the data plus 5 jiffies for the
2010 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2011 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2012 * value obtained by this formula is too small. Therefore, if the value
2013 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2014 */
2015 if (s->chan_rx) {
5f6d8515
NI		 2016 unsigned int bits;
2017
2018 /* byte size and parity */
2019 switch (termios->c_cflag & CSIZE) {
2020 case CS5:
2021 bits = 7;
2022 break;
2023 case CS6:
2024 bits = 8;
2025 break;
2026 case CS7:
2027 bits = 9;
2028 break;
2029 default:
2030 bits = 10;
2031 break;
2032 }
2033
2034 if (termios->c_cflag & CSTOPB)
2035 bits++;
2036 if (termios->c_cflag & PARENB)
2037 bits++;
2038 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2039 (baud / 10), 10);
9b971cd2 2040 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2041 s->rx_timeout * 1000 / HZ, port->timeout);
2042 if (s->rx_timeout < msecs_to_jiffies(20))
2043 s->rx_timeout = msecs_to_jiffies(20);
2044 }
2045#endif
2046
1da177e4 2047 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2048 sci_start_rx(port);
36003386 2049
23241d43 2050 sci_port_disable(s);
1da177e4
LT		 2051}
2052
0174e5ca
TK		 2053static void sci_pm(struct uart_port *port, unsigned int state,
2054 unsigned int oldstate)
2055{
2056 struct sci_port *sci_port = to_sci_port(port);
2057
2058 switch (state) {
d3dfe5d9 2059 case UART_PM_STATE_OFF:
0174e5ca
TK		 2060 sci_port_disable(sci_port);
2061 break;
2062 default:
2063 sci_port_enable(sci_port);
2064 break;
2065 }
2066}
2067
1da177e4
LT		 2068static const char *sci_type(struct uart_port *port)
2069{
2070 switch (port->type) {
e7c98dc7
MT		 2071 case PORT_IRDA:
2072 return "irda";
2073 case PORT_SCI:
2074 return "sci";
2075 case PORT_SCIF:
2076 return "scif";
2077 case PORT_SCIFA:
2078 return "scifa";
d1d4b10c
GL		 2079 case PORT_SCIFB:
2080 return "scifb";
f303b364
UH		 2081 case PORT_HSCIF:
2082 return "hscif";
1da177e4
LT		 2083 }
2084
fa43972f 2085 return NULL;
1da177e4
LT		 2086}
2087
f6e9495d
PM		 2088static int sci_remap_port(struct uart_port *port)
2089{
e4d6f911 2090 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2091
2092 /*
2093 * Nothing to do if there's already an established membase.
2094 */
2095 if (port->membase)
2096 return 0;
2097
2098 if (port->flags & UPF_IOREMAP) {
e4d6f911 2099 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2100 if (unlikely(!port->membase)) {
2101 dev_err(port->dev, "can't remap port#%d\n", port->line);
2102 return -ENXIO;
2103 }
2104 } else {
2105 /*
2106 * For the simple (and majority of) cases where we don't
2107 * need to do any remapping, just cast the cookie
2108 * directly.
2109 */
3af4e960 2110 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2111 }
2112
2113 return 0;
2114}
2115
e2651647 2116static void sci_release_port(struct uart_port *port)
1da177e4 2117{
e4d6f911
YS		 2118 struct sci_port *sport = to_sci_port(port);
2119
e2651647
PM		 2120 if (port->flags & UPF_IOREMAP) {
2121 iounmap(port->membase);
2122 port->membase = NULL;
2123 }
2124
e4d6f911 2125 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2126}
2127
e2651647 2128static int sci_request_port(struct uart_port *port)
1da177e4 2129{
e2651647 2130 struct resource *res;
e4d6f911 2131 struct sci_port *sport = to_sci_port(port);
f6e9495d 2132 int ret;
1da177e4 2133
e4d6f911
YS		 2134 res = request_mem_region(port->mapbase, sport->reg_size,
2135 dev_name(port->dev));
2136 if (unlikely(res == NULL)) {
2137 dev_err(port->dev, "request_mem_region failed.");
e2651647 2138 return -EBUSY;
e4d6f911 2139 }
1da177e4 2140
f6e9495d
PM		 2141 ret = sci_remap_port(port);
2142 if (unlikely(ret != 0)) {
2143 release_resource(res);
2144 return ret;
7ff731ae 2145 }
e2651647
PM		 2146
2147 return 0;
2148}
2149
2150static void sci_config_port(struct uart_port *port, int flags)
2151{
2152 if (flags & UART_CONFIG_TYPE) {
2153 struct sci_port *sport = to_sci_port(port);
2154
2155 port->type = sport->cfg->type;
2156 sci_request_port(port);
2157 }
1da177e4
LT		 2158}
2159
2160static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2161{
1da177e4
LT		 2162 if (ser->baud_base < 2400)
2163 /* No paper tape reader for Mitch.. */
2164 return -EINVAL;
2165
2166 return 0;
2167}
2168
2169static struct uart_ops sci_uart_ops = {
2170 .tx_empty = sci_tx_empty,
2171 .set_mctrl = sci_set_mctrl,
2172 .get_mctrl = sci_get_mctrl,
2173 .start_tx = sci_start_tx,
2174 .stop_tx = sci_stop_tx,
2175 .stop_rx = sci_stop_rx,
1da177e4
LT		 2176 .break_ctl = sci_break_ctl,
2177 .startup = sci_startup,
2178 .shutdown = sci_shutdown,
2179 .set_termios = sci_set_termios,
0174e5ca 2180 .pm = sci_pm,
1da177e4
LT		 2181 .type = sci_type,
2182 .release_port = sci_release_port,
2183 .request_port = sci_request_port,
2184 .config_port = sci_config_port,
2185 .verify_port = sci_verify_port,
07d2a1a1
PM		 2186#ifdef CONFIG_CONSOLE_POLL
2187 .poll_get_char = sci_poll_get_char,
2188 .poll_put_char = sci_poll_put_char,
2189#endif
1da177e4
LT		 2190};
2191
9671f099 2192static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2193 struct sci_port *sci_port, unsigned int index,
2194 struct plat_sci_port *p, bool early)
e108b2ca 2195{
73a19e4c 2196 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2197 const struct resource *res;
2198 unsigned int i;
3127c6b2 2199 int ret;
e108b2ca 2200
50f0959a
PM		 2201 sci_port->cfg = p;
2202
73a19e4c
GL		 2203 port->ops = &sci_uart_ops;
2204 port->iotype = UPIO_MEM;
2205 port->line = index;
75136d48 2206
89b5c1ab
LP		 2207 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2208 if (res == NULL)
2209 return -ENOMEM;
1fcc91a6 2210
89b5c1ab 2211 port->mapbase = res->start;
e4d6f911 2212 sci_port->reg_size = resource_size(res);
1fcc91a6 2213
89b5c1ab
LP		 2214 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2215 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2216
89b5c1ab
LP		 2217 /* The SCI generates several interrupts. They can be muxed together or
2218 * connected to different interrupt lines. In the muxed case only one
2219 * interrupt resource is specified. In the non-muxed case three or four
2220 * interrupt resources are specified, as the BRI interrupt is optional.
2221 */
2222 if (sci_port->irqs[0] < 0)
2223 return -ENXIO;
1fcc91a6 2224
89b5c1ab
LP		 2225 if (sci_port->irqs[1] < 0) {
2226 sci_port->irqs[1] = sci_port->irqs[0];
2227 sci_port->irqs[2] = sci_port->irqs[0];
2228 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2229 }
2230
b545e4f4
LP		 2231 if (p->regtype == SCIx_PROBE_REGTYPE) {
2232 ret = sci_probe_regmap(p);
2233 if (unlikely(ret))
2234 return ret;
2235 }
2236
75136d48 2237 switch (p->type) {
d1d4b10c
GL		 2238 case PORT_SCIFB:
2239 port->fifosize = 256;
2e0842a1 2240 sci_port->overrun_reg = SCxSR;
75c249fd 2241 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2242 sci_port->sampling_rate = 16;
d1d4b10c 2243 break;
f303b364
UH		 2244 case PORT_HSCIF:
2245 port->fifosize = 128;
2e0842a1 2246 sci_port->overrun_reg = SCLSR;
75c249fd 2247 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2248 sci_port->sampling_rate = 0;
f303b364 2249 break;
75136d48 2250 case PORT_SCIFA:
73a19e4c 2251 port->fifosize = 64;
2e0842a1 2252 sci_port->overrun_reg = SCxSR;
75c249fd 2253 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2254 sci_port->sampling_rate = 16;
75136d48
MP		 2255 break;
2256 case PORT_SCIF:
73a19e4c 2257 port->fifosize = 16;
ec09c5eb 2258 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2259 sci_port->overrun_reg = SCxSR;
75c249fd 2260 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2261 sci_port->sampling_rate = 16;
ec09c5eb 2262 } else {
2e0842a1 2263 sci_port->overrun_reg = SCLSR;
75c249fd 2264 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2265 sci_port->sampling_rate = 32;
ec09c5eb 2266 }
75136d48
MP		 2267 break;
2268 default:
73a19e4c 2269 port->fifosize = 1;
2e0842a1 2270 sci_port->overrun_reg = SCxSR;
75c249fd 2271 sci_port->overrun_mask = SCI_ORER;
f84b6bdc 2272 sci_port->sampling_rate = 32;
75136d48
MP		 2273 break;
2274 }
7b6fd3bf 2275
878fbb91
LP		 2276 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2277 * match the SoC datasheet, this should be investigated. Let platform
2278 * data override the sampling rate for now.
ec09c5eb 2279 */
f84b6bdc
GU		 2280 if (p->sampling_rate)
2281 sci_port->sampling_rate = p->sampling_rate;
ec09c5eb 2282
1fcc91a6 2283 if (!early) {
c7ed1ab3
PM		 2284 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2285 if (IS_ERR(sci_port->iclk)) {
2286 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2287 if (IS_ERR(sci_port->iclk)) {
2288 dev_err(&dev->dev, "can't get iclk\n");
2289 return PTR_ERR(sci_port->iclk);
2290 }
2291 }
2292
2293 /*
2294 * The function clock is optional, ignore it if we can't
2295 * find it.
2296 */
2297 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2298 if (IS_ERR(sci_port->fclk))
2299 sci_port->fclk = NULL;
2300
73a19e4c 2301 port->dev = &dev->dev;
5e50d2d6
MD		 2302
2303 pm_runtime_enable(&dev->dev);
7b6fd3bf 2304 }
e108b2ca 2305
7ed7e071
MD		 2306 sci_port->break_timer.data = (unsigned long)sci_port;
2307 sci_port->break_timer.function = sci_break_timer;
2308 init_timer(&sci_port->break_timer);
2309
debf9507
PM		 2310 /*
2311 * Establish some sensible defaults for the error detection.
2312 */
5da0f468
GU		 2313 if (p->type == PORT_SCI) {
2314 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2315 sci_port->error_clear = SCI_ERROR_CLEAR;
2316 } else {
2317 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2318 sci_port->error_clear = SCIF_ERROR_CLEAR;
2319 }
debf9507 2320
3ae988d9
LP		 2321 /*
2322 * Make the error mask inclusive of overrun detection, if
2323 * supported.
2324 */
5da0f468 2325 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2326 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2327 sci_port->error_clear &= ~sci_port->overrun_mask;
2328 }
debf9507 2329
ce6738b6 2330 port->type = p->type;
b6e4a3f1 2331 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2332 port->regshift = p->regshift;
73a19e4c 2333
ce6738b6 2334 /*
61a6976b 2335 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2336 * for the multi-IRQ ports, which is where we are primarily
2337 * concerned with the shutdown path synchronization.
2338 *
2339 * For the muxed case there's nothing more to do.
2340 */
1fcc91a6 2341 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2342 port->irqflags = 0;
73a19e4c 2343
61a6976b
PM		 2344 port->serial_in = sci_serial_in;
2345 port->serial_out = sci_serial_out;
2346
937bb6e4
GL		 2347 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2348 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2349 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2350
c7ed1ab3 2351 return 0;
e108b2ca
PM		 2352}
2353
6dae1421
LP		 2354static void sci_cleanup_single(struct sci_port *port)
2355{
6dae1421
LP		 2356 clk_put(port->iclk);
2357 clk_put(port->fclk);
2358
2359 pm_runtime_disable(port->port.dev);
2360}
2361
1da177e4 2362#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2363static void serial_console_putchar(struct uart_port *port, int ch)
2364{
2365 sci_poll_put_char(port, ch);
2366}
2367
1da177e4
LT		 2368/*
2369 * Print a string to the serial port trying not to disturb
2370 * any possible real use of the port...
2371 */
2372static void serial_console_write(struct console *co, const char *s,
2373 unsigned count)
2374{
906b17dc
PM		 2375 struct sci_port *sci_port = &sci_ports[co->index];
2376 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2377 unsigned short bits, ctrl;
2378 unsigned long flags;
2379 int locked = 1;
2380
2381 local_irq_save(flags);
2382 if (port->sysrq)
2383 locked = 0;
2384 else if (oops_in_progress)
2385 locked = spin_trylock(&port->lock);
2386 else
2387 spin_lock(&port->lock);
2388
2389 /* first save the SCSCR then disable the interrupts */
2390 ctrl = serial_port_in(port, SCSCR);
2391 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2392
501b825d 2393 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2394
2395 /* wait until fifo is empty and last bit has been transmitted */
2396 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2397 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2398 cpu_relax();
40f70c03
SK		 2399
2400 /* restore the SCSCR */
2401 serial_port_out(port, SCSCR, ctrl);
2402
2403 if (locked)
2404 spin_unlock(&port->lock);
2405 local_irq_restore(flags);
1da177e4
LT		 2406}
2407
9671f099 2408static int serial_console_setup(struct console *co, char *options)
1da177e4 2409{
dc8e6f5b 2410 struct sci_port *sci_port;
1da177e4
LT		 2411 struct uart_port *port;
2412 int baud = 115200;
2413 int bits = 8;
2414 int parity = 'n';
2415 int flow = 'n';
2416 int ret;
2417
e108b2ca 2418 /*
906b17dc 2419 * Refuse to handle any bogus ports.
1da177e4 2420 */
906b17dc 2421 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2422 return -ENODEV;
e108b2ca 2423
906b17dc
PM		 2424 sci_port = &sci_ports[co->index];
2425 port = &sci_port->port;
2426
b2267a6b
AC		 2427 /*
2428 * Refuse to handle uninitialized ports.
2429 */
2430 if (!port->ops)
2431 return -ENODEV;
2432
f6e9495d
PM		 2433 ret = sci_remap_port(port);
2434 if (unlikely(ret != 0))
2435 return ret;
e108b2ca 2436
1da177e4
LT		 2437 if (options)
2438 uart_parse_options(options, &baud, &parity, &bits, &flow);
2439
ab7cfb55 2440 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2441}
2442
2443static struct console serial_console = {
2444 .name = "ttySC",
906b17dc 2445 .device = uart_console_device,
1da177e4
LT		 2446 .write = serial_console_write,
2447 .setup = serial_console_setup,
fa5da2f7 2448 .flags = CON_PRINTBUFFER,
1da177e4 2449 .index = -1,
906b17dc 2450 .data = &sci_uart_driver,
1da177e4
LT		 2451};
2452
7b6fd3bf
MD		 2453static struct console early_serial_console = {
2454 .name = "early_ttySC",
2455 .write = serial_console_write,
2456 .flags = CON_PRINTBUFFER,
906b17dc 2457 .index = -1,
7b6fd3bf 2458};
ecdf8a46 2459
7b6fd3bf
MD		 2460static char early_serial_buf[32];
2461
9671f099 2462static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2463{
574de559 2464 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2465
2466 if (early_serial_console.data)
2467 return -EEXIST;
2468
2469 early_serial_console.index = pdev->id;
ecdf8a46 2470
1fcc91a6 2471 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2472
2473 serial_console_setup(&early_serial_console, early_serial_buf);
2474
2475 if (!strstr(early_serial_buf, "keep"))
2476 early_serial_console.flags |= CON_BOOT;
2477
2478 register_console(&early_serial_console);
2479 return 0;
2480}
6a8c9799
NI		 2481
2482#define SCI_CONSOLE (&serial_console)
2483
ecdf8a46 2484#else
9671f099 2485static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2486{
2487 return -EINVAL;
2488}
1da177e4 2489
6a8c9799
NI		 2490#define SCI_CONSOLE NULL
2491
2492#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2493
6c13d5d2 2494static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2495
2496static struct uart_driver sci_uart_driver = {
2497 .owner = THIS_MODULE,
2498 .driver_name = "sci",
1da177e4
LT		 2499 .dev_name = "ttySC",
2500 .major = SCI_MAJOR,
2501 .minor = SCI_MINOR_START,
e108b2ca 2502 .nr = SCI_NPORTS,
1da177e4
LT		 2503 .cons = SCI_CONSOLE,
2504};
2505
54507f6e 2506static int sci_remove(struct platform_device *dev)
e552de24 2507{
d535a230 2508 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2509
d535a230
PM		 2510 cpufreq_unregister_notifier(&port->freq_transition,
2511 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2512
d535a230
PM		 2513 uart_remove_one_port(&sci_uart_driver, &port->port);
2514
6dae1421 2515 sci_cleanup_single(port);
e552de24 2516
e552de24
MD		 2517 return 0;
2518}
2519
20bdcab8
BH		 2520struct sci_port_info {
2521 unsigned int type;
2522 unsigned int regtype;
2523};
2524
2525static const struct of_device_id of_sci_match[] = {
2526 {
2527 .compatible = "renesas,scif",
ff43da00 2528 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2529 .type = PORT_SCIF,
2530 .regtype = SCIx_SH4_SCIF_REGTYPE,
2531 },
2532 }, {
2533 .compatible = "renesas,scifa",
ff43da00 2534 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2535 .type = PORT_SCIFA,
2536 .regtype = SCIx_SCIFA_REGTYPE,
2537 },
2538 }, {
2539 .compatible = "renesas,scifb",
ff43da00 2540 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2541 .type = PORT_SCIFB,
2542 .regtype = SCIx_SCIFB_REGTYPE,
2543 },
2544 }, {
2545 .compatible = "renesas,hscif",
ff43da00 2546 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2547 .type = PORT_HSCIF,
2548 .regtype = SCIx_HSCIF_REGTYPE,
2549 },
e1d0be61
YS		 2550 }, {
2551 .compatible = "renesas,sci",
2552 .data = &(const struct sci_port_info) {
2553 .type = PORT_SCI,
2554 .regtype = SCIx_SCI_REGTYPE,
2555 },
20bdcab8
BH		 2556 }, {
2557 /* Terminator */
2558 },
2559};
2560MODULE_DEVICE_TABLE(of, of_sci_match);
2561
2562static struct plat_sci_port *
2563sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2564{
2565 struct device_node *np = pdev->dev.of_node;
2566 const struct of_device_id *match;
2567 const struct sci_port_info *info;
2568 struct plat_sci_port *p;
2569 int id;
2570
2571 if (!IS_ENABLED(CONFIG_OF) || !np)
2572 return NULL;
2573
2574 match = of_match_node(of_sci_match, pdev->dev.of_node);
2575 if (!match)
2576 return NULL;
2577
2578 info = match->data;
2579
2580 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2581 if (!p)
20bdcab8 2582 return NULL;
20bdcab8
BH		 2583
2584 /* Get the line number for the aliases node. */
2585 id = of_alias_get_id(np, "serial");
2586 if (id < 0) {
2587 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2588 return NULL;
2589 }
2590
2591 *dev_id = id;
2592
2593 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2594 p->type = info->type;
2595 p->regtype = info->regtype;
2596 p->scscr = SCSCR_RE | SCSCR_TE;
2597
2598 return p;
2599}
2600
9671f099 2601static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2602 unsigned int index,
2603 struct plat_sci_port *p,
2604 struct sci_port *sciport)
2605{
0ee70712
MD		 2606 int ret;
2607
2608 /* Sanity check */
2609 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2610 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2611 index+1, SCI_NPORTS);
9b971cd2 2612 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2613 return -EINVAL;
0ee70712
MD		 2614 }
2615
1fcc91a6 2616 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2617 if (ret)
2618 return ret;
0ee70712 2619
6dae1421
LP		 2620 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2621 if (ret) {
2622 sci_cleanup_single(sciport);
2623 return ret;
2624 }
2625
2626 return 0;
0ee70712
MD		 2627}
2628
9671f099 2629static int sci_probe(struct platform_device *dev)
1da177e4 2630{
20bdcab8
BH		 2631 struct plat_sci_port *p;
2632 struct sci_port *sp;
2633 unsigned int dev_id;
ecdf8a46 2634 int ret;
d535a230 2635
ecdf8a46
PM		 2636 /*
2637 * If we've come here via earlyprintk initialization, head off to
2638 * the special early probe. We don't have sufficient device state
2639 * to make it beyond this yet.
2640 */
2641 if (is_early_platform_device(dev))
2642 return sci_probe_earlyprintk(dev);
7b6fd3bf 2643
20bdcab8
BH		 2644 if (dev->dev.of_node) {
2645 p = sci_parse_dt(dev, &dev_id);
2646 if (p == NULL)
2647 return -EINVAL;
2648 } else {
2649 p = dev->dev.platform_data;
2650 if (p == NULL) {
2651 dev_err(&dev->dev, "no platform data supplied\n");
2652 return -EINVAL;
2653 }
2654
2655 dev_id = dev->id;
2656 }
2657
2658 sp = &sci_ports[dev_id];
d535a230 2659 platform_set_drvdata(dev, sp);
e552de24 2660
20bdcab8 2661 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2662 if (ret)
6dae1421 2663 return ret;
e552de24 2664
d535a230 2665 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2666
d535a230
PM		 2667 ret = cpufreq_register_notifier(&sp->freq_transition,
2668 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2669 if (unlikely(ret < 0)) {
bf13c9a8 2670 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2671 sci_cleanup_single(sp);
2672 return ret;
2673 }
1da177e4
LT		 2674
2675#ifdef CONFIG_SH_STANDARD_BIOS
2676 sh_bios_gdb_detach();
2677#endif
2678
e108b2ca 2679 return 0;
1da177e4
LT		 2680}
2681
cb876341 2682static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2683{
d535a230 2684 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2685
d535a230
PM		 2686 if (sport)
2687 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2688
e108b2ca
PM		 2689 return 0;
2690}
1da177e4 2691
cb876341 2692static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2693{
d535a230 2694 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2695
d535a230
PM		 2696 if (sport)
2697 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2698
2699 return 0;
2700}
2701
cb876341 2702static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2703
e108b2ca
PM		 2704static struct platform_driver sci_driver = {
2705 .probe = sci_probe,
b9e39c89 2706 .remove = sci_remove,
e108b2ca
PM		 2707 .driver = {
2708 .name = "sh-sci",
6daa79b3 2709 .pm = &sci_dev_pm_ops,
20bdcab8 2710 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2711 },
2712};
2713
2714static int __init sci_init(void)
2715{
2716 int ret;
2717
6c13d5d2 2718 pr_info("%s\n", banner);
e108b2ca 2719
e108b2ca
PM		 2720 ret = uart_register_driver(&sci_uart_driver);
2721 if (likely(ret == 0)) {
2722 ret = platform_driver_register(&sci_driver);
2723 if (unlikely(ret))
2724 uart_unregister_driver(&sci_uart_driver);
2725 }
2726
2727 return ret;
2728}
2729
2730static void __exit sci_exit(void)
2731{
2732 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2733 uart_unregister_driver(&sci_uart_driver);
2734}
2735
7b6fd3bf
MD		 2736#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2737early_platform_init_buffer("earlyprintk", &sci_driver,
2738 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2739#endif
1da177e4
LT		 2740module_init(sci_init);
2741module_exit(sci_exit);
2742
e108b2ca 2743MODULE_LICENSE("GPL");
e169c139 2744MODULE_ALIAS("platform:sh-sci");
7f405f9c 2745MODULE_AUTHOR("Paul Mundt");
f303b364 2746MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
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