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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) |
3 | * | |
f43dc23d | 4 | * Copyright (C) 2002 - 2011 Paul Mundt |
3ea6bc3d | 5 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). |
1da177e4 LT |
6 | * |
7 | * based off of the old drivers/char/sh-sci.c by: | |
8 | * | |
9 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
10 | * Copyright (C) 2000 Sugioka Toshinobu | |
11 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
12 | * Modified to support SecureEdge. David McCullough (2002) | |
13 | * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). | |
d89ddd1c | 14 | * Removed SH7300 support (Jul 2007). |
1da177e4 LT |
15 | * |
16 | * This file is subject to the terms and conditions of the GNU General Public | |
17 | * License. See the file "COPYING" in the main directory of this archive | |
18 | * for more details. | |
19 | */ | |
0b3d4ef6 PM |
20 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
21 | #define SUPPORT_SYSRQ | |
22 | #endif | |
1da177e4 LT |
23 | |
24 | #undef DEBUG | |
25 | ||
8fb9631c LP |
26 | #include <linux/clk.h> |
27 | #include <linux/console.h> | |
28 | #include <linux/ctype.h> | |
29 | #include <linux/cpufreq.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/dmaengine.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/err.h> | |
1da177e4 | 34 | #include <linux/errno.h> |
8fb9631c | 35 | #include <linux/init.h> |
1da177e4 | 36 | #include <linux/interrupt.h> |
1da177e4 | 37 | #include <linux/ioport.h> |
8fb9631c LP |
38 | #include <linux/major.h> |
39 | #include <linux/module.h> | |
1da177e4 | 40 | #include <linux/mm.h> |
1da177e4 | 41 | #include <linux/notifier.h> |
20bdcab8 | 42 | #include <linux/of.h> |
8fb9631c | 43 | #include <linux/platform_device.h> |
5e50d2d6 | 44 | #include <linux/pm_runtime.h> |
73a19e4c | 45 | #include <linux/scatterlist.h> |
8fb9631c LP |
46 | #include <linux/serial.h> |
47 | #include <linux/serial_sci.h> | |
48 | #include <linux/sh_dma.h> | |
5a0e3ad6 | 49 | #include <linux/slab.h> |
8fb9631c LP |
50 | #include <linux/string.h> |
51 | #include <linux/sysrq.h> | |
52 | #include <linux/timer.h> | |
53 | #include <linux/tty.h> | |
54 | #include <linux/tty_flip.h> | |
85f094ec PM |
55 | |
56 | #ifdef CONFIG_SUPERH | |
1da177e4 LT |
57 | #include <asm/sh_bios.h> |
58 | #endif | |
59 | ||
1da177e4 LT |
60 | #include "sh-sci.h" |
61 | ||
89b5c1ab LP |
62 | /* Offsets into the sci_port->irqs array */ |
63 | enum { | |
64 | SCIx_ERI_IRQ, | |
65 | SCIx_RXI_IRQ, | |
66 | SCIx_TXI_IRQ, | |
67 | SCIx_BRI_IRQ, | |
68 | SCIx_NR_IRQS, | |
69 | ||
70 | SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ | |
71 | }; | |
72 | ||
73 | #define SCIx_IRQ_IS_MUXED(port) \ | |
74 | ((port)->irqs[SCIx_ERI_IRQ] == \ | |
75 | (port)->irqs[SCIx_RXI_IRQ]) || \ | |
76 | ((port)->irqs[SCIx_ERI_IRQ] && \ | |
77 | ((port)->irqs[SCIx_RXI_IRQ] < 0)) | |
78 | ||
e108b2ca PM |
79 | struct sci_port { |
80 | struct uart_port port; | |
81 | ||
ce6738b6 PM |
82 | /* Platform configuration */ |
83 | struct plat_sci_port *cfg; | |
2e0842a1 | 84 | unsigned int overrun_reg; |
75c249fd | 85 | unsigned int overrun_mask; |
3ae988d9 | 86 | unsigned int error_mask; |
5da0f468 | 87 | unsigned int error_clear; |
ec09c5eb | 88 | unsigned int sampling_rate; |
e4d6f911 | 89 | resource_size_t reg_size; |
e108b2ca | 90 | |
e108b2ca PM |
91 | /* Break timer */ |
92 | struct timer_list break_timer; | |
93 | int break_flag; | |
1534a3b3 | 94 | |
501b825d MD |
95 | /* Interface clock */ |
96 | struct clk *iclk; | |
c7ed1ab3 PM |
97 | /* Function clock */ |
98 | struct clk *fclk; | |
edad1f20 | 99 | |
1fcc91a6 | 100 | int irqs[SCIx_NR_IRQS]; |
9174fc8f PM |
101 | char *irqstr[SCIx_NR_IRQS]; |
102 | ||
73a19e4c GL |
103 | struct dma_chan *chan_tx; |
104 | struct dma_chan *chan_rx; | |
f43dc23d | 105 | |
73a19e4c | 106 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
73a19e4c GL |
107 | dma_cookie_t cookie_tx; |
108 | dma_cookie_t cookie_rx[2]; | |
109 | dma_cookie_t active_rx; | |
79904420 GU |
110 | dma_addr_t tx_dma_addr; |
111 | unsigned int tx_dma_len; | |
73a19e4c | 112 | struct scatterlist sg_rx[2]; |
7b39d901 | 113 | void *rx_buf[2]; |
73a19e4c GL |
114 | size_t buf_len_rx; |
115 | struct sh_dmae_slave param_tx; | |
116 | struct sh_dmae_slave param_rx; | |
117 | struct work_struct work_tx; | |
118 | struct work_struct work_rx; | |
119 | struct timer_list rx_timer; | |
3089f381 | 120 | unsigned int rx_timeout; |
73a19e4c | 121 | #endif |
e552de24 | 122 | |
d535a230 | 123 | struct notifier_block freq_transition; |
e108b2ca PM |
124 | }; |
125 | ||
1da177e4 | 126 | /* Function prototypes */ |
d535a230 | 127 | static void sci_start_tx(struct uart_port *port); |
b129a8cc | 128 | static void sci_stop_tx(struct uart_port *port); |
d535a230 | 129 | static void sci_start_rx(struct uart_port *port); |
1da177e4 | 130 | |
e108b2ca | 131 | #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS |
b7a76e4b | 132 | |
e108b2ca PM |
133 | static struct sci_port sci_ports[SCI_NPORTS]; |
134 | static struct uart_driver sci_uart_driver; | |
1da177e4 | 135 | |
e7c98dc7 MT |
136 | static inline struct sci_port * |
137 | to_sci_port(struct uart_port *uart) | |
138 | { | |
139 | return container_of(uart, struct sci_port, port); | |
140 | } | |
141 | ||
61a6976b PM |
142 | struct plat_sci_reg { |
143 | u8 offset, size; | |
144 | }; | |
145 | ||
146 | /* Helper for invalidating specific entries of an inherited map. */ | |
147 | #define sci_reg_invalid { .offset = 0, .size = 0 } | |
148 | ||
d3184e68 | 149 | static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { |
61a6976b PM |
150 | [SCIx_PROBE_REGTYPE] = { |
151 | [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, | |
152 | }, | |
153 | ||
154 | /* | |
155 | * Common SCI definitions, dependent on the port's regshift | |
156 | * value. | |
157 | */ | |
158 | [SCIx_SCI_REGTYPE] = { | |
159 | [SCSMR] = { 0x00, 8 }, | |
160 | [SCBRR] = { 0x01, 8 }, | |
161 | [SCSCR] = { 0x02, 8 }, | |
162 | [SCxTDR] = { 0x03, 8 }, | |
163 | [SCxSR] = { 0x04, 8 }, | |
164 | [SCxRDR] = { 0x05, 8 }, | |
165 | [SCFCR] = sci_reg_invalid, | |
166 | [SCFDR] = sci_reg_invalid, | |
167 | [SCTFDR] = sci_reg_invalid, | |
168 | [SCRFDR] = sci_reg_invalid, | |
169 | [SCSPTR] = sci_reg_invalid, | |
170 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 171 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
172 | [SCPCR] = sci_reg_invalid, |
173 | [SCPDR] = sci_reg_invalid, | |
61a6976b PM |
174 | }, |
175 | ||
176 | /* | |
177 | * Common definitions for legacy IrDA ports, dependent on | |
178 | * regshift value. | |
179 | */ | |
180 | [SCIx_IRDA_REGTYPE] = { | |
181 | [SCSMR] = { 0x00, 8 }, | |
182 | [SCBRR] = { 0x01, 8 }, | |
183 | [SCSCR] = { 0x02, 8 }, | |
184 | [SCxTDR] = { 0x03, 8 }, | |
185 | [SCxSR] = { 0x04, 8 }, | |
186 | [SCxRDR] = { 0x05, 8 }, | |
187 | [SCFCR] = { 0x06, 8 }, | |
188 | [SCFDR] = { 0x07, 16 }, | |
189 | [SCTFDR] = sci_reg_invalid, | |
190 | [SCRFDR] = sci_reg_invalid, | |
191 | [SCSPTR] = sci_reg_invalid, | |
192 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 193 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
194 | [SCPCR] = sci_reg_invalid, |
195 | [SCPDR] = sci_reg_invalid, | |
61a6976b PM |
196 | }, |
197 | ||
198 | /* | |
199 | * Common SCIFA definitions. | |
200 | */ | |
201 | [SCIx_SCIFA_REGTYPE] = { | |
202 | [SCSMR] = { 0x00, 16 }, | |
203 | [SCBRR] = { 0x04, 8 }, | |
204 | [SCSCR] = { 0x08, 16 }, | |
205 | [SCxTDR] = { 0x20, 8 }, | |
206 | [SCxSR] = { 0x14, 16 }, | |
207 | [SCxRDR] = { 0x24, 8 }, | |
208 | [SCFCR] = { 0x18, 16 }, | |
209 | [SCFDR] = { 0x1c, 16 }, | |
210 | [SCTFDR] = sci_reg_invalid, | |
211 | [SCRFDR] = sci_reg_invalid, | |
212 | [SCSPTR] = sci_reg_invalid, | |
213 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 214 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
215 | [SCPCR] = { 0x30, 16 }, |
216 | [SCPDR] = { 0x34, 16 }, | |
61a6976b PM |
217 | }, |
218 | ||
219 | /* | |
220 | * Common SCIFB definitions. | |
221 | */ | |
222 | [SCIx_SCIFB_REGTYPE] = { | |
223 | [SCSMR] = { 0x00, 16 }, | |
224 | [SCBRR] = { 0x04, 8 }, | |
225 | [SCSCR] = { 0x08, 16 }, | |
226 | [SCxTDR] = { 0x40, 8 }, | |
227 | [SCxSR] = { 0x14, 16 }, | |
228 | [SCxRDR] = { 0x60, 8 }, | |
229 | [SCFCR] = { 0x18, 16 }, | |
8c66d6d2 TY |
230 | [SCFDR] = sci_reg_invalid, |
231 | [SCTFDR] = { 0x38, 16 }, | |
232 | [SCRFDR] = { 0x3c, 16 }, | |
61a6976b PM |
233 | [SCSPTR] = sci_reg_invalid, |
234 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 235 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
236 | [SCPCR] = { 0x30, 16 }, |
237 | [SCPDR] = { 0x34, 16 }, | |
61a6976b PM |
238 | }, |
239 | ||
3af1f8a4 PE |
240 | /* |
241 | * Common SH-2(A) SCIF definitions for ports with FIFO data | |
242 | * count registers. | |
243 | */ | |
244 | [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { | |
245 | [SCSMR] = { 0x00, 16 }, | |
246 | [SCBRR] = { 0x04, 8 }, | |
247 | [SCSCR] = { 0x08, 16 }, | |
248 | [SCxTDR] = { 0x0c, 8 }, | |
249 | [SCxSR] = { 0x10, 16 }, | |
250 | [SCxRDR] = { 0x14, 8 }, | |
251 | [SCFCR] = { 0x18, 16 }, | |
252 | [SCFDR] = { 0x1c, 16 }, | |
253 | [SCTFDR] = sci_reg_invalid, | |
254 | [SCRFDR] = sci_reg_invalid, | |
255 | [SCSPTR] = { 0x20, 16 }, | |
256 | [SCLSR] = { 0x24, 16 }, | |
f303b364 | 257 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
258 | [SCPCR] = sci_reg_invalid, |
259 | [SCPDR] = sci_reg_invalid, | |
3af1f8a4 PE |
260 | }, |
261 | ||
61a6976b PM |
262 | /* |
263 | * Common SH-3 SCIF definitions. | |
264 | */ | |
265 | [SCIx_SH3_SCIF_REGTYPE] = { | |
266 | [SCSMR] = { 0x00, 8 }, | |
267 | [SCBRR] = { 0x02, 8 }, | |
268 | [SCSCR] = { 0x04, 8 }, | |
269 | [SCxTDR] = { 0x06, 8 }, | |
270 | [SCxSR] = { 0x08, 16 }, | |
271 | [SCxRDR] = { 0x0a, 8 }, | |
272 | [SCFCR] = { 0x0c, 8 }, | |
273 | [SCFDR] = { 0x0e, 16 }, | |
274 | [SCTFDR] = sci_reg_invalid, | |
275 | [SCRFDR] = sci_reg_invalid, | |
276 | [SCSPTR] = sci_reg_invalid, | |
277 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 278 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
279 | [SCPCR] = sci_reg_invalid, |
280 | [SCPDR] = sci_reg_invalid, | |
61a6976b PM |
281 | }, |
282 | ||
283 | /* | |
284 | * Common SH-4(A) SCIF(B) definitions. | |
285 | */ | |
286 | [SCIx_SH4_SCIF_REGTYPE] = { | |
287 | [SCSMR] = { 0x00, 16 }, | |
288 | [SCBRR] = { 0x04, 8 }, | |
289 | [SCSCR] = { 0x08, 16 }, | |
290 | [SCxTDR] = { 0x0c, 8 }, | |
291 | [SCxSR] = { 0x10, 16 }, | |
292 | [SCxRDR] = { 0x14, 8 }, | |
293 | [SCFCR] = { 0x18, 16 }, | |
294 | [SCFDR] = { 0x1c, 16 }, | |
295 | [SCTFDR] = sci_reg_invalid, | |
296 | [SCRFDR] = sci_reg_invalid, | |
297 | [SCSPTR] = { 0x20, 16 }, | |
298 | [SCLSR] = { 0x24, 16 }, | |
f303b364 | 299 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
300 | [SCPCR] = sci_reg_invalid, |
301 | [SCPDR] = sci_reg_invalid, | |
f303b364 UH |
302 | }, |
303 | ||
304 | /* | |
305 | * Common HSCIF definitions. | |
306 | */ | |
307 | [SCIx_HSCIF_REGTYPE] = { | |
308 | [SCSMR] = { 0x00, 16 }, | |
309 | [SCBRR] = { 0x04, 8 }, | |
310 | [SCSCR] = { 0x08, 16 }, | |
311 | [SCxTDR] = { 0x0c, 8 }, | |
312 | [SCxSR] = { 0x10, 16 }, | |
313 | [SCxRDR] = { 0x14, 8 }, | |
314 | [SCFCR] = { 0x18, 16 }, | |
315 | [SCFDR] = { 0x1c, 16 }, | |
316 | [SCTFDR] = sci_reg_invalid, | |
317 | [SCRFDR] = sci_reg_invalid, | |
318 | [SCSPTR] = { 0x20, 16 }, | |
319 | [SCLSR] = { 0x24, 16 }, | |
320 | [HSSRR] = { 0x40, 16 }, | |
c097abc3 GU |
321 | [SCPCR] = sci_reg_invalid, |
322 | [SCPDR] = sci_reg_invalid, | |
61a6976b PM |
323 | }, |
324 | ||
325 | /* | |
326 | * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR | |
327 | * register. | |
328 | */ | |
329 | [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { | |
330 | [SCSMR] = { 0x00, 16 }, | |
331 | [SCBRR] = { 0x04, 8 }, | |
332 | [SCSCR] = { 0x08, 16 }, | |
333 | [SCxTDR] = { 0x0c, 8 }, | |
334 | [SCxSR] = { 0x10, 16 }, | |
335 | [SCxRDR] = { 0x14, 8 }, | |
336 | [SCFCR] = { 0x18, 16 }, | |
337 | [SCFDR] = { 0x1c, 16 }, | |
338 | [SCTFDR] = sci_reg_invalid, | |
339 | [SCRFDR] = sci_reg_invalid, | |
340 | [SCSPTR] = sci_reg_invalid, | |
341 | [SCLSR] = { 0x24, 16 }, | |
f303b364 | 342 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
343 | [SCPCR] = sci_reg_invalid, |
344 | [SCPDR] = sci_reg_invalid, | |
61a6976b PM |
345 | }, |
346 | ||
347 | /* | |
348 | * Common SH-4(A) SCIF(B) definitions for ports with FIFO data | |
349 | * count registers. | |
350 | */ | |
351 | [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { | |
352 | [SCSMR] = { 0x00, 16 }, | |
353 | [SCBRR] = { 0x04, 8 }, | |
354 | [SCSCR] = { 0x08, 16 }, | |
355 | [SCxTDR] = { 0x0c, 8 }, | |
356 | [SCxSR] = { 0x10, 16 }, | |
357 | [SCxRDR] = { 0x14, 8 }, | |
358 | [SCFCR] = { 0x18, 16 }, | |
359 | [SCFDR] = { 0x1c, 16 }, | |
360 | [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ | |
361 | [SCRFDR] = { 0x20, 16 }, | |
362 | [SCSPTR] = { 0x24, 16 }, | |
363 | [SCLSR] = { 0x28, 16 }, | |
f303b364 | 364 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
365 | [SCPCR] = sci_reg_invalid, |
366 | [SCPDR] = sci_reg_invalid, | |
61a6976b PM |
367 | }, |
368 | ||
369 | /* | |
370 | * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR | |
371 | * registers. | |
372 | */ | |
373 | [SCIx_SH7705_SCIF_REGTYPE] = { | |
374 | [SCSMR] = { 0x00, 16 }, | |
375 | [SCBRR] = { 0x04, 8 }, | |
376 | [SCSCR] = { 0x08, 16 }, | |
377 | [SCxTDR] = { 0x20, 8 }, | |
378 | [SCxSR] = { 0x14, 16 }, | |
379 | [SCxRDR] = { 0x24, 8 }, | |
380 | [SCFCR] = { 0x18, 16 }, | |
381 | [SCFDR] = { 0x1c, 16 }, | |
382 | [SCTFDR] = sci_reg_invalid, | |
383 | [SCRFDR] = sci_reg_invalid, | |
384 | [SCSPTR] = sci_reg_invalid, | |
385 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 386 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
387 | [SCPCR] = sci_reg_invalid, |
388 | [SCPDR] = sci_reg_invalid, | |
61a6976b PM |
389 | }, |
390 | }; | |
391 | ||
72b294cf PM |
392 | #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) |
393 | ||
61a6976b PM |
394 | /* |
395 | * The "offset" here is rather misleading, in that it refers to an enum | |
396 | * value relative to the port mapping rather than the fixed offset | |
397 | * itself, which needs to be manually retrieved from the platform's | |
398 | * register map for the given port. | |
399 | */ | |
400 | static unsigned int sci_serial_in(struct uart_port *p, int offset) | |
401 | { | |
d3184e68 | 402 | const struct plat_sci_reg *reg = sci_getreg(p, offset); |
61a6976b PM |
403 | |
404 | if (reg->size == 8) | |
405 | return ioread8(p->membase + (reg->offset << p->regshift)); | |
406 | else if (reg->size == 16) | |
407 | return ioread16(p->membase + (reg->offset << p->regshift)); | |
408 | else | |
409 | WARN(1, "Invalid register access\n"); | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
414 | static void sci_serial_out(struct uart_port *p, int offset, int value) | |
415 | { | |
d3184e68 | 416 | const struct plat_sci_reg *reg = sci_getreg(p, offset); |
61a6976b PM |
417 | |
418 | if (reg->size == 8) | |
419 | iowrite8(value, p->membase + (reg->offset << p->regshift)); | |
420 | else if (reg->size == 16) | |
421 | iowrite16(value, p->membase + (reg->offset << p->regshift)); | |
422 | else | |
423 | WARN(1, "Invalid register access\n"); | |
424 | } | |
425 | ||
61a6976b PM |
426 | static int sci_probe_regmap(struct plat_sci_port *cfg) |
427 | { | |
428 | switch (cfg->type) { | |
429 | case PORT_SCI: | |
430 | cfg->regtype = SCIx_SCI_REGTYPE; | |
431 | break; | |
432 | case PORT_IRDA: | |
433 | cfg->regtype = SCIx_IRDA_REGTYPE; | |
434 | break; | |
435 | case PORT_SCIFA: | |
436 | cfg->regtype = SCIx_SCIFA_REGTYPE; | |
437 | break; | |
438 | case PORT_SCIFB: | |
439 | cfg->regtype = SCIx_SCIFB_REGTYPE; | |
440 | break; | |
441 | case PORT_SCIF: | |
442 | /* | |
443 | * The SH-4 is a bit of a misnomer here, although that's | |
444 | * where this particular port layout originated. This | |
445 | * configuration (or some slight variation thereof) | |
446 | * remains the dominant model for all SCIFs. | |
447 | */ | |
448 | cfg->regtype = SCIx_SH4_SCIF_REGTYPE; | |
449 | break; | |
f303b364 UH |
450 | case PORT_HSCIF: |
451 | cfg->regtype = SCIx_HSCIF_REGTYPE; | |
452 | break; | |
61a6976b | 453 | default: |
6c13d5d2 | 454 | pr_err("Can't probe register map for given port\n"); |
61a6976b PM |
455 | return -EINVAL; |
456 | } | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
23241d43 PM |
461 | static void sci_port_enable(struct sci_port *sci_port) |
462 | { | |
463 | if (!sci_port->port.dev) | |
464 | return; | |
465 | ||
466 | pm_runtime_get_sync(sci_port->port.dev); | |
467 | ||
b016b646 | 468 | clk_prepare_enable(sci_port->iclk); |
23241d43 | 469 | sci_port->port.uartclk = clk_get_rate(sci_port->iclk); |
b016b646 | 470 | clk_prepare_enable(sci_port->fclk); |
23241d43 PM |
471 | } |
472 | ||
473 | static void sci_port_disable(struct sci_port *sci_port) | |
474 | { | |
475 | if (!sci_port->port.dev) | |
476 | return; | |
477 | ||
caec7038 LP |
478 | /* Cancel the break timer to ensure that the timer handler will not try |
479 | * to access the hardware with clocks and power disabled. Reset the | |
480 | * break flag to make the break debouncing state machine ready for the | |
481 | * next break. | |
482 | */ | |
483 | del_timer_sync(&sci_port->break_timer); | |
484 | sci_port->break_flag = 0; | |
485 | ||
b016b646 LP |
486 | clk_disable_unprepare(sci_port->fclk); |
487 | clk_disable_unprepare(sci_port->iclk); | |
23241d43 PM |
488 | |
489 | pm_runtime_put_sync(sci_port->port.dev); | |
490 | } | |
491 | ||
a1b5b43f GU |
492 | static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) |
493 | { | |
494 | if (port->type == PORT_SCI) { | |
495 | /* Just store the mask */ | |
496 | serial_port_out(port, SCxSR, mask); | |
497 | } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) { | |
498 | /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ | |
499 | /* Only clear the status bits we want to clear */ | |
500 | serial_port_out(port, SCxSR, | |
501 | serial_port_in(port, SCxSR) & mask); | |
502 | } else { | |
503 | /* Store the mask, clear parity/framing errors */ | |
504 | serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); | |
505 | } | |
506 | } | |
507 | ||
07d2a1a1 | 508 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
1f6fd5c9 PM |
509 | |
510 | #ifdef CONFIG_CONSOLE_POLL | |
07d2a1a1 | 511 | static int sci_poll_get_char(struct uart_port *port) |
1da177e4 | 512 | { |
1da177e4 LT |
513 | unsigned short status; |
514 | int c; | |
515 | ||
e108b2ca | 516 | do { |
b12bb29f | 517 | status = serial_port_in(port, SCxSR); |
1da177e4 | 518 | if (status & SCxSR_ERRORS(port)) { |
a1b5b43f | 519 | sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); |
1da177e4 LT |
520 | continue; |
521 | } | |
3f255eb3 JW |
522 | break; |
523 | } while (1); | |
524 | ||
525 | if (!(status & SCxSR_RDxF(port))) | |
526 | return NO_POLL_CHAR; | |
07d2a1a1 | 527 | |
b12bb29f | 528 | c = serial_port_in(port, SCxRDR); |
07d2a1a1 | 529 | |
e7c98dc7 | 530 | /* Dummy read */ |
b12bb29f | 531 | serial_port_in(port, SCxSR); |
a1b5b43f | 532 | sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); |
1da177e4 LT |
533 | |
534 | return c; | |
535 | } | |
1f6fd5c9 | 536 | #endif |
1da177e4 | 537 | |
07d2a1a1 | 538 | static void sci_poll_put_char(struct uart_port *port, unsigned char c) |
1da177e4 | 539 | { |
1da177e4 LT |
540 | unsigned short status; |
541 | ||
1da177e4 | 542 | do { |
b12bb29f | 543 | status = serial_port_in(port, SCxSR); |
1da177e4 LT |
544 | } while (!(status & SCxSR_TDxE(port))); |
545 | ||
b12bb29f | 546 | serial_port_out(port, SCxTDR, c); |
a1b5b43f | 547 | sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); |
1da177e4 | 548 | } |
07d2a1a1 | 549 | #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ |
1da177e4 | 550 | |
61a6976b | 551 | static void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 | 552 | { |
61a6976b | 553 | struct sci_port *s = to_sci_port(port); |
d3184e68 | 554 | const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; |
1da177e4 | 555 | |
61a6976b PM |
556 | /* |
557 | * Use port-specific handler if provided. | |
558 | */ | |
559 | if (s->cfg->ops && s->cfg->ops->init_pins) { | |
560 | s->cfg->ops->init_pins(port, cflag); | |
561 | return; | |
1da177e4 | 562 | } |
41504c39 | 563 | |
61a6976b PM |
564 | /* |
565 | * For the generic path SCSPTR is necessary. Bail out if that's | |
566 | * unavailable, too. | |
567 | */ | |
568 | if (!reg->size) | |
569 | return; | |
41504c39 | 570 | |
faf02f8f PM |
571 | if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) && |
572 | ((!(cflag & CRTSCTS)))) { | |
573 | unsigned short status; | |
574 | ||
b12bb29f | 575 | status = serial_port_in(port, SCSPTR); |
faf02f8f PM |
576 | status &= ~SCSPTR_CTSIO; |
577 | status |= SCSPTR_RTSIO; | |
b12bb29f | 578 | serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */ |
faf02f8f | 579 | } |
d5701647 | 580 | } |
e108b2ca | 581 | |
72b294cf | 582 | static int sci_txfill(struct uart_port *port) |
e108b2ca | 583 | { |
d3184e68 | 584 | const struct plat_sci_reg *reg; |
e108b2ca | 585 | |
72b294cf PM |
586 | reg = sci_getreg(port, SCTFDR); |
587 | if (reg->size) | |
63f7ad11 | 588 | return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1); |
c63847a3 | 589 | |
72b294cf PM |
590 | reg = sci_getreg(port, SCFDR); |
591 | if (reg->size) | |
b12bb29f | 592 | return serial_port_in(port, SCFDR) >> 8; |
d1d4b10c | 593 | |
b12bb29f | 594 | return !(serial_port_in(port, SCxSR) & SCI_TDRE); |
e108b2ca PM |
595 | } |
596 | ||
73a19e4c GL |
597 | static int sci_txroom(struct uart_port *port) |
598 | { | |
72b294cf | 599 | return port->fifosize - sci_txfill(port); |
73a19e4c GL |
600 | } |
601 | ||
602 | static int sci_rxfill(struct uart_port *port) | |
e108b2ca | 603 | { |
d3184e68 | 604 | const struct plat_sci_reg *reg; |
72b294cf PM |
605 | |
606 | reg = sci_getreg(port, SCRFDR); | |
607 | if (reg->size) | |
63f7ad11 | 608 | return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1); |
72b294cf PM |
609 | |
610 | reg = sci_getreg(port, SCFDR); | |
611 | if (reg->size) | |
b12bb29f | 612 | return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1); |
72b294cf | 613 | |
b12bb29f | 614 | return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; |
e108b2ca PM |
615 | } |
616 | ||
514820eb PM |
617 | /* |
618 | * SCI helper for checking the state of the muxed port/RXD pins. | |
619 | */ | |
620 | static inline int sci_rxd_in(struct uart_port *port) | |
621 | { | |
622 | struct sci_port *s = to_sci_port(port); | |
623 | ||
624 | if (s->cfg->port_reg <= 0) | |
625 | return 1; | |
626 | ||
0dd4d5cb | 627 | /* Cast for ARM damage */ |
e2afca69 | 628 | return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg); |
514820eb PM |
629 | } |
630 | ||
1da177e4 LT |
631 | /* ********************************************************************** * |
632 | * the interrupt related routines * | |
633 | * ********************************************************************** */ | |
634 | ||
635 | static void sci_transmit_chars(struct uart_port *port) | |
636 | { | |
ebd2c8f6 | 637 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 | 638 | unsigned int stopped = uart_tx_stopped(port); |
1da177e4 LT |
639 | unsigned short status; |
640 | unsigned short ctrl; | |
e108b2ca | 641 | int count; |
1da177e4 | 642 | |
b12bb29f | 643 | status = serial_port_in(port, SCxSR); |
1da177e4 | 644 | if (!(status & SCxSR_TDxE(port))) { |
b12bb29f | 645 | ctrl = serial_port_in(port, SCSCR); |
e7c98dc7 | 646 | if (uart_circ_empty(xmit)) |
8e698614 | 647 | ctrl &= ~SCSCR_TIE; |
e7c98dc7 | 648 | else |
8e698614 | 649 | ctrl |= SCSCR_TIE; |
b12bb29f | 650 | serial_port_out(port, SCSCR, ctrl); |
1da177e4 LT |
651 | return; |
652 | } | |
653 | ||
72b294cf | 654 | count = sci_txroom(port); |
1da177e4 LT |
655 | |
656 | do { | |
657 | unsigned char c; | |
658 | ||
659 | if (port->x_char) { | |
660 | c = port->x_char; | |
661 | port->x_char = 0; | |
662 | } else if (!uart_circ_empty(xmit) && !stopped) { | |
663 | c = xmit->buf[xmit->tail]; | |
664 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
665 | } else { | |
666 | break; | |
667 | } | |
668 | ||
b12bb29f | 669 | serial_port_out(port, SCxTDR, c); |
1da177e4 LT |
670 | |
671 | port->icount.tx++; | |
672 | } while (--count > 0); | |
673 | ||
a1b5b43f | 674 | sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); |
1da177e4 LT |
675 | |
676 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
677 | uart_write_wakeup(port); | |
678 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 679 | sci_stop_tx(port); |
1da177e4 | 680 | } else { |
b12bb29f | 681 | ctrl = serial_port_in(port, SCSCR); |
1da177e4 | 682 | |
1a22f08d | 683 | if (port->type != PORT_SCI) { |
b12bb29f | 684 | serial_port_in(port, SCxSR); /* Dummy read */ |
a1b5b43f | 685 | sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); |
1da177e4 | 686 | } |
1da177e4 | 687 | |
8e698614 | 688 | ctrl |= SCSCR_TIE; |
b12bb29f | 689 | serial_port_out(port, SCSCR, ctrl); |
1da177e4 LT |
690 | } |
691 | } | |
692 | ||
693 | /* On SH3, SCIF may read end-of-break as a space->mark char */ | |
e7c98dc7 | 694 | #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) |
1da177e4 | 695 | |
94c8b6db | 696 | static void sci_receive_chars(struct uart_port *port) |
1da177e4 | 697 | { |
e7c98dc7 | 698 | struct sci_port *sci_port = to_sci_port(port); |
227434f8 | 699 | struct tty_port *tport = &port->state->port; |
1da177e4 LT |
700 | int i, count, copied = 0; |
701 | unsigned short status; | |
33f0f88f | 702 | unsigned char flag; |
1da177e4 | 703 | |
b12bb29f | 704 | status = serial_port_in(port, SCxSR); |
1da177e4 LT |
705 | if (!(status & SCxSR_RDxF(port))) |
706 | return; | |
707 | ||
708 | while (1) { | |
1da177e4 | 709 | /* Don't copy more bytes than there is room for in the buffer */ |
227434f8 | 710 | count = tty_buffer_request_room(tport, sci_rxfill(port)); |
1da177e4 LT |
711 | |
712 | /* If for any reason we can't copy more data, we're done! */ | |
713 | if (count == 0) | |
714 | break; | |
715 | ||
716 | if (port->type == PORT_SCI) { | |
b12bb29f | 717 | char c = serial_port_in(port, SCxRDR); |
e7c98dc7 MT |
718 | if (uart_handle_sysrq_char(port, c) || |
719 | sci_port->break_flag) | |
1da177e4 | 720 | count = 0; |
e7c98dc7 | 721 | else |
92a19f9c | 722 | tty_insert_flip_char(tport, c, TTY_NORMAL); |
1da177e4 | 723 | } else { |
e7c98dc7 | 724 | for (i = 0; i < count; i++) { |
b12bb29f | 725 | char c = serial_port_in(port, SCxRDR); |
d97fbbed | 726 | |
b12bb29f | 727 | status = serial_port_in(port, SCxSR); |
1da177e4 LT |
728 | #if defined(CONFIG_CPU_SH3) |
729 | /* Skip "chars" during break */ | |
e108b2ca | 730 | if (sci_port->break_flag) { |
1da177e4 LT |
731 | if ((c == 0) && |
732 | (status & SCxSR_FER(port))) { | |
733 | count--; i--; | |
734 | continue; | |
735 | } | |
e108b2ca | 736 | |
1da177e4 | 737 | /* Nonzero => end-of-break */ |
762c69e3 | 738 | dev_dbg(port->dev, "debounce<%02x>\n", c); |
e108b2ca PM |
739 | sci_port->break_flag = 0; |
740 | ||
1da177e4 LT |
741 | if (STEPFN(c)) { |
742 | count--; i--; | |
743 | continue; | |
744 | } | |
745 | } | |
746 | #endif /* CONFIG_CPU_SH3 */ | |
7d12e780 | 747 | if (uart_handle_sysrq_char(port, c)) { |
1da177e4 LT |
748 | count--; i--; |
749 | continue; | |
750 | } | |
751 | ||
752 | /* Store data and status */ | |
73a19e4c | 753 | if (status & SCxSR_FER(port)) { |
33f0f88f | 754 | flag = TTY_FRAME; |
d97fbbed | 755 | port->icount.frame++; |
762c69e3 | 756 | dev_notice(port->dev, "frame error\n"); |
73a19e4c | 757 | } else if (status & SCxSR_PER(port)) { |
33f0f88f | 758 | flag = TTY_PARITY; |
d97fbbed | 759 | port->icount.parity++; |
762c69e3 | 760 | dev_notice(port->dev, "parity error\n"); |
33f0f88f AC |
761 | } else |
762 | flag = TTY_NORMAL; | |
762c69e3 | 763 | |
92a19f9c | 764 | tty_insert_flip_char(tport, c, flag); |
1da177e4 LT |
765 | } |
766 | } | |
767 | ||
b12bb29f | 768 | serial_port_in(port, SCxSR); /* dummy read */ |
a1b5b43f | 769 | sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); |
1da177e4 | 770 | |
1da177e4 LT |
771 | copied += count; |
772 | port->icount.rx += count; | |
773 | } | |
774 | ||
775 | if (copied) { | |
776 | /* Tell the rest of the system the news. New characters! */ | |
2e124b4a | 777 | tty_flip_buffer_push(tport); |
1da177e4 | 778 | } else { |
b12bb29f | 779 | serial_port_in(port, SCxSR); /* dummy read */ |
a1b5b43f | 780 | sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); |
1da177e4 LT |
781 | } |
782 | } | |
783 | ||
784 | #define SCI_BREAK_JIFFIES (HZ/20) | |
94c8b6db PM |
785 | |
786 | /* | |
787 | * The sci generates interrupts during the break, | |
1da177e4 LT |
788 | * 1 per millisecond or so during the break period, for 9600 baud. |
789 | * So dont bother disabling interrupts. | |
790 | * But dont want more than 1 break event. | |
791 | * Use a kernel timer to periodically poll the rx line until | |
792 | * the break is finished. | |
793 | */ | |
94c8b6db | 794 | static inline void sci_schedule_break_timer(struct sci_port *port) |
1da177e4 | 795 | { |
bc9b3f5c | 796 | mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); |
1da177e4 | 797 | } |
94c8b6db | 798 | |
1da177e4 LT |
799 | /* Ensure that two consecutive samples find the break over. */ |
800 | static void sci_break_timer(unsigned long data) | |
801 | { | |
e108b2ca PM |
802 | struct sci_port *port = (struct sci_port *)data; |
803 | ||
804 | if (sci_rxd_in(&port->port) == 0) { | |
1da177e4 | 805 | port->break_flag = 1; |
e108b2ca PM |
806 | sci_schedule_break_timer(port); |
807 | } else if (port->break_flag == 1) { | |
1da177e4 LT |
808 | /* break is over. */ |
809 | port->break_flag = 2; | |
e108b2ca PM |
810 | sci_schedule_break_timer(port); |
811 | } else | |
812 | port->break_flag = 0; | |
1da177e4 LT |
813 | } |
814 | ||
94c8b6db | 815 | static int sci_handle_errors(struct uart_port *port) |
1da177e4 LT |
816 | { |
817 | int copied = 0; | |
b12bb29f | 818 | unsigned short status = serial_port_in(port, SCxSR); |
92a19f9c | 819 | struct tty_port *tport = &port->state->port; |
debf9507 | 820 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 821 | |
3ae988d9 | 822 | /* Handle overruns */ |
75c249fd | 823 | if (status & s->overrun_mask) { |
3ae988d9 | 824 | port->icount.overrun++; |
d97fbbed | 825 | |
3ae988d9 LP |
826 | /* overrun error */ |
827 | if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) | |
828 | copied++; | |
762c69e3 | 829 | |
9b971cd2 | 830 | dev_notice(port->dev, "overrun error\n"); |
1da177e4 LT |
831 | } |
832 | ||
e108b2ca | 833 | if (status & SCxSR_FER(port)) { |
1da177e4 LT |
834 | if (sci_rxd_in(port) == 0) { |
835 | /* Notify of BREAK */ | |
e7c98dc7 | 836 | struct sci_port *sci_port = to_sci_port(port); |
e108b2ca PM |
837 | |
838 | if (!sci_port->break_flag) { | |
d97fbbed PM |
839 | port->icount.brk++; |
840 | ||
e108b2ca PM |
841 | sci_port->break_flag = 1; |
842 | sci_schedule_break_timer(sci_port); | |
843 | ||
1da177e4 | 844 | /* Do sysrq handling. */ |
e108b2ca | 845 | if (uart_handle_break(port)) |
1da177e4 | 846 | return 0; |
762c69e3 PM |
847 | |
848 | dev_dbg(port->dev, "BREAK detected\n"); | |
849 | ||
92a19f9c | 850 | if (tty_insert_flip_char(tport, 0, TTY_BREAK)) |
e7c98dc7 MT |
851 | copied++; |
852 | } | |
853 | ||
e108b2ca | 854 | } else { |
1da177e4 | 855 | /* frame error */ |
d97fbbed PM |
856 | port->icount.frame++; |
857 | ||
92a19f9c | 858 | if (tty_insert_flip_char(tport, 0, TTY_FRAME)) |
33f0f88f | 859 | copied++; |
762c69e3 PM |
860 | |
861 | dev_notice(port->dev, "frame error\n"); | |
1da177e4 LT |
862 | } |
863 | } | |
864 | ||
e108b2ca | 865 | if (status & SCxSR_PER(port)) { |
1da177e4 | 866 | /* parity error */ |
d97fbbed PM |
867 | port->icount.parity++; |
868 | ||
92a19f9c | 869 | if (tty_insert_flip_char(tport, 0, TTY_PARITY)) |
e108b2ca | 870 | copied++; |
762c69e3 | 871 | |
9b971cd2 | 872 | dev_notice(port->dev, "parity error\n"); |
1da177e4 LT |
873 | } |
874 | ||
33f0f88f | 875 | if (copied) |
2e124b4a | 876 | tty_flip_buffer_push(tport); |
1da177e4 LT |
877 | |
878 | return copied; | |
879 | } | |
880 | ||
94c8b6db | 881 | static int sci_handle_fifo_overrun(struct uart_port *port) |
d830fa45 | 882 | { |
92a19f9c | 883 | struct tty_port *tport = &port->state->port; |
debf9507 | 884 | struct sci_port *s = to_sci_port(port); |
d3184e68 | 885 | const struct plat_sci_reg *reg; |
2e0842a1 | 886 | int copied = 0; |
75c249fd | 887 | u16 status; |
d830fa45 | 888 | |
2e0842a1 | 889 | reg = sci_getreg(port, s->overrun_reg); |
4b8c59a3 | 890 | if (!reg->size) |
d830fa45 PM |
891 | return 0; |
892 | ||
2e0842a1 | 893 | status = serial_port_in(port, s->overrun_reg); |
75c249fd GU |
894 | if (status & s->overrun_mask) { |
895 | status &= ~s->overrun_mask; | |
2e0842a1 | 896 | serial_port_out(port, s->overrun_reg, status); |
d830fa45 | 897 | |
d97fbbed PM |
898 | port->icount.overrun++; |
899 | ||
92a19f9c | 900 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); |
2e124b4a | 901 | tty_flip_buffer_push(tport); |
d830fa45 | 902 | |
51b31f1c | 903 | dev_dbg(port->dev, "overrun error\n"); |
d830fa45 PM |
904 | copied++; |
905 | } | |
906 | ||
907 | return copied; | |
908 | } | |
909 | ||
94c8b6db | 910 | static int sci_handle_breaks(struct uart_port *port) |
1da177e4 LT |
911 | { |
912 | int copied = 0; | |
b12bb29f | 913 | unsigned short status = serial_port_in(port, SCxSR); |
92a19f9c | 914 | struct tty_port *tport = &port->state->port; |
a5660ada | 915 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 916 | |
0b3d4ef6 PM |
917 | if (uart_handle_break(port)) |
918 | return 0; | |
919 | ||
b7a76e4b | 920 | if (!s->break_flag && status & SCxSR_BRK(port)) { |
1da177e4 LT |
921 | #if defined(CONFIG_CPU_SH3) |
922 | /* Debounce break */ | |
923 | s->break_flag = 1; | |
924 | #endif | |
d97fbbed PM |
925 | |
926 | port->icount.brk++; | |
927 | ||
1da177e4 | 928 | /* Notify of BREAK */ |
92a19f9c | 929 | if (tty_insert_flip_char(tport, 0, TTY_BREAK)) |
33f0f88f | 930 | copied++; |
762c69e3 PM |
931 | |
932 | dev_dbg(port->dev, "BREAK detected\n"); | |
1da177e4 LT |
933 | } |
934 | ||
33f0f88f | 935 | if (copied) |
2e124b4a | 936 | tty_flip_buffer_push(tport); |
e108b2ca | 937 | |
d830fa45 PM |
938 | copied += sci_handle_fifo_overrun(port); |
939 | ||
1da177e4 LT |
940 | return copied; |
941 | } | |
942 | ||
73a19e4c | 943 | static irqreturn_t sci_rx_interrupt(int irq, void *ptr) |
1da177e4 | 944 | { |
73a19e4c GL |
945 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
946 | struct uart_port *port = ptr; | |
947 | struct sci_port *s = to_sci_port(port); | |
948 | ||
949 | if (s->chan_rx) { | |
b12bb29f PM |
950 | u16 scr = serial_port_in(port, SCSCR); |
951 | u16 ssr = serial_port_in(port, SCxSR); | |
73a19e4c GL |
952 | |
953 | /* Disable future Rx interrupts */ | |
d1d4b10c | 954 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 | 955 | disable_irq_nosync(irq); |
26de4f1b | 956 | scr |= SCSCR_RDRQE; |
3089f381 | 957 | } else { |
f43dc23d | 958 | scr &= ~SCSCR_RIE; |
3089f381 | 959 | } |
b12bb29f | 960 | serial_port_out(port, SCSCR, scr); |
73a19e4c | 961 | /* Clear current interrupt */ |
54af5001 GU |
962 | serial_port_out(port, SCxSR, |
963 | ssr & ~(SCIF_DR | SCxSR_RDxF(port))); | |
3089f381 GL |
964 | dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", |
965 | jiffies, s->rx_timeout); | |
966 | mod_timer(&s->rx_timer, jiffies + s->rx_timeout); | |
73a19e4c GL |
967 | |
968 | return IRQ_HANDLED; | |
969 | } | |
970 | #endif | |
971 | ||
1da177e4 LT |
972 | /* I think sci_receive_chars has to be called irrespective |
973 | * of whether the I_IXOFF is set, otherwise, how is the interrupt | |
974 | * to be disabled? | |
975 | */ | |
73a19e4c | 976 | sci_receive_chars(ptr); |
1da177e4 LT |
977 | |
978 | return IRQ_HANDLED; | |
979 | } | |
980 | ||
7d12e780 | 981 | static irqreturn_t sci_tx_interrupt(int irq, void *ptr) |
1da177e4 LT |
982 | { |
983 | struct uart_port *port = ptr; | |
fd78a76a | 984 | unsigned long flags; |
1da177e4 | 985 | |
fd78a76a | 986 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 | 987 | sci_transmit_chars(port); |
fd78a76a | 988 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
989 | |
990 | return IRQ_HANDLED; | |
991 | } | |
992 | ||
7d12e780 | 993 | static irqreturn_t sci_er_interrupt(int irq, void *ptr) |
1da177e4 LT |
994 | { |
995 | struct uart_port *port = ptr; | |
996 | ||
997 | /* Handle errors */ | |
998 | if (port->type == PORT_SCI) { | |
999 | if (sci_handle_errors(port)) { | |
1000 | /* discard character in rx buffer */ | |
b12bb29f | 1001 | serial_port_in(port, SCxSR); |
a1b5b43f | 1002 | sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); |
1da177e4 LT |
1003 | } |
1004 | } else { | |
d830fa45 | 1005 | sci_handle_fifo_overrun(port); |
7d12e780 | 1006 | sci_rx_interrupt(irq, ptr); |
1da177e4 LT |
1007 | } |
1008 | ||
a1b5b43f | 1009 | sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); |
1da177e4 LT |
1010 | |
1011 | /* Kick the transmission */ | |
7d12e780 | 1012 | sci_tx_interrupt(irq, ptr); |
1da177e4 LT |
1013 | |
1014 | return IRQ_HANDLED; | |
1015 | } | |
1016 | ||
7d12e780 | 1017 | static irqreturn_t sci_br_interrupt(int irq, void *ptr) |
1da177e4 LT |
1018 | { |
1019 | struct uart_port *port = ptr; | |
1020 | ||
1021 | /* Handle BREAKs */ | |
1022 | sci_handle_breaks(port); | |
a1b5b43f | 1023 | sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); |
1da177e4 LT |
1024 | |
1025 | return IRQ_HANDLED; | |
1026 | } | |
1027 | ||
f43dc23d PM |
1028 | static inline unsigned long port_rx_irq_mask(struct uart_port *port) |
1029 | { | |
1030 | /* | |
1031 | * Not all ports (such as SCIFA) will support REIE. Rather than | |
1032 | * special-casing the port type, we check the port initialization | |
1033 | * IRQ enable mask to see whether the IRQ is desired at all. If | |
1034 | * it's unset, it's logically inferred that there's no point in | |
1035 | * testing for it. | |
1036 | */ | |
ce6738b6 | 1037 | return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); |
f43dc23d PM |
1038 | } |
1039 | ||
7d12e780 | 1040 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
1da177e4 | 1041 | { |
cb772fe7 | 1042 | unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; |
a8884e34 | 1043 | struct uart_port *port = ptr; |
73a19e4c | 1044 | struct sci_port *s = to_sci_port(port); |
a8884e34 | 1045 | irqreturn_t ret = IRQ_NONE; |
1da177e4 | 1046 | |
b12bb29f PM |
1047 | ssr_status = serial_port_in(port, SCxSR); |
1048 | scr_status = serial_port_in(port, SCSCR); | |
2e0842a1 | 1049 | if (s->overrun_reg == SCxSR) |
cb772fe7 | 1050 | orer_status = ssr_status; |
2e0842a1 GU |
1051 | else { |
1052 | if (sci_getreg(port, s->overrun_reg)->size) | |
1053 | orer_status = serial_port_in(port, s->overrun_reg); | |
cb772fe7 NI |
1054 | } |
1055 | ||
f43dc23d | 1056 | err_enabled = scr_status & port_rx_irq_mask(port); |
1da177e4 LT |
1057 | |
1058 | /* Tx Interrupt */ | |
f43dc23d | 1059 | if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && |
73a19e4c | 1060 | !s->chan_tx) |
a8884e34 | 1061 | ret = sci_tx_interrupt(irq, ptr); |
f43dc23d | 1062 | |
73a19e4c GL |
1063 | /* |
1064 | * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / | |
1065 | * DR flags | |
1066 | */ | |
1067 | if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && | |
e0a12a27 | 1068 | (scr_status & SCSCR_RIE)) |
a8884e34 | 1069 | ret = sci_rx_interrupt(irq, ptr); |
f43dc23d | 1070 | |
1da177e4 | 1071 | /* Error Interrupt */ |
dd4da3a5 | 1072 | if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) |
a8884e34 | 1073 | ret = sci_er_interrupt(irq, ptr); |
f43dc23d | 1074 | |
1da177e4 | 1075 | /* Break Interrupt */ |
dd4da3a5 | 1076 | if ((ssr_status & SCxSR_BRK(port)) && err_enabled) |
a8884e34 | 1077 | ret = sci_br_interrupt(irq, ptr); |
1da177e4 | 1078 | |
8b6ff84c | 1079 | /* Overrun Interrupt */ |
90803072 | 1080 | if (orer_status & s->overrun_mask) { |
cb772fe7 | 1081 | sci_handle_fifo_overrun(port); |
90803072 YS |
1082 | ret = IRQ_HANDLED; |
1083 | } | |
8b6ff84c | 1084 | |
a8884e34 | 1085 | return ret; |
1da177e4 LT |
1086 | } |
1087 | ||
1da177e4 | 1088 | /* |
25985edc | 1089 | * Here we define a transition notifier so that we can update all of our |
1da177e4 LT |
1090 | * ports' baud rate when the peripheral clock changes. |
1091 | */ | |
e108b2ca PM |
1092 | static int sci_notifier(struct notifier_block *self, |
1093 | unsigned long phase, void *p) | |
1da177e4 | 1094 | { |
e552de24 MD |
1095 | struct sci_port *sci_port; |
1096 | unsigned long flags; | |
1da177e4 | 1097 | |
d535a230 PM |
1098 | sci_port = container_of(self, struct sci_port, freq_transition); |
1099 | ||
0b443ead | 1100 | if (phase == CPUFREQ_POSTCHANGE) { |
d535a230 | 1101 | struct uart_port *port = &sci_port->port; |
073e84c9 | 1102 | |
d535a230 PM |
1103 | spin_lock_irqsave(&port->lock, flags); |
1104 | port->uartclk = clk_get_rate(sci_port->iclk); | |
1105 | spin_unlock_irqrestore(&port->lock, flags); | |
e552de24 | 1106 | } |
1da177e4 | 1107 | |
1da177e4 LT |
1108 | return NOTIFY_OK; |
1109 | } | |
501b825d | 1110 | |
d56a91e8 | 1111 | static const struct sci_irq_desc { |
9174fc8f PM |
1112 | const char *desc; |
1113 | irq_handler_t handler; | |
1114 | } sci_irq_desc[] = { | |
1115 | /* | |
1116 | * Split out handlers, the default case. | |
1117 | */ | |
1118 | [SCIx_ERI_IRQ] = { | |
1119 | .desc = "rx err", | |
1120 | .handler = sci_er_interrupt, | |
1121 | }, | |
1122 | ||
1123 | [SCIx_RXI_IRQ] = { | |
1124 | .desc = "rx full", | |
1125 | .handler = sci_rx_interrupt, | |
1126 | }, | |
1127 | ||
1128 | [SCIx_TXI_IRQ] = { | |
1129 | .desc = "tx empty", | |
1130 | .handler = sci_tx_interrupt, | |
1131 | }, | |
1132 | ||
1133 | [SCIx_BRI_IRQ] = { | |
1134 | .desc = "break", | |
1135 | .handler = sci_br_interrupt, | |
1136 | }, | |
1137 | ||
1138 | /* | |
1139 | * Special muxed handler. | |
1140 | */ | |
1141 | [SCIx_MUX_IRQ] = { | |
1142 | .desc = "mux", | |
1143 | .handler = sci_mpxed_interrupt, | |
1144 | }, | |
1145 | }; | |
1146 | ||
1da177e4 LT |
1147 | static int sci_request_irq(struct sci_port *port) |
1148 | { | |
9174fc8f PM |
1149 | struct uart_port *up = &port->port; |
1150 | int i, j, ret = 0; | |
1151 | ||
1152 | for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { | |
d56a91e8 | 1153 | const struct sci_irq_desc *desc; |
1fcc91a6 | 1154 | int irq; |
9174fc8f PM |
1155 | |
1156 | if (SCIx_IRQ_IS_MUXED(port)) { | |
1157 | i = SCIx_MUX_IRQ; | |
1158 | irq = up->irq; | |
0e8963de | 1159 | } else { |
1fcc91a6 | 1160 | irq = port->irqs[i]; |
9174fc8f | 1161 | |
0e8963de PM |
1162 | /* |
1163 | * Certain port types won't support all of the | |
1164 | * available interrupt sources. | |
1165 | */ | |
1fcc91a6 | 1166 | if (unlikely(irq < 0)) |
0e8963de PM |
1167 | continue; |
1168 | } | |
1169 | ||
9174fc8f PM |
1170 | desc = sci_irq_desc + i; |
1171 | port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", | |
1172 | dev_name(up->dev), desc->desc); | |
4205463c | 1173 | if (!port->irqstr[j]) |
9174fc8f | 1174 | goto out_nomem; |
9174fc8f PM |
1175 | |
1176 | ret = request_irq(irq, desc->handler, up->irqflags, | |
1177 | port->irqstr[j], port); | |
1178 | if (unlikely(ret)) { | |
1179 | dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); | |
1180 | goto out_noirq; | |
1da177e4 LT |
1181 | } |
1182 | } | |
1183 | ||
1184 | return 0; | |
9174fc8f PM |
1185 | |
1186 | out_noirq: | |
1187 | while (--i >= 0) | |
1fcc91a6 | 1188 | free_irq(port->irqs[i], port); |
9174fc8f PM |
1189 | |
1190 | out_nomem: | |
1191 | while (--j >= 0) | |
1192 | kfree(port->irqstr[j]); | |
1193 | ||
1194 | return ret; | |
1da177e4 LT |
1195 | } |
1196 | ||
1197 | static void sci_free_irq(struct sci_port *port) | |
1198 | { | |
1199 | int i; | |
1200 | ||
9174fc8f PM |
1201 | /* |
1202 | * Intentionally in reverse order so we iterate over the muxed | |
1203 | * IRQ first. | |
1204 | */ | |
1205 | for (i = 0; i < SCIx_NR_IRQS; i++) { | |
1fcc91a6 | 1206 | int irq = port->irqs[i]; |
0e8963de PM |
1207 | |
1208 | /* | |
1209 | * Certain port types won't support all of the available | |
1210 | * interrupt sources. | |
1211 | */ | |
1fcc91a6 | 1212 | if (unlikely(irq < 0)) |
0e8963de PM |
1213 | continue; |
1214 | ||
1fcc91a6 | 1215 | free_irq(port->irqs[i], port); |
9174fc8f | 1216 | kfree(port->irqstr[i]); |
1da177e4 | 1217 | |
9174fc8f PM |
1218 | if (SCIx_IRQ_IS_MUXED(port)) { |
1219 | /* If there's only one IRQ, we're done. */ | |
1220 | return; | |
1da177e4 LT |
1221 | } |
1222 | } | |
1223 | } | |
1224 | ||
1225 | static unsigned int sci_tx_empty(struct uart_port *port) | |
1226 | { | |
b12bb29f | 1227 | unsigned short status = serial_port_in(port, SCxSR); |
72b294cf | 1228 | unsigned short in_tx_fifo = sci_txfill(port); |
73a19e4c GL |
1229 | |
1230 | return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; | |
1da177e4 LT |
1231 | } |
1232 | ||
cdf7c42f PM |
1233 | /* |
1234 | * Modem control is a bit of a mixed bag for SCI(F) ports. Generally | |
1235 | * CTS/RTS is supported in hardware by at least one port and controlled | |
1236 | * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently | |
1237 | * handled via the ->init_pins() op, which is a bit of a one-way street, | |
1238 | * lacking any ability to defer pin control -- this will later be | |
1239 | * converted over to the GPIO framework). | |
dc7e3ef7 PM |
1240 | * |
1241 | * Other modes (such as loopback) are supported generically on certain | |
1242 | * port types, but not others. For these it's sufficient to test for the | |
1243 | * existence of the support register and simply ignore the port type. | |
cdf7c42f | 1244 | */ |
1da177e4 LT |
1245 | static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1246 | { | |
dc7e3ef7 | 1247 | if (mctrl & TIOCM_LOOP) { |
d3184e68 | 1248 | const struct plat_sci_reg *reg; |
dc7e3ef7 PM |
1249 | |
1250 | /* | |
1251 | * Standard loopback mode for SCFCR ports. | |
1252 | */ | |
1253 | reg = sci_getreg(port, SCFCR); | |
1254 | if (reg->size) | |
26de4f1b GU |
1255 | serial_port_out(port, SCFCR, |
1256 | serial_port_in(port, SCFCR) | | |
1257 | SCFCR_LOOP); | |
dc7e3ef7 | 1258 | } |
1da177e4 LT |
1259 | } |
1260 | ||
1261 | static unsigned int sci_get_mctrl(struct uart_port *port) | |
1262 | { | |
cdf7c42f PM |
1263 | /* |
1264 | * CTS/RTS is handled in hardware when supported, while nothing | |
1265 | * else is wired up. Keep it simple and simply assert DSR/CAR. | |
1266 | */ | |
1267 | return TIOCM_DSR | TIOCM_CAR; | |
1da177e4 LT |
1268 | } |
1269 | ||
73a19e4c GL |
1270 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1271 | static void sci_dma_tx_complete(void *arg) | |
1272 | { | |
1273 | struct sci_port *s = arg; | |
1274 | struct uart_port *port = &s->port; | |
1275 | struct circ_buf *xmit = &port->state->xmit; | |
1276 | unsigned long flags; | |
1277 | ||
1278 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); | |
1279 | ||
1280 | spin_lock_irqsave(&port->lock, flags); | |
1281 | ||
79904420 | 1282 | xmit->tail += s->tx_dma_len; |
73a19e4c GL |
1283 | xmit->tail &= UART_XMIT_SIZE - 1; |
1284 | ||
79904420 | 1285 | port->icount.tx += s->tx_dma_len; |
73a19e4c | 1286 | |
73a19e4c GL |
1287 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
1288 | uart_write_wakeup(port); | |
1289 | ||
3089f381 | 1290 | if (!uart_circ_empty(xmit)) { |
49d4bcad | 1291 | s->cookie_tx = 0; |
73a19e4c | 1292 | schedule_work(&s->work_tx); |
49d4bcad TY |
1293 | } else { |
1294 | s->cookie_tx = -EINVAL; | |
1295 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { | |
b12bb29f PM |
1296 | u16 ctrl = serial_port_in(port, SCSCR); |
1297 | serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); | |
49d4bcad | 1298 | } |
3089f381 GL |
1299 | } |
1300 | ||
1301 | spin_unlock_irqrestore(&port->lock, flags); | |
73a19e4c GL |
1302 | } |
1303 | ||
1304 | /* Locking: called with port lock held */ | |
7b39d901 | 1305 | static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) |
73a19e4c GL |
1306 | { |
1307 | struct uart_port *port = &s->port; | |
227434f8 | 1308 | struct tty_port *tport = &port->state->port; |
47b0e94a | 1309 | int copied; |
73a19e4c | 1310 | |
7b39d901 | 1311 | copied = tty_insert_flip_string(tport, buf, count); |
47b0e94a | 1312 | if (copied < count) { |
e2afca69 | 1313 | dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n", |
47b0e94a GU |
1314 | count - copied); |
1315 | port->icount.buf_overrun++; | |
1316 | } | |
73a19e4c | 1317 | |
47b0e94a | 1318 | port->icount.rx += copied; |
73a19e4c | 1319 | |
47b0e94a | 1320 | return copied; |
73a19e4c GL |
1321 | } |
1322 | ||
0533502d GU |
1323 | static int sci_dma_rx_find_active(struct sci_port *s) |
1324 | { | |
1325 | unsigned int i; | |
1326 | ||
1327 | for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) | |
1328 | if (s->active_rx == s->cookie_rx[i]) | |
1329 | return i; | |
1330 | ||
1331 | dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__, | |
1332 | s->active_rx); | |
1333 | return -1; | |
1334 | } | |
1335 | ||
73a19e4c GL |
1336 | static void sci_dma_rx_complete(void *arg) |
1337 | { | |
1338 | struct sci_port *s = arg; | |
1339 | struct uart_port *port = &s->port; | |
73a19e4c | 1340 | unsigned long flags; |
0533502d | 1341 | int active, count = 0; |
73a19e4c | 1342 | |
beb9487b GU |
1343 | dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, |
1344 | s->active_rx); | |
73a19e4c GL |
1345 | |
1346 | spin_lock_irqsave(&port->lock, flags); | |
1347 | ||
0533502d GU |
1348 | active = sci_dma_rx_find_active(s); |
1349 | if (active >= 0) | |
7b39d901 | 1350 | count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); |
73a19e4c | 1351 | |
3089f381 | 1352 | mod_timer(&s->rx_timer, jiffies + s->rx_timeout); |
73a19e4c GL |
1353 | |
1354 | spin_unlock_irqrestore(&port->lock, flags); | |
1355 | ||
1356 | if (count) | |
2e124b4a | 1357 | tty_flip_buffer_push(&port->state->port); |
73a19e4c GL |
1358 | |
1359 | schedule_work(&s->work_rx); | |
1360 | } | |
1361 | ||
73a19e4c GL |
1362 | static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) |
1363 | { | |
1364 | struct dma_chan *chan = s->chan_rx; | |
1365 | struct uart_port *port = &s->port; | |
04928b79 | 1366 | unsigned long flags; |
73a19e4c | 1367 | |
04928b79 | 1368 | spin_lock_irqsave(&port->lock, flags); |
73a19e4c GL |
1369 | s->chan_rx = NULL; |
1370 | s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; | |
04928b79 GU |
1371 | spin_unlock_irqrestore(&port->lock, flags); |
1372 | dmaengine_terminate_all(chan); | |
7b39d901 YS |
1373 | dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], |
1374 | sg_dma_address(&s->sg_rx[0])); | |
8e14ba8f | 1375 | dma_release_channel(chan); |
73a19e4c GL |
1376 | if (enable_pio) |
1377 | sci_start_rx(port); | |
1378 | } | |
1379 | ||
1380 | static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) | |
1381 | { | |
1382 | struct dma_chan *chan = s->chan_tx; | |
1383 | struct uart_port *port = &s->port; | |
04928b79 | 1384 | unsigned long flags; |
73a19e4c | 1385 | |
04928b79 | 1386 | spin_lock_irqsave(&port->lock, flags); |
73a19e4c GL |
1387 | s->chan_tx = NULL; |
1388 | s->cookie_tx = -EINVAL; | |
04928b79 GU |
1389 | spin_unlock_irqrestore(&port->lock, flags); |
1390 | dmaengine_terminate_all(chan); | |
2e301474 GU |
1391 | dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, |
1392 | DMA_TO_DEVICE); | |
73a19e4c GL |
1393 | dma_release_channel(chan); |
1394 | if (enable_pio) | |
1395 | sci_start_tx(port); | |
1396 | } | |
1397 | ||
1398 | static void sci_submit_rx(struct sci_port *s) | |
1399 | { | |
1400 | struct dma_chan *chan = s->chan_rx; | |
1401 | int i; | |
1402 | ||
1403 | for (i = 0; i < 2; i++) { | |
1404 | struct scatterlist *sg = &s->sg_rx[i]; | |
1405 | struct dma_async_tx_descriptor *desc; | |
1406 | ||
16052827 | 1407 | desc = dmaengine_prep_slave_sg(chan, |
47aceb92 GU |
1408 | sg, 1, DMA_DEV_TO_MEM, |
1409 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
658daa95 GU |
1410 | if (!desc) |
1411 | goto fail; | |
73a19e4c | 1412 | |
658daa95 GU |
1413 | desc->callback = sci_dma_rx_complete; |
1414 | desc->callback_param = s; | |
1415 | s->cookie_rx[i] = dmaengine_submit(desc); | |
1416 | if (dma_submit_error(s->cookie_rx[i])) | |
1417 | goto fail; | |
73a19e4c | 1418 | |
beb9487b GU |
1419 | dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, |
1420 | s->cookie_rx[i], i); | |
73a19e4c GL |
1421 | } |
1422 | ||
1423 | s->active_rx = s->cookie_rx[0]; | |
1424 | ||
1425 | dma_async_issue_pending(chan); | |
658daa95 GU |
1426 | return; |
1427 | ||
1428 | fail: | |
1429 | if (i) | |
1430 | dmaengine_terminate_all(chan); | |
47aceb92 | 1431 | for (i = 0; i < 2; i++) |
658daa95 | 1432 | s->cookie_rx[i] = -EINVAL; |
658daa95 GU |
1433 | s->active_rx = -EINVAL; |
1434 | dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n"); | |
1435 | sci_rx_dma_release(s, true); | |
73a19e4c GL |
1436 | } |
1437 | ||
1438 | static void work_fn_rx(struct work_struct *work) | |
1439 | { | |
1440 | struct sci_port *s = container_of(work, struct sci_port, work_rx); | |
1441 | struct uart_port *port = &s->port; | |
1442 | struct dma_async_tx_descriptor *desc; | |
565dd11a GU |
1443 | struct dma_tx_state state; |
1444 | enum dma_status status; | |
0907c100 | 1445 | unsigned long flags; |
73a19e4c GL |
1446 | int new; |
1447 | ||
0907c100 | 1448 | spin_lock_irqsave(&port->lock, flags); |
0533502d GU |
1449 | new = sci_dma_rx_find_active(s); |
1450 | if (new < 0) { | |
04928b79 GU |
1451 | spin_unlock_irqrestore(&port->lock, flags); |
1452 | return; | |
73a19e4c | 1453 | } |
73a19e4c | 1454 | |
565dd11a GU |
1455 | status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); |
1456 | if (status != DMA_COMPLETE) { | |
73a19e4c | 1457 | /* Handle incomplete DMA receive */ |
73a19e4c | 1458 | struct dma_chan *chan = s->chan_rx; |
565dd11a | 1459 | unsigned int read; |
73a19e4c GL |
1460 | int count; |
1461 | ||
2bcd90d5 | 1462 | dmaengine_terminate_all(chan); |
565dd11a GU |
1463 | read = sg_dma_len(&s->sg_rx[new]) - state.residue; |
1464 | dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read, | |
1465 | s->active_rx); | |
73a19e4c | 1466 | |
7b39d901 | 1467 | count = sci_dma_rx_push(s, s->rx_buf[new], read); |
73a19e4c GL |
1468 | |
1469 | if (count) | |
2e124b4a | 1470 | tty_flip_buffer_push(&port->state->port); |
73a19e4c | 1471 | |
04928b79 | 1472 | spin_unlock_irqrestore(&port->lock, flags); |
73a19e4c | 1473 | |
04928b79 GU |
1474 | sci_submit_rx(s); |
1475 | return; | |
73a19e4c GL |
1476 | } |
1477 | ||
47aceb92 GU |
1478 | desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[new], 1, |
1479 | DMA_DEV_TO_MEM, | |
1480 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1481 | if (!desc) | |
1482 | goto fail; | |
1483 | ||
1484 | desc->callback = sci_dma_rx_complete; | |
1485 | desc->callback_param = s; | |
3e14670c | 1486 | s->cookie_rx[new] = dmaengine_submit(desc); |
47aceb92 GU |
1487 | if (dma_submit_error(s->cookie_rx[new])) |
1488 | goto fail; | |
73a19e4c | 1489 | |
73a19e4c | 1490 | s->active_rx = s->cookie_rx[!new]; |
3089f381 | 1491 | |
beb9487b | 1492 | dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", |
9b971cd2 | 1493 | __func__, s->cookie_rx[new], new, s->active_rx); |
0907c100 | 1494 | spin_unlock_irqrestore(&port->lock, flags); |
47aceb92 GU |
1495 | return; |
1496 | ||
1497 | fail: | |
04928b79 | 1498 | spin_unlock_irqrestore(&port->lock, flags); |
47aceb92 GU |
1499 | dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); |
1500 | sci_rx_dma_release(s, true); | |
73a19e4c GL |
1501 | } |
1502 | ||
1503 | static void work_fn_tx(struct work_struct *work) | |
1504 | { | |
1505 | struct sci_port *s = container_of(work, struct sci_port, work_tx); | |
1506 | struct dma_async_tx_descriptor *desc; | |
1507 | struct dma_chan *chan = s->chan_tx; | |
1508 | struct uart_port *port = &s->port; | |
1509 | struct circ_buf *xmit = &port->state->xmit; | |
79904420 | 1510 | dma_addr_t buf; |
73a19e4c GL |
1511 | |
1512 | /* | |
1513 | * DMA is idle now. | |
1514 | * Port xmit buffer is already mapped, and it is one page... Just adjust | |
1515 | * offsets and lengths. Since it is a circular buffer, we have to | |
1516 | * transmit till the end, and then the rest. Take the port lock to get a | |
1517 | * consistent xmit buffer state. | |
1518 | */ | |
1519 | spin_lock_irq(&port->lock); | |
79904420 GU |
1520 | buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1)); |
1521 | s->tx_dma_len = min_t(unsigned int, | |
092248aa | 1522 | CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), |
73a19e4c | 1523 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); |
73a19e4c GL |
1524 | spin_unlock_irq(&port->lock); |
1525 | ||
79904420 GU |
1526 | desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, |
1527 | DMA_MEM_TO_DEV, | |
1528 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
73a19e4c | 1529 | if (!desc) { |
beb9487b | 1530 | dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); |
73a19e4c GL |
1531 | /* switch to PIO */ |
1532 | sci_tx_dma_release(s, true); | |
1533 | return; | |
1534 | } | |
1535 | ||
79904420 GU |
1536 | dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, |
1537 | DMA_TO_DEVICE); | |
73a19e4c GL |
1538 | |
1539 | spin_lock_irq(&port->lock); | |
73a19e4c GL |
1540 | desc->callback = sci_dma_tx_complete; |
1541 | desc->callback_param = s; | |
1542 | spin_unlock_irq(&port->lock); | |
3e14670c GU |
1543 | s->cookie_tx = dmaengine_submit(desc); |
1544 | if (dma_submit_error(s->cookie_tx)) { | |
73a19e4c GL |
1545 | dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); |
1546 | /* switch to PIO */ | |
1547 | sci_tx_dma_release(s, true); | |
1548 | return; | |
1549 | } | |
1550 | ||
9b971cd2 JP |
1551 | dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", |
1552 | __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx); | |
73a19e4c GL |
1553 | |
1554 | dma_async_issue_pending(chan); | |
1555 | } | |
1556 | #endif | |
1557 | ||
b129a8cc | 1558 | static void sci_start_tx(struct uart_port *port) |
1da177e4 | 1559 | { |
3089f381 | 1560 | struct sci_port *s = to_sci_port(port); |
e108b2ca | 1561 | unsigned short ctrl; |
1da177e4 | 1562 | |
73a19e4c | 1563 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
d1d4b10c | 1564 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
b12bb29f | 1565 | u16 new, scr = serial_port_in(port, SCSCR); |
3089f381 | 1566 | if (s->chan_tx) |
26de4f1b | 1567 | new = scr | SCSCR_TDRQE; |
3089f381 | 1568 | else |
26de4f1b | 1569 | new = scr & ~SCSCR_TDRQE; |
3089f381 | 1570 | if (new != scr) |
b12bb29f | 1571 | serial_port_out(port, SCSCR, new); |
73a19e4c | 1572 | } |
f43dc23d | 1573 | |
3089f381 | 1574 | if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && |
3e14670c | 1575 | dma_submit_error(s->cookie_tx)) { |
49d4bcad | 1576 | s->cookie_tx = 0; |
3089f381 | 1577 | schedule_work(&s->work_tx); |
49d4bcad | 1578 | } |
73a19e4c | 1579 | #endif |
f43dc23d | 1580 | |
d1d4b10c | 1581 | if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 | 1582 | /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ |
b12bb29f PM |
1583 | ctrl = serial_port_in(port, SCSCR); |
1584 | serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); | |
3089f381 | 1585 | } |
1da177e4 LT |
1586 | } |
1587 | ||
b129a8cc | 1588 | static void sci_stop_tx(struct uart_port *port) |
1da177e4 | 1589 | { |
1da177e4 LT |
1590 | unsigned short ctrl; |
1591 | ||
1592 | /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
b12bb29f | 1593 | ctrl = serial_port_in(port, SCSCR); |
f43dc23d | 1594 | |
d1d4b10c | 1595 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
26de4f1b | 1596 | ctrl &= ~SCSCR_TDRQE; |
f43dc23d | 1597 | |
8e698614 | 1598 | ctrl &= ~SCSCR_TIE; |
f43dc23d | 1599 | |
b12bb29f | 1600 | serial_port_out(port, SCSCR, ctrl); |
1da177e4 LT |
1601 | } |
1602 | ||
73a19e4c | 1603 | static void sci_start_rx(struct uart_port *port) |
1da177e4 | 1604 | { |
1da177e4 LT |
1605 | unsigned short ctrl; |
1606 | ||
b12bb29f | 1607 | ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); |
1da177e4 | 1608 | |
d1d4b10c | 1609 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
26de4f1b | 1610 | ctrl &= ~SCSCR_RDRQE; |
f43dc23d | 1611 | |
b12bb29f | 1612 | serial_port_out(port, SCSCR, ctrl); |
1da177e4 LT |
1613 | } |
1614 | ||
1615 | static void sci_stop_rx(struct uart_port *port) | |
1616 | { | |
1da177e4 LT |
1617 | unsigned short ctrl; |
1618 | ||
b12bb29f | 1619 | ctrl = serial_port_in(port, SCSCR); |
f43dc23d | 1620 | |
d1d4b10c | 1621 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
26de4f1b | 1622 | ctrl &= ~SCSCR_RDRQE; |
f43dc23d PM |
1623 | |
1624 | ctrl &= ~port_rx_irq_mask(port); | |
1625 | ||
b12bb29f | 1626 | serial_port_out(port, SCSCR, ctrl); |
1da177e4 LT |
1627 | } |
1628 | ||
1da177e4 LT |
1629 | static void sci_break_ctl(struct uart_port *port, int break_state) |
1630 | { | |
bbb4ce50 | 1631 | struct sci_port *s = to_sci_port(port); |
d3184e68 | 1632 | const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; |
bbb4ce50 SY |
1633 | unsigned short scscr, scsptr; |
1634 | ||
a4e02f6d SY |
1635 | /* check wheter the port has SCSPTR */ |
1636 | if (!reg->size) { | |
bbb4ce50 SY |
1637 | /* |
1638 | * Not supported by hardware. Most parts couple break and rx | |
1639 | * interrupts together, with break detection always enabled. | |
1640 | */ | |
a4e02f6d | 1641 | return; |
bbb4ce50 | 1642 | } |
a4e02f6d SY |
1643 | |
1644 | scsptr = serial_port_in(port, SCSPTR); | |
1645 | scscr = serial_port_in(port, SCSCR); | |
1646 | ||
1647 | if (break_state == -1) { | |
1648 | scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; | |
1649 | scscr &= ~SCSCR_TE; | |
1650 | } else { | |
1651 | scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; | |
1652 | scscr |= SCSCR_TE; | |
1653 | } | |
1654 | ||
1655 | serial_port_out(port, SCSPTR, scsptr); | |
1656 | serial_port_out(port, SCSCR, scscr); | |
1da177e4 LT |
1657 | } |
1658 | ||
73a19e4c GL |
1659 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1660 | static bool filter(struct dma_chan *chan, void *slave) | |
1661 | { | |
1662 | struct sh_dmae_slave *param = slave; | |
1663 | ||
9b971cd2 JP |
1664 | dev_dbg(chan->device->dev, "%s: slave ID %d\n", |
1665 | __func__, param->shdma_slave.slave_id); | |
73a19e4c | 1666 | |
d6fa5a4e | 1667 | chan->private = ¶m->shdma_slave; |
937bb6e4 | 1668 | return true; |
73a19e4c GL |
1669 | } |
1670 | ||
1671 | static void rx_timer_fn(unsigned long arg) | |
1672 | { | |
1673 | struct sci_port *s = (struct sci_port *)arg; | |
1674 | struct uart_port *port = &s->port; | |
b12bb29f | 1675 | u16 scr = serial_port_in(port, SCSCR); |
3089f381 | 1676 | |
d1d4b10c | 1677 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
26de4f1b | 1678 | scr &= ~SCSCR_RDRQE; |
1fcc91a6 | 1679 | enable_irq(s->irqs[SCIx_RXI_IRQ]); |
3089f381 | 1680 | } |
b12bb29f | 1681 | serial_port_out(port, SCSCR, scr | SCSCR_RIE); |
73a19e4c GL |
1682 | dev_dbg(port->dev, "DMA Rx timed out\n"); |
1683 | schedule_work(&s->work_rx); | |
1684 | } | |
1685 | ||
1686 | static void sci_request_dma(struct uart_port *port) | |
1687 | { | |
1688 | struct sci_port *s = to_sci_port(port); | |
1689 | struct sh_dmae_slave *param; | |
1690 | struct dma_chan *chan; | |
1691 | dma_cap_mask_t mask; | |
73a19e4c | 1692 | |
9b971cd2 | 1693 | dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); |
73a19e4c | 1694 | |
937bb6e4 | 1695 | if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0) |
73a19e4c GL |
1696 | return; |
1697 | ||
1698 | dma_cap_zero(mask); | |
1699 | dma_cap_set(DMA_SLAVE, mask); | |
1700 | ||
1701 | param = &s->param_tx; | |
1702 | ||
1703 | /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ | |
d6fa5a4e | 1704 | param->shdma_slave.slave_id = s->cfg->dma_slave_tx; |
73a19e4c GL |
1705 | |
1706 | s->cookie_tx = -EINVAL; | |
1707 | chan = dma_request_channel(mask, filter, param); | |
1708 | dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); | |
1709 | if (chan) { | |
1710 | s->chan_tx = chan; | |
73a19e4c | 1711 | /* UART circular tx buffer is an aligned page. */ |
79904420 GU |
1712 | s->tx_dma_addr = dma_map_single(chan->device->dev, |
1713 | port->state->xmit.buf, | |
1714 | UART_XMIT_SIZE, | |
1715 | DMA_TO_DEVICE); | |
1716 | if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { | |
beb9487b | 1717 | dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); |
b9258020 GU |
1718 | dma_release_channel(chan); |
1719 | s->chan_tx = NULL; | |
beb9487b | 1720 | } else { |
79904420 GU |
1721 | dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", |
1722 | __func__, UART_XMIT_SIZE, | |
1723 | port->state->xmit.buf, &s->tx_dma_addr); | |
beb9487b | 1724 | } |
73a19e4c | 1725 | |
73a19e4c GL |
1726 | INIT_WORK(&s->work_tx, work_fn_tx); |
1727 | } | |
1728 | ||
1729 | param = &s->param_rx; | |
1730 | ||
1731 | /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ | |
d6fa5a4e | 1732 | param->shdma_slave.slave_id = s->cfg->dma_slave_rx; |
73a19e4c GL |
1733 | |
1734 | chan = dma_request_channel(mask, filter, param); | |
1735 | dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); | |
1736 | if (chan) { | |
ba172c70 GU |
1737 | unsigned int i; |
1738 | dma_addr_t dma; | |
1739 | void *buf; | |
73a19e4c GL |
1740 | |
1741 | s->chan_rx = chan; | |
1742 | ||
092248aa | 1743 | s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); |
ba172c70 GU |
1744 | buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, |
1745 | &dma, GFP_KERNEL); | |
1746 | if (!buf) { | |
73a19e4c | 1747 | dev_warn(port->dev, |
beb9487b | 1748 | "Failed to allocate Rx dma buffer, using PIO\n"); |
b9258020 GU |
1749 | dma_release_channel(chan); |
1750 | s->chan_rx = NULL; | |
1751 | sci_start_rx(port); | |
73a19e4c GL |
1752 | return; |
1753 | } | |
1754 | ||
73a19e4c GL |
1755 | for (i = 0; i < 2; i++) { |
1756 | struct scatterlist *sg = &s->sg_rx[i]; | |
1757 | ||
1758 | sg_init_table(sg, 1); | |
7b39d901 | 1759 | s->rx_buf[i] = buf; |
ba172c70 | 1760 | sg_dma_address(sg) = dma; |
7b39d901 | 1761 | sg->length = s->buf_len_rx; |
ba172c70 GU |
1762 | |
1763 | buf += s->buf_len_rx; | |
1764 | dma += s->buf_len_rx; | |
73a19e4c GL |
1765 | } |
1766 | ||
1767 | INIT_WORK(&s->work_rx, work_fn_rx); | |
1768 | setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); | |
1769 | ||
1770 | sci_submit_rx(s); | |
1771 | } | |
1772 | } | |
1773 | ||
1774 | static void sci_free_dma(struct uart_port *port) | |
1775 | { | |
1776 | struct sci_port *s = to_sci_port(port); | |
1777 | ||
73a19e4c GL |
1778 | if (s->chan_tx) |
1779 | sci_tx_dma_release(s, false); | |
1780 | if (s->chan_rx) | |
1781 | sci_rx_dma_release(s, false); | |
1782 | } | |
27bd1075 PM |
1783 | #else |
1784 | static inline void sci_request_dma(struct uart_port *port) | |
1785 | { | |
1786 | } | |
1787 | ||
1788 | static inline void sci_free_dma(struct uart_port *port) | |
1789 | { | |
1790 | } | |
73a19e4c GL |
1791 | #endif |
1792 | ||
1da177e4 LT |
1793 | static int sci_startup(struct uart_port *port) |
1794 | { | |
a5660ada | 1795 | struct sci_port *s = to_sci_port(port); |
33b48e16 | 1796 | unsigned long flags; |
073e84c9 | 1797 | int ret; |
1da177e4 | 1798 | |
73a19e4c GL |
1799 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
1800 | ||
073e84c9 PM |
1801 | ret = sci_request_irq(s); |
1802 | if (unlikely(ret < 0)) | |
1803 | return ret; | |
1804 | ||
73a19e4c | 1805 | sci_request_dma(port); |
073e84c9 | 1806 | |
33b48e16 | 1807 | spin_lock_irqsave(&port->lock, flags); |
d656901b | 1808 | sci_start_tx(port); |
73a19e4c | 1809 | sci_start_rx(port); |
33b48e16 | 1810 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
1811 | |
1812 | return 0; | |
1813 | } | |
1814 | ||
1815 | static void sci_shutdown(struct uart_port *port) | |
1816 | { | |
a5660ada | 1817 | struct sci_port *s = to_sci_port(port); |
33b48e16 | 1818 | unsigned long flags; |
1da177e4 | 1819 | |
73a19e4c GL |
1820 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
1821 | ||
33b48e16 | 1822 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 | 1823 | sci_stop_rx(port); |
b129a8cc | 1824 | sci_stop_tx(port); |
33b48e16 | 1825 | spin_unlock_irqrestore(&port->lock, flags); |
073e84c9 | 1826 | |
73a19e4c | 1827 | sci_free_dma(port); |
1da177e4 | 1828 | sci_free_irq(s); |
1da177e4 LT |
1829 | } |
1830 | ||
ec09c5eb | 1831 | static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps, |
26c92f37 PM |
1832 | unsigned long freq) |
1833 | { | |
ec09c5eb LP |
1834 | if (s->sampling_rate) |
1835 | return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1; | |
1836 | ||
26c92f37 PM |
1837 | /* Warn, but use a safe default */ |
1838 | WARN_ON(1); | |
e8183a6c | 1839 | |
26c92f37 PM |
1840 | return ((freq + 16 * bps) / (32 * bps) - 1); |
1841 | } | |
1842 | ||
730c4e78 NI |
1843 | /* calculate frame length from SMR */ |
1844 | static int sci_baud_calc_frame_len(unsigned int smr_val) | |
1845 | { | |
1846 | int len = 10; | |
1847 | ||
1848 | if (smr_val & SCSMR_CHR) | |
1849 | len--; | |
1850 | if (smr_val & SCSMR_PE) | |
1851 | len++; | |
1852 | if (smr_val & SCSMR_STOP) | |
1853 | len++; | |
1854 | ||
1855 | return len; | |
1856 | } | |
1857 | ||
1858 | ||
f303b364 UH |
1859 | /* calculate sample rate, BRR, and clock select for HSCIF */ |
1860 | static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq, | |
1861 | int *brr, unsigned int *srr, | |
730c4e78 | 1862 | unsigned int *cks, int frame_len) |
f303b364 | 1863 | { |
730c4e78 | 1864 | int sr, c, br, err, recv_margin; |
f303b364 | 1865 | int min_err = 1000; /* 100% */ |
730c4e78 | 1866 | int recv_max_margin = 0; |
f303b364 UH |
1867 | |
1868 | /* Find the combination of sample rate and clock select with the | |
1869 | smallest deviation from the desired baud rate. */ | |
1870 | for (sr = 8; sr <= 32; sr++) { | |
1871 | for (c = 0; c <= 3; c++) { | |
1872 | /* integerized formulas from HSCIF documentation */ | |
b7d66397 NI |
1873 | br = DIV_ROUND_CLOSEST(freq, (sr * |
1874 | (1 << (2 * c + 1)) * bps)) - 1; | |
bcb9973a | 1875 | br = clamp(br, 0, 255); |
b7d66397 NI |
1876 | err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr * |
1877 | (1 << (2 * c + 1)) / 1000)) - | |
1878 | 1000; | |
730c4e78 NI |
1879 | /* Calc recv margin |
1880 | * M: Receive margin (%) | |
1881 | * N: Ratio of bit rate to clock (N = sampling rate) | |
1882 | * D: Clock duty (D = 0 to 1.0) | |
1883 | * L: Frame length (L = 9 to 12) | |
1884 | * F: Absolute value of clock frequency deviation | |
1885 | * | |
1886 | * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - | |
1887 | * (|D - 0.5| / N * (1 + F))| | |
1888 | * NOTE: Usually, treat D for 0.5, F is 0 by this | |
1889 | * calculation. | |
1890 | */ | |
1891 | recv_margin = abs((500 - | |
1892 | DIV_ROUND_CLOSEST(1000, sr << 1)) / 10); | |
f53297fb | 1893 | if (abs(min_err) > abs(err)) { |
f303b364 | 1894 | min_err = err; |
730c4e78 NI |
1895 | recv_max_margin = recv_margin; |
1896 | } else if ((min_err == err) && | |
1897 | (recv_margin > recv_max_margin)) | |
1898 | recv_max_margin = recv_margin; | |
1899 | else | |
1900 | continue; | |
1901 | ||
1902 | *brr = br; | |
1903 | *srr = sr - 1; | |
1904 | *cks = c; | |
f303b364 UH |
1905 | } |
1906 | } | |
1907 | ||
1908 | if (min_err == 1000) { | |
1909 | WARN_ON(1); | |
1910 | /* use defaults */ | |
1911 | *brr = 255; | |
1912 | *srr = 15; | |
1913 | *cks = 0; | |
1914 | } | |
1915 | } | |
1916 | ||
1ba76220 MD |
1917 | static void sci_reset(struct uart_port *port) |
1918 | { | |
d3184e68 | 1919 | const struct plat_sci_reg *reg; |
1ba76220 MD |
1920 | unsigned int status; |
1921 | ||
1922 | do { | |
b12bb29f | 1923 | status = serial_port_in(port, SCxSR); |
1ba76220 MD |
1924 | } while (!(status & SCxSR_TEND(port))); |
1925 | ||
b12bb29f | 1926 | serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ |
1ba76220 | 1927 | |
0979e0e6 PM |
1928 | reg = sci_getreg(port, SCFCR); |
1929 | if (reg->size) | |
b12bb29f | 1930 | serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); |
1ba76220 MD |
1931 | } |
1932 | ||
606d099c AC |
1933 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
1934 | struct ktermios *old) | |
1da177e4 | 1935 | { |
00b9de9c | 1936 | struct sci_port *s = to_sci_port(port); |
d3184e68 | 1937 | const struct plat_sci_reg *reg; |
730c4e78 | 1938 | unsigned int baud, smr_val = 0, max_baud, cks = 0; |
a2159b52 | 1939 | int t = -1; |
d4759ded | 1940 | unsigned int srr = 15; |
1da177e4 | 1941 | |
730c4e78 NI |
1942 | if ((termios->c_cflag & CSIZE) == CS7) |
1943 | smr_val |= SCSMR_CHR; | |
1944 | if (termios->c_cflag & PARENB) | |
1945 | smr_val |= SCSMR_PE; | |
1946 | if (termios->c_cflag & PARODD) | |
1947 | smr_val |= SCSMR_PE | SCSMR_ODD; | |
1948 | if (termios->c_cflag & CSTOPB) | |
1949 | smr_val |= SCSMR_STOP; | |
1950 | ||
154280fd MD |
1951 | /* |
1952 | * earlyprintk comes here early on with port->uartclk set to zero. | |
1953 | * the clock framework is not up and running at this point so here | |
1954 | * we assume that 115200 is the maximum baud rate. please note that | |
1955 | * the baud rate is not programmed during earlyprintk - it is assumed | |
1956 | * that the previous boot loader has enabled required clocks and | |
1957 | * setup the baud rate generator hardware for us already. | |
1958 | */ | |
1959 | max_baud = port->uartclk ? port->uartclk / 16 : 115200; | |
1da177e4 | 1960 | |
154280fd | 1961 | baud = uart_get_baud_rate(port, termios, old, 0, max_baud); |
f303b364 | 1962 | if (likely(baud && port->uartclk)) { |
ec09c5eb | 1963 | if (s->cfg->type == PORT_HSCIF) { |
730c4e78 | 1964 | int frame_len = sci_baud_calc_frame_len(smr_val); |
f303b364 | 1965 | sci_baud_calc_hscif(baud, port->uartclk, &t, &srr, |
730c4e78 | 1966 | &cks, frame_len); |
f303b364 | 1967 | } else { |
ec09c5eb | 1968 | t = sci_scbrr_calc(s, baud, port->uartclk); |
f303b364 UH |
1969 | for (cks = 0; t >= 256 && cks <= 3; cks++) |
1970 | t >>= 2; | |
1971 | } | |
1972 | } | |
e108b2ca | 1973 | |
23241d43 | 1974 | sci_port_enable(s); |
36003386 | 1975 | |
1ba76220 | 1976 | sci_reset(port); |
1da177e4 | 1977 | |
2944a331 | 1978 | smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS; |
1da177e4 LT |
1979 | |
1980 | uart_update_timeout(port, termios->c_cflag, baud); | |
1981 | ||
9d482cc3 TY |
1982 | dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n", |
1983 | __func__, smr_val, cks, t, s->cfg->scscr); | |
73a19e4c | 1984 | |
4ffc3cdb | 1985 | if (t >= 0) { |
26de4f1b | 1986 | serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks); |
b12bb29f | 1987 | serial_port_out(port, SCBRR, t); |
f303b364 UH |
1988 | reg = sci_getreg(port, HSSRR); |
1989 | if (reg->size) | |
1990 | serial_port_out(port, HSSRR, srr | HSCIF_SRE); | |
1da177e4 | 1991 | udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ |
9d482cc3 TY |
1992 | } else |
1993 | serial_port_out(port, SCSMR, smr_val); | |
1da177e4 | 1994 | |
d5701647 | 1995 | sci_init_pins(port, termios->c_cflag); |
0979e0e6 | 1996 | |
73c3d53f PM |
1997 | reg = sci_getreg(port, SCFCR); |
1998 | if (reg->size) { | |
b12bb29f | 1999 | unsigned short ctrl = serial_port_in(port, SCFCR); |
0979e0e6 | 2000 | |
73c3d53f | 2001 | if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) { |
faf02f8f PM |
2002 | if (termios->c_cflag & CRTSCTS) |
2003 | ctrl |= SCFCR_MCE; | |
2004 | else | |
2005 | ctrl &= ~SCFCR_MCE; | |
faf02f8f | 2006 | } |
73c3d53f PM |
2007 | |
2008 | /* | |
2009 | * As we've done a sci_reset() above, ensure we don't | |
2010 | * interfere with the FIFOs while toggling MCE. As the | |
2011 | * reset values could still be set, simply mask them out. | |
2012 | */ | |
2013 | ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); | |
2014 | ||
b12bb29f | 2015 | serial_port_out(port, SCFCR, ctrl); |
0979e0e6 | 2016 | } |
b7a76e4b | 2017 | |
b12bb29f | 2018 | serial_port_out(port, SCSCR, s->cfg->scscr); |
1da177e4 | 2019 | |
3089f381 GL |
2020 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
2021 | /* | |
5f6d8515 | 2022 | * Calculate delay for 2 DMA buffers (4 FIFO). |
f5835c1d GU |
2023 | * See serial_core.c::uart_update_timeout(). |
2024 | * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above | |
2025 | * function calculates 1 jiffie for the data plus 5 jiffies for the | |
2026 | * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA | |
2027 | * buffers (4 FIFO sizes), but when performing a faster transfer, the | |
2028 | * value obtained by this formula is too small. Therefore, if the value | |
2029 | * is smaller than 20ms, use 20ms as the timeout value for DMA. | |
3089f381 GL |
2030 | */ |
2031 | if (s->chan_rx) { | |
5f6d8515 NI |
2032 | unsigned int bits; |
2033 | ||
2034 | /* byte size and parity */ | |
2035 | switch (termios->c_cflag & CSIZE) { | |
2036 | case CS5: | |
2037 | bits = 7; | |
2038 | break; | |
2039 | case CS6: | |
2040 | bits = 8; | |
2041 | break; | |
2042 | case CS7: | |
2043 | bits = 9; | |
2044 | break; | |
2045 | default: | |
2046 | bits = 10; | |
2047 | break; | |
2048 | } | |
2049 | ||
2050 | if (termios->c_cflag & CSTOPB) | |
2051 | bits++; | |
2052 | if (termios->c_cflag & PARENB) | |
2053 | bits++; | |
2054 | s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) / | |
2055 | (baud / 10), 10); | |
9b971cd2 | 2056 | dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n", |
3089f381 GL |
2057 | s->rx_timeout * 1000 / HZ, port->timeout); |
2058 | if (s->rx_timeout < msecs_to_jiffies(20)) | |
2059 | s->rx_timeout = msecs_to_jiffies(20); | |
2060 | } | |
2061 | #endif | |
2062 | ||
1da177e4 | 2063 | if ((termios->c_cflag & CREAD) != 0) |
73a19e4c | 2064 | sci_start_rx(port); |
36003386 | 2065 | |
23241d43 | 2066 | sci_port_disable(s); |
1da177e4 LT |
2067 | } |
2068 | ||
0174e5ca TK |
2069 | static void sci_pm(struct uart_port *port, unsigned int state, |
2070 | unsigned int oldstate) | |
2071 | { | |
2072 | struct sci_port *sci_port = to_sci_port(port); | |
2073 | ||
2074 | switch (state) { | |
d3dfe5d9 | 2075 | case UART_PM_STATE_OFF: |
0174e5ca TK |
2076 | sci_port_disable(sci_port); |
2077 | break; | |
2078 | default: | |
2079 | sci_port_enable(sci_port); | |
2080 | break; | |
2081 | } | |
2082 | } | |
2083 | ||
1da177e4 LT |
2084 | static const char *sci_type(struct uart_port *port) |
2085 | { | |
2086 | switch (port->type) { | |
e7c98dc7 MT |
2087 | case PORT_IRDA: |
2088 | return "irda"; | |
2089 | case PORT_SCI: | |
2090 | return "sci"; | |
2091 | case PORT_SCIF: | |
2092 | return "scif"; | |
2093 | case PORT_SCIFA: | |
2094 | return "scifa"; | |
d1d4b10c GL |
2095 | case PORT_SCIFB: |
2096 | return "scifb"; | |
f303b364 UH |
2097 | case PORT_HSCIF: |
2098 | return "hscif"; | |
1da177e4 LT |
2099 | } |
2100 | ||
fa43972f | 2101 | return NULL; |
1da177e4 LT |
2102 | } |
2103 | ||
f6e9495d PM |
2104 | static int sci_remap_port(struct uart_port *port) |
2105 | { | |
e4d6f911 | 2106 | struct sci_port *sport = to_sci_port(port); |
f6e9495d PM |
2107 | |
2108 | /* | |
2109 | * Nothing to do if there's already an established membase. | |
2110 | */ | |
2111 | if (port->membase) | |
2112 | return 0; | |
2113 | ||
2114 | if (port->flags & UPF_IOREMAP) { | |
e4d6f911 | 2115 | port->membase = ioremap_nocache(port->mapbase, sport->reg_size); |
f6e9495d PM |
2116 | if (unlikely(!port->membase)) { |
2117 | dev_err(port->dev, "can't remap port#%d\n", port->line); | |
2118 | return -ENXIO; | |
2119 | } | |
2120 | } else { | |
2121 | /* | |
2122 | * For the simple (and majority of) cases where we don't | |
2123 | * need to do any remapping, just cast the cookie | |
2124 | * directly. | |
2125 | */ | |
3af4e960 | 2126 | port->membase = (void __iomem *)(uintptr_t)port->mapbase; |
f6e9495d PM |
2127 | } |
2128 | ||
2129 | return 0; | |
2130 | } | |
2131 | ||
e2651647 | 2132 | static void sci_release_port(struct uart_port *port) |
1da177e4 | 2133 | { |
e4d6f911 YS |
2134 | struct sci_port *sport = to_sci_port(port); |
2135 | ||
e2651647 PM |
2136 | if (port->flags & UPF_IOREMAP) { |
2137 | iounmap(port->membase); | |
2138 | port->membase = NULL; | |
2139 | } | |
2140 | ||
e4d6f911 | 2141 | release_mem_region(port->mapbase, sport->reg_size); |
1da177e4 LT |
2142 | } |
2143 | ||
e2651647 | 2144 | static int sci_request_port(struct uart_port *port) |
1da177e4 | 2145 | { |
e2651647 | 2146 | struct resource *res; |
e4d6f911 | 2147 | struct sci_port *sport = to_sci_port(port); |
f6e9495d | 2148 | int ret; |
1da177e4 | 2149 | |
e4d6f911 YS |
2150 | res = request_mem_region(port->mapbase, sport->reg_size, |
2151 | dev_name(port->dev)); | |
2152 | if (unlikely(res == NULL)) { | |
2153 | dev_err(port->dev, "request_mem_region failed."); | |
e2651647 | 2154 | return -EBUSY; |
e4d6f911 | 2155 | } |
1da177e4 | 2156 | |
f6e9495d PM |
2157 | ret = sci_remap_port(port); |
2158 | if (unlikely(ret != 0)) { | |
2159 | release_resource(res); | |
2160 | return ret; | |
7ff731ae | 2161 | } |
e2651647 PM |
2162 | |
2163 | return 0; | |
2164 | } | |
2165 | ||
2166 | static void sci_config_port(struct uart_port *port, int flags) | |
2167 | { | |
2168 | if (flags & UART_CONFIG_TYPE) { | |
2169 | struct sci_port *sport = to_sci_port(port); | |
2170 | ||
2171 | port->type = sport->cfg->type; | |
2172 | sci_request_port(port); | |
2173 | } | |
1da177e4 LT |
2174 | } |
2175 | ||
2176 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | |
2177 | { | |
1da177e4 LT |
2178 | if (ser->baud_base < 2400) |
2179 | /* No paper tape reader for Mitch.. */ | |
2180 | return -EINVAL; | |
2181 | ||
2182 | return 0; | |
2183 | } | |
2184 | ||
2185 | static struct uart_ops sci_uart_ops = { | |
2186 | .tx_empty = sci_tx_empty, | |
2187 | .set_mctrl = sci_set_mctrl, | |
2188 | .get_mctrl = sci_get_mctrl, | |
2189 | .start_tx = sci_start_tx, | |
2190 | .stop_tx = sci_stop_tx, | |
2191 | .stop_rx = sci_stop_rx, | |
1da177e4 LT |
2192 | .break_ctl = sci_break_ctl, |
2193 | .startup = sci_startup, | |
2194 | .shutdown = sci_shutdown, | |
2195 | .set_termios = sci_set_termios, | |
0174e5ca | 2196 | .pm = sci_pm, |
1da177e4 LT |
2197 | .type = sci_type, |
2198 | .release_port = sci_release_port, | |
2199 | .request_port = sci_request_port, | |
2200 | .config_port = sci_config_port, | |
2201 | .verify_port = sci_verify_port, | |
07d2a1a1 PM |
2202 | #ifdef CONFIG_CONSOLE_POLL |
2203 | .poll_get_char = sci_poll_get_char, | |
2204 | .poll_put_char = sci_poll_put_char, | |
2205 | #endif | |
1da177e4 LT |
2206 | }; |
2207 | ||
9671f099 | 2208 | static int sci_init_single(struct platform_device *dev, |
1fcc91a6 LP |
2209 | struct sci_port *sci_port, unsigned int index, |
2210 | struct plat_sci_port *p, bool early) | |
e108b2ca | 2211 | { |
73a19e4c | 2212 | struct uart_port *port = &sci_port->port; |
1fcc91a6 LP |
2213 | const struct resource *res; |
2214 | unsigned int i; | |
3127c6b2 | 2215 | int ret; |
e108b2ca | 2216 | |
50f0959a PM |
2217 | sci_port->cfg = p; |
2218 | ||
73a19e4c GL |
2219 | port->ops = &sci_uart_ops; |
2220 | port->iotype = UPIO_MEM; | |
2221 | port->line = index; | |
75136d48 | 2222 | |
89b5c1ab LP |
2223 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
2224 | if (res == NULL) | |
2225 | return -ENOMEM; | |
1fcc91a6 | 2226 | |
89b5c1ab | 2227 | port->mapbase = res->start; |
e4d6f911 | 2228 | sci_port->reg_size = resource_size(res); |
1fcc91a6 | 2229 | |
89b5c1ab LP |
2230 | for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) |
2231 | sci_port->irqs[i] = platform_get_irq(dev, i); | |
1fcc91a6 | 2232 | |
89b5c1ab LP |
2233 | /* The SCI generates several interrupts. They can be muxed together or |
2234 | * connected to different interrupt lines. In the muxed case only one | |
2235 | * interrupt resource is specified. In the non-muxed case three or four | |
2236 | * interrupt resources are specified, as the BRI interrupt is optional. | |
2237 | */ | |
2238 | if (sci_port->irqs[0] < 0) | |
2239 | return -ENXIO; | |
1fcc91a6 | 2240 | |
89b5c1ab LP |
2241 | if (sci_port->irqs[1] < 0) { |
2242 | sci_port->irqs[1] = sci_port->irqs[0]; | |
2243 | sci_port->irqs[2] = sci_port->irqs[0]; | |
2244 | sci_port->irqs[3] = sci_port->irqs[0]; | |
1fcc91a6 LP |
2245 | } |
2246 | ||
b545e4f4 LP |
2247 | if (p->regtype == SCIx_PROBE_REGTYPE) { |
2248 | ret = sci_probe_regmap(p); | |
2249 | if (unlikely(ret)) | |
2250 | return ret; | |
2251 | } | |
2252 | ||
75136d48 | 2253 | switch (p->type) { |
d1d4b10c GL |
2254 | case PORT_SCIFB: |
2255 | port->fifosize = 256; | |
2e0842a1 | 2256 | sci_port->overrun_reg = SCxSR; |
75c249fd | 2257 | sci_port->overrun_mask = SCIFA_ORER; |
f84b6bdc | 2258 | sci_port->sampling_rate = 16; |
d1d4b10c | 2259 | break; |
f303b364 UH |
2260 | case PORT_HSCIF: |
2261 | port->fifosize = 128; | |
2e0842a1 | 2262 | sci_port->overrun_reg = SCLSR; |
75c249fd | 2263 | sci_port->overrun_mask = SCLSR_ORER; |
f84b6bdc | 2264 | sci_port->sampling_rate = 0; |
f303b364 | 2265 | break; |
75136d48 | 2266 | case PORT_SCIFA: |
73a19e4c | 2267 | port->fifosize = 64; |
2e0842a1 | 2268 | sci_port->overrun_reg = SCxSR; |
75c249fd | 2269 | sci_port->overrun_mask = SCIFA_ORER; |
f84b6bdc | 2270 | sci_port->sampling_rate = 16; |
75136d48 MP |
2271 | break; |
2272 | case PORT_SCIF: | |
73a19e4c | 2273 | port->fifosize = 16; |
ec09c5eb | 2274 | if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) { |
2e0842a1 | 2275 | sci_port->overrun_reg = SCxSR; |
75c249fd | 2276 | sci_port->overrun_mask = SCIFA_ORER; |
f84b6bdc | 2277 | sci_port->sampling_rate = 16; |
ec09c5eb | 2278 | } else { |
2e0842a1 | 2279 | sci_port->overrun_reg = SCLSR; |
75c249fd | 2280 | sci_port->overrun_mask = SCLSR_ORER; |
f84b6bdc | 2281 | sci_port->sampling_rate = 32; |
ec09c5eb | 2282 | } |
75136d48 MP |
2283 | break; |
2284 | default: | |
73a19e4c | 2285 | port->fifosize = 1; |
2e0842a1 | 2286 | sci_port->overrun_reg = SCxSR; |
75c249fd | 2287 | sci_port->overrun_mask = SCI_ORER; |
f84b6bdc | 2288 | sci_port->sampling_rate = 32; |
75136d48 MP |
2289 | break; |
2290 | } | |
7b6fd3bf | 2291 | |
878fbb91 LP |
2292 | /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't |
2293 | * match the SoC datasheet, this should be investigated. Let platform | |
2294 | * data override the sampling rate for now. | |
ec09c5eb | 2295 | */ |
f84b6bdc GU |
2296 | if (p->sampling_rate) |
2297 | sci_port->sampling_rate = p->sampling_rate; | |
ec09c5eb | 2298 | |
1fcc91a6 | 2299 | if (!early) { |
c7ed1ab3 PM |
2300 | sci_port->iclk = clk_get(&dev->dev, "sci_ick"); |
2301 | if (IS_ERR(sci_port->iclk)) { | |
2302 | sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); | |
2303 | if (IS_ERR(sci_port->iclk)) { | |
2304 | dev_err(&dev->dev, "can't get iclk\n"); | |
2305 | return PTR_ERR(sci_port->iclk); | |
2306 | } | |
2307 | } | |
2308 | ||
2309 | /* | |
2310 | * The function clock is optional, ignore it if we can't | |
2311 | * find it. | |
2312 | */ | |
2313 | sci_port->fclk = clk_get(&dev->dev, "sci_fck"); | |
2314 | if (IS_ERR(sci_port->fclk)) | |
2315 | sci_port->fclk = NULL; | |
2316 | ||
73a19e4c | 2317 | port->dev = &dev->dev; |
5e50d2d6 MD |
2318 | |
2319 | pm_runtime_enable(&dev->dev); | |
7b6fd3bf | 2320 | } |
e108b2ca | 2321 | |
7ed7e071 MD |
2322 | sci_port->break_timer.data = (unsigned long)sci_port; |
2323 | sci_port->break_timer.function = sci_break_timer; | |
2324 | init_timer(&sci_port->break_timer); | |
2325 | ||
debf9507 PM |
2326 | /* |
2327 | * Establish some sensible defaults for the error detection. | |
2328 | */ | |
5da0f468 GU |
2329 | if (p->type == PORT_SCI) { |
2330 | sci_port->error_mask = SCI_DEFAULT_ERROR_MASK; | |
2331 | sci_port->error_clear = SCI_ERROR_CLEAR; | |
2332 | } else { | |
2333 | sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK; | |
2334 | sci_port->error_clear = SCIF_ERROR_CLEAR; | |
2335 | } | |
debf9507 | 2336 | |
3ae988d9 LP |
2337 | /* |
2338 | * Make the error mask inclusive of overrun detection, if | |
2339 | * supported. | |
2340 | */ | |
5da0f468 | 2341 | if (sci_port->overrun_reg == SCxSR) { |
afd66db6 | 2342 | sci_port->error_mask |= sci_port->overrun_mask; |
5da0f468 GU |
2343 | sci_port->error_clear &= ~sci_port->overrun_mask; |
2344 | } | |
debf9507 | 2345 | |
ce6738b6 | 2346 | port->type = p->type; |
b6e4a3f1 | 2347 | port->flags = UPF_FIXED_PORT | p->flags; |
61a6976b | 2348 | port->regshift = p->regshift; |
73a19e4c | 2349 | |
ce6738b6 | 2350 | /* |
61a6976b | 2351 | * The UART port needs an IRQ value, so we peg this to the RX IRQ |
ce6738b6 PM |
2352 | * for the multi-IRQ ports, which is where we are primarily |
2353 | * concerned with the shutdown path synchronization. | |
2354 | * | |
2355 | * For the muxed case there's nothing more to do. | |
2356 | */ | |
1fcc91a6 | 2357 | port->irq = sci_port->irqs[SCIx_RXI_IRQ]; |
9cfb5c05 | 2358 | port->irqflags = 0; |
73a19e4c | 2359 | |
61a6976b PM |
2360 | port->serial_in = sci_serial_in; |
2361 | port->serial_out = sci_serial_out; | |
2362 | ||
937bb6e4 GL |
2363 | if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) |
2364 | dev_dbg(port->dev, "DMA tx %d, rx %d\n", | |
2365 | p->dma_slave_tx, p->dma_slave_rx); | |
7ed7e071 | 2366 | |
c7ed1ab3 | 2367 | return 0; |
e108b2ca PM |
2368 | } |
2369 | ||
6dae1421 LP |
2370 | static void sci_cleanup_single(struct sci_port *port) |
2371 | { | |
6dae1421 LP |
2372 | clk_put(port->iclk); |
2373 | clk_put(port->fclk); | |
2374 | ||
2375 | pm_runtime_disable(port->port.dev); | |
2376 | } | |
2377 | ||
1da177e4 | 2378 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
dc8e6f5b MD |
2379 | static void serial_console_putchar(struct uart_port *port, int ch) |
2380 | { | |
2381 | sci_poll_put_char(port, ch); | |
2382 | } | |
2383 | ||
1da177e4 LT |
2384 | /* |
2385 | * Print a string to the serial port trying not to disturb | |
2386 | * any possible real use of the port... | |
2387 | */ | |
2388 | static void serial_console_write(struct console *co, const char *s, | |
2389 | unsigned count) | |
2390 | { | |
906b17dc PM |
2391 | struct sci_port *sci_port = &sci_ports[co->index]; |
2392 | struct uart_port *port = &sci_port->port; | |
40f70c03 SK |
2393 | unsigned short bits, ctrl; |
2394 | unsigned long flags; | |
2395 | int locked = 1; | |
2396 | ||
2397 | local_irq_save(flags); | |
2398 | if (port->sysrq) | |
2399 | locked = 0; | |
2400 | else if (oops_in_progress) | |
2401 | locked = spin_trylock(&port->lock); | |
2402 | else | |
2403 | spin_lock(&port->lock); | |
2404 | ||
2405 | /* first save the SCSCR then disable the interrupts */ | |
2406 | ctrl = serial_port_in(port, SCSCR); | |
2407 | serial_port_out(port, SCSCR, sci_port->cfg->scscr); | |
07d2a1a1 | 2408 | |
501b825d | 2409 | uart_console_write(port, s, count, serial_console_putchar); |
973e5d52 MD |
2410 | |
2411 | /* wait until fifo is empty and last bit has been transmitted */ | |
2412 | bits = SCxSR_TDxE(port) | SCxSR_TEND(port); | |
b12bb29f | 2413 | while ((serial_port_in(port, SCxSR) & bits) != bits) |
973e5d52 | 2414 | cpu_relax(); |
40f70c03 SK |
2415 | |
2416 | /* restore the SCSCR */ | |
2417 | serial_port_out(port, SCSCR, ctrl); | |
2418 | ||
2419 | if (locked) | |
2420 | spin_unlock(&port->lock); | |
2421 | local_irq_restore(flags); | |
1da177e4 LT |
2422 | } |
2423 | ||
9671f099 | 2424 | static int serial_console_setup(struct console *co, char *options) |
1da177e4 | 2425 | { |
dc8e6f5b | 2426 | struct sci_port *sci_port; |
1da177e4 LT |
2427 | struct uart_port *port; |
2428 | int baud = 115200; | |
2429 | int bits = 8; | |
2430 | int parity = 'n'; | |
2431 | int flow = 'n'; | |
2432 | int ret; | |
2433 | ||
e108b2ca | 2434 | /* |
906b17dc | 2435 | * Refuse to handle any bogus ports. |
1da177e4 | 2436 | */ |
906b17dc | 2437 | if (co->index < 0 || co->index >= SCI_NPORTS) |
e108b2ca | 2438 | return -ENODEV; |
e108b2ca | 2439 | |
906b17dc PM |
2440 | sci_port = &sci_ports[co->index]; |
2441 | port = &sci_port->port; | |
2442 | ||
b2267a6b AC |
2443 | /* |
2444 | * Refuse to handle uninitialized ports. | |
2445 | */ | |
2446 | if (!port->ops) | |
2447 | return -ENODEV; | |
2448 | ||
f6e9495d PM |
2449 | ret = sci_remap_port(port); |
2450 | if (unlikely(ret != 0)) | |
2451 | return ret; | |
e108b2ca | 2452 | |
1da177e4 LT |
2453 | if (options) |
2454 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2455 | ||
ab7cfb55 | 2456 | return uart_set_options(port, co, baud, parity, bits, flow); |
1da177e4 LT |
2457 | } |
2458 | ||
2459 | static struct console serial_console = { | |
2460 | .name = "ttySC", | |
906b17dc | 2461 | .device = uart_console_device, |
1da177e4 LT |
2462 | .write = serial_console_write, |
2463 | .setup = serial_console_setup, | |
fa5da2f7 | 2464 | .flags = CON_PRINTBUFFER, |
1da177e4 | 2465 | .index = -1, |
906b17dc | 2466 | .data = &sci_uart_driver, |
1da177e4 LT |
2467 | }; |
2468 | ||
7b6fd3bf MD |
2469 | static struct console early_serial_console = { |
2470 | .name = "early_ttySC", | |
2471 | .write = serial_console_write, | |
2472 | .flags = CON_PRINTBUFFER, | |
906b17dc | 2473 | .index = -1, |
7b6fd3bf | 2474 | }; |
ecdf8a46 | 2475 | |
7b6fd3bf MD |
2476 | static char early_serial_buf[32]; |
2477 | ||
9671f099 | 2478 | static int sci_probe_earlyprintk(struct platform_device *pdev) |
ecdf8a46 | 2479 | { |
574de559 | 2480 | struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); |
ecdf8a46 PM |
2481 | |
2482 | if (early_serial_console.data) | |
2483 | return -EEXIST; | |
2484 | ||
2485 | early_serial_console.index = pdev->id; | |
ecdf8a46 | 2486 | |
1fcc91a6 | 2487 | sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); |
ecdf8a46 PM |
2488 | |
2489 | serial_console_setup(&early_serial_console, early_serial_buf); | |
2490 | ||
2491 | if (!strstr(early_serial_buf, "keep")) | |
2492 | early_serial_console.flags |= CON_BOOT; | |
2493 | ||
2494 | register_console(&early_serial_console); | |
2495 | return 0; | |
2496 | } | |
6a8c9799 NI |
2497 | |
2498 | #define SCI_CONSOLE (&serial_console) | |
2499 | ||
ecdf8a46 | 2500 | #else |
9671f099 | 2501 | static inline int sci_probe_earlyprintk(struct platform_device *pdev) |
ecdf8a46 PM |
2502 | { |
2503 | return -EINVAL; | |
2504 | } | |
1da177e4 | 2505 | |
6a8c9799 NI |
2506 | #define SCI_CONSOLE NULL |
2507 | ||
2508 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ | |
1da177e4 | 2509 | |
6c13d5d2 | 2510 | static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; |
1da177e4 LT |
2511 | |
2512 | static struct uart_driver sci_uart_driver = { | |
2513 | .owner = THIS_MODULE, | |
2514 | .driver_name = "sci", | |
1da177e4 LT |
2515 | .dev_name = "ttySC", |
2516 | .major = SCI_MAJOR, | |
2517 | .minor = SCI_MINOR_START, | |
e108b2ca | 2518 | .nr = SCI_NPORTS, |
1da177e4 LT |
2519 | .cons = SCI_CONSOLE, |
2520 | }; | |
2521 | ||
54507f6e | 2522 | static int sci_remove(struct platform_device *dev) |
e552de24 | 2523 | { |
d535a230 | 2524 | struct sci_port *port = platform_get_drvdata(dev); |
e552de24 | 2525 | |
d535a230 PM |
2526 | cpufreq_unregister_notifier(&port->freq_transition, |
2527 | CPUFREQ_TRANSITION_NOTIFIER); | |
e552de24 | 2528 | |
d535a230 PM |
2529 | uart_remove_one_port(&sci_uart_driver, &port->port); |
2530 | ||
6dae1421 | 2531 | sci_cleanup_single(port); |
e552de24 | 2532 | |
e552de24 MD |
2533 | return 0; |
2534 | } | |
2535 | ||
20bdcab8 BH |
2536 | struct sci_port_info { |
2537 | unsigned int type; | |
2538 | unsigned int regtype; | |
2539 | }; | |
2540 | ||
2541 | static const struct of_device_id of_sci_match[] = { | |
2542 | { | |
2543 | .compatible = "renesas,scif", | |
ff43da00 | 2544 | .data = &(const struct sci_port_info) { |
20bdcab8 BH |
2545 | .type = PORT_SCIF, |
2546 | .regtype = SCIx_SH4_SCIF_REGTYPE, | |
2547 | }, | |
2548 | }, { | |
2549 | .compatible = "renesas,scifa", | |
ff43da00 | 2550 | .data = &(const struct sci_port_info) { |
20bdcab8 BH |
2551 | .type = PORT_SCIFA, |
2552 | .regtype = SCIx_SCIFA_REGTYPE, | |
2553 | }, | |
2554 | }, { | |
2555 | .compatible = "renesas,scifb", | |
ff43da00 | 2556 | .data = &(const struct sci_port_info) { |
20bdcab8 BH |
2557 | .type = PORT_SCIFB, |
2558 | .regtype = SCIx_SCIFB_REGTYPE, | |
2559 | }, | |
2560 | }, { | |
2561 | .compatible = "renesas,hscif", | |
ff43da00 | 2562 | .data = &(const struct sci_port_info) { |
20bdcab8 BH |
2563 | .type = PORT_HSCIF, |
2564 | .regtype = SCIx_HSCIF_REGTYPE, | |
2565 | }, | |
e1d0be61 YS |
2566 | }, { |
2567 | .compatible = "renesas,sci", | |
2568 | .data = &(const struct sci_port_info) { | |
2569 | .type = PORT_SCI, | |
2570 | .regtype = SCIx_SCI_REGTYPE, | |
2571 | }, | |
20bdcab8 BH |
2572 | }, { |
2573 | /* Terminator */ | |
2574 | }, | |
2575 | }; | |
2576 | MODULE_DEVICE_TABLE(of, of_sci_match); | |
2577 | ||
2578 | static struct plat_sci_port * | |
2579 | sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id) | |
2580 | { | |
2581 | struct device_node *np = pdev->dev.of_node; | |
2582 | const struct of_device_id *match; | |
2583 | const struct sci_port_info *info; | |
2584 | struct plat_sci_port *p; | |
2585 | int id; | |
2586 | ||
2587 | if (!IS_ENABLED(CONFIG_OF) || !np) | |
2588 | return NULL; | |
2589 | ||
2590 | match = of_match_node(of_sci_match, pdev->dev.of_node); | |
2591 | if (!match) | |
2592 | return NULL; | |
2593 | ||
2594 | info = match->data; | |
2595 | ||
2596 | p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); | |
4205463c | 2597 | if (!p) |
20bdcab8 | 2598 | return NULL; |
20bdcab8 BH |
2599 | |
2600 | /* Get the line number for the aliases node. */ | |
2601 | id = of_alias_get_id(np, "serial"); | |
2602 | if (id < 0) { | |
2603 | dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); | |
2604 | return NULL; | |
2605 | } | |
2606 | ||
2607 | *dev_id = id; | |
2608 | ||
2609 | p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; | |
2610 | p->type = info->type; | |
2611 | p->regtype = info->regtype; | |
2612 | p->scscr = SCSCR_RE | SCSCR_TE; | |
2613 | ||
2614 | return p; | |
2615 | } | |
2616 | ||
9671f099 | 2617 | static int sci_probe_single(struct platform_device *dev, |
0ee70712 MD |
2618 | unsigned int index, |
2619 | struct plat_sci_port *p, | |
2620 | struct sci_port *sciport) | |
2621 | { | |
0ee70712 MD |
2622 | int ret; |
2623 | ||
2624 | /* Sanity check */ | |
2625 | if (unlikely(index >= SCI_NPORTS)) { | |
9b971cd2 | 2626 | dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", |
0ee70712 | 2627 | index+1, SCI_NPORTS); |
9b971cd2 | 2628 | dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); |
b6c5ef6f | 2629 | return -EINVAL; |
0ee70712 MD |
2630 | } |
2631 | ||
1fcc91a6 | 2632 | ret = sci_init_single(dev, sciport, index, p, false); |
c7ed1ab3 PM |
2633 | if (ret) |
2634 | return ret; | |
0ee70712 | 2635 | |
6dae1421 LP |
2636 | ret = uart_add_one_port(&sci_uart_driver, &sciport->port); |
2637 | if (ret) { | |
2638 | sci_cleanup_single(sciport); | |
2639 | return ret; | |
2640 | } | |
2641 | ||
2642 | return 0; | |
0ee70712 MD |
2643 | } |
2644 | ||
9671f099 | 2645 | static int sci_probe(struct platform_device *dev) |
1da177e4 | 2646 | { |
20bdcab8 BH |
2647 | struct plat_sci_port *p; |
2648 | struct sci_port *sp; | |
2649 | unsigned int dev_id; | |
ecdf8a46 | 2650 | int ret; |
d535a230 | 2651 | |
ecdf8a46 PM |
2652 | /* |
2653 | * If we've come here via earlyprintk initialization, head off to | |
2654 | * the special early probe. We don't have sufficient device state | |
2655 | * to make it beyond this yet. | |
2656 | */ | |
2657 | if (is_early_platform_device(dev)) | |
2658 | return sci_probe_earlyprintk(dev); | |
7b6fd3bf | 2659 | |
20bdcab8 BH |
2660 | if (dev->dev.of_node) { |
2661 | p = sci_parse_dt(dev, &dev_id); | |
2662 | if (p == NULL) | |
2663 | return -EINVAL; | |
2664 | } else { | |
2665 | p = dev->dev.platform_data; | |
2666 | if (p == NULL) { | |
2667 | dev_err(&dev->dev, "no platform data supplied\n"); | |
2668 | return -EINVAL; | |
2669 | } | |
2670 | ||
2671 | dev_id = dev->id; | |
2672 | } | |
2673 | ||
2674 | sp = &sci_ports[dev_id]; | |
d535a230 | 2675 | platform_set_drvdata(dev, sp); |
e552de24 | 2676 | |
20bdcab8 | 2677 | ret = sci_probe_single(dev, dev_id, p, sp); |
d535a230 | 2678 | if (ret) |
6dae1421 | 2679 | return ret; |
e552de24 | 2680 | |
d535a230 | 2681 | sp->freq_transition.notifier_call = sci_notifier; |
1da177e4 | 2682 | |
d535a230 PM |
2683 | ret = cpufreq_register_notifier(&sp->freq_transition, |
2684 | CPUFREQ_TRANSITION_NOTIFIER); | |
6dae1421 | 2685 | if (unlikely(ret < 0)) { |
bf13c9a8 | 2686 | uart_remove_one_port(&sci_uart_driver, &sp->port); |
6dae1421 LP |
2687 | sci_cleanup_single(sp); |
2688 | return ret; | |
2689 | } | |
1da177e4 LT |
2690 | |
2691 | #ifdef CONFIG_SH_STANDARD_BIOS | |
2692 | sh_bios_gdb_detach(); | |
2693 | #endif | |
2694 | ||
e108b2ca | 2695 | return 0; |
1da177e4 LT |
2696 | } |
2697 | ||
cb876341 | 2698 | static __maybe_unused int sci_suspend(struct device *dev) |
1da177e4 | 2699 | { |
d535a230 | 2700 | struct sci_port *sport = dev_get_drvdata(dev); |
e108b2ca | 2701 | |
d535a230 PM |
2702 | if (sport) |
2703 | uart_suspend_port(&sci_uart_driver, &sport->port); | |
1da177e4 | 2704 | |
e108b2ca PM |
2705 | return 0; |
2706 | } | |
1da177e4 | 2707 | |
cb876341 | 2708 | static __maybe_unused int sci_resume(struct device *dev) |
e108b2ca | 2709 | { |
d535a230 | 2710 | struct sci_port *sport = dev_get_drvdata(dev); |
e108b2ca | 2711 | |
d535a230 PM |
2712 | if (sport) |
2713 | uart_resume_port(&sci_uart_driver, &sport->port); | |
e108b2ca PM |
2714 | |
2715 | return 0; | |
2716 | } | |
2717 | ||
cb876341 | 2718 | static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); |
6daa79b3 | 2719 | |
e108b2ca PM |
2720 | static struct platform_driver sci_driver = { |
2721 | .probe = sci_probe, | |
b9e39c89 | 2722 | .remove = sci_remove, |
e108b2ca PM |
2723 | .driver = { |
2724 | .name = "sh-sci", | |
6daa79b3 | 2725 | .pm = &sci_dev_pm_ops, |
20bdcab8 | 2726 | .of_match_table = of_match_ptr(of_sci_match), |
e108b2ca PM |
2727 | }, |
2728 | }; | |
2729 | ||
2730 | static int __init sci_init(void) | |
2731 | { | |
2732 | int ret; | |
2733 | ||
6c13d5d2 | 2734 | pr_info("%s\n", banner); |
e108b2ca | 2735 | |
e108b2ca PM |
2736 | ret = uart_register_driver(&sci_uart_driver); |
2737 | if (likely(ret == 0)) { | |
2738 | ret = platform_driver_register(&sci_driver); | |
2739 | if (unlikely(ret)) | |
2740 | uart_unregister_driver(&sci_uart_driver); | |
2741 | } | |
2742 | ||
2743 | return ret; | |
2744 | } | |
2745 | ||
2746 | static void __exit sci_exit(void) | |
2747 | { | |
2748 | platform_driver_unregister(&sci_driver); | |
1da177e4 LT |
2749 | uart_unregister_driver(&sci_uart_driver); |
2750 | } | |
2751 | ||
7b6fd3bf MD |
2752 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
2753 | early_platform_init_buffer("earlyprintk", &sci_driver, | |
2754 | early_serial_buf, ARRAY_SIZE(early_serial_buf)); | |
2755 | #endif | |
1da177e4 LT |
2756 | module_init(sci_init); |
2757 | module_exit(sci_exit); | |
2758 | ||
e108b2ca | 2759 | MODULE_LICENSE("GPL"); |
e169c139 | 2760 | MODULE_ALIAS("platform:sh-sci"); |
7f405f9c | 2761 | MODULE_AUTHOR("Paul Mundt"); |
f303b364 | 2762 | MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); |