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serial: 8250_mid: Enable HSU on Intel Cedar Fork PCH
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
f4998e55 5 * Copyright (C) 2015 Glider bvba
3ea6bc3d 6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 15 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
0b3d4ef6
PM		 21#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
1da177e4
LT		 24
25#undef DEBUG
26
8fb9631c
LP		 27#include <linux/clk.h>
28#include <linux/console.h>
29#include <linux/ctype.h>
30#include <linux/cpufreq.h>
31#include <linux/delay.h>
32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/err.h>
1da177e4 35#include <linux/errno.h>
8fb9631c 36#include <linux/init.h>
1da177e4 37#include <linux/interrupt.h>
1da177e4 38#include <linux/ioport.h>
8fb9631c
LP		 39#include <linux/major.h>
40#include <linux/module.h>
1da177e4 41#include <linux/mm.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
f907c9ea 60#include "serial_mctrl_gpio.h"
1da177e4
LT		 61#include "sh-sci.h"
62
89b5c1ab
LP		 63/* Offsets into the sci_port->irqs array */
64enum {
65 SCIx_ERI_IRQ,
66 SCIx_RXI_IRQ,
67 SCIx_TXI_IRQ,
68 SCIx_BRI_IRQ,
69 SCIx_NR_IRQS,
70
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72};
73
74#define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79
f4998e55
GU		 80enum SCI_CLKS {
81 SCI_FCK, /* Functional Clock */
6af27bf2 82 SCI_SCK, /* Optional External Clock */
1270f865
GU		 83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
f4998e55
GU		 85 SCI_NUM_CLKS
86};
87
69eee8e9
GU		 88/* Bit x set means sampling rate x + 1 is supported */
89#define SCI_SR(x) BIT((x) - 1)
90#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
91
92a05748
GU		 92#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
95
69eee8e9
GU		 96#define min_sr(_port) ffs((_port)->sampling_rate_mask)
97#define max_sr(_port) fls((_port)->sampling_rate_mask)
98
99/* Iterate over all supported sampling rates, from high to low */
100#define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
103
e095ee6b
LP		 104struct plat_sci_reg {
105 u8 offset, size;
106};
107
108struct sci_port_params {
109 const struct plat_sci_reg regs[SCIx_NR_REGS];
b2f20ed9
LP		 110 unsigned int fifosize;
111 unsigned int overrun_reg;
112 unsigned int overrun_mask;
113 unsigned int sampling_rate_mask;
114 unsigned int error_mask;
115 unsigned int error_clear;
e095ee6b
LP		 116};
117
e108b2ca
PM		 118struct sci_port {
119 struct uart_port port;
120
ce6738b6 121 /* Platform configuration */
e095ee6b 122 const struct sci_port_params *params;
daf5a895 123 const struct plat_sci_port *cfg;
69eee8e9 124 unsigned int sampling_rate_mask;
e4d6f911 125 resource_size_t reg_size;
f907c9ea 126 struct mctrl_gpios *gpios;
e108b2ca 127
f4998e55
GU		 128 /* Clocks */
129 struct clk *clks[SCI_NUM_CLKS];
130 unsigned long clk_rates[SCI_NUM_CLKS];
edad1f20 131
1fcc91a6 132 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 133 char *irqstr[SCIx_NR_IRQS];
134
73a19e4c
GL		 135 struct dma_chan *chan_tx;
136 struct dma_chan *chan_rx;
f43dc23d 137
73a19e4c 138#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 139 dma_cookie_t cookie_tx;
140 dma_cookie_t cookie_rx[2];
141 dma_cookie_t active_rx;
79904420
GU		 142 dma_addr_t tx_dma_addr;
143 unsigned int tx_dma_len;
73a19e4c 144 struct scatterlist sg_rx[2];
7b39d901 145 void *rx_buf[2];
73a19e4c 146 size_t buf_len_rx;
73a19e4c 147 struct work_struct work_tx;
73a19e4c 148 struct timer_list rx_timer;
3089f381 149 unsigned int rx_timeout;
73a19e4c 150#endif
03940376 151 unsigned int rx_frame;
18e8cf15 152 int rx_trigger;
03940376
UH		 153 struct timer_list rx_fifo_timer;
154 int rx_fifo_timeout;
fa2abb03 155 u16 hscif_tot;
33f50ffc 156
97ed9790 157 bool has_rtscts;
33f50ffc 158 bool autorts;
e108b2ca
PM		 159};
160
e108b2ca 161#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 162
e108b2ca
PM		 163static struct sci_port sci_ports[SCI_NPORTS];
164static struct uart_driver sci_uart_driver;
1da177e4 165
e7c98dc7
MT		 166static inline struct sci_port *
167to_sci_port(struct uart_port *uart)
168{
169 return container_of(uart, struct sci_port, port);
170}
171
e095ee6b 172static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
61a6976b
PM		 173 /*
174 * Common SCI definitions, dependent on the port's regshift
175 * value.
176 */
177 [SCIx_SCI_REGTYPE] = {
e095ee6b
LP		 178 .regs = {
179 [SCSMR] = { 0x00, 8 },
180 [SCBRR] = { 0x01, 8 },
181 [SCSCR] = { 0x02, 8 },
182 [SCxTDR] = { 0x03, 8 },
183 [SCxSR] = { 0x04, 8 },
184 [SCxRDR] = { 0x05, 8 },
185 },
b2f20ed9
LP		 186 .fifosize = 1,
187 .overrun_reg = SCxSR,
188 .overrun_mask = SCI_ORER,
189 .sampling_rate_mask = SCI_SR(32),
190 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
191 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 192 },
193
194 /*
a752ba18 195 * Common definitions for legacy IrDA ports.
61a6976b
PM		 196 */
197 [SCIx_IRDA_REGTYPE] = {
e095ee6b
LP		 198 .regs = {
199 [SCSMR] = { 0x00, 8 },
200 [SCBRR] = { 0x02, 8 },
201 [SCSCR] = { 0x04, 8 },
202 [SCxTDR] = { 0x06, 8 },
203 [SCxSR] = { 0x08, 16 },
204 [SCxRDR] = { 0x0a, 8 },
205 [SCFCR] = { 0x0c, 8 },
206 [SCFDR] = { 0x0e, 16 },
207 },
b2f20ed9
LP		 208 .fifosize = 1,
209 .overrun_reg = SCxSR,
210 .overrun_mask = SCI_ORER,
211 .sampling_rate_mask = SCI_SR(32),
212 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
213 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 214 },
215
216 /*
217 * Common SCIFA definitions.
218 */
219 [SCIx_SCIFA_REGTYPE] = {
e095ee6b
LP		 220 .regs = {
221 [SCSMR] = { 0x00, 16 },
222 [SCBRR] = { 0x04, 8 },
223 [SCSCR] = { 0x08, 16 },
224 [SCxTDR] = { 0x20, 8 },
225 [SCxSR] = { 0x14, 16 },
226 [SCxRDR] = { 0x24, 8 },
227 [SCFCR] = { 0x18, 16 },
228 [SCFDR] = { 0x1c, 16 },
229 [SCPCR] = { 0x30, 16 },
230 [SCPDR] = { 0x34, 16 },
231 },
b2f20ed9
LP		 232 .fifosize = 64,
233 .overrun_reg = SCxSR,
234 .overrun_mask = SCIFA_ORER,
235 .sampling_rate_mask = SCI_SR_SCIFAB,
236 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
237 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 238 },
239
240 /*
241 * Common SCIFB definitions.
242 */
243 [SCIx_SCIFB_REGTYPE] = {
e095ee6b
LP		 244 .regs = {
245 [SCSMR] = { 0x00, 16 },
246 [SCBRR] = { 0x04, 8 },
247 [SCSCR] = { 0x08, 16 },
248 [SCxTDR] = { 0x40, 8 },
249 [SCxSR] = { 0x14, 16 },
250 [SCxRDR] = { 0x60, 8 },
251 [SCFCR] = { 0x18, 16 },
252 [SCTFDR] = { 0x38, 16 },
253 [SCRFDR] = { 0x3c, 16 },
254 [SCPCR] = { 0x30, 16 },
255 [SCPDR] = { 0x34, 16 },
256 },
b2f20ed9
LP		 257 .fifosize = 256,
258 .overrun_reg = SCxSR,
259 .overrun_mask = SCIFA_ORER,
260 .sampling_rate_mask = SCI_SR_SCIFAB,
261 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
262 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 263 },
264
3af1f8a4
PE		 265 /*
266 * Common SH-2(A) SCIF definitions for ports with FIFO data
267 * count registers.
268 */
269 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 270 .regs = {
271 [SCSMR] = { 0x00, 16 },
272 [SCBRR] = { 0x04, 8 },
273 [SCSCR] = { 0x08, 16 },
274 [SCxTDR] = { 0x0c, 8 },
275 [SCxSR] = { 0x10, 16 },
276 [SCxRDR] = { 0x14, 8 },
277 [SCFCR] = { 0x18, 16 },
278 [SCFDR] = { 0x1c, 16 },
279 [SCSPTR] = { 0x20, 16 },
280 [SCLSR] = { 0x24, 16 },
281 },
b2f20ed9
LP		 282 .fifosize = 16,
283 .overrun_reg = SCLSR,
284 .overrun_mask = SCLSR_ORER,
285 .sampling_rate_mask = SCI_SR(32),
286 .error_mask = SCIF_DEFAULT_ERROR_MASK,
287 .error_clear = SCIF_ERROR_CLEAR,
3af1f8a4
PE		 288 },
289
61a6976b
PM		 290 /*
291 * Common SH-3 SCIF definitions.
292 */
293 [SCIx_SH3_SCIF_REGTYPE] = {
e095ee6b
LP		 294 .regs = {
295 [SCSMR] = { 0x00, 8 },
296 [SCBRR] = { 0x02, 8 },
297 [SCSCR] = { 0x04, 8 },
298 [SCxTDR] = { 0x06, 8 },
299 [SCxSR] = { 0x08, 16 },
300 [SCxRDR] = { 0x0a, 8 },
301 [SCFCR] = { 0x0c, 8 },
302 [SCFDR] = { 0x0e, 16 },
303 },
b2f20ed9
LP		 304 .fifosize = 16,
305 .overrun_reg = SCLSR,
306 .overrun_mask = SCLSR_ORER,
307 .sampling_rate_mask = SCI_SR(32),
308 .error_mask = SCIF_DEFAULT_ERROR_MASK,
309 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 310 },
311
312 /*
313 * Common SH-4(A) SCIF(B) definitions.
314 */
315 [SCIx_SH4_SCIF_REGTYPE] = {
e095ee6b
LP		 316 .regs = {
317 [SCSMR] = { 0x00, 16 },
318 [SCBRR] = { 0x04, 8 },
319 [SCSCR] = { 0x08, 16 },
320 [SCxTDR] = { 0x0c, 8 },
321 [SCxSR] = { 0x10, 16 },
322 [SCxRDR] = { 0x14, 8 },
323 [SCFCR] = { 0x18, 16 },
324 [SCFDR] = { 0x1c, 16 },
325 [SCSPTR] = { 0x20, 16 },
326 [SCLSR] = { 0x24, 16 },
327 },
b2f20ed9
LP		 328 .fifosize = 16,
329 .overrun_reg = SCLSR,
330 .overrun_mask = SCLSR_ORER,
331 .sampling_rate_mask = SCI_SR(32),
332 .error_mask = SCIF_DEFAULT_ERROR_MASK,
333 .error_clear = SCIF_ERROR_CLEAR,
b8bbd6b2
GU		 334 },
335
336 /*
337 * Common SCIF definitions for ports with a Baud Rate Generator for
338 * External Clock (BRG).
339 */
340 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
e095ee6b
LP		 341 .regs = {
342 [SCSMR] = { 0x00, 16 },
343 [SCBRR] = { 0x04, 8 },
344 [SCSCR] = { 0x08, 16 },
345 [SCxTDR] = { 0x0c, 8 },
346 [SCxSR] = { 0x10, 16 },
347 [SCxRDR] = { 0x14, 8 },
348 [SCFCR] = { 0x18, 16 },
349 [SCFDR] = { 0x1c, 16 },
350 [SCSPTR] = { 0x20, 16 },
351 [SCLSR] = { 0x24, 16 },
352 [SCDL] = { 0x30, 16 },
353 [SCCKS] = { 0x34, 16 },
354 },
b2f20ed9
LP		 355 .fifosize = 16,
356 .overrun_reg = SCLSR,
357 .overrun_mask = SCLSR_ORER,
358 .sampling_rate_mask = SCI_SR(32),
359 .error_mask = SCIF_DEFAULT_ERROR_MASK,
360 .error_clear = SCIF_ERROR_CLEAR,
f303b364
UH		 361 },
362
363 /*
364 * Common HSCIF definitions.
365 */
366 [SCIx_HSCIF_REGTYPE] = {
e095ee6b
LP		 367 .regs = {
368 [SCSMR] = { 0x00, 16 },
369 [SCBRR] = { 0x04, 8 },
370 [SCSCR] = { 0x08, 16 },
371 [SCxTDR] = { 0x0c, 8 },
372 [SCxSR] = { 0x10, 16 },
373 [SCxRDR] = { 0x14, 8 },
374 [SCFCR] = { 0x18, 16 },
375 [SCFDR] = { 0x1c, 16 },
376 [SCSPTR] = { 0x20, 16 },
377 [SCLSR] = { 0x24, 16 },
378 [HSSRR] = { 0x40, 16 },
379 [SCDL] = { 0x30, 16 },
380 [SCCKS] = { 0x34, 16 },
54e14ae2
UH		 381 [HSRTRGR] = { 0x54, 16 },
382 [HSTTRGR] = { 0x58, 16 },
e095ee6b 383 },
b2f20ed9
LP		 384 .fifosize = 128,
385 .overrun_reg = SCLSR,
386 .overrun_mask = SCLSR_ORER,
387 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
388 .error_mask = SCIF_DEFAULT_ERROR_MASK,
389 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 390 },
391
392 /*
393 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
394 * register.
395 */
396 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
e095ee6b
LP		 397 .regs = {
398 [SCSMR] = { 0x00, 16 },
399 [SCBRR] = { 0x04, 8 },
400 [SCSCR] = { 0x08, 16 },
401 [SCxTDR] = { 0x0c, 8 },
402 [SCxSR] = { 0x10, 16 },
403 [SCxRDR] = { 0x14, 8 },
404 [SCFCR] = { 0x18, 16 },
405 [SCFDR] = { 0x1c, 16 },
406 [SCLSR] = { 0x24, 16 },
407 },
b2f20ed9
LP		 408 .fifosize = 16,
409 .overrun_reg = SCLSR,
410 .overrun_mask = SCLSR_ORER,
411 .sampling_rate_mask = SCI_SR(32),
412 .error_mask = SCIF_DEFAULT_ERROR_MASK,
413 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 414 },
415
416 /*
417 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
418 * count registers.
419 */
420 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 421 .regs = {
422 [SCSMR] = { 0x00, 16 },
423 [SCBRR] = { 0x04, 8 },
424 [SCSCR] = { 0x08, 16 },
425 [SCxTDR] = { 0x0c, 8 },
426 [SCxSR] = { 0x10, 16 },
427 [SCxRDR] = { 0x14, 8 },
428 [SCFCR] = { 0x18, 16 },
429 [SCFDR] = { 0x1c, 16 },
430 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
431 [SCRFDR] = { 0x20, 16 },
432 [SCSPTR] = { 0x24, 16 },
433 [SCLSR] = { 0x28, 16 },
434 },
b2f20ed9
LP		 435 .fifosize = 16,
436 .overrun_reg = SCLSR,
437 .overrun_mask = SCLSR_ORER,
438 .sampling_rate_mask = SCI_SR(32),
439 .error_mask = SCIF_DEFAULT_ERROR_MASK,
440 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 441 },
442
443 /*
444 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
445 * registers.
446 */
447 [SCIx_SH7705_SCIF_REGTYPE] = {
e095ee6b
LP		 448 .regs = {
449 [SCSMR] = { 0x00, 16 },
450 [SCBRR] = { 0x04, 8 },
451 [SCSCR] = { 0x08, 16 },
452 [SCxTDR] = { 0x20, 8 },
453 [SCxSR] = { 0x14, 16 },
454 [SCxRDR] = { 0x24, 8 },
455 [SCFCR] = { 0x18, 16 },
456 [SCFDR] = { 0x1c, 16 },
457 },
18e8cf15 458 .fifosize = 64,
b2f20ed9
LP		 459 .overrun_reg = SCxSR,
460 .overrun_mask = SCIFA_ORER,
461 .sampling_rate_mask = SCI_SR(16),
462 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
463 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 464 },
465};
466
e095ee6b 467#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
72b294cf 468
61a6976b
PM		 469/*
470 * The "offset" here is rather misleading, in that it refers to an enum
471 * value relative to the port mapping rather than the fixed offset
472 * itself, which needs to be manually retrieved from the platform's
473 * register map for the given port.
474 */
475static unsigned int sci_serial_in(struct uart_port *p, int offset)
476{
d3184e68 477 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 478
479 if (reg->size == 8)
480 return ioread8(p->membase + (reg->offset << p->regshift));
481 else if (reg->size == 16)
482 return ioread16(p->membase + (reg->offset << p->regshift));
483 else
484 WARN(1, "Invalid register access\n");
485
486 return 0;
487}
488
489static void sci_serial_out(struct uart_port *p, int offset, int value)
490{
d3184e68 491 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 492
493 if (reg->size == 8)
494 iowrite8(value, p->membase + (reg->offset << p->regshift));
495 else if (reg->size == 16)
496 iowrite16(value, p->membase + (reg->offset << p->regshift));
497 else
498 WARN(1, "Invalid register access\n");
499}
500
23241d43
PM		 501static void sci_port_enable(struct sci_port *sci_port)
502{
f4998e55
GU		 503 unsigned int i;
504
23241d43
PM		 505 if (!sci_port->port.dev)
506 return;
507
508 pm_runtime_get_sync(sci_port->port.dev);
509
f4998e55
GU		 510 for (i = 0; i < SCI_NUM_CLKS; i++) {
511 clk_prepare_enable(sci_port->clks[i]);
512 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
513 }
514 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
23241d43
PM		 515}
516
517static void sci_port_disable(struct sci_port *sci_port)
518{
f4998e55
GU		 519 unsigned int i;
520
23241d43
PM		 521 if (!sci_port->port.dev)
522 return;
523
f4998e55
GU		 524 for (i = SCI_NUM_CLKS; i-- > 0; )
525 clk_disable_unprepare(sci_port->clks[i]);
23241d43
PM		 526
527 pm_runtime_put_sync(sci_port->port.dev);
528}
529
e1910fcd
GU		 530static inline unsigned long port_rx_irq_mask(struct uart_port *port)
531{
532 /*
533 * Not all ports (such as SCIFA) will support REIE. Rather than
534 * special-casing the port type, we check the port initialization
535 * IRQ enable mask to see whether the IRQ is desired at all. If
536 * it's unset, it's logically inferred that there's no point in
537 * testing for it.
538 */
539 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
540}
541
542static void sci_start_tx(struct uart_port *port)
543{
544 struct sci_port *s = to_sci_port(port);
545 unsigned short ctrl;
546
547#ifdef CONFIG_SERIAL_SH_SCI_DMA
548 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
549 u16 new, scr = serial_port_in(port, SCSCR);
550 if (s->chan_tx)
551 new = scr | SCSCR_TDRQE;
552 else
553 new = scr & ~SCSCR_TDRQE;
554 if (new != scr)
555 serial_port_out(port, SCSCR, new);
556 }
557
558 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
559 dma_submit_error(s->cookie_tx)) {
560 s->cookie_tx = 0;
561 schedule_work(&s->work_tx);
562 }
563#endif
564
565 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
566 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
567 ctrl = serial_port_in(port, SCSCR);
568 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
569 }
570}
571
572static void sci_stop_tx(struct uart_port *port)
573{
574 unsigned short ctrl;
575
576 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
577 ctrl = serial_port_in(port, SCSCR);
578
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
580 ctrl &= ~SCSCR_TDRQE;
581
582 ctrl &= ~SCSCR_TIE;
583
584 serial_port_out(port, SCSCR, ctrl);
585}
586
587static void sci_start_rx(struct uart_port *port)
588{
589 unsigned short ctrl;
590
591 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
592
593 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
594 ctrl &= ~SCSCR_RDRQE;
595
596 serial_port_out(port, SCSCR, ctrl);
597}
598
599static void sci_stop_rx(struct uart_port *port)
600{
601 unsigned short ctrl;
602
603 ctrl = serial_port_in(port, SCSCR);
604
605 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
606 ctrl &= ~SCSCR_RDRQE;
607
608 ctrl &= ~port_rx_irq_mask(port);
609
610 serial_port_out(port, SCSCR, ctrl);
611}
612
a1b5b43f
GU		 613static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
614{
615 if (port->type == PORT_SCI) {
616 /* Just store the mask */
617 serial_port_out(port, SCxSR, mask);
b2f20ed9 618 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
a1b5b43f
GU		 619 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
620 /* Only clear the status bits we want to clear */
621 serial_port_out(port, SCxSR,
622 serial_port_in(port, SCxSR) & mask);
623 } else {
624 /* Store the mask, clear parity/framing errors */
625 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
626 }
627}
628
0b0cced1
YS		 629#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
630 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
1f6fd5c9
PM		 631
632#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 633static int sci_poll_get_char(struct uart_port *port)
1da177e4 634{
1da177e4
LT		 635 unsigned short status;
636 int c;
637
e108b2ca 638 do {
b12bb29f 639 status = serial_port_in(port, SCxSR);
1da177e4 640 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 641 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 642 continue;
643 }
3f255eb3
JW		 644 break;
645 } while (1);
646
647 if (!(status & SCxSR_RDxF(port)))
648 return NO_POLL_CHAR;
07d2a1a1 649
b12bb29f 650 c = serial_port_in(port, SCxRDR);
07d2a1a1 651
e7c98dc7 652 /* Dummy read */
b12bb29f 653 serial_port_in(port, SCxSR);
a1b5b43f 654 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 655
656 return c;
657}
1f6fd5c9 658#endif
1da177e4 659
07d2a1a1 660static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 661{
1da177e4
LT		 662 unsigned short status;
663
1da177e4 664 do {
b12bb29f 665 status = serial_port_in(port, SCxSR);
1da177e4
LT		 666 } while (!(status & SCxSR_TDxE(port)));
667
b12bb29f 668 serial_port_out(port, SCxTDR, c);
a1b5b43f 669 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 670}
0b0cced1
YS		 671#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
672 CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 673
61a6976b 674static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 675{
61a6976b 676 struct sci_port *s = to_sci_port(port);
1da177e4 677
61a6976b
PM		 678 /*
679 * Use port-specific handler if provided.
680 */
681 if (s->cfg->ops && s->cfg->ops->init_pins) {
682 s->cfg->ops->init_pins(port, cflag);
683 return;
1da177e4 684 }
41504c39 685
e9d7a45a 686 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
cfa6eb23 687 u16 data = serial_port_in(port, SCPDR);
e9d7a45a
GU		 688 u16 ctrl = serial_port_in(port, SCPCR);
689
690 /* Enable RXD and TXD pin functions */
691 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
97ed9790 692 if (to_sci_port(port)->has_rtscts) {
cfa6eb23
GU		 693 /* RTS# is output, active low, unless autorts */
694 if (!(port->mctrl & TIOCM_RTS)) {
695 ctrl |= SCPCR_RTSC;
696 data |= SCPDR_RTSD;
697 } else if (!s->autorts) {
698 ctrl |= SCPCR_RTSC;
699 data &= ~SCPDR_RTSD;
700 } else {
701 /* Enable RTS# pin function */
702 ctrl &= ~SCPCR_RTSC;
703 }
e9d7a45a
GU		 704 /* Enable CTS# pin function */
705 ctrl &= ~SCPCR_CTSC;
706 }
cfa6eb23 707 serial_port_out(port, SCPDR, data);
e9d7a45a
GU		 708 serial_port_out(port, SCPCR, ctrl);
709 } else if (sci_getreg(port, SCSPTR)->size) {
d2b9775d
GU		 710 u16 status = serial_port_in(port, SCSPTR);
711
cfa6eb23
GU		 712 /* RTS# is always output; and active low, unless autorts */
713 status |= SCSPTR_RTSIO;
714 if (!(port->mctrl & TIOCM_RTS))
715 status |= SCSPTR_RTSDT;
716 else if (!s->autorts)
717 status &= ~SCSPTR_RTSDT;
d2b9775d
GU		 718 /* CTS# and SCK are inputs */
719 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
720 serial_port_out(port, SCSPTR, status);
faf02f8f 721 }
d5701647 722}
e108b2ca 723
72b294cf 724static int sci_txfill(struct uart_port *port)
e108b2ca 725{
b2f20ed9
LP		 726 struct sci_port *s = to_sci_port(port);
727 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 728 const struct plat_sci_reg *reg;
e108b2ca 729
72b294cf
PM		 730 reg = sci_getreg(port, SCTFDR);
731 if (reg->size)
b2f20ed9 732 return serial_port_in(port, SCTFDR) & fifo_mask;
c63847a3 733
72b294cf
PM		 734 reg = sci_getreg(port, SCFDR);
735 if (reg->size)
b12bb29f 736 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 737
b12bb29f 738 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 739}
740
73a19e4c
GL		 741static int sci_txroom(struct uart_port *port)
742{
72b294cf 743 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 744}
745
746static int sci_rxfill(struct uart_port *port)
e108b2ca 747{
b2f20ed9
LP		 748 struct sci_port *s = to_sci_port(port);
749 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 750 const struct plat_sci_reg *reg;
72b294cf
PM		 751
752 reg = sci_getreg(port, SCRFDR);
753 if (reg->size)
b2f20ed9 754 return serial_port_in(port, SCRFDR) & fifo_mask;
72b294cf
PM		 755
756 reg = sci_getreg(port, SCFDR);
757 if (reg->size)
b2f20ed9 758 return serial_port_in(port, SCFDR) & fifo_mask;
72b294cf 759
b12bb29f 760 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 761}
762
1da177e4
LT		 763/* ********************************************************************** *
764 * the interrupt related routines *
765 * ********************************************************************** */
766
767static void sci_transmit_chars(struct uart_port *port)
768{
ebd2c8f6 769 struct circ_buf *xmit = &port->state->xmit;
1da177e4 770 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 771 unsigned short status;
772 unsigned short ctrl;
e108b2ca 773 int count;
1da177e4 774
b12bb29f 775 status = serial_port_in(port, SCxSR);
1da177e4 776 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 777 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 778 if (uart_circ_empty(xmit))
8e698614 779 ctrl &= ~SCSCR_TIE;
e7c98dc7 780 else
8e698614 781 ctrl |= SCSCR_TIE;
b12bb29f 782 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 783 return;
784 }
785
72b294cf 786 count = sci_txroom(port);
1da177e4
LT		 787
788 do {
789 unsigned char c;
790
791 if (port->x_char) {
792 c = port->x_char;
793 port->x_char = 0;
794 } else if (!uart_circ_empty(xmit) && !stopped) {
795 c = xmit->buf[xmit->tail];
796 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
797 } else {
798 break;
799 }
800
b12bb29f 801 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 802
803 port->icount.tx++;
804 } while (--count > 0);
805
a1b5b43f 806 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 807
808 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
809 uart_write_wakeup(port);
810 if (uart_circ_empty(xmit)) {
b129a8cc 811 sci_stop_tx(port);
1da177e4 812 } else {
b12bb29f 813 ctrl = serial_port_in(port, SCSCR);
1da177e4 814
1a22f08d 815 if (port->type != PORT_SCI) {
b12bb29f 816 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 817 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 818 }
1da177e4 819
8e698614 820 ctrl |= SCSCR_TIE;
b12bb29f 821 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 822 }
823}
824
825/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 826#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 827
94c8b6db 828static void sci_receive_chars(struct uart_port *port)
1da177e4 829{
227434f8 830 struct tty_port *tport = &port->state->port;
1da177e4
LT		 831 int i, count, copied = 0;
832 unsigned short status;
33f0f88f 833 unsigned char flag;
1da177e4 834
b12bb29f 835 status = serial_port_in(port, SCxSR);
1da177e4
LT		 836 if (!(status & SCxSR_RDxF(port)))
837 return;
838
839 while (1) {
1da177e4 840 /* Don't copy more bytes than there is room for in the buffer */
227434f8 841 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 842
843 /* If for any reason we can't copy more data, we're done! */
844 if (count == 0)
845 break;
846
847 if (port->type == PORT_SCI) {
b12bb29f 848 char c = serial_port_in(port, SCxRDR);
d5cb1319 849 if (uart_handle_sysrq_char(port, c))
1da177e4 850 count = 0;
e7c98dc7 851 else
92a19f9c 852 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 853 } else {
e7c98dc7 854 for (i = 0; i < count; i++) {
b12bb29f 855 char c = serial_port_in(port, SCxRDR);
d97fbbed 856
b12bb29f 857 status = serial_port_in(port, SCxSR);
7d12e780 858 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 859 count--; i--;
860 continue;
861 }
862
863 /* Store data and status */
73a19e4c 864 if (status & SCxSR_FER(port)) {
33f0f88f 865 flag = TTY_FRAME;
d97fbbed 866 port->icount.frame++;
762c69e3 867 dev_notice(port->dev, "frame error\n");
73a19e4c 868 } else if (status & SCxSR_PER(port)) {
33f0f88f 869 flag = TTY_PARITY;
d97fbbed 870 port->icount.parity++;
762c69e3 871 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 872 } else
873 flag = TTY_NORMAL;
762c69e3 874
92a19f9c 875 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 876 }
877 }
878
b12bb29f 879 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 880 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 881
1da177e4
LT		 882 copied += count;
883 port->icount.rx += count;
884 }
885
886 if (copied) {
887 /* Tell the rest of the system the news. New characters! */
2e124b4a 888 tty_flip_buffer_push(tport);
1da177e4 889 } else {
b12bb29f 890 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 891 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 892 }
893}
894
94c8b6db 895static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 896{
897 int copied = 0;
b12bb29f 898 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 899 struct tty_port *tport = &port->state->port;
debf9507 900 struct sci_port *s = to_sci_port(port);
1da177e4 901
3ae988d9 902 /* Handle overruns */
b2f20ed9 903 if (status & s->params->overrun_mask) {
3ae988d9 904 port->icount.overrun++;
d97fbbed 905
3ae988d9
LP		 906 /* overrun error */
907 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
908 copied++;
762c69e3 909
9b971cd2 910 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 911 }
912
e108b2ca 913 if (status & SCxSR_FER(port)) {
d5cb1319
LP		 914 /* frame error */
915 port->icount.frame++;
d97fbbed 916
d5cb1319
LP		 917 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
918 copied++;
762c69e3 919
d5cb1319 920 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 921 }
922
e108b2ca 923 if (status & SCxSR_PER(port)) {
1da177e4 924 /* parity error */
d97fbbed
PM		 925 port->icount.parity++;
926
92a19f9c 927 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 928 copied++;
762c69e3 929
9b971cd2 930 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 931 }
932
33f0f88f 933 if (copied)
2e124b4a 934 tty_flip_buffer_push(tport);
1da177e4
LT		 935
936 return copied;
937}
938
94c8b6db 939static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 940{
92a19f9c 941 struct tty_port *tport = &port->state->port;
debf9507 942 struct sci_port *s = to_sci_port(port);
d3184e68 943 const struct plat_sci_reg *reg;
2e0842a1 944 int copied = 0;
75c249fd 945 u16 status;
d830fa45 946
b2f20ed9 947 reg = sci_getreg(port, s->params->overrun_reg);
4b8c59a3 948 if (!reg->size)
d830fa45
PM		 949 return 0;
950
b2f20ed9
LP		 951 status = serial_port_in(port, s->params->overrun_reg);
952 if (status & s->params->overrun_mask) {
953 status &= ~s->params->overrun_mask;
954 serial_port_out(port, s->params->overrun_reg, status);
d830fa45 955
d97fbbed
PM		 956 port->icount.overrun++;
957
92a19f9c 958 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 959 tty_flip_buffer_push(tport);
d830fa45 960
51b31f1c 961 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 962 copied++;
963 }
964
965 return copied;
966}
967
94c8b6db 968static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 969{
970 int copied = 0;
b12bb29f 971 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 972 struct tty_port *tport = &port->state->port;
1da177e4 973
0b3d4ef6
PM		 974 if (uart_handle_break(port))
975 return 0;
976
d5cb1319 977 if (status & SCxSR_BRK(port)) {
d97fbbed
PM		 978 port->icount.brk++;
979
1da177e4 980 /* Notify of BREAK */
92a19f9c 981 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 982 copied++;
762c69e3
PM		 983
984 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 985 }
986
33f0f88f 987 if (copied)
2e124b4a 988 tty_flip_buffer_push(tport);
e108b2ca 989
d830fa45
PM		 990 copied += sci_handle_fifo_overrun(port);
991
1da177e4
LT		 992 return copied;
993}
994
a380ed46
UH		 995static int scif_set_rtrg(struct uart_port *port, int rx_trig)
996{
997 unsigned int bits;
998
999 if (rx_trig < 1)
1000 rx_trig = 1;
1001 if (rx_trig >= port->fifosize)
1002 rx_trig = port->fifosize;
1003
1004 /* HSCIF can be set to an arbitrary level. */
1005 if (sci_getreg(port, HSRTRGR)->size) {
1006 serial_port_out(port, HSRTRGR, rx_trig);
1007 return rx_trig;
1008 }
1009
1010 switch (port->type) {
1011 case PORT_SCIF:
1012 if (rx_trig < 4) {
1013 bits = 0;
1014 rx_trig = 1;
1015 } else if (rx_trig < 8) {
1016 bits = SCFCR_RTRG0;
1017 rx_trig = 4;
1018 } else if (rx_trig < 14) {
1019 bits = SCFCR_RTRG1;
1020 rx_trig = 8;
1021 } else {
1022 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1023 rx_trig = 14;
1024 }
1025 break;
1026 case PORT_SCIFA:
1027 case PORT_SCIFB:
1028 if (rx_trig < 16) {
1029 bits = 0;
1030 rx_trig = 1;
1031 } else if (rx_trig < 32) {
1032 bits = SCFCR_RTRG0;
1033 rx_trig = 16;
1034 } else if (rx_trig < 48) {
1035 bits = SCFCR_RTRG1;
1036 rx_trig = 32;
1037 } else {
1038 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1039 rx_trig = 48;
1040 }
1041 break;
1042 default:
1043 WARN(1, "unknown FIFO configuration");
1044 return 1;
1045 }
1046
1047 serial_port_out(port, SCFCR,
1048 (serial_port_in(port, SCFCR) &
1049 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1050
1051 return rx_trig;
1052}
1053
03940376
UH		 1054static int scif_rtrg_enabled(struct uart_port *port)
1055{
1056 if (sci_getreg(port, HSRTRGR)->size)
1057 return serial_port_in(port, HSRTRGR) != 0;
1058 else
1059 return (serial_port_in(port, SCFCR) &
1060 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1061}
1062
1063static void rx_fifo_timer_fn(unsigned long arg)
1064{
1065 struct sci_port *s = (struct sci_port *)arg;
1066 struct uart_port *port = &s->port;
1067
1068 dev_dbg(port->dev, "Rx timed out\n");
1069 scif_set_rtrg(port, 1);
1070}
1071
5d23188a
UH		 1072static ssize_t rx_trigger_show(struct device *dev,
1073 struct device_attribute *attr,
1074 char *buf)
1075{
1076 struct uart_port *port = dev_get_drvdata(dev);
1077 struct sci_port *sci = to_sci_port(port);
1078
1079 return sprintf(buf, "%d\n", sci->rx_trigger);
1080}
1081
1082static ssize_t rx_trigger_store(struct device *dev,
1083 struct device_attribute *attr,
1084 const char *buf,
1085 size_t count)
1086{
1087 struct uart_port *port = dev_get_drvdata(dev);
1088 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1089 int ret;
5d23188a
UH		 1090 long r;
1091
4ab3c51e
DC		 1092 ret = kstrtol(buf, 0, &r);
1093 if (ret)
1094 return ret;
90afa525 1095
5d23188a 1096 sci->rx_trigger = scif_set_rtrg(port, r);
90afa525
UH		 1097 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1098 scif_set_rtrg(port, 1);
1099
5d23188a
UH		 1100 return count;
1101}
1102
1103static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1104
1105static ssize_t rx_fifo_timeout_show(struct device *dev,
1106 struct device_attribute *attr,
1107 char *buf)
1108{
1109 struct uart_port *port = dev_get_drvdata(dev);
1110 struct sci_port *sci = to_sci_port(port);
fa2abb03 1111 int v;
5d23188a 1112
fa2abb03
UH		 1113 if (port->type == PORT_HSCIF)
1114 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1115 else
1116 v = sci->rx_fifo_timeout;
1117
1118 return sprintf(buf, "%d\n", v);
5d23188a
UH		 1119}
1120
1121static ssize_t rx_fifo_timeout_store(struct device *dev,
1122 struct device_attribute *attr,
1123 const char *buf,
1124 size_t count)
1125{
1126 struct uart_port *port = dev_get_drvdata(dev);
1127 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1128 int ret;
5d23188a
UH		 1129 long r;
1130
4ab3c51e
DC		 1131 ret = kstrtol(buf, 0, &r);
1132 if (ret)
1133 return ret;
fa2abb03
UH		 1134
1135 if (port->type == PORT_HSCIF) {
1136 if (r < 0 || r > 3)
1137 return -EINVAL;
1138 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1139 } else {
1140 sci->rx_fifo_timeout = r;
1141 scif_set_rtrg(port, 1);
1142 if (r > 0)
1143 setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn,
1144 (unsigned long)sci);
1145 }
1146
5d23188a
UH		 1147 return count;
1148}
1149
1150static DEVICE_ATTR(rx_fifo_timeout, 0644, rx_fifo_timeout_show, rx_fifo_timeout_store);
1151
1152
73a19e4c 1153#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1154static void sci_dma_tx_complete(void *arg)
1155{
1156 struct sci_port *s = arg;
1157 struct uart_port *port = &s->port;
1158 struct circ_buf *xmit = &port->state->xmit;
1159 unsigned long flags;
73a19e4c 1160
e1910fcd 1161 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1162
e1910fcd 1163 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1164
e1910fcd
GU		 1165 xmit->tail += s->tx_dma_len;
1166 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1167
e1910fcd 1168 port->icount.tx += s->tx_dma_len;
1da177e4 1169
e1910fcd
GU		 1170 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1171 uart_write_wakeup(port);
1da177e4 1172
e1910fcd
GU		 1173 if (!uart_circ_empty(xmit)) {
1174 s->cookie_tx = 0;
1175 schedule_work(&s->work_tx);
1176 } else {
1177 s->cookie_tx = -EINVAL;
1178 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1179 u16 ctrl = serial_port_in(port, SCSCR);
1180 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1181 }
1182 }
1da177e4 1183
fd78a76a 1184 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1185}
1186
e1910fcd
GU		 1187/* Locking: called with port lock held */
1188static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1189{
e1910fcd
GU		 1190 struct uart_port *port = &s->port;
1191 struct tty_port *tport = &port->state->port;
1192 int copied;
1da177e4 1193
e1910fcd 1194 copied = tty_insert_flip_string(tport, buf, count);
6fc5a520 1195 if (copied < count)
e1910fcd 1196 port->icount.buf_overrun++;
1da177e4 1197
e1910fcd 1198 port->icount.rx += copied;
1da177e4 1199
e1910fcd 1200 return copied;
1da177e4
LT		 1201}
1202
e1910fcd 1203static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1204{
e1910fcd 1205 unsigned int i;
1da177e4 1206
e1910fcd
GU		 1207 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1208 if (s->active_rx == s->cookie_rx[i])
1209 return i;
1da177e4 1210
e1910fcd 1211 return -1;
1da177e4
LT		 1212}
1213
e1910fcd 1214static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1215{
e1910fcd
GU		 1216 struct dma_chan *chan = s->chan_rx;
1217 struct uart_port *port = &s->port;
1218 unsigned long flags;
1219
1220 spin_lock_irqsave(&port->lock, flags);
1221 s->chan_rx = NULL;
1222 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1223 spin_unlock_irqrestore(&port->lock, flags);
1224 dmaengine_terminate_all(chan);
1225 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1226 sg_dma_address(&s->sg_rx[0]));
1227 dma_release_channel(chan);
1228 if (enable_pio)
1229 sci_start_rx(port);
f43dc23d
PM		 1230}
1231
e1910fcd 1232static void sci_dma_rx_complete(void *arg)
1da177e4 1233{
e1910fcd 1234 struct sci_port *s = arg;
1d3db608 1235 struct dma_chan *chan = s->chan_rx;
e1910fcd 1236 struct uart_port *port = &s->port;
67f462b0 1237 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1238 unsigned long flags;
1239 int active, count = 0;
1da177e4 1240
e1910fcd
GU		 1241 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1242 s->active_rx);
cb772fe7 1243
e1910fcd 1244 spin_lock_irqsave(&port->lock, flags);
1da177e4 1245
e1910fcd
GU		 1246 active = sci_dma_rx_find_active(s);
1247 if (active >= 0)
1248 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1249
e1910fcd 1250 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1251
e1910fcd
GU		 1252 if (count)
1253 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1254
67f462b0
GU		 1255 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1256 DMA_DEV_TO_MEM,
1257 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1258 if (!desc)
1259 goto fail;
1260
1261 desc->callback = sci_dma_rx_complete;
1262 desc->callback_param = s;
1263 s->cookie_rx[active] = dmaengine_submit(desc);
1264 if (dma_submit_error(s->cookie_rx[active]))
1265 goto fail;
1266
1267 s->active_rx = s->cookie_rx[!active];
1268
1d3db608
MHF		 1269 dma_async_issue_pending(chan);
1270
6fc5a520 1271 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1272 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1273 __func__, s->cookie_rx[active], active, s->active_rx);
67f462b0
GU		 1274 return;
1275
1276fail:
1277 spin_unlock_irqrestore(&port->lock, flags);
1278 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1279 sci_rx_dma_release(s, true);
1da177e4
LT		 1280}
1281
e1910fcd 1282static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1283{
e1910fcd
GU		 1284 struct dma_chan *chan = s->chan_tx;
1285 struct uart_port *port = &s->port;
e552de24 1286 unsigned long flags;
1da177e4 1287
e1910fcd
GU		 1288 spin_lock_irqsave(&port->lock, flags);
1289 s->chan_tx = NULL;
1290 s->cookie_tx = -EINVAL;
1291 spin_unlock_irqrestore(&port->lock, flags);
1292 dmaengine_terminate_all(chan);
1293 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1294 DMA_TO_DEVICE);
1295 dma_release_channel(chan);
1296 if (enable_pio)
1297 sci_start_tx(port);
1298}
d535a230 1299
e1910fcd
GU		 1300static void sci_submit_rx(struct sci_port *s)
1301{
1302 struct dma_chan *chan = s->chan_rx;
1303 int i;
073e84c9 1304
e1910fcd
GU		 1305 for (i = 0; i < 2; i++) {
1306 struct scatterlist *sg = &s->sg_rx[i];
1307 struct dma_async_tx_descriptor *desc;
1da177e4 1308
e1910fcd
GU		 1309 desc = dmaengine_prep_slave_sg(chan,
1310 sg, 1, DMA_DEV_TO_MEM,
1311 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1312 if (!desc)
1313 goto fail;
501b825d 1314
e1910fcd
GU		 1315 desc->callback = sci_dma_rx_complete;
1316 desc->callback_param = s;
1317 s->cookie_rx[i] = dmaengine_submit(desc);
1318 if (dma_submit_error(s->cookie_rx[i]))
1319 goto fail;
9174fc8f 1320
e1910fcd 1321 }
9174fc8f 1322
e1910fcd 1323 s->active_rx = s->cookie_rx[0];
9174fc8f 1324
e1910fcd
GU		 1325 dma_async_issue_pending(chan);
1326 return;
9174fc8f 1327
e1910fcd
GU		 1328fail:
1329 if (i)
1330 dmaengine_terminate_all(chan);
1331 for (i = 0; i < 2; i++)
1332 s->cookie_rx[i] = -EINVAL;
1333 s->active_rx = -EINVAL;
e1910fcd
GU		 1334 sci_rx_dma_release(s, true);
1335}
9174fc8f 1336
e1910fcd 1337static void work_fn_tx(struct work_struct *work)
1da177e4 1338{
e1910fcd
GU		 1339 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1340 struct dma_async_tx_descriptor *desc;
1341 struct dma_chan *chan = s->chan_tx;
1342 struct uart_port *port = &s->port;
1343 struct circ_buf *xmit = &port->state->xmit;
1344 dma_addr_t buf;
1da177e4 1345
9174fc8f 1346 /*
e1910fcd
GU		 1347 * DMA is idle now.
1348 * Port xmit buffer is already mapped, and it is one page... Just adjust
1349 * offsets and lengths. Since it is a circular buffer, we have to
1350 * transmit till the end, and then the rest. Take the port lock to get a
1351 * consistent xmit buffer state.
9174fc8f 1352 */
e1910fcd
GU		 1353 spin_lock_irq(&port->lock);
1354 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1355 s->tx_dma_len = min_t(unsigned int,
1356 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1357 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1358 spin_unlock_irq(&port->lock);
0e8963de 1359
e1910fcd
GU		 1360 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1361 DMA_MEM_TO_DEV,
1362 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1363 if (!desc) {
1364 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1365 /* switch to PIO */
1366 sci_tx_dma_release(s, true);
1367 return;
1368 }
0e8963de 1369
e1910fcd
GU		 1370 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1371 DMA_TO_DEVICE);
1da177e4 1372
e1910fcd
GU		 1373 spin_lock_irq(&port->lock);
1374 desc->callback = sci_dma_tx_complete;
1375 desc->callback_param = s;
1376 spin_unlock_irq(&port->lock);
1377 s->cookie_tx = dmaengine_submit(desc);
1378 if (dma_submit_error(s->cookie_tx)) {
1379 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1380 /* switch to PIO */
1381 sci_tx_dma_release(s, true);
1382 return;
1da177e4 1383 }
1da177e4 1384
e1910fcd
GU		 1385 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1386 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1387
e1910fcd 1388 dma_async_issue_pending(chan);
1da177e4
LT		 1389}
1390
e1910fcd 1391static void rx_timer_fn(unsigned long arg)
1da177e4 1392{
e1910fcd 1393 struct sci_port *s = (struct sci_port *)arg;
e7327c09 1394 struct dma_chan *chan = s->chan_rx;
e1910fcd 1395 struct uart_port *port = &s->port;
67f462b0
GU		 1396 struct dma_tx_state state;
1397 enum dma_status status;
1398 unsigned long flags;
1399 unsigned int read;
1400 int active, count;
1401 u16 scr;
1402
67f462b0 1403 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0 1404
6fc5a520
TA		 1405 spin_lock_irqsave(&port->lock, flags);
1406
67f462b0
GU		 1407 active = sci_dma_rx_find_active(s);
1408 if (active < 0) {
1409 spin_unlock_irqrestore(&port->lock, flags);
1410 return;
1411 }
1412
1413 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1414 if (status == DMA_COMPLETE) {
6fc5a520 1415 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1416 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1417 s->active_rx, active);
3b963042
MHF		 1418
1419 /* Let packet complete handler take care of the packet */
1420 return;
1421 }
67f462b0 1422
e7327c09
MHF		 1423 dmaengine_pause(chan);
1424
1425 /*
1426 * sometimes DMA transfer doesn't stop even if it is stopped and
1427 * data keeps on coming until transaction is complete so check
1428 * for DMA_COMPLETE again
1429 * Let packet complete handler take care of the packet
1430 */
1431 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1432 if (status == DMA_COMPLETE) {
1433 spin_unlock_irqrestore(&port->lock, flags);
1434 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1435 return;
1436 }
1437
67f462b0
GU		 1438 /* Handle incomplete DMA receive */
1439 dmaengine_terminate_all(s->chan_rx);
1440 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
67f462b0
GU		 1441
1442 if (read) {
1443 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1444 if (count)
1445 tty_flip_buffer_push(&port->state->port);
1446 }
1447
756981be
GU		 1448 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1449 sci_submit_rx(s);
371cfed3
MHF		 1450
1451 /* Direct new serial port interrupts back to CPU */
1452 scr = serial_port_in(port, SCSCR);
1453 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1454 scr &= ~SCSCR_RDRQE;
1455 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1456 }
1457 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1458
1459 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1460}
1461
ff441129 1462static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
219fb0c1 1463 enum dma_transfer_direction dir)
ff441129 1464{
ff441129
GU		 1465 struct dma_chan *chan;
1466 struct dma_slave_config cfg;
1467 int ret;
1468
219fb0c1
LP		 1469 chan = dma_request_slave_channel(port->dev,
1470 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
ff441129 1471 if (!chan) {
9b7becf1 1472 dev_warn(port->dev, "dma_request_slave_channel failed\n");
ff441129
GU		 1473 return NULL;
1474 }
1475
1476 memset(&cfg, 0, sizeof(cfg));
1477 cfg.direction = dir;
1478 if (dir == DMA_MEM_TO_DEV) {
1479 cfg.dst_addr = port->mapbase +
1480 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1481 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1482 } else {
1483 cfg.src_addr = port->mapbase +
1484 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1485 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1486 }
1487
1488 ret = dmaengine_slave_config(chan, &cfg);
1489 if (ret) {
1490 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1491 dma_release_channel(chan);
1492 return NULL;
1493 }
1494
1495 return chan;
1496}
1497
e1910fcd 1498static void sci_request_dma(struct uart_port *port)
73a19e4c 1499{
e1910fcd 1500 struct sci_port *s = to_sci_port(port);
e1910fcd 1501 struct dma_chan *chan;
73a19e4c 1502
e1910fcd 1503 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1504
219fb0c1 1505 if (!port->dev->of_node)
e1910fcd 1506 return;
73a19e4c 1507
e1910fcd 1508 s->cookie_tx = -EINVAL;
219fb0c1 1509 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
e1910fcd
GU		 1510 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1511 if (chan) {
1512 s->chan_tx = chan;
1513 /* UART circular tx buffer is an aligned page. */
1514 s->tx_dma_addr = dma_map_single(chan->device->dev,
1515 port->state->xmit.buf,
1516 UART_XMIT_SIZE,
1517 DMA_TO_DEVICE);
1518 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1519 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1520 dma_release_channel(chan);
1521 s->chan_tx = NULL;
1522 } else {
1523 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1524 __func__, UART_XMIT_SIZE,
1525 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1526 }
e1910fcd
GU		 1527
1528 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1529 }
1530
219fb0c1 1531 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
e1910fcd
GU		 1532 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1533 if (chan) {
1534 unsigned int i;
1535 dma_addr_t dma;
1536 void *buf;
73a19e4c 1537
e1910fcd 1538 s->chan_rx = chan;
73a19e4c 1539
e1910fcd
GU		 1540 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1541 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1542 &dma, GFP_KERNEL);
1543 if (!buf) {
1544 dev_warn(port->dev,
1545 "Failed to allocate Rx dma buffer, using PIO\n");
1546 dma_release_channel(chan);
1547 s->chan_rx = NULL;
e1910fcd
GU		 1548 return;
1549 }
73a19e4c 1550
e1910fcd
GU		 1551 for (i = 0; i < 2; i++) {
1552 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1553
e1910fcd
GU		 1554 sg_init_table(sg, 1);
1555 s->rx_buf[i] = buf;
1556 sg_dma_address(sg) = dma;
d09959e7 1557 sg_dma_len(sg) = s->buf_len_rx;
0533502d 1558
e1910fcd
GU		 1559 buf += s->buf_len_rx;
1560 dma += s->buf_len_rx;
1561 }
1562
e1910fcd
GU		 1563 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1564
756981be
GU		 1565 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1566 sci_submit_rx(s);
e1910fcd 1567 }
0533502d
GU		 1568}
1569
e1910fcd 1570static void sci_free_dma(struct uart_port *port)
73a19e4c 1571{
e1910fcd 1572 struct sci_port *s = to_sci_port(port);
73a19e4c 1573
e1910fcd
GU		 1574 if (s->chan_tx)
1575 sci_tx_dma_release(s, false);
1576 if (s->chan_rx)
1577 sci_rx_dma_release(s, false);
1578}
1cf4a7ef
GU		 1579
1580static void sci_flush_buffer(struct uart_port *port)
1581{
1582 /*
1583 * In uart_flush_buffer(), the xmit circular buffer has just been
1584 * cleared, so we have to reset tx_dma_len accordingly.
1585 */
1586 to_sci_port(port)->tx_dma_len = 0;
1587}
1588#else /* !CONFIG_SERIAL_SH_SCI_DMA */
e1910fcd
GU		 1589static inline void sci_request_dma(struct uart_port *port)
1590{
1591}
73a19e4c 1592
e1910fcd
GU		 1593static inline void sci_free_dma(struct uart_port *port)
1594{
1595}
1cf4a7ef
GU		 1596
1597#define sci_flush_buffer NULL
1598#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
73a19e4c 1599
e1910fcd
GU		 1600static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1601{
e1910fcd
GU		 1602 struct uart_port *port = ptr;
1603 struct sci_port *s = to_sci_port(port);
73a19e4c 1604
03940376 1605#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1606 if (s->chan_rx) {
1607 u16 scr = serial_port_in(port, SCSCR);
1608 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1609
e1910fcd
GU		 1610 /* Disable future Rx interrupts */
1611 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1612 disable_irq_nosync(irq);
1613 scr |= SCSCR_RDRQE;
1614 } else {
1615 scr &= ~SCSCR_RIE;
756981be 1616 sci_submit_rx(s);
e1910fcd
GU		 1617 }
1618 serial_port_out(port, SCSCR, scr);
1619 /* Clear current interrupt */
1620 serial_port_out(port, SCxSR,
1621 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1622 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1623 jiffies, s->rx_timeout);
1624 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1625
e1910fcd
GU		 1626 return IRQ_HANDLED;
1627 }
1628#endif
73a19e4c 1629
03940376
UH		 1630 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1631 if (!scif_rtrg_enabled(port))
1632 scif_set_rtrg(port, s->rx_trigger);
1633
1634 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1635 s->rx_frame * s->rx_fifo_timeout, 1000));
1636 }
1637
e1910fcd
GU		 1638 /* I think sci_receive_chars has to be called irrespective
1639 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1640 * to be disabled?
1641 */
1642 sci_receive_chars(ptr);
1643
1644 return IRQ_HANDLED;
73a19e4c
GL		 1645}
1646
e1910fcd 1647static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1648{
e1910fcd 1649 struct uart_port *port = ptr;
04928b79 1650 unsigned long flags;
73a19e4c 1651
04928b79 1652 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1653 sci_transmit_chars(port);
04928b79 1654 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1655
1656 return IRQ_HANDLED;
73a19e4c
GL		 1657}
1658
e1910fcd 1659static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1660{
e1910fcd
GU		 1661 struct uart_port *port = ptr;
1662 struct sci_port *s = to_sci_port(port);
73a19e4c 1663
e1910fcd
GU		 1664 /* Handle errors */
1665 if (port->type == PORT_SCI) {
1666 if (sci_handle_errors(port)) {
1667 /* discard character in rx buffer */
1668 serial_port_in(port, SCxSR);
1669 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1670 }
1671 } else {
1672 sci_handle_fifo_overrun(port);
1673 if (!s->chan_rx)
1674 sci_receive_chars(ptr);
1675 }
1676
1677 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1678
1679 /* Kick the transmission */
1680 if (!s->chan_tx)
1681 sci_tx_interrupt(irq, ptr);
1682
1683 return IRQ_HANDLED;
73a19e4c
GL		 1684}
1685
e1910fcd 1686static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1687{
e1910fcd 1688 struct uart_port *port = ptr;
73a19e4c 1689
e1910fcd
GU		 1690 /* Handle BREAKs */
1691 sci_handle_breaks(port);
1692 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1693
e1910fcd
GU		 1694 return IRQ_HANDLED;
1695}
73a19e4c 1696
e1910fcd
GU		 1697static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1698{
1699 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1700 struct uart_port *port = ptr;
1701 struct sci_port *s = to_sci_port(port);
1702 irqreturn_t ret = IRQ_NONE;
73a19e4c 1703
e1910fcd
GU		 1704 ssr_status = serial_port_in(port, SCxSR);
1705 scr_status = serial_port_in(port, SCSCR);
b2f20ed9 1706 if (s->params->overrun_reg == SCxSR)
e1910fcd 1707 orer_status = ssr_status;
b2f20ed9
LP		 1708 else if (sci_getreg(port, s->params->overrun_reg)->size)
1709 orer_status = serial_port_in(port, s->params->overrun_reg);
73a19e4c 1710
e1910fcd 1711 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1712
e1910fcd
GU		 1713 /* Tx Interrupt */
1714 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1715 !s->chan_tx)
1716 ret = sci_tx_interrupt(irq, ptr);
658daa95 1717
e1910fcd
GU		 1718 /*
1719 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1720 * DR flags
1721 */
1722 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1723 (scr_status & SCSCR_RIE))
1724 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1725
e1910fcd
GU		 1726 /* Error Interrupt */
1727 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1728 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1729
e1910fcd
GU		 1730 /* Break Interrupt */
1731 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1732 ret = sci_br_interrupt(irq, ptr);
1733
1734 /* Overrun Interrupt */
b2f20ed9 1735 if (orer_status & s->params->overrun_mask) {
e1910fcd
GU		 1736 sci_handle_fifo_overrun(port);
1737 ret = IRQ_HANDLED;
73a19e4c 1738 }
73a19e4c 1739
e1910fcd
GU		 1740 return ret;
1741}
73a19e4c 1742
e1910fcd
GU		 1743static const struct sci_irq_desc {
1744 const char *desc;
1745 irq_handler_t handler;
1746} sci_irq_desc[] = {
1747 /*
1748 * Split out handlers, the default case.
1749 */
1750 [SCIx_ERI_IRQ] = {
1751 .desc = "rx err",
1752 .handler = sci_er_interrupt,
1753 },
3089f381 1754
e1910fcd
GU		 1755 [SCIx_RXI_IRQ] = {
1756 .desc = "rx full",
1757 .handler = sci_rx_interrupt,
1758 },
47aceb92 1759
e1910fcd
GU		 1760 [SCIx_TXI_IRQ] = {
1761 .desc = "tx empty",
1762 .handler = sci_tx_interrupt,
1763 },
73a19e4c 1764
e1910fcd
GU		 1765 [SCIx_BRI_IRQ] = {
1766 .desc = "break",
1767 .handler = sci_br_interrupt,
1768 },
73a19e4c
GL		 1769
1770 /*
e1910fcd 1771 * Special muxed handler.
73a19e4c 1772 */
e1910fcd
GU		 1773 [SCIx_MUX_IRQ] = {
1774 .desc = "mux",
1775 .handler = sci_mpxed_interrupt,
1776 },
1777};
73a19e4c 1778
e1910fcd
GU		 1779static int sci_request_irq(struct sci_port *port)
1780{
1781 struct uart_port *up = &port->port;
1782 int i, j, ret = 0;
73a19e4c 1783
e1910fcd
GU		 1784 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1785 const struct sci_irq_desc *desc;
1786 int irq;
73a19e4c 1787
e1910fcd
GU		 1788 if (SCIx_IRQ_IS_MUXED(port)) {
1789 i = SCIx_MUX_IRQ;
1790 irq = up->irq;
1791 } else {
1792 irq = port->irqs[i];
1793
1794 /*
1795 * Certain port types won't support all of the
1796 * available interrupt sources.
1797 */
1798 if (unlikely(irq < 0))
1799 continue;
1800 }
1801
1802 desc = sci_irq_desc + i;
1803 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1804 dev_name(up->dev), desc->desc);
623ac1d4
PB		 1805 if (!port->irqstr[j]) {
1806 ret = -ENOMEM;
e1910fcd 1807 goto out_nomem;
623ac1d4 1808 }
e1910fcd
GU		 1809
1810 ret = request_irq(irq, desc->handler, up->irqflags,
1811 port->irqstr[j], port);
1812 if (unlikely(ret)) {
1813 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1814 goto out_noirq;
1815 }
73a19e4c
GL		 1816 }
1817
e1910fcd 1818 return 0;
1da177e4 1819
e1910fcd
GU		 1820out_noirq:
1821 while (--i >= 0)
1822 free_irq(port->irqs[i], port);
f43dc23d 1823
e1910fcd
GU		 1824out_nomem:
1825 while (--j >= 0)
1826 kfree(port->irqstr[j]);
f43dc23d 1827
e1910fcd 1828 return ret;
1da177e4
LT		 1829}
1830
e1910fcd 1831static void sci_free_irq(struct sci_port *port)
1da177e4 1832{
e1910fcd 1833 int i;
1da177e4 1834
e1910fcd
GU		 1835 /*
1836 * Intentionally in reverse order so we iterate over the muxed
1837 * IRQ first.
1838 */
1839 for (i = 0; i < SCIx_NR_IRQS; i++) {
1840 int irq = port->irqs[i];
f43dc23d 1841
e1910fcd
GU		 1842 /*
1843 * Certain port types won't support all of the available
1844 * interrupt sources.
1845 */
1846 if (unlikely(irq < 0))
1847 continue;
f43dc23d 1848
e1910fcd
GU		 1849 free_irq(port->irqs[i], port);
1850 kfree(port->irqstr[i]);
f43dc23d 1851
e1910fcd
GU		 1852 if (SCIx_IRQ_IS_MUXED(port)) {
1853 /* If there's only one IRQ, we're done. */
1854 return;
1855 }
1856 }
1da177e4
LT		 1857}
1858
e1910fcd 1859static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1860{
e1910fcd
GU		 1861 unsigned short status = serial_port_in(port, SCxSR);
1862 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1863
e1910fcd 1864 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1865}
1866
33f50ffc
GU		 1867static void sci_set_rts(struct uart_port *port, bool state)
1868{
1869 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1870 u16 data = serial_port_in(port, SCPDR);
1871
1872 /* Active low */
1873 if (state)
1874 data &= ~SCPDR_RTSD;
1875 else
1876 data |= SCPDR_RTSD;
1877 serial_port_out(port, SCPDR, data);
1878
1879 /* RTS# is output */
1880 serial_port_out(port, SCPCR,
1881 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1882 } else if (sci_getreg(port, SCSPTR)->size) {
1883 u16 ctrl = serial_port_in(port, SCSPTR);
1884
1885 /* Active low */
1886 if (state)
1887 ctrl &= ~SCSPTR_RTSDT;
1888 else
1889 ctrl |= SCSPTR_RTSDT;
1890 serial_port_out(port, SCSPTR, ctrl);
1891 }
1892}
1893
1894static bool sci_get_cts(struct uart_port *port)
1895{
1896 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1897 /* Active low */
1898 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1899 } else if (sci_getreg(port, SCSPTR)->size) {
1900 /* Active low */
1901 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1902 }
1903
1904 return true;
1905}
1906
e1910fcd
GU		 1907/*
1908 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1909 * CTS/RTS is supported in hardware by at least one port and controlled
1910 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1911 * handled via the ->init_pins() op, which is a bit of a one-way street,
1912 * lacking any ability to defer pin control -- this will later be
1913 * converted over to the GPIO framework).
1914 *
1915 * Other modes (such as loopback) are supported generically on certain
1916 * port types, but not others. For these it's sufficient to test for the
1917 * existence of the support register and simply ignore the port type.
1918 */
1919static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1920{
f907c9ea
GU		 1921 struct sci_port *s = to_sci_port(port);
1922
e1910fcd
GU		 1923 if (mctrl & TIOCM_LOOP) {
1924 const struct plat_sci_reg *reg;
f43dc23d 1925
e1910fcd
GU		 1926 /*
1927 * Standard loopback mode for SCFCR ports.
1928 */
1929 reg = sci_getreg(port, SCFCR);
1930 if (reg->size)
1931 serial_port_out(port, SCFCR,
1932 serial_port_in(port, SCFCR) |
1933 SCFCR_LOOP);
1934 }
f907c9ea
GU		 1935
1936 mctrl_gpio_set(s->gpios, mctrl);
33f50ffc 1937
97ed9790 1938 if (!s->has_rtscts)
33f50ffc
GU		 1939 return;
1940
1941 if (!(mctrl & TIOCM_RTS)) {
1942 /* Disable Auto RTS */
1943 serial_port_out(port, SCFCR,
1944 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1945
1946 /* Clear RTS */
1947 sci_set_rts(port, 0);
1948 } else if (s->autorts) {
1949 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1950 /* Enable RTS# pin function */
1951 serial_port_out(port, SCPCR,
1952 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1953 }
1954
1955 /* Enable Auto RTS */
1956 serial_port_out(port, SCFCR,
1957 serial_port_in(port, SCFCR) | SCFCR_MCE);
1958 } else {
1959 /* Set RTS */
1960 sci_set_rts(port, 1);
1961 }
e1910fcd 1962}
f43dc23d 1963
e1910fcd
GU		 1964static unsigned int sci_get_mctrl(struct uart_port *port)
1965{
f907c9ea
GU		 1966 struct sci_port *s = to_sci_port(port);
1967 struct mctrl_gpios *gpios = s->gpios;
1968 unsigned int mctrl = 0;
1969
1970 mctrl_gpio_get(gpios, &mctrl);
1971
e1910fcd
GU		 1972 /*
1973 * CTS/RTS is handled in hardware when supported, while nothing
33f50ffc 1974 * else is wired up.
e1910fcd 1975 */
33f50ffc
GU		 1976 if (s->autorts) {
1977 if (sci_get_cts(port))
1978 mctrl |= TIOCM_CTS;
1979 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
f907c9ea 1980 mctrl |= TIOCM_CTS;
33f50ffc 1981 }
f907c9ea
GU		 1982 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1983 mctrl |= TIOCM_DSR;
1984 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1985 mctrl |= TIOCM_CAR;
1986
1987 return mctrl;
1988}
1989
1990static void sci_enable_ms(struct uart_port *port)
1991{
1992 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1da177e4
LT		 1993}
1994
1da177e4
LT		 1995static void sci_break_ctl(struct uart_port *port, int break_state)
1996{
bbb4ce50
SY		 1997 unsigned short scscr, scsptr;
1998
a4e02f6d 1999 /* check wheter the port has SCSPTR */
abbf121f 2000 if (!sci_getreg(port, SCSPTR)->size) {
bbb4ce50
SY		 2001 /*
2002 * Not supported by hardware. Most parts couple break and rx
2003 * interrupts together, with break detection always enabled.
2004 */
a4e02f6d 2005 return;
bbb4ce50 2006 }
a4e02f6d
SY		 2007
2008 scsptr = serial_port_in(port, SCSPTR);
2009 scscr = serial_port_in(port, SCSCR);
2010
2011 if (break_state == -1) {
2012 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2013 scscr &= ~SCSCR_TE;
2014 } else {
2015 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2016 scscr |= SCSCR_TE;
2017 }
2018
2019 serial_port_out(port, SCSPTR, scsptr);
2020 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 2021}
2022
2023static int sci_startup(struct uart_port *port)
2024{
a5660ada 2025 struct sci_port *s = to_sci_port(port);
073e84c9 2026 int ret;
1da177e4 2027
73a19e4c
GL		 2028 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2029
3c910176
TA		 2030 sci_request_dma(port);
2031
073e84c9 2032 ret = sci_request_irq(s);
3c910176
TA		 2033 if (unlikely(ret < 0)) {
2034 sci_free_dma(port);
073e84c9 2035 return ret;
3c910176 2036 }
073e84c9 2037
1da177e4
LT		 2038 return 0;
2039}
2040
2041static void sci_shutdown(struct uart_port *port)
2042{
a5660ada 2043 struct sci_port *s = to_sci_port(port);
33b48e16 2044 unsigned long flags;
5fd2b6ee 2045 u16 scr;
1da177e4 2046
73a19e4c
GL		 2047 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2048
33f50ffc 2049 s->autorts = false;
f907c9ea
GU		 2050 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2051
33b48e16 2052 spin_lock_irqsave(&port->lock, flags);
1da177e4 2053 sci_stop_rx(port);
b129a8cc 2054 sci_stop_tx(port);
fa2abb03
UH		 2055 /*
2056 * Stop RX and TX, disable related interrupts, keep clock source
2057 * and HSCIF TOT bits
2058 */
5fd2b6ee 2059 scr = serial_port_in(port, SCSCR);
fa2abb03
UH		 2060 serial_port_out(port, SCSCR, scr &
2061 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
33b48e16 2062 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 2063
9ab76556
AM		 2064#ifdef CONFIG_SERIAL_SH_SCI_DMA
2065 if (s->chan_rx) {
2066 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2067 port->line);
2068 del_timer_sync(&s->rx_timer);
2069 }
2070#endif
2071
1da177e4 2072 sci_free_irq(s);
3c910176 2073 sci_free_dma(port);
1da177e4
LT		 2074}
2075
6af27bf2
GU		 2076static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2077 unsigned int *srr)
26c92f37 2078{
6af27bf2 2079 unsigned long freq = s->clk_rates[SCI_SCK];
6af27bf2 2080 int err, min_err = INT_MAX;
69eee8e9 2081 unsigned int sr;
6af27bf2 2082
7b5c0c08
GU		 2083 if (s->port.type != PORT_HSCIF)
2084 freq *= 2;
6af27bf2 2085
69eee8e9 2086 for_each_sr(sr, s) {
6af27bf2
GU		 2087 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2088 if (abs(err) >= abs(min_err))
2089 continue;
2090
2091 min_err = err;
2092 *srr = sr - 1;
ec09c5eb 2093
6af27bf2
GU		 2094 if (!err)
2095 break;
2096 }
e8183a6c 2097
6af27bf2
GU		 2098 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2099 *srr + 1);
2100 return min_err;
26c92f37
PM		 2101}
2102
1270f865
GU		 2103static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2104 unsigned long freq, unsigned int *dlr,
2105 unsigned int *srr)
730c4e78 2106{
1270f865 2107 int err, min_err = INT_MAX;
69eee8e9 2108 unsigned int sr, dl;
730c4e78 2109
7b5c0c08
GU		 2110 if (s->port.type != PORT_HSCIF)
2111 freq *= 2;
730c4e78 2112
69eee8e9 2113 for_each_sr(sr, s) {
1270f865
GU		 2114 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2115 dl = clamp(dl, 1U, 65535U);
2116
2117 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2118 if (abs(err) >= abs(min_err))
2119 continue;
2120
2121 min_err = err;
2122 *dlr = dl;
2123 *srr = sr - 1;
2124
2125 if (!err)
2126 break;
2127 }
730c4e78 2128
1270f865
GU		 2129 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2130 min_err, *dlr, *srr + 1);
2131 return min_err;
2132}
730c4e78 2133
b4a5c459 2134/* calculate sample rate, BRR, and clock select */
f4998e55
GU		 2135static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2136 unsigned int *brr, unsigned int *srr,
2137 unsigned int *cks)
f303b364 2138{
f4998e55 2139 unsigned long freq = s->clk_rates[SCI_FCK];
69eee8e9 2140 unsigned int sr, br, prediv, scrate, c;
6c51332d 2141 int err, min_err = INT_MAX;
f303b364 2142
7b5c0c08
GU		 2143 if (s->port.type != PORT_HSCIF)
2144 freq *= 2;
b4a5c459 2145
6c51332d
GU		 2146 /*
2147 * Find the combination of sample rate and clock select with the
2148 * smallest deviation from the desired baud rate.
2149 * Prefer high sample rates to maximise the receive margin.
2150 *
2151 * M: Receive margin (%)
2152 * N: Ratio of bit rate to clock (N = sampling rate)
2153 * D: Clock duty (D = 0 to 1.0)
2154 * L: Frame length (L = 9 to 12)
2155 * F: Absolute value of clock frequency deviation
2156 *
2157 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2158 * (|D - 0.5| / N * (1 + F))|
2159 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2160 */
69eee8e9 2161 for_each_sr(sr, s) {
f303b364
UH		 2162 for (c = 0; c <= 3; c++) {
2163 /* integerized formulas from HSCIF documentation */
7b5c0c08 2164 prediv = sr * (1 << (2 * c + 1));
de01e6cd
GU		 2165
2166 /*
2167 * We need to calculate:
2168 *
2169 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 2170 * err = freq / (br * prediv) - bps
730c4e78 2171 *
de01e6cd
GU		 2172 * Watch out for overflow when calculating the desired
2173 * sampling clock rate!
730c4e78 2174 */
de01e6cd
GU		 2175 if (bps > UINT_MAX / prediv)
2176 break;
2177
2178 scrate = prediv * bps;
2179 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 2180 br = clamp(br, 1U, 256U);
6c51332d 2181
881a7489 2182 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 2183 if (abs(err) >= abs(min_err))
730c4e78
NI		 2184 continue;
2185
6c51332d 2186 min_err = err;
95a2703e 2187 *brr = br - 1;
730c4e78
NI		 2188 *srr = sr - 1;
2189 *cks = c;
6c51332d
GU		 2190
2191 if (!err)
2192 goto found;
f303b364
UH		 2193 }
2194 }
2195
6c51332d 2196found:
881a7489
GU		 2197 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2198 min_err, *brr, *srr + 1, *cks);
f4998e55 2199 return min_err;
f303b364
UH		 2200}
2201
1ba76220
MD		 2202static void sci_reset(struct uart_port *port)
2203{
d3184e68 2204 const struct plat_sci_reg *reg;
1ba76220 2205 unsigned int status;
18e8cf15 2206 struct sci_port *s = to_sci_port(port);
1ba76220 2207
fa2abb03 2208 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
1ba76220 2209
0979e0e6
PM		 2210 reg = sci_getreg(port, SCFCR);
2211 if (reg->size)
b12bb29f 2212 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2768cf42
GU		 2213
2214 sci_clear_SCxSR(port,
2215 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2216 SCxSR_BREAK_CLEAR(port));
fc2af334
GU		 2217 if (sci_getreg(port, SCLSR)->size) {
2218 status = serial_port_in(port, SCLSR);
2219 status &= ~(SCLSR_TO | SCLSR_ORER);
2220 serial_port_out(port, SCLSR, status);
2221 }
18e8cf15 2222
03940376
UH		 2223 if (s->rx_trigger > 1) {
2224 if (s->rx_fifo_timeout) {
2225 scif_set_rtrg(port, 1);
2226 setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn,
2227 (unsigned long)s);
2228 } else {
90afa525
UH		 2229 if (port->type == PORT_SCIFA ||
2230 port->type == PORT_SCIFB)
2231 scif_set_rtrg(port, 1);
2232 else
2233 scif_set_rtrg(port, s->rx_trigger);
03940376
UH		 2234 }
2235 }
1ba76220
MD		 2236}
2237
606d099c
AC		 2238static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2239 struct ktermios *old)
1da177e4 2240{
03940376 2241 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
1270f865
GU		 2242 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2243 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
00b9de9c 2244 struct sci_port *s = to_sci_port(port);
d3184e68 2245 const struct plat_sci_reg *reg;
f4998e55
GU		 2246 int min_err = INT_MAX, err;
2247 unsigned long max_freq = 0;
2248 int best_clk = -1;
1da177e4 2249
730c4e78
NI		 2250 if ((termios->c_cflag & CSIZE) == CS7)
2251 smr_val |= SCSMR_CHR;
2252 if (termios->c_cflag & PARENB)
2253 smr_val |= SCSMR_PE;
2254 if (termios->c_cflag & PARODD)
2255 smr_val |= SCSMR_PE | SCSMR_ODD;
2256 if (termios->c_cflag & CSTOPB)
2257 smr_val |= SCSMR_STOP;
2258
154280fd
MD		 2259 /*
2260 * earlyprintk comes here early on with port->uartclk set to zero.
2261 * the clock framework is not up and running at this point so here
2262 * we assume that 115200 is the maximum baud rate. please note that
2263 * the baud rate is not programmed during earlyprintk - it is assumed
2264 * that the previous boot loader has enabled required clocks and
2265 * setup the baud rate generator hardware for us already.
2266 */
f4998e55
GU		 2267 if (!port->uartclk) {
2268 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2269 goto done;
2270 }
1da177e4 2271
f4998e55
GU		 2272 for (i = 0; i < SCI_NUM_CLKS; i++)
2273 max_freq = max(max_freq, s->clk_rates[i]);
2274
69eee8e9 2275 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
f4998e55
GU		 2276 if (!baud)
2277 goto done;
2278
2279 /*
2280 * There can be multiple sources for the sampling clock. Find the one
2281 * that gives us the smallest deviation from the desired baud rate.
2282 */
2283
6af27bf2
GU		 2284 /* Optional Undivided External Clock */
2285 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2286 port->type != PORT_SCIFB) {
2287 err = sci_sck_calc(s, baud, &srr1);
2288 if (abs(err) < abs(min_err)) {
2289 best_clk = SCI_SCK;
2290 scr_val = SCSCR_CKE1;
2291 sccks = SCCKS_CKS;
2292 min_err = err;
2293 srr = srr1;
2294 if (!err)
2295 goto done;
2296 }
2297 }
2298
1270f865
GU		 2299 /* Optional BRG Frequency Divided External Clock */
2300 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2301 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2302 &srr1);
2303 if (abs(err) < abs(min_err)) {
2304 best_clk = SCI_SCIF_CLK;
2305 scr_val = SCSCR_CKE1;
2306 sccks = 0;
2307 min_err = err;
2308 dl = dl1;
2309 srr = srr1;
2310 if (!err)
2311 goto done;
2312 }
2313 }
2314
2315 /* Optional BRG Frequency Divided Internal Clock */
2316 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2317 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2318 &srr1);
2319 if (abs(err) < abs(min_err)) {
2320 best_clk = SCI_BRG_INT;
2321 scr_val = SCSCR_CKE1;
2322 sccks = SCCKS_XIN;
2323 min_err = err;
2324 dl = dl1;
2325 srr = srr1;
2326 if (!min_err)
2327 goto done;
f303b364
UH		 2328 }
2329 }
e108b2ca 2330
f4998e55
GU		 2331 /* Divided Functional Clock using standard Bit Rate Register */
2332 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2333 if (abs(err) < abs(min_err)) {
2334 best_clk = SCI_FCK;
6af27bf2 2335 scr_val = 0;
f4998e55
GU		 2336 min_err = err;
2337 brr = brr1;
2338 srr = srr1;
2339 cks = cks1;
2340 }
2341
2342done:
2343 if (best_clk >= 0)
2344 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2345 s->clks[best_clk], baud, min_err);
e108b2ca 2346
23241d43 2347 sci_port_enable(s);
36003386 2348
6af27bf2
GU		 2349 /*
2350 * Program the optional External Baud Rate Generator (BRG) first.
2351 * It controls the mux to select (H)SCK or frequency divided clock.
2352 */
1270f865
GU		 2353 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2354 serial_port_out(port, SCDL, dl);
6af27bf2 2355 serial_port_out(port, SCCKS, sccks);
1270f865 2356 }
1da177e4 2357
1ba76220 2358 sci_reset(port);
1da177e4
LT		 2359
2360 uart_update_timeout(port, termios->c_cflag, baud);
2361
f4998e55 2362 if (best_clk >= 0) {
92a05748
GU		 2363 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2364 switch (srr + 1) {
2365 case 5: smr_val |= SCSMR_SRC_5; break;
2366 case 7: smr_val |= SCSMR_SRC_7; break;
2367 case 11: smr_val |= SCSMR_SRC_11; break;
2368 case 13: smr_val |= SCSMR_SRC_13; break;
2369 case 16: smr_val |= SCSMR_SRC_16; break;
2370 case 17: smr_val |= SCSMR_SRC_17; break;
2371 case 19: smr_val |= SCSMR_SRC_19; break;
2372 case 27: smr_val |= SCSMR_SRC_27; break;
2373 }
f4998e55 2374 smr_val |= cks;
6af27bf2 2375 dev_dbg(port->dev,
1270f865
GU		 2376 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2377 scr_val, smr_val, brr, sccks, dl, srr);
fa2abb03 2378 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
f4998e55
GU		 2379 serial_port_out(port, SCSMR, smr_val);
2380 serial_port_out(port, SCBRR, brr);
2381 if (sci_getreg(port, HSSRR)->size)
f303b364 2382 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
f4998e55
GU		 2383
2384 /* Wait one bit interval */
2385 udelay((1000000 + (baud - 1)) / baud);
2386 } else {
2387 /* Don't touch the bit rate configuration */
2388 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
3a964abe
GU		 2389 smr_val |= serial_port_in(port, SCSMR) &
2390 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
f4998e55 2391 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
fa2abb03 2392 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
9d482cc3 2393 serial_port_out(port, SCSMR, smr_val);
f4998e55 2394 }
1da177e4 2395
d5701647 2396 sci_init_pins(port, termios->c_cflag);
0979e0e6 2397
33f50ffc
GU		 2398 port->status &= ~UPSTAT_AUTOCTS;
2399 s->autorts = false;
73c3d53f
PM		 2400 reg = sci_getreg(port, SCFCR);
2401 if (reg->size) {
b12bb29f 2402 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2403
33f50ffc
GU		 2404 if ((port->flags & UPF_HARD_FLOW) &&
2405 (termios->c_cflag & CRTSCTS)) {
2406 /* There is no CTS interrupt to restart the hardware */
2407 port->status |= UPSTAT_AUTOCTS;
2408 /* MCE is enabled when RTS is raised */
2409 s->autorts = true;
faf02f8f 2410 }
73c3d53f
PM		 2411
2412 /*
2413 * As we've done a sci_reset() above, ensure we don't
2414 * interfere with the FIFOs while toggling MCE. As the
2415 * reset values could still be set, simply mask them out.
2416 */
2417 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2418
b12bb29f 2419 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2420 }
5f76895e
GU		 2421 if (port->flags & UPF_HARD_FLOW) {
2422 /* Refresh (Auto) RTS */
2423 sci_set_mctrl(port, port->mctrl);
2424 }
b7a76e4b 2425
9f8325b3
LP		 2426 scr_val |= SCSCR_RE | SCSCR_TE |
2427 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
f4998e55 2428 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
fa2abb03 2429 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
92a05748
GU		 2430 if ((srr + 1 == 5) &&
2431 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2432 /*
2433 * In asynchronous mode, when the sampling rate is 1/5, first
2434 * received data may become invalid on some SCIFA and SCIFB.
2435 * To avoid this problem wait more than 1 serial data time (1
2436 * bit time x serial data number) after setting SCSCR.RE = 1.
2437 */
2438 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2439 }
1da177e4 2440
3089f381 2441 /*
5f6d8515 2442 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2443 * See serial_core.c::uart_update_timeout().
2444 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2445 * function calculates 1 jiffie for the data plus 5 jiffies for the
2446 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2447 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2448 * value obtained by this formula is too small. Therefore, if the value
2449 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381 2450 */
03940376
UH		 2451 /* byte size and parity */
2452 switch (termios->c_cflag & CSIZE) {
2453 case CS5:
2454 bits = 7;
2455 break;
2456 case CS6:
2457 bits = 8;
2458 break;
2459 case CS7:
2460 bits = 9;
2461 break;
2462 default:
2463 bits = 10;
2464 break;
2465 }
5f6d8515 2466
03940376
UH		 2467 if (termios->c_cflag & CSTOPB)
2468 bits++;
2469 if (termios->c_cflag & PARENB)
2470 bits++;
5f6d8515 2471
03940376
UH		 2472 s->rx_frame = (100 * bits * HZ) / (baud / 10);
2473#ifdef CONFIG_SERIAL_SH_SCI_DMA
2474 s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000);
2475 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2476 s->rx_timeout * 1000 / HZ, port->timeout);
2477 if (s->rx_timeout < msecs_to_jiffies(20))
2478 s->rx_timeout = msecs_to_jiffies(20);
3089f381
GL		 2479#endif
2480
1da177e4 2481 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2482 sci_start_rx(port);
36003386 2483
23241d43 2484 sci_port_disable(s);
f907c9ea
GU		 2485
2486 if (UART_ENABLE_MS(port, termios->c_cflag))
2487 sci_enable_ms(port);
1da177e4
LT		 2488}
2489
0174e5ca
TK		 2490static void sci_pm(struct uart_port *port, unsigned int state,
2491 unsigned int oldstate)
2492{
2493 struct sci_port *sci_port = to_sci_port(port);
2494
2495 switch (state) {
d3dfe5d9 2496 case UART_PM_STATE_OFF:
0174e5ca
TK		 2497 sci_port_disable(sci_port);
2498 break;
2499 default:
2500 sci_port_enable(sci_port);
2501 break;
2502 }
2503}
2504
1da177e4
LT		 2505static const char *sci_type(struct uart_port *port)
2506{
2507 switch (port->type) {
e7c98dc7
MT		 2508 case PORT_IRDA:
2509 return "irda";
2510 case PORT_SCI:
2511 return "sci";
2512 case PORT_SCIF:
2513 return "scif";
2514 case PORT_SCIFA:
2515 return "scifa";
d1d4b10c
GL		 2516 case PORT_SCIFB:
2517 return "scifb";
f303b364
UH		 2518 case PORT_HSCIF:
2519 return "hscif";
1da177e4
LT		 2520 }
2521
fa43972f 2522 return NULL;
1da177e4
LT		 2523}
2524
f6e9495d
PM		 2525static int sci_remap_port(struct uart_port *port)
2526{
e4d6f911 2527 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2528
2529 /*
2530 * Nothing to do if there's already an established membase.
2531 */
2532 if (port->membase)
2533 return 0;
2534
3d73f32b 2535 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e4d6f911 2536 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2537 if (unlikely(!port->membase)) {
2538 dev_err(port->dev, "can't remap port#%d\n", port->line);
2539 return -ENXIO;
2540 }
2541 } else {
2542 /*
2543 * For the simple (and majority of) cases where we don't
2544 * need to do any remapping, just cast the cookie
2545 * directly.
2546 */
3af4e960 2547 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2548 }
2549
2550 return 0;
2551}
2552
e2651647 2553static void sci_release_port(struct uart_port *port)
1da177e4 2554{
e4d6f911
YS		 2555 struct sci_port *sport = to_sci_port(port);
2556
3d73f32b 2557 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e2651647
PM		 2558 iounmap(port->membase);
2559 port->membase = NULL;
2560 }
2561
e4d6f911 2562 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2563}
2564
e2651647 2565static int sci_request_port(struct uart_port *port)
1da177e4 2566{
e2651647 2567 struct resource *res;
e4d6f911 2568 struct sci_port *sport = to_sci_port(port);
f6e9495d 2569 int ret;
1da177e4 2570
e4d6f911
YS		 2571 res = request_mem_region(port->mapbase, sport->reg_size,
2572 dev_name(port->dev));
2573 if (unlikely(res == NULL)) {
2574 dev_err(port->dev, "request_mem_region failed.");
e2651647 2575 return -EBUSY;
e4d6f911 2576 }
1da177e4 2577
f6e9495d
PM		 2578 ret = sci_remap_port(port);
2579 if (unlikely(ret != 0)) {
2580 release_resource(res);
2581 return ret;
7ff731ae 2582 }
e2651647
PM		 2583
2584 return 0;
2585}
2586
2587static void sci_config_port(struct uart_port *port, int flags)
2588{
2589 if (flags & UART_CONFIG_TYPE) {
2590 struct sci_port *sport = to_sci_port(port);
2591
2592 port->type = sport->cfg->type;
2593 sci_request_port(port);
2594 }
1da177e4
LT		 2595}
2596
2597static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2598{
1da177e4
LT		 2599 if (ser->baud_base < 2400)
2600 /* No paper tape reader for Mitch.. */
2601 return -EINVAL;
2602
2603 return 0;
2604}
2605
069a47e5 2606static const struct uart_ops sci_uart_ops = {
1da177e4
LT		 2607 .tx_empty = sci_tx_empty,
2608 .set_mctrl = sci_set_mctrl,
2609 .get_mctrl = sci_get_mctrl,
2610 .start_tx = sci_start_tx,
2611 .stop_tx = sci_stop_tx,
2612 .stop_rx = sci_stop_rx,
f907c9ea 2613 .enable_ms = sci_enable_ms,
1da177e4
LT		 2614 .break_ctl = sci_break_ctl,
2615 .startup = sci_startup,
2616 .shutdown = sci_shutdown,
1cf4a7ef 2617 .flush_buffer = sci_flush_buffer,
1da177e4 2618 .set_termios = sci_set_termios,
0174e5ca 2619 .pm = sci_pm,
1da177e4
LT		 2620 .type = sci_type,
2621 .release_port = sci_release_port,
2622 .request_port = sci_request_port,
2623 .config_port = sci_config_port,
2624 .verify_port = sci_verify_port,
07d2a1a1
PM		 2625#ifdef CONFIG_CONSOLE_POLL
2626 .poll_get_char = sci_poll_get_char,
2627 .poll_put_char = sci_poll_put_char,
2628#endif
1da177e4
LT		 2629};
2630
a9ec81f4
LP		 2631static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2632{
f4998e55
GU		 2633 const char *clk_names[] = {
2634 [SCI_FCK] = "fck",
6af27bf2 2635 [SCI_SCK] = "sck",
1270f865
GU		 2636 [SCI_BRG_INT] = "brg_int",
2637 [SCI_SCIF_CLK] = "scif_clk",
f4998e55
GU		 2638 };
2639 struct clk *clk;
2640 unsigned int i;
a9ec81f4 2641
6af27bf2
GU		 2642 if (sci_port->cfg->type == PORT_HSCIF)
2643 clk_names[SCI_SCK] = "hsck";
2644
f4998e55
GU		 2645 for (i = 0; i < SCI_NUM_CLKS; i++) {
2646 clk = devm_clk_get(dev, clk_names[i]);
2647 if (PTR_ERR(clk) == -EPROBE_DEFER)
2648 return -EPROBE_DEFER;
a9ec81f4 2649
f4998e55
GU		 2650 if (IS_ERR(clk) && i == SCI_FCK) {
2651 /*
2652 * "fck" used to be called "sci_ick", and we need to
2653 * maintain DT backward compatibility.
2654 */
2655 clk = devm_clk_get(dev, "sci_ick");
2656 if (PTR_ERR(clk) == -EPROBE_DEFER)
2657 return -EPROBE_DEFER;
a9ec81f4 2658
f4998e55
GU		 2659 if (!IS_ERR(clk))
2660 goto found;
a9ec81f4 2661
f4998e55
GU		 2662 /*
2663 * Not all SH platforms declare a clock lookup entry
2664 * for SCI devices, in which case we need to get the
2665 * global "peripheral_clk" clock.
2666 */
2667 clk = devm_clk_get(dev, "peripheral_clk");
2668 if (!IS_ERR(clk))
2669 goto found;
2670
2671 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2672 PTR_ERR(clk));
2673 return PTR_ERR(clk);
2674 }
2675
2676found:
2677 if (IS_ERR(clk))
2678 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2679 PTR_ERR(clk));
2680 else
2681 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2682 clk, clk);
2683 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2684 }
2685 return 0;
a9ec81f4
LP		 2686}
2687
daf5a895
LP		 2688static const struct sci_port_params *
2689sci_probe_regmap(const struct plat_sci_port *cfg)
2690{
2691 unsigned int regtype;
2692
2693 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2694 return &sci_port_params[cfg->regtype];
2695
2696 switch (cfg->type) {
2697 case PORT_SCI:
2698 regtype = SCIx_SCI_REGTYPE;
2699 break;
2700 case PORT_IRDA:
2701 regtype = SCIx_IRDA_REGTYPE;
2702 break;
2703 case PORT_SCIFA:
2704 regtype = SCIx_SCIFA_REGTYPE;
2705 break;
2706 case PORT_SCIFB:
2707 regtype = SCIx_SCIFB_REGTYPE;
2708 break;
2709 case PORT_SCIF:
2710 /*
2711 * The SH-4 is a bit of a misnomer here, although that's
2712 * where this particular port layout originated. This
2713 * configuration (or some slight variation thereof)
2714 * remains the dominant model for all SCIFs.
2715 */
2716 regtype = SCIx_SH4_SCIF_REGTYPE;
2717 break;
2718 case PORT_HSCIF:
2719 regtype = SCIx_HSCIF_REGTYPE;
2720 break;
2721 default:
2722 pr_err("Can't probe register map for given port\n");
2723 return NULL;
2724 }
2725
2726 return &sci_port_params[regtype];
2727}
2728
9671f099 2729static int sci_init_single(struct platform_device *dev,
1fcc91a6 2730 struct sci_port *sci_port, unsigned int index,
daf5a895 2731 const struct plat_sci_port *p, bool early)
e108b2ca 2732{
73a19e4c 2733 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2734 const struct resource *res;
2735 unsigned int i;
3127c6b2 2736 int ret;
e108b2ca 2737
50f0959a
PM		 2738 sci_port->cfg = p;
2739
73a19e4c
GL		 2740 port->ops = &sci_uart_ops;
2741 port->iotype = UPIO_MEM;
2742 port->line = index;
75136d48 2743
89b5c1ab
LP		 2744 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2745 if (res == NULL)
2746 return -ENOMEM;
1fcc91a6 2747
89b5c1ab 2748 port->mapbase = res->start;
e4d6f911 2749 sci_port->reg_size = resource_size(res);
1fcc91a6 2750
89b5c1ab
LP		 2751 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2752 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2753
89b5c1ab
LP		 2754 /* The SCI generates several interrupts. They can be muxed together or
2755 * connected to different interrupt lines. In the muxed case only one
2756 * interrupt resource is specified. In the non-muxed case three or four
2757 * interrupt resources are specified, as the BRI interrupt is optional.
2758 */
2759 if (sci_port->irqs[0] < 0)
2760 return -ENXIO;
1fcc91a6 2761
89b5c1ab
LP		 2762 if (sci_port->irqs[1] < 0) {
2763 sci_port->irqs[1] = sci_port->irqs[0];
2764 sci_port->irqs[2] = sci_port->irqs[0];
2765 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2766 }
2767
daf5a895
LP		 2768 sci_port->params = sci_probe_regmap(p);
2769 if (unlikely(sci_port->params == NULL))
2770 return -EINVAL;
e095ee6b 2771
18e8cf15
UH		 2772 switch (p->type) {
2773 case PORT_SCIFB:
2774 sci_port->rx_trigger = 48;
2775 break;
2776 case PORT_HSCIF:
2777 sci_port->rx_trigger = 64;
2778 break;
2779 case PORT_SCIFA:
2780 sci_port->rx_trigger = 32;
2781 break;
2782 case PORT_SCIF:
2783 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2784 /* RX triggering not implemented for this IP */
2785 sci_port->rx_trigger = 1;
2786 else
2787 sci_port->rx_trigger = 8;
2788 break;
2789 default:
2790 sci_port->rx_trigger = 1;
2791 break;
2792 }
2793
03940376 2794 sci_port->rx_fifo_timeout = 0;
fa2abb03 2795 sci_port->hscif_tot = 0;
03940376 2796
878fbb91
LP		 2797 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2798 * match the SoC datasheet, this should be investigated. Let platform
2799 * data override the sampling rate for now.
ec09c5eb 2800 */
b2f20ed9
LP		 2801 sci_port->sampling_rate_mask = p->sampling_rate
2802 ? SCI_SR(p->sampling_rate)
2803 : sci_port->params->sampling_rate_mask;
ec09c5eb 2804
1fcc91a6 2805 if (!early) {
a9ec81f4
LP		 2806 ret = sci_init_clocks(sci_port, &dev->dev);
2807 if (ret < 0)
2808 return ret;
c7ed1ab3 2809
73a19e4c 2810 port->dev = &dev->dev;
5e50d2d6
MD		 2811
2812 pm_runtime_enable(&dev->dev);
7b6fd3bf 2813 }
e108b2ca 2814
ce6738b6 2815 port->type = p->type;
3d73f32b 2816 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
b2f20ed9 2817 port->fifosize = sci_port->params->fifosize;
73a19e4c 2818
dfc80387
LP		 2819 if (port->type == PORT_SCI) {
2820 if (sci_port->reg_size >= 0x20)
2821 port->regshift = 2;
2822 else
2823 port->regshift = 1;
2824 }
2825
ce6738b6 2826 /*
61a6976b 2827 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2828 * for the multi-IRQ ports, which is where we are primarily
2829 * concerned with the shutdown path synchronization.
2830 *
2831 * For the muxed case there's nothing more to do.
2832 */
1fcc91a6 2833 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2834 port->irqflags = 0;
73a19e4c 2835
61a6976b
PM		 2836 port->serial_in = sci_serial_in;
2837 port->serial_out = sci_serial_out;
2838
c7ed1ab3 2839 return 0;
e108b2ca
PM		 2840}
2841
6dae1421
LP		 2842static void sci_cleanup_single(struct sci_port *port)
2843{
6dae1421
LP		 2844 pm_runtime_disable(port->port.dev);
2845}
2846
0b0cced1
YS		 2847#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2848 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
dc8e6f5b
MD		 2849static void serial_console_putchar(struct uart_port *port, int ch)
2850{
2851 sci_poll_put_char(port, ch);
2852}
2853
1da177e4
LT		 2854/*
2855 * Print a string to the serial port trying not to disturb
2856 * any possible real use of the port...
2857 */
2858static void serial_console_write(struct console *co, const char *s,
2859 unsigned count)
2860{
906b17dc
PM		 2861 struct sci_port *sci_port = &sci_ports[co->index];
2862 struct uart_port *port = &sci_port->port;
a67969b5 2863 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2864 unsigned long flags;
2865 int locked = 1;
2866
2867 local_irq_save(flags);
0b0cced1 2868#if defined(SUPPORT_SYSRQ)
40f70c03
SK		 2869 if (port->sysrq)
2870 locked = 0;
0b0cced1
YS		 2871 else
2872#endif
2873 if (oops_in_progress)
40f70c03
SK		 2874 locked = spin_trylock(&port->lock);
2875 else
2876 spin_lock(&port->lock);
2877
a67969b5 2878 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2879 ctrl = serial_port_in(port, SCSCR);
9f8325b3
LP		 2880 ctrl_temp = SCSCR_RE | SCSCR_TE |
2881 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
a67969b5 2882 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 2883 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
07d2a1a1 2884
501b825d 2885 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2886
2887 /* wait until fifo is empty and last bit has been transmitted */
2888 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2889 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2890 cpu_relax();
40f70c03
SK		 2891
2892 /* restore the SCSCR */
2893 serial_port_out(port, SCSCR, ctrl);
2894
2895 if (locked)
2896 spin_unlock(&port->lock);
2897 local_irq_restore(flags);
1da177e4
LT		 2898}
2899
9671f099 2900static int serial_console_setup(struct console *co, char *options)
1da177e4 2901{
dc8e6f5b 2902 struct sci_port *sci_port;
1da177e4
LT		 2903 struct uart_port *port;
2904 int baud = 115200;
2905 int bits = 8;
2906 int parity = 'n';
2907 int flow = 'n';
2908 int ret;
2909
e108b2ca 2910 /*
906b17dc 2911 * Refuse to handle any bogus ports.
1da177e4 2912 */
906b17dc 2913 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2914 return -ENODEV;
e108b2ca 2915
906b17dc
PM		 2916 sci_port = &sci_ports[co->index];
2917 port = &sci_port->port;
2918
b2267a6b
AC		 2919 /*
2920 * Refuse to handle uninitialized ports.
2921 */
2922 if (!port->ops)
2923 return -ENODEV;
2924
f6e9495d
PM		 2925 ret = sci_remap_port(port);
2926 if (unlikely(ret != 0))
2927 return ret;
e108b2ca 2928
1da177e4
LT		 2929 if (options)
2930 uart_parse_options(options, &baud, &parity, &bits, &flow);
2931
ab7cfb55 2932 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2933}
2934
2935static struct console serial_console = {
2936 .name = "ttySC",
906b17dc 2937 .device = uart_console_device,
1da177e4
LT		 2938 .write = serial_console_write,
2939 .setup = serial_console_setup,
fa5da2f7 2940 .flags = CON_PRINTBUFFER,
1da177e4 2941 .index = -1,
906b17dc 2942 .data = &sci_uart_driver,
1da177e4
LT		 2943};
2944
7b6fd3bf
MD		 2945static struct console early_serial_console = {
2946 .name = "early_ttySC",
2947 .write = serial_console_write,
2948 .flags = CON_PRINTBUFFER,
906b17dc 2949 .index = -1,
7b6fd3bf 2950};
ecdf8a46 2951
7b6fd3bf
MD		 2952static char early_serial_buf[32];
2953
9671f099 2954static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2955{
daf5a895 2956 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2957
2958 if (early_serial_console.data)
2959 return -EEXIST;
2960
2961 early_serial_console.index = pdev->id;
ecdf8a46 2962
1fcc91a6 2963 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2964
2965 serial_console_setup(&early_serial_console, early_serial_buf);
2966
2967 if (!strstr(early_serial_buf, "keep"))
2968 early_serial_console.flags |= CON_BOOT;
2969
2970 register_console(&early_serial_console);
2971 return 0;
2972}
6a8c9799
NI		 2973
2974#define SCI_CONSOLE (&serial_console)
2975
ecdf8a46 2976#else
9671f099 2977static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2978{
2979 return -EINVAL;
2980}
1da177e4 2981
6a8c9799
NI		 2982#define SCI_CONSOLE NULL
2983
0b0cced1 2984#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 2985
6c13d5d2 2986static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4 2987
352b9266 2988static DEFINE_MUTEX(sci_uart_registration_lock);
1da177e4
LT		 2989static struct uart_driver sci_uart_driver = {
2990 .owner = THIS_MODULE,
2991 .driver_name = "sci",
1da177e4
LT		 2992 .dev_name = "ttySC",
2993 .major = SCI_MAJOR,
2994 .minor = SCI_MINOR_START,
e108b2ca 2995 .nr = SCI_NPORTS,
1da177e4
LT		 2996 .cons = SCI_CONSOLE,
2997};
2998
54507f6e 2999static int sci_remove(struct platform_device *dev)
e552de24 3000{
d535a230 3001 struct sci_port *port = platform_get_drvdata(dev);
e552de24 3002
d535a230
PM		 3003 uart_remove_one_port(&sci_uart_driver, &port->port);
3004
6dae1421 3005 sci_cleanup_single(port);
e552de24 3006
5d23188a
UH		 3007 if (port->port.fifosize > 1) {
3008 sysfs_remove_file(&dev->dev.kobj,
3009 &dev_attr_rx_fifo_trigger.attr);
3010 }
fa2abb03
UH		 3011 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
3012 port->port.type == PORT_HSCIF) {
5d23188a
UH		 3013 sysfs_remove_file(&dev->dev.kobj,
3014 &dev_attr_rx_fifo_timeout.attr);
3015 }
3016
e552de24
MD		 3017 return 0;
3018}
3019
bd2238fb
GU		 3020
3021#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3022#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3023#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
20bdcab8
BH		 3024
3025static const struct of_device_id of_sci_match[] = {
f443ff80
GU		 3026 /* SoC-specific types */
3027 {
3028 .compatible = "renesas,scif-r7s72100",
3029 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3030 },
9ed44bb2
GU		 3031 /* Family-specific types */
3032 {
3033 .compatible = "renesas,rcar-gen1-scif",
3034 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3035 }, {
3036 .compatible = "renesas,rcar-gen2-scif",
3037 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3038 }, {
3039 .compatible = "renesas,rcar-gen3-scif",
3040 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3041 },
f443ff80 3042 /* Generic types */
20bdcab8
BH		 3043 {
3044 .compatible = "renesas,scif",
bd2238fb 3045 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
20bdcab8
BH		 3046 }, {
3047 .compatible = "renesas,scifa",
bd2238fb 3048 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
20bdcab8
BH		 3049 }, {
3050 .compatible = "renesas,scifb",
bd2238fb 3051 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
20bdcab8
BH		 3052 }, {
3053 .compatible = "renesas,hscif",
bd2238fb 3054 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
e1d0be61
YS		 3055 }, {
3056 .compatible = "renesas,sci",
bd2238fb 3057 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
20bdcab8
BH		 3058 }, {
3059 /* Terminator */
3060 },
3061};
3062MODULE_DEVICE_TABLE(of, of_sci_match);
3063
54b12c48
GU		 3064static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3065 unsigned int *dev_id)
20bdcab8
BH		 3066{
3067 struct device_node *np = pdev->dev.of_node;
3068 const struct of_device_id *match;
20bdcab8 3069 struct plat_sci_port *p;
97ed9790 3070 struct sci_port *sp;
20bdcab8
BH		 3071 int id;
3072
3073 if (!IS_ENABLED(CONFIG_OF) || !np)
3074 return NULL;
3075
495bb47c 3076 match = of_match_node(of_sci_match, np);
20bdcab8
BH		 3077 if (!match)
3078 return NULL;
3079
20bdcab8 3080 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 3081 if (!p)
20bdcab8 3082 return NULL;
20bdcab8 3083
2095fc76 3084 /* Get the line number from the aliases node. */
20bdcab8
BH		 3085 id = of_alias_get_id(np, "serial");
3086 if (id < 0) {
3087 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3088 return NULL;
3089 }
3090
97ed9790 3091 sp = &sci_ports[id];
20bdcab8
BH		 3092 *dev_id = id;
3093
bd2238fb
GU		 3094 p->type = SCI_OF_TYPE(match->data);
3095 p->regtype = SCI_OF_REGTYPE(match->data);
20bdcab8 3096
43c61286 3097 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
861a70ab 3098
20bdcab8
BH		 3099 return p;
3100}
3101
9671f099 3102static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 3103 unsigned int index,
3104 struct plat_sci_port *p,
3105 struct sci_port *sciport)
3106{
0ee70712
MD		 3107 int ret;
3108
3109 /* Sanity check */
3110 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 3111 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 3112 index+1, SCI_NPORTS);
9b971cd2 3113 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 3114 return -EINVAL;
0ee70712
MD		 3115 }
3116
352b9266
SS		 3117 mutex_lock(&sci_uart_registration_lock);
3118 if (!sci_uart_driver.state) {
3119 ret = uart_register_driver(&sci_uart_driver);
3120 if (ret) {
3121 mutex_unlock(&sci_uart_registration_lock);
3122 return ret;
3123 }
3124 }
3125 mutex_unlock(&sci_uart_registration_lock);
3126
1fcc91a6 3127 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 3128 if (ret)
3129 return ret;
0ee70712 3130
f907c9ea
GU		 3131 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3132 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3133 return PTR_ERR(sciport->gpios);
3134
97ed9790 3135 if (sciport->has_rtscts) {
f907c9ea
GU		 3136 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3137 UART_GPIO_CTS)) ||
3138 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3139 UART_GPIO_RTS))) {
3140 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3141 return -EINVAL;
3142 }
33f50ffc 3143 sciport->port.flags |= UPF_HARD_FLOW;
f907c9ea
GU		 3144 }
3145
6dae1421
LP		 3146 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3147 if (ret) {
3148 sci_cleanup_single(sciport);
3149 return ret;
3150 }
3151
3152 return 0;
0ee70712
MD		 3153}
3154
9671f099 3155static int sci_probe(struct platform_device *dev)
1da177e4 3156{
20bdcab8
BH		 3157 struct plat_sci_port *p;
3158 struct sci_port *sp;
3159 unsigned int dev_id;
ecdf8a46 3160 int ret;
d535a230 3161
ecdf8a46
PM		 3162 /*
3163 * If we've come here via earlyprintk initialization, head off to
3164 * the special early probe. We don't have sufficient device state
3165 * to make it beyond this yet.
3166 */
3167 if (is_early_platform_device(dev))
3168 return sci_probe_earlyprintk(dev);
7b6fd3bf 3169
20bdcab8
BH		 3170 if (dev->dev.of_node) {
3171 p = sci_parse_dt(dev, &dev_id);
3172 if (p == NULL)
3173 return -EINVAL;
3174 } else {
3175 p = dev->dev.platform_data;
3176 if (p == NULL) {
3177 dev_err(&dev->dev, "no platform data supplied\n");
3178 return -EINVAL;
3179 }
3180
3181 dev_id = dev->id;
3182 }
3183
3184 sp = &sci_ports[dev_id];
d535a230 3185 platform_set_drvdata(dev, sp);
e552de24 3186
20bdcab8 3187 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 3188 if (ret)
6dae1421 3189 return ret;
e552de24 3190
5d23188a
UH		 3191 if (sp->port.fifosize > 1) {
3192 ret = sysfs_create_file(&dev->dev.kobj,
3193 &dev_attr_rx_fifo_trigger.attr);
3194 if (ret)
3195 return ret;
3196 }
fa2abb03
UH		 3197 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3198 sp->port.type == PORT_HSCIF) {
5d23188a
UH		 3199 ret = sysfs_create_file(&dev->dev.kobj,
3200 &dev_attr_rx_fifo_timeout.attr);
3201 if (ret) {
3202 if (sp->port.fifosize > 1) {
3203 sysfs_remove_file(&dev->dev.kobj,
3204 &dev_attr_rx_fifo_trigger.attr);
3205 }
3206 return ret;
3207 }
3208 }
3209
1da177e4
LT		 3210#ifdef CONFIG_SH_STANDARD_BIOS
3211 sh_bios_gdb_detach();
3212#endif
3213
e108b2ca 3214 return 0;
1da177e4
LT		 3215}
3216
cb876341 3217static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 3218{
d535a230 3219 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3220
d535a230
PM		 3221 if (sport)
3222 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 3223
e108b2ca
PM		 3224 return 0;
3225}
1da177e4 3226
cb876341 3227static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 3228{
d535a230 3229 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3230
d535a230
PM		 3231 if (sport)
3232 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 3233
3234 return 0;
3235}
3236
cb876341 3237static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 3238
e108b2ca
PM		 3239static struct platform_driver sci_driver = {
3240 .probe = sci_probe,
b9e39c89 3241 .remove = sci_remove,
e108b2ca
PM		 3242 .driver = {
3243 .name = "sh-sci",
6daa79b3 3244 .pm = &sci_dev_pm_ops,
20bdcab8 3245 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 3246 },
3247};
3248
3249static int __init sci_init(void)
3250{
6c13d5d2 3251 pr_info("%s\n", banner);
e108b2ca 3252
352b9266 3253 return platform_driver_register(&sci_driver);
e108b2ca
PM		 3254}
3255
3256static void __exit sci_exit(void)
3257{
3258 platform_driver_unregister(&sci_driver);
352b9266
SS		 3259
3260 if (sci_uart_driver.state)
3261 uart_unregister_driver(&sci_uart_driver);
1da177e4
LT		 3262}
3263
7b6fd3bf
MD		 3264#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3265early_platform_init_buffer("earlyprintk", &sci_driver,
3266 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3267#endif
0b0cced1
YS		 3268#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3269static struct __init plat_sci_port port_cfg;
3270
3271static int __init early_console_setup(struct earlycon_device *device,
3272 int type)
3273{
3274 if (!device->port.membase)
3275 return -ENODEV;
3276
3277 device->port.serial_in = sci_serial_in;
3278 device->port.serial_out = sci_serial_out;
3279 device->port.type = type;
3280 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
daf5a895 3281 port_cfg.type = type;
0b0cced1 3282 sci_ports[0].cfg = &port_cfg;
daf5a895 3283 sci_ports[0].params = sci_probe_regmap(&port_cfg);
9f8325b3
LP		 3284 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3285 sci_serial_out(&sci_ports[0].port, SCSCR,
3286 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
0b0cced1
YS		 3287
3288 device->con->write = serial_console_write;
3289 return 0;
3290}
3291static int __init sci_early_console_setup(struct earlycon_device *device,
3292 const char *opt)
3293{
3294 return early_console_setup(device, PORT_SCI);
3295}
3296static int __init scif_early_console_setup(struct earlycon_device *device,
3297 const char *opt)
3298{
3299 return early_console_setup(device, PORT_SCIF);
3300}
3301static int __init scifa_early_console_setup(struct earlycon_device *device,
3302 const char *opt)
3303{
3304 return early_console_setup(device, PORT_SCIFA);
3305}
3306static int __init scifb_early_console_setup(struct earlycon_device *device,
3307 const char *opt)
3308{
3309 return early_console_setup(device, PORT_SCIFB);
3310}
3311static int __init hscif_early_console_setup(struct earlycon_device *device,
3312 const char *opt)
3313{
3314 return early_console_setup(device, PORT_HSCIF);
3315}
3316
0b0cced1 3317OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
0b0cced1 3318OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
0b0cced1 3319OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
0b0cced1 3320OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
0b0cced1
YS		 3321OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3322#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3323
1da177e4
LT		 3324module_init(sci_init);
3325module_exit(sci_exit);
3326
e108b2ca 3327MODULE_LICENSE("GPL");
e169c139 3328MODULE_ALIAS("platform:sh-sci");
7f405f9c 3329MODULE_AUTHOR("Paul Mundt");
f303b364 3330MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
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