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serial: sh-sci: Avoid overflow in sci_baud_calc_hscif()
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
2e0842a1 84 unsigned int overrun_reg;
75c249fd 85 unsigned int overrun_mask;
3ae988d9 86 unsigned int error_mask;
5da0f468 87 unsigned int error_clear;
ec09c5eb 88 unsigned int sampling_rate;
e4d6f911 89 resource_size_t reg_size;
e108b2ca 90
e108b2ca
PM		 91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
1534a3b3 94
c7ed1ab3
PM		 95 /* Function clock */
96 struct clk *fclk;
edad1f20 97
1fcc91a6 98 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 99 char *irqstr[SCIx_NR_IRQS];
100
73a19e4c
GL		 101 struct dma_chan *chan_tx;
102 struct dma_chan *chan_rx;
f43dc23d 103
73a19e4c 104#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 105 dma_cookie_t cookie_tx;
106 dma_cookie_t cookie_rx[2];
107 dma_cookie_t active_rx;
79904420
GU		 108 dma_addr_t tx_dma_addr;
109 unsigned int tx_dma_len;
73a19e4c 110 struct scatterlist sg_rx[2];
7b39d901 111 void *rx_buf[2];
73a19e4c 112 size_t buf_len_rx;
73a19e4c 113 struct work_struct work_tx;
73a19e4c 114 struct timer_list rx_timer;
3089f381 115 unsigned int rx_timeout;
73a19e4c 116#endif
e552de24 117
d535a230 118 struct notifier_block freq_transition;
e108b2ca
PM		 119};
120
e108b2ca 121#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 122
e108b2ca
PM		 123static struct sci_port sci_ports[SCI_NPORTS];
124static struct uart_driver sci_uart_driver;
1da177e4 125
e7c98dc7
MT		 126static inline struct sci_port *
127to_sci_port(struct uart_port *uart)
128{
129 return container_of(uart, struct sci_port, port);
130}
131
61a6976b
PM		 132struct plat_sci_reg {
133 u8 offset, size;
134};
135
136/* Helper for invalidating specific entries of an inherited map. */
137#define sci_reg_invalid { .offset = 0, .size = 0 }
138
d3184e68 139static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 140 [SCIx_PROBE_REGTYPE] = {
141 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
142 },
143
144 /*
145 * Common SCI definitions, dependent on the port's regshift
146 * value.
147 */
148 [SCIx_SCI_REGTYPE] = {
149 [SCSMR] = { 0x00, 8 },
150 [SCBRR] = { 0x01, 8 },
151 [SCSCR] = { 0x02, 8 },
152 [SCxTDR] = { 0x03, 8 },
153 [SCxSR] = { 0x04, 8 },
154 [SCxRDR] = { 0x05, 8 },
155 [SCFCR] = sci_reg_invalid,
156 [SCFDR] = sci_reg_invalid,
157 [SCTFDR] = sci_reg_invalid,
158 [SCRFDR] = sci_reg_invalid,
159 [SCSPTR] = sci_reg_invalid,
160 [SCLSR] = sci_reg_invalid,
f303b364 161 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 162 [SCPCR] = sci_reg_invalid,
163 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 164 },
165
166 /*
167 * Common definitions for legacy IrDA ports, dependent on
168 * regshift value.
169 */
170 [SCIx_IRDA_REGTYPE] = {
171 [SCSMR] = { 0x00, 8 },
172 [SCBRR] = { 0x01, 8 },
173 [SCSCR] = { 0x02, 8 },
174 [SCxTDR] = { 0x03, 8 },
175 [SCxSR] = { 0x04, 8 },
176 [SCxRDR] = { 0x05, 8 },
177 [SCFCR] = { 0x06, 8 },
178 [SCFDR] = { 0x07, 16 },
179 [SCTFDR] = sci_reg_invalid,
180 [SCRFDR] = sci_reg_invalid,
181 [SCSPTR] = sci_reg_invalid,
182 [SCLSR] = sci_reg_invalid,
f303b364 183 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 184 [SCPCR] = sci_reg_invalid,
185 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 186 },
187
188 /*
189 * Common SCIFA definitions.
190 */
191 [SCIx_SCIFA_REGTYPE] = {
192 [SCSMR] = { 0x00, 16 },
193 [SCBRR] = { 0x04, 8 },
194 [SCSCR] = { 0x08, 16 },
195 [SCxTDR] = { 0x20, 8 },
196 [SCxSR] = { 0x14, 16 },
197 [SCxRDR] = { 0x24, 8 },
198 [SCFCR] = { 0x18, 16 },
199 [SCFDR] = { 0x1c, 16 },
200 [SCTFDR] = sci_reg_invalid,
201 [SCRFDR] = sci_reg_invalid,
202 [SCSPTR] = sci_reg_invalid,
203 [SCLSR] = sci_reg_invalid,
f303b364 204 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 205 [SCPCR] = { 0x30, 16 },
206 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 207 },
208
209 /*
210 * Common SCIFB definitions.
211 */
212 [SCIx_SCIFB_REGTYPE] = {
213 [SCSMR] = { 0x00, 16 },
214 [SCBRR] = { 0x04, 8 },
215 [SCSCR] = { 0x08, 16 },
216 [SCxTDR] = { 0x40, 8 },
217 [SCxSR] = { 0x14, 16 },
218 [SCxRDR] = { 0x60, 8 },
219 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 220 [SCFDR] = sci_reg_invalid,
221 [SCTFDR] = { 0x38, 16 },
222 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 223 [SCSPTR] = sci_reg_invalid,
224 [SCLSR] = sci_reg_invalid,
f303b364 225 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 226 [SCPCR] = { 0x30, 16 },
227 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 228 },
229
3af1f8a4
PE		 230 /*
231 * Common SH-2(A) SCIF definitions for ports with FIFO data
232 * count registers.
233 */
234 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
235 [SCSMR] = { 0x00, 16 },
236 [SCBRR] = { 0x04, 8 },
237 [SCSCR] = { 0x08, 16 },
238 [SCxTDR] = { 0x0c, 8 },
239 [SCxSR] = { 0x10, 16 },
240 [SCxRDR] = { 0x14, 8 },
241 [SCFCR] = { 0x18, 16 },
242 [SCFDR] = { 0x1c, 16 },
243 [SCTFDR] = sci_reg_invalid,
244 [SCRFDR] = sci_reg_invalid,
245 [SCSPTR] = { 0x20, 16 },
246 [SCLSR] = { 0x24, 16 },
f303b364 247 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 248 [SCPCR] = sci_reg_invalid,
249 [SCPDR] = sci_reg_invalid,
3af1f8a4
PE		 250 },
251
61a6976b
PM		 252 /*
253 * Common SH-3 SCIF definitions.
254 */
255 [SCIx_SH3_SCIF_REGTYPE] = {
256 [SCSMR] = { 0x00, 8 },
257 [SCBRR] = { 0x02, 8 },
258 [SCSCR] = { 0x04, 8 },
259 [SCxTDR] = { 0x06, 8 },
260 [SCxSR] = { 0x08, 16 },
261 [SCxRDR] = { 0x0a, 8 },
262 [SCFCR] = { 0x0c, 8 },
263 [SCFDR] = { 0x0e, 16 },
264 [SCTFDR] = sci_reg_invalid,
265 [SCRFDR] = sci_reg_invalid,
266 [SCSPTR] = sci_reg_invalid,
267 [SCLSR] = sci_reg_invalid,
f303b364 268 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 269 [SCPCR] = sci_reg_invalid,
270 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 271 },
272
273 /*
274 * Common SH-4(A) SCIF(B) definitions.
275 */
276 [SCIx_SH4_SCIF_REGTYPE] = {
277 [SCSMR] = { 0x00, 16 },
278 [SCBRR] = { 0x04, 8 },
279 [SCSCR] = { 0x08, 16 },
280 [SCxTDR] = { 0x0c, 8 },
281 [SCxSR] = { 0x10, 16 },
282 [SCxRDR] = { 0x14, 8 },
283 [SCFCR] = { 0x18, 16 },
284 [SCFDR] = { 0x1c, 16 },
285 [SCTFDR] = sci_reg_invalid,
286 [SCRFDR] = sci_reg_invalid,
287 [SCSPTR] = { 0x20, 16 },
288 [SCLSR] = { 0x24, 16 },
f303b364 289 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 290 [SCPCR] = sci_reg_invalid,
291 [SCPDR] = sci_reg_invalid,
f303b364
UH		 292 },
293
294 /*
295 * Common HSCIF definitions.
296 */
297 [SCIx_HSCIF_REGTYPE] = {
298 [SCSMR] = { 0x00, 16 },
299 [SCBRR] = { 0x04, 8 },
300 [SCSCR] = { 0x08, 16 },
301 [SCxTDR] = { 0x0c, 8 },
302 [SCxSR] = { 0x10, 16 },
303 [SCxRDR] = { 0x14, 8 },
304 [SCFCR] = { 0x18, 16 },
305 [SCFDR] = { 0x1c, 16 },
306 [SCTFDR] = sci_reg_invalid,
307 [SCRFDR] = sci_reg_invalid,
308 [SCSPTR] = { 0x20, 16 },
309 [SCLSR] = { 0x24, 16 },
310 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 311 [SCPCR] = sci_reg_invalid,
312 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 313 },
314
315 /*
316 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
317 * register.
318 */
319 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
320 [SCSMR] = { 0x00, 16 },
321 [SCBRR] = { 0x04, 8 },
322 [SCSCR] = { 0x08, 16 },
323 [SCxTDR] = { 0x0c, 8 },
324 [SCxSR] = { 0x10, 16 },
325 [SCxRDR] = { 0x14, 8 },
326 [SCFCR] = { 0x18, 16 },
327 [SCFDR] = { 0x1c, 16 },
328 [SCTFDR] = sci_reg_invalid,
329 [SCRFDR] = sci_reg_invalid,
330 [SCSPTR] = sci_reg_invalid,
331 [SCLSR] = { 0x24, 16 },
f303b364 332 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 333 [SCPCR] = sci_reg_invalid,
334 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 335 },
336
337 /*
338 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
339 * count registers.
340 */
341 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
342 [SCSMR] = { 0x00, 16 },
343 [SCBRR] = { 0x04, 8 },
344 [SCSCR] = { 0x08, 16 },
345 [SCxTDR] = { 0x0c, 8 },
346 [SCxSR] = { 0x10, 16 },
347 [SCxRDR] = { 0x14, 8 },
348 [SCFCR] = { 0x18, 16 },
349 [SCFDR] = { 0x1c, 16 },
350 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
351 [SCRFDR] = { 0x20, 16 },
352 [SCSPTR] = { 0x24, 16 },
353 [SCLSR] = { 0x28, 16 },
f303b364 354 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 355 [SCPCR] = sci_reg_invalid,
356 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 357 },
358
359 /*
360 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
361 * registers.
362 */
363 [SCIx_SH7705_SCIF_REGTYPE] = {
364 [SCSMR] = { 0x00, 16 },
365 [SCBRR] = { 0x04, 8 },
366 [SCSCR] = { 0x08, 16 },
367 [SCxTDR] = { 0x20, 8 },
368 [SCxSR] = { 0x14, 16 },
369 [SCxRDR] = { 0x24, 8 },
370 [SCFCR] = { 0x18, 16 },
371 [SCFDR] = { 0x1c, 16 },
372 [SCTFDR] = sci_reg_invalid,
373 [SCRFDR] = sci_reg_invalid,
374 [SCSPTR] = sci_reg_invalid,
375 [SCLSR] = sci_reg_invalid,
f303b364 376 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 377 [SCPCR] = sci_reg_invalid,
378 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 379 },
380};
381
72b294cf
PM		 382#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
383
61a6976b
PM		 384/*
385 * The "offset" here is rather misleading, in that it refers to an enum
386 * value relative to the port mapping rather than the fixed offset
387 * itself, which needs to be manually retrieved from the platform's
388 * register map for the given port.
389 */
390static unsigned int sci_serial_in(struct uart_port *p, int offset)
391{
d3184e68 392 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 393
394 if (reg->size == 8)
395 return ioread8(p->membase + (reg->offset << p->regshift));
396 else if (reg->size == 16)
397 return ioread16(p->membase + (reg->offset << p->regshift));
398 else
399 WARN(1, "Invalid register access\n");
400
401 return 0;
402}
403
404static void sci_serial_out(struct uart_port *p, int offset, int value)
405{
d3184e68 406 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 407
408 if (reg->size == 8)
409 iowrite8(value, p->membase + (reg->offset << p->regshift));
410 else if (reg->size == 16)
411 iowrite16(value, p->membase + (reg->offset << p->regshift));
412 else
413 WARN(1, "Invalid register access\n");
414}
415
61a6976b
PM		 416static int sci_probe_regmap(struct plat_sci_port *cfg)
417{
418 switch (cfg->type) {
419 case PORT_SCI:
420 cfg->regtype = SCIx_SCI_REGTYPE;
421 break;
422 case PORT_IRDA:
423 cfg->regtype = SCIx_IRDA_REGTYPE;
424 break;
425 case PORT_SCIFA:
426 cfg->regtype = SCIx_SCIFA_REGTYPE;
427 break;
428 case PORT_SCIFB:
429 cfg->regtype = SCIx_SCIFB_REGTYPE;
430 break;
431 case PORT_SCIF:
432 /*
433 * The SH-4 is a bit of a misnomer here, although that's
434 * where this particular port layout originated. This
435 * configuration (or some slight variation thereof)
436 * remains the dominant model for all SCIFs.
437 */
438 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
439 break;
f303b364
UH		 440 case PORT_HSCIF:
441 cfg->regtype = SCIx_HSCIF_REGTYPE;
442 break;
61a6976b 443 default:
6c13d5d2 444 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 445 return -EINVAL;
446 }
447
448 return 0;
449}
450
23241d43
PM		 451static void sci_port_enable(struct sci_port *sci_port)
452{
453 if (!sci_port->port.dev)
454 return;
455
456 pm_runtime_get_sync(sci_port->port.dev);
457
b016b646 458 clk_prepare_enable(sci_port->fclk);
a9ec81f4 459 sci_port->port.uartclk = clk_get_rate(sci_port->fclk);
23241d43
PM		 460}
461
462static void sci_port_disable(struct sci_port *sci_port)
463{
464 if (!sci_port->port.dev)
465 return;
466
caec7038
LP		 467 /* Cancel the break timer to ensure that the timer handler will not try
468 * to access the hardware with clocks and power disabled. Reset the
469 * break flag to make the break debouncing state machine ready for the
470 * next break.
471 */
472 del_timer_sync(&sci_port->break_timer);
473 sci_port->break_flag = 0;
474
b016b646 475 clk_disable_unprepare(sci_port->fclk);
23241d43
PM		 476
477 pm_runtime_put_sync(sci_port->port.dev);
478}
479
e1910fcd
GU		 480static inline unsigned long port_rx_irq_mask(struct uart_port *port)
481{
482 /*
483 * Not all ports (such as SCIFA) will support REIE. Rather than
484 * special-casing the port type, we check the port initialization
485 * IRQ enable mask to see whether the IRQ is desired at all. If
486 * it's unset, it's logically inferred that there's no point in
487 * testing for it.
488 */
489 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
490}
491
492static void sci_start_tx(struct uart_port *port)
493{
494 struct sci_port *s = to_sci_port(port);
495 unsigned short ctrl;
496
497#ifdef CONFIG_SERIAL_SH_SCI_DMA
498 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
499 u16 new, scr = serial_port_in(port, SCSCR);
500 if (s->chan_tx)
501 new = scr | SCSCR_TDRQE;
502 else
503 new = scr & ~SCSCR_TDRQE;
504 if (new != scr)
505 serial_port_out(port, SCSCR, new);
506 }
507
508 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
509 dma_submit_error(s->cookie_tx)) {
510 s->cookie_tx = 0;
511 schedule_work(&s->work_tx);
512 }
513#endif
514
515 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
516 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
517 ctrl = serial_port_in(port, SCSCR);
518 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
519 }
520}
521
522static void sci_stop_tx(struct uart_port *port)
523{
524 unsigned short ctrl;
525
526 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
527 ctrl = serial_port_in(port, SCSCR);
528
529 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
530 ctrl &= ~SCSCR_TDRQE;
531
532 ctrl &= ~SCSCR_TIE;
533
534 serial_port_out(port, SCSCR, ctrl);
535}
536
537static void sci_start_rx(struct uart_port *port)
538{
539 unsigned short ctrl;
540
541 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
542
543 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
544 ctrl &= ~SCSCR_RDRQE;
545
546 serial_port_out(port, SCSCR, ctrl);
547}
548
549static void sci_stop_rx(struct uart_port *port)
550{
551 unsigned short ctrl;
552
553 ctrl = serial_port_in(port, SCSCR);
554
555 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
556 ctrl &= ~SCSCR_RDRQE;
557
558 ctrl &= ~port_rx_irq_mask(port);
559
560 serial_port_out(port, SCSCR, ctrl);
561}
562
a1b5b43f
GU		 563static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
564{
565 if (port->type == PORT_SCI) {
566 /* Just store the mask */
567 serial_port_out(port, SCxSR, mask);
568 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
569 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
570 /* Only clear the status bits we want to clear */
571 serial_port_out(port, SCxSR,
572 serial_port_in(port, SCxSR) & mask);
573 } else {
574 /* Store the mask, clear parity/framing errors */
575 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
576 }
577}
578
07d2a1a1 579#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 580
581#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 582static int sci_poll_get_char(struct uart_port *port)
1da177e4 583{
1da177e4
LT		 584 unsigned short status;
585 int c;
586
e108b2ca 587 do {
b12bb29f 588 status = serial_port_in(port, SCxSR);
1da177e4 589 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 590 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 591 continue;
592 }
3f255eb3
JW		 593 break;
594 } while (1);
595
596 if (!(status & SCxSR_RDxF(port)))
597 return NO_POLL_CHAR;
07d2a1a1 598
b12bb29f 599 c = serial_port_in(port, SCxRDR);
07d2a1a1 600
e7c98dc7 601 /* Dummy read */
b12bb29f 602 serial_port_in(port, SCxSR);
a1b5b43f 603 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 604
605 return c;
606}
1f6fd5c9 607#endif
1da177e4 608
07d2a1a1 609static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 610{
1da177e4
LT		 611 unsigned short status;
612
1da177e4 613 do {
b12bb29f 614 status = serial_port_in(port, SCxSR);
1da177e4
LT		 615 } while (!(status & SCxSR_TDxE(port)));
616
b12bb29f 617 serial_port_out(port, SCxTDR, c);
a1b5b43f 618 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 619}
07d2a1a1 620#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 621
61a6976b 622static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 623{
61a6976b 624 struct sci_port *s = to_sci_port(port);
d3184e68 625 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 626
61a6976b
PM		 627 /*
628 * Use port-specific handler if provided.
629 */
630 if (s->cfg->ops && s->cfg->ops->init_pins) {
631 s->cfg->ops->init_pins(port, cflag);
632 return;
1da177e4 633 }
41504c39 634
61a6976b
PM		 635 /*
636 * For the generic path SCSPTR is necessary. Bail out if that's
637 * unavailable, too.
638 */
639 if (!reg->size)
640 return;
41504c39 641
faf02f8f
PM		 642 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
643 ((!(cflag & CRTSCTS)))) {
644 unsigned short status;
645
b12bb29f 646 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 647 status &= ~SCSPTR_CTSIO;
648 status |= SCSPTR_RTSIO;
b12bb29f 649 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 650 }
d5701647 651}
e108b2ca 652
72b294cf 653static int sci_txfill(struct uart_port *port)
e108b2ca 654{
d3184e68 655 const struct plat_sci_reg *reg;
e108b2ca 656
72b294cf
PM		 657 reg = sci_getreg(port, SCTFDR);
658 if (reg->size)
63f7ad11 659 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 660
72b294cf
PM		 661 reg = sci_getreg(port, SCFDR);
662 if (reg->size)
b12bb29f 663 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 664
b12bb29f 665 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 666}
667
73a19e4c
GL		 668static int sci_txroom(struct uart_port *port)
669{
72b294cf 670 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 671}
672
673static int sci_rxfill(struct uart_port *port)
e108b2ca 674{
d3184e68 675 const struct plat_sci_reg *reg;
72b294cf
PM		 676
677 reg = sci_getreg(port, SCRFDR);
678 if (reg->size)
63f7ad11 679 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 680
681 reg = sci_getreg(port, SCFDR);
682 if (reg->size)
b12bb29f 683 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 684
b12bb29f 685 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 686}
687
514820eb
PM		 688/*
689 * SCI helper for checking the state of the muxed port/RXD pins.
690 */
691static inline int sci_rxd_in(struct uart_port *port)
692{
693 struct sci_port *s = to_sci_port(port);
694
695 if (s->cfg->port_reg <= 0)
696 return 1;
697
0dd4d5cb 698 /* Cast for ARM damage */
e2afca69 699 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 700}
701
1da177e4
LT		 702/* ********************************************************************** *
703 * the interrupt related routines *
704 * ********************************************************************** */
705
706static void sci_transmit_chars(struct uart_port *port)
707{
ebd2c8f6 708 struct circ_buf *xmit = &port->state->xmit;
1da177e4 709 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 710 unsigned short status;
711 unsigned short ctrl;
e108b2ca 712 int count;
1da177e4 713
b12bb29f 714 status = serial_port_in(port, SCxSR);
1da177e4 715 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 716 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 717 if (uart_circ_empty(xmit))
8e698614 718 ctrl &= ~SCSCR_TIE;
e7c98dc7 719 else
8e698614 720 ctrl |= SCSCR_TIE;
b12bb29f 721 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 722 return;
723 }
724
72b294cf 725 count = sci_txroom(port);
1da177e4
LT		 726
727 do {
728 unsigned char c;
729
730 if (port->x_char) {
731 c = port->x_char;
732 port->x_char = 0;
733 } else if (!uart_circ_empty(xmit) && !stopped) {
734 c = xmit->buf[xmit->tail];
735 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
736 } else {
737 break;
738 }
739
b12bb29f 740 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 741
742 port->icount.tx++;
743 } while (--count > 0);
744
a1b5b43f 745 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 746
747 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
748 uart_write_wakeup(port);
749 if (uart_circ_empty(xmit)) {
b129a8cc 750 sci_stop_tx(port);
1da177e4 751 } else {
b12bb29f 752 ctrl = serial_port_in(port, SCSCR);
1da177e4 753
1a22f08d 754 if (port->type != PORT_SCI) {
b12bb29f 755 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 756 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 757 }
1da177e4 758
8e698614 759 ctrl |= SCSCR_TIE;
b12bb29f 760 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 761 }
762}
763
764/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 765#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 766
94c8b6db 767static void sci_receive_chars(struct uart_port *port)
1da177e4 768{
e7c98dc7 769 struct sci_port *sci_port = to_sci_port(port);
227434f8 770 struct tty_port *tport = &port->state->port;
1da177e4
LT		 771 int i, count, copied = 0;
772 unsigned short status;
33f0f88f 773 unsigned char flag;
1da177e4 774
b12bb29f 775 status = serial_port_in(port, SCxSR);
1da177e4
LT		 776 if (!(status & SCxSR_RDxF(port)))
777 return;
778
779 while (1) {
1da177e4 780 /* Don't copy more bytes than there is room for in the buffer */
227434f8 781 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 782
783 /* If for any reason we can't copy more data, we're done! */
784 if (count == 0)
785 break;
786
787 if (port->type == PORT_SCI) {
b12bb29f 788 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 789 if (uart_handle_sysrq_char(port, c) ||
790 sci_port->break_flag)
1da177e4 791 count = 0;
e7c98dc7 792 else
92a19f9c 793 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 794 } else {
e7c98dc7 795 for (i = 0; i < count; i++) {
b12bb29f 796 char c = serial_port_in(port, SCxRDR);
d97fbbed 797
b12bb29f 798 status = serial_port_in(port, SCxSR);
1da177e4
LT		 799#if defined(CONFIG_CPU_SH3)
800 /* Skip "chars" during break */
e108b2ca 801 if (sci_port->break_flag) {
1da177e4
LT		 802 if ((c == 0) &&
803 (status & SCxSR_FER(port))) {
804 count--; i--;
805 continue;
806 }
e108b2ca 807
1da177e4 808 /* Nonzero => end-of-break */
762c69e3 809 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 810 sci_port->break_flag = 0;
811
1da177e4
LT		 812 if (STEPFN(c)) {
813 count--; i--;
814 continue;
815 }
816 }
817#endif /* CONFIG_CPU_SH3 */
7d12e780 818 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 819 count--; i--;
820 continue;
821 }
822
823 /* Store data and status */
73a19e4c 824 if (status & SCxSR_FER(port)) {
33f0f88f 825 flag = TTY_FRAME;
d97fbbed 826 port->icount.frame++;
762c69e3 827 dev_notice(port->dev, "frame error\n");
73a19e4c 828 } else if (status & SCxSR_PER(port)) {
33f0f88f 829 flag = TTY_PARITY;
d97fbbed 830 port->icount.parity++;
762c69e3 831 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 832 } else
833 flag = TTY_NORMAL;
762c69e3 834
92a19f9c 835 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 836 }
837 }
838
b12bb29f 839 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 840 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 841
1da177e4
LT		 842 copied += count;
843 port->icount.rx += count;
844 }
845
846 if (copied) {
847 /* Tell the rest of the system the news. New characters! */
2e124b4a 848 tty_flip_buffer_push(tport);
1da177e4 849 } else {
b12bb29f 850 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 851 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 852 }
853}
854
855#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 856
857/*
858 * The sci generates interrupts during the break,
1da177e4
LT		 859 * 1 per millisecond or so during the break period, for 9600 baud.
860 * So dont bother disabling interrupts.
861 * But dont want more than 1 break event.
862 * Use a kernel timer to periodically poll the rx line until
863 * the break is finished.
864 */
94c8b6db 865static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 866{
bc9b3f5c 867 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 868}
94c8b6db 869
1da177e4
LT		 870/* Ensure that two consecutive samples find the break over. */
871static void sci_break_timer(unsigned long data)
872{
e108b2ca
PM		 873 struct sci_port *port = (struct sci_port *)data;
874
875 if (sci_rxd_in(&port->port) == 0) {
1da177e4 876 port->break_flag = 1;
e108b2ca
PM		 877 sci_schedule_break_timer(port);
878 } else if (port->break_flag == 1) {
1da177e4
LT		 879 /* break is over. */
880 port->break_flag = 2;
e108b2ca
PM		 881 sci_schedule_break_timer(port);
882 } else
883 port->break_flag = 0;
1da177e4
LT		 884}
885
94c8b6db 886static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 887{
888 int copied = 0;
b12bb29f 889 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 890 struct tty_port *tport = &port->state->port;
debf9507 891 struct sci_port *s = to_sci_port(port);
1da177e4 892
3ae988d9 893 /* Handle overruns */
75c249fd 894 if (status & s->overrun_mask) {
3ae988d9 895 port->icount.overrun++;
d97fbbed 896
3ae988d9
LP		 897 /* overrun error */
898 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
899 copied++;
762c69e3 900
9b971cd2 901 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 902 }
903
e108b2ca 904 if (status & SCxSR_FER(port)) {
1da177e4
LT		 905 if (sci_rxd_in(port) == 0) {
906 /* Notify of BREAK */
e7c98dc7 907 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 908
909 if (!sci_port->break_flag) {
d97fbbed
PM		 910 port->icount.brk++;
911
e108b2ca
PM		 912 sci_port->break_flag = 1;
913 sci_schedule_break_timer(sci_port);
914
1da177e4 915 /* Do sysrq handling. */
e108b2ca 916 if (uart_handle_break(port))
1da177e4 917 return 0;
762c69e3
PM		 918
919 dev_dbg(port->dev, "BREAK detected\n");
920
92a19f9c 921 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 922 copied++;
923 }
924
e108b2ca 925 } else {
1da177e4 926 /* frame error */
d97fbbed
PM		 927 port->icount.frame++;
928
92a19f9c 929 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 930 copied++;
762c69e3
PM		 931
932 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 933 }
934 }
935
e108b2ca 936 if (status & SCxSR_PER(port)) {
1da177e4 937 /* parity error */
d97fbbed
PM		 938 port->icount.parity++;
939
92a19f9c 940 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 941 copied++;
762c69e3 942
9b971cd2 943 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 944 }
945
33f0f88f 946 if (copied)
2e124b4a 947 tty_flip_buffer_push(tport);
1da177e4
LT		 948
949 return copied;
950}
951
94c8b6db 952static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 953{
92a19f9c 954 struct tty_port *tport = &port->state->port;
debf9507 955 struct sci_port *s = to_sci_port(port);
d3184e68 956 const struct plat_sci_reg *reg;
2e0842a1 957 int copied = 0;
75c249fd 958 u16 status;
d830fa45 959
2e0842a1 960 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 961 if (!reg->size)
d830fa45
PM		 962 return 0;
963
2e0842a1 964 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 965 if (status & s->overrun_mask) {
966 status &= ~s->overrun_mask;
2e0842a1 967 serial_port_out(port, s->overrun_reg, status);
d830fa45 968
d97fbbed
PM		 969 port->icount.overrun++;
970
92a19f9c 971 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 972 tty_flip_buffer_push(tport);
d830fa45 973
51b31f1c 974 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 975 copied++;
976 }
977
978 return copied;
979}
980
94c8b6db 981static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 982{
983 int copied = 0;
b12bb29f 984 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 985 struct tty_port *tport = &port->state->port;
a5660ada 986 struct sci_port *s = to_sci_port(port);
1da177e4 987
0b3d4ef6
PM		 988 if (uart_handle_break(port))
989 return 0;
990
b7a76e4b 991 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 992#if defined(CONFIG_CPU_SH3)
993 /* Debounce break */
994 s->break_flag = 1;
995#endif
d97fbbed
PM		 996
997 port->icount.brk++;
998
1da177e4 999 /* Notify of BREAK */
92a19f9c 1000 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 1001 copied++;
762c69e3
PM		 1002
1003 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 1004 }
1005
33f0f88f 1006 if (copied)
2e124b4a 1007 tty_flip_buffer_push(tport);
e108b2ca 1008
d830fa45
PM		 1009 copied += sci_handle_fifo_overrun(port);
1010
1da177e4
LT		 1011 return copied;
1012}
1013
73a19e4c 1014#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1015static void sci_dma_tx_complete(void *arg)
1016{
1017 struct sci_port *s = arg;
1018 struct uart_port *port = &s->port;
1019 struct circ_buf *xmit = &port->state->xmit;
1020 unsigned long flags;
73a19e4c 1021
e1910fcd 1022 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1023
e1910fcd 1024 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1025
e1910fcd
GU		 1026 xmit->tail += s->tx_dma_len;
1027 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1028
e1910fcd 1029 port->icount.tx += s->tx_dma_len;
1da177e4 1030
e1910fcd
GU		 1031 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1032 uart_write_wakeup(port);
1da177e4 1033
e1910fcd
GU		 1034 if (!uart_circ_empty(xmit)) {
1035 s->cookie_tx = 0;
1036 schedule_work(&s->work_tx);
1037 } else {
1038 s->cookie_tx = -EINVAL;
1039 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1040 u16 ctrl = serial_port_in(port, SCSCR);
1041 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1042 }
1043 }
1da177e4 1044
fd78a76a 1045 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1046}
1047
e1910fcd
GU		 1048/* Locking: called with port lock held */
1049static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1050{
e1910fcd
GU		 1051 struct uart_port *port = &s->port;
1052 struct tty_port *tport = &port->state->port;
1053 int copied;
1da177e4 1054
e1910fcd
GU		 1055 copied = tty_insert_flip_string(tport, buf, count);
1056 if (copied < count) {
1057 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1058 count - copied);
1059 port->icount.buf_overrun++;
1da177e4
LT		 1060 }
1061
e1910fcd 1062 port->icount.rx += copied;
1da177e4 1063
e1910fcd 1064 return copied;
1da177e4
LT		 1065}
1066
e1910fcd 1067static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1068{
e1910fcd 1069 unsigned int i;
1da177e4 1070
e1910fcd
GU		 1071 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1072 if (s->active_rx == s->cookie_rx[i])
1073 return i;
1da177e4 1074
e1910fcd
GU		 1075 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1076 s->active_rx);
1077 return -1;
1da177e4
LT		 1078}
1079
e1910fcd 1080static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1081{
e1910fcd
GU		 1082 struct dma_chan *chan = s->chan_rx;
1083 struct uart_port *port = &s->port;
1084 unsigned long flags;
1085
1086 spin_lock_irqsave(&port->lock, flags);
1087 s->chan_rx = NULL;
1088 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1089 spin_unlock_irqrestore(&port->lock, flags);
1090 dmaengine_terminate_all(chan);
1091 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1092 sg_dma_address(&s->sg_rx[0]));
1093 dma_release_channel(chan);
1094 if (enable_pio)
1095 sci_start_rx(port);
f43dc23d
PM		 1096}
1097
e1910fcd 1098static void sci_dma_rx_complete(void *arg)
1da177e4 1099{
e1910fcd 1100 struct sci_port *s = arg;
1d3db608 1101 struct dma_chan *chan = s->chan_rx;
e1910fcd 1102 struct uart_port *port = &s->port;
67f462b0 1103 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1104 unsigned long flags;
1105 int active, count = 0;
1da177e4 1106
e1910fcd
GU		 1107 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1108 s->active_rx);
cb772fe7 1109
e1910fcd 1110 spin_lock_irqsave(&port->lock, flags);
1da177e4 1111
e1910fcd
GU		 1112 active = sci_dma_rx_find_active(s);
1113 if (active >= 0)
1114 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1115
e1910fcd 1116 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1117
e1910fcd
GU		 1118 if (count)
1119 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1120
67f462b0
GU		 1121 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1122 DMA_DEV_TO_MEM,
1123 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1124 if (!desc)
1125 goto fail;
1126
1127 desc->callback = sci_dma_rx_complete;
1128 desc->callback_param = s;
1129 s->cookie_rx[active] = dmaengine_submit(desc);
1130 if (dma_submit_error(s->cookie_rx[active]))
1131 goto fail;
1132
1133 s->active_rx = s->cookie_rx[!active];
1134
1d3db608
MHF		 1135 dma_async_issue_pending(chan);
1136
67f462b0
GU		 1137 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1138 __func__, s->cookie_rx[active], active, s->active_rx);
1139 spin_unlock_irqrestore(&port->lock, flags);
1140 return;
1141
1142fail:
1143 spin_unlock_irqrestore(&port->lock, flags);
1144 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1145 sci_rx_dma_release(s, true);
1da177e4
LT		 1146}
1147
e1910fcd 1148static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1149{
e1910fcd
GU		 1150 struct dma_chan *chan = s->chan_tx;
1151 struct uart_port *port = &s->port;
e552de24 1152 unsigned long flags;
1da177e4 1153
e1910fcd
GU		 1154 spin_lock_irqsave(&port->lock, flags);
1155 s->chan_tx = NULL;
1156 s->cookie_tx = -EINVAL;
1157 spin_unlock_irqrestore(&port->lock, flags);
1158 dmaengine_terminate_all(chan);
1159 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1160 DMA_TO_DEVICE);
1161 dma_release_channel(chan);
1162 if (enable_pio)
1163 sci_start_tx(port);
1164}
d535a230 1165
e1910fcd
GU		 1166static void sci_submit_rx(struct sci_port *s)
1167{
1168 struct dma_chan *chan = s->chan_rx;
1169 int i;
073e84c9 1170
e1910fcd
GU		 1171 for (i = 0; i < 2; i++) {
1172 struct scatterlist *sg = &s->sg_rx[i];
1173 struct dma_async_tx_descriptor *desc;
1da177e4 1174
e1910fcd
GU		 1175 desc = dmaengine_prep_slave_sg(chan,
1176 sg, 1, DMA_DEV_TO_MEM,
1177 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1178 if (!desc)
1179 goto fail;
501b825d 1180
e1910fcd
GU		 1181 desc->callback = sci_dma_rx_complete;
1182 desc->callback_param = s;
1183 s->cookie_rx[i] = dmaengine_submit(desc);
1184 if (dma_submit_error(s->cookie_rx[i]))
1185 goto fail;
9174fc8f 1186
e1910fcd
GU		 1187 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1188 s->cookie_rx[i], i);
1189 }
9174fc8f 1190
e1910fcd 1191 s->active_rx = s->cookie_rx[0];
9174fc8f 1192
e1910fcd
GU		 1193 dma_async_issue_pending(chan);
1194 return;
9174fc8f 1195
e1910fcd
GU		 1196fail:
1197 if (i)
1198 dmaengine_terminate_all(chan);
1199 for (i = 0; i < 2; i++)
1200 s->cookie_rx[i] = -EINVAL;
1201 s->active_rx = -EINVAL;
1202 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1203 sci_rx_dma_release(s, true);
1204}
9174fc8f 1205
e1910fcd 1206static void work_fn_tx(struct work_struct *work)
1da177e4 1207{
e1910fcd
GU		 1208 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1209 struct dma_async_tx_descriptor *desc;
1210 struct dma_chan *chan = s->chan_tx;
1211 struct uart_port *port = &s->port;
1212 struct circ_buf *xmit = &port->state->xmit;
1213 dma_addr_t buf;
1da177e4 1214
9174fc8f 1215 /*
e1910fcd
GU		 1216 * DMA is idle now.
1217 * Port xmit buffer is already mapped, and it is one page... Just adjust
1218 * offsets and lengths. Since it is a circular buffer, we have to
1219 * transmit till the end, and then the rest. Take the port lock to get a
1220 * consistent xmit buffer state.
9174fc8f 1221 */
e1910fcd
GU		 1222 spin_lock_irq(&port->lock);
1223 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1224 s->tx_dma_len = min_t(unsigned int,
1225 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1226 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1227 spin_unlock_irq(&port->lock);
0e8963de 1228
e1910fcd
GU		 1229 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1230 DMA_MEM_TO_DEV,
1231 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1232 if (!desc) {
1233 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1234 /* switch to PIO */
1235 sci_tx_dma_release(s, true);
1236 return;
1237 }
0e8963de 1238
e1910fcd
GU		 1239 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1240 DMA_TO_DEVICE);
1da177e4 1241
e1910fcd
GU		 1242 spin_lock_irq(&port->lock);
1243 desc->callback = sci_dma_tx_complete;
1244 desc->callback_param = s;
1245 spin_unlock_irq(&port->lock);
1246 s->cookie_tx = dmaengine_submit(desc);
1247 if (dma_submit_error(s->cookie_tx)) {
1248 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1249 /* switch to PIO */
1250 sci_tx_dma_release(s, true);
1251 return;
1da177e4 1252 }
1da177e4 1253
e1910fcd
GU		 1254 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1255 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1256
e1910fcd 1257 dma_async_issue_pending(chan);
1da177e4
LT		 1258}
1259
e1910fcd 1260static void rx_timer_fn(unsigned long arg)
1da177e4 1261{
e1910fcd 1262 struct sci_port *s = (struct sci_port *)arg;
e7327c09 1263 struct dma_chan *chan = s->chan_rx;
e1910fcd 1264 struct uart_port *port = &s->port;
67f462b0
GU		 1265 struct dma_tx_state state;
1266 enum dma_status status;
1267 unsigned long flags;
1268 unsigned int read;
1269 int active, count;
1270 u16 scr;
1271
1272 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1273
67f462b0 1274 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0
GU		 1275
1276 active = sci_dma_rx_find_active(s);
1277 if (active < 0) {
1278 spin_unlock_irqrestore(&port->lock, flags);
1279 return;
1280 }
1281
1282 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1283 if (status == DMA_COMPLETE) {
67f462b0
GU		 1284 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1285 s->active_rx, active);
3b963042
MHF		 1286 spin_unlock_irqrestore(&port->lock, flags);
1287
1288 /* Let packet complete handler take care of the packet */
1289 return;
1290 }
67f462b0 1291
e7327c09
MHF		 1292 dmaengine_pause(chan);
1293
1294 /*
1295 * sometimes DMA transfer doesn't stop even if it is stopped and
1296 * data keeps on coming until transaction is complete so check
1297 * for DMA_COMPLETE again
1298 * Let packet complete handler take care of the packet
1299 */
1300 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1301 if (status == DMA_COMPLETE) {
1302 spin_unlock_irqrestore(&port->lock, flags);
1303 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1304 return;
1305 }
1306
67f462b0
GU		 1307 /* Handle incomplete DMA receive */
1308 dmaengine_terminate_all(s->chan_rx);
1309 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1310 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1311 s->active_rx);
1312
1313 if (read) {
1314 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1315 if (count)
1316 tty_flip_buffer_push(&port->state->port);
1317 }
1318
756981be
GU		 1319 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1320 sci_submit_rx(s);
371cfed3
MHF		 1321
1322 /* Direct new serial port interrupts back to CPU */
1323 scr = serial_port_in(port, SCSCR);
1324 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1325 scr &= ~SCSCR_RDRQE;
1326 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1327 }
1328 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1329
1330 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1331}
1332
ff441129
GU		 1333static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1334 enum dma_transfer_direction dir,
1335 unsigned int id)
1336{
1337 dma_cap_mask_t mask;
1338 struct dma_chan *chan;
1339 struct dma_slave_config cfg;
1340 int ret;
1341
1342 dma_cap_zero(mask);
1343 dma_cap_set(DMA_SLAVE, mask);
1344
1345 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1346 (void *)(unsigned long)id, port->dev,
1347 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1348 if (!chan) {
1349 dev_warn(port->dev,
1350 "dma_request_slave_channel_compat failed\n");
1351 return NULL;
1352 }
1353
1354 memset(&cfg, 0, sizeof(cfg));
1355 cfg.direction = dir;
1356 if (dir == DMA_MEM_TO_DEV) {
1357 cfg.dst_addr = port->mapbase +
1358 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1359 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1360 } else {
1361 cfg.src_addr = port->mapbase +
1362 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1363 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1364 }
1365
1366 ret = dmaengine_slave_config(chan, &cfg);
1367 if (ret) {
1368 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1369 dma_release_channel(chan);
1370 return NULL;
1371 }
1372
1373 return chan;
1374}
1375
e1910fcd 1376static void sci_request_dma(struct uart_port *port)
73a19e4c 1377{
e1910fcd 1378 struct sci_port *s = to_sci_port(port);
e1910fcd 1379 struct dma_chan *chan;
73a19e4c 1380
e1910fcd 1381 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1382
ff441129
GU		 1383 if (!port->dev->of_node &&
1384 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
e1910fcd 1385 return;
73a19e4c 1386
e1910fcd 1387 s->cookie_tx = -EINVAL;
ff441129 1388 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
e1910fcd
GU		 1389 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1390 if (chan) {
1391 s->chan_tx = chan;
1392 /* UART circular tx buffer is an aligned page. */
1393 s->tx_dma_addr = dma_map_single(chan->device->dev,
1394 port->state->xmit.buf,
1395 UART_XMIT_SIZE,
1396 DMA_TO_DEVICE);
1397 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1398 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1399 dma_release_channel(chan);
1400 s->chan_tx = NULL;
1401 } else {
1402 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1403 __func__, UART_XMIT_SIZE,
1404 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1405 }
e1910fcd
GU		 1406
1407 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1408 }
1409
ff441129 1410 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
e1910fcd
GU		 1411 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1412 if (chan) {
1413 unsigned int i;
1414 dma_addr_t dma;
1415 void *buf;
73a19e4c 1416
e1910fcd 1417 s->chan_rx = chan;
73a19e4c 1418
e1910fcd
GU		 1419 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1420 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1421 &dma, GFP_KERNEL);
1422 if (!buf) {
1423 dev_warn(port->dev,
1424 "Failed to allocate Rx dma buffer, using PIO\n");
1425 dma_release_channel(chan);
1426 s->chan_rx = NULL;
e1910fcd
GU		 1427 return;
1428 }
73a19e4c 1429
e1910fcd
GU		 1430 for (i = 0; i < 2; i++) {
1431 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1432
e1910fcd
GU		 1433 sg_init_table(sg, 1);
1434 s->rx_buf[i] = buf;
1435 sg_dma_address(sg) = dma;
1436 sg->length = s->buf_len_rx;
0533502d 1437
e1910fcd
GU		 1438 buf += s->buf_len_rx;
1439 dma += s->buf_len_rx;
1440 }
1441
e1910fcd
GU		 1442 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1443
756981be
GU		 1444 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1445 sci_submit_rx(s);
e1910fcd 1446 }
0533502d
GU		 1447}
1448
e1910fcd 1449static void sci_free_dma(struct uart_port *port)
73a19e4c 1450{
e1910fcd 1451 struct sci_port *s = to_sci_port(port);
73a19e4c 1452
e1910fcd
GU		 1453 if (s->chan_tx)
1454 sci_tx_dma_release(s, false);
1455 if (s->chan_rx)
1456 sci_rx_dma_release(s, false);
1457}
1458#else
1459static inline void sci_request_dma(struct uart_port *port)
1460{
1461}
73a19e4c 1462
e1910fcd
GU		 1463static inline void sci_free_dma(struct uart_port *port)
1464{
1465}
1466#endif
73a19e4c 1467
e1910fcd
GU		 1468static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1469{
1470#ifdef CONFIG_SERIAL_SH_SCI_DMA
1471 struct uart_port *port = ptr;
1472 struct sci_port *s = to_sci_port(port);
73a19e4c 1473
e1910fcd
GU		 1474 if (s->chan_rx) {
1475 u16 scr = serial_port_in(port, SCSCR);
1476 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1477
e1910fcd
GU		 1478 /* Disable future Rx interrupts */
1479 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1480 disable_irq_nosync(irq);
1481 scr |= SCSCR_RDRQE;
1482 } else {
1483 scr &= ~SCSCR_RIE;
756981be 1484 sci_submit_rx(s);
e1910fcd
GU		 1485 }
1486 serial_port_out(port, SCSCR, scr);
1487 /* Clear current interrupt */
1488 serial_port_out(port, SCxSR,
1489 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1490 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1491 jiffies, s->rx_timeout);
1492 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1493
e1910fcd
GU		 1494 return IRQ_HANDLED;
1495 }
1496#endif
73a19e4c 1497
e1910fcd
GU		 1498 /* I think sci_receive_chars has to be called irrespective
1499 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1500 * to be disabled?
1501 */
1502 sci_receive_chars(ptr);
1503
1504 return IRQ_HANDLED;
73a19e4c
GL		 1505}
1506
e1910fcd 1507static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1508{
e1910fcd 1509 struct uart_port *port = ptr;
04928b79 1510 unsigned long flags;
73a19e4c 1511
04928b79 1512 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1513 sci_transmit_chars(port);
04928b79 1514 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1515
1516 return IRQ_HANDLED;
73a19e4c
GL		 1517}
1518
e1910fcd 1519static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1520{
e1910fcd
GU		 1521 struct uart_port *port = ptr;
1522 struct sci_port *s = to_sci_port(port);
73a19e4c 1523
e1910fcd
GU		 1524 /* Handle errors */
1525 if (port->type == PORT_SCI) {
1526 if (sci_handle_errors(port)) {
1527 /* discard character in rx buffer */
1528 serial_port_in(port, SCxSR);
1529 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1530 }
1531 } else {
1532 sci_handle_fifo_overrun(port);
1533 if (!s->chan_rx)
1534 sci_receive_chars(ptr);
1535 }
1536
1537 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1538
1539 /* Kick the transmission */
1540 if (!s->chan_tx)
1541 sci_tx_interrupt(irq, ptr);
1542
1543 return IRQ_HANDLED;
73a19e4c
GL		 1544}
1545
e1910fcd 1546static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1547{
e1910fcd 1548 struct uart_port *port = ptr;
73a19e4c 1549
e1910fcd
GU		 1550 /* Handle BREAKs */
1551 sci_handle_breaks(port);
1552 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1553
e1910fcd
GU		 1554 return IRQ_HANDLED;
1555}
73a19e4c 1556
e1910fcd
GU		 1557static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1558{
1559 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1560 struct uart_port *port = ptr;
1561 struct sci_port *s = to_sci_port(port);
1562 irqreturn_t ret = IRQ_NONE;
73a19e4c 1563
e1910fcd
GU		 1564 ssr_status = serial_port_in(port, SCxSR);
1565 scr_status = serial_port_in(port, SCSCR);
1566 if (s->overrun_reg == SCxSR)
1567 orer_status = ssr_status;
1568 else {
1569 if (sci_getreg(port, s->overrun_reg)->size)
1570 orer_status = serial_port_in(port, s->overrun_reg);
73a19e4c
GL		 1571 }
1572
e1910fcd 1573 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1574
e1910fcd
GU		 1575 /* Tx Interrupt */
1576 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1577 !s->chan_tx)
1578 ret = sci_tx_interrupt(irq, ptr);
658daa95 1579
e1910fcd
GU		 1580 /*
1581 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1582 * DR flags
1583 */
1584 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1585 (scr_status & SCSCR_RIE))
1586 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1587
e1910fcd
GU		 1588 /* Error Interrupt */
1589 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1590 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1591
e1910fcd
GU		 1592 /* Break Interrupt */
1593 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1594 ret = sci_br_interrupt(irq, ptr);
1595
1596 /* Overrun Interrupt */
1597 if (orer_status & s->overrun_mask) {
1598 sci_handle_fifo_overrun(port);
1599 ret = IRQ_HANDLED;
73a19e4c 1600 }
73a19e4c 1601
e1910fcd
GU		 1602 return ret;
1603}
73a19e4c 1604
e1910fcd
GU		 1605/*
1606 * Here we define a transition notifier so that we can update all of our
1607 * ports' baud rate when the peripheral clock changes.
1608 */
1609static int sci_notifier(struct notifier_block *self,
1610 unsigned long phase, void *p)
1611{
1612 struct sci_port *sci_port;
1613 unsigned long flags;
73a19e4c 1614
e1910fcd 1615 sci_port = container_of(self, struct sci_port, freq_transition);
73a19e4c 1616
e1910fcd
GU		 1617 if (phase == CPUFREQ_POSTCHANGE) {
1618 struct uart_port *port = &sci_port->port;
73a19e4c 1619
e1910fcd 1620 spin_lock_irqsave(&port->lock, flags);
a9ec81f4 1621 port->uartclk = clk_get_rate(sci_port->fclk);
e1910fcd 1622 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1623 }
1624
e1910fcd
GU		 1625 return NOTIFY_OK;
1626}
73a19e4c 1627
e1910fcd
GU		 1628static const struct sci_irq_desc {
1629 const char *desc;
1630 irq_handler_t handler;
1631} sci_irq_desc[] = {
1632 /*
1633 * Split out handlers, the default case.
1634 */
1635 [SCIx_ERI_IRQ] = {
1636 .desc = "rx err",
1637 .handler = sci_er_interrupt,
1638 },
3089f381 1639
e1910fcd
GU		 1640 [SCIx_RXI_IRQ] = {
1641 .desc = "rx full",
1642 .handler = sci_rx_interrupt,
1643 },
47aceb92 1644
e1910fcd
GU		 1645 [SCIx_TXI_IRQ] = {
1646 .desc = "tx empty",
1647 .handler = sci_tx_interrupt,
1648 },
73a19e4c 1649
e1910fcd
GU		 1650 [SCIx_BRI_IRQ] = {
1651 .desc = "break",
1652 .handler = sci_br_interrupt,
1653 },
73a19e4c
GL		 1654
1655 /*
e1910fcd 1656 * Special muxed handler.
73a19e4c 1657 */
e1910fcd
GU		 1658 [SCIx_MUX_IRQ] = {
1659 .desc = "mux",
1660 .handler = sci_mpxed_interrupt,
1661 },
1662};
73a19e4c 1663
e1910fcd
GU		 1664static int sci_request_irq(struct sci_port *port)
1665{
1666 struct uart_port *up = &port->port;
1667 int i, j, ret = 0;
73a19e4c 1668
e1910fcd
GU		 1669 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1670 const struct sci_irq_desc *desc;
1671 int irq;
73a19e4c 1672
e1910fcd
GU		 1673 if (SCIx_IRQ_IS_MUXED(port)) {
1674 i = SCIx_MUX_IRQ;
1675 irq = up->irq;
1676 } else {
1677 irq = port->irqs[i];
1678
1679 /*
1680 * Certain port types won't support all of the
1681 * available interrupt sources.
1682 */
1683 if (unlikely(irq < 0))
1684 continue;
1685 }
1686
1687 desc = sci_irq_desc + i;
1688 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1689 dev_name(up->dev), desc->desc);
1690 if (!port->irqstr[j])
1691 goto out_nomem;
1692
1693 ret = request_irq(irq, desc->handler, up->irqflags,
1694 port->irqstr[j], port);
1695 if (unlikely(ret)) {
1696 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1697 goto out_noirq;
1698 }
73a19e4c
GL		 1699 }
1700
e1910fcd 1701 return 0;
1da177e4 1702
e1910fcd
GU		 1703out_noirq:
1704 while (--i >= 0)
1705 free_irq(port->irqs[i], port);
f43dc23d 1706
e1910fcd
GU		 1707out_nomem:
1708 while (--j >= 0)
1709 kfree(port->irqstr[j]);
f43dc23d 1710
e1910fcd 1711 return ret;
1da177e4
LT		 1712}
1713
e1910fcd 1714static void sci_free_irq(struct sci_port *port)
1da177e4 1715{
e1910fcd 1716 int i;
1da177e4 1717
e1910fcd
GU		 1718 /*
1719 * Intentionally in reverse order so we iterate over the muxed
1720 * IRQ first.
1721 */
1722 for (i = 0; i < SCIx_NR_IRQS; i++) {
1723 int irq = port->irqs[i];
f43dc23d 1724
e1910fcd
GU		 1725 /*
1726 * Certain port types won't support all of the available
1727 * interrupt sources.
1728 */
1729 if (unlikely(irq < 0))
1730 continue;
f43dc23d 1731
e1910fcd
GU		 1732 free_irq(port->irqs[i], port);
1733 kfree(port->irqstr[i]);
f43dc23d 1734
e1910fcd
GU		 1735 if (SCIx_IRQ_IS_MUXED(port)) {
1736 /* If there's only one IRQ, we're done. */
1737 return;
1738 }
1739 }
1da177e4
LT		 1740}
1741
e1910fcd 1742static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1743{
e1910fcd
GU		 1744 unsigned short status = serial_port_in(port, SCxSR);
1745 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1746
e1910fcd 1747 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1748}
1749
e1910fcd
GU		 1750/*
1751 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1752 * CTS/RTS is supported in hardware by at least one port and controlled
1753 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1754 * handled via the ->init_pins() op, which is a bit of a one-way street,
1755 * lacking any ability to defer pin control -- this will later be
1756 * converted over to the GPIO framework).
1757 *
1758 * Other modes (such as loopback) are supported generically on certain
1759 * port types, but not others. For these it's sufficient to test for the
1760 * existence of the support register and simply ignore the port type.
1761 */
1762static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1763{
e1910fcd
GU		 1764 if (mctrl & TIOCM_LOOP) {
1765 const struct plat_sci_reg *reg;
f43dc23d 1766
e1910fcd
GU		 1767 /*
1768 * Standard loopback mode for SCFCR ports.
1769 */
1770 reg = sci_getreg(port, SCFCR);
1771 if (reg->size)
1772 serial_port_out(port, SCFCR,
1773 serial_port_in(port, SCFCR) |
1774 SCFCR_LOOP);
1775 }
1776}
f43dc23d 1777
e1910fcd
GU		 1778static unsigned int sci_get_mctrl(struct uart_port *port)
1779{
1780 /*
1781 * CTS/RTS is handled in hardware when supported, while nothing
1782 * else is wired up. Keep it simple and simply assert DSR/CAR.
1783 */
1784 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1785}
1786
1da177e4
LT		 1787static void sci_break_ctl(struct uart_port *port, int break_state)
1788{
bbb4ce50 1789 struct sci_port *s = to_sci_port(port);
d3184e68 1790 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1791 unsigned short scscr, scsptr;
1792
a4e02f6d
SY		 1793 /* check wheter the port has SCSPTR */
1794 if (!reg->size) {
bbb4ce50
SY		 1795 /*
1796 * Not supported by hardware. Most parts couple break and rx
1797 * interrupts together, with break detection always enabled.
1798 */
a4e02f6d 1799 return;
bbb4ce50 1800 }
a4e02f6d
SY		 1801
1802 scsptr = serial_port_in(port, SCSPTR);
1803 scscr = serial_port_in(port, SCSCR);
1804
1805 if (break_state == -1) {
1806 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1807 scscr &= ~SCSCR_TE;
1808 } else {
1809 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1810 scscr |= SCSCR_TE;
1811 }
1812
1813 serial_port_out(port, SCSPTR, scsptr);
1814 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1815}
1816
1817static int sci_startup(struct uart_port *port)
1818{
a5660ada 1819 struct sci_port *s = to_sci_port(port);
33b48e16 1820 unsigned long flags;
073e84c9 1821 int ret;
1da177e4 1822
73a19e4c
GL		 1823 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1824
073e84c9
PM		 1825 ret = sci_request_irq(s);
1826 if (unlikely(ret < 0))
1827 return ret;
1828
73a19e4c 1829 sci_request_dma(port);
073e84c9 1830
33b48e16 1831 spin_lock_irqsave(&port->lock, flags);
d656901b 1832 sci_start_tx(port);
73a19e4c 1833 sci_start_rx(port);
33b48e16 1834 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1835
1836 return 0;
1837}
1838
1839static void sci_shutdown(struct uart_port *port)
1840{
a5660ada 1841 struct sci_port *s = to_sci_port(port);
33b48e16 1842 unsigned long flags;
1da177e4 1843
73a19e4c
GL		 1844 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1845
33b48e16 1846 spin_lock_irqsave(&port->lock, flags);
1da177e4 1847 sci_stop_rx(port);
b129a8cc 1848 sci_stop_tx(port);
33b48e16 1849 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1850
9ab76556
AM		 1851#ifdef CONFIG_SERIAL_SH_SCI_DMA
1852 if (s->chan_rx) {
1853 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1854 port->line);
1855 del_timer_sync(&s->rx_timer);
1856 }
1857#endif
1858
73a19e4c 1859 sci_free_dma(port);
1da177e4 1860 sci_free_irq(s);
1da177e4
LT		 1861}
1862
ec09c5eb 1863static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1864 unsigned long freq)
1865{
dcafbb47 1866 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
26c92f37
PM		 1867}
1868
f303b364 1869/* calculate sample rate, BRR, and clock select for HSCIF */
bdcb3826
GU		 1870static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq, int *brr,
1871 unsigned int *srr, unsigned int *cks)
f303b364 1872{
de01e6cd 1873 unsigned int sr, br, prediv, scrate, c;
95a2703e 1874 int err, recv_margin;
f303b364 1875 int min_err = 1000; /* 100% */
730c4e78 1876 int recv_max_margin = 0;
f303b364
UH		 1877
1878 /* Find the combination of sample rate and clock select with the
1879 smallest deviation from the desired baud rate. */
1880 for (sr = 8; sr <= 32; sr++) {
1881 for (c = 0; c <= 3; c++) {
1882 /* integerized formulas from HSCIF documentation */
de01e6cd
GU		 1883 prediv = sr * (1 << (2 * c + 1));
1884
1885 /*
1886 * We need to calculate:
1887 *
1888 * br = freq / (prediv * bps) clamped to [1..256]
1889 * err = (freq / (br * prediv * bps / 1000)) - 1000
1890 *
1891 * Watch out for overflow when calculating the desired
1892 * sampling clock rate!
1893 */
1894 if (bps > UINT_MAX / prediv)
1895 break;
1896
1897 scrate = prediv * bps;
1898 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 1899 br = clamp(br, 1U, 256U);
de01e6cd
GU		 1900 err = DIV_ROUND_CLOSEST(freq, (br * scrate) / 1000) -
1901 1000;
730c4e78
NI		 1902 /* Calc recv margin
1903 * M: Receive margin (%)
1904 * N: Ratio of bit rate to clock (N = sampling rate)
1905 * D: Clock duty (D = 0 to 1.0)
1906 * L: Frame length (L = 9 to 12)
1907 * F: Absolute value of clock frequency deviation
1908 *
1909 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1910 * (|D - 0.5| / N * (1 + F))|
1911 * NOTE: Usually, treat D for 0.5, F is 0 by this
1912 * calculation.
1913 */
1914 recv_margin = abs((500 -
1915 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
f53297fb 1916 if (abs(min_err) > abs(err)) {
f303b364 1917 min_err = err;
730c4e78
NI		 1918 recv_max_margin = recv_margin;
1919 } else if ((min_err == err) &&
1920 (recv_margin > recv_max_margin))
1921 recv_max_margin = recv_margin;
1922 else
1923 continue;
1924
95a2703e 1925 *brr = br - 1;
730c4e78
NI		 1926 *srr = sr - 1;
1927 *cks = c;
f303b364
UH		 1928 }
1929 }
1930
1931 if (min_err == 1000) {
1932 WARN_ON(1);
1933 /* use defaults */
1934 *brr = 255;
1935 *srr = 15;
1936 *cks = 0;
1937 }
1938}
1939
1ba76220
MD		 1940static void sci_reset(struct uart_port *port)
1941{
d3184e68 1942 const struct plat_sci_reg *reg;
1ba76220
MD		 1943 unsigned int status;
1944
1945 do {
b12bb29f 1946 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1947 } while (!(status & SCxSR_TEND(port)));
1948
b12bb29f 1949 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1950
0979e0e6
PM		 1951 reg = sci_getreg(port, SCFCR);
1952 if (reg->size)
b12bb29f 1953 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1954}
1955
606d099c
AC		 1956static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1957 struct ktermios *old)
1da177e4 1958{
00b9de9c 1959 struct sci_port *s = to_sci_port(port);
d3184e68 1960 const struct plat_sci_reg *reg;
730c4e78 1961 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 1962 int t = -1;
d4759ded 1963 unsigned int srr = 15;
1da177e4 1964
730c4e78
NI		 1965 if ((termios->c_cflag & CSIZE) == CS7)
1966 smr_val |= SCSMR_CHR;
1967 if (termios->c_cflag & PARENB)
1968 smr_val |= SCSMR_PE;
1969 if (termios->c_cflag & PARODD)
1970 smr_val |= SCSMR_PE | SCSMR_ODD;
1971 if (termios->c_cflag & CSTOPB)
1972 smr_val |= SCSMR_STOP;
1973
154280fd
MD		 1974 /*
1975 * earlyprintk comes here early on with port->uartclk set to zero.
1976 * the clock framework is not up and running at this point so here
1977 * we assume that 115200 is the maximum baud rate. please note that
1978 * the baud rate is not programmed during earlyprintk - it is assumed
1979 * that the previous boot loader has enabled required clocks and
1980 * setup the baud rate generator hardware for us already.
1981 */
1982 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1983
154280fd 1984 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1985 if (likely(baud && port->uartclk)) {
ec09c5eb 1986 if (s->cfg->type == PORT_HSCIF) {
f303b364 1987 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
bdcb3826 1988 &cks);
f303b364 1989 } else {
ec09c5eb 1990 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 1991 for (cks = 0; t >= 256 && cks <= 3; cks++)
1992 t >>= 2;
1993 }
1994 }
e108b2ca 1995
23241d43 1996 sci_port_enable(s);
36003386 1997
1ba76220 1998 sci_reset(port);
1da177e4 1999
2944a331 2000 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1da177e4
LT		 2001
2002 uart_update_timeout(port, termios->c_cflag, baud);
2003
9d482cc3
TY		 2004 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
2005 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 2006
4ffc3cdb 2007 if (t >= 0) {
26de4f1b 2008 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 2009 serial_port_out(port, SCBRR, t);
f303b364
UH		 2010 reg = sci_getreg(port, HSSRR);
2011 if (reg->size)
2012 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 2013 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 2014 } else
2015 serial_port_out(port, SCSMR, smr_val);
1da177e4 2016
d5701647 2017 sci_init_pins(port, termios->c_cflag);
0979e0e6 2018
73c3d53f
PM		 2019 reg = sci_getreg(port, SCFCR);
2020 if (reg->size) {
b12bb29f 2021 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2022
73c3d53f 2023 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 2024 if (termios->c_cflag & CRTSCTS)
2025 ctrl |= SCFCR_MCE;
2026 else
2027 ctrl &= ~SCFCR_MCE;
faf02f8f 2028 }
73c3d53f
PM		 2029
2030 /*
2031 * As we've done a sci_reset() above, ensure we don't
2032 * interfere with the FIFOs while toggling MCE. As the
2033 * reset values could still be set, simply mask them out.
2034 */
2035 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2036
b12bb29f 2037 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2038 }
b7a76e4b 2039
b12bb29f 2040 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 2041
3089f381
GL		 2042#ifdef CONFIG_SERIAL_SH_SCI_DMA
2043 /*
5f6d8515 2044 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2045 * See serial_core.c::uart_update_timeout().
2046 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2047 * function calculates 1 jiffie for the data plus 5 jiffies for the
2048 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2049 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2050 * value obtained by this formula is too small. Therefore, if the value
2051 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2052 */
2053 if (s->chan_rx) {
5f6d8515
NI		 2054 unsigned int bits;
2055
2056 /* byte size and parity */
2057 switch (termios->c_cflag & CSIZE) {
2058 case CS5:
2059 bits = 7;
2060 break;
2061 case CS6:
2062 bits = 8;
2063 break;
2064 case CS7:
2065 bits = 9;
2066 break;
2067 default:
2068 bits = 10;
2069 break;
2070 }
2071
2072 if (termios->c_cflag & CSTOPB)
2073 bits++;
2074 if (termios->c_cflag & PARENB)
2075 bits++;
2076 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2077 (baud / 10), 10);
9b971cd2 2078 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2079 s->rx_timeout * 1000 / HZ, port->timeout);
2080 if (s->rx_timeout < msecs_to_jiffies(20))
2081 s->rx_timeout = msecs_to_jiffies(20);
2082 }
2083#endif
2084
1da177e4 2085 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2086 sci_start_rx(port);
36003386 2087
23241d43 2088 sci_port_disable(s);
1da177e4
LT		 2089}
2090
0174e5ca
TK		 2091static void sci_pm(struct uart_port *port, unsigned int state,
2092 unsigned int oldstate)
2093{
2094 struct sci_port *sci_port = to_sci_port(port);
2095
2096 switch (state) {
d3dfe5d9 2097 case UART_PM_STATE_OFF:
0174e5ca
TK		 2098 sci_port_disable(sci_port);
2099 break;
2100 default:
2101 sci_port_enable(sci_port);
2102 break;
2103 }
2104}
2105
1da177e4
LT		 2106static const char *sci_type(struct uart_port *port)
2107{
2108 switch (port->type) {
e7c98dc7
MT		 2109 case PORT_IRDA:
2110 return "irda";
2111 case PORT_SCI:
2112 return "sci";
2113 case PORT_SCIF:
2114 return "scif";
2115 case PORT_SCIFA:
2116 return "scifa";
d1d4b10c
GL		 2117 case PORT_SCIFB:
2118 return "scifb";
f303b364
UH		 2119 case PORT_HSCIF:
2120 return "hscif";
1da177e4
LT		 2121 }
2122
fa43972f 2123 return NULL;
1da177e4
LT		 2124}
2125
f6e9495d
PM		 2126static int sci_remap_port(struct uart_port *port)
2127{
e4d6f911 2128 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2129
2130 /*
2131 * Nothing to do if there's already an established membase.
2132 */
2133 if (port->membase)
2134 return 0;
2135
2136 if (port->flags & UPF_IOREMAP) {
e4d6f911 2137 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2138 if (unlikely(!port->membase)) {
2139 dev_err(port->dev, "can't remap port#%d\n", port->line);
2140 return -ENXIO;
2141 }
2142 } else {
2143 /*
2144 * For the simple (and majority of) cases where we don't
2145 * need to do any remapping, just cast the cookie
2146 * directly.
2147 */
3af4e960 2148 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2149 }
2150
2151 return 0;
2152}
2153
e2651647 2154static void sci_release_port(struct uart_port *port)
1da177e4 2155{
e4d6f911
YS		 2156 struct sci_port *sport = to_sci_port(port);
2157
e2651647
PM		 2158 if (port->flags & UPF_IOREMAP) {
2159 iounmap(port->membase);
2160 port->membase = NULL;
2161 }
2162
e4d6f911 2163 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2164}
2165
e2651647 2166static int sci_request_port(struct uart_port *port)
1da177e4 2167{
e2651647 2168 struct resource *res;
e4d6f911 2169 struct sci_port *sport = to_sci_port(port);
f6e9495d 2170 int ret;
1da177e4 2171
e4d6f911
YS		 2172 res = request_mem_region(port->mapbase, sport->reg_size,
2173 dev_name(port->dev));
2174 if (unlikely(res == NULL)) {
2175 dev_err(port->dev, "request_mem_region failed.");
e2651647 2176 return -EBUSY;
e4d6f911 2177 }
1da177e4 2178
f6e9495d
PM		 2179 ret = sci_remap_port(port);
2180 if (unlikely(ret != 0)) {
2181 release_resource(res);
2182 return ret;
7ff731ae 2183 }
e2651647
PM		 2184
2185 return 0;
2186}
2187
2188static void sci_config_port(struct uart_port *port, int flags)
2189{
2190 if (flags & UART_CONFIG_TYPE) {
2191 struct sci_port *sport = to_sci_port(port);
2192
2193 port->type = sport->cfg->type;
2194 sci_request_port(port);
2195 }
1da177e4
LT		 2196}
2197
2198static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2199{
1da177e4
LT		 2200 if (ser->baud_base < 2400)
2201 /* No paper tape reader for Mitch.. */
2202 return -EINVAL;
2203
2204 return 0;
2205}
2206
2207static struct uart_ops sci_uart_ops = {
2208 .tx_empty = sci_tx_empty,
2209 .set_mctrl = sci_set_mctrl,
2210 .get_mctrl = sci_get_mctrl,
2211 .start_tx = sci_start_tx,
2212 .stop_tx = sci_stop_tx,
2213 .stop_rx = sci_stop_rx,
1da177e4
LT		 2214 .break_ctl = sci_break_ctl,
2215 .startup = sci_startup,
2216 .shutdown = sci_shutdown,
2217 .set_termios = sci_set_termios,
0174e5ca 2218 .pm = sci_pm,
1da177e4
LT		 2219 .type = sci_type,
2220 .release_port = sci_release_port,
2221 .request_port = sci_request_port,
2222 .config_port = sci_config_port,
2223 .verify_port = sci_verify_port,
07d2a1a1
PM		 2224#ifdef CONFIG_CONSOLE_POLL
2225 .poll_get_char = sci_poll_get_char,
2226 .poll_put_char = sci_poll_put_char,
2227#endif
1da177e4
LT		 2228};
2229
a9ec81f4
LP		 2230static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2231{
2232 /* Get the SCI functional clock. It's called "fck" on ARM. */
f4de472e 2233 sci_port->fclk = devm_clk_get(dev, "fck");
a9ec81f4
LP		 2234 if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
2235 return -EPROBE_DEFER;
2236 if (!IS_ERR(sci_port->fclk))
2237 return 0;
2238
2239 /*
2240 * But it used to be called "sci_ick", and we need to maintain DT
2241 * backward compatibility.
2242 */
f4de472e 2243 sci_port->fclk = devm_clk_get(dev, "sci_ick");
a9ec81f4
LP		 2244 if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
2245 return -EPROBE_DEFER;
2246 if (!IS_ERR(sci_port->fclk))
2247 return 0;
2248
2249 /* SH has historically named the clock "sci_fck". */
f4de472e 2250 sci_port->fclk = devm_clk_get(dev, "sci_fck");
a9ec81f4
LP		 2251 if (!IS_ERR(sci_port->fclk))
2252 return 0;
2253
2254 /*
2255 * Not all SH platforms declare a clock lookup entry for SCI devices,
2256 * in which case we need to get the global "peripheral_clk" clock.
2257 */
f4de472e 2258 sci_port->fclk = devm_clk_get(dev, "peripheral_clk");
a9ec81f4
LP		 2259 if (!IS_ERR(sci_port->fclk))
2260 return 0;
2261
2262 dev_err(dev, "failed to get functional clock\n");
2263 return PTR_ERR(sci_port->fclk);
2264}
2265
9671f099 2266static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2267 struct sci_port *sci_port, unsigned int index,
2268 struct plat_sci_port *p, bool early)
e108b2ca 2269{
73a19e4c 2270 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2271 const struct resource *res;
2272 unsigned int i;
3127c6b2 2273 int ret;
e108b2ca 2274
50f0959a
PM		 2275 sci_port->cfg = p;
2276
73a19e4c
GL		 2277 port->ops = &sci_uart_ops;
2278 port->iotype = UPIO_MEM;
2279 port->line = index;
75136d48 2280
89b5c1ab
LP		 2281 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2282 if (res == NULL)
2283 return -ENOMEM;
1fcc91a6 2284
89b5c1ab 2285 port->mapbase = res->start;
e4d6f911 2286 sci_port->reg_size = resource_size(res);
1fcc91a6 2287
89b5c1ab
LP		 2288 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2289 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2290
89b5c1ab
LP		 2291 /* The SCI generates several interrupts. They can be muxed together or
2292 * connected to different interrupt lines. In the muxed case only one
2293 * interrupt resource is specified. In the non-muxed case three or four
2294 * interrupt resources are specified, as the BRI interrupt is optional.
2295 */
2296 if (sci_port->irqs[0] < 0)
2297 return -ENXIO;
1fcc91a6 2298
89b5c1ab
LP		 2299 if (sci_port->irqs[1] < 0) {
2300 sci_port->irqs[1] = sci_port->irqs[0];
2301 sci_port->irqs[2] = sci_port->irqs[0];
2302 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2303 }
2304
b545e4f4
LP		 2305 if (p->regtype == SCIx_PROBE_REGTYPE) {
2306 ret = sci_probe_regmap(p);
2307 if (unlikely(ret))
2308 return ret;
2309 }
2310
75136d48 2311 switch (p->type) {
d1d4b10c
GL		 2312 case PORT_SCIFB:
2313 port->fifosize = 256;
2e0842a1 2314 sci_port->overrun_reg = SCxSR;
75c249fd 2315 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2316 sci_port->sampling_rate = 16;
d1d4b10c 2317 break;
f303b364
UH		 2318 case PORT_HSCIF:
2319 port->fifosize = 128;
2e0842a1 2320 sci_port->overrun_reg = SCLSR;
75c249fd 2321 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2322 sci_port->sampling_rate = 0;
f303b364 2323 break;
75136d48 2324 case PORT_SCIFA:
73a19e4c 2325 port->fifosize = 64;
2e0842a1 2326 sci_port->overrun_reg = SCxSR;
75c249fd 2327 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2328 sci_port->sampling_rate = 16;
75136d48
MP		 2329 break;
2330 case PORT_SCIF:
73a19e4c 2331 port->fifosize = 16;
ec09c5eb 2332 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2333 sci_port->overrun_reg = SCxSR;
75c249fd 2334 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2335 sci_port->sampling_rate = 16;
ec09c5eb 2336 } else {
2e0842a1 2337 sci_port->overrun_reg = SCLSR;
75c249fd 2338 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2339 sci_port->sampling_rate = 32;
ec09c5eb 2340 }
75136d48
MP		 2341 break;
2342 default:
73a19e4c 2343 port->fifosize = 1;
2e0842a1 2344 sci_port->overrun_reg = SCxSR;
75c249fd 2345 sci_port->overrun_mask = SCI_ORER;
f84b6bdc 2346 sci_port->sampling_rate = 32;
75136d48
MP		 2347 break;
2348 }
7b6fd3bf 2349
878fbb91
LP		 2350 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2351 * match the SoC datasheet, this should be investigated. Let platform
2352 * data override the sampling rate for now.
ec09c5eb 2353 */
f84b6bdc
GU		 2354 if (p->sampling_rate)
2355 sci_port->sampling_rate = p->sampling_rate;
ec09c5eb 2356
1fcc91a6 2357 if (!early) {
a9ec81f4
LP		 2358 ret = sci_init_clocks(sci_port, &dev->dev);
2359 if (ret < 0)
2360 return ret;
c7ed1ab3 2361
73a19e4c 2362 port->dev = &dev->dev;
5e50d2d6
MD		 2363
2364 pm_runtime_enable(&dev->dev);
7b6fd3bf 2365 }
e108b2ca 2366
7ed7e071
MD		 2367 sci_port->break_timer.data = (unsigned long)sci_port;
2368 sci_port->break_timer.function = sci_break_timer;
2369 init_timer(&sci_port->break_timer);
2370
debf9507
PM		 2371 /*
2372 * Establish some sensible defaults for the error detection.
2373 */
5da0f468
GU		 2374 if (p->type == PORT_SCI) {
2375 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2376 sci_port->error_clear = SCI_ERROR_CLEAR;
2377 } else {
2378 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2379 sci_port->error_clear = SCIF_ERROR_CLEAR;
2380 }
debf9507 2381
3ae988d9
LP		 2382 /*
2383 * Make the error mask inclusive of overrun detection, if
2384 * supported.
2385 */
5da0f468 2386 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2387 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2388 sci_port->error_clear &= ~sci_port->overrun_mask;
2389 }
debf9507 2390
ce6738b6 2391 port->type = p->type;
b6e4a3f1 2392 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2393 port->regshift = p->regshift;
73a19e4c 2394
ce6738b6 2395 /*
61a6976b 2396 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2397 * for the multi-IRQ ports, which is where we are primarily
2398 * concerned with the shutdown path synchronization.
2399 *
2400 * For the muxed case there's nothing more to do.
2401 */
1fcc91a6 2402 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2403 port->irqflags = 0;
73a19e4c 2404
61a6976b
PM		 2405 port->serial_in = sci_serial_in;
2406 port->serial_out = sci_serial_out;
2407
937bb6e4
GL		 2408 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2409 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2410 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2411
c7ed1ab3 2412 return 0;
e108b2ca
PM		 2413}
2414
6dae1421
LP		 2415static void sci_cleanup_single(struct sci_port *port)
2416{
6dae1421
LP		 2417 pm_runtime_disable(port->port.dev);
2418}
2419
1da177e4 2420#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2421static void serial_console_putchar(struct uart_port *port, int ch)
2422{
2423 sci_poll_put_char(port, ch);
2424}
2425
1da177e4
LT		 2426/*
2427 * Print a string to the serial port trying not to disturb
2428 * any possible real use of the port...
2429 */
2430static void serial_console_write(struct console *co, const char *s,
2431 unsigned count)
2432{
906b17dc
PM		 2433 struct sci_port *sci_port = &sci_ports[co->index];
2434 struct uart_port *port = &sci_port->port;
a67969b5 2435 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2436 unsigned long flags;
2437 int locked = 1;
2438
2439 local_irq_save(flags);
2440 if (port->sysrq)
2441 locked = 0;
2442 else if (oops_in_progress)
2443 locked = spin_trylock(&port->lock);
2444 else
2445 spin_lock(&port->lock);
2446
a67969b5 2447 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2448 ctrl = serial_port_in(port, SCSCR);
a67969b5
GU		 2449 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2450 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2451 serial_port_out(port, SCSCR, ctrl_temp);
07d2a1a1 2452
501b825d 2453 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2454
2455 /* wait until fifo is empty and last bit has been transmitted */
2456 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2457 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2458 cpu_relax();
40f70c03
SK		 2459
2460 /* restore the SCSCR */
2461 serial_port_out(port, SCSCR, ctrl);
2462
2463 if (locked)
2464 spin_unlock(&port->lock);
2465 local_irq_restore(flags);
1da177e4
LT		 2466}
2467
9671f099 2468static int serial_console_setup(struct console *co, char *options)
1da177e4 2469{
dc8e6f5b 2470 struct sci_port *sci_port;
1da177e4
LT		 2471 struct uart_port *port;
2472 int baud = 115200;
2473 int bits = 8;
2474 int parity = 'n';
2475 int flow = 'n';
2476 int ret;
2477
e108b2ca 2478 /*
906b17dc 2479 * Refuse to handle any bogus ports.
1da177e4 2480 */
906b17dc 2481 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2482 return -ENODEV;
e108b2ca 2483
906b17dc
PM		 2484 sci_port = &sci_ports[co->index];
2485 port = &sci_port->port;
2486
b2267a6b
AC		 2487 /*
2488 * Refuse to handle uninitialized ports.
2489 */
2490 if (!port->ops)
2491 return -ENODEV;
2492
f6e9495d
PM		 2493 ret = sci_remap_port(port);
2494 if (unlikely(ret != 0))
2495 return ret;
e108b2ca 2496
1da177e4
LT		 2497 if (options)
2498 uart_parse_options(options, &baud, &parity, &bits, &flow);
2499
ab7cfb55 2500 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2501}
2502
2503static struct console serial_console = {
2504 .name = "ttySC",
906b17dc 2505 .device = uart_console_device,
1da177e4
LT		 2506 .write = serial_console_write,
2507 .setup = serial_console_setup,
fa5da2f7 2508 .flags = CON_PRINTBUFFER,
1da177e4 2509 .index = -1,
906b17dc 2510 .data = &sci_uart_driver,
1da177e4
LT		 2511};
2512
7b6fd3bf
MD		 2513static struct console early_serial_console = {
2514 .name = "early_ttySC",
2515 .write = serial_console_write,
2516 .flags = CON_PRINTBUFFER,
906b17dc 2517 .index = -1,
7b6fd3bf 2518};
ecdf8a46 2519
7b6fd3bf
MD		 2520static char early_serial_buf[32];
2521
9671f099 2522static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2523{
574de559 2524 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2525
2526 if (early_serial_console.data)
2527 return -EEXIST;
2528
2529 early_serial_console.index = pdev->id;
ecdf8a46 2530
1fcc91a6 2531 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2532
2533 serial_console_setup(&early_serial_console, early_serial_buf);
2534
2535 if (!strstr(early_serial_buf, "keep"))
2536 early_serial_console.flags |= CON_BOOT;
2537
2538 register_console(&early_serial_console);
2539 return 0;
2540}
6a8c9799
NI		 2541
2542#define SCI_CONSOLE (&serial_console)
2543
ecdf8a46 2544#else
9671f099 2545static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2546{
2547 return -EINVAL;
2548}
1da177e4 2549
6a8c9799
NI		 2550#define SCI_CONSOLE NULL
2551
2552#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2553
6c13d5d2 2554static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2555
2556static struct uart_driver sci_uart_driver = {
2557 .owner = THIS_MODULE,
2558 .driver_name = "sci",
1da177e4
LT		 2559 .dev_name = "ttySC",
2560 .major = SCI_MAJOR,
2561 .minor = SCI_MINOR_START,
e108b2ca 2562 .nr = SCI_NPORTS,
1da177e4
LT		 2563 .cons = SCI_CONSOLE,
2564};
2565
54507f6e 2566static int sci_remove(struct platform_device *dev)
e552de24 2567{
d535a230 2568 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2569
d535a230
PM		 2570 cpufreq_unregister_notifier(&port->freq_transition,
2571 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2572
d535a230
PM		 2573 uart_remove_one_port(&sci_uart_driver, &port->port);
2574
6dae1421 2575 sci_cleanup_single(port);
e552de24 2576
e552de24
MD		 2577 return 0;
2578}
2579
20bdcab8
BH		 2580struct sci_port_info {
2581 unsigned int type;
2582 unsigned int regtype;
2583};
2584
2585static const struct of_device_id of_sci_match[] = {
2586 {
2587 .compatible = "renesas,scif",
ff43da00 2588 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2589 .type = PORT_SCIF,
2590 .regtype = SCIx_SH4_SCIF_REGTYPE,
2591 },
2592 }, {
2593 .compatible = "renesas,scifa",
ff43da00 2594 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2595 .type = PORT_SCIFA,
2596 .regtype = SCIx_SCIFA_REGTYPE,
2597 },
2598 }, {
2599 .compatible = "renesas,scifb",
ff43da00 2600 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2601 .type = PORT_SCIFB,
2602 .regtype = SCIx_SCIFB_REGTYPE,
2603 },
2604 }, {
2605 .compatible = "renesas,hscif",
ff43da00 2606 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2607 .type = PORT_HSCIF,
2608 .regtype = SCIx_HSCIF_REGTYPE,
2609 },
e1d0be61
YS		 2610 }, {
2611 .compatible = "renesas,sci",
2612 .data = &(const struct sci_port_info) {
2613 .type = PORT_SCI,
2614 .regtype = SCIx_SCI_REGTYPE,
2615 },
20bdcab8
BH		 2616 }, {
2617 /* Terminator */
2618 },
2619};
2620MODULE_DEVICE_TABLE(of, of_sci_match);
2621
2622static struct plat_sci_port *
2623sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2624{
2625 struct device_node *np = pdev->dev.of_node;
2626 const struct of_device_id *match;
2627 const struct sci_port_info *info;
2628 struct plat_sci_port *p;
2629 int id;
2630
2631 if (!IS_ENABLED(CONFIG_OF) || !np)
2632 return NULL;
2633
495bb47c 2634 match = of_match_node(of_sci_match, np);
20bdcab8
BH		 2635 if (!match)
2636 return NULL;
2637
2638 info = match->data;
2639
2640 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2641 if (!p)
20bdcab8 2642 return NULL;
20bdcab8 2643
2095fc76 2644 /* Get the line number from the aliases node. */
20bdcab8
BH		 2645 id = of_alias_get_id(np, "serial");
2646 if (id < 0) {
2647 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2648 return NULL;
2649 }
2650
2651 *dev_id = id;
2652
2653 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2654 p->type = info->type;
2655 p->regtype = info->regtype;
2656 p->scscr = SCSCR_RE | SCSCR_TE;
2657
2658 return p;
2659}
2660
9671f099 2661static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2662 unsigned int index,
2663 struct plat_sci_port *p,
2664 struct sci_port *sciport)
2665{
0ee70712
MD		 2666 int ret;
2667
2668 /* Sanity check */
2669 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2670 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2671 index+1, SCI_NPORTS);
9b971cd2 2672 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2673 return -EINVAL;
0ee70712
MD		 2674 }
2675
1fcc91a6 2676 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2677 if (ret)
2678 return ret;
0ee70712 2679
6dae1421
LP		 2680 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2681 if (ret) {
2682 sci_cleanup_single(sciport);
2683 return ret;
2684 }
2685
2686 return 0;
0ee70712
MD		 2687}
2688
9671f099 2689static int sci_probe(struct platform_device *dev)
1da177e4 2690{
20bdcab8
BH		 2691 struct plat_sci_port *p;
2692 struct sci_port *sp;
2693 unsigned int dev_id;
ecdf8a46 2694 int ret;
d535a230 2695
ecdf8a46
PM		 2696 /*
2697 * If we've come here via earlyprintk initialization, head off to
2698 * the special early probe. We don't have sufficient device state
2699 * to make it beyond this yet.
2700 */
2701 if (is_early_platform_device(dev))
2702 return sci_probe_earlyprintk(dev);
7b6fd3bf 2703
20bdcab8
BH		 2704 if (dev->dev.of_node) {
2705 p = sci_parse_dt(dev, &dev_id);
2706 if (p == NULL)
2707 return -EINVAL;
2708 } else {
2709 p = dev->dev.platform_data;
2710 if (p == NULL) {
2711 dev_err(&dev->dev, "no platform data supplied\n");
2712 return -EINVAL;
2713 }
2714
2715 dev_id = dev->id;
2716 }
2717
2718 sp = &sci_ports[dev_id];
d535a230 2719 platform_set_drvdata(dev, sp);
e552de24 2720
20bdcab8 2721 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2722 if (ret)
6dae1421 2723 return ret;
e552de24 2724
d535a230 2725 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2726
d535a230
PM		 2727 ret = cpufreq_register_notifier(&sp->freq_transition,
2728 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2729 if (unlikely(ret < 0)) {
bf13c9a8 2730 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2731 sci_cleanup_single(sp);
2732 return ret;
2733 }
1da177e4
LT		 2734
2735#ifdef CONFIG_SH_STANDARD_BIOS
2736 sh_bios_gdb_detach();
2737#endif
2738
e108b2ca 2739 return 0;
1da177e4
LT		 2740}
2741
cb876341 2742static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2743{
d535a230 2744 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2745
d535a230
PM		 2746 if (sport)
2747 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2748
e108b2ca
PM		 2749 return 0;
2750}
1da177e4 2751
cb876341 2752static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2753{
d535a230 2754 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2755
d535a230
PM		 2756 if (sport)
2757 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2758
2759 return 0;
2760}
2761
cb876341 2762static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2763
e108b2ca
PM		 2764static struct platform_driver sci_driver = {
2765 .probe = sci_probe,
b9e39c89 2766 .remove = sci_remove,
e108b2ca
PM		 2767 .driver = {
2768 .name = "sh-sci",
6daa79b3 2769 .pm = &sci_dev_pm_ops,
20bdcab8 2770 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2771 },
2772};
2773
2774static int __init sci_init(void)
2775{
2776 int ret;
2777
6c13d5d2 2778 pr_info("%s\n", banner);
e108b2ca 2779
e108b2ca
PM		 2780 ret = uart_register_driver(&sci_uart_driver);
2781 if (likely(ret == 0)) {
2782 ret = platform_driver_register(&sci_driver);
2783 if (unlikely(ret))
2784 uart_unregister_driver(&sci_uart_driver);
2785 }
2786
2787 return ret;
2788}
2789
2790static void __exit sci_exit(void)
2791{
2792 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2793 uart_unregister_driver(&sci_uart_driver);
2794}
2795
7b6fd3bf
MD		 2796#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2797early_platform_init_buffer("earlyprintk", &sci_driver,
2798 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2799#endif
1da177e4
LT		 2800module_init(sci_init);
2801module_exit(sci_exit);
2802
e108b2ca 2803MODULE_LICENSE("GPL");
e169c139 2804MODULE_ALIAS("platform:sh-sci");
7f405f9c 2805MODULE_AUTHOR("Paul Mundt");
f303b364 2806MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
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