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serial: Fix port type numbering for TI DA8xx
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
f4998e55 5 * Copyright (C) 2015 Glider bvba
3ea6bc3d 6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 15 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
0b3d4ef6
PM		 21#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
1da177e4
LT		 24
25#undef DEBUG
26
8fb9631c
LP		 27#include <linux/clk.h>
28#include <linux/console.h>
29#include <linux/ctype.h>
30#include <linux/cpufreq.h>
31#include <linux/delay.h>
32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/err.h>
1da177e4 35#include <linux/errno.h>
8fb9631c 36#include <linux/init.h>
1da177e4 37#include <linux/interrupt.h>
1da177e4 38#include <linux/ioport.h>
8fb9631c
LP		 39#include <linux/major.h>
40#include <linux/module.h>
1da177e4 41#include <linux/mm.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
f907c9ea 60#include "serial_mctrl_gpio.h"
1da177e4
LT		 61#include "sh-sci.h"
62
89b5c1ab
LP		 63/* Offsets into the sci_port->irqs array */
64enum {
65 SCIx_ERI_IRQ,
66 SCIx_RXI_IRQ,
67 SCIx_TXI_IRQ,
68 SCIx_BRI_IRQ,
69 SCIx_NR_IRQS,
70
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72};
73
74#define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79
f4998e55
GU		 80enum SCI_CLKS {
81 SCI_FCK, /* Functional Clock */
6af27bf2 82 SCI_SCK, /* Optional External Clock */
1270f865
GU		 83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
f4998e55
GU		 85 SCI_NUM_CLKS
86};
87
69eee8e9
GU		 88/* Bit x set means sampling rate x + 1 is supported */
89#define SCI_SR(x) BIT((x) - 1)
90#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
91
92a05748
GU		 92#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
95
69eee8e9
GU		 96#define min_sr(_port) ffs((_port)->sampling_rate_mask)
97#define max_sr(_port) fls((_port)->sampling_rate_mask)
98
99/* Iterate over all supported sampling rates, from high to low */
100#define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
103
e095ee6b
LP		 104struct plat_sci_reg {
105 u8 offset, size;
106};
107
108struct sci_port_params {
109 const struct plat_sci_reg regs[SCIx_NR_REGS];
b2f20ed9
LP		 110 unsigned int fifosize;
111 unsigned int overrun_reg;
112 unsigned int overrun_mask;
113 unsigned int sampling_rate_mask;
114 unsigned int error_mask;
115 unsigned int error_clear;
e095ee6b
LP		 116};
117
e108b2ca
PM		 118struct sci_port {
119 struct uart_port port;
120
ce6738b6 121 /* Platform configuration */
e095ee6b 122 const struct sci_port_params *params;
daf5a895 123 const struct plat_sci_port *cfg;
69eee8e9 124 unsigned int sampling_rate_mask;
e4d6f911 125 resource_size_t reg_size;
f907c9ea 126 struct mctrl_gpios *gpios;
e108b2ca 127
f4998e55
GU		 128 /* Clocks */
129 struct clk *clks[SCI_NUM_CLKS];
130 unsigned long clk_rates[SCI_NUM_CLKS];
edad1f20 131
1fcc91a6 132 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 133 char *irqstr[SCIx_NR_IRQS];
134
73a19e4c
GL		 135 struct dma_chan *chan_tx;
136 struct dma_chan *chan_rx;
f43dc23d 137
73a19e4c 138#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 139 dma_cookie_t cookie_tx;
140 dma_cookie_t cookie_rx[2];
141 dma_cookie_t active_rx;
79904420
GU		 142 dma_addr_t tx_dma_addr;
143 unsigned int tx_dma_len;
73a19e4c 144 struct scatterlist sg_rx[2];
7b39d901 145 void *rx_buf[2];
73a19e4c 146 size_t buf_len_rx;
73a19e4c 147 struct work_struct work_tx;
73a19e4c 148 struct timer_list rx_timer;
3089f381 149 unsigned int rx_timeout;
73a19e4c 150#endif
03940376 151 unsigned int rx_frame;
18e8cf15 152 int rx_trigger;
03940376
UH		 153 struct timer_list rx_fifo_timer;
154 int rx_fifo_timeout;
33f50ffc 155
97ed9790 156 bool has_rtscts;
33f50ffc 157 bool autorts;
e108b2ca
PM		 158};
159
e108b2ca 160#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 161
e108b2ca
PM		 162static struct sci_port sci_ports[SCI_NPORTS];
163static struct uart_driver sci_uart_driver;
1da177e4 164
e7c98dc7
MT		 165static inline struct sci_port *
166to_sci_port(struct uart_port *uart)
167{
168 return container_of(uart, struct sci_port, port);
169}
170
e095ee6b 171static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
61a6976b
PM		 172 /*
173 * Common SCI definitions, dependent on the port's regshift
174 * value.
175 */
176 [SCIx_SCI_REGTYPE] = {
e095ee6b
LP		 177 .regs = {
178 [SCSMR] = { 0x00, 8 },
179 [SCBRR] = { 0x01, 8 },
180 [SCSCR] = { 0x02, 8 },
181 [SCxTDR] = { 0x03, 8 },
182 [SCxSR] = { 0x04, 8 },
183 [SCxRDR] = { 0x05, 8 },
184 },
b2f20ed9
LP		 185 .fifosize = 1,
186 .overrun_reg = SCxSR,
187 .overrun_mask = SCI_ORER,
188 .sampling_rate_mask = SCI_SR(32),
189 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
190 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 191 },
192
193 /*
a752ba18 194 * Common definitions for legacy IrDA ports.
61a6976b
PM		 195 */
196 [SCIx_IRDA_REGTYPE] = {
e095ee6b
LP		 197 .regs = {
198 [SCSMR] = { 0x00, 8 },
199 [SCBRR] = { 0x02, 8 },
200 [SCSCR] = { 0x04, 8 },
201 [SCxTDR] = { 0x06, 8 },
202 [SCxSR] = { 0x08, 16 },
203 [SCxRDR] = { 0x0a, 8 },
204 [SCFCR] = { 0x0c, 8 },
205 [SCFDR] = { 0x0e, 16 },
206 },
b2f20ed9
LP		 207 .fifosize = 1,
208 .overrun_reg = SCxSR,
209 .overrun_mask = SCI_ORER,
210 .sampling_rate_mask = SCI_SR(32),
211 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
212 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 213 },
214
215 /*
216 * Common SCIFA definitions.
217 */
218 [SCIx_SCIFA_REGTYPE] = {
e095ee6b
LP		 219 .regs = {
220 [SCSMR] = { 0x00, 16 },
221 [SCBRR] = { 0x04, 8 },
222 [SCSCR] = { 0x08, 16 },
223 [SCxTDR] = { 0x20, 8 },
224 [SCxSR] = { 0x14, 16 },
225 [SCxRDR] = { 0x24, 8 },
226 [SCFCR] = { 0x18, 16 },
227 [SCFDR] = { 0x1c, 16 },
228 [SCPCR] = { 0x30, 16 },
229 [SCPDR] = { 0x34, 16 },
230 },
b2f20ed9
LP		 231 .fifosize = 64,
232 .overrun_reg = SCxSR,
233 .overrun_mask = SCIFA_ORER,
234 .sampling_rate_mask = SCI_SR_SCIFAB,
235 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
236 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 237 },
238
239 /*
240 * Common SCIFB definitions.
241 */
242 [SCIx_SCIFB_REGTYPE] = {
e095ee6b
LP		 243 .regs = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x40, 8 },
248 [SCxSR] = { 0x14, 16 },
249 [SCxRDR] = { 0x60, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCTFDR] = { 0x38, 16 },
252 [SCRFDR] = { 0x3c, 16 },
253 [SCPCR] = { 0x30, 16 },
254 [SCPDR] = { 0x34, 16 },
255 },
b2f20ed9
LP		 256 .fifosize = 256,
257 .overrun_reg = SCxSR,
258 .overrun_mask = SCIFA_ORER,
259 .sampling_rate_mask = SCI_SR_SCIFAB,
260 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
261 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 262 },
263
3af1f8a4
PE		 264 /*
265 * Common SH-2(A) SCIF definitions for ports with FIFO data
266 * count registers.
267 */
268 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 269 .regs = {
270 [SCSMR] = { 0x00, 16 },
271 [SCBRR] = { 0x04, 8 },
272 [SCSCR] = { 0x08, 16 },
273 [SCxTDR] = { 0x0c, 8 },
274 [SCxSR] = { 0x10, 16 },
275 [SCxRDR] = { 0x14, 8 },
276 [SCFCR] = { 0x18, 16 },
277 [SCFDR] = { 0x1c, 16 },
278 [SCSPTR] = { 0x20, 16 },
279 [SCLSR] = { 0x24, 16 },
280 },
b2f20ed9
LP		 281 .fifosize = 16,
282 .overrun_reg = SCLSR,
283 .overrun_mask = SCLSR_ORER,
284 .sampling_rate_mask = SCI_SR(32),
285 .error_mask = SCIF_DEFAULT_ERROR_MASK,
286 .error_clear = SCIF_ERROR_CLEAR,
3af1f8a4
PE		 287 },
288
61a6976b
PM		 289 /*
290 * Common SH-3 SCIF definitions.
291 */
292 [SCIx_SH3_SCIF_REGTYPE] = {
e095ee6b
LP		 293 .regs = {
294 [SCSMR] = { 0x00, 8 },
295 [SCBRR] = { 0x02, 8 },
296 [SCSCR] = { 0x04, 8 },
297 [SCxTDR] = { 0x06, 8 },
298 [SCxSR] = { 0x08, 16 },
299 [SCxRDR] = { 0x0a, 8 },
300 [SCFCR] = { 0x0c, 8 },
301 [SCFDR] = { 0x0e, 16 },
302 },
b2f20ed9
LP		 303 .fifosize = 16,
304 .overrun_reg = SCLSR,
305 .overrun_mask = SCLSR_ORER,
306 .sampling_rate_mask = SCI_SR(32),
307 .error_mask = SCIF_DEFAULT_ERROR_MASK,
308 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 309 },
310
311 /*
312 * Common SH-4(A) SCIF(B) definitions.
313 */
314 [SCIx_SH4_SCIF_REGTYPE] = {
e095ee6b
LP		 315 .regs = {
316 [SCSMR] = { 0x00, 16 },
317 [SCBRR] = { 0x04, 8 },
318 [SCSCR] = { 0x08, 16 },
319 [SCxTDR] = { 0x0c, 8 },
320 [SCxSR] = { 0x10, 16 },
321 [SCxRDR] = { 0x14, 8 },
322 [SCFCR] = { 0x18, 16 },
323 [SCFDR] = { 0x1c, 16 },
324 [SCSPTR] = { 0x20, 16 },
325 [SCLSR] = { 0x24, 16 },
326 },
b2f20ed9
LP		 327 .fifosize = 16,
328 .overrun_reg = SCLSR,
329 .overrun_mask = SCLSR_ORER,
330 .sampling_rate_mask = SCI_SR(32),
331 .error_mask = SCIF_DEFAULT_ERROR_MASK,
332 .error_clear = SCIF_ERROR_CLEAR,
b8bbd6b2
GU		 333 },
334
335 /*
336 * Common SCIF definitions for ports with a Baud Rate Generator for
337 * External Clock (BRG).
338 */
339 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
e095ee6b
LP		 340 .regs = {
341 [SCSMR] = { 0x00, 16 },
342 [SCBRR] = { 0x04, 8 },
343 [SCSCR] = { 0x08, 16 },
344 [SCxTDR] = { 0x0c, 8 },
345 [SCxSR] = { 0x10, 16 },
346 [SCxRDR] = { 0x14, 8 },
347 [SCFCR] = { 0x18, 16 },
348 [SCFDR] = { 0x1c, 16 },
349 [SCSPTR] = { 0x20, 16 },
350 [SCLSR] = { 0x24, 16 },
351 [SCDL] = { 0x30, 16 },
352 [SCCKS] = { 0x34, 16 },
353 },
b2f20ed9
LP		 354 .fifosize = 16,
355 .overrun_reg = SCLSR,
356 .overrun_mask = SCLSR_ORER,
357 .sampling_rate_mask = SCI_SR(32),
358 .error_mask = SCIF_DEFAULT_ERROR_MASK,
359 .error_clear = SCIF_ERROR_CLEAR,
f303b364
UH		 360 },
361
362 /*
363 * Common HSCIF definitions.
364 */
365 [SCIx_HSCIF_REGTYPE] = {
e095ee6b
LP		 366 .regs = {
367 [SCSMR] = { 0x00, 16 },
368 [SCBRR] = { 0x04, 8 },
369 [SCSCR] = { 0x08, 16 },
370 [SCxTDR] = { 0x0c, 8 },
371 [SCxSR] = { 0x10, 16 },
372 [SCxRDR] = { 0x14, 8 },
373 [SCFCR] = { 0x18, 16 },
374 [SCFDR] = { 0x1c, 16 },
375 [SCSPTR] = { 0x20, 16 },
376 [SCLSR] = { 0x24, 16 },
377 [HSSRR] = { 0x40, 16 },
378 [SCDL] = { 0x30, 16 },
379 [SCCKS] = { 0x34, 16 },
54e14ae2
UH		 380 [HSRTRGR] = { 0x54, 16 },
381 [HSTTRGR] = { 0x58, 16 },
e095ee6b 382 },
b2f20ed9
LP		 383 .fifosize = 128,
384 .overrun_reg = SCLSR,
385 .overrun_mask = SCLSR_ORER,
386 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
387 .error_mask = SCIF_DEFAULT_ERROR_MASK,
388 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 389 },
390
391 /*
392 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
393 * register.
394 */
395 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
e095ee6b
LP		 396 .regs = {
397 [SCSMR] = { 0x00, 16 },
398 [SCBRR] = { 0x04, 8 },
399 [SCSCR] = { 0x08, 16 },
400 [SCxTDR] = { 0x0c, 8 },
401 [SCxSR] = { 0x10, 16 },
402 [SCxRDR] = { 0x14, 8 },
403 [SCFCR] = { 0x18, 16 },
404 [SCFDR] = { 0x1c, 16 },
405 [SCLSR] = { 0x24, 16 },
406 },
b2f20ed9
LP		 407 .fifosize = 16,
408 .overrun_reg = SCLSR,
409 .overrun_mask = SCLSR_ORER,
410 .sampling_rate_mask = SCI_SR(32),
411 .error_mask = SCIF_DEFAULT_ERROR_MASK,
412 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 413 },
414
415 /*
416 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
417 * count registers.
418 */
419 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 420 .regs = {
421 [SCSMR] = { 0x00, 16 },
422 [SCBRR] = { 0x04, 8 },
423 [SCSCR] = { 0x08, 16 },
424 [SCxTDR] = { 0x0c, 8 },
425 [SCxSR] = { 0x10, 16 },
426 [SCxRDR] = { 0x14, 8 },
427 [SCFCR] = { 0x18, 16 },
428 [SCFDR] = { 0x1c, 16 },
429 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
430 [SCRFDR] = { 0x20, 16 },
431 [SCSPTR] = { 0x24, 16 },
432 [SCLSR] = { 0x28, 16 },
433 },
b2f20ed9
LP		 434 .fifosize = 16,
435 .overrun_reg = SCLSR,
436 .overrun_mask = SCLSR_ORER,
437 .sampling_rate_mask = SCI_SR(32),
438 .error_mask = SCIF_DEFAULT_ERROR_MASK,
439 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 440 },
441
442 /*
443 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
444 * registers.
445 */
446 [SCIx_SH7705_SCIF_REGTYPE] = {
e095ee6b
LP		 447 .regs = {
448 [SCSMR] = { 0x00, 16 },
449 [SCBRR] = { 0x04, 8 },
450 [SCSCR] = { 0x08, 16 },
451 [SCxTDR] = { 0x20, 8 },
452 [SCxSR] = { 0x14, 16 },
453 [SCxRDR] = { 0x24, 8 },
454 [SCFCR] = { 0x18, 16 },
455 [SCFDR] = { 0x1c, 16 },
456 },
18e8cf15 457 .fifosize = 64,
b2f20ed9
LP		 458 .overrun_reg = SCxSR,
459 .overrun_mask = SCIFA_ORER,
460 .sampling_rate_mask = SCI_SR(16),
461 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
462 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 463 },
464};
465
e095ee6b 466#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
72b294cf 467
61a6976b
PM		 468/*
469 * The "offset" here is rather misleading, in that it refers to an enum
470 * value relative to the port mapping rather than the fixed offset
471 * itself, which needs to be manually retrieved from the platform's
472 * register map for the given port.
473 */
474static unsigned int sci_serial_in(struct uart_port *p, int offset)
475{
d3184e68 476 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 477
478 if (reg->size == 8)
479 return ioread8(p->membase + (reg->offset << p->regshift));
480 else if (reg->size == 16)
481 return ioread16(p->membase + (reg->offset << p->regshift));
482 else
483 WARN(1, "Invalid register access\n");
484
485 return 0;
486}
487
488static void sci_serial_out(struct uart_port *p, int offset, int value)
489{
d3184e68 490 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 491
492 if (reg->size == 8)
493 iowrite8(value, p->membase + (reg->offset << p->regshift));
494 else if (reg->size == 16)
495 iowrite16(value, p->membase + (reg->offset << p->regshift));
496 else
497 WARN(1, "Invalid register access\n");
498}
499
23241d43
PM		 500static void sci_port_enable(struct sci_port *sci_port)
501{
f4998e55
GU		 502 unsigned int i;
503
23241d43
PM		 504 if (!sci_port->port.dev)
505 return;
506
507 pm_runtime_get_sync(sci_port->port.dev);
508
f4998e55
GU		 509 for (i = 0; i < SCI_NUM_CLKS; i++) {
510 clk_prepare_enable(sci_port->clks[i]);
511 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
512 }
513 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
23241d43
PM		 514}
515
516static void sci_port_disable(struct sci_port *sci_port)
517{
f4998e55
GU		 518 unsigned int i;
519
23241d43
PM		 520 if (!sci_port->port.dev)
521 return;
522
f4998e55
GU		 523 for (i = SCI_NUM_CLKS; i-- > 0; )
524 clk_disable_unprepare(sci_port->clks[i]);
23241d43
PM		 525
526 pm_runtime_put_sync(sci_port->port.dev);
527}
528
e1910fcd
GU		 529static inline unsigned long port_rx_irq_mask(struct uart_port *port)
530{
531 /*
532 * Not all ports (such as SCIFA) will support REIE. Rather than
533 * special-casing the port type, we check the port initialization
534 * IRQ enable mask to see whether the IRQ is desired at all. If
535 * it's unset, it's logically inferred that there's no point in
536 * testing for it.
537 */
538 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
539}
540
541static void sci_start_tx(struct uart_port *port)
542{
543 struct sci_port *s = to_sci_port(port);
544 unsigned short ctrl;
545
546#ifdef CONFIG_SERIAL_SH_SCI_DMA
547 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
548 u16 new, scr = serial_port_in(port, SCSCR);
549 if (s->chan_tx)
550 new = scr | SCSCR_TDRQE;
551 else
552 new = scr & ~SCSCR_TDRQE;
553 if (new != scr)
554 serial_port_out(port, SCSCR, new);
555 }
556
557 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
558 dma_submit_error(s->cookie_tx)) {
559 s->cookie_tx = 0;
560 schedule_work(&s->work_tx);
561 }
562#endif
563
564 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
565 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
566 ctrl = serial_port_in(port, SCSCR);
567 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
568 }
569}
570
571static void sci_stop_tx(struct uart_port *port)
572{
573 unsigned short ctrl;
574
575 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
576 ctrl = serial_port_in(port, SCSCR);
577
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
579 ctrl &= ~SCSCR_TDRQE;
580
581 ctrl &= ~SCSCR_TIE;
582
583 serial_port_out(port, SCSCR, ctrl);
584}
585
586static void sci_start_rx(struct uart_port *port)
587{
588 unsigned short ctrl;
589
590 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
591
592 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
593 ctrl &= ~SCSCR_RDRQE;
594
595 serial_port_out(port, SCSCR, ctrl);
596}
597
598static void sci_stop_rx(struct uart_port *port)
599{
600 unsigned short ctrl;
601
602 ctrl = serial_port_in(port, SCSCR);
603
604 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
605 ctrl &= ~SCSCR_RDRQE;
606
607 ctrl &= ~port_rx_irq_mask(port);
608
609 serial_port_out(port, SCSCR, ctrl);
610}
611
a1b5b43f
GU		 612static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
613{
614 if (port->type == PORT_SCI) {
615 /* Just store the mask */
616 serial_port_out(port, SCxSR, mask);
b2f20ed9 617 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
a1b5b43f
GU		 618 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
619 /* Only clear the status bits we want to clear */
620 serial_port_out(port, SCxSR,
621 serial_port_in(port, SCxSR) & mask);
622 } else {
623 /* Store the mask, clear parity/framing errors */
624 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
625 }
626}
627
0b0cced1
YS		 628#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
629 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
1f6fd5c9
PM		 630
631#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 632static int sci_poll_get_char(struct uart_port *port)
1da177e4 633{
1da177e4
LT		 634 unsigned short status;
635 int c;
636
e108b2ca 637 do {
b12bb29f 638 status = serial_port_in(port, SCxSR);
1da177e4 639 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 640 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 641 continue;
642 }
3f255eb3
JW		 643 break;
644 } while (1);
645
646 if (!(status & SCxSR_RDxF(port)))
647 return NO_POLL_CHAR;
07d2a1a1 648
b12bb29f 649 c = serial_port_in(port, SCxRDR);
07d2a1a1 650
e7c98dc7 651 /* Dummy read */
b12bb29f 652 serial_port_in(port, SCxSR);
a1b5b43f 653 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 654
655 return c;
656}
1f6fd5c9 657#endif
1da177e4 658
07d2a1a1 659static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 660{
1da177e4
LT		 661 unsigned short status;
662
1da177e4 663 do {
b12bb29f 664 status = serial_port_in(port, SCxSR);
1da177e4
LT		 665 } while (!(status & SCxSR_TDxE(port)));
666
b12bb29f 667 serial_port_out(port, SCxTDR, c);
a1b5b43f 668 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 669}
0b0cced1
YS		 670#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
671 CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 672
61a6976b 673static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 674{
61a6976b 675 struct sci_port *s = to_sci_port(port);
1da177e4 676
61a6976b
PM		 677 /*
678 * Use port-specific handler if provided.
679 */
680 if (s->cfg->ops && s->cfg->ops->init_pins) {
681 s->cfg->ops->init_pins(port, cflag);
682 return;
1da177e4 683 }
41504c39 684
e9d7a45a 685 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
cfa6eb23 686 u16 data = serial_port_in(port, SCPDR);
e9d7a45a
GU		 687 u16 ctrl = serial_port_in(port, SCPCR);
688
689 /* Enable RXD and TXD pin functions */
690 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
97ed9790 691 if (to_sci_port(port)->has_rtscts) {
cfa6eb23
GU		 692 /* RTS# is output, active low, unless autorts */
693 if (!(port->mctrl & TIOCM_RTS)) {
694 ctrl |= SCPCR_RTSC;
695 data |= SCPDR_RTSD;
696 } else if (!s->autorts) {
697 ctrl |= SCPCR_RTSC;
698 data &= ~SCPDR_RTSD;
699 } else {
700 /* Enable RTS# pin function */
701 ctrl &= ~SCPCR_RTSC;
702 }
e9d7a45a
GU		 703 /* Enable CTS# pin function */
704 ctrl &= ~SCPCR_CTSC;
705 }
cfa6eb23 706 serial_port_out(port, SCPDR, data);
e9d7a45a
GU		 707 serial_port_out(port, SCPCR, ctrl);
708 } else if (sci_getreg(port, SCSPTR)->size) {
d2b9775d
GU		 709 u16 status = serial_port_in(port, SCSPTR);
710
cfa6eb23
GU		 711 /* RTS# is always output; and active low, unless autorts */
712 status |= SCSPTR_RTSIO;
713 if (!(port->mctrl & TIOCM_RTS))
714 status |= SCSPTR_RTSDT;
715 else if (!s->autorts)
716 status &= ~SCSPTR_RTSDT;
d2b9775d
GU		 717 /* CTS# and SCK are inputs */
718 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
719 serial_port_out(port, SCSPTR, status);
faf02f8f 720 }
d5701647 721}
e108b2ca 722
72b294cf 723static int sci_txfill(struct uart_port *port)
e108b2ca 724{
b2f20ed9
LP		 725 struct sci_port *s = to_sci_port(port);
726 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 727 const struct plat_sci_reg *reg;
e108b2ca 728
72b294cf
PM		 729 reg = sci_getreg(port, SCTFDR);
730 if (reg->size)
b2f20ed9 731 return serial_port_in(port, SCTFDR) & fifo_mask;
c63847a3 732
72b294cf
PM		 733 reg = sci_getreg(port, SCFDR);
734 if (reg->size)
b12bb29f 735 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 736
b12bb29f 737 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 738}
739
73a19e4c
GL		 740static int sci_txroom(struct uart_port *port)
741{
72b294cf 742 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 743}
744
745static int sci_rxfill(struct uart_port *port)
e108b2ca 746{
b2f20ed9
LP		 747 struct sci_port *s = to_sci_port(port);
748 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 749 const struct plat_sci_reg *reg;
72b294cf
PM		 750
751 reg = sci_getreg(port, SCRFDR);
752 if (reg->size)
b2f20ed9 753 return serial_port_in(port, SCRFDR) & fifo_mask;
72b294cf
PM		 754
755 reg = sci_getreg(port, SCFDR);
756 if (reg->size)
b2f20ed9 757 return serial_port_in(port, SCFDR) & fifo_mask;
72b294cf 758
b12bb29f 759 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 760}
761
1da177e4
LT		 762/* ********************************************************************** *
763 * the interrupt related routines *
764 * ********************************************************************** */
765
766static void sci_transmit_chars(struct uart_port *port)
767{
ebd2c8f6 768 struct circ_buf *xmit = &port->state->xmit;
1da177e4 769 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 770 unsigned short status;
771 unsigned short ctrl;
e108b2ca 772 int count;
1da177e4 773
b12bb29f 774 status = serial_port_in(port, SCxSR);
1da177e4 775 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 776 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 777 if (uart_circ_empty(xmit))
8e698614 778 ctrl &= ~SCSCR_TIE;
e7c98dc7 779 else
8e698614 780 ctrl |= SCSCR_TIE;
b12bb29f 781 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 782 return;
783 }
784
72b294cf 785 count = sci_txroom(port);
1da177e4
LT		 786
787 do {
788 unsigned char c;
789
790 if (port->x_char) {
791 c = port->x_char;
792 port->x_char = 0;
793 } else if (!uart_circ_empty(xmit) && !stopped) {
794 c = xmit->buf[xmit->tail];
795 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
796 } else {
797 break;
798 }
799
b12bb29f 800 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 801
802 port->icount.tx++;
803 } while (--count > 0);
804
a1b5b43f 805 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 806
807 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
808 uart_write_wakeup(port);
809 if (uart_circ_empty(xmit)) {
b129a8cc 810 sci_stop_tx(port);
1da177e4 811 } else {
b12bb29f 812 ctrl = serial_port_in(port, SCSCR);
1da177e4 813
1a22f08d 814 if (port->type != PORT_SCI) {
b12bb29f 815 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 816 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 817 }
1da177e4 818
8e698614 819 ctrl |= SCSCR_TIE;
b12bb29f 820 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 821 }
822}
823
824/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 825#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 826
94c8b6db 827static void sci_receive_chars(struct uart_port *port)
1da177e4 828{
227434f8 829 struct tty_port *tport = &port->state->port;
1da177e4
LT		 830 int i, count, copied = 0;
831 unsigned short status;
33f0f88f 832 unsigned char flag;
1da177e4 833
b12bb29f 834 status = serial_port_in(port, SCxSR);
1da177e4
LT		 835 if (!(status & SCxSR_RDxF(port)))
836 return;
837
838 while (1) {
1da177e4 839 /* Don't copy more bytes than there is room for in the buffer */
227434f8 840 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 841
842 /* If for any reason we can't copy more data, we're done! */
843 if (count == 0)
844 break;
845
846 if (port->type == PORT_SCI) {
b12bb29f 847 char c = serial_port_in(port, SCxRDR);
d5cb1319 848 if (uart_handle_sysrq_char(port, c))
1da177e4 849 count = 0;
e7c98dc7 850 else
92a19f9c 851 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 852 } else {
e7c98dc7 853 for (i = 0; i < count; i++) {
b12bb29f 854 char c = serial_port_in(port, SCxRDR);
d97fbbed 855
b12bb29f 856 status = serial_port_in(port, SCxSR);
7d12e780 857 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 858 count--; i--;
859 continue;
860 }
861
862 /* Store data and status */
73a19e4c 863 if (status & SCxSR_FER(port)) {
33f0f88f 864 flag = TTY_FRAME;
d97fbbed 865 port->icount.frame++;
762c69e3 866 dev_notice(port->dev, "frame error\n");
73a19e4c 867 } else if (status & SCxSR_PER(port)) {
33f0f88f 868 flag = TTY_PARITY;
d97fbbed 869 port->icount.parity++;
762c69e3 870 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 871 } else
872 flag = TTY_NORMAL;
762c69e3 873
92a19f9c 874 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 875 }
876 }
877
b12bb29f 878 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 879 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 880
1da177e4
LT		 881 copied += count;
882 port->icount.rx += count;
883 }
884
885 if (copied) {
886 /* Tell the rest of the system the news. New characters! */
2e124b4a 887 tty_flip_buffer_push(tport);
1da177e4 888 } else {
b12bb29f 889 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 890 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 891 }
892}
893
94c8b6db 894static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 895{
896 int copied = 0;
b12bb29f 897 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 898 struct tty_port *tport = &port->state->port;
debf9507 899 struct sci_port *s = to_sci_port(port);
1da177e4 900
3ae988d9 901 /* Handle overruns */
b2f20ed9 902 if (status & s->params->overrun_mask) {
3ae988d9 903 port->icount.overrun++;
d97fbbed 904
3ae988d9
LP		 905 /* overrun error */
906 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
907 copied++;
762c69e3 908
9b971cd2 909 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 910 }
911
e108b2ca 912 if (status & SCxSR_FER(port)) {
d5cb1319
LP		 913 /* frame error */
914 port->icount.frame++;
d97fbbed 915
d5cb1319
LP		 916 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
917 copied++;
762c69e3 918
d5cb1319 919 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 920 }
921
e108b2ca 922 if (status & SCxSR_PER(port)) {
1da177e4 923 /* parity error */
d97fbbed
PM		 924 port->icount.parity++;
925
92a19f9c 926 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 927 copied++;
762c69e3 928
9b971cd2 929 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 930 }
931
33f0f88f 932 if (copied)
2e124b4a 933 tty_flip_buffer_push(tport);
1da177e4
LT		 934
935 return copied;
936}
937
94c8b6db 938static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 939{
92a19f9c 940 struct tty_port *tport = &port->state->port;
debf9507 941 struct sci_port *s = to_sci_port(port);
d3184e68 942 const struct plat_sci_reg *reg;
2e0842a1 943 int copied = 0;
75c249fd 944 u16 status;
d830fa45 945
b2f20ed9 946 reg = sci_getreg(port, s->params->overrun_reg);
4b8c59a3 947 if (!reg->size)
d830fa45
PM		 948 return 0;
949
b2f20ed9
LP		 950 status = serial_port_in(port, s->params->overrun_reg);
951 if (status & s->params->overrun_mask) {
952 status &= ~s->params->overrun_mask;
953 serial_port_out(port, s->params->overrun_reg, status);
d830fa45 954
d97fbbed
PM		 955 port->icount.overrun++;
956
92a19f9c 957 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 958 tty_flip_buffer_push(tport);
d830fa45 959
51b31f1c 960 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 961 copied++;
962 }
963
964 return copied;
965}
966
94c8b6db 967static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 968{
969 int copied = 0;
b12bb29f 970 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 971 struct tty_port *tport = &port->state->port;
1da177e4 972
0b3d4ef6
PM		 973 if (uart_handle_break(port))
974 return 0;
975
d5cb1319 976 if (status & SCxSR_BRK(port)) {
d97fbbed
PM		 977 port->icount.brk++;
978
1da177e4 979 /* Notify of BREAK */
92a19f9c 980 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 981 copied++;
762c69e3
PM		 982
983 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 984 }
985
33f0f88f 986 if (copied)
2e124b4a 987 tty_flip_buffer_push(tport);
e108b2ca 988
d830fa45
PM		 989 copied += sci_handle_fifo_overrun(port);
990
1da177e4
LT		 991 return copied;
992}
993
a380ed46
UH		 994static int scif_set_rtrg(struct uart_port *port, int rx_trig)
995{
996 unsigned int bits;
997
998 if (rx_trig < 1)
999 rx_trig = 1;
1000 if (rx_trig >= port->fifosize)
1001 rx_trig = port->fifosize;
1002
1003 /* HSCIF can be set to an arbitrary level. */
1004 if (sci_getreg(port, HSRTRGR)->size) {
1005 serial_port_out(port, HSRTRGR, rx_trig);
1006 return rx_trig;
1007 }
1008
1009 switch (port->type) {
1010 case PORT_SCIF:
1011 if (rx_trig < 4) {
1012 bits = 0;
1013 rx_trig = 1;
1014 } else if (rx_trig < 8) {
1015 bits = SCFCR_RTRG0;
1016 rx_trig = 4;
1017 } else if (rx_trig < 14) {
1018 bits = SCFCR_RTRG1;
1019 rx_trig = 8;
1020 } else {
1021 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1022 rx_trig = 14;
1023 }
1024 break;
1025 case PORT_SCIFA:
1026 case PORT_SCIFB:
1027 if (rx_trig < 16) {
1028 bits = 0;
1029 rx_trig = 1;
1030 } else if (rx_trig < 32) {
1031 bits = SCFCR_RTRG0;
1032 rx_trig = 16;
1033 } else if (rx_trig < 48) {
1034 bits = SCFCR_RTRG1;
1035 rx_trig = 32;
1036 } else {
1037 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1038 rx_trig = 48;
1039 }
1040 break;
1041 default:
1042 WARN(1, "unknown FIFO configuration");
1043 return 1;
1044 }
1045
1046 serial_port_out(port, SCFCR,
1047 (serial_port_in(port, SCFCR) &
1048 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1049
1050 return rx_trig;
1051}
1052
03940376
UH		 1053static int scif_rtrg_enabled(struct uart_port *port)
1054{
1055 if (sci_getreg(port, HSRTRGR)->size)
1056 return serial_port_in(port, HSRTRGR) != 0;
1057 else
1058 return (serial_port_in(port, SCFCR) &
1059 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1060}
1061
1062static void rx_fifo_timer_fn(unsigned long arg)
1063{
1064 struct sci_port *s = (struct sci_port *)arg;
1065 struct uart_port *port = &s->port;
1066
1067 dev_dbg(port->dev, "Rx timed out\n");
1068 scif_set_rtrg(port, 1);
1069}
1070
5d23188a
UH		 1071static ssize_t rx_trigger_show(struct device *dev,
1072 struct device_attribute *attr,
1073 char *buf)
1074{
1075 struct uart_port *port = dev_get_drvdata(dev);
1076 struct sci_port *sci = to_sci_port(port);
1077
1078 return sprintf(buf, "%d\n", sci->rx_trigger);
1079}
1080
1081static ssize_t rx_trigger_store(struct device *dev,
1082 struct device_attribute *attr,
1083 const char *buf,
1084 size_t count)
1085{
1086 struct uart_port *port = dev_get_drvdata(dev);
1087 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1088 int ret;
5d23188a
UH		 1089 long r;
1090
4ab3c51e
DC		 1091 ret = kstrtol(buf, 0, &r);
1092 if (ret)
1093 return ret;
90afa525 1094
5d23188a 1095 sci->rx_trigger = scif_set_rtrg(port, r);
90afa525
UH		 1096 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1097 scif_set_rtrg(port, 1);
1098
5d23188a
UH		 1099 return count;
1100}
1101
1102static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1103
1104static ssize_t rx_fifo_timeout_show(struct device *dev,
1105 struct device_attribute *attr,
1106 char *buf)
1107{
1108 struct uart_port *port = dev_get_drvdata(dev);
1109 struct sci_port *sci = to_sci_port(port);
1110
1111 return sprintf(buf, "%d\n", sci->rx_fifo_timeout);
1112}
1113
1114static ssize_t rx_fifo_timeout_store(struct device *dev,
1115 struct device_attribute *attr,
1116 const char *buf,
1117 size_t count)
1118{
1119 struct uart_port *port = dev_get_drvdata(dev);
1120 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1121 int ret;
5d23188a
UH		 1122 long r;
1123
4ab3c51e
DC		 1124 ret = kstrtol(buf, 0, &r);
1125 if (ret)
1126 return ret;
5d23188a
UH		 1127 sci->rx_fifo_timeout = r;
1128 scif_set_rtrg(port, 1);
1129 if (r > 0)
1130 setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn,
1131 (unsigned long)sci);
1132 return count;
1133}
1134
1135static DEVICE_ATTR(rx_fifo_timeout, 0644, rx_fifo_timeout_show, rx_fifo_timeout_store);
1136
1137
73a19e4c 1138#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1139static void sci_dma_tx_complete(void *arg)
1140{
1141 struct sci_port *s = arg;
1142 struct uart_port *port = &s->port;
1143 struct circ_buf *xmit = &port->state->xmit;
1144 unsigned long flags;
73a19e4c 1145
e1910fcd 1146 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1147
e1910fcd 1148 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1149
e1910fcd
GU		 1150 xmit->tail += s->tx_dma_len;
1151 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1152
e1910fcd 1153 port->icount.tx += s->tx_dma_len;
1da177e4 1154
e1910fcd
GU		 1155 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1156 uart_write_wakeup(port);
1da177e4 1157
e1910fcd
GU		 1158 if (!uart_circ_empty(xmit)) {
1159 s->cookie_tx = 0;
1160 schedule_work(&s->work_tx);
1161 } else {
1162 s->cookie_tx = -EINVAL;
1163 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1164 u16 ctrl = serial_port_in(port, SCSCR);
1165 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1166 }
1167 }
1da177e4 1168
fd78a76a 1169 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1170}
1171
e1910fcd
GU		 1172/* Locking: called with port lock held */
1173static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1174{
e1910fcd
GU		 1175 struct uart_port *port = &s->port;
1176 struct tty_port *tport = &port->state->port;
1177 int copied;
1da177e4 1178
e1910fcd 1179 copied = tty_insert_flip_string(tport, buf, count);
6fc5a520 1180 if (copied < count)
e1910fcd 1181 port->icount.buf_overrun++;
1da177e4 1182
e1910fcd 1183 port->icount.rx += copied;
1da177e4 1184
e1910fcd 1185 return copied;
1da177e4
LT		 1186}
1187
e1910fcd 1188static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1189{
e1910fcd 1190 unsigned int i;
1da177e4 1191
e1910fcd
GU		 1192 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1193 if (s->active_rx == s->cookie_rx[i])
1194 return i;
1da177e4 1195
e1910fcd 1196 return -1;
1da177e4
LT		 1197}
1198
e1910fcd 1199static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1200{
e1910fcd
GU		 1201 struct dma_chan *chan = s->chan_rx;
1202 struct uart_port *port = &s->port;
1203 unsigned long flags;
1204
1205 spin_lock_irqsave(&port->lock, flags);
1206 s->chan_rx = NULL;
1207 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1208 spin_unlock_irqrestore(&port->lock, flags);
1209 dmaengine_terminate_all(chan);
1210 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1211 sg_dma_address(&s->sg_rx[0]));
1212 dma_release_channel(chan);
1213 if (enable_pio)
1214 sci_start_rx(port);
f43dc23d
PM		 1215}
1216
e1910fcd 1217static void sci_dma_rx_complete(void *arg)
1da177e4 1218{
e1910fcd 1219 struct sci_port *s = arg;
1d3db608 1220 struct dma_chan *chan = s->chan_rx;
e1910fcd 1221 struct uart_port *port = &s->port;
67f462b0 1222 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1223 unsigned long flags;
1224 int active, count = 0;
1da177e4 1225
e1910fcd
GU		 1226 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1227 s->active_rx);
cb772fe7 1228
e1910fcd 1229 spin_lock_irqsave(&port->lock, flags);
1da177e4 1230
e1910fcd
GU		 1231 active = sci_dma_rx_find_active(s);
1232 if (active >= 0)
1233 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1234
e1910fcd 1235 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1236
e1910fcd
GU		 1237 if (count)
1238 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1239
67f462b0
GU		 1240 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1241 DMA_DEV_TO_MEM,
1242 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1243 if (!desc)
1244 goto fail;
1245
1246 desc->callback = sci_dma_rx_complete;
1247 desc->callback_param = s;
1248 s->cookie_rx[active] = dmaengine_submit(desc);
1249 if (dma_submit_error(s->cookie_rx[active]))
1250 goto fail;
1251
1252 s->active_rx = s->cookie_rx[!active];
1253
1d3db608
MHF		 1254 dma_async_issue_pending(chan);
1255
6fc5a520 1256 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1257 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1258 __func__, s->cookie_rx[active], active, s->active_rx);
67f462b0
GU		 1259 return;
1260
1261fail:
1262 spin_unlock_irqrestore(&port->lock, flags);
1263 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1264 sci_rx_dma_release(s, true);
1da177e4
LT		 1265}
1266
e1910fcd 1267static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1268{
e1910fcd
GU		 1269 struct dma_chan *chan = s->chan_tx;
1270 struct uart_port *port = &s->port;
e552de24 1271 unsigned long flags;
1da177e4 1272
e1910fcd
GU		 1273 spin_lock_irqsave(&port->lock, flags);
1274 s->chan_tx = NULL;
1275 s->cookie_tx = -EINVAL;
1276 spin_unlock_irqrestore(&port->lock, flags);
1277 dmaengine_terminate_all(chan);
1278 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1279 DMA_TO_DEVICE);
1280 dma_release_channel(chan);
1281 if (enable_pio)
1282 sci_start_tx(port);
1283}
d535a230 1284
e1910fcd
GU		 1285static void sci_submit_rx(struct sci_port *s)
1286{
1287 struct dma_chan *chan = s->chan_rx;
1288 int i;
073e84c9 1289
e1910fcd
GU		 1290 for (i = 0; i < 2; i++) {
1291 struct scatterlist *sg = &s->sg_rx[i];
1292 struct dma_async_tx_descriptor *desc;
1da177e4 1293
e1910fcd
GU		 1294 desc = dmaengine_prep_slave_sg(chan,
1295 sg, 1, DMA_DEV_TO_MEM,
1296 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1297 if (!desc)
1298 goto fail;
501b825d 1299
e1910fcd
GU		 1300 desc->callback = sci_dma_rx_complete;
1301 desc->callback_param = s;
1302 s->cookie_rx[i] = dmaengine_submit(desc);
1303 if (dma_submit_error(s->cookie_rx[i]))
1304 goto fail;
9174fc8f 1305
e1910fcd 1306 }
9174fc8f 1307
e1910fcd 1308 s->active_rx = s->cookie_rx[0];
9174fc8f 1309
e1910fcd
GU		 1310 dma_async_issue_pending(chan);
1311 return;
9174fc8f 1312
e1910fcd
GU		 1313fail:
1314 if (i)
1315 dmaengine_terminate_all(chan);
1316 for (i = 0; i < 2; i++)
1317 s->cookie_rx[i] = -EINVAL;
1318 s->active_rx = -EINVAL;
e1910fcd
GU		 1319 sci_rx_dma_release(s, true);
1320}
9174fc8f 1321
e1910fcd 1322static void work_fn_tx(struct work_struct *work)
1da177e4 1323{
e1910fcd
GU		 1324 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1325 struct dma_async_tx_descriptor *desc;
1326 struct dma_chan *chan = s->chan_tx;
1327 struct uart_port *port = &s->port;
1328 struct circ_buf *xmit = &port->state->xmit;
1329 dma_addr_t buf;
1da177e4 1330
9174fc8f 1331 /*
e1910fcd
GU		 1332 * DMA is idle now.
1333 * Port xmit buffer is already mapped, and it is one page... Just adjust
1334 * offsets and lengths. Since it is a circular buffer, we have to
1335 * transmit till the end, and then the rest. Take the port lock to get a
1336 * consistent xmit buffer state.
9174fc8f 1337 */
e1910fcd
GU		 1338 spin_lock_irq(&port->lock);
1339 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1340 s->tx_dma_len = min_t(unsigned int,
1341 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1342 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1343 spin_unlock_irq(&port->lock);
0e8963de 1344
e1910fcd
GU		 1345 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1346 DMA_MEM_TO_DEV,
1347 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1348 if (!desc) {
1349 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1350 /* switch to PIO */
1351 sci_tx_dma_release(s, true);
1352 return;
1353 }
0e8963de 1354
e1910fcd
GU		 1355 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1356 DMA_TO_DEVICE);
1da177e4 1357
e1910fcd
GU		 1358 spin_lock_irq(&port->lock);
1359 desc->callback = sci_dma_tx_complete;
1360 desc->callback_param = s;
1361 spin_unlock_irq(&port->lock);
1362 s->cookie_tx = dmaengine_submit(desc);
1363 if (dma_submit_error(s->cookie_tx)) {
1364 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1365 /* switch to PIO */
1366 sci_tx_dma_release(s, true);
1367 return;
1da177e4 1368 }
1da177e4 1369
e1910fcd
GU		 1370 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1371 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1372
e1910fcd 1373 dma_async_issue_pending(chan);
1da177e4
LT		 1374}
1375
e1910fcd 1376static void rx_timer_fn(unsigned long arg)
1da177e4 1377{
e1910fcd 1378 struct sci_port *s = (struct sci_port *)arg;
e7327c09 1379 struct dma_chan *chan = s->chan_rx;
e1910fcd 1380 struct uart_port *port = &s->port;
67f462b0
GU		 1381 struct dma_tx_state state;
1382 enum dma_status status;
1383 unsigned long flags;
1384 unsigned int read;
1385 int active, count;
1386 u16 scr;
1387
67f462b0 1388 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0 1389
6fc5a520
TA		 1390 spin_lock_irqsave(&port->lock, flags);
1391
67f462b0
GU		 1392 active = sci_dma_rx_find_active(s);
1393 if (active < 0) {
1394 spin_unlock_irqrestore(&port->lock, flags);
1395 return;
1396 }
1397
1398 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1399 if (status == DMA_COMPLETE) {
6fc5a520 1400 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1401 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1402 s->active_rx, active);
3b963042
MHF		 1403
1404 /* Let packet complete handler take care of the packet */
1405 return;
1406 }
67f462b0 1407
e7327c09
MHF		 1408 dmaengine_pause(chan);
1409
1410 /*
1411 * sometimes DMA transfer doesn't stop even if it is stopped and
1412 * data keeps on coming until transaction is complete so check
1413 * for DMA_COMPLETE again
1414 * Let packet complete handler take care of the packet
1415 */
1416 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1417 if (status == DMA_COMPLETE) {
1418 spin_unlock_irqrestore(&port->lock, flags);
1419 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1420 return;
1421 }
1422
67f462b0
GU		 1423 /* Handle incomplete DMA receive */
1424 dmaengine_terminate_all(s->chan_rx);
1425 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
67f462b0
GU		 1426
1427 if (read) {
1428 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1429 if (count)
1430 tty_flip_buffer_push(&port->state->port);
1431 }
1432
756981be
GU		 1433 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1434 sci_submit_rx(s);
371cfed3
MHF		 1435
1436 /* Direct new serial port interrupts back to CPU */
1437 scr = serial_port_in(port, SCSCR);
1438 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1439 scr &= ~SCSCR_RDRQE;
1440 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1441 }
1442 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1443
1444 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1445}
1446
ff441129 1447static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
219fb0c1 1448 enum dma_transfer_direction dir)
ff441129 1449{
ff441129
GU		 1450 struct dma_chan *chan;
1451 struct dma_slave_config cfg;
1452 int ret;
1453
219fb0c1
LP		 1454 chan = dma_request_slave_channel(port->dev,
1455 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
ff441129 1456 if (!chan) {
9b7becf1 1457 dev_warn(port->dev, "dma_request_slave_channel failed\n");
ff441129
GU		 1458 return NULL;
1459 }
1460
1461 memset(&cfg, 0, sizeof(cfg));
1462 cfg.direction = dir;
1463 if (dir == DMA_MEM_TO_DEV) {
1464 cfg.dst_addr = port->mapbase +
1465 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1466 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1467 } else {
1468 cfg.src_addr = port->mapbase +
1469 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1470 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1471 }
1472
1473 ret = dmaengine_slave_config(chan, &cfg);
1474 if (ret) {
1475 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1476 dma_release_channel(chan);
1477 return NULL;
1478 }
1479
1480 return chan;
1481}
1482
e1910fcd 1483static void sci_request_dma(struct uart_port *port)
73a19e4c 1484{
e1910fcd 1485 struct sci_port *s = to_sci_port(port);
e1910fcd 1486 struct dma_chan *chan;
73a19e4c 1487
e1910fcd 1488 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1489
219fb0c1 1490 if (!port->dev->of_node)
e1910fcd 1491 return;
73a19e4c 1492
e1910fcd 1493 s->cookie_tx = -EINVAL;
219fb0c1 1494 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
e1910fcd
GU		 1495 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1496 if (chan) {
1497 s->chan_tx = chan;
1498 /* UART circular tx buffer is an aligned page. */
1499 s->tx_dma_addr = dma_map_single(chan->device->dev,
1500 port->state->xmit.buf,
1501 UART_XMIT_SIZE,
1502 DMA_TO_DEVICE);
1503 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1504 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1505 dma_release_channel(chan);
1506 s->chan_tx = NULL;
1507 } else {
1508 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1509 __func__, UART_XMIT_SIZE,
1510 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1511 }
e1910fcd
GU		 1512
1513 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1514 }
1515
219fb0c1 1516 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
e1910fcd
GU		 1517 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1518 if (chan) {
1519 unsigned int i;
1520 dma_addr_t dma;
1521 void *buf;
73a19e4c 1522
e1910fcd 1523 s->chan_rx = chan;
73a19e4c 1524
e1910fcd
GU		 1525 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1526 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1527 &dma, GFP_KERNEL);
1528 if (!buf) {
1529 dev_warn(port->dev,
1530 "Failed to allocate Rx dma buffer, using PIO\n");
1531 dma_release_channel(chan);
1532 s->chan_rx = NULL;
e1910fcd
GU		 1533 return;
1534 }
73a19e4c 1535
e1910fcd
GU		 1536 for (i = 0; i < 2; i++) {
1537 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1538
e1910fcd
GU		 1539 sg_init_table(sg, 1);
1540 s->rx_buf[i] = buf;
1541 sg_dma_address(sg) = dma;
d09959e7 1542 sg_dma_len(sg) = s->buf_len_rx;
0533502d 1543
e1910fcd
GU		 1544 buf += s->buf_len_rx;
1545 dma += s->buf_len_rx;
1546 }
1547
e1910fcd
GU		 1548 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1549
756981be
GU		 1550 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1551 sci_submit_rx(s);
e1910fcd 1552 }
0533502d
GU		 1553}
1554
e1910fcd 1555static void sci_free_dma(struct uart_port *port)
73a19e4c 1556{
e1910fcd 1557 struct sci_port *s = to_sci_port(port);
73a19e4c 1558
e1910fcd
GU		 1559 if (s->chan_tx)
1560 sci_tx_dma_release(s, false);
1561 if (s->chan_rx)
1562 sci_rx_dma_release(s, false);
1563}
1cf4a7ef
GU		 1564
1565static void sci_flush_buffer(struct uart_port *port)
1566{
1567 /*
1568 * In uart_flush_buffer(), the xmit circular buffer has just been
1569 * cleared, so we have to reset tx_dma_len accordingly.
1570 */
1571 to_sci_port(port)->tx_dma_len = 0;
1572}
1573#else /* !CONFIG_SERIAL_SH_SCI_DMA */
e1910fcd
GU		 1574static inline void sci_request_dma(struct uart_port *port)
1575{
1576}
73a19e4c 1577
e1910fcd
GU		 1578static inline void sci_free_dma(struct uart_port *port)
1579{
1580}
1cf4a7ef
GU		 1581
1582#define sci_flush_buffer NULL
1583#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
73a19e4c 1584
e1910fcd
GU		 1585static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1586{
e1910fcd
GU		 1587 struct uart_port *port = ptr;
1588 struct sci_port *s = to_sci_port(port);
73a19e4c 1589
03940376 1590#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1591 if (s->chan_rx) {
1592 u16 scr = serial_port_in(port, SCSCR);
1593 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1594
e1910fcd
GU		 1595 /* Disable future Rx interrupts */
1596 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1597 disable_irq_nosync(irq);
1598 scr |= SCSCR_RDRQE;
1599 } else {
1600 scr &= ~SCSCR_RIE;
756981be 1601 sci_submit_rx(s);
e1910fcd
GU		 1602 }
1603 serial_port_out(port, SCSCR, scr);
1604 /* Clear current interrupt */
1605 serial_port_out(port, SCxSR,
1606 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1607 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1608 jiffies, s->rx_timeout);
1609 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1610
e1910fcd
GU		 1611 return IRQ_HANDLED;
1612 }
1613#endif
73a19e4c 1614
03940376
UH		 1615 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1616 if (!scif_rtrg_enabled(port))
1617 scif_set_rtrg(port, s->rx_trigger);
1618
1619 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1620 s->rx_frame * s->rx_fifo_timeout, 1000));
1621 }
1622
e1910fcd
GU		 1623 /* I think sci_receive_chars has to be called irrespective
1624 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1625 * to be disabled?
1626 */
1627 sci_receive_chars(ptr);
1628
1629 return IRQ_HANDLED;
73a19e4c
GL		 1630}
1631
e1910fcd 1632static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1633{
e1910fcd 1634 struct uart_port *port = ptr;
04928b79 1635 unsigned long flags;
73a19e4c 1636
04928b79 1637 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1638 sci_transmit_chars(port);
04928b79 1639 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1640
1641 return IRQ_HANDLED;
73a19e4c
GL		 1642}
1643
e1910fcd 1644static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1645{
e1910fcd
GU		 1646 struct uart_port *port = ptr;
1647 struct sci_port *s = to_sci_port(port);
73a19e4c 1648
e1910fcd
GU		 1649 /* Handle errors */
1650 if (port->type == PORT_SCI) {
1651 if (sci_handle_errors(port)) {
1652 /* discard character in rx buffer */
1653 serial_port_in(port, SCxSR);
1654 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1655 }
1656 } else {
1657 sci_handle_fifo_overrun(port);
1658 if (!s->chan_rx)
1659 sci_receive_chars(ptr);
1660 }
1661
1662 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1663
1664 /* Kick the transmission */
1665 if (!s->chan_tx)
1666 sci_tx_interrupt(irq, ptr);
1667
1668 return IRQ_HANDLED;
73a19e4c
GL		 1669}
1670
e1910fcd 1671static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1672{
e1910fcd 1673 struct uart_port *port = ptr;
73a19e4c 1674
e1910fcd
GU		 1675 /* Handle BREAKs */
1676 sci_handle_breaks(port);
1677 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1678
e1910fcd
GU		 1679 return IRQ_HANDLED;
1680}
73a19e4c 1681
e1910fcd
GU		 1682static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1683{
1684 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1685 struct uart_port *port = ptr;
1686 struct sci_port *s = to_sci_port(port);
1687 irqreturn_t ret = IRQ_NONE;
73a19e4c 1688
e1910fcd
GU		 1689 ssr_status = serial_port_in(port, SCxSR);
1690 scr_status = serial_port_in(port, SCSCR);
b2f20ed9 1691 if (s->params->overrun_reg == SCxSR)
e1910fcd 1692 orer_status = ssr_status;
b2f20ed9
LP		 1693 else if (sci_getreg(port, s->params->overrun_reg)->size)
1694 orer_status = serial_port_in(port, s->params->overrun_reg);
73a19e4c 1695
e1910fcd 1696 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1697
e1910fcd
GU		 1698 /* Tx Interrupt */
1699 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1700 !s->chan_tx)
1701 ret = sci_tx_interrupt(irq, ptr);
658daa95 1702
e1910fcd
GU		 1703 /*
1704 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1705 * DR flags
1706 */
1707 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1708 (scr_status & SCSCR_RIE))
1709 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1710
e1910fcd
GU		 1711 /* Error Interrupt */
1712 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1713 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1714
e1910fcd
GU		 1715 /* Break Interrupt */
1716 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1717 ret = sci_br_interrupt(irq, ptr);
1718
1719 /* Overrun Interrupt */
b2f20ed9 1720 if (orer_status & s->params->overrun_mask) {
e1910fcd
GU		 1721 sci_handle_fifo_overrun(port);
1722 ret = IRQ_HANDLED;
73a19e4c 1723 }
73a19e4c 1724
e1910fcd
GU		 1725 return ret;
1726}
73a19e4c 1727
e1910fcd
GU		 1728static const struct sci_irq_desc {
1729 const char *desc;
1730 irq_handler_t handler;
1731} sci_irq_desc[] = {
1732 /*
1733 * Split out handlers, the default case.
1734 */
1735 [SCIx_ERI_IRQ] = {
1736 .desc = "rx err",
1737 .handler = sci_er_interrupt,
1738 },
3089f381 1739
e1910fcd
GU		 1740 [SCIx_RXI_IRQ] = {
1741 .desc = "rx full",
1742 .handler = sci_rx_interrupt,
1743 },
47aceb92 1744
e1910fcd
GU		 1745 [SCIx_TXI_IRQ] = {
1746 .desc = "tx empty",
1747 .handler = sci_tx_interrupt,
1748 },
73a19e4c 1749
e1910fcd
GU		 1750 [SCIx_BRI_IRQ] = {
1751 .desc = "break",
1752 .handler = sci_br_interrupt,
1753 },
73a19e4c
GL		 1754
1755 /*
e1910fcd 1756 * Special muxed handler.
73a19e4c 1757 */
e1910fcd
GU		 1758 [SCIx_MUX_IRQ] = {
1759 .desc = "mux",
1760 .handler = sci_mpxed_interrupt,
1761 },
1762};
73a19e4c 1763
e1910fcd
GU		 1764static int sci_request_irq(struct sci_port *port)
1765{
1766 struct uart_port *up = &port->port;
1767 int i, j, ret = 0;
73a19e4c 1768
e1910fcd
GU		 1769 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1770 const struct sci_irq_desc *desc;
1771 int irq;
73a19e4c 1772
e1910fcd
GU		 1773 if (SCIx_IRQ_IS_MUXED(port)) {
1774 i = SCIx_MUX_IRQ;
1775 irq = up->irq;
1776 } else {
1777 irq = port->irqs[i];
1778
1779 /*
1780 * Certain port types won't support all of the
1781 * available interrupt sources.
1782 */
1783 if (unlikely(irq < 0))
1784 continue;
1785 }
1786
1787 desc = sci_irq_desc + i;
1788 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1789 dev_name(up->dev), desc->desc);
623ac1d4
PB		 1790 if (!port->irqstr[j]) {
1791 ret = -ENOMEM;
e1910fcd 1792 goto out_nomem;
623ac1d4 1793 }
e1910fcd
GU		 1794
1795 ret = request_irq(irq, desc->handler, up->irqflags,
1796 port->irqstr[j], port);
1797 if (unlikely(ret)) {
1798 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1799 goto out_noirq;
1800 }
73a19e4c
GL		 1801 }
1802
e1910fcd 1803 return 0;
1da177e4 1804
e1910fcd
GU		 1805out_noirq:
1806 while (--i >= 0)
1807 free_irq(port->irqs[i], port);
f43dc23d 1808
e1910fcd
GU		 1809out_nomem:
1810 while (--j >= 0)
1811 kfree(port->irqstr[j]);
f43dc23d 1812
e1910fcd 1813 return ret;
1da177e4
LT		 1814}
1815
e1910fcd 1816static void sci_free_irq(struct sci_port *port)
1da177e4 1817{
e1910fcd 1818 int i;
1da177e4 1819
e1910fcd
GU		 1820 /*
1821 * Intentionally in reverse order so we iterate over the muxed
1822 * IRQ first.
1823 */
1824 for (i = 0; i < SCIx_NR_IRQS; i++) {
1825 int irq = port->irqs[i];
f43dc23d 1826
e1910fcd
GU		 1827 /*
1828 * Certain port types won't support all of the available
1829 * interrupt sources.
1830 */
1831 if (unlikely(irq < 0))
1832 continue;
f43dc23d 1833
e1910fcd
GU		 1834 free_irq(port->irqs[i], port);
1835 kfree(port->irqstr[i]);
f43dc23d 1836
e1910fcd
GU		 1837 if (SCIx_IRQ_IS_MUXED(port)) {
1838 /* If there's only one IRQ, we're done. */
1839 return;
1840 }
1841 }
1da177e4
LT		 1842}
1843
e1910fcd 1844static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1845{
e1910fcd
GU		 1846 unsigned short status = serial_port_in(port, SCxSR);
1847 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1848
e1910fcd 1849 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1850}
1851
33f50ffc
GU		 1852static void sci_set_rts(struct uart_port *port, bool state)
1853{
1854 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1855 u16 data = serial_port_in(port, SCPDR);
1856
1857 /* Active low */
1858 if (state)
1859 data &= ~SCPDR_RTSD;
1860 else
1861 data |= SCPDR_RTSD;
1862 serial_port_out(port, SCPDR, data);
1863
1864 /* RTS# is output */
1865 serial_port_out(port, SCPCR,
1866 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1867 } else if (sci_getreg(port, SCSPTR)->size) {
1868 u16 ctrl = serial_port_in(port, SCSPTR);
1869
1870 /* Active low */
1871 if (state)
1872 ctrl &= ~SCSPTR_RTSDT;
1873 else
1874 ctrl |= SCSPTR_RTSDT;
1875 serial_port_out(port, SCSPTR, ctrl);
1876 }
1877}
1878
1879static bool sci_get_cts(struct uart_port *port)
1880{
1881 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1882 /* Active low */
1883 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1884 } else if (sci_getreg(port, SCSPTR)->size) {
1885 /* Active low */
1886 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1887 }
1888
1889 return true;
1890}
1891
e1910fcd
GU		 1892/*
1893 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1894 * CTS/RTS is supported in hardware by at least one port and controlled
1895 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1896 * handled via the ->init_pins() op, which is a bit of a one-way street,
1897 * lacking any ability to defer pin control -- this will later be
1898 * converted over to the GPIO framework).
1899 *
1900 * Other modes (such as loopback) are supported generically on certain
1901 * port types, but not others. For these it's sufficient to test for the
1902 * existence of the support register and simply ignore the port type.
1903 */
1904static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1905{
f907c9ea
GU		 1906 struct sci_port *s = to_sci_port(port);
1907
e1910fcd
GU		 1908 if (mctrl & TIOCM_LOOP) {
1909 const struct plat_sci_reg *reg;
f43dc23d 1910
e1910fcd
GU		 1911 /*
1912 * Standard loopback mode for SCFCR ports.
1913 */
1914 reg = sci_getreg(port, SCFCR);
1915 if (reg->size)
1916 serial_port_out(port, SCFCR,
1917 serial_port_in(port, SCFCR) |
1918 SCFCR_LOOP);
1919 }
f907c9ea
GU		 1920
1921 mctrl_gpio_set(s->gpios, mctrl);
33f50ffc 1922
97ed9790 1923 if (!s->has_rtscts)
33f50ffc
GU		 1924 return;
1925
1926 if (!(mctrl & TIOCM_RTS)) {
1927 /* Disable Auto RTS */
1928 serial_port_out(port, SCFCR,
1929 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1930
1931 /* Clear RTS */
1932 sci_set_rts(port, 0);
1933 } else if (s->autorts) {
1934 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1935 /* Enable RTS# pin function */
1936 serial_port_out(port, SCPCR,
1937 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1938 }
1939
1940 /* Enable Auto RTS */
1941 serial_port_out(port, SCFCR,
1942 serial_port_in(port, SCFCR) | SCFCR_MCE);
1943 } else {
1944 /* Set RTS */
1945 sci_set_rts(port, 1);
1946 }
e1910fcd 1947}
f43dc23d 1948
e1910fcd
GU		 1949static unsigned int sci_get_mctrl(struct uart_port *port)
1950{
f907c9ea
GU		 1951 struct sci_port *s = to_sci_port(port);
1952 struct mctrl_gpios *gpios = s->gpios;
1953 unsigned int mctrl = 0;
1954
1955 mctrl_gpio_get(gpios, &mctrl);
1956
e1910fcd
GU		 1957 /*
1958 * CTS/RTS is handled in hardware when supported, while nothing
33f50ffc 1959 * else is wired up.
e1910fcd 1960 */
33f50ffc
GU		 1961 if (s->autorts) {
1962 if (sci_get_cts(port))
1963 mctrl |= TIOCM_CTS;
1964 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
f907c9ea 1965 mctrl |= TIOCM_CTS;
33f50ffc 1966 }
f907c9ea
GU		 1967 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1968 mctrl |= TIOCM_DSR;
1969 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1970 mctrl |= TIOCM_CAR;
1971
1972 return mctrl;
1973}
1974
1975static void sci_enable_ms(struct uart_port *port)
1976{
1977 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1da177e4
LT		 1978}
1979
1da177e4
LT		 1980static void sci_break_ctl(struct uart_port *port, int break_state)
1981{
bbb4ce50
SY		 1982 unsigned short scscr, scsptr;
1983
a4e02f6d 1984 /* check wheter the port has SCSPTR */
abbf121f 1985 if (!sci_getreg(port, SCSPTR)->size) {
bbb4ce50
SY		 1986 /*
1987 * Not supported by hardware. Most parts couple break and rx
1988 * interrupts together, with break detection always enabled.
1989 */
a4e02f6d 1990 return;
bbb4ce50 1991 }
a4e02f6d
SY		 1992
1993 scsptr = serial_port_in(port, SCSPTR);
1994 scscr = serial_port_in(port, SCSCR);
1995
1996 if (break_state == -1) {
1997 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1998 scscr &= ~SCSCR_TE;
1999 } else {
2000 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2001 scscr |= SCSCR_TE;
2002 }
2003
2004 serial_port_out(port, SCSPTR, scsptr);
2005 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 2006}
2007
2008static int sci_startup(struct uart_port *port)
2009{
a5660ada 2010 struct sci_port *s = to_sci_port(port);
073e84c9 2011 int ret;
1da177e4 2012
73a19e4c
GL		 2013 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2014
3c910176
TA		 2015 sci_request_dma(port);
2016
073e84c9 2017 ret = sci_request_irq(s);
3c910176
TA		 2018 if (unlikely(ret < 0)) {
2019 sci_free_dma(port);
073e84c9 2020 return ret;
3c910176 2021 }
073e84c9 2022
1da177e4
LT		 2023 return 0;
2024}
2025
2026static void sci_shutdown(struct uart_port *port)
2027{
a5660ada 2028 struct sci_port *s = to_sci_port(port);
33b48e16 2029 unsigned long flags;
5fd2b6ee 2030 u16 scr;
1da177e4 2031
73a19e4c
GL		 2032 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2033
33f50ffc 2034 s->autorts = false;
f907c9ea
GU		 2035 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2036
33b48e16 2037 spin_lock_irqsave(&port->lock, flags);
1da177e4 2038 sci_stop_rx(port);
b129a8cc 2039 sci_stop_tx(port);
5fd2b6ee
GU		 2040 /* Stop RX and TX, disable related interrupts, keep clock source */
2041 scr = serial_port_in(port, SCSCR);
2042 serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0));
33b48e16 2043 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 2044
9ab76556
AM		 2045#ifdef CONFIG_SERIAL_SH_SCI_DMA
2046 if (s->chan_rx) {
2047 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2048 port->line);
2049 del_timer_sync(&s->rx_timer);
2050 }
2051#endif
2052
1da177e4 2053 sci_free_irq(s);
3c910176 2054 sci_free_dma(port);
1da177e4
LT		 2055}
2056
6af27bf2
GU		 2057static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2058 unsigned int *srr)
26c92f37 2059{
6af27bf2 2060 unsigned long freq = s->clk_rates[SCI_SCK];
6af27bf2 2061 int err, min_err = INT_MAX;
69eee8e9 2062 unsigned int sr;
6af27bf2 2063
7b5c0c08
GU		 2064 if (s->port.type != PORT_HSCIF)
2065 freq *= 2;
6af27bf2 2066
69eee8e9 2067 for_each_sr(sr, s) {
6af27bf2
GU		 2068 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2069 if (abs(err) >= abs(min_err))
2070 continue;
2071
2072 min_err = err;
2073 *srr = sr - 1;
ec09c5eb 2074
6af27bf2
GU		 2075 if (!err)
2076 break;
2077 }
e8183a6c 2078
6af27bf2
GU		 2079 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2080 *srr + 1);
2081 return min_err;
26c92f37
PM		 2082}
2083
1270f865
GU		 2084static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2085 unsigned long freq, unsigned int *dlr,
2086 unsigned int *srr)
730c4e78 2087{
1270f865 2088 int err, min_err = INT_MAX;
69eee8e9 2089 unsigned int sr, dl;
730c4e78 2090
7b5c0c08
GU		 2091 if (s->port.type != PORT_HSCIF)
2092 freq *= 2;
730c4e78 2093
69eee8e9 2094 for_each_sr(sr, s) {
1270f865
GU		 2095 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2096 dl = clamp(dl, 1U, 65535U);
2097
2098 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2099 if (abs(err) >= abs(min_err))
2100 continue;
2101
2102 min_err = err;
2103 *dlr = dl;
2104 *srr = sr - 1;
2105
2106 if (!err)
2107 break;
2108 }
730c4e78 2109
1270f865
GU		 2110 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2111 min_err, *dlr, *srr + 1);
2112 return min_err;
2113}
730c4e78 2114
b4a5c459 2115/* calculate sample rate, BRR, and clock select */
f4998e55
GU		 2116static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2117 unsigned int *brr, unsigned int *srr,
2118 unsigned int *cks)
f303b364 2119{
f4998e55 2120 unsigned long freq = s->clk_rates[SCI_FCK];
69eee8e9 2121 unsigned int sr, br, prediv, scrate, c;
6c51332d 2122 int err, min_err = INT_MAX;
f303b364 2123
7b5c0c08
GU		 2124 if (s->port.type != PORT_HSCIF)
2125 freq *= 2;
b4a5c459 2126
6c51332d
GU		 2127 /*
2128 * Find the combination of sample rate and clock select with the
2129 * smallest deviation from the desired baud rate.
2130 * Prefer high sample rates to maximise the receive margin.
2131 *
2132 * M: Receive margin (%)
2133 * N: Ratio of bit rate to clock (N = sampling rate)
2134 * D: Clock duty (D = 0 to 1.0)
2135 * L: Frame length (L = 9 to 12)
2136 * F: Absolute value of clock frequency deviation
2137 *
2138 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2139 * (|D - 0.5| / N * (1 + F))|
2140 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2141 */
69eee8e9 2142 for_each_sr(sr, s) {
f303b364
UH		 2143 for (c = 0; c <= 3; c++) {
2144 /* integerized formulas from HSCIF documentation */
7b5c0c08 2145 prediv = sr * (1 << (2 * c + 1));
de01e6cd
GU		 2146
2147 /*
2148 * We need to calculate:
2149 *
2150 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 2151 * err = freq / (br * prediv) - bps
730c4e78 2152 *
de01e6cd
GU		 2153 * Watch out for overflow when calculating the desired
2154 * sampling clock rate!
730c4e78 2155 */
de01e6cd
GU		 2156 if (bps > UINT_MAX / prediv)
2157 break;
2158
2159 scrate = prediv * bps;
2160 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 2161 br = clamp(br, 1U, 256U);
6c51332d 2162
881a7489 2163 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 2164 if (abs(err) >= abs(min_err))
730c4e78
NI		 2165 continue;
2166
6c51332d 2167 min_err = err;
95a2703e 2168 *brr = br - 1;
730c4e78
NI		 2169 *srr = sr - 1;
2170 *cks = c;
6c51332d
GU		 2171
2172 if (!err)
2173 goto found;
f303b364
UH		 2174 }
2175 }
2176
6c51332d 2177found:
881a7489
GU		 2178 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2179 min_err, *brr, *srr + 1, *cks);
f4998e55 2180 return min_err;
f303b364
UH		 2181}
2182
1ba76220
MD		 2183static void sci_reset(struct uart_port *port)
2184{
d3184e68 2185 const struct plat_sci_reg *reg;
1ba76220 2186 unsigned int status;
18e8cf15 2187 struct sci_port *s = to_sci_port(port);
1ba76220 2188
b12bb29f 2189 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 2190
0979e0e6
PM		 2191 reg = sci_getreg(port, SCFCR);
2192 if (reg->size)
b12bb29f 2193 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2768cf42
GU		 2194
2195 sci_clear_SCxSR(port,
2196 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2197 SCxSR_BREAK_CLEAR(port));
fc2af334
GU		 2198 if (sci_getreg(port, SCLSR)->size) {
2199 status = serial_port_in(port, SCLSR);
2200 status &= ~(SCLSR_TO | SCLSR_ORER);
2201 serial_port_out(port, SCLSR, status);
2202 }
18e8cf15 2203
03940376
UH		 2204 if (s->rx_trigger > 1) {
2205 if (s->rx_fifo_timeout) {
2206 scif_set_rtrg(port, 1);
2207 setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn,
2208 (unsigned long)s);
2209 } else {
90afa525
UH		 2210 if (port->type == PORT_SCIFA ||
2211 port->type == PORT_SCIFB)
2212 scif_set_rtrg(port, 1);
2213 else
2214 scif_set_rtrg(port, s->rx_trigger);
03940376
UH		 2215 }
2216 }
1ba76220
MD		 2217}
2218
606d099c
AC		 2219static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2220 struct ktermios *old)
1da177e4 2221{
03940376 2222 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
1270f865
GU		 2223 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2224 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
00b9de9c 2225 struct sci_port *s = to_sci_port(port);
d3184e68 2226 const struct plat_sci_reg *reg;
f4998e55
GU		 2227 int min_err = INT_MAX, err;
2228 unsigned long max_freq = 0;
2229 int best_clk = -1;
1da177e4 2230
730c4e78
NI		 2231 if ((termios->c_cflag & CSIZE) == CS7)
2232 smr_val |= SCSMR_CHR;
2233 if (termios->c_cflag & PARENB)
2234 smr_val |= SCSMR_PE;
2235 if (termios->c_cflag & PARODD)
2236 smr_val |= SCSMR_PE | SCSMR_ODD;
2237 if (termios->c_cflag & CSTOPB)
2238 smr_val |= SCSMR_STOP;
2239
154280fd
MD		 2240 /*
2241 * earlyprintk comes here early on with port->uartclk set to zero.
2242 * the clock framework is not up and running at this point so here
2243 * we assume that 115200 is the maximum baud rate. please note that
2244 * the baud rate is not programmed during earlyprintk - it is assumed
2245 * that the previous boot loader has enabled required clocks and
2246 * setup the baud rate generator hardware for us already.
2247 */
f4998e55
GU		 2248 if (!port->uartclk) {
2249 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2250 goto done;
2251 }
1da177e4 2252
f4998e55
GU		 2253 for (i = 0; i < SCI_NUM_CLKS; i++)
2254 max_freq = max(max_freq, s->clk_rates[i]);
2255
69eee8e9 2256 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
f4998e55
GU		 2257 if (!baud)
2258 goto done;
2259
2260 /*
2261 * There can be multiple sources for the sampling clock. Find the one
2262 * that gives us the smallest deviation from the desired baud rate.
2263 */
2264
6af27bf2
GU		 2265 /* Optional Undivided External Clock */
2266 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2267 port->type != PORT_SCIFB) {
2268 err = sci_sck_calc(s, baud, &srr1);
2269 if (abs(err) < abs(min_err)) {
2270 best_clk = SCI_SCK;
2271 scr_val = SCSCR_CKE1;
2272 sccks = SCCKS_CKS;
2273 min_err = err;
2274 srr = srr1;
2275 if (!err)
2276 goto done;
2277 }
2278 }
2279
1270f865
GU		 2280 /* Optional BRG Frequency Divided External Clock */
2281 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2282 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2283 &srr1);
2284 if (abs(err) < abs(min_err)) {
2285 best_clk = SCI_SCIF_CLK;
2286 scr_val = SCSCR_CKE1;
2287 sccks = 0;
2288 min_err = err;
2289 dl = dl1;
2290 srr = srr1;
2291 if (!err)
2292 goto done;
2293 }
2294 }
2295
2296 /* Optional BRG Frequency Divided Internal Clock */
2297 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2298 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2299 &srr1);
2300 if (abs(err) < abs(min_err)) {
2301 best_clk = SCI_BRG_INT;
2302 scr_val = SCSCR_CKE1;
2303 sccks = SCCKS_XIN;
2304 min_err = err;
2305 dl = dl1;
2306 srr = srr1;
2307 if (!min_err)
2308 goto done;
f303b364
UH		 2309 }
2310 }
e108b2ca 2311
f4998e55
GU		 2312 /* Divided Functional Clock using standard Bit Rate Register */
2313 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2314 if (abs(err) < abs(min_err)) {
2315 best_clk = SCI_FCK;
6af27bf2 2316 scr_val = 0;
f4998e55
GU		 2317 min_err = err;
2318 brr = brr1;
2319 srr = srr1;
2320 cks = cks1;
2321 }
2322
2323done:
2324 if (best_clk >= 0)
2325 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2326 s->clks[best_clk], baud, min_err);
e108b2ca 2327
23241d43 2328 sci_port_enable(s);
36003386 2329
6af27bf2
GU		 2330 /*
2331 * Program the optional External Baud Rate Generator (BRG) first.
2332 * It controls the mux to select (H)SCK or frequency divided clock.
2333 */
1270f865
GU		 2334 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2335 serial_port_out(port, SCDL, dl);
6af27bf2 2336 serial_port_out(port, SCCKS, sccks);
1270f865 2337 }
1da177e4 2338
1ba76220 2339 sci_reset(port);
1da177e4
LT		 2340
2341 uart_update_timeout(port, termios->c_cflag, baud);
2342
f4998e55 2343 if (best_clk >= 0) {
92a05748
GU		 2344 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2345 switch (srr + 1) {
2346 case 5: smr_val |= SCSMR_SRC_5; break;
2347 case 7: smr_val |= SCSMR_SRC_7; break;
2348 case 11: smr_val |= SCSMR_SRC_11; break;
2349 case 13: smr_val |= SCSMR_SRC_13; break;
2350 case 16: smr_val |= SCSMR_SRC_16; break;
2351 case 17: smr_val |= SCSMR_SRC_17; break;
2352 case 19: smr_val |= SCSMR_SRC_19; break;
2353 case 27: smr_val |= SCSMR_SRC_27; break;
2354 }
f4998e55 2355 smr_val |= cks;
6af27bf2 2356 dev_dbg(port->dev,
1270f865
GU		 2357 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2358 scr_val, smr_val, brr, sccks, dl, srr);
6af27bf2 2359 serial_port_out(port, SCSCR, scr_val);
f4998e55
GU		 2360 serial_port_out(port, SCSMR, smr_val);
2361 serial_port_out(port, SCBRR, brr);
2362 if (sci_getreg(port, HSSRR)->size)
f303b364 2363 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
f4998e55
GU		 2364
2365 /* Wait one bit interval */
2366 udelay((1000000 + (baud - 1)) / baud);
2367 } else {
2368 /* Don't touch the bit rate configuration */
2369 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
3a964abe
GU		 2370 smr_val |= serial_port_in(port, SCSMR) &
2371 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
f4998e55
GU		 2372 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2373 serial_port_out(port, SCSCR, scr_val);
9d482cc3 2374 serial_port_out(port, SCSMR, smr_val);
f4998e55 2375 }
1da177e4 2376
d5701647 2377 sci_init_pins(port, termios->c_cflag);
0979e0e6 2378
33f50ffc
GU		 2379 port->status &= ~UPSTAT_AUTOCTS;
2380 s->autorts = false;
73c3d53f
PM		 2381 reg = sci_getreg(port, SCFCR);
2382 if (reg->size) {
b12bb29f 2383 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2384
33f50ffc
GU		 2385 if ((port->flags & UPF_HARD_FLOW) &&
2386 (termios->c_cflag & CRTSCTS)) {
2387 /* There is no CTS interrupt to restart the hardware */
2388 port->status |= UPSTAT_AUTOCTS;
2389 /* MCE is enabled when RTS is raised */
2390 s->autorts = true;
faf02f8f 2391 }
73c3d53f
PM		 2392
2393 /*
2394 * As we've done a sci_reset() above, ensure we don't
2395 * interfere with the FIFOs while toggling MCE. As the
2396 * reset values could still be set, simply mask them out.
2397 */
2398 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2399
b12bb29f 2400 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2401 }
5f76895e
GU		 2402 if (port->flags & UPF_HARD_FLOW) {
2403 /* Refresh (Auto) RTS */
2404 sci_set_mctrl(port, port->mctrl);
2405 }
b7a76e4b 2406
9f8325b3
LP		 2407 scr_val |= SCSCR_RE | SCSCR_TE |
2408 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
f4998e55
GU		 2409 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2410 serial_port_out(port, SCSCR, scr_val);
92a05748
GU		 2411 if ((srr + 1 == 5) &&
2412 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2413 /*
2414 * In asynchronous mode, when the sampling rate is 1/5, first
2415 * received data may become invalid on some SCIFA and SCIFB.
2416 * To avoid this problem wait more than 1 serial data time (1
2417 * bit time x serial data number) after setting SCSCR.RE = 1.
2418 */
2419 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2420 }
1da177e4 2421
3089f381 2422 /*
5f6d8515 2423 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2424 * See serial_core.c::uart_update_timeout().
2425 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2426 * function calculates 1 jiffie for the data plus 5 jiffies for the
2427 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2428 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2429 * value obtained by this formula is too small. Therefore, if the value
2430 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381 2431 */
03940376
UH		 2432 /* byte size and parity */
2433 switch (termios->c_cflag & CSIZE) {
2434 case CS5:
2435 bits = 7;
2436 break;
2437 case CS6:
2438 bits = 8;
2439 break;
2440 case CS7:
2441 bits = 9;
2442 break;
2443 default:
2444 bits = 10;
2445 break;
2446 }
5f6d8515 2447
03940376
UH		 2448 if (termios->c_cflag & CSTOPB)
2449 bits++;
2450 if (termios->c_cflag & PARENB)
2451 bits++;
5f6d8515 2452
03940376
UH		 2453 s->rx_frame = (100 * bits * HZ) / (baud / 10);
2454#ifdef CONFIG_SERIAL_SH_SCI_DMA
2455 s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000);
2456 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2457 s->rx_timeout * 1000 / HZ, port->timeout);
2458 if (s->rx_timeout < msecs_to_jiffies(20))
2459 s->rx_timeout = msecs_to_jiffies(20);
3089f381
GL		 2460#endif
2461
1da177e4 2462 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2463 sci_start_rx(port);
36003386 2464
23241d43 2465 sci_port_disable(s);
f907c9ea
GU		 2466
2467 if (UART_ENABLE_MS(port, termios->c_cflag))
2468 sci_enable_ms(port);
1da177e4
LT		 2469}
2470
0174e5ca
TK		 2471static void sci_pm(struct uart_port *port, unsigned int state,
2472 unsigned int oldstate)
2473{
2474 struct sci_port *sci_port = to_sci_port(port);
2475
2476 switch (state) {
d3dfe5d9 2477 case UART_PM_STATE_OFF:
0174e5ca
TK		 2478 sci_port_disable(sci_port);
2479 break;
2480 default:
2481 sci_port_enable(sci_port);
2482 break;
2483 }
2484}
2485
1da177e4
LT		 2486static const char *sci_type(struct uart_port *port)
2487{
2488 switch (port->type) {
e7c98dc7
MT		 2489 case PORT_IRDA:
2490 return "irda";
2491 case PORT_SCI:
2492 return "sci";
2493 case PORT_SCIF:
2494 return "scif";
2495 case PORT_SCIFA:
2496 return "scifa";
d1d4b10c
GL		 2497 case PORT_SCIFB:
2498 return "scifb";
f303b364
UH		 2499 case PORT_HSCIF:
2500 return "hscif";
1da177e4
LT		 2501 }
2502
fa43972f 2503 return NULL;
1da177e4
LT		 2504}
2505
f6e9495d
PM		 2506static int sci_remap_port(struct uart_port *port)
2507{
e4d6f911 2508 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2509
2510 /*
2511 * Nothing to do if there's already an established membase.
2512 */
2513 if (port->membase)
2514 return 0;
2515
3d73f32b 2516 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e4d6f911 2517 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2518 if (unlikely(!port->membase)) {
2519 dev_err(port->dev, "can't remap port#%d\n", port->line);
2520 return -ENXIO;
2521 }
2522 } else {
2523 /*
2524 * For the simple (and majority of) cases where we don't
2525 * need to do any remapping, just cast the cookie
2526 * directly.
2527 */
3af4e960 2528 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2529 }
2530
2531 return 0;
2532}
2533
e2651647 2534static void sci_release_port(struct uart_port *port)
1da177e4 2535{
e4d6f911
YS		 2536 struct sci_port *sport = to_sci_port(port);
2537
3d73f32b 2538 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e2651647
PM		 2539 iounmap(port->membase);
2540 port->membase = NULL;
2541 }
2542
e4d6f911 2543 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2544}
2545
e2651647 2546static int sci_request_port(struct uart_port *port)
1da177e4 2547{
e2651647 2548 struct resource *res;
e4d6f911 2549 struct sci_port *sport = to_sci_port(port);
f6e9495d 2550 int ret;
1da177e4 2551
e4d6f911
YS		 2552 res = request_mem_region(port->mapbase, sport->reg_size,
2553 dev_name(port->dev));
2554 if (unlikely(res == NULL)) {
2555 dev_err(port->dev, "request_mem_region failed.");
e2651647 2556 return -EBUSY;
e4d6f911 2557 }
1da177e4 2558
f6e9495d
PM		 2559 ret = sci_remap_port(port);
2560 if (unlikely(ret != 0)) {
2561 release_resource(res);
2562 return ret;
7ff731ae 2563 }
e2651647
PM		 2564
2565 return 0;
2566}
2567
2568static void sci_config_port(struct uart_port *port, int flags)
2569{
2570 if (flags & UART_CONFIG_TYPE) {
2571 struct sci_port *sport = to_sci_port(port);
2572
2573 port->type = sport->cfg->type;
2574 sci_request_port(port);
2575 }
1da177e4
LT		 2576}
2577
2578static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2579{
1da177e4
LT		 2580 if (ser->baud_base < 2400)
2581 /* No paper tape reader for Mitch.. */
2582 return -EINVAL;
2583
2584 return 0;
2585}
2586
069a47e5 2587static const struct uart_ops sci_uart_ops = {
1da177e4
LT		 2588 .tx_empty = sci_tx_empty,
2589 .set_mctrl = sci_set_mctrl,
2590 .get_mctrl = sci_get_mctrl,
2591 .start_tx = sci_start_tx,
2592 .stop_tx = sci_stop_tx,
2593 .stop_rx = sci_stop_rx,
f907c9ea 2594 .enable_ms = sci_enable_ms,
1da177e4
LT		 2595 .break_ctl = sci_break_ctl,
2596 .startup = sci_startup,
2597 .shutdown = sci_shutdown,
1cf4a7ef 2598 .flush_buffer = sci_flush_buffer,
1da177e4 2599 .set_termios = sci_set_termios,
0174e5ca 2600 .pm = sci_pm,
1da177e4
LT		 2601 .type = sci_type,
2602 .release_port = sci_release_port,
2603 .request_port = sci_request_port,
2604 .config_port = sci_config_port,
2605 .verify_port = sci_verify_port,
07d2a1a1
PM		 2606#ifdef CONFIG_CONSOLE_POLL
2607 .poll_get_char = sci_poll_get_char,
2608 .poll_put_char = sci_poll_put_char,
2609#endif
1da177e4
LT		 2610};
2611
a9ec81f4
LP		 2612static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2613{
f4998e55
GU		 2614 const char *clk_names[] = {
2615 [SCI_FCK] = "fck",
6af27bf2 2616 [SCI_SCK] = "sck",
1270f865
GU		 2617 [SCI_BRG_INT] = "brg_int",
2618 [SCI_SCIF_CLK] = "scif_clk",
f4998e55
GU		 2619 };
2620 struct clk *clk;
2621 unsigned int i;
a9ec81f4 2622
6af27bf2
GU		 2623 if (sci_port->cfg->type == PORT_HSCIF)
2624 clk_names[SCI_SCK] = "hsck";
2625
f4998e55
GU		 2626 for (i = 0; i < SCI_NUM_CLKS; i++) {
2627 clk = devm_clk_get(dev, clk_names[i]);
2628 if (PTR_ERR(clk) == -EPROBE_DEFER)
2629 return -EPROBE_DEFER;
a9ec81f4 2630
f4998e55
GU		 2631 if (IS_ERR(clk) && i == SCI_FCK) {
2632 /*
2633 * "fck" used to be called "sci_ick", and we need to
2634 * maintain DT backward compatibility.
2635 */
2636 clk = devm_clk_get(dev, "sci_ick");
2637 if (PTR_ERR(clk) == -EPROBE_DEFER)
2638 return -EPROBE_DEFER;
a9ec81f4 2639
f4998e55
GU		 2640 if (!IS_ERR(clk))
2641 goto found;
a9ec81f4 2642
f4998e55
GU		 2643 /*
2644 * Not all SH platforms declare a clock lookup entry
2645 * for SCI devices, in which case we need to get the
2646 * global "peripheral_clk" clock.
2647 */
2648 clk = devm_clk_get(dev, "peripheral_clk");
2649 if (!IS_ERR(clk))
2650 goto found;
2651
2652 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2653 PTR_ERR(clk));
2654 return PTR_ERR(clk);
2655 }
2656
2657found:
2658 if (IS_ERR(clk))
2659 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2660 PTR_ERR(clk));
2661 else
2662 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2663 clk, clk);
2664 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2665 }
2666 return 0;
a9ec81f4
LP		 2667}
2668
daf5a895
LP		 2669static const struct sci_port_params *
2670sci_probe_regmap(const struct plat_sci_port *cfg)
2671{
2672 unsigned int regtype;
2673
2674 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2675 return &sci_port_params[cfg->regtype];
2676
2677 switch (cfg->type) {
2678 case PORT_SCI:
2679 regtype = SCIx_SCI_REGTYPE;
2680 break;
2681 case PORT_IRDA:
2682 regtype = SCIx_IRDA_REGTYPE;
2683 break;
2684 case PORT_SCIFA:
2685 regtype = SCIx_SCIFA_REGTYPE;
2686 break;
2687 case PORT_SCIFB:
2688 regtype = SCIx_SCIFB_REGTYPE;
2689 break;
2690 case PORT_SCIF:
2691 /*
2692 * The SH-4 is a bit of a misnomer here, although that's
2693 * where this particular port layout originated. This
2694 * configuration (or some slight variation thereof)
2695 * remains the dominant model for all SCIFs.
2696 */
2697 regtype = SCIx_SH4_SCIF_REGTYPE;
2698 break;
2699 case PORT_HSCIF:
2700 regtype = SCIx_HSCIF_REGTYPE;
2701 break;
2702 default:
2703 pr_err("Can't probe register map for given port\n");
2704 return NULL;
2705 }
2706
2707 return &sci_port_params[regtype];
2708}
2709
9671f099 2710static int sci_init_single(struct platform_device *dev,
1fcc91a6 2711 struct sci_port *sci_port, unsigned int index,
daf5a895 2712 const struct plat_sci_port *p, bool early)
e108b2ca 2713{
73a19e4c 2714 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2715 const struct resource *res;
2716 unsigned int i;
3127c6b2 2717 int ret;
e108b2ca 2718
50f0959a
PM		 2719 sci_port->cfg = p;
2720
73a19e4c
GL		 2721 port->ops = &sci_uart_ops;
2722 port->iotype = UPIO_MEM;
2723 port->line = index;
75136d48 2724
89b5c1ab
LP		 2725 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2726 if (res == NULL)
2727 return -ENOMEM;
1fcc91a6 2728
89b5c1ab 2729 port->mapbase = res->start;
e4d6f911 2730 sci_port->reg_size = resource_size(res);
1fcc91a6 2731
89b5c1ab
LP		 2732 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2733 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2734
89b5c1ab
LP		 2735 /* The SCI generates several interrupts. They can be muxed together or
2736 * connected to different interrupt lines. In the muxed case only one
2737 * interrupt resource is specified. In the non-muxed case three or four
2738 * interrupt resources are specified, as the BRI interrupt is optional.
2739 */
2740 if (sci_port->irqs[0] < 0)
2741 return -ENXIO;
1fcc91a6 2742
89b5c1ab
LP		 2743 if (sci_port->irqs[1] < 0) {
2744 sci_port->irqs[1] = sci_port->irqs[0];
2745 sci_port->irqs[2] = sci_port->irqs[0];
2746 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2747 }
2748
daf5a895
LP		 2749 sci_port->params = sci_probe_regmap(p);
2750 if (unlikely(sci_port->params == NULL))
2751 return -EINVAL;
e095ee6b 2752
18e8cf15
UH		 2753 switch (p->type) {
2754 case PORT_SCIFB:
2755 sci_port->rx_trigger = 48;
2756 break;
2757 case PORT_HSCIF:
2758 sci_port->rx_trigger = 64;
2759 break;
2760 case PORT_SCIFA:
2761 sci_port->rx_trigger = 32;
2762 break;
2763 case PORT_SCIF:
2764 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2765 /* RX triggering not implemented for this IP */
2766 sci_port->rx_trigger = 1;
2767 else
2768 sci_port->rx_trigger = 8;
2769 break;
2770 default:
2771 sci_port->rx_trigger = 1;
2772 break;
2773 }
2774
03940376
UH		 2775 sci_port->rx_fifo_timeout = 0;
2776
878fbb91
LP		 2777 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2778 * match the SoC datasheet, this should be investigated. Let platform
2779 * data override the sampling rate for now.
ec09c5eb 2780 */
b2f20ed9
LP		 2781 sci_port->sampling_rate_mask = p->sampling_rate
2782 ? SCI_SR(p->sampling_rate)
2783 : sci_port->params->sampling_rate_mask;
ec09c5eb 2784
1fcc91a6 2785 if (!early) {
a9ec81f4
LP		 2786 ret = sci_init_clocks(sci_port, &dev->dev);
2787 if (ret < 0)
2788 return ret;
c7ed1ab3 2789
73a19e4c 2790 port->dev = &dev->dev;
5e50d2d6
MD		 2791
2792 pm_runtime_enable(&dev->dev);
7b6fd3bf 2793 }
e108b2ca 2794
ce6738b6 2795 port->type = p->type;
3d73f32b 2796 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
b2f20ed9 2797 port->fifosize = sci_port->params->fifosize;
73a19e4c 2798
dfc80387
LP		 2799 if (port->type == PORT_SCI) {
2800 if (sci_port->reg_size >= 0x20)
2801 port->regshift = 2;
2802 else
2803 port->regshift = 1;
2804 }
2805
ce6738b6 2806 /*
61a6976b 2807 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2808 * for the multi-IRQ ports, which is where we are primarily
2809 * concerned with the shutdown path synchronization.
2810 *
2811 * For the muxed case there's nothing more to do.
2812 */
1fcc91a6 2813 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2814 port->irqflags = 0;
73a19e4c 2815
61a6976b
PM		 2816 port->serial_in = sci_serial_in;
2817 port->serial_out = sci_serial_out;
2818
c7ed1ab3 2819 return 0;
e108b2ca
PM		 2820}
2821
6dae1421
LP		 2822static void sci_cleanup_single(struct sci_port *port)
2823{
6dae1421
LP		 2824 pm_runtime_disable(port->port.dev);
2825}
2826
0b0cced1
YS		 2827#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2828 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
dc8e6f5b
MD		 2829static void serial_console_putchar(struct uart_port *port, int ch)
2830{
2831 sci_poll_put_char(port, ch);
2832}
2833
1da177e4
LT		 2834/*
2835 * Print a string to the serial port trying not to disturb
2836 * any possible real use of the port...
2837 */
2838static void serial_console_write(struct console *co, const char *s,
2839 unsigned count)
2840{
906b17dc
PM		 2841 struct sci_port *sci_port = &sci_ports[co->index];
2842 struct uart_port *port = &sci_port->port;
a67969b5 2843 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2844 unsigned long flags;
2845 int locked = 1;
2846
2847 local_irq_save(flags);
0b0cced1 2848#if defined(SUPPORT_SYSRQ)
40f70c03
SK		 2849 if (port->sysrq)
2850 locked = 0;
0b0cced1
YS		 2851 else
2852#endif
2853 if (oops_in_progress)
40f70c03
SK		 2854 locked = spin_trylock(&port->lock);
2855 else
2856 spin_lock(&port->lock);
2857
a67969b5 2858 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2859 ctrl = serial_port_in(port, SCSCR);
9f8325b3
LP		 2860 ctrl_temp = SCSCR_RE | SCSCR_TE |
2861 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
a67969b5
GU		 2862 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2863 serial_port_out(port, SCSCR, ctrl_temp);
07d2a1a1 2864
501b825d 2865 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2866
2867 /* wait until fifo is empty and last bit has been transmitted */
2868 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2869 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2870 cpu_relax();
40f70c03
SK		 2871
2872 /* restore the SCSCR */
2873 serial_port_out(port, SCSCR, ctrl);
2874
2875 if (locked)
2876 spin_unlock(&port->lock);
2877 local_irq_restore(flags);
1da177e4
LT		 2878}
2879
9671f099 2880static int serial_console_setup(struct console *co, char *options)
1da177e4 2881{
dc8e6f5b 2882 struct sci_port *sci_port;
1da177e4
LT		 2883 struct uart_port *port;
2884 int baud = 115200;
2885 int bits = 8;
2886 int parity = 'n';
2887 int flow = 'n';
2888 int ret;
2889
e108b2ca 2890 /*
906b17dc 2891 * Refuse to handle any bogus ports.
1da177e4 2892 */
906b17dc 2893 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2894 return -ENODEV;
e108b2ca 2895
906b17dc
PM		 2896 sci_port = &sci_ports[co->index];
2897 port = &sci_port->port;
2898
b2267a6b
AC		 2899 /*
2900 * Refuse to handle uninitialized ports.
2901 */
2902 if (!port->ops)
2903 return -ENODEV;
2904
f6e9495d
PM		 2905 ret = sci_remap_port(port);
2906 if (unlikely(ret != 0))
2907 return ret;
e108b2ca 2908
1da177e4
LT		 2909 if (options)
2910 uart_parse_options(options, &baud, &parity, &bits, &flow);
2911
ab7cfb55 2912 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2913}
2914
2915static struct console serial_console = {
2916 .name = "ttySC",
906b17dc 2917 .device = uart_console_device,
1da177e4
LT		 2918 .write = serial_console_write,
2919 .setup = serial_console_setup,
fa5da2f7 2920 .flags = CON_PRINTBUFFER,
1da177e4 2921 .index = -1,
906b17dc 2922 .data = &sci_uart_driver,
1da177e4
LT		 2923};
2924
7b6fd3bf
MD		 2925static struct console early_serial_console = {
2926 .name = "early_ttySC",
2927 .write = serial_console_write,
2928 .flags = CON_PRINTBUFFER,
906b17dc 2929 .index = -1,
7b6fd3bf 2930};
ecdf8a46 2931
7b6fd3bf
MD		 2932static char early_serial_buf[32];
2933
9671f099 2934static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2935{
daf5a895 2936 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2937
2938 if (early_serial_console.data)
2939 return -EEXIST;
2940
2941 early_serial_console.index = pdev->id;
ecdf8a46 2942
1fcc91a6 2943 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2944
2945 serial_console_setup(&early_serial_console, early_serial_buf);
2946
2947 if (!strstr(early_serial_buf, "keep"))
2948 early_serial_console.flags |= CON_BOOT;
2949
2950 register_console(&early_serial_console);
2951 return 0;
2952}
6a8c9799
NI		 2953
2954#define SCI_CONSOLE (&serial_console)
2955
ecdf8a46 2956#else
9671f099 2957static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2958{
2959 return -EINVAL;
2960}
1da177e4 2961
6a8c9799
NI		 2962#define SCI_CONSOLE NULL
2963
0b0cced1 2964#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 2965
6c13d5d2 2966static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4 2967
352b9266 2968static DEFINE_MUTEX(sci_uart_registration_lock);
1da177e4
LT		 2969static struct uart_driver sci_uart_driver = {
2970 .owner = THIS_MODULE,
2971 .driver_name = "sci",
1da177e4
LT		 2972 .dev_name = "ttySC",
2973 .major = SCI_MAJOR,
2974 .minor = SCI_MINOR_START,
e108b2ca 2975 .nr = SCI_NPORTS,
1da177e4
LT		 2976 .cons = SCI_CONSOLE,
2977};
2978
54507f6e 2979static int sci_remove(struct platform_device *dev)
e552de24 2980{
d535a230 2981 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2982
d535a230
PM		 2983 uart_remove_one_port(&sci_uart_driver, &port->port);
2984
6dae1421 2985 sci_cleanup_single(port);
e552de24 2986
5d23188a
UH		 2987 if (port->port.fifosize > 1) {
2988 sysfs_remove_file(&dev->dev.kobj,
2989 &dev_attr_rx_fifo_trigger.attr);
2990 }
2991 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB) {
2992 sysfs_remove_file(&dev->dev.kobj,
2993 &dev_attr_rx_fifo_timeout.attr);
2994 }
2995
e552de24
MD		 2996 return 0;
2997}
2998
bd2238fb
GU		 2999
3000#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3001#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3002#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
20bdcab8
BH		 3003
3004static const struct of_device_id of_sci_match[] = {
f443ff80
GU		 3005 /* SoC-specific types */
3006 {
3007 .compatible = "renesas,scif-r7s72100",
3008 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3009 },
9ed44bb2
GU		 3010 /* Family-specific types */
3011 {
3012 .compatible = "renesas,rcar-gen1-scif",
3013 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3014 }, {
3015 .compatible = "renesas,rcar-gen2-scif",
3016 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3017 }, {
3018 .compatible = "renesas,rcar-gen3-scif",
3019 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3020 },
f443ff80 3021 /* Generic types */
20bdcab8
BH		 3022 {
3023 .compatible = "renesas,scif",
bd2238fb 3024 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
20bdcab8
BH		 3025 }, {
3026 .compatible = "renesas,scifa",
bd2238fb 3027 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
20bdcab8
BH		 3028 }, {
3029 .compatible = "renesas,scifb",
bd2238fb 3030 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
20bdcab8
BH		 3031 }, {
3032 .compatible = "renesas,hscif",
bd2238fb 3033 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
e1d0be61
YS		 3034 }, {
3035 .compatible = "renesas,sci",
bd2238fb 3036 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
20bdcab8
BH		 3037 }, {
3038 /* Terminator */
3039 },
3040};
3041MODULE_DEVICE_TABLE(of, of_sci_match);
3042
54b12c48
GU		 3043static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3044 unsigned int *dev_id)
20bdcab8
BH		 3045{
3046 struct device_node *np = pdev->dev.of_node;
3047 const struct of_device_id *match;
20bdcab8 3048 struct plat_sci_port *p;
97ed9790 3049 struct sci_port *sp;
20bdcab8
BH		 3050 int id;
3051
3052 if (!IS_ENABLED(CONFIG_OF) || !np)
3053 return NULL;
3054
495bb47c 3055 match = of_match_node(of_sci_match, np);
20bdcab8
BH		 3056 if (!match)
3057 return NULL;
3058
20bdcab8 3059 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 3060 if (!p)
20bdcab8 3061 return NULL;
20bdcab8 3062
2095fc76 3063 /* Get the line number from the aliases node. */
20bdcab8
BH		 3064 id = of_alias_get_id(np, "serial");
3065 if (id < 0) {
3066 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3067 return NULL;
3068 }
3069
97ed9790 3070 sp = &sci_ports[id];
20bdcab8
BH		 3071 *dev_id = id;
3072
bd2238fb
GU		 3073 p->type = SCI_OF_TYPE(match->data);
3074 p->regtype = SCI_OF_REGTYPE(match->data);
20bdcab8 3075
861a70ab 3076 if (of_find_property(np, "uart-has-rtscts", NULL))
97ed9790 3077 sp->has_rtscts = true;
861a70ab 3078
20bdcab8
BH		 3079 return p;
3080}
3081
9671f099 3082static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 3083 unsigned int index,
3084 struct plat_sci_port *p,
3085 struct sci_port *sciport)
3086{
0ee70712
MD		 3087 int ret;
3088
3089 /* Sanity check */
3090 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 3091 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 3092 index+1, SCI_NPORTS);
9b971cd2 3093 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 3094 return -EINVAL;
0ee70712
MD		 3095 }
3096
352b9266
SS		 3097 mutex_lock(&sci_uart_registration_lock);
3098 if (!sci_uart_driver.state) {
3099 ret = uart_register_driver(&sci_uart_driver);
3100 if (ret) {
3101 mutex_unlock(&sci_uart_registration_lock);
3102 return ret;
3103 }
3104 }
3105 mutex_unlock(&sci_uart_registration_lock);
3106
1fcc91a6 3107 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 3108 if (ret)
3109 return ret;
0ee70712 3110
f907c9ea
GU		 3111 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3112 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3113 return PTR_ERR(sciport->gpios);
3114
97ed9790 3115 if (sciport->has_rtscts) {
f907c9ea
GU		 3116 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3117 UART_GPIO_CTS)) ||
3118 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3119 UART_GPIO_RTS))) {
3120 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3121 return -EINVAL;
3122 }
33f50ffc 3123 sciport->port.flags |= UPF_HARD_FLOW;
f907c9ea
GU		 3124 }
3125
6dae1421
LP		 3126 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3127 if (ret) {
3128 sci_cleanup_single(sciport);
3129 return ret;
3130 }
3131
3132 return 0;
0ee70712
MD		 3133}
3134
9671f099 3135static int sci_probe(struct platform_device *dev)
1da177e4 3136{
20bdcab8
BH		 3137 struct plat_sci_port *p;
3138 struct sci_port *sp;
3139 unsigned int dev_id;
ecdf8a46 3140 int ret;
d535a230 3141
ecdf8a46
PM		 3142 /*
3143 * If we've come here via earlyprintk initialization, head off to
3144 * the special early probe. We don't have sufficient device state
3145 * to make it beyond this yet.
3146 */
3147 if (is_early_platform_device(dev))
3148 return sci_probe_earlyprintk(dev);
7b6fd3bf 3149
20bdcab8
BH		 3150 if (dev->dev.of_node) {
3151 p = sci_parse_dt(dev, &dev_id);
3152 if (p == NULL)
3153 return -EINVAL;
3154 } else {
3155 p = dev->dev.platform_data;
3156 if (p == NULL) {
3157 dev_err(&dev->dev, "no platform data supplied\n");
3158 return -EINVAL;
3159 }
3160
3161 dev_id = dev->id;
3162 }
3163
3164 sp = &sci_ports[dev_id];
d535a230 3165 platform_set_drvdata(dev, sp);
e552de24 3166
20bdcab8 3167 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 3168 if (ret)
6dae1421 3169 return ret;
e552de24 3170
5d23188a
UH		 3171 if (sp->port.fifosize > 1) {
3172 ret = sysfs_create_file(&dev->dev.kobj,
3173 &dev_attr_rx_fifo_trigger.attr);
3174 if (ret)
3175 return ret;
3176 }
3177 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB) {
3178 ret = sysfs_create_file(&dev->dev.kobj,
3179 &dev_attr_rx_fifo_timeout.attr);
3180 if (ret) {
3181 if (sp->port.fifosize > 1) {
3182 sysfs_remove_file(&dev->dev.kobj,
3183 &dev_attr_rx_fifo_trigger.attr);
3184 }
3185 return ret;
3186 }
3187 }
3188
1da177e4
LT		 3189#ifdef CONFIG_SH_STANDARD_BIOS
3190 sh_bios_gdb_detach();
3191#endif
3192
e108b2ca 3193 return 0;
1da177e4
LT		 3194}
3195
cb876341 3196static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 3197{
d535a230 3198 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3199
d535a230
PM		 3200 if (sport)
3201 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 3202
e108b2ca
PM		 3203 return 0;
3204}
1da177e4 3205
cb876341 3206static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 3207{
d535a230 3208 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3209
d535a230
PM		 3210 if (sport)
3211 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 3212
3213 return 0;
3214}
3215
cb876341 3216static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 3217
e108b2ca
PM		 3218static struct platform_driver sci_driver = {
3219 .probe = sci_probe,
b9e39c89 3220 .remove = sci_remove,
e108b2ca
PM		 3221 .driver = {
3222 .name = "sh-sci",
6daa79b3 3223 .pm = &sci_dev_pm_ops,
20bdcab8 3224 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 3225 },
3226};
3227
3228static int __init sci_init(void)
3229{
6c13d5d2 3230 pr_info("%s\n", banner);
e108b2ca 3231
352b9266 3232 return platform_driver_register(&sci_driver);
e108b2ca
PM		 3233}
3234
3235static void __exit sci_exit(void)
3236{
3237 platform_driver_unregister(&sci_driver);
352b9266
SS		 3238
3239 if (sci_uart_driver.state)
3240 uart_unregister_driver(&sci_uart_driver);
1da177e4
LT		 3241}
3242
7b6fd3bf
MD		 3243#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3244early_platform_init_buffer("earlyprintk", &sci_driver,
3245 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3246#endif
0b0cced1
YS		 3247#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3248static struct __init plat_sci_port port_cfg;
3249
3250static int __init early_console_setup(struct earlycon_device *device,
3251 int type)
3252{
3253 if (!device->port.membase)
3254 return -ENODEV;
3255
3256 device->port.serial_in = sci_serial_in;
3257 device->port.serial_out = sci_serial_out;
3258 device->port.type = type;
3259 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
daf5a895 3260 port_cfg.type = type;
0b0cced1 3261 sci_ports[0].cfg = &port_cfg;
daf5a895 3262 sci_ports[0].params = sci_probe_regmap(&port_cfg);
9f8325b3
LP		 3263 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3264 sci_serial_out(&sci_ports[0].port, SCSCR,
3265 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
0b0cced1
YS		 3266
3267 device->con->write = serial_console_write;
3268 return 0;
3269}
3270static int __init sci_early_console_setup(struct earlycon_device *device,
3271 const char *opt)
3272{
3273 return early_console_setup(device, PORT_SCI);
3274}
3275static int __init scif_early_console_setup(struct earlycon_device *device,
3276 const char *opt)
3277{
3278 return early_console_setup(device, PORT_SCIF);
3279}
3280static int __init scifa_early_console_setup(struct earlycon_device *device,
3281 const char *opt)
3282{
3283 return early_console_setup(device, PORT_SCIFA);
3284}
3285static int __init scifb_early_console_setup(struct earlycon_device *device,
3286 const char *opt)
3287{
3288 return early_console_setup(device, PORT_SCIFB);
3289}
3290static int __init hscif_early_console_setup(struct earlycon_device *device,
3291 const char *opt)
3292{
3293 return early_console_setup(device, PORT_HSCIF);
3294}
3295
0b0cced1 3296OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
0b0cced1 3297OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
0b0cced1 3298OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
0b0cced1 3299OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
0b0cced1
YS		 3300OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3301#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3302
1da177e4
LT		 3303module_init(sci_init);
3304module_exit(sci_exit);
3305
e108b2ca 3306MODULE_LICENSE("GPL");
e169c139 3307MODULE_ALIAS("platform:sh-sci");
7f405f9c 3308MODULE_AUTHOR("Paul Mundt");
f303b364 3309MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
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