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tty: add SPDX identifiers to all remaining files in drivers/tty/
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / sirfsoc_uart.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
161e773c
RW		 2/*
3 * Driver for CSR SiRFprimaII onboard UARTs.
4 *
5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10#include <linux/module.h>
11#include <linux/ioport.h>
12#include <linux/platform_device.h>
13#include <linux/init.h>
14#include <linux/sysrq.h>
15#include <linux/console.h>
16#include <linux/tty.h>
17#include <linux/tty_flip.h>
18#include <linux/serial_core.h>
19#include <linux/serial.h>
20#include <linux/clk.h>
21#include <linux/of.h>
22#include <linux/slab.h>
23#include <linux/io.h>
2eb5618d 24#include <linux/of_gpio.h>
8316d04c
QL		 25#include <linux/dmaengine.h>
26#include <linux/dma-direction.h>
27#include <linux/dma-mapping.h>
161e773c
RW		 28#include <asm/irq.h>
29#include <asm/mach/irq.h>
161e773c
RW		 30
31#include "sirfsoc_uart.h"
32
33static unsigned int
34sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
35static unsigned int
36sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
37static struct uart_driver sirfsoc_uart_drv;
38
8316d04c 39static void sirfsoc_uart_tx_dma_complete_callback(void *param);
161e773c
RW		 40static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
41 {4000000, 2359296},
42 {3500000, 1310721},
43 {3000000, 1572865},
44 {2500000, 1245186},
45 {2000000, 1572866},
46 {1500000, 1245188},
47 {1152000, 1638404},
48 {1000000, 1572869},
49 {921600, 1114120},
50 {576000, 1245196},
51 {500000, 1245198},
52 {460800, 1572876},
53 {230400, 1310750},
54 {115200, 1310781},
55 {57600, 1310843},
56 {38400, 1114328},
57 {19200, 1114545},
58 {9600, 1114979},
59};
60
a6ffe896 61static struct sirfsoc_uart_port *sirf_ports[SIRFSOC_UART_NR];
161e773c
RW		 62
63static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
64{
65 return container_of(port, struct sirfsoc_uart_port, port);
66}
67
68static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
69{
70 unsigned long reg;
5df83111
QL		 71 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
72 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
73 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
74 reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status);
cb4595a2 75 return (reg & ufifo_st->ff_empty(port)) ? TIOCSER_TEMT : 0;
161e773c
RW		 76}
77
78static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
79{
80 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111 81 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
2eb5618d 82 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
161e773c 83 goto cts_asserted;
2eb5618d 84 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
5df83111
QL		 85 if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) &
86 SIRFUART_AFC_CTS_STATUS))
161e773c
RW		 87 goto cts_asserted;
88 else
89 goto cts_deasserted;
2eb5618d
QL		 90 } else {
91 if (!gpio_get_value(sirfport->cts_gpio))
92 goto cts_asserted;
93 else
94 goto cts_deasserted;
161e773c
RW		 95 }
96cts_deasserted:
97 return TIOCM_CAR | TIOCM_DSR;
98cts_asserted:
99 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
100}
101
102static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
103{
104 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111 105 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
161e773c
RW		 106 unsigned int assert = mctrl & TIOCM_RTS;
107 unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
108 unsigned int current_val;
2eb5618d 109
7f60f2fe
QL		 110 if (mctrl & TIOCM_LOOP) {
111 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART)
112 wr_regl(port, ureg->sirfsoc_line_ctrl,
113 rd_regl(port, ureg->sirfsoc_line_ctrl) |
114 SIRFUART_LOOP_BACK);
115 else
116 wr_regl(port, ureg->sirfsoc_mode1,
117 rd_regl(port, ureg->sirfsoc_mode1) |
118 SIRFSOC_USP_LOOP_BACK_CTRL);
119 } else {
120 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART)
121 wr_regl(port, ureg->sirfsoc_line_ctrl,
122 rd_regl(port, ureg->sirfsoc_line_ctrl) &
123 ~SIRFUART_LOOP_BACK);
124 else
125 wr_regl(port, ureg->sirfsoc_mode1,
126 rd_regl(port, ureg->sirfsoc_mode1) &
127 ~SIRFSOC_USP_LOOP_BACK_CTRL);
128 }
129
2eb5618d
QL		 130 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
131 return;
132 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
5df83111 133 current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF;
161e773c 134 val |= current_val;
5df83111 135 wr_regl(port, ureg->sirfsoc_afc_ctrl, val);
2eb5618d
QL		 136 } else {
137 if (!val)
138 gpio_set_value(sirfport->rts_gpio, 1);
139 else
140 gpio_set_value(sirfport->rts_gpio, 0);
161e773c
RW		 141 }
142}
143
144static void sirfsoc_uart_stop_tx(struct uart_port *port)
145{
909102db 146 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 147 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
148 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
909102db 149
9be16b38 150 if (sirfport->tx_dma_chan) {
8316d04c
QL		 151 if (sirfport->tx_dma_state == TX_DMA_RUNNING) {
152 dmaengine_pause(sirfport->tx_dma_chan);
153 sirfport->tx_dma_state = TX_DMA_PAUSE;
154 } else {
057badd6 155 if (!sirfport->is_atlas7)
8316d04c
QL		 156 wr_regl(port, ureg->sirfsoc_int_en_reg,
157 rd_regl(port, ureg->sirfsoc_int_en_reg) &
158 ~uint_en->sirfsoc_txfifo_empty_en);
159 else
c1b7ac6f 160 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
8316d04c
QL		 161 uint_en->sirfsoc_txfifo_empty_en);
162 }
163 } else {
c1b7ac6f
QL		 164 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
165 wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port,
166 ureg->sirfsoc_tx_rx_en) & ~SIRFUART_TX_EN);
057badd6 167 if (!sirfport->is_atlas7)
8316d04c
QL		 168 wr_regl(port, ureg->sirfsoc_int_en_reg,
169 rd_regl(port, ureg->sirfsoc_int_en_reg) &
170 ~uint_en->sirfsoc_txfifo_empty_en);
171 else
c1b7ac6f 172 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
8316d04c
QL		 173 uint_en->sirfsoc_txfifo_empty_en);
174 }
175}
176
177static void sirfsoc_uart_tx_with_dma(struct sirfsoc_uart_port *sirfport)
178{
179 struct uart_port *port = &sirfport->port;
180 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
181 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
182 struct circ_buf *xmit = &port->state->xmit;
183 unsigned long tran_size;
184 unsigned long tran_start;
185 unsigned long pio_tx_size;
186
187 tran_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
188 tran_start = (unsigned long)(xmit->buf + xmit->tail);
189 if (uart_circ_empty(xmit) || uart_tx_stopped(port) ||
190 !tran_size)
191 return;
192 if (sirfport->tx_dma_state == TX_DMA_PAUSE) {
193 dmaengine_resume(sirfport->tx_dma_chan);
194 return;
195 }
196 if (sirfport->tx_dma_state == TX_DMA_RUNNING)
197 return;
057badd6 198 if (!sirfport->is_atlas7)
5df83111 199 wr_regl(port, ureg->sirfsoc_int_en_reg,
8316d04c
QL		 200 rd_regl(port, ureg->sirfsoc_int_en_reg)&
201 ~(uint_en->sirfsoc_txfifo_empty_en));
202 else
c1b7ac6f 203 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
5df83111 204 uint_en->sirfsoc_txfifo_empty_en);
8316d04c
QL		 205 /*
206 * DMA requires buffer address and buffer length are both aligned with
207 * 4 bytes, so we use PIO for
208 * 1. if address is not aligned with 4bytes, use PIO for the first 1~3
209 * bytes, and move to DMA for the left part aligned with 4bytes
210 * 2. if buffer length is not aligned with 4bytes, use DMA for aligned
211 * part first, move to PIO for the left 1~3 bytes
212 */
213 if (tran_size < 4 || BYTES_TO_ALIGN(tran_start)) {
214 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
215 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
216 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)|
217 SIRFUART_IO_MODE);
218 if (BYTES_TO_ALIGN(tran_start)) {
219 pio_tx_size = sirfsoc_uart_pio_tx_chars(sirfport,
220 BYTES_TO_ALIGN(tran_start));
221 tran_size -= pio_tx_size;
222 }
223 if (tran_size < 4)
224 sirfsoc_uart_pio_tx_chars(sirfport, tran_size);
057badd6 225 if (!sirfport->is_atlas7)
8316d04c
QL		 226 wr_regl(port, ureg->sirfsoc_int_en_reg,
227 rd_regl(port, ureg->sirfsoc_int_en_reg)|
228 uint_en->sirfsoc_txfifo_empty_en);
229 else
230 wr_regl(port, ureg->sirfsoc_int_en_reg,
231 uint_en->sirfsoc_txfifo_empty_en);
232 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
233 } else {
234 /* tx transfer mode switch into dma mode */
235 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
236 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
237 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)&
238 ~SIRFUART_IO_MODE);
239 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
240 tran_size &= ~(0x3);
241
242 sirfport->tx_dma_addr = dma_map_single(port->dev,
243 xmit->buf + xmit->tail,
244 tran_size, DMA_TO_DEVICE);
245 sirfport->tx_dma_desc = dmaengine_prep_slave_single(
246 sirfport->tx_dma_chan, sirfport->tx_dma_addr,
247 tran_size, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
248 if (!sirfport->tx_dma_desc) {
249 dev_err(port->dev, "DMA prep slave single fail\n");
250 return;
251 }
252 sirfport->tx_dma_desc->callback =
253 sirfsoc_uart_tx_dma_complete_callback;
254 sirfport->tx_dma_desc->callback_param = (void *)sirfport;
255 sirfport->transfer_size = tran_size;
256
257 dmaengine_submit(sirfport->tx_dma_desc);
258 dma_async_issue_pending(sirfport->tx_dma_chan);
259 sirfport->tx_dma_state = TX_DMA_RUNNING;
260 }
161e773c
RW		 261}
262
ada1f443 263static void sirfsoc_uart_start_tx(struct uart_port *port)
161e773c
RW		 264{
265 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 266 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
267 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
9be16b38 268 if (sirfport->tx_dma_chan)
8316d04c
QL		 269 sirfsoc_uart_tx_with_dma(sirfport);
270 else {
c1b7ac6f
QL		 271 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
272 wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port,
273 ureg->sirfsoc_tx_rx_en) | SIRFUART_TX_EN);
326707ed 274 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
cb4595a2 275 sirfsoc_uart_pio_tx_chars(sirfport, port->fifosize);
8316d04c 276 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
057badd6 277 if (!sirfport->is_atlas7)
8316d04c
QL		 278 wr_regl(port, ureg->sirfsoc_int_en_reg,
279 rd_regl(port, ureg->sirfsoc_int_en_reg)|
280 uint_en->sirfsoc_txfifo_empty_en);
281 else
282 wr_regl(port, ureg->sirfsoc_int_en_reg,
283 uint_en->sirfsoc_txfifo_empty_en);
284 }
161e773c
RW		 285}
286
287static void sirfsoc_uart_stop_rx(struct uart_port *port)
288{
909102db 289 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 290 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
291 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
8316d04c 292
5df83111 293 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
9be16b38 294 if (sirfport->rx_dma_chan) {
057badd6 295 if (!sirfport->is_atlas7)
8316d04c
QL		 296 wr_regl(port, ureg->sirfsoc_int_en_reg,
297 rd_regl(port, ureg->sirfsoc_int_en_reg) &
c1b7ac6f
QL		 298 ~(SIRFUART_RX_DMA_INT_EN(uint_en,
299 sirfport->uart_reg->uart_type) |
8316d04c
QL		 300 uint_en->sirfsoc_rx_done_en));
301 else
c1b7ac6f
QL		 302 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
303 SIRFUART_RX_DMA_INT_EN(uint_en,
304 sirfport->uart_reg->uart_type)|
305 uint_en->sirfsoc_rx_done_en);
8316d04c
QL		 306 dmaengine_terminate_all(sirfport->rx_dma_chan);
307 } else {
057badd6 308 if (!sirfport->is_atlas7)
8316d04c
QL		 309 wr_regl(port, ureg->sirfsoc_int_en_reg,
310 rd_regl(port, ureg->sirfsoc_int_en_reg)&
c1b7ac6f
QL		 311 ~(SIRFUART_RX_IO_INT_EN(uint_en,
312 sirfport->uart_reg->uart_type)));
8316d04c 313 else
c1b7ac6f
QL		 314 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
315 SIRFUART_RX_IO_INT_EN(uint_en,
316 sirfport->uart_reg->uart_type));
8316d04c 317 }
161e773c
RW		 318}
319
320static void sirfsoc_uart_disable_ms(struct uart_port *port)
321{
322 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 323 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
324 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
909102db 325
161e773c
RW		 326 if (!sirfport->hw_flow_ctrl)
327 return;
2eb5618d
QL		 328 sirfport->ms_enabled = false;
329 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
330 wr_regl(port, ureg->sirfsoc_afc_ctrl,
331 rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF);
057badd6 332 if (!sirfport->is_atlas7)
2eb5618d
QL		 333 wr_regl(port, ureg->sirfsoc_int_en_reg,
334 rd_regl(port, ureg->sirfsoc_int_en_reg)&
335 ~uint_en->sirfsoc_cts_en);
336 else
c1b7ac6f 337 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
2eb5618d 338 uint_en->sirfsoc_cts_en);
5df83111 339 } else
2eb5618d
QL		 340 disable_irq(gpio_to_irq(sirfport->cts_gpio));
341}
342
343static irqreturn_t sirfsoc_uart_usp_cts_handler(int irq, void *dev_id)
344{
345 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
346 struct uart_port *port = &sirfport->port;
07d410e0 347 spin_lock(&port->lock);
2eb5618d
QL		 348 if (gpio_is_valid(sirfport->cts_gpio) && sirfport->ms_enabled)
349 uart_handle_cts_change(port,
350 !gpio_get_value(sirfport->cts_gpio));
07d410e0 351 spin_unlock(&port->lock);
2eb5618d 352 return IRQ_HANDLED;
161e773c
RW		 353}
354
355static void sirfsoc_uart_enable_ms(struct uart_port *port)
356{
357 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 358 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
359 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
909102db 360
161e773c
RW		 361 if (!sirfport->hw_flow_ctrl)
362 return;
2eb5618d
QL		 363 sirfport->ms_enabled = true;
364 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
365 wr_regl(port, ureg->sirfsoc_afc_ctrl,
366 rd_regl(port, ureg->sirfsoc_afc_ctrl) |
eab192ae
QL		 367 SIRFUART_AFC_TX_EN | SIRFUART_AFC_RX_EN |
368 SIRFUART_AFC_CTRL_RX_THD);
057badd6 369 if (!sirfport->is_atlas7)
2eb5618d
QL		 370 wr_regl(port, ureg->sirfsoc_int_en_reg,
371 rd_regl(port, ureg->sirfsoc_int_en_reg)
372 | uint_en->sirfsoc_cts_en);
373 else
374 wr_regl(port, ureg->sirfsoc_int_en_reg,
375 uint_en->sirfsoc_cts_en);
5df83111 376 } else
2eb5618d 377 enable_irq(gpio_to_irq(sirfport->cts_gpio));
161e773c
RW		 378}
379
380static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
381{
5df83111
QL		 382 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
383 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
384 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
385 unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl);
386 if (break_state)
387 ulcon |= SIRFUART_SET_BREAK;
388 else
389 ulcon &= ~SIRFUART_SET_BREAK;
390 wr_regl(port, ureg->sirfsoc_line_ctrl, ulcon);
391 }
161e773c
RW		 392}
393
394static unsigned int
395sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
396{
5df83111
QL		 397 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
398 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
399 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
161e773c 400 unsigned int ch, rx_count = 0;
5df83111
QL		 401 struct tty_struct *tty;
402 tty = tty_port_tty_get(&port->state->port);
403 if (!tty)
404 return -ENODEV;
405 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
cb4595a2 406 ufifo_st->ff_empty(port))) {
5df83111
QL		 407 ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) |
408 SIRFUART_DUMMY_READ;
161e773c
RW		 409 if (unlikely(uart_handle_sysrq_char(port, ch)))
410 continue;
411 uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
412 rx_count++;
413 if (rx_count >= max_rx_count)
414 break;
415 }
416
417 port->icount.rx += rx_count;
8b9ade9f 418
161e773c
RW		 419 return rx_count;
420}
421
422static unsigned int
423sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
424{
425 struct uart_port *port = &sirfport->port;
5df83111
QL		 426 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
427 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
161e773c
RW		 428 struct circ_buf *xmit = &port->state->xmit;
429 unsigned int num_tx = 0;
430 while (!uart_circ_empty(xmit) &&
5df83111 431 !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
cb4595a2 432 ufifo_st->ff_full(port)) &&
161e773c 433 count--) {
5df83111
QL		 434 wr_regl(port, ureg->sirfsoc_tx_fifo_data,
435 xmit->buf[xmit->tail]);
161e773c
RW		 436 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
437 port->icount.tx++;
438 num_tx++;
439 }
440 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
441 uart_write_wakeup(port);
442 return num_tx;
443}
444
8316d04c
QL		 445static void sirfsoc_uart_tx_dma_complete_callback(void *param)
446{
447 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
448 struct uart_port *port = &sirfport->port;
449 struct circ_buf *xmit = &port->state->xmit;
450 unsigned long flags;
451
07d410e0 452 spin_lock_irqsave(&port->lock, flags);
8316d04c
QL		 453 xmit->tail = (xmit->tail + sirfport->transfer_size) &
454 (UART_XMIT_SIZE - 1);
455 port->icount.tx += sirfport->transfer_size;
456 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
457 uart_write_wakeup(port);
458 if (sirfport->tx_dma_addr)
459 dma_unmap_single(port->dev, sirfport->tx_dma_addr,
460 sirfport->transfer_size, DMA_TO_DEVICE);
8316d04c
QL		 461 sirfport->tx_dma_state = TX_DMA_IDLE;
462 sirfsoc_uart_tx_with_dma(sirfport);
07d410e0 463 spin_unlock_irqrestore(&port->lock, flags);
8316d04c
QL		 464}
465
161e773c
RW		 466static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
467{
468 unsigned long intr_status;
469 unsigned long cts_status;
470 unsigned long flag = TTY_NORMAL;
471 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
472 struct uart_port *port = &sirfport->port;
5df83111
QL		 473 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
474 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
475 struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
476 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
161e773c
RW		 477 struct uart_state *state = port->state;
478 struct circ_buf *xmit = &port->state->xmit;
5425e03f 479 spin_lock(&port->lock);
5df83111
QL		 480 intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg);
481 wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status);
8316d04c 482 intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg);
c1b7ac6f
QL		 483 if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT(uint_st,
484 sirfport->uart_reg->uart_type)))) {
5df83111
QL		 485 if (intr_status & uint_st->sirfsoc_rxd_brk) {
486 port->icount.brk++;
161e773c
RW		 487 if (uart_handle_break(port))
488 goto recv_char;
161e773c 489 }
d9e8e976 490 if (intr_status & uint_st->sirfsoc_rx_oflow) {
161e773c 491 port->icount.overrun++;
d9e8e976
QL		 492 flag = TTY_OVERRUN;
493 }
5df83111 494 if (intr_status & uint_st->sirfsoc_frm_err) {
161e773c
RW		 495 port->icount.frame++;
496 flag = TTY_FRAME;
497 }
d9e8e976
QL		 498 if (intr_status & uint_st->sirfsoc_parity_err) {
499 port->icount.parity++;
161e773c 500 flag = TTY_PARITY;
d9e8e976 501 }
5df83111
QL		 502 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
503 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
504 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
161e773c
RW		 505 intr_status &= port->read_status_mask;
506 uart_insert_char(port, intr_status,
5df83111 507 uint_en->sirfsoc_rx_oflow_en, 0, flag);
161e773c
RW		 508 }
509recv_char:
5df83111 510 if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) &&
8316d04c
QL		 511 (intr_status & SIRFUART_CTS_INT_ST(uint_st)) &&
512 !sirfport->tx_dma_state) {
5df83111
QL		 513 cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) &
514 SIRFUART_AFC_CTS_STATUS;
515 if (cts_status != 0)
516 cts_status = 0;
517 else
518 cts_status = 1;
519 uart_handle_cts_change(port, cts_status);
520 wake_up_interruptible(&state->port.delta_msr_wait);
161e773c 521 }
0f17e3b4
QL		 522 if (!sirfport->rx_dma_chan &&
523 (intr_status & SIRFUART_RX_IO_INT_ST(uint_st))) {
c1b7ac6f
QL		 524 /*
525 * chip will trigger continuous RX_TIMEOUT interrupt
526 * in RXFIFO empty and not trigger if RXFIFO recevice
527 * data in limit time, original method use RX_TIMEOUT
528 * will trigger lots of useless interrupt in RXFIFO
529 * empty.RXFIFO received one byte will trigger RX_DONE
530 * interrupt.use RX_DONE to wait for data received
531 * into RXFIFO, use RX_THD/RX_FULL for lots data receive
532 * and use RX_TIMEOUT for the last left data.
533 */
534 if (intr_status & uint_st->sirfsoc_rx_done) {
535 if (!sirfport->is_atlas7) {
536 wr_regl(port, ureg->sirfsoc_int_en_reg,
537 rd_regl(port, ureg->sirfsoc_int_en_reg)
538 & ~(uint_en->sirfsoc_rx_done_en));
539 wr_regl(port, ureg->sirfsoc_int_en_reg,
540 rd_regl(port, ureg->sirfsoc_int_en_reg)
541 | (uint_en->sirfsoc_rx_timeout_en));
542 } else {
543 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
544 uint_en->sirfsoc_rx_done_en);
545 wr_regl(port, ureg->sirfsoc_int_en_reg,
546 uint_en->sirfsoc_rx_timeout_en);
547 }
548 } else {
549 if (intr_status & uint_st->sirfsoc_rx_timeout) {
550 if (!sirfport->is_atlas7) {
551 wr_regl(port, ureg->sirfsoc_int_en_reg,
552 rd_regl(port, ureg->sirfsoc_int_en_reg)
553 & ~(uint_en->sirfsoc_rx_timeout_en));
554 wr_regl(port, ureg->sirfsoc_int_en_reg,
555 rd_regl(port, ureg->sirfsoc_int_en_reg)
556 | (uint_en->sirfsoc_rx_done_en));
557 } else {
558 wr_regl(port,
559 ureg->sirfsoc_int_en_clr_reg,
560 uint_en->sirfsoc_rx_timeout_en);
561 wr_regl(port, ureg->sirfsoc_int_en_reg,
562 uint_en->sirfsoc_rx_done_en);
563 }
564 }
cb4595a2 565 sirfsoc_uart_pio_rx_chars(port, port->fifosize);
c1b7ac6f 566 }
8316d04c 567 }
07d410e0
QL		 568 spin_unlock(&port->lock);
569 tty_flip_buffer_push(&state->port);
570 spin_lock(&port->lock);
5df83111 571 if (intr_status & uint_st->sirfsoc_txfifo_empty) {
9be16b38 572 if (sirfport->tx_dma_chan)
8316d04c
QL		 573 sirfsoc_uart_tx_with_dma(sirfport);
574 else {
575 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
576 spin_unlock(&port->lock);
577 return IRQ_HANDLED;
578 } else {
579 sirfsoc_uart_pio_tx_chars(sirfport,
cb4595a2 580 port->fifosize);
8316d04c 581 if ((uart_circ_empty(xmit)) &&
5df83111 582 (rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
cb4595a2 583 ufifo_st->ff_empty(port)))
8316d04c
QL		 584 sirfsoc_uart_stop_tx(port);
585 }
161e773c
RW		 586 }
587 }
5425e03f 588 spin_unlock(&port->lock);
07d410e0 589
161e773c
RW		 590 return IRQ_HANDLED;
591}
592
8316d04c
QL		 593static void sirfsoc_uart_rx_dma_complete_callback(void *param)
594{
8316d04c
QL		 595}
596
597/* submit rx dma task into dmaengine */
598static void sirfsoc_uart_start_next_rx_dma(struct uart_port *port)
161e773c 599{
909102db 600 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 601 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
602 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
8316d04c
QL		 603 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
604 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
605 ~SIRFUART_IO_MODE);
0f17e3b4
QL		 606 sirfport->rx_dma_items.xmit.tail =
607 sirfport->rx_dma_items.xmit.head = 0;
608 sirfport->rx_dma_items.desc =
609 dmaengine_prep_dma_cyclic(sirfport->rx_dma_chan,
610 sirfport->rx_dma_items.dma_addr, SIRFSOC_RX_DMA_BUF_SIZE,
611 SIRFSOC_RX_DMA_BUF_SIZE / 2,
612 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
613 if (IS_ERR_OR_NULL(sirfport->rx_dma_items.desc)) {
614 dev_err(port->dev, "DMA slave single fail\n");
615 return;
616 }
617 sirfport->rx_dma_items.desc->callback =
618 sirfsoc_uart_rx_dma_complete_callback;
619 sirfport->rx_dma_items.desc->callback_param = sirfport;
620 sirfport->rx_dma_items.cookie =
621 dmaengine_submit(sirfport->rx_dma_items.desc);
622 dma_async_issue_pending(sirfport->rx_dma_chan);
057badd6 623 if (!sirfport->is_atlas7)
5df83111 624 wr_regl(port, ureg->sirfsoc_int_en_reg,
8316d04c 625 rd_regl(port, ureg->sirfsoc_int_en_reg) |
c1b7ac6f
QL		 626 SIRFUART_RX_DMA_INT_EN(uint_en,
627 sirfport->uart_reg->uart_type));
8316d04c
QL		 628 else
629 wr_regl(port, ureg->sirfsoc_int_en_reg,
c1b7ac6f
QL		 630 SIRFUART_RX_DMA_INT_EN(uint_en,
631 sirfport->uart_reg->uart_type));
8316d04c
QL		 632}
633
5df83111
QL		 634static unsigned int
635sirfsoc_usp_calc_sample_div(unsigned long set_rate,
636 unsigned long ioclk_rate, unsigned long *sample_reg)
637{
638 unsigned long min_delta = ~0UL;
639 unsigned short sample_div;
640 unsigned long ioclk_div = 0;
641 unsigned long temp_delta;
642
cb4595a2 643 for (sample_div = SIRF_USP_MIN_SAMPLE_DIV;
5df83111
QL		 644 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
645 temp_delta = ioclk_rate -
646 (ioclk_rate + (set_rate * sample_div) / 2)
647 / (set_rate * sample_div) * set_rate * sample_div;
909102db 648
5df83111
QL		 649 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
650 if (temp_delta < min_delta) {
651 ioclk_div = (2 * ioclk_rate /
652 (set_rate * sample_div) + 1) / 2 - 1;
653 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
654 continue;
655 min_delta = temp_delta;
656 *sample_reg = sample_div;
657 if (!temp_delta)
658 break;
659 }
660 }
661 return ioclk_div;
161e773c
RW		 662}
663
664static unsigned int
5df83111
QL		 665sirfsoc_uart_calc_sample_div(unsigned long baud_rate,
666 unsigned long ioclk_rate, unsigned long *set_baud)
161e773c
RW		 667{
668 unsigned long min_delta = ~0UL;
669 unsigned short sample_div;
670 unsigned int regv = 0;
671 unsigned long ioclk_div;
672 unsigned long baud_tmp;
673 int temp_delta;
674
675 for (sample_div = SIRF_MIN_SAMPLE_DIV;
676 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
677 ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
678 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
679 continue;
680 baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
681 temp_delta = baud_tmp - baud_rate;
682 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
683 if (temp_delta < min_delta) {
684 regv = regv & (~SIRF_IOCLK_DIV_MASK);
685 regv = regv | ioclk_div;
686 regv = regv & (~SIRF_SAMPLE_DIV_MASK);
687 regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
688 min_delta = temp_delta;
5df83111 689 *set_baud = baud_tmp;
161e773c
RW		 690 }
691 }
692 return regv;
693}
694
695static void sirfsoc_uart_set_termios(struct uart_port *port,
696 struct ktermios *termios,
697 struct ktermios *old)
698{
699 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 700 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
701 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
161e773c
RW		 702 unsigned long config_reg = 0;
703 unsigned long baud_rate;
5df83111 704 unsigned long set_baud;
161e773c
RW		 705 unsigned long flags;
706 unsigned long ic;
707 unsigned int clk_div_reg = 0;
8316d04c 708 unsigned long txfifo_op_reg, ioclk_rate;
161e773c
RW		 709 unsigned long rx_time_out;
710 int threshold_div;
5df83111
QL		 711 u32 data_bit_len, stop_bit_len, len_val;
712 unsigned long sample_div_reg = 0xf;
713 ioclk_rate = port->uartclk;
161e773c 714
161e773c
RW		 715 switch (termios->c_cflag & CSIZE) {
716 default:
717 case CS8:
5df83111 718 data_bit_len = 8;
161e773c
RW		 719 config_reg |= SIRFUART_DATA_BIT_LEN_8;
720 break;
721 case CS7:
5df83111 722 data_bit_len = 7;
161e773c
RW		 723 config_reg |= SIRFUART_DATA_BIT_LEN_7;
724 break;
725 case CS6:
5df83111 726 data_bit_len = 6;
161e773c
RW		 727 config_reg |= SIRFUART_DATA_BIT_LEN_6;
728 break;
729 case CS5:
5df83111 730 data_bit_len = 5;
161e773c
RW		 731 config_reg |= SIRFUART_DATA_BIT_LEN_5;
732 break;
733 }
5df83111 734 if (termios->c_cflag & CSTOPB) {
161e773c 735 config_reg |= SIRFUART_STOP_BIT_LEN_2;
5df83111
QL		 736 stop_bit_len = 2;
737 } else
738 stop_bit_len = 1;
739
161e773c 740 spin_lock_irqsave(&port->lock, flags);
5df83111 741 port->read_status_mask = uint_en->sirfsoc_rx_oflow_en;
161e773c 742 port->ignore_status_mask = 0;
5df83111
QL		 743 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
744 if (termios->c_iflag & INPCK)
745 port->read_status_mask |= uint_en->sirfsoc_frm_err_en |
746 uint_en->sirfsoc_parity_err_en;
2eb5618d 747 } else {
5df83111
QL		 748 if (termios->c_iflag & INPCK)
749 port->read_status_mask |= uint_en->sirfsoc_frm_err_en;
750 }
ef8b9ddc 751 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
5df83111
QL		 752 port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en;
753 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
754 if (termios->c_iflag & IGNPAR)
755 port->ignore_status_mask |=
756 uint_en->sirfsoc_frm_err_en |
757 uint_en->sirfsoc_parity_err_en;
758 if (termios->c_cflag & PARENB) {
759 if (termios->c_cflag & CMSPAR) {
760 if (termios->c_cflag & PARODD)
761 config_reg |= SIRFUART_STICK_BIT_MARK;
762 else
763 config_reg |= SIRFUART_STICK_BIT_SPACE;
5df83111 764 } else {
d9e8e976
QL		 765 if (termios->c_cflag & PARODD)
766 config_reg |= SIRFUART_STICK_BIT_ODD;
767 else
768 config_reg |= SIRFUART_STICK_BIT_EVEN;
5df83111
QL		 769 }
770 }
2eb5618d 771 } else {
5df83111
QL		 772 if (termios->c_iflag & IGNPAR)
773 port->ignore_status_mask |=
774 uint_en->sirfsoc_frm_err_en;
775 if (termios->c_cflag & PARENB)
776 dev_warn(port->dev,
777 "USP-UART not support parity err\n");
778 }
779 if (termios->c_iflag & IGNBRK) {
161e773c 780 port->ignore_status_mask |=
5df83111
QL		 781 uint_en->sirfsoc_rxd_brk_en;
782 if (termios->c_iflag & IGNPAR)
783 port->ignore_status_mask |=
784 uint_en->sirfsoc_rx_oflow_en;
785 }
161e773c
RW		 786 if ((termios->c_cflag & CREAD) == 0)
787 port->ignore_status_mask |= SIRFUART_DUMMY_READ;
161e773c
RW		 788 /* Hardware Flow Control Settings */
789 if (UART_ENABLE_MS(port, termios->c_cflag)) {
790 if (!sirfport->ms_enabled)
791 sirfsoc_uart_enable_ms(port);
792 } else {
793 if (sirfport->ms_enabled)
794 sirfsoc_uart_disable_ms(port);
795 }
5df83111
QL		 796 baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
797 if (ioclk_rate == 150000000) {
ac4ce718
BS		 798 for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
799 if (baud_rate == baudrate_to_regv[ic].baud_rate)
800 clk_div_reg = baudrate_to_regv[ic].reg_val;
801 }
5df83111
QL		 802 set_baud = baud_rate;
803 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
804 if (unlikely(clk_div_reg == 0))
805 clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate,
806 ioclk_rate, &set_baud);
807 wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg);
2eb5618d 808 } else {
5df83111
QL		 809 clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate,
810 ioclk_rate, &sample_div_reg);
811 sample_div_reg--;
812 set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) /
813 (sample_div_reg + 1));
814 /* setting usp mode 2 */
459f15c4
QL		 815 len_val = ((1 << SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET) |
816 (1 << SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET));
817 len_val |= ((clk_div_reg & SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK)
818 << SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET);
819 wr_regl(port, ureg->sirfsoc_mode2, len_val);
5df83111 820 }
161e773c 821 if (tty_termios_baud_rate(termios))
5df83111
QL		 822 tty_termios_encode_baud_rate(termios, set_baud, set_baud);
823 /* set receive timeout && data bits len */
824 rx_time_out = SIRFSOC_UART_RX_TIMEOUT(set_baud, 20000);
825 rx_time_out = SIRFUART_RECV_TIMEOUT_VALUE(rx_time_out);
8316d04c 826 txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op);
5df83111 827 wr_regl(port, ureg->sirfsoc_tx_fifo_op,
8316d04c 828 (txfifo_op_reg & ~SIRFUART_FIFO_START));
5df83111 829 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
c1b7ac6f 830 config_reg |= SIRFUART_UART_RECV_TIMEOUT(rx_time_out);
5df83111 831 wr_regl(port, ureg->sirfsoc_line_ctrl, config_reg);
2eb5618d 832 } else {
5df83111 833 /*tx frame ctrl*/
459f15c4
QL		 834 len_val = (data_bit_len - 1) << SIRFSOC_USP_TX_DATA_LEN_OFFSET;
835 len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
836 SIRFSOC_USP_TX_FRAME_LEN_OFFSET;
837 len_val |= ((data_bit_len - 1) <<
838 SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET);
839 len_val |= (((clk_div_reg & 0xc00) >> 10) <<
840 SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET);
5df83111
QL		 841 wr_regl(port, ureg->sirfsoc_tx_frame_ctrl, len_val);
842 /*rx frame ctrl*/
459f15c4
QL		 843 len_val = (data_bit_len - 1) << SIRFSOC_USP_RX_DATA_LEN_OFFSET;
844 len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
845 SIRFSOC_USP_RX_FRAME_LEN_OFFSET;
846 len_val |= (data_bit_len - 1) <<
847 SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET;
848 len_val |= (((clk_div_reg & 0xf000) >> 12) <<
849 SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET);
5df83111
QL		 850 wr_regl(port, ureg->sirfsoc_rx_frame_ctrl, len_val);
851 /*async param*/
852 wr_regl(port, ureg->sirfsoc_async_param_reg,
c1b7ac6f 853 (SIRFUART_USP_RECV_TIMEOUT(rx_time_out)) |
459f15c4
QL		 854 (sample_div_reg & SIRFSOC_USP_ASYNC_DIV2_MASK) <<
855 SIRFSOC_USP_ASYNC_DIV2_OFFSET);
5df83111 856 }
9be16b38 857 if (sirfport->tx_dma_chan)
8316d04c
QL		 858 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_DMA_MODE);
859 else
860 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_IO_MODE);
9be16b38 861 if (sirfport->rx_dma_chan)
1d26c9ff
QL		 862 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
863 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
864 ~SIRFUART_IO_MODE);
8316d04c 865 else
1d26c9ff
QL		 866 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
867 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
868 SIRFUART_IO_MODE);
0f17e3b4 869 sirfport->rx_period_time = 20000000;
161e773c 870 /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
5df83111 871 if (set_baud < 1000000)
161e773c
RW		 872 threshold_div = 1;
873 else
874 threshold_div = 2;
8316d04c
QL		 875 wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl,
876 SIRFUART_FIFO_THD(port) / threshold_div);
877 wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl,
878 SIRFUART_FIFO_THD(port) / threshold_div);
879 txfifo_op_reg |= SIRFUART_FIFO_START;
880 wr_regl(port, ureg->sirfsoc_tx_fifo_op, txfifo_op_reg);
5df83111 881 uart_update_timeout(port, termios->c_cflag, set_baud);
5df83111 882 wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_TX_EN | SIRFUART_RX_EN);
161e773c
RW		 883 spin_unlock_irqrestore(&port->lock, flags);
884}
885
388faf9f
QL		 886static void sirfsoc_uart_pm(struct uart_port *port, unsigned int state,
887 unsigned int oldstate)
888{
889 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
4b8038dc 890 if (!state)
388faf9f 891 clk_prepare_enable(sirfport->clk);
4b8038dc 892 else
388faf9f
QL		 893 clk_disable_unprepare(sirfport->clk);
894}
895
161e773c
RW		 896static int sirfsoc_uart_startup(struct uart_port *port)
897{
898 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
15cdcb12 899 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
466e285b 900 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
161e773c
RW		 901 unsigned int index = port->line;
902 int ret;
2a446241 903 irq_modify_status(port->irq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
161e773c
RW		 904 ret = request_irq(port->irq,
905 sirfsoc_uart_isr,
906 0,
907 SIRFUART_PORT_NAME,
908 sirfport);
909 if (ret != 0) {
910 dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
911 index, port->irq);
912 goto irq_err;
913 }
15cdcb12
QL		 914 /* initial hardware settings */
915 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
916 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) |
917 SIRFUART_IO_MODE);
918 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
919 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
920 SIRFUART_IO_MODE);
0f17e3b4
QL		 921 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
922 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
923 ~SIRFUART_RX_DMA_FLUSH);
15cdcb12
QL		 924 wr_regl(port, ureg->sirfsoc_tx_dma_io_len, 0);
925 wr_regl(port, ureg->sirfsoc_rx_dma_io_len, 0);
926 wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_RX_EN | SIRFUART_TX_EN);
927 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
928 wr_regl(port, ureg->sirfsoc_mode1,
929 SIRFSOC_USP_ENDIAN_CTRL_LSBF |
930 SIRFSOC_USP_EN);
931 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_RESET);
15cdcb12
QL		 932 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
933 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
934 wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, SIRFUART_FIFO_THD(port));
935 wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, SIRFUART_FIFO_THD(port));
9be16b38 936 if (sirfport->rx_dma_chan)
8316d04c 937 wr_regl(port, ureg->sirfsoc_rx_fifo_level_chk,
1d26c9ff
QL		 938 SIRFUART_RX_FIFO_CHK_SC(port->line, 0x1) |
939 SIRFUART_RX_FIFO_CHK_LC(port->line, 0x2) |
940 SIRFUART_RX_FIFO_CHK_HC(port->line, 0x4));
9be16b38 941 if (sirfport->tx_dma_chan) {
8316d04c
QL		 942 sirfport->tx_dma_state = TX_DMA_IDLE;
943 wr_regl(port, ureg->sirfsoc_tx_fifo_level_chk,
944 SIRFUART_TX_FIFO_CHK_SC(port->line, 0x1b) |
945 SIRFUART_TX_FIFO_CHK_LC(port->line, 0xe) |
946 SIRFUART_TX_FIFO_CHK_HC(port->line, 0x4));
947 }
2eb5618d
QL		 948 sirfport->ms_enabled = false;
949 if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
950 sirfport->hw_flow_ctrl) {
2a446241
RH		 951 irq_modify_status(gpio_to_irq(sirfport->cts_gpio),
952 IRQ_NOREQUEST, IRQ_NOAUTOEN);
2eb5618d
QL		 953 ret = request_irq(gpio_to_irq(sirfport->cts_gpio),
954 sirfsoc_uart_usp_cts_handler, IRQF_TRIGGER_FALLING |
955 IRQF_TRIGGER_RISING, "usp_cts_irq", sirfport);
956 if (ret != 0) {
957 dev_err(port->dev, "UART-USP:request gpio irq fail\n");
958 goto init_rx_err;
959 }
960 }
1d26c9ff
QL		 961 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART &&
962 sirfport->rx_dma_chan)
963 wr_regl(port, ureg->sirfsoc_swh_dma_io,
964 SIRFUART_CLEAR_RX_ADDR_EN);
965 if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
966 sirfport->rx_dma_chan)
967 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
968 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
969 SIRFSOC_USP_FRADDR_CLR_EN);
0f17e3b4
QL		 970 if (sirfport->rx_dma_chan && !sirfport->is_hrt_enabled) {
971 sirfport->is_hrt_enabled = true;
972 sirfport->rx_period_time = 20000000;
1d26c9ff
QL		 973 sirfport->rx_last_pos = -1;
974 sirfport->pio_fetch_cnt = 0;
0f17e3b4
QL		 975 sirfport->rx_dma_items.xmit.tail =
976 sirfport->rx_dma_items.xmit.head = 0;
977 hrtimer_start(&sirfport->hrt,
978 ns_to_ktime(sirfport->rx_period_time),
979 HRTIMER_MODE_REL);
980 }
466e285b
QL		 981 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
982 if (sirfport->rx_dma_chan)
983 sirfsoc_uart_start_next_rx_dma(port);
984 else {
985 if (!sirfport->is_atlas7)
986 wr_regl(port, ureg->sirfsoc_int_en_reg,
987 rd_regl(port, ureg->sirfsoc_int_en_reg) |
988 SIRFUART_RX_IO_INT_EN(uint_en,
989 sirfport->uart_reg->uart_type));
990 else
991 wr_regl(port, ureg->sirfsoc_int_en_reg,
992 SIRFUART_RX_IO_INT_EN(uint_en,
993 sirfport->uart_reg->uart_type));
994 }
995 enable_irq(port->irq);
2eb5618d 996
15cdcb12 997 return 0;
2eb5618d
QL		 998init_rx_err:
999 free_irq(port->irq, sirfport);
161e773c
RW		 1000irq_err:
1001 return ret;
1002}
1003
1004static void sirfsoc_uart_shutdown(struct uart_port *port)
1005{
1006 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111 1007 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1d26c9ff
QL		 1008 struct circ_buf *xmit;
1009
1010 xmit = &sirfport->rx_dma_items.xmit;
057badd6 1011 if (!sirfport->is_atlas7)
5df83111 1012 wr_regl(port, ureg->sirfsoc_int_en_reg, 0);
909102db 1013 else
c1b7ac6f 1014 wr_regl(port, ureg->sirfsoc_int_en_clr_reg, ~0UL);
909102db 1015
161e773c 1016 free_irq(port->irq, sirfport);
2eb5618d 1017 if (sirfport->ms_enabled)
161e773c 1018 sirfsoc_uart_disable_ms(port);
2eb5618d
QL		 1019 if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
1020 sirfport->hw_flow_ctrl) {
1021 gpio_set_value(sirfport->rts_gpio, 1);
1022 free_irq(gpio_to_irq(sirfport->cts_gpio), sirfport);
161e773c 1023 }
9be16b38 1024 if (sirfport->tx_dma_chan)
8316d04c 1025 sirfport->tx_dma_state = TX_DMA_IDLE;
0f17e3b4 1026 if (sirfport->rx_dma_chan && sirfport->is_hrt_enabled) {
1d26c9ff
QL		 1027 while (((rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
1028 SIRFUART_RX_FIFO_MASK) > sirfport->pio_fetch_cnt) &&
1029 !CIRC_CNT(xmit->head, xmit->tail,
1030 SIRFSOC_RX_DMA_BUF_SIZE))
0f17e3b4
QL		 1031 ;
1032 sirfport->is_hrt_enabled = false;
1033 hrtimer_cancel(&sirfport->hrt);
1034 }
161e773c
RW		 1035}
1036
1037static const char *sirfsoc_uart_type(struct uart_port *port)
1038{
1039 return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
1040}
1041
1042static int sirfsoc_uart_request_port(struct uart_port *port)
1043{
5df83111
QL		 1044 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1045 struct sirfsoc_uart_param *uart_param = &sirfport->uart_reg->uart_param;
161e773c
RW		 1046 void *ret;
1047 ret = request_mem_region(port->mapbase,
5df83111 1048 SIRFUART_MAP_SIZE, uart_param->port_name);
161e773c
RW		 1049 return ret ? 0 : -EBUSY;
1050}
1051
1052static void sirfsoc_uart_release_port(struct uart_port *port)
1053{
1054 release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
1055}
1056
1057static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
1058{
1059 if (flags & UART_CONFIG_TYPE) {
1060 port->type = SIRFSOC_PORT_TYPE;
1061 sirfsoc_uart_request_port(port);
1062 }
1063}
1064
2331e068 1065static const struct uart_ops sirfsoc_uart_ops = {
161e773c
RW		 1066 .tx_empty = sirfsoc_uart_tx_empty,
1067 .get_mctrl = sirfsoc_uart_get_mctrl,
1068 .set_mctrl = sirfsoc_uart_set_mctrl,
1069 .stop_tx = sirfsoc_uart_stop_tx,
1070 .start_tx = sirfsoc_uart_start_tx,
1071 .stop_rx = sirfsoc_uart_stop_rx,
1072 .enable_ms = sirfsoc_uart_enable_ms,
1073 .break_ctl = sirfsoc_uart_break_ctl,
1074 .startup = sirfsoc_uart_startup,
1075 .shutdown = sirfsoc_uart_shutdown,
1076 .set_termios = sirfsoc_uart_set_termios,
388faf9f 1077 .pm = sirfsoc_uart_pm,
161e773c
RW		 1078 .type = sirfsoc_uart_type,
1079 .release_port = sirfsoc_uart_release_port,
1080 .request_port = sirfsoc_uart_request_port,
1081 .config_port = sirfsoc_uart_config_port,
1082};
1083
1084#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
5df83111
QL		 1085static int __init
1086sirfsoc_uart_console_setup(struct console *co, char *options)
161e773c
RW		 1087{
1088 unsigned int baud = 115200;
1089 unsigned int bits = 8;
1090 unsigned int parity = 'n';
1091 unsigned int flow = 'n';
a6ffe896
QL		 1092 struct sirfsoc_uart_port *sirfport;
1093 struct sirfsoc_register *ureg;
161e773c 1094 if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
c35b49b7 1095 co->index = 1;
a6ffe896
QL		 1096 sirfport = sirf_ports[co->index];
1097 if (!sirfport)
1098 return -ENODEV;
1099 ureg = &sirfport->uart_reg->uart_reg;
1100 if (!sirfport->port.mapbase)
161e773c
RW		 1101 return -ENODEV;
1102
5df83111
QL		 1103 /* enable usp in mode1 register */
1104 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
a6ffe896 1105 wr_regl(&sirfport->port, ureg->sirfsoc_mode1, SIRFSOC_USP_EN |
5df83111 1106 SIRFSOC_USP_ENDIAN_CTRL_LSBF);
161e773c
RW		 1107 if (options)
1108 uart_parse_options(options, &baud, &parity, &bits, &flow);
a6ffe896 1109 sirfport->port.cons = co;
5df83111 1110
8316d04c 1111 /* default console tx/rx transfer using io mode */
9be16b38
QL		 1112 sirfport->rx_dma_chan = NULL;
1113 sirfport->tx_dma_chan = NULL;
a6ffe896 1114 return uart_set_options(&sirfport->port, co, baud, parity, bits, flow);
161e773c
RW		 1115}
1116
1117static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
1118{
5df83111
QL		 1119 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1120 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1121 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
cb4595a2
QL		 1122 while (rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
1123 ufifo_st->ff_full(port))
161e773c 1124 cpu_relax();
205c384f 1125 wr_regl(port, ureg->sirfsoc_tx_fifo_data, ch);
161e773c
RW		 1126}
1127
1128static void sirfsoc_uart_console_write(struct console *co, const char *s,
1129 unsigned int count)
1130{
a6ffe896
QL		 1131 struct sirfsoc_uart_port *sirfport = sirf_ports[co->index];
1132
1133 uart_console_write(&sirfport->port, s, count,
1134 sirfsoc_uart_console_putchar);
161e773c
RW		 1135}
1136
1137static struct console sirfsoc_uart_console = {
1138 .name = SIRFSOC_UART_NAME,
1139 .device = uart_console_device,
1140 .flags = CON_PRINTBUFFER,
1141 .index = -1,
1142 .write = sirfsoc_uart_console_write,
1143 .setup = sirfsoc_uart_console_setup,
1144 .data = &sirfsoc_uart_drv,
1145};
1146
1147static int __init sirfsoc_uart_console_init(void)
1148{
1149 register_console(&sirfsoc_uart_console);
1150 return 0;
1151}
1152console_initcall(sirfsoc_uart_console_init);
1153#endif
1154
1155static struct uart_driver sirfsoc_uart_drv = {
1156 .owner = THIS_MODULE,
1157 .driver_name = SIRFUART_PORT_NAME,
1158 .nr = SIRFSOC_UART_NR,
1159 .dev_name = SIRFSOC_UART_NAME,
1160 .major = SIRFSOC_UART_MAJOR,
1161 .minor = SIRFSOC_UART_MINOR,
1162#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
1163 .cons = &sirfsoc_uart_console,
1164#else
1165 .cons = NULL,
1166#endif
1167};
1168
0f17e3b4
QL		 1169static enum hrtimer_restart
1170 sirfsoc_uart_rx_dma_hrtimer_callback(struct hrtimer *hrt)
1171{
1172 struct sirfsoc_uart_port *sirfport;
1173 struct uart_port *port;
1174 int count, inserted;
1175 struct dma_tx_state tx_state;
1176 struct tty_struct *tty;
1177 struct sirfsoc_register *ureg;
1178 struct circ_buf *xmit;
1d26c9ff
QL		 1179 struct sirfsoc_fifo_status *ufifo_st;
1180 int max_pio_cnt;
0f17e3b4
QL		 1181
1182 sirfport = container_of(hrt, struct sirfsoc_uart_port, hrt);
1183 port = &sirfport->port;
1184 inserted = 0;
1185 tty = port->state->port.tty;
1186 ureg = &sirfport->uart_reg->uart_reg;
1187 xmit = &sirfport->rx_dma_items.xmit;
1d26c9ff
QL		 1188 ufifo_st = &sirfport->uart_reg->fifo_status;
1189
0f17e3b4 1190 dmaengine_tx_status(sirfport->rx_dma_chan,
1d26c9ff
QL		 1191 sirfport->rx_dma_items.cookie, &tx_state);
1192 if (SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue !=
1193 sirfport->rx_last_pos) {
1194 xmit->head = SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue;
1195 sirfport->rx_last_pos = xmit->head;
1196 sirfport->pio_fetch_cnt = 0;
1197 }
0f17e3b4
QL		 1198 count = CIRC_CNT_TO_END(xmit->head, xmit->tail,
1199 SIRFSOC_RX_DMA_BUF_SIZE);
1200 while (count > 0) {
1201 inserted = tty_insert_flip_string(tty->port,
1202 (const unsigned char *)&xmit->buf[xmit->tail], count);
1203 if (!inserted)
1204 goto next_hrt;
1205 port->icount.rx += inserted;
1206 xmit->tail = (xmit->tail + inserted) &
1207 (SIRFSOC_RX_DMA_BUF_SIZE - 1);
1208 count = CIRC_CNT_TO_END(xmit->head, xmit->tail,
1209 SIRFSOC_RX_DMA_BUF_SIZE);
1210 tty_flip_buffer_push(tty->port);
1211 }
1212 /*
1213 * if RX DMA buffer data have all push into tty buffer, and there is
1214 * only little data(less than a dma transfer unit) left in rxfifo,
1215 * fetch it out in pio mode and switch back to dma immediately
1216 */
1217 if (!inserted && !count &&
1218 ((rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
1d26c9ff
QL		 1219 SIRFUART_RX_FIFO_MASK) > sirfport->pio_fetch_cnt)) {
1220 dmaengine_pause(sirfport->rx_dma_chan);
0f17e3b4
QL		 1221 /* switch to pio mode */
1222 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
1223 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
1224 SIRFUART_IO_MODE);
1d26c9ff
QL		 1225 /*
1226 * UART controller SWH_DMA_IO register have CLEAR_RX_ADDR_EN
1227 * When found changing I/O to DMA mode, it clears
1228 * two low bits of read point;
1229 * USP have similar FRADDR_CLR_EN bit in USP_RX_DMA_IO_CTRL.
1230 * Fetch data out from rxfifo into DMA buffer in PIO mode,
1231 * while switch back to DMA mode, the data fetched will override
1232 * by DMA, as hardware have a strange behaviour:
1233 * after switch back to DMA mode, check rxfifo status it will
1234 * be the number PIO fetched, so record the fetched data count
1235 * to avoid the repeated fetch
1236 */
1237 max_pio_cnt = 3;
1238 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
1239 ufifo_st->ff_empty(port)) && max_pio_cnt--) {
1240 xmit->buf[xmit->head] =
1241 rd_regl(port, ureg->sirfsoc_rx_fifo_data);
1242 xmit->head = (xmit->head + 1) &
1243 (SIRFSOC_RX_DMA_BUF_SIZE - 1);
1244 sirfport->pio_fetch_cnt++;
0f17e3b4 1245 }
0f17e3b4
QL		 1246 /* switch back to dma mode */
1247 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
1248 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
1249 ~SIRFUART_IO_MODE);
1d26c9ff 1250 dmaengine_resume(sirfport->rx_dma_chan);
0f17e3b4
QL		 1251 }
1252next_hrt:
1253 hrtimer_forward_now(hrt, ns_to_ktime(sirfport->rx_period_time));
1254 return HRTIMER_RESTART;
1255}
1256
51949543 1257static const struct of_device_id sirfsoc_uart_ids[] = {
5df83111 1258 { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,},
057badd6 1259 { .compatible = "sirf,atlas7-uart", .data = &sirfsoc_uart},
5df83111 1260 { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp},
c1b7ac6f 1261 { .compatible = "sirf,atlas7-usp-uart", .data = &sirfsoc_usp},
5df83111
QL		 1262 {}
1263};
1264MODULE_DEVICE_TABLE(of, sirfsoc_uart_ids);
1265
ada1f443 1266static int sirfsoc_uart_probe(struct platform_device *pdev)
161e773c 1267{
af99c187 1268 struct device_node *np = pdev->dev.of_node;
161e773c
RW		 1269 struct sirfsoc_uart_port *sirfport;
1270 struct uart_port *port;
1271 struct resource *res;
1272 int ret;
9be16b38 1273 struct dma_slave_config slv_cfg = {
1d26c9ff 1274 .src_maxburst = 1,
9be16b38
QL		 1275 };
1276 struct dma_slave_config tx_slv_cfg = {
1277 .dst_maxburst = 2,
1278 };
5df83111 1279 const struct of_device_id *match;
161e773c 1280
af99c187 1281 match = of_match_node(sirfsoc_uart_ids, np);
a6ffe896
QL		 1282 sirfport = devm_kzalloc(&pdev->dev, sizeof(*sirfport), GFP_KERNEL);
1283 if (!sirfport) {
1284 ret = -ENOMEM;
161e773c
RW		 1285 goto err;
1286 }
af99c187 1287 sirfport->port.line = of_alias_get_id(np, "serial");
a6ffe896
QL		 1288 sirf_ports[sirfport->port.line] = sirfport;
1289 sirfport->port.iotype = UPIO_MEM;
1290 sirfport->port.flags = UPF_BOOT_AUTOCONF;
161e773c
RW		 1291 port = &sirfport->port;
1292 port->dev = &pdev->dev;
1293 port->private_data = sirfport;
5df83111 1294 sirfport->uart_reg = (struct sirfsoc_uart_register *)match->data;
161e773c 1295
af99c187 1296 sirfport->hw_flow_ctrl =
7f60830a
GU		 1297 of_property_read_bool(np, "uart-has-rtscts") ||
1298 of_property_read_bool(np, "sirf,uart-has-rtscts") /* deprecated */;
af99c187
GU		 1299 if (of_device_is_compatible(np, "sirf,prima2-uart") ||
1300 of_device_is_compatible(np, "sirf,atlas7-uart"))
5df83111 1301 sirfport->uart_reg->uart_type = SIRF_REAL_UART;
af99c187
GU		 1302 if (of_device_is_compatible(np, "sirf,prima2-usp-uart") ||
1303 of_device_is_compatible(np, "sirf,atlas7-usp-uart")) {
5df83111 1304 sirfport->uart_reg->uart_type = SIRF_USP_UART;
2eb5618d
QL		 1305 if (!sirfport->hw_flow_ctrl)
1306 goto usp_no_flow_control;
af99c187
GU		 1307 if (of_find_property(np, "cts-gpios", NULL))
1308 sirfport->cts_gpio =
1309 of_get_named_gpio(np, "cts-gpios", 0);
2eb5618d
QL		 1310 else
1311 sirfport->cts_gpio = -1;
af99c187
GU		 1312 if (of_find_property(np, "rts-gpios", NULL))
1313 sirfport->rts_gpio =
1314 of_get_named_gpio(np, "rts-gpios", 0);
2eb5618d
QL		 1315 else
1316 sirfport->rts_gpio = -1;
1317
1318 if ((!gpio_is_valid(sirfport->cts_gpio) ||
1319 !gpio_is_valid(sirfport->rts_gpio))) {
1320 ret = -EINVAL;
1321 dev_err(&pdev->dev,
67bc306c 1322 "Usp flow control must have cts and rts gpio");
2eb5618d
QL		 1323 goto err;
1324 }
1325 ret = devm_gpio_request(&pdev->dev, sirfport->cts_gpio,
67bc306c 1326 "usp-cts-gpio");
2eb5618d 1327 if (ret) {
67bc306c 1328 dev_err(&pdev->dev, "Unable request cts gpio");
2eb5618d
QL		 1329 goto err;
1330 }
1331 gpio_direction_input(sirfport->cts_gpio);
1332 ret = devm_gpio_request(&pdev->dev, sirfport->rts_gpio,
67bc306c 1333 "usp-rts-gpio");
2eb5618d 1334 if (ret) {
67bc306c 1335 dev_err(&pdev->dev, "Unable request rts gpio");
2eb5618d
QL		 1336 goto err;
1337 }
1338 gpio_direction_output(sirfport->rts_gpio, 1);
1339 }
1340usp_no_flow_control:
af99c187
GU		 1341 if (of_device_is_compatible(np, "sirf,atlas7-uart") ||
1342 of_device_is_compatible(np, "sirf,atlas7-usp-uart"))
057badd6 1343 sirfport->is_atlas7 = true;
909102db 1344
af99c187 1345 if (of_property_read_u32(np, "fifosize", &port->fifosize)) {
161e773c
RW		 1346 dev_err(&pdev->dev,
1347 "Unable to find fifosize in uart node.\n");
1348 ret = -EFAULT;
1349 goto err;
1350 }
1351
1352 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1353 if (res == NULL) {
1354 dev_err(&pdev->dev, "Insufficient resources.\n");
1355 ret = -EFAULT;
1356 goto err;
1357 }
1358 port->mapbase = res->start;
0f17e3b4
QL		 1359 port->membase = devm_ioremap(&pdev->dev,
1360 res->start, resource_size(res));
161e773c
RW		 1361 if (!port->membase) {
1362 dev_err(&pdev->dev, "Cannot remap resource.\n");
1363 ret = -ENOMEM;
1364 goto err;
1365 }
1366 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1367 if (res == NULL) {
1368 dev_err(&pdev->dev, "Insufficient resources.\n");
1369 ret = -EFAULT;
9250dd57 1370 goto err;
161e773c
RW		 1371 }
1372 port->irq = res->start;
1373
adeede73 1374 sirfport->clk = devm_clk_get(&pdev->dev, NULL);
ac4ce718
BS		 1375 if (IS_ERR(sirfport->clk)) {
1376 ret = PTR_ERR(sirfport->clk);
a343756e 1377 goto err;
ac4ce718 1378 }
ac4ce718
BS		 1379 port->uartclk = clk_get_rate(sirfport->clk);
1380
161e773c
RW		 1381 port->ops = &sirfsoc_uart_ops;
1382 spin_lock_init(&port->lock);
1383
1384 platform_set_drvdata(pdev, sirfport);
1385 ret = uart_add_one_port(&sirfsoc_uart_drv, port);
1386 if (ret != 0) {
1387 dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
adeede73 1388 goto err;
161e773c
RW		 1389 }
1390
9be16b38 1391 sirfport->rx_dma_chan = dma_request_slave_channel(port->dev, "rx");
0f17e3b4
QL		 1392 sirfport->rx_dma_items.xmit.buf =
1393 dma_alloc_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1394 &sirfport->rx_dma_items.dma_addr, GFP_KERNEL);
1395 if (!sirfport->rx_dma_items.xmit.buf) {
1396 dev_err(port->dev, "Uart alloc bufa failed\n");
1397 ret = -ENOMEM;
1398 goto alloc_coherent_err;
9be16b38 1399 }
0f17e3b4
QL		 1400 sirfport->rx_dma_items.xmit.head =
1401 sirfport->rx_dma_items.xmit.tail = 0;
9be16b38
QL		 1402 if (sirfport->rx_dma_chan)
1403 dmaengine_slave_config(sirfport->rx_dma_chan, &slv_cfg);
1404 sirfport->tx_dma_chan = dma_request_slave_channel(port->dev, "tx");
1405 if (sirfport->tx_dma_chan)
1406 dmaengine_slave_config(sirfport->tx_dma_chan, &tx_slv_cfg);
0f17e3b4
QL		 1407 if (sirfport->rx_dma_chan) {
1408 hrtimer_init(&sirfport->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1409 sirfport->hrt.function = sirfsoc_uart_rx_dma_hrtimer_callback;
1410 sirfport->is_hrt_enabled = false;
1411 }
161e773c 1412
9be16b38
QL		 1413 return 0;
1414alloc_coherent_err:
0f17e3b4
QL		 1415 dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1416 sirfport->rx_dma_items.xmit.buf,
1417 sirfport->rx_dma_items.dma_addr);
9be16b38 1418 dma_release_channel(sirfport->rx_dma_chan);
161e773c
RW		 1419err:
1420 return ret;
1421}
1422
1423static int sirfsoc_uart_remove(struct platform_device *pdev)
1424{
1425 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
1426 struct uart_port *port = &sirfport->port;
161e773c 1427 uart_remove_one_port(&sirfsoc_uart_drv, port);
9be16b38 1428 if (sirfport->rx_dma_chan) {
9be16b38
QL		 1429 dmaengine_terminate_all(sirfport->rx_dma_chan);
1430 dma_release_channel(sirfport->rx_dma_chan);
0f17e3b4
QL		 1431 dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1432 sirfport->rx_dma_items.xmit.buf,
1433 sirfport->rx_dma_items.dma_addr);
9be16b38
QL		 1434 }
1435 if (sirfport->tx_dma_chan) {
1436 dmaengine_terminate_all(sirfport->tx_dma_chan);
1437 dma_release_channel(sirfport->tx_dma_chan);
1438 }
161e773c
RW		 1439 return 0;
1440}
1441
99e626f5 1442#ifdef CONFIG_PM_SLEEP
161e773c 1443static int
99e626f5 1444sirfsoc_uart_suspend(struct device *pdev)
161e773c 1445{
99e626f5 1446 struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
161e773c
RW		 1447 struct uart_port *port = &sirfport->port;
1448 uart_suspend_port(&sirfsoc_uart_drv, port);
1449 return 0;
1450}
1451
99e626f5 1452static int sirfsoc_uart_resume(struct device *pdev)
161e773c 1453{
99e626f5 1454 struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
161e773c
RW		 1455 struct uart_port *port = &sirfport->port;
1456 uart_resume_port(&sirfsoc_uart_drv, port);
1457 return 0;
1458}
99e626f5
QL		 1459#endif
1460
1461static const struct dev_pm_ops sirfsoc_uart_pm_ops = {
1462 SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_uart_suspend, sirfsoc_uart_resume)
1463};
161e773c 1464
161e773c
RW		 1465static struct platform_driver sirfsoc_uart_driver = {
1466 .probe = sirfsoc_uart_probe,
2d47b716 1467 .remove = sirfsoc_uart_remove,
161e773c
RW		 1468 .driver = {
1469 .name = SIRFUART_PORT_NAME,
161e773c 1470 .of_match_table = sirfsoc_uart_ids,
99e626f5 1471 .pm = &sirfsoc_uart_pm_ops,
161e773c
RW		 1472 },
1473};
1474
1475static int __init sirfsoc_uart_init(void)
1476{
1477 int ret = 0;
1478
1479 ret = uart_register_driver(&sirfsoc_uart_drv);
1480 if (ret)
1481 goto out;
1482
1483 ret = platform_driver_register(&sirfsoc_uart_driver);
1484 if (ret)
1485 uart_unregister_driver(&sirfsoc_uart_drv);
1486out:
1487 return ret;
1488}
1489module_init(sirfsoc_uart_init);
1490
1491static void __exit sirfsoc_uart_exit(void)
1492{
1493 platform_driver_unregister(&sirfsoc_uart_driver);
1494 uart_unregister_driver(&sirfsoc_uart_drv);
1495}
1496module_exit(sirfsoc_uart_exit);
1497
1498MODULE_LICENSE("GPL v2");
1499MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
1500MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");
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