[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / sirfsoc_uart.h

// SPDX-License-Identifier: GPL-2.0+
/*
 * Drivers for CSR SiRFprimaII onboard UARTs.
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */
#include <linux/bitops.h>
#include <linux/log2.h>
#include <linux/hrtimer.h>
struct sirfsoc_uart_param {
	const char *uart_name;
	const char *port_name;
};

struct sirfsoc_register {
	/* hardware uart specific */
	u32 sirfsoc_line_ctrl;
	u32 sirfsoc_divisor;
	/* uart - usp common */
	u32 sirfsoc_tx_rx_en;
	u32 sirfsoc_int_en_reg;
	u32 sirfsoc_int_st_reg;
	u32 sirfsoc_int_en_clr_reg;
	u32 sirfsoc_tx_dma_io_ctrl;
	u32 sirfsoc_tx_dma_io_len;
	u32 sirfsoc_tx_fifo_ctrl;
	u32 sirfsoc_tx_fifo_level_chk;
	u32 sirfsoc_tx_fifo_op;
	u32 sirfsoc_tx_fifo_status;
	u32 sirfsoc_tx_fifo_data;
	u32 sirfsoc_rx_dma_io_ctrl;
	u32 sirfsoc_rx_dma_io_len;
	u32 sirfsoc_rx_fifo_ctrl;
	u32 sirfsoc_rx_fifo_level_chk;
	u32 sirfsoc_rx_fifo_op;
	u32 sirfsoc_rx_fifo_status;
	u32 sirfsoc_rx_fifo_data;
	u32 sirfsoc_afc_ctrl;
	u32 sirfsoc_swh_dma_io;
	/* hardware usp specific */
	u32 sirfsoc_mode1;
	u32 sirfsoc_mode2;
	u32 sirfsoc_tx_frame_ctrl;
	u32 sirfsoc_rx_frame_ctrl;
	u32 sirfsoc_async_param_reg;
};

typedef u32 (*fifo_full_mask)(struct uart_port *port);
typedef u32 (*fifo_empty_mask)(struct uart_port *port);

struct sirfsoc_fifo_status {
	fifo_full_mask ff_full;
	fifo_empty_mask ff_empty;
};

struct sirfsoc_int_en {
	u32 sirfsoc_rx_done_en;
	u32 sirfsoc_tx_done_en;
	u32 sirfsoc_rx_oflow_en;
	u32 sirfsoc_tx_allout_en;
	u32 sirfsoc_rx_io_dma_en;
	u32 sirfsoc_tx_io_dma_en;
	u32 sirfsoc_rxfifo_full_en;
	u32 sirfsoc_txfifo_empty_en;
	u32 sirfsoc_rxfifo_thd_en;
	u32 sirfsoc_txfifo_thd_en;
	u32 sirfsoc_frm_err_en;
	u32 sirfsoc_rxd_brk_en;
	u32 sirfsoc_rx_timeout_en;
	u32 sirfsoc_parity_err_en;
	u32 sirfsoc_cts_en;
	u32 sirfsoc_rts_en;
};

struct sirfsoc_int_status {
	u32 sirfsoc_rx_done;
	u32 sirfsoc_tx_done;
	u32 sirfsoc_rx_oflow;
	u32 sirfsoc_tx_allout;
	u32 sirfsoc_rx_io_dma;
	u32 sirfsoc_tx_io_dma;
	u32 sirfsoc_rxfifo_full;
	u32 sirfsoc_txfifo_empty;
	u32 sirfsoc_rxfifo_thd;
	u32 sirfsoc_txfifo_thd;
	u32 sirfsoc_frm_err;
	u32 sirfsoc_rxd_brk;
	u32 sirfsoc_rx_timeout;
	u32 sirfsoc_parity_err;
	u32 sirfsoc_cts;
	u32 sirfsoc_rts;
};

enum sirfsoc_uart_type {
	SIRF_REAL_UART,
	SIRF_USP_UART,
};

struct sirfsoc_uart_register {
	struct sirfsoc_register uart_reg;
	struct sirfsoc_int_en uart_int_en;
	struct sirfsoc_int_status uart_int_st;
	struct sirfsoc_fifo_status fifo_status;
	struct sirfsoc_uart_param uart_param;
	enum sirfsoc_uart_type uart_type;
};

static u32 uart_usp_ff_full_mask(struct uart_port *port)
{
	u32 full_bit;

	full_bit = ilog2(port->fifosize);
	return (1 << full_bit);
}

static u32 uart_usp_ff_empty_mask(struct uart_port *port)
{
	u32 empty_bit;

	empty_bit = ilog2(port->fifosize) + 1;
	return (1 << empty_bit);
}
struct sirfsoc_uart_register sirfsoc_usp = {
	.uart_reg = {
		.sirfsoc_mode1		= 0x0000,
		.sirfsoc_mode2		= 0x0004,
		.sirfsoc_tx_frame_ctrl	= 0x0008,
		.sirfsoc_rx_frame_ctrl	= 0x000c,
		.sirfsoc_tx_rx_en	= 0x0010,
		.sirfsoc_int_en_reg	= 0x0014,
		.sirfsoc_int_st_reg	= 0x0018,
		.sirfsoc_async_param_reg = 0x0024,
		.sirfsoc_tx_dma_io_ctrl	= 0x0100,
		.sirfsoc_tx_dma_io_len	= 0x0104,
		.sirfsoc_tx_fifo_ctrl	= 0x0108,
		.sirfsoc_tx_fifo_level_chk = 0x010c,
		.sirfsoc_tx_fifo_op	= 0x0110,
		.sirfsoc_tx_fifo_status	= 0x0114,
		.sirfsoc_tx_fifo_data	= 0x0118,
		.sirfsoc_rx_dma_io_ctrl	= 0x0120,
		.sirfsoc_rx_dma_io_len	= 0x0124,
		.sirfsoc_rx_fifo_ctrl	= 0x0128,
		.sirfsoc_rx_fifo_level_chk = 0x012c,
		.sirfsoc_rx_fifo_op	= 0x0130,
		.sirfsoc_rx_fifo_status	= 0x0134,
		.sirfsoc_rx_fifo_data	= 0x0138,
		.sirfsoc_int_en_clr_reg = 0x140,
	},
	.uart_int_en = {
		.sirfsoc_rx_done_en	= BIT(0),
		.sirfsoc_tx_done_en	= BIT(1),
		.sirfsoc_rx_oflow_en	= BIT(2),
		.sirfsoc_tx_allout_en	= BIT(3),
		.sirfsoc_rx_io_dma_en	= BIT(4),
		.sirfsoc_tx_io_dma_en	= BIT(5),
		.sirfsoc_rxfifo_full_en	= BIT(6),
		.sirfsoc_txfifo_empty_en = BIT(7),
		.sirfsoc_rxfifo_thd_en	= BIT(8),
		.sirfsoc_txfifo_thd_en	= BIT(9),
		.sirfsoc_frm_err_en	= BIT(10),
		.sirfsoc_rx_timeout_en	= BIT(11),
		.sirfsoc_rxd_brk_en	= BIT(15),
	},
	.uart_int_st = {
		.sirfsoc_rx_done	= BIT(0),
		.sirfsoc_tx_done	= BIT(1),
		.sirfsoc_rx_oflow	= BIT(2),
		.sirfsoc_tx_allout	= BIT(3),
		.sirfsoc_rx_io_dma	= BIT(4),
		.sirfsoc_tx_io_dma	= BIT(5),
		.sirfsoc_rxfifo_full	= BIT(6),
		.sirfsoc_txfifo_empty	= BIT(7),
		.sirfsoc_rxfifo_thd	= BIT(8),
		.sirfsoc_txfifo_thd	= BIT(9),
		.sirfsoc_frm_err	= BIT(10),
		.sirfsoc_rx_timeout	= BIT(11),
		.sirfsoc_rxd_brk	= BIT(15),
	},
	.fifo_status = {
		.ff_full		= uart_usp_ff_full_mask,
		.ff_empty		= uart_usp_ff_empty_mask,
	},
	.uart_param = {
		.uart_name = "ttySiRF",
		.port_name = "sirfsoc-uart",
	},
};

struct sirfsoc_uart_register sirfsoc_uart = {
	.uart_reg = {
		.sirfsoc_line_ctrl	= 0x0040,
		.sirfsoc_tx_rx_en	= 0x004c,
		.sirfsoc_divisor	= 0x0050,
		.sirfsoc_int_en_reg	= 0x0054,
		.sirfsoc_int_st_reg	= 0x0058,
		.sirfsoc_int_en_clr_reg	= 0x0060,
		.sirfsoc_tx_dma_io_ctrl	= 0x0100,
		.sirfsoc_tx_dma_io_len	= 0x0104,
		.sirfsoc_tx_fifo_ctrl	= 0x0108,
		.sirfsoc_tx_fifo_level_chk = 0x010c,
		.sirfsoc_tx_fifo_op	= 0x0110,
		.sirfsoc_tx_fifo_status	= 0x0114,
		.sirfsoc_tx_fifo_data	= 0x0118,
		.sirfsoc_rx_dma_io_ctrl	= 0x0120,
		.sirfsoc_rx_dma_io_len	= 0x0124,
		.sirfsoc_rx_fifo_ctrl	= 0x0128,
		.sirfsoc_rx_fifo_level_chk = 0x012c,
		.sirfsoc_rx_fifo_op	= 0x0130,
		.sirfsoc_rx_fifo_status	= 0x0134,
		.sirfsoc_rx_fifo_data	= 0x0138,
		.sirfsoc_afc_ctrl	= 0x0140,
		.sirfsoc_swh_dma_io	= 0x0148,
	},
	.uart_int_en = {
		.sirfsoc_rx_done_en	= BIT(0),
		.sirfsoc_tx_done_en	= BIT(1),
		.sirfsoc_rx_oflow_en	= BIT(2),
		.sirfsoc_tx_allout_en	= BIT(3),
		.sirfsoc_rx_io_dma_en	= BIT(4),
		.sirfsoc_tx_io_dma_en	= BIT(5),
		.sirfsoc_rxfifo_full_en	= BIT(6),
		.sirfsoc_txfifo_empty_en = BIT(7),
		.sirfsoc_rxfifo_thd_en	= BIT(8),
		.sirfsoc_txfifo_thd_en	= BIT(9),
		.sirfsoc_frm_err_en	= BIT(10),
		.sirfsoc_rxd_brk_en	= BIT(11),
		.sirfsoc_rx_timeout_en	= BIT(12),
		.sirfsoc_parity_err_en	= BIT(13),
		.sirfsoc_cts_en		= BIT(14),
		.sirfsoc_rts_en		= BIT(15),
	},
	.uart_int_st = {
		.sirfsoc_rx_done	= BIT(0),
		.sirfsoc_tx_done	= BIT(1),
		.sirfsoc_rx_oflow	= BIT(2),
		.sirfsoc_tx_allout	= BIT(3),
		.sirfsoc_rx_io_dma	= BIT(4),
		.sirfsoc_tx_io_dma	= BIT(5),
		.sirfsoc_rxfifo_full	= BIT(6),
		.sirfsoc_txfifo_empty	= BIT(7),
		.sirfsoc_rxfifo_thd	= BIT(8),
		.sirfsoc_txfifo_thd	= BIT(9),
		.sirfsoc_frm_err	= BIT(10),
		.sirfsoc_rxd_brk	= BIT(11),
		.sirfsoc_rx_timeout	= BIT(12),
		.sirfsoc_parity_err	= BIT(13),
		.sirfsoc_cts		= BIT(14),
		.sirfsoc_rts		= BIT(15),
	},
	.fifo_status = {
		.ff_full		= uart_usp_ff_full_mask,
		.ff_empty		= uart_usp_ff_empty_mask,
	},
	.uart_param = {
		.uart_name = "ttySiRF",
		.port_name = "sirfsoc_uart",
	},
};
/* uart io ctrl */
#define SIRFUART_DATA_BIT_LEN_MASK		0x3
#define SIRFUART_DATA_BIT_LEN_5			BIT(0)
#define SIRFUART_DATA_BIT_LEN_6			1
#define SIRFUART_DATA_BIT_LEN_7			2
#define SIRFUART_DATA_BIT_LEN_8			3
#define SIRFUART_STOP_BIT_LEN_1			0
#define SIRFUART_STOP_BIT_LEN_2			BIT(2)
#define SIRFUART_PARITY_EN			BIT(3)
#define SIRFUART_EVEN_BIT			BIT(4)
#define SIRFUART_STICK_BIT_MASK			(7 << 3)
#define SIRFUART_STICK_BIT_NONE			(0 << 3)
#define SIRFUART_STICK_BIT_EVEN			BIT(3)
#define SIRFUART_STICK_BIT_ODD			(3 << 3)
#define SIRFUART_STICK_BIT_MARK			(5 << 3)
#define SIRFUART_STICK_BIT_SPACE		(7 << 3)
#define SIRFUART_SET_BREAK			BIT(6)
#define SIRFUART_LOOP_BACK			BIT(7)
#define SIRFUART_PARITY_MASK			(7 << 3)
#define SIRFUART_DUMMY_READ			BIT(16)
#define SIRFUART_AFC_CTRL_RX_THD		0x70
#define SIRFUART_AFC_RX_EN			BIT(8)
#define SIRFUART_AFC_TX_EN			BIT(9)
#define SIRFUART_AFC_CTS_CTRL			BIT(10)
#define SIRFUART_AFC_RTS_CTRL			BIT(11)
#define	SIRFUART_AFC_CTS_STATUS			BIT(12)
#define	SIRFUART_AFC_RTS_STATUS			BIT(13)
/* UART FIFO Register */
#define SIRFUART_FIFO_STOP			0x0
#define SIRFUART_FIFO_RESET			BIT(0)
#define SIRFUART_FIFO_START			BIT(1)

#define SIRFUART_RX_EN				BIT(0)
#define SIRFUART_TX_EN				BIT(1)

#define SIRFUART_IO_MODE			BIT(0)
#define SIRFUART_DMA_MODE			0x0
#define SIRFUART_RX_DMA_FLUSH			0x4

#define SIRFUART_CLEAR_RX_ADDR_EN		0x2
/* Baud Rate Calculation */
#define SIRF_USP_MIN_SAMPLE_DIV			0x1
#define SIRF_MIN_SAMPLE_DIV			0xf
#define SIRF_MAX_SAMPLE_DIV			0x3f
#define SIRF_IOCLK_DIV_MAX			0xffff
#define SIRF_SAMPLE_DIV_SHIFT			16
#define SIRF_IOCLK_DIV_MASK			0xffff
#define SIRF_SAMPLE_DIV_MASK			0x3f0000
#define SIRF_BAUD_RATE_SUPPORT_NR		18

/* USP SPEC */
#define SIRFSOC_USP_ENDIAN_CTRL_LSBF		BIT(4)
#define SIRFSOC_USP_EN				BIT(5)
#define SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET	0
#define SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET	8
#define SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK	0x3ff
#define SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET	21
#define SIRFSOC_USP_TX_DATA_LEN_OFFSET		0
#define SIRFSOC_USP_TX_SYNC_LEN_OFFSET		8
#define SIRFSOC_USP_TX_FRAME_LEN_OFFSET		16
#define SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET	24
#define SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET	30
#define SIRFSOC_USP_RX_DATA_LEN_OFFSET		0
#define SIRFSOC_USP_RX_FRAME_LEN_OFFSET		8
#define SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET	16
#define SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET	24
#define SIRFSOC_USP_ASYNC_DIV2_MASK		0x3f
#define SIRFSOC_USP_ASYNC_DIV2_OFFSET		16
#define SIRFSOC_USP_LOOP_BACK_CTRL		BIT(2)
#define SIRFSOC_USP_FRADDR_CLR_EN		BIT(1)
/* USP-UART Common */
#define SIRFSOC_UART_RX_TIMEOUT(br, to)	(((br) * (((to) + 999) / 1000)) / 1000)
#define SIRFUART_RECV_TIMEOUT_VALUE(x)	\
				(((x) > 0xFFFF) ? 0xFFFF : ((x) & 0xFFFF))
#define SIRFUART_USP_RECV_TIMEOUT(x)	(x & 0xFFFF)
#define SIRFUART_UART_RECV_TIMEOUT(x)	((x & 0xFFFF) << 16)

#define SIRFUART_FIFO_THD(port)		(port->fifosize >> 1)
#define SIRFUART_ERR_INT_STAT(unit_st, uart_type)			\
				(uint_st->sirfsoc_rx_oflow |		\
				uint_st->sirfsoc_frm_err |		\
				uint_st->sirfsoc_rxd_brk |		\
				((uart_type != SIRF_REAL_UART) ? \
				 0 : uint_st->sirfsoc_parity_err))
#define SIRFUART_RX_IO_INT_EN(uint_en, uart_type)			\
				(uint_en->sirfsoc_rx_done_en |\
				 uint_en->sirfsoc_rxfifo_thd_en |\
				 uint_en->sirfsoc_rxfifo_full_en |\
				 uint_en->sirfsoc_frm_err_en |\
				 uint_en->sirfsoc_rx_oflow_en |\
				 uint_en->sirfsoc_rxd_brk_en |\
				((uart_type != SIRF_REAL_UART) ? \
				 0 : uint_en->sirfsoc_parity_err_en))
#define SIRFUART_RX_IO_INT_ST(uint_st)				\
				(uint_st->sirfsoc_rxfifo_thd |\
				 uint_st->sirfsoc_rxfifo_full|\
				 uint_st->sirfsoc_rx_done |\
				 uint_st->sirfsoc_rx_timeout)
#define SIRFUART_CTS_INT_ST(uint_st)	(uint_st->sirfsoc_cts)
#define SIRFUART_RX_DMA_INT_EN(uint_en, uart_type)		\
				(uint_en->sirfsoc_frm_err_en |\
				 uint_en->sirfsoc_rx_oflow_en |\
				 uint_en->sirfsoc_rxd_brk_en |\
				((uart_type != SIRF_REAL_UART) ? \
				 0 : uint_en->sirfsoc_parity_err_en))
/* Generic Definitions */
#define SIRFSOC_UART_NAME			"ttySiRF"
#define SIRFSOC_UART_MAJOR			0
#define SIRFSOC_UART_MINOR			0
#define SIRFUART_PORT_NAME			"sirfsoc-uart"
#define SIRFUART_MAP_SIZE			0x200
#define SIRFSOC_UART_NR				11
#define SIRFSOC_PORT_TYPE			0xa5

/* Uart Common Use Macro*/
#define SIRFSOC_RX_DMA_BUF_SIZE		(1024 * 32)
#define BYTES_TO_ALIGN(dma_addr)	((unsigned long)(dma_addr) & 0x3)
/* Uart Fifo Level Chk */
#define SIRFUART_TX_FIFO_SC_OFFSET	0
#define SIRFUART_TX_FIFO_LC_OFFSET	10
#define SIRFUART_TX_FIFO_HC_OFFSET	20
#define SIRFUART_TX_FIFO_CHK_SC(line, value) ((((line) == 1) ? (value & 0x3) :\
				(value & 0x1f)) << SIRFUART_TX_FIFO_SC_OFFSET)
#define SIRFUART_TX_FIFO_CHK_LC(line, value) ((((line) == 1) ? (value & 0x3) :\
				(value & 0x1f)) << SIRFUART_TX_FIFO_LC_OFFSET)
#define SIRFUART_TX_FIFO_CHK_HC(line, value) ((((line) == 1) ? (value & 0x3) :\
				(value & 0x1f)) << SIRFUART_TX_FIFO_HC_OFFSET)

#define SIRFUART_RX_FIFO_CHK_SC SIRFUART_TX_FIFO_CHK_SC
#define	SIRFUART_RX_FIFO_CHK_LC SIRFUART_TX_FIFO_CHK_LC
#define SIRFUART_RX_FIFO_CHK_HC SIRFUART_TX_FIFO_CHK_HC
#define SIRFUART_RX_FIFO_MASK 0x7f
/* Indicate how many buffers used */

/* For Fast Baud Rate Calculation */
struct sirfsoc_baudrate_to_regv {
	unsigned int baud_rate;
	unsigned int reg_val;
};

enum sirfsoc_tx_state {
	TX_DMA_IDLE,
	TX_DMA_RUNNING,
	TX_DMA_PAUSE,
};

struct sirfsoc_rx_buffer {
	struct circ_buf			xmit;
	dma_cookie_t			cookie;
	struct dma_async_tx_descriptor	*desc;
	dma_addr_t			dma_addr;
};

struct sirfsoc_uart_port {
	bool				hw_flow_ctrl;
	bool				ms_enabled;

	struct uart_port		port;
	struct clk			*clk;
	/* for SiRFatlas7, there are SET/CLR for UART_INT_EN */
	bool				is_atlas7;
	struct sirfsoc_uart_register	*uart_reg;
	struct dma_chan			*rx_dma_chan;
	struct dma_chan			*tx_dma_chan;
	dma_addr_t			tx_dma_addr;
	struct dma_async_tx_descriptor	*tx_dma_desc;
	unsigned long			transfer_size;
	enum sirfsoc_tx_state		tx_dma_state;
	unsigned int			cts_gpio;
	unsigned int			rts_gpio;

	struct sirfsoc_rx_buffer	rx_dma_items;
	struct hrtimer			hrt;
	bool				is_hrt_enabled;
	unsigned long			rx_period_time;
	unsigned long			rx_last_pos;
	unsigned long			pio_fetch_cnt;
};

/* Register Access Control */
#define portaddr(port, reg)		((port)->membase + (reg))
#define rd_regl(port, reg)		(__raw_readl(portaddr(port, reg)))
#define wr_regl(port, reg, val)		__raw_writel(val, portaddr(port, reg))

/* UART Port Mask */
#define SIRFUART_FIFOLEVEL_MASK(port)	((port->fifosize - 1) & 0xFFF)
#define SIRFUART_FIFOFULL_MASK(port)	(port->fifosize & 0xFFF)
#define SIRFUART_FIFOEMPTY_MASK(port)	((port->fifosize & 0xFFF) << 1)
Commit	Line	Data
e3b3d0f5	1	// SPDX-License-Identifier: GPL-2.0+
161e773c RW	2	/*
	3	* Drivers for CSR SiRFprimaII onboard UARTs.
	4	*
	5	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
	6	*
	7	* Licensed under GPLv2 or later.
	8	*/
	9	#include <linux/bitops.h>
cb4595a2	10	#include <linux/log2.h>
0f17e3b4	11	#include <linux/hrtimer.h>
5df83111 QL	12	struct sirfsoc_uart_param {
	13	const char *uart_name;
	14	const char *port_name;
5df83111 QL	15	};
	16
	17	struct sirfsoc_register {
	18	/* hardware uart specific */
	19	u32 sirfsoc_line_ctrl;
	20	u32 sirfsoc_divisor;
	21	/* uart - usp common */
	22	u32 sirfsoc_tx_rx_en;
	23	u32 sirfsoc_int_en_reg;
	24	u32 sirfsoc_int_st_reg;
c1b7ac6f	25	u32 sirfsoc_int_en_clr_reg;
5df83111 QL	26	u32 sirfsoc_tx_dma_io_ctrl;
	27	u32 sirfsoc_tx_dma_io_len;
	28	u32 sirfsoc_tx_fifo_ctrl;
	29	u32 sirfsoc_tx_fifo_level_chk;
	30	u32 sirfsoc_tx_fifo_op;
	31	u32 sirfsoc_tx_fifo_status;
	32	u32 sirfsoc_tx_fifo_data;
	33	u32 sirfsoc_rx_dma_io_ctrl;
	34	u32 sirfsoc_rx_dma_io_len;
	35	u32 sirfsoc_rx_fifo_ctrl;
	36	u32 sirfsoc_rx_fifo_level_chk;
	37	u32 sirfsoc_rx_fifo_op;
	38	u32 sirfsoc_rx_fifo_status;
	39	u32 sirfsoc_rx_fifo_data;
	40	u32 sirfsoc_afc_ctrl;
	41	u32 sirfsoc_swh_dma_io;
	42	/* hardware usp specific */
	43	u32 sirfsoc_mode1;
	44	u32 sirfsoc_mode2;
	45	u32 sirfsoc_tx_frame_ctrl;
	46	u32 sirfsoc_rx_frame_ctrl;
	47	u32 sirfsoc_async_param_reg;
	48	};
	49
cb4595a2 QL	50	typedef u32 (fifo_full_mask)(struct uart_port port);
cb4595a2 QL	51	typedef u32 (fifo_empty_mask)(struct uart_port port);
5df83111 QL	52
	53	struct sirfsoc_fifo_status {
	54	fifo_full_mask ff_full;
	55	fifo_empty_mask ff_empty;
	56	};
	57
	58	struct sirfsoc_int_en {
	59	u32 sirfsoc_rx_done_en;
	60	u32 sirfsoc_tx_done_en;
	61	u32 sirfsoc_rx_oflow_en;
	62	u32 sirfsoc_tx_allout_en;
	63	u32 sirfsoc_rx_io_dma_en;
	64	u32 sirfsoc_tx_io_dma_en;
	65	u32 sirfsoc_rxfifo_full_en;
	66	u32 sirfsoc_txfifo_empty_en;
	67	u32 sirfsoc_rxfifo_thd_en;
	68	u32 sirfsoc_txfifo_thd_en;
	69	u32 sirfsoc_frm_err_en;
	70	u32 sirfsoc_rxd_brk_en;
	71	u32 sirfsoc_rx_timeout_en;
	72	u32 sirfsoc_parity_err_en;
	73	u32 sirfsoc_cts_en;
	74	u32 sirfsoc_rts_en;
	75	};
	76
	77	struct sirfsoc_int_status {
	78	u32 sirfsoc_rx_done;
	79	u32 sirfsoc_tx_done;
	80	u32 sirfsoc_rx_oflow;
	81	u32 sirfsoc_tx_allout;
	82	u32 sirfsoc_rx_io_dma;
	83	u32 sirfsoc_tx_io_dma;
	84	u32 sirfsoc_rxfifo_full;
	85	u32 sirfsoc_txfifo_empty;
	86	u32 sirfsoc_rxfifo_thd;
	87	u32 sirfsoc_txfifo_thd;
	88	u32 sirfsoc_frm_err;
	89	u32 sirfsoc_rxd_brk;
	90	u32 sirfsoc_rx_timeout;
	91	u32 sirfsoc_parity_err;
	92	u32 sirfsoc_cts;
	93	u32 sirfsoc_rts;
	94	};
	95
	96	enum sirfsoc_uart_type {
	97	SIRF_REAL_UART,
	98	SIRF_USP_UART,
	99	};
	100
	101	struct sirfsoc_uart_register {
	102	struct sirfsoc_register uart_reg;
	103	struct sirfsoc_int_en uart_int_en;
	104	struct sirfsoc_int_status uart_int_st;
	105	struct sirfsoc_fifo_status fifo_status;
	106	struct sirfsoc_uart_param uart_param;
	107	enum sirfsoc_uart_type uart_type;
	108	};
161e773c	109
3548e45c	110	static u32 uart_usp_ff_full_mask(struct uart_port *port)
5df83111	111	{
cb4595a2 QL	112	u32 full_bit;
	113
	114	full_bit = ilog2(port->fifosize);
	115	return (1 << full_bit);
5df83111	116	}
cb4595a2	117
3548e45c	118	static u32 uart_usp_ff_empty_mask(struct uart_port *port)
5df83111	119	{
cb4595a2 QL	120	u32 empty_bit;
cb4595a2 QL	121
86459b0e	122	empty_bit = ilog2(port->fifosize) + 1;
cb4595a2	123	return (1 << empty_bit);
5df83111 QL	124	}
	125	struct sirfsoc_uart_register sirfsoc_usp = {
	126	.uart_reg = {
	127	.sirfsoc_mode1 = 0x0000,
	128	.sirfsoc_mode2 = 0x0004,
	129	.sirfsoc_tx_frame_ctrl = 0x0008,
	130	.sirfsoc_rx_frame_ctrl = 0x000c,
	131	.sirfsoc_tx_rx_en = 0x0010,
	132	.sirfsoc_int_en_reg = 0x0014,
	133	.sirfsoc_int_st_reg = 0x0018,
	134	.sirfsoc_async_param_reg = 0x0024,
	135	.sirfsoc_tx_dma_io_ctrl = 0x0100,
	136	.sirfsoc_tx_dma_io_len = 0x0104,
	137	.sirfsoc_tx_fifo_ctrl = 0x0108,
	138	.sirfsoc_tx_fifo_level_chk = 0x010c,
	139	.sirfsoc_tx_fifo_op = 0x0110,
	140	.sirfsoc_tx_fifo_status = 0x0114,
	141	.sirfsoc_tx_fifo_data = 0x0118,
	142	.sirfsoc_rx_dma_io_ctrl = 0x0120,
	143	.sirfsoc_rx_dma_io_len = 0x0124,
	144	.sirfsoc_rx_fifo_ctrl = 0x0128,
	145	.sirfsoc_rx_fifo_level_chk = 0x012c,
	146	.sirfsoc_rx_fifo_op = 0x0130,
	147	.sirfsoc_rx_fifo_status = 0x0134,
	148	.sirfsoc_rx_fifo_data = 0x0138,
c1b7ac6f	149	.sirfsoc_int_en_clr_reg = 0x140,
5df83111 QL	150	},
	151	.uart_int_en = {
	152	.sirfsoc_rx_done_en = BIT(0),
	153	.sirfsoc_tx_done_en = BIT(1),
	154	.sirfsoc_rx_oflow_en = BIT(2),
	155	.sirfsoc_tx_allout_en = BIT(3),
	156	.sirfsoc_rx_io_dma_en = BIT(4),
	157	.sirfsoc_tx_io_dma_en = BIT(5),
	158	.sirfsoc_rxfifo_full_en = BIT(6),
	159	.sirfsoc_txfifo_empty_en = BIT(7),
	160	.sirfsoc_rxfifo_thd_en = BIT(8),
	161	.sirfsoc_txfifo_thd_en = BIT(9),
	162	.sirfsoc_frm_err_en = BIT(10),
	163	.sirfsoc_rx_timeout_en = BIT(11),
	164	.sirfsoc_rxd_brk_en = BIT(15),
	165	},
	166	.uart_int_st = {
	167	.sirfsoc_rx_done = BIT(0),
	168	.sirfsoc_tx_done = BIT(1),
	169	.sirfsoc_rx_oflow = BIT(2),
	170	.sirfsoc_tx_allout = BIT(3),
	171	.sirfsoc_rx_io_dma = BIT(4),
	172	.sirfsoc_tx_io_dma = BIT(5),
	173	.sirfsoc_rxfifo_full = BIT(6),
	174	.sirfsoc_txfifo_empty = BIT(7),
	175	.sirfsoc_rxfifo_thd = BIT(8),
	176	.sirfsoc_txfifo_thd = BIT(9),
	177	.sirfsoc_frm_err = BIT(10),
	178	.sirfsoc_rx_timeout = BIT(11),
	179	.sirfsoc_rxd_brk = BIT(15),
	180	},
	181	.fifo_status = {
cb4595a2 QL	182	.ff_full = uart_usp_ff_full_mask,
cb4595a2 QL	183	.ff_empty = uart_usp_ff_empty_mask,
5df83111 QL	184	},
	185	.uart_param = {
	186	.uart_name = "ttySiRF",
	187	.port_name = "sirfsoc-uart",
5df83111 QL	188	},
	189	};
	190
	191	struct sirfsoc_uart_register sirfsoc_uart = {
	192	.uart_reg = {
	193	.sirfsoc_line_ctrl = 0x0040,
	194	.sirfsoc_tx_rx_en = 0x004c,
	195	.sirfsoc_divisor = 0x0050,
	196	.sirfsoc_int_en_reg = 0x0054,
	197	.sirfsoc_int_st_reg = 0x0058,
c1b7ac6f	198	.sirfsoc_int_en_clr_reg = 0x0060,
5df83111 QL	199	.sirfsoc_tx_dma_io_ctrl = 0x0100,
	200	.sirfsoc_tx_dma_io_len = 0x0104,
	201	.sirfsoc_tx_fifo_ctrl = 0x0108,
	202	.sirfsoc_tx_fifo_level_chk = 0x010c,
	203	.sirfsoc_tx_fifo_op = 0x0110,
	204	.sirfsoc_tx_fifo_status = 0x0114,
	205	.sirfsoc_tx_fifo_data = 0x0118,
	206	.sirfsoc_rx_dma_io_ctrl = 0x0120,
	207	.sirfsoc_rx_dma_io_len = 0x0124,
	208	.sirfsoc_rx_fifo_ctrl = 0x0128,
	209	.sirfsoc_rx_fifo_level_chk = 0x012c,
	210	.sirfsoc_rx_fifo_op = 0x0130,
	211	.sirfsoc_rx_fifo_status = 0x0134,
	212	.sirfsoc_rx_fifo_data = 0x0138,
	213	.sirfsoc_afc_ctrl = 0x0140,
	214	.sirfsoc_swh_dma_io = 0x0148,
	215	},
	216	.uart_int_en = {
	217	.sirfsoc_rx_done_en = BIT(0),
	218	.sirfsoc_tx_done_en = BIT(1),
	219	.sirfsoc_rx_oflow_en = BIT(2),
	220	.sirfsoc_tx_allout_en = BIT(3),
	221	.sirfsoc_rx_io_dma_en = BIT(4),
	222	.sirfsoc_tx_io_dma_en = BIT(5),
	223	.sirfsoc_rxfifo_full_en = BIT(6),
	224	.sirfsoc_txfifo_empty_en = BIT(7),
	225	.sirfsoc_rxfifo_thd_en = BIT(8),
	226	.sirfsoc_txfifo_thd_en = BIT(9),
	227	.sirfsoc_frm_err_en = BIT(10),
	228	.sirfsoc_rxd_brk_en = BIT(11),
	229	.sirfsoc_rx_timeout_en = BIT(12),
	230	.sirfsoc_parity_err_en = BIT(13),
	231	.sirfsoc_cts_en = BIT(14),
	232	.sirfsoc_rts_en = BIT(15),
	233	},
	234	.uart_int_st = {
	235	.sirfsoc_rx_done = BIT(0),
	236	.sirfsoc_tx_done = BIT(1),
	237	.sirfsoc_rx_oflow = BIT(2),
	238	.sirfsoc_tx_allout = BIT(3),
	239	.sirfsoc_rx_io_dma = BIT(4),
	240	.sirfsoc_tx_io_dma = BIT(5),
	241	.sirfsoc_rxfifo_full = BIT(6),
	242	.sirfsoc_txfifo_empty = BIT(7),
	243	.sirfsoc_rxfifo_thd = BIT(8),
	244	.sirfsoc_txfifo_thd = BIT(9),
	245	.sirfsoc_frm_err = BIT(10),
	246	.sirfsoc_rxd_brk = BIT(11),
	247	.sirfsoc_rx_timeout = BIT(12),
	248	.sirfsoc_parity_err = BIT(13),
	249	.sirfsoc_cts = BIT(14),
	250	.sirfsoc_rts = BIT(15),
	251	},
	252	.fifo_status = {
cb4595a2 QL	253	.ff_full = uart_usp_ff_full_mask,
cb4595a2 QL	254	.ff_empty = uart_usp_ff_empty_mask,
5df83111 QL	255	},
	256	.uart_param = {
	257	.uart_name = "ttySiRF",
	258	.port_name = "sirfsoc_uart",
5df83111 QL	259	},
	260	};
	261	/* uart io ctrl */
161e773c RW	262	#define SIRFUART_DATA_BIT_LEN_MASK 0x3
	263	#define SIRFUART_DATA_BIT_LEN_5 BIT(0)
	264	#define SIRFUART_DATA_BIT_LEN_6 1
	265	#define SIRFUART_DATA_BIT_LEN_7 2
	266	#define SIRFUART_DATA_BIT_LEN_8 3
	267	#define SIRFUART_STOP_BIT_LEN_1 0
	268	#define SIRFUART_STOP_BIT_LEN_2 BIT(2)
	269	#define SIRFUART_PARITY_EN BIT(3)
	270	#define SIRFUART_EVEN_BIT BIT(4)
	271	#define SIRFUART_STICK_BIT_MASK (7 << 3)
	272	#define SIRFUART_STICK_BIT_NONE (0 << 3)
	273	#define SIRFUART_STICK_BIT_EVEN BIT(3)
	274	#define SIRFUART_STICK_BIT_ODD (3 << 3)
	275	#define SIRFUART_STICK_BIT_MARK (5 << 3)
	276	#define SIRFUART_STICK_BIT_SPACE (7 << 3)
	277	#define SIRFUART_SET_BREAK BIT(6)
	278	#define SIRFUART_LOOP_BACK BIT(7)
	279	#define SIRFUART_PARITY_MASK (7 << 3)
	280	#define SIRFUART_DUMMY_READ BIT(16)
5df83111	281	#define SIRFUART_AFC_CTRL_RX_THD 0x70
161e773c RW	282	#define SIRFUART_AFC_RX_EN BIT(8)
161e773c RW	283	#define SIRFUART_AFC_TX_EN BIT(9)
5df83111 QL	284	#define SIRFUART_AFC_CTS_CTRL BIT(10)
	285	#define SIRFUART_AFC_RTS_CTRL BIT(11)
	286	#define SIRFUART_AFC_CTS_STATUS BIT(12)
	287	#define SIRFUART_AFC_RTS_STATUS BIT(13)
161e773c	288	/* UART FIFO Register */
5df83111 QL	289	#define SIRFUART_FIFO_STOP 0x0
	290	#define SIRFUART_FIFO_RESET BIT(0)
	291	#define SIRFUART_FIFO_START BIT(1)
	292
	293	#define SIRFUART_RX_EN BIT(0)
	294	#define SIRFUART_TX_EN BIT(1)
	295
	296	#define SIRFUART_IO_MODE BIT(0)
	297	#define SIRFUART_DMA_MODE 0x0
0f17e3b4	298	#define SIRFUART_RX_DMA_FLUSH 0x4
5df83111	299
1d26c9ff	300	#define SIRFUART_CLEAR_RX_ADDR_EN 0x2
5df83111	301	/* Baud Rate Calculation */
cb4595a2	302	#define SIRF_USP_MIN_SAMPLE_DIV 0x1
5df83111 QL	303	#define SIRF_MIN_SAMPLE_DIV 0xf
	304	#define SIRF_MAX_SAMPLE_DIV 0x3f
	305	#define SIRF_IOCLK_DIV_MAX 0xffff
	306	#define SIRF_SAMPLE_DIV_SHIFT 16
	307	#define SIRF_IOCLK_DIV_MASK 0xffff
	308	#define SIRF_SAMPLE_DIV_MASK 0x3f0000
	309	#define SIRF_BAUD_RATE_SUPPORT_NR 18
	310
	311	/* USP SPEC */
	312	#define SIRFSOC_USP_ENDIAN_CTRL_LSBF BIT(4)
	313	#define SIRFSOC_USP_EN BIT(5)
459f15c4 QL	314	#define SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET 0
	315	#define SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET 8
	316	#define SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK 0x3ff
	317	#define SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET 21
	318	#define SIRFSOC_USP_TX_DATA_LEN_OFFSET 0
	319	#define SIRFSOC_USP_TX_SYNC_LEN_OFFSET 8
	320	#define SIRFSOC_USP_TX_FRAME_LEN_OFFSET 16
	321	#define SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET 24
	322	#define SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET 30
	323	#define SIRFSOC_USP_RX_DATA_LEN_OFFSET 0
	324	#define SIRFSOC_USP_RX_FRAME_LEN_OFFSET 8
	325	#define SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET 16
	326	#define SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET 24
	327	#define SIRFSOC_USP_ASYNC_DIV2_MASK 0x3f
	328	#define SIRFSOC_USP_ASYNC_DIV2_OFFSET 16
7f60f2fe	329	#define SIRFSOC_USP_LOOP_BACK_CTRL BIT(2)
1d26c9ff	330	#define SIRFSOC_USP_FRADDR_CLR_EN BIT(1)
5df83111 QL	331	/* USP-UART Common */
	332	#define SIRFSOC_UART_RX_TIMEOUT(br, to) (((br) * (((to) + 999) / 1000)) / 1000)
	333	#define SIRFUART_RECV_TIMEOUT_VALUE(x) \
	334	(((x) > 0xFFFF) ? 0xFFFF : ((x) & 0xFFFF))
c1b7ac6f QL	335	#define SIRFUART_USP_RECV_TIMEOUT(x) (x & 0xFFFF)
c1b7ac6f QL	336	#define SIRFUART_UART_RECV_TIMEOUT(x) ((x & 0xFFFF) << 16)
161e773c	337
cb4595a2	338	#define SIRFUART_FIFO_THD(port) (port->fifosize >> 1)
c1b7ac6f	339	#define SIRFUART_ERR_INT_STAT(unit_st, uart_type) \
5df83111 QL	340	(uint_st->sirfsoc_rx_oflow \| \
	341	uint_st->sirfsoc_frm_err \| \
	342	uint_st->sirfsoc_rxd_brk \| \
c1b7ac6f QL	343	((uart_type != SIRF_REAL_UART) ? \
	344	0 : uint_st->sirfsoc_parity_err))
	345	#define SIRFUART_RX_IO_INT_EN(uint_en, uart_type) \
	346	(uint_en->sirfsoc_rx_done_en \|\
5df83111 QL	347	uint_en->sirfsoc_rxfifo_thd_en \|\
	348	uint_en->sirfsoc_rxfifo_full_en \|\
	349	uint_en->sirfsoc_frm_err_en \|\
	350	uint_en->sirfsoc_rx_oflow_en \|\
	351	uint_en->sirfsoc_rxd_brk_en \|\
c1b7ac6f QL	352	((uart_type != SIRF_REAL_UART) ? \
c1b7ac6f QL	353	0 : uint_en->sirfsoc_parity_err_en))
5df83111	354	#define SIRFUART_RX_IO_INT_ST(uint_st) \
c1b7ac6f QL	355	(uint_st->sirfsoc_rxfifo_thd \|\
	356	uint_st->sirfsoc_rxfifo_full\|\
	357	uint_st->sirfsoc_rx_done \|\
	358	uint_st->sirfsoc_rx_timeout)
5df83111	359	#define SIRFUART_CTS_INT_ST(uint_st) (uint_st->sirfsoc_cts)
c1b7ac6f	360	#define SIRFUART_RX_DMA_INT_EN(uint_en, uart_type) \
0f17e3b4	361	(uint_en->sirfsoc_frm_err_en \|\
8316d04c QL	362	uint_en->sirfsoc_rx_oflow_en \|\
8316d04c QL	363	uint_en->sirfsoc_rxd_brk_en \|\
c1b7ac6f QL	364	((uart_type != SIRF_REAL_UART) ? \
c1b7ac6f QL	365	0 : uint_en->sirfsoc_parity_err_en))
161e773c RW	366	/* Generic Definitions */
	367	#define SIRFSOC_UART_NAME "ttySiRF"
	368	#define SIRFSOC_UART_MAJOR 0
	369	#define SIRFSOC_UART_MINOR 0
	370	#define SIRFUART_PORT_NAME "sirfsoc-uart"
	371	#define SIRFUART_MAP_SIZE 0x200
a6ffe896	372	#define SIRFSOC_UART_NR 11
161e773c RW	373	#define SIRFSOC_PORT_TYPE 0xa5
161e773c RW	374
8316d04c	375	/* Uart Common Use Macro*/
0f17e3b4	376	#define SIRFSOC_RX_DMA_BUF_SIZE (1024 * 32)
8316d04c	377	#define BYTES_TO_ALIGN(dma_addr) ((unsigned long)(dma_addr) & 0x3)
8316d04c QL	378	/* Uart Fifo Level Chk */
	379	#define SIRFUART_TX_FIFO_SC_OFFSET 0
	380	#define SIRFUART_TX_FIFO_LC_OFFSET 10
	381	#define SIRFUART_TX_FIFO_HC_OFFSET 20
	382	#define SIRFUART_TX_FIFO_CHK_SC(line, value) ((((line) == 1) ? (value & 0x3) :\
	383	(value & 0x1f)) << SIRFUART_TX_FIFO_SC_OFFSET)
	384	#define SIRFUART_TX_FIFO_CHK_LC(line, value) ((((line) == 1) ? (value & 0x3) :\
	385	(value & 0x1f)) << SIRFUART_TX_FIFO_LC_OFFSET)
	386	#define SIRFUART_TX_FIFO_CHK_HC(line, value) ((((line) == 1) ? (value & 0x3) :\
	387	(value & 0x1f)) << SIRFUART_TX_FIFO_HC_OFFSET)
	388
	389	#define SIRFUART_RX_FIFO_CHK_SC SIRFUART_TX_FIFO_CHK_SC
	390	#define SIRFUART_RX_FIFO_CHK_LC SIRFUART_TX_FIFO_CHK_LC
	391	#define SIRFUART_RX_FIFO_CHK_HC SIRFUART_TX_FIFO_CHK_HC
0f17e3b4	392	#define SIRFUART_RX_FIFO_MASK 0x7f
8316d04c	393	/* Indicate how many buffers used */
8316d04c	394
161e773c RW	395	/* For Fast Baud Rate Calculation */
	396	struct sirfsoc_baudrate_to_regv {
	397	unsigned int baud_rate;
	398	unsigned int reg_val;
	399	};
	400
8316d04c QL	401	enum sirfsoc_tx_state {
	402	TX_DMA_IDLE,
	403	TX_DMA_RUNNING,
	404	TX_DMA_PAUSE,
	405	};
	406
0f17e3b4	407	struct sirfsoc_rx_buffer {
8316d04c QL	408	struct circ_buf xmit;
	409	dma_cookie_t cookie;
	410	struct dma_async_tx_descriptor *desc;
	411	dma_addr_t dma_addr;
	412	};
	413
161e773c	414	struct sirfsoc_uart_port {
2eb5618d QL	415	bool hw_flow_ctrl;
2eb5618d QL	416	bool ms_enabled;
161e773c RW	417
161e773c RW	418	struct uart_port port;
ac4ce718	419	struct clk *clk;
057badd6 BS	420	/* for SiRFatlas7, there are SET/CLR for UART_INT_EN */
057badd6 BS	421	bool is_atlas7;
5df83111	422	struct sirfsoc_uart_register *uart_reg;
8316d04c QL	423	struct dma_chan *rx_dma_chan;
	424	struct dma_chan *tx_dma_chan;
	425	dma_addr_t tx_dma_addr;
	426	struct dma_async_tx_descriptor *tx_dma_desc;
8316d04c QL	427	unsigned long transfer_size;
8316d04c QL	428	enum sirfsoc_tx_state tx_dma_state;
2eb5618d QL	429	unsigned int cts_gpio;
2eb5618d QL	430	unsigned int rts_gpio;
8316d04c	431
0f17e3b4 QL	432	struct sirfsoc_rx_buffer rx_dma_items;
	433	struct hrtimer hrt;
	434	bool is_hrt_enabled;
	435	unsigned long rx_period_time;
1d26c9ff QL	436	unsigned long rx_last_pos;
1d26c9ff QL	437	unsigned long pio_fetch_cnt;
161e773c RW	438	};
161e773c RW	439
161e773c RW	440	/* Register Access Control */
161e773c RW	441	#define portaddr(port, reg) ((port)->membase + (reg))
161e773c	442	#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
161e773c RW	443	#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
	444
	445	/* UART Port Mask */
cb4595a2 QL	446	#define SIRFUART_FIFOLEVEL_MASK(port) ((port->fifosize - 1) & 0xFFF)
	447	#define SIRFUART_FIFOFULL_MASK(port) (port->fifosize & 0xFFF)
	448	#define SIRFUART_FIFOEMPTY_MASK(port) ((port->fifosize & 0xFFF) << 1)