[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / uartlite.c

/*
 * uartlite.c: Serial driver for Xilinx uartlite serial controller
 *
 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
 * Copyright (C) 2007 Secret Lab Technologies Ltd.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/console.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>

#define ULITE_NAME		"ttyUL"
#define ULITE_MAJOR		204
#define ULITE_MINOR		187
#define ULITE_NR_UARTS		4

/* ---------------------------------------------------------------------
 * Register definitions
 *
 * For register details see datasheet:
 * http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
 */

#define ULITE_RX		0x00
#define ULITE_TX		0x04
#define ULITE_STATUS		0x08
#define ULITE_CONTROL		0x0c

#define ULITE_REGION		16

#define ULITE_STATUS_RXVALID	0x01
#define ULITE_STATUS_RXFULL	0x02
#define ULITE_STATUS_TXEMPTY	0x04
#define ULITE_STATUS_TXFULL	0x08
#define ULITE_STATUS_IE		0x10
#define ULITE_STATUS_OVERRUN	0x20
#define ULITE_STATUS_FRAME	0x40
#define ULITE_STATUS_PARITY	0x80

#define ULITE_CONTROL_RST_TX	0x01
#define ULITE_CONTROL_RST_RX	0x02
#define ULITE_CONTROL_IE	0x10

struct uartlite_reg_ops {
	u32 (*in)(void __iomem *addr);
	void (*out)(u32 val, void __iomem *addr);
};

static u32 uartlite_inbe32(void __iomem *addr)
{
	return ioread32be(addr);
}

static void uartlite_outbe32(u32 val, void __iomem *addr)
{
	iowrite32be(val, addr);
}

static struct uartlite_reg_ops uartlite_be = {
	.in = uartlite_inbe32,
	.out = uartlite_outbe32,
};

static u32 uartlite_inle32(void __iomem *addr)
{
	return ioread32(addr);
}

static void uartlite_outle32(u32 val, void __iomem *addr)
{
	iowrite32(val, addr);
}

static struct uartlite_reg_ops uartlite_le = {
	.in = uartlite_inle32,
	.out = uartlite_outle32,
};

static inline u32 uart_in32(u32 offset, struct uart_port *port)
{
	struct uartlite_reg_ops *reg_ops = port->private_data;

	return reg_ops->in(port->membase + offset);
}

static inline void uart_out32(u32 val, u32 offset, struct uart_port *port)
{
	struct uartlite_reg_ops *reg_ops = port->private_data;

	reg_ops->out(val, port->membase + offset);
}

static struct uart_port ulite_ports[ULITE_NR_UARTS];

/* ---------------------------------------------------------------------
 * Core UART driver operations
 */

static int ulite_receive(struct uart_port *port, int stat)
{
	struct tty_port *tport = &port->state->port;
	unsigned char ch = 0;
	char flag = TTY_NORMAL;

	if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
		     | ULITE_STATUS_FRAME)) == 0)
		return 0;

	/* stats */
	if (stat & ULITE_STATUS_RXVALID) {
		port->icount.rx++;
		ch = uart_in32(ULITE_RX, port);

		if (stat & ULITE_STATUS_PARITY)
			port->icount.parity++;
	}

	if (stat & ULITE_STATUS_OVERRUN)
		port->icount.overrun++;

	if (stat & ULITE_STATUS_FRAME)
		port->icount.frame++;


	/* drop byte with parity error if IGNPAR specificed */
	if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
		stat &= ~ULITE_STATUS_RXVALID;

	stat &= port->read_status_mask;

	if (stat & ULITE_STATUS_PARITY)
		flag = TTY_PARITY;


	stat &= ~port->ignore_status_mask;

	if (stat & ULITE_STATUS_RXVALID)
		tty_insert_flip_char(tport, ch, flag);

	if (stat & ULITE_STATUS_FRAME)
		tty_insert_flip_char(tport, 0, TTY_FRAME);

	if (stat & ULITE_STATUS_OVERRUN)
		tty_insert_flip_char(tport, 0, TTY_OVERRUN);

	return 1;
}

static int ulite_transmit(struct uart_port *port, int stat)
{
	struct circ_buf *xmit  = &port->state->xmit;

	if (stat & ULITE_STATUS_TXFULL)
		return 0;

	if (port->x_char) {
		uart_out32(port->x_char, ULITE_TX, port);
		port->x_char = 0;
		port->icount.tx++;
		return 1;
	}

	if (uart_circ_empty(xmit) || uart_tx_stopped(port))
		return 0;

	uart_out32(xmit->buf[xmit->tail], ULITE_TX, port);
	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
	port->icount.tx++;

	/* wake up */
	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);

	return 1;
}

static irqreturn_t ulite_isr(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	int busy, n = 0;

	do {
		int stat = uart_in32(ULITE_STATUS, port);
		busy  = ulite_receive(port, stat);
		busy |= ulite_transmit(port, stat);
		n++;
	} while (busy);

	/* work done? */
	if (n > 1) {
		tty_flip_buffer_push(&port->state->port);
		return IRQ_HANDLED;
	} else {
		return IRQ_NONE;
	}
}

static unsigned int ulite_tx_empty(struct uart_port *port)
{
	unsigned long flags;
	unsigned int ret;

	spin_lock_irqsave(&port->lock, flags);
	ret = uart_in32(ULITE_STATUS, port);
	spin_unlock_irqrestore(&port->lock, flags);

	return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
}

static unsigned int ulite_get_mctrl(struct uart_port *port)
{
	return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
}

static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
	/* N/A */
}

static void ulite_stop_tx(struct uart_port *port)
{
	/* N/A */
}

static void ulite_start_tx(struct uart_port *port)
{
	ulite_transmit(port, uart_in32(ULITE_STATUS, port));
}

static void ulite_stop_rx(struct uart_port *port)
{
	/* don't forward any more data (like !CREAD) */
	port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
		| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
}

static void ulite_enable_ms(struct uart_port *port)
{
	/* N/A */
}

static void ulite_break_ctl(struct uart_port *port, int ctl)
{
	/* N/A */
}

static int ulite_startup(struct uart_port *port)
{
	int ret;

	ret = request_irq(port->irq, ulite_isr, IRQF_SHARED, "uartlite", port);
	if (ret)
		return ret;

	uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
		ULITE_CONTROL, port);
	uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);

	return 0;
}

static void ulite_shutdown(struct uart_port *port)
{
	uart_out32(0, ULITE_CONTROL, port);
	uart_in32(ULITE_CONTROL, port); /* dummy */
	free_irq(port->irq, port);
}

static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
			      struct ktermios *old)
{
	unsigned long flags;
	unsigned int baud;

	spin_lock_irqsave(&port->lock, flags);

	port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
		| ULITE_STATUS_TXFULL;

	if (termios->c_iflag & INPCK)
		port->read_status_mask |=
			ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;

	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |= ULITE_STATUS_PARITY
			| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;

	/* ignore all characters if CREAD is not set */
	if ((termios->c_cflag & CREAD) == 0)
		port->ignore_status_mask |=
			ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
			| ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;

	/* update timeout */
	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	uart_update_timeout(port, termios->c_cflag, baud);

	spin_unlock_irqrestore(&port->lock, flags);
}

static const char *ulite_type(struct uart_port *port)
{
	return port->type == PORT_UARTLITE ? "uartlite" : NULL;
}

static void ulite_release_port(struct uart_port *port)
{
	release_mem_region(port->mapbase, ULITE_REGION);
	iounmap(port->membase);
	port->membase = NULL;
}

static int ulite_request_port(struct uart_port *port)
{
	int ret;

	pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
		 port, (unsigned long long) port->mapbase);

	if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
		dev_err(port->dev, "Memory region busy\n");
		return -EBUSY;
	}

	port->membase = ioremap(port->mapbase, ULITE_REGION);
	if (!port->membase) {
		dev_err(port->dev, "Unable to map registers\n");
		release_mem_region(port->mapbase, ULITE_REGION);
		return -EBUSY;
	}

	port->private_data = &uartlite_be;
	ret = uart_in32(ULITE_CONTROL, port);
	uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port);
	ret = uart_in32(ULITE_STATUS, port);
	/* Endianess detection */
	if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY)
		port->private_data = &uartlite_le;

	return 0;
}

static void ulite_config_port(struct uart_port *port, int flags)
{
	if (!ulite_request_port(port))
		port->type = PORT_UARTLITE;
}

static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
{
	/* we don't want the core code to modify any port params */
	return -EINVAL;
}

#ifdef CONFIG_CONSOLE_POLL
static int ulite_get_poll_char(struct uart_port *port)
{
	if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID))
		return NO_POLL_CHAR;

	return uart_in32(ULITE_RX, port);
}

static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
{
	while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL)
		cpu_relax();

	/* write char to device */
	uart_out32(ch, ULITE_TX, port);
}
#endif

static struct uart_ops ulite_ops = {
	.tx_empty	= ulite_tx_empty,
	.set_mctrl	= ulite_set_mctrl,
	.get_mctrl	= ulite_get_mctrl,
	.stop_tx	= ulite_stop_tx,
	.start_tx	= ulite_start_tx,
	.stop_rx	= ulite_stop_rx,
	.enable_ms	= ulite_enable_ms,
	.break_ctl	= ulite_break_ctl,
	.startup	= ulite_startup,
	.shutdown	= ulite_shutdown,
	.set_termios	= ulite_set_termios,
	.type		= ulite_type,
	.release_port	= ulite_release_port,
	.request_port	= ulite_request_port,
	.config_port	= ulite_config_port,
	.verify_port	= ulite_verify_port,
#ifdef CONFIG_CONSOLE_POLL
	.poll_get_char	= ulite_get_poll_char,
	.poll_put_char	= ulite_put_poll_char,
#endif
};

/* ---------------------------------------------------------------------
 * Console driver operations
 */

#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
static void ulite_console_wait_tx(struct uart_port *port)
{
	u8 val;
	unsigned long timeout;

	/*
	 * Spin waiting for TX fifo to have space available.
	 * When using the Microblaze Debug Module this can take up to 1s
	 */
	timeout = jiffies + msecs_to_jiffies(1000);
	while (1) {
		val = uart_in32(ULITE_STATUS, port);
		if ((val & ULITE_STATUS_TXFULL) == 0)
			break;
		if (time_after(jiffies, timeout)) {
			dev_warn(port->dev,
				 "timeout waiting for TX buffer empty\n");
			break;
		}
		cpu_relax();
	}
}

static void ulite_console_putchar(struct uart_port *port, int ch)
{
	ulite_console_wait_tx(port);
	uart_out32(ch, ULITE_TX, port);
}

static void ulite_console_write(struct console *co, const char *s,
				unsigned int count)
{
	struct uart_port *port = &ulite_ports[co->index];
	unsigned long flags;
	unsigned int ier;
	int locked = 1;

	if (oops_in_progress) {
		locked = spin_trylock_irqsave(&port->lock, flags);
	} else
		spin_lock_irqsave(&port->lock, flags);

	/* save and disable interrupt */
	ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE;
	uart_out32(0, ULITE_CONTROL, port);

	uart_console_write(port, s, count, ulite_console_putchar);

	ulite_console_wait_tx(port);

	/* restore interrupt state */
	if (ier)
		uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);

	if (locked)
		spin_unlock_irqrestore(&port->lock, flags);
}

static int ulite_console_setup(struct console *co, char *options)
{
	struct uart_port *port;
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	if (co->index < 0 || co->index >= ULITE_NR_UARTS)
		return -EINVAL;

	port = &ulite_ports[co->index];

	/* Has the device been initialized yet? */
	if (!port->mapbase) {
		pr_debug("console on ttyUL%i not present\n", co->index);
		return -ENODEV;
	}

	/* not initialized yet? */
	if (!port->membase) {
		if (ulite_request_port(port))
			return -ENODEV;
	}

	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);

	return uart_set_options(port, co, baud, parity, bits, flow);
}

static struct uart_driver ulite_uart_driver;

static struct console ulite_console = {
	.name	= ULITE_NAME,
	.write	= ulite_console_write,
	.device	= uart_console_device,
	.setup	= ulite_console_setup,
	.flags	= CON_PRINTBUFFER,
	.index	= -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
	.data	= &ulite_uart_driver,
};

static int __init ulite_console_init(void)
{
	register_console(&ulite_console);
	return 0;
}

console_initcall(ulite_console_init);

#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */

static struct uart_driver ulite_uart_driver = {
	.owner		= THIS_MODULE,
	.driver_name	= "uartlite",
	.dev_name	= ULITE_NAME,
	.major		= ULITE_MAJOR,
	.minor		= ULITE_MINOR,
	.nr		= ULITE_NR_UARTS,
#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	.cons		= &ulite_console,
#endif
};

/* ---------------------------------------------------------------------
 * Port assignment functions (mapping devices to uart_port structures)
 */

/** ulite_assign: register a uartlite device with the driver
 *
 * @dev: pointer to device structure
 * @id: requested id number.  Pass -1 for automatic port assignment
 * @base: base address of uartlite registers
 * @irq: irq number for uartlite
 *
 * Returns: 0 on success, <0 otherwise
 */
static int ulite_assign(struct device *dev, int id, u32 base, int irq)
{
	struct uart_port *port;
	int rc;

	/* if id = -1; then scan for a free id and use that */
	if (id < 0) {
		for (id = 0; id < ULITE_NR_UARTS; id++)
			if (ulite_ports[id].mapbase == 0)
				break;
	}
	if (id < 0 || id >= ULITE_NR_UARTS) {
		dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
		return -EINVAL;
	}

	if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
		dev_err(dev, "cannot assign to %s%i; it is already in use\n",
			ULITE_NAME, id);
		return -EBUSY;
	}

	port = &ulite_ports[id];

	spin_lock_init(&port->lock);
	port->fifosize = 16;
	port->regshift = 2;
	port->iotype = UPIO_MEM;
	port->iobase = 1; /* mark port in use */
	port->mapbase = base;
	port->membase = NULL;
	port->ops = &ulite_ops;
	port->irq = irq;
	port->flags = UPF_BOOT_AUTOCONF;
	port->dev = dev;
	port->type = PORT_UNKNOWN;
	port->line = id;

	dev_set_drvdata(dev, port);

	/* Register the port */
	rc = uart_add_one_port(&ulite_uart_driver, port);
	if (rc) {
		dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
		port->mapbase = 0;
		dev_set_drvdata(dev, NULL);
		return rc;
	}

	return 0;
}

/** ulite_release: register a uartlite device with the driver
 *
 * @dev: pointer to device structure
 */
static int ulite_release(struct device *dev)
{
	struct uart_port *port = dev_get_drvdata(dev);
	int rc = 0;

	if (port) {
		rc = uart_remove_one_port(&ulite_uart_driver, port);
		dev_set_drvdata(dev, NULL);
		port->mapbase = 0;
	}

	return rc;
}

/* ---------------------------------------------------------------------
 * Platform bus binding
 */

#if defined(CONFIG_OF)
/* Match table for of_platform binding */
static struct of_device_id ulite_of_match[] = {
	{ .compatible = "xlnx,opb-uartlite-1.00.b", },
	{ .compatible = "xlnx,xps-uartlite-1.00.a", },
	{}
};
MODULE_DEVICE_TABLE(of, ulite_of_match);
#endif /* CONFIG_OF */

static int ulite_probe(struct platform_device *pdev)
{
	struct resource *res, *res2;
	int id = pdev->id;
#ifdef CONFIG_OF
	const __be32 *prop;

	prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
	if (prop)
		id = be32_to_cpup(prop);
#endif

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res2)
		return -ENODEV;

	return ulite_assign(&pdev->dev, id, res->start, res2->start);
}

static int ulite_remove(struct platform_device *pdev)
{
	return ulite_release(&pdev->dev);
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:uartlite");

static struct platform_driver ulite_platform_driver = {
	.probe = ulite_probe,
	.remove = ulite_remove,
	.driver = {
		.owner = THIS_MODULE,
		.name  = "uartlite",
		.of_match_table = of_match_ptr(ulite_of_match),
	},
};

/* ---------------------------------------------------------------------
 * Module setup/teardown
 */

static int __init ulite_init(void)
{
	int ret;

	pr_debug("uartlite: calling uart_register_driver()\n");
	ret = uart_register_driver(&ulite_uart_driver);
	if (ret)
		goto err_uart;

	pr_debug("uartlite: calling platform_driver_register()\n");
	ret = platform_driver_register(&ulite_platform_driver);
	if (ret)
		goto err_plat;

	return 0;

err_plat:
	uart_unregister_driver(&ulite_uart_driver);
err_uart:
	pr_err("registering uartlite driver failed: err=%i", ret);
	return ret;
}

static void __exit ulite_exit(void)
{
	platform_driver_unregister(&ulite_platform_driver);
	uart_unregister_driver(&ulite_uart_driver);
}

module_init(ulite_init);
module_exit(ulite_exit);

MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
MODULE_DESCRIPTION("Xilinx uartlite serial driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
238b8721 PK	1	/*
	2	* uartlite.c: Serial driver for Xilinx uartlite serial controller
	3	*
852e1ea7 GL	4	* Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
852e1ea7 GL	5	* Copyright (C) 2007 Secret Lab Technologies Ltd.
238b8721 PK	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
	12	#include <linux/platform_device.h>
	13	#include <linux/module.h>
	14	#include <linux/console.h>
	15	#include <linux/serial.h>
	16	#include <linux/serial_core.h>
	17	#include <linux/tty.h>
ee160a38	18	#include <linux/tty_flip.h>
238b8721 PK	19	#include <linux/delay.h>
238b8721 PK	20	#include <linux/interrupt.h>
0e349b0e	21	#include <linux/init.h>
3240b48d	22	#include <linux/io.h>
0e349b0e	23	#include <linux/of.h>
22ae782f	24	#include <linux/of_address.h>
852e1ea7 GL	25	#include <linux/of_device.h>
852e1ea7 GL	26	#include <linux/of_platform.h>
0e349b0e	27
00775828	28	#define ULITE_NAME "ttyUL"
238b8721 PK	29	#define ULITE_MAJOR 204
	30	#define ULITE_MINOR 187
	31	#define ULITE_NR_UARTS 4
	32
435706b3 GL	33	/* ---------------------------------------------------------------------
	34	* Register definitions
	35	*
	36	* For register details see datasheet:
6d53c3b7	37	* http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
435706b3 GL	38	*/
435706b3 GL	39
238b8721 PK	40	#define ULITE_RX 0x00
	41	#define ULITE_TX 0x04
	42	#define ULITE_STATUS 0x08
	43	#define ULITE_CONTROL 0x0c
	44
	45	#define ULITE_REGION 16
	46
	47	#define ULITE_STATUS_RXVALID 0x01
	48	#define ULITE_STATUS_RXFULL 0x02
	49	#define ULITE_STATUS_TXEMPTY 0x04
	50	#define ULITE_STATUS_TXFULL 0x08
	51	#define ULITE_STATUS_IE 0x10
	52	#define ULITE_STATUS_OVERRUN 0x20
	53	#define ULITE_STATUS_FRAME 0x40
	54	#define ULITE_STATUS_PARITY 0x80
	55
	56	#define ULITE_CONTROL_RST_TX 0x01
	57	#define ULITE_CONTROL_RST_RX 0x02
	58	#define ULITE_CONTROL_IE 0x10
	59
6d53c3b7 MS	60	struct uartlite_reg_ops {
	61	u32 (in)(void __iomem addr);
	62	void (out)(u32 val, void __iomem addr);
	63	};
	64
	65	static u32 uartlite_inbe32(void __iomem *addr)
	66	{
	67	return ioread32be(addr);
	68	}
	69
	70	static void uartlite_outbe32(u32 val, void __iomem *addr)
	71	{
	72	iowrite32be(val, addr);
	73	}
	74
	75	static struct uartlite_reg_ops uartlite_be = {
	76	.in = uartlite_inbe32,
	77	.out = uartlite_outbe32,
	78	};
	79
	80	static u32 uartlite_inle32(void __iomem *addr)
	81	{
	82	return ioread32(addr);
	83	}
	84
	85	static void uartlite_outle32(u32 val, void __iomem *addr)
	86	{
	87	iowrite32(val, addr);
	88	}
	89
	90	static struct uartlite_reg_ops uartlite_le = {
	91	.in = uartlite_inle32,
	92	.out = uartlite_outle32,
	93	};
	94
	95	static inline u32 uart_in32(u32 offset, struct uart_port *port)
	96	{
	97	struct uartlite_reg_ops *reg_ops = port->private_data;
	98
	99	return reg_ops->in(port->membase + offset);
	100	}
	101
	102	static inline void uart_out32(u32 val, u32 offset, struct uart_port *port)
	103	{
	104	struct uartlite_reg_ops *reg_ops = port->private_data;
	105
	106	reg_ops->out(val, port->membase + offset);
	107	}
238b8721	108
483c79db	109	static struct uart_port ulite_ports[ULITE_NR_UARTS];
238b8721	110
435706b3 GL	111	/* ---------------------------------------------------------------------
	112	* Core UART driver operations
	113	*/
	114
238b8721 PK	115	static int ulite_receive(struct uart_port *port, int stat)
238b8721 PK	116	{
92a19f9c	117	struct tty_port *tport = &port->state->port;
238b8721 PK	118	unsigned char ch = 0;
	119	char flag = TTY_NORMAL;
	120
	121	if ((stat & (ULITE_STATUS_RXVALID \| ULITE_STATUS_OVERRUN
	122	\| ULITE_STATUS_FRAME)) == 0)
	123	return 0;
	124
	125	/* stats */
	126	if (stat & ULITE_STATUS_RXVALID) {
	127	port->icount.rx++;
6d53c3b7	128	ch = uart_in32(ULITE_RX, port);
238b8721 PK	129
	130	if (stat & ULITE_STATUS_PARITY)
	131	port->icount.parity++;
	132	}
	133
	134	if (stat & ULITE_STATUS_OVERRUN)
	135	port->icount.overrun++;
	136
	137	if (stat & ULITE_STATUS_FRAME)
	138	port->icount.frame++;
	139
	140
	141	/* drop byte with parity error if IGNPAR specificed */
	142	if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
	143	stat &= ~ULITE_STATUS_RXVALID;
	144
	145	stat &= port->read_status_mask;
	146
	147	if (stat & ULITE_STATUS_PARITY)
	148	flag = TTY_PARITY;
	149
	150
	151	stat &= ~port->ignore_status_mask;
	152
	153	if (stat & ULITE_STATUS_RXVALID)
92a19f9c	154	tty_insert_flip_char(tport, ch, flag);
238b8721 PK	155
238b8721 PK	156	if (stat & ULITE_STATUS_FRAME)
92a19f9c	157	tty_insert_flip_char(tport, 0, TTY_FRAME);
238b8721 PK	158
238b8721 PK	159	if (stat & ULITE_STATUS_OVERRUN)
92a19f9c	160	tty_insert_flip_char(tport, 0, TTY_OVERRUN);
238b8721 PK	161
	162	return 1;
	163	}
	164
	165	static int ulite_transmit(struct uart_port *port, int stat)
	166	{
ebd2c8f6	167	struct circ_buf *xmit = &port->state->xmit;
238b8721 PK	168
	169	if (stat & ULITE_STATUS_TXFULL)
	170	return 0;
	171
	172	if (port->x_char) {
6d53c3b7	173	uart_out32(port->x_char, ULITE_TX, port);
238b8721 PK	174	port->x_char = 0;
	175	port->icount.tx++;
	176	return 1;
	177	}
	178
	179	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port))
	180	return 0;
	181
6d53c3b7	182	uart_out32(xmit->buf[xmit->tail], ULITE_TX, port);
238b8721 PK	183	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
	184	port->icount.tx++;
	185
	186	/* wake up */
	187	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	188	uart_write_wakeup(port);
	189
	190	return 1;
	191	}
	192
	193	static irqreturn_t ulite_isr(int irq, void *dev_id)
	194	{
15aafa2f	195	struct uart_port *port = dev_id;
d2cfe962	196	int busy, n = 0;
238b8721 PK	197
238b8721 PK	198	do {
6d53c3b7	199	int stat = uart_in32(ULITE_STATUS, port);
238b8721 PK	200	busy = ulite_receive(port, stat);
238b8721 PK	201	busy \|= ulite_transmit(port, stat);
d2cfe962	202	n++;
238b8721 PK	203	} while (busy);
238b8721 PK	204
d2cfe962 PK	205	/* work done? */
d2cfe962 PK	206	if (n > 1) {
2e124b4a	207	tty_flip_buffer_push(&port->state->port);
d2cfe962 PK	208	return IRQ_HANDLED;
	209	} else {
	210	return IRQ_NONE;
	211	}
238b8721 PK	212	}
	213
	214	static unsigned int ulite_tx_empty(struct uart_port *port)
	215	{
	216	unsigned long flags;
	217	unsigned int ret;
	218
	219	spin_lock_irqsave(&port->lock, flags);
6d53c3b7	220	ret = uart_in32(ULITE_STATUS, port);
238b8721 PK	221	spin_unlock_irqrestore(&port->lock, flags);
	222
	223	return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
	224	}
	225
	226	static unsigned int ulite_get_mctrl(struct uart_port *port)
	227	{
	228	return TIOCM_CTS \| TIOCM_DSR \| TIOCM_CAR;
	229	}
	230
	231	static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
	232	{
	233	/* N/A */
	234	}
	235
	236	static void ulite_stop_tx(struct uart_port *port)
	237	{
	238	/* N/A */
	239	}
	240
	241	static void ulite_start_tx(struct uart_port *port)
	242	{
6d53c3b7	243	ulite_transmit(port, uart_in32(ULITE_STATUS, port));
238b8721 PK	244	}
	245
	246	static void ulite_stop_rx(struct uart_port *port)
	247	{
	248	/* don't forward any more data (like !CREAD) */
	249	port->ignore_status_mask = ULITE_STATUS_RXVALID \| ULITE_STATUS_PARITY
	250	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	251	}
	252
	253	static void ulite_enable_ms(struct uart_port *port)
	254	{
	255	/* N/A */
	256	}
	257
	258	static void ulite_break_ctl(struct uart_port *port, int ctl)
	259	{
	260	/* N/A */
	261	}
	262
	263	static int ulite_startup(struct uart_port *port)
	264	{
	265	int ret;
	266
fc4b1863	267	ret = request_irq(port->irq, ulite_isr, IRQF_SHARED, "uartlite", port);
238b8721 PK	268	if (ret)
	269	return ret;
	270
6d53c3b7 MS	271	uart_out32(ULITE_CONTROL_RST_RX \| ULITE_CONTROL_RST_TX,
	272	ULITE_CONTROL, port);
	273	uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
238b8721 PK	274
	275	return 0;
	276	}
	277
	278	static void ulite_shutdown(struct uart_port *port)
	279	{
6d53c3b7 MS	280	uart_out32(0, ULITE_CONTROL, port);
6d53c3b7 MS	281	uart_in32(ULITE_CONTROL, port); /* dummy */
238b8721 PK	282	free_irq(port->irq, port);
	283	}
	284
606d099c AC	285	static void ulite_set_termios(struct uart_port port, struct ktermios termios,
606d099c AC	286	struct ktermios *old)
238b8721 PK	287	{
	288	unsigned long flags;
	289	unsigned int baud;
	290
	291	spin_lock_irqsave(&port->lock, flags);
	292
	293	port->read_status_mask = ULITE_STATUS_RXVALID \| ULITE_STATUS_OVERRUN
	294	\| ULITE_STATUS_TXFULL;
	295
	296	if (termios->c_iflag & INPCK)
	297	port->read_status_mask \|=
	298	ULITE_STATUS_PARITY \| ULITE_STATUS_FRAME;
	299
	300	port->ignore_status_mask = 0;
	301	if (termios->c_iflag & IGNPAR)
	302	port->ignore_status_mask \|= ULITE_STATUS_PARITY
	303	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	304
	305	/* ignore all characters if CREAD is not set */
	306	if ((termios->c_cflag & CREAD) == 0)
	307	port->ignore_status_mask \|=
	308	ULITE_STATUS_RXVALID \| ULITE_STATUS_PARITY
	309	\| ULITE_STATUS_FRAME \| ULITE_STATUS_OVERRUN;
	310
	311	/* update timeout */
	312	baud = uart_get_baud_rate(port, termios, old, 0, 460800);
	313	uart_update_timeout(port, termios->c_cflag, baud);
	314
	315	spin_unlock_irqrestore(&port->lock, flags);
	316	}
	317
	318	static const char ulite_type(struct uart_port port)
	319	{
	320	return port->type == PORT_UARTLITE ? "uartlite" : NULL;
	321	}
	322
	323	static void ulite_release_port(struct uart_port *port)
	324	{
	325	release_mem_region(port->mapbase, ULITE_REGION);
	326	iounmap(port->membase);
b81831c6	327	port->membase = NULL;
238b8721 PK	328	}
	329
	330	static int ulite_request_port(struct uart_port *port)
	331	{
6d53c3b7 MS	332	int ret;
6d53c3b7 MS	333
a1080968 GL	334	pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
a1080968 GL	335	port, (unsigned long long) port->mapbase);
0e349b0e	336
238b8721 PK	337	if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
	338	dev_err(port->dev, "Memory region busy\n");
	339	return -EBUSY;
	340	}
	341
	342	port->membase = ioremap(port->mapbase, ULITE_REGION);
	343	if (!port->membase) {
	344	dev_err(port->dev, "Unable to map registers\n");
	345	release_mem_region(port->mapbase, ULITE_REGION);
	346	return -EBUSY;
	347	}
	348
6d53c3b7 MS	349	port->private_data = &uartlite_be;
	350	ret = uart_in32(ULITE_CONTROL, port);
	351	uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port);
	352	ret = uart_in32(ULITE_STATUS, port);
	353	/* Endianess detection */
	354	if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY)
	355	port->private_data = &uartlite_le;
	356
238b8721 PK	357	return 0;
	358	}
	359
	360	static void ulite_config_port(struct uart_port *port, int flags)
	361	{
e21654a7 PK	362	if (!ulite_request_port(port))
e21654a7 PK	363	port->type = PORT_UARTLITE;
238b8721 PK	364	}
	365
	366	static int ulite_verify_port(struct uart_port port, struct serial_struct ser)
	367	{
	368	/* we don't want the core code to modify any port params */
	369	return -EINVAL;
	370	}
	371
8a28af7f MS	372	#ifdef CONFIG_CONSOLE_POLL
	373	static int ulite_get_poll_char(struct uart_port *port)
	374	{
6d53c3b7	375	if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID))
8a28af7f MS	376	return NO_POLL_CHAR;
8a28af7f MS	377
6d53c3b7	378	return uart_in32(ULITE_RX, port);
8a28af7f MS	379	}
	380
	381	static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
	382	{
6d53c3b7	383	while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL)
8a28af7f MS	384	cpu_relax();
	385
	386	/* write char to device */
6d53c3b7	387	uart_out32(ch, ULITE_TX, port);
8a28af7f MS	388	}
	389	#endif
	390
238b8721 PK	391	static struct uart_ops ulite_ops = {
	392	.tx_empty = ulite_tx_empty,
	393	.set_mctrl = ulite_set_mctrl,
	394	.get_mctrl = ulite_get_mctrl,
	395	.stop_tx = ulite_stop_tx,
	396	.start_tx = ulite_start_tx,
	397	.stop_rx = ulite_stop_rx,
	398	.enable_ms = ulite_enable_ms,
	399	.break_ctl = ulite_break_ctl,
	400	.startup = ulite_startup,
	401	.shutdown = ulite_shutdown,
	402	.set_termios = ulite_set_termios,
	403	.type = ulite_type,
	404	.release_port = ulite_release_port,
	405	.request_port = ulite_request_port,
	406	.config_port = ulite_config_port,
8a28af7f MS	407	.verify_port = ulite_verify_port,
	408	#ifdef CONFIG_CONSOLE_POLL
	409	.poll_get_char = ulite_get_poll_char,
	410	.poll_put_char = ulite_put_poll_char,
	411	#endif
238b8721 PK	412	};
238b8721 PK	413
435706b3 GL	414	/* ---------------------------------------------------------------------
	415	* Console driver operations
	416	*/
	417
238b8721 PK	418	#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	419	static void ulite_console_wait_tx(struct uart_port *port)
	420	{
1d6b6987	421	u8 val;
d3352154 MS	422	unsigned long timeout;
	423
	424	/*
	425	* Spin waiting for TX fifo to have space available.
	426	* When using the Microblaze Debug Module this can take up to 1s
	427	*/
	428	timeout = jiffies + msecs_to_jiffies(1000);
	429	while (1) {
6d53c3b7	430	val = uart_in32(ULITE_STATUS, port);
1d6b6987	431	if ((val & ULITE_STATUS_TXFULL) == 0)
238b8721	432	break;
d3352154 MS	433	if (time_after(jiffies, timeout)) {
	434	dev_warn(port->dev,
	435	"timeout waiting for TX buffer empty\n");
	436	break;
	437	}
1d6b6987	438	cpu_relax();
238b8721 PK	439	}
	440	}
	441
	442	static void ulite_console_putchar(struct uart_port *port, int ch)
	443	{
	444	ulite_console_wait_tx(port);
6d53c3b7	445	uart_out32(ch, ULITE_TX, port);
238b8721 PK	446	}
	447
	448	static void ulite_console_write(struct console co, const char s,
	449	unsigned int count)
	450	{
483c79db	451	struct uart_port *port = &ulite_ports[co->index];
238b8721 PK	452	unsigned long flags;
	453	unsigned int ier;
	454	int locked = 1;
	455
	456	if (oops_in_progress) {
	457	locked = spin_trylock_irqsave(&port->lock, flags);
	458	} else
	459	spin_lock_irqsave(&port->lock, flags);
	460
	461	/* save and disable interrupt */
6d53c3b7 MS	462	ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE;
6d53c3b7 MS	463	uart_out32(0, ULITE_CONTROL, port);
238b8721 PK	464
	465	uart_console_write(port, s, count, ulite_console_putchar);
	466
	467	ulite_console_wait_tx(port);
	468
	469	/* restore interrupt state */
	470	if (ier)
6d53c3b7	471	uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
238b8721 PK	472
	473	if (locked)
	474	spin_unlock_irqrestore(&port->lock, flags);
	475	}
	476
9671f099	477	static int ulite_console_setup(struct console co, char options)
238b8721 PK	478	{
	479	struct uart_port *port;
	480	int baud = 9600;
	481	int bits = 8;
	482	int parity = 'n';
	483	int flow = 'n';
	484
	485	if (co->index < 0 \|\| co->index >= ULITE_NR_UARTS)
	486	return -EINVAL;
	487
483c79db	488	port = &ulite_ports[co->index];
238b8721	489
3de66a17	490	/* Has the device been initialized yet? */
fb4e6e66 GL	491	if (!port->mapbase) {
	492	pr_debug("console on ttyUL%i not present\n", co->index);
	493	return -ENODEV;
	494	}
	495
238b8721	496	/* not initialized yet? */
852e1ea7	497	if (!port->membase) {
fb4e6e66 GL	498	if (ulite_request_port(port))
fb4e6e66 GL	499	return -ENODEV;
852e1ea7	500	}
238b8721 PK	501
	502	if (options)
	503	uart_parse_options(options, &baud, &parity, &bits, &flow);
	504
	505	return uart_set_options(port, co, baud, parity, bits, flow);
	506	}
	507
	508	static struct uart_driver ulite_uart_driver;
	509
	510	static struct console ulite_console = {
00775828	511	.name = ULITE_NAME,
238b8721 PK	512	.write = ulite_console_write,
	513	.device = uart_console_device,
	514	.setup = ulite_console_setup,
	515	.flags = CON_PRINTBUFFER,
	516	.index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
	517	.data = &ulite_uart_driver,
	518	};
	519
	520	static int __init ulite_console_init(void)
	521	{
	522	register_console(&ulite_console);
	523	return 0;
	524	}
	525
	526	console_initcall(ulite_console_init);
	527
	528	#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
	529
	530	static struct uart_driver ulite_uart_driver = {
	531	.owner = THIS_MODULE,
	532	.driver_name = "uartlite",
00775828	533	.dev_name = ULITE_NAME,
238b8721 PK	534	.major = ULITE_MAJOR,
	535	.minor = ULITE_MINOR,
	536	.nr = ULITE_NR_UARTS,
	537	#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
	538	.cons = &ulite_console,
	539	#endif
	540	};
	541
435706b3 GL	542	/* ---------------------------------------------------------------------
	543	* Port assignment functions (mapping devices to uart_port structures)
	544	*/
	545
	546	/** ulite_assign: register a uartlite device with the driver
	547	*
	548	* @dev: pointer to device structure
	549	* @id: requested id number. Pass -1 for automatic port assignment
	550	* @base: base address of uartlite registers
	551	* @irq: irq number for uartlite
	552	*
	553	* Returns: 0 on success, <0 otherwise
	554	*/
9671f099	555	static int ulite_assign(struct device *dev, int id, u32 base, int irq)
238b8721	556	{
238b8721	557	struct uart_port *port;
8fa7b610	558	int rc;
238b8721	559
8fa7b610 GL	560	/* if id = -1; then scan for a free id and use that */
	561	if (id < 0) {
	562	for (id = 0; id < ULITE_NR_UARTS; id++)
	563	if (ulite_ports[id].mapbase == 0)
	564	break;
	565	}
	566	if (id < 0 \|\| id >= ULITE_NR_UARTS) {
	567	dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
238b8721	568	return -EINVAL;
8fa7b610	569	}
238b8721	570
fb4e6e66	571	if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
8fa7b610 GL	572	dev_err(dev, "cannot assign to %s%i; it is already in use\n",
8fa7b610 GL	573	ULITE_NAME, id);
238b8721	574	return -EBUSY;
8fa7b610	575	}
238b8721	576
8fa7b610	577	port = &ulite_ports[id];
238b8721	578
8fa7b610 GL	579	spin_lock_init(&port->lock);
	580	port->fifosize = 16;
	581	port->regshift = 2;
	582	port->iotype = UPIO_MEM;
	583	port->iobase = 1; /* mark port in use */
	584	port->mapbase = base;
	585	port->membase = NULL;
	586	port->ops = &ulite_ops;
	587	port->irq = irq;
	588	port->flags = UPF_BOOT_AUTOCONF;
	589	port->dev = dev;
	590	port->type = PORT_UNKNOWN;
	591	port->line = id;
	592
	593	dev_set_drvdata(dev, port);
	594
	595	/* Register the port */
	596	rc = uart_add_one_port(&ulite_uart_driver, port);
	597	if (rc) {
	598	dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
	599	port->mapbase = 0;
	600	dev_set_drvdata(dev, NULL);
	601	return rc;
	602	}
238b8721	603
8fa7b610 GL	604	return 0;
8fa7b610 GL	605	}
238b8721	606
435706b3 GL	607	/** ulite_release: register a uartlite device with the driver
	608	*
	609	* @dev: pointer to device structure
	610	*/
ae8d8a14	611	static int ulite_release(struct device *dev)
8fa7b610 GL	612	{
	613	struct uart_port *port = dev_get_drvdata(dev);
	614	int rc = 0;
238b8721	615
8fa7b610 GL	616	if (port) {
	617	rc = uart_remove_one_port(&ulite_uart_driver, port);
	618	dev_set_drvdata(dev, NULL);
	619	port->mapbase = 0;
	620	}
238b8721	621
8fa7b610	622	return rc;
238b8721 PK	623	}
238b8721 PK	624
435706b3 GL	625	/* ---------------------------------------------------------------------
	626	* Platform bus binding
	627	*/
	628
e5263a51 GL	629	#if defined(CONFIG_OF)
e5263a51 GL	630	/* Match table for of_platform binding */
de88b340	631	static struct of_device_id ulite_of_match[] = {
e5263a51 GL	632	{ .compatible = "xlnx,opb-uartlite-1.00.b", },
	633	{ .compatible = "xlnx,xps-uartlite-1.00.a", },
	634	{}
	635	};
	636	MODULE_DEVICE_TABLE(of, ulite_of_match);
e5263a51 GL	637	#endif /* CONFIG_OF */
e5263a51 GL	638
9671f099	639	static int ulite_probe(struct platform_device *pdev)
238b8721	640	{
8fa7b610	641	struct resource res, res2;
e5263a51 GL	642	int id = pdev->id;
	643	#ifdef CONFIG_OF
	644	const __be32 *prop;
	645
	646	prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
	647	if (prop)
	648	id = be32_to_cpup(prop);
	649	#endif
238b8721	650
8fa7b610 GL	651	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	652	if (!res)
	653	return -ENODEV;
238b8721	654
8fa7b610 GL	655	res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	656	if (!res2)
	657	return -ENODEV;
238b8721	658
e5263a51	659	return ulite_assign(&pdev->dev, id, res->start, res2->start);
8fa7b610	660	}
238b8721	661
ae8d8a14	662	static int ulite_remove(struct platform_device *pdev)
8fa7b610 GL	663	{
8fa7b610 GL	664	return ulite_release(&pdev->dev);
238b8721 PK	665	}
238b8721 PK	666
e169c139 KS	667	/* work with hotplug and coldplug */
	668	MODULE_ALIAS("platform:uartlite");
	669
238b8721	670	static struct platform_driver ulite_platform_driver = {
e5263a51	671	.probe = ulite_probe,
2d47b716	672	.remove = ulite_remove,
852e1ea7	673	.driver = {
4018294b	674	.owner = THIS_MODULE,
e5263a51	675	.name = "uartlite",
85888069	676	.of_match_table = of_match_ptr(ulite_of_match),
852e1ea7 GL	677	},
	678	};
	679
435706b3 GL	680	/* ---------------------------------------------------------------------
	681	* Module setup/teardown
	682	*/
	683
3240b48d	684	static int __init ulite_init(void)
238b8721 PK	685	{
	686	int ret;
	687
852e1ea7	688	pr_debug("uartlite: calling uart_register_driver()\n");
238b8721 PK	689	ret = uart_register_driver(&ulite_uart_driver);
238b8721 PK	690	if (ret)
852e1ea7 GL	691	goto err_uart;
852e1ea7 GL	692
852e1ea7	693	pr_debug("uartlite: calling platform_driver_register()\n");
238b8721 PK	694	ret = platform_driver_register(&ulite_platform_driver);
238b8721 PK	695	if (ret)
852e1ea7 GL	696	goto err_plat;
	697
	698	return 0;
238b8721	699
852e1ea7	700	err_plat:
852e1ea7 GL	701	uart_unregister_driver(&ulite_uart_driver);
852e1ea7 GL	702	err_uart:
3240b48d	703	pr_err("registering uartlite driver failed: err=%i", ret);
238b8721 PK	704	return ret;
	705	}
	706
3240b48d	707	static void __exit ulite_exit(void)
238b8721 PK	708	{
	709	platform_driver_unregister(&ulite_platform_driver);
	710	uart_unregister_driver(&ulite_uart_driver);
	711	}
	712
	713	module_init(ulite_init);
	714	module_exit(ulite_exit);
	715
	716	MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
	717	MODULE_DESCRIPTION("Xilinx uartlite serial driver");
	718	MODULE_LICENSE("GPL");