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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Driver for NEC VR4100 series Serial Interface Unit. | |
3 | * | |
ada8e951 | 4 | * Copyright (C) 2004-2008 Yoichi Yuasa <yuasa@linux-mips.org> |
1da177e4 LT |
5 | * |
6 | * Based on drivers/serial/8250.c, by Russell King. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
1da177e4 LT |
22 | |
23 | #if defined(CONFIG_SERIAL_VR41XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
24 | #define SUPPORT_SYSRQ | |
25 | #endif | |
26 | ||
27 | #include <linux/console.h> | |
89164940 | 28 | #include <linux/errno.h> |
1da177e4 LT |
29 | #include <linux/init.h> |
30 | #include <linux/interrupt.h> | |
89164940 | 31 | #include <linux/ioport.h> |
1da177e4 | 32 | #include <linux/module.h> |
89164940 | 33 | #include <linux/platform_device.h> |
1da177e4 LT |
34 | #include <linux/serial.h> |
35 | #include <linux/serial_core.h> | |
36 | #include <linux/serial_reg.h> | |
37 | #include <linux/tty.h> | |
38 | #include <linux/tty_flip.h> | |
39 | ||
40 | #include <asm/io.h> | |
41 | #include <asm/vr41xx/siu.h> | |
42 | #include <asm/vr41xx/vr41xx.h> | |
43 | ||
1da177e4 LT |
44 | #define SIU_BAUD_BASE 1152000 |
45 | #define SIU_MAJOR 204 | |
46 | #define SIU_MINOR_BASE 82 | |
47 | ||
48 | #define RX_MAX_COUNT 256 | |
49 | #define TX_MAX_COUNT 15 | |
50 | ||
51 | #define SIUIRSEL 0x08 | |
52 | #define TMICMODE 0x20 | |
53 | #define TMICTX 0x10 | |
54 | #define IRMSEL 0x0c | |
55 | #define IRMSEL_HP 0x08 | |
56 | #define IRMSEL_TEMIC 0x04 | |
57 | #define IRMSEL_SHARP 0x00 | |
58 | #define IRUSESEL 0x02 | |
59 | #define SIRSEL 0x01 | |
60 | ||
89164940 YY |
61 | static struct uart_port siu_uart_ports[SIU_PORTS_MAX] = { |
62 | [0 ... SIU_PORTS_MAX-1] = { | |
63 | .lock = __SPIN_LOCK_UNLOCKED(siu_uart_ports->lock), | |
d4e33fac | 64 | .irq = 0, |
89164940 | 65 | }, |
1da177e4 LT |
66 | }; |
67 | ||
2174041d | 68 | #ifdef CONFIG_SERIAL_VR41XX_CONSOLE |
1da177e4 | 69 | static uint8_t lsr_break_flag[SIU_PORTS_MAX]; |
2174041d | 70 | #endif |
1da177e4 LT |
71 | |
72 | #define siu_read(port, offset) readb((port)->membase + (offset)) | |
73 | #define siu_write(port, offset, value) writeb((value), (port)->membase + (offset)) | |
74 | ||
75 | void vr41xx_select_siu_interface(siu_interface_t interface) | |
76 | { | |
77 | struct uart_port *port; | |
78 | unsigned long flags; | |
79 | uint8_t irsel; | |
80 | ||
81 | port = &siu_uart_ports[0]; | |
82 | ||
83 | spin_lock_irqsave(&port->lock, flags); | |
84 | ||
85 | irsel = siu_read(port, SIUIRSEL); | |
86 | if (interface == SIU_INTERFACE_IRDA) | |
87 | irsel |= SIRSEL; | |
88 | else | |
89 | irsel &= ~SIRSEL; | |
90 | siu_write(port, SIUIRSEL, irsel); | |
91 | ||
92 | spin_unlock_irqrestore(&port->lock, flags); | |
93 | } | |
1da177e4 LT |
94 | EXPORT_SYMBOL_GPL(vr41xx_select_siu_interface); |
95 | ||
96 | void vr41xx_use_irda(irda_use_t use) | |
97 | { | |
98 | struct uart_port *port; | |
99 | unsigned long flags; | |
100 | uint8_t irsel; | |
101 | ||
102 | port = &siu_uart_ports[0]; | |
103 | ||
104 | spin_lock_irqsave(&port->lock, flags); | |
105 | ||
106 | irsel = siu_read(port, SIUIRSEL); | |
107 | if (use == FIR_USE_IRDA) | |
108 | irsel |= IRUSESEL; | |
109 | else | |
110 | irsel &= ~IRUSESEL; | |
111 | siu_write(port, SIUIRSEL, irsel); | |
112 | ||
113 | spin_unlock_irqrestore(&port->lock, flags); | |
114 | } | |
1da177e4 LT |
115 | EXPORT_SYMBOL_GPL(vr41xx_use_irda); |
116 | ||
117 | void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed) | |
118 | { | |
119 | struct uart_port *port; | |
120 | unsigned long flags; | |
121 | uint8_t irsel; | |
122 | ||
123 | port = &siu_uart_ports[0]; | |
124 | ||
125 | spin_lock_irqsave(&port->lock, flags); | |
126 | ||
127 | irsel = siu_read(port, SIUIRSEL); | |
128 | irsel &= ~(IRMSEL | TMICTX | TMICMODE); | |
129 | switch (module) { | |
130 | case SHARP_IRDA: | |
131 | irsel |= IRMSEL_SHARP; | |
132 | break; | |
133 | case TEMIC_IRDA: | |
134 | irsel |= IRMSEL_TEMIC | TMICMODE; | |
135 | if (speed == IRDA_TX_4MBPS) | |
136 | irsel |= TMICTX; | |
137 | break; | |
138 | case HP_IRDA: | |
139 | irsel |= IRMSEL_HP; | |
140 | break; | |
141 | default: | |
142 | break; | |
143 | } | |
144 | siu_write(port, SIUIRSEL, irsel); | |
145 | ||
146 | spin_unlock_irqrestore(&port->lock, flags); | |
147 | } | |
1da177e4 LT |
148 | EXPORT_SYMBOL_GPL(vr41xx_select_irda_module); |
149 | ||
150 | static inline void siu_clear_fifo(struct uart_port *port) | |
151 | { | |
152 | siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO); | |
153 | siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | | |
154 | UART_FCR_CLEAR_XMIT); | |
155 | siu_write(port, UART_FCR, 0); | |
156 | } | |
157 | ||
1da177e4 LT |
158 | static inline unsigned long siu_port_size(struct uart_port *port) |
159 | { | |
160 | switch (port->type) { | |
161 | case PORT_VR41XX_SIU: | |
162 | return 11UL; | |
163 | case PORT_VR41XX_DSIU: | |
164 | return 8UL; | |
165 | } | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
170 | static inline unsigned int siu_check_type(struct uart_port *port) | |
171 | { | |
89164940 YY |
172 | if (port->line == 0) |
173 | return PORT_VR41XX_SIU; | |
d4e33fac | 174 | if (port->line == 1 && port->irq) |
89164940 | 175 | return PORT_VR41XX_DSIU; |
1da177e4 LT |
176 | |
177 | return PORT_UNKNOWN; | |
178 | } | |
179 | ||
180 | static inline const char *siu_type_name(struct uart_port *port) | |
181 | { | |
182 | switch (port->type) { | |
183 | case PORT_VR41XX_SIU: | |
184 | return "SIU"; | |
185 | case PORT_VR41XX_DSIU: | |
186 | return "DSIU"; | |
187 | } | |
188 | ||
eae936e2 | 189 | return NULL; |
1da177e4 LT |
190 | } |
191 | ||
192 | static unsigned int siu_tx_empty(struct uart_port *port) | |
193 | { | |
194 | uint8_t lsr; | |
195 | ||
196 | lsr = siu_read(port, UART_LSR); | |
197 | if (lsr & UART_LSR_TEMT) | |
198 | return TIOCSER_TEMT; | |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
203 | static void siu_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
204 | { | |
205 | uint8_t mcr = 0; | |
206 | ||
207 | if (mctrl & TIOCM_DTR) | |
208 | mcr |= UART_MCR_DTR; | |
209 | if (mctrl & TIOCM_RTS) | |
210 | mcr |= UART_MCR_RTS; | |
211 | if (mctrl & TIOCM_OUT1) | |
212 | mcr |= UART_MCR_OUT1; | |
213 | if (mctrl & TIOCM_OUT2) | |
214 | mcr |= UART_MCR_OUT2; | |
215 | if (mctrl & TIOCM_LOOP) | |
216 | mcr |= UART_MCR_LOOP; | |
217 | ||
218 | siu_write(port, UART_MCR, mcr); | |
219 | } | |
220 | ||
221 | static unsigned int siu_get_mctrl(struct uart_port *port) | |
222 | { | |
223 | uint8_t msr; | |
224 | unsigned int mctrl = 0; | |
225 | ||
226 | msr = siu_read(port, UART_MSR); | |
227 | if (msr & UART_MSR_DCD) | |
228 | mctrl |= TIOCM_CAR; | |
229 | if (msr & UART_MSR_RI) | |
230 | mctrl |= TIOCM_RNG; | |
231 | if (msr & UART_MSR_DSR) | |
232 | mctrl |= TIOCM_DSR; | |
233 | if (msr & UART_MSR_CTS) | |
234 | mctrl |= TIOCM_CTS; | |
235 | ||
236 | return mctrl; | |
237 | } | |
238 | ||
b129a8cc | 239 | static void siu_stop_tx(struct uart_port *port) |
1da177e4 LT |
240 | { |
241 | unsigned long flags; | |
242 | uint8_t ier; | |
243 | ||
244 | spin_lock_irqsave(&port->lock, flags); | |
245 | ||
246 | ier = siu_read(port, UART_IER); | |
247 | ier &= ~UART_IER_THRI; | |
248 | siu_write(port, UART_IER, ier); | |
249 | ||
250 | spin_unlock_irqrestore(&port->lock, flags); | |
251 | } | |
252 | ||
b129a8cc | 253 | static void siu_start_tx(struct uart_port *port) |
1da177e4 LT |
254 | { |
255 | unsigned long flags; | |
256 | uint8_t ier; | |
257 | ||
258 | spin_lock_irqsave(&port->lock, flags); | |
259 | ||
260 | ier = siu_read(port, UART_IER); | |
261 | ier |= UART_IER_THRI; | |
262 | siu_write(port, UART_IER, ier); | |
263 | ||
264 | spin_unlock_irqrestore(&port->lock, flags); | |
265 | } | |
266 | ||
267 | static void siu_stop_rx(struct uart_port *port) | |
268 | { | |
269 | unsigned long flags; | |
270 | uint8_t ier; | |
271 | ||
272 | spin_lock_irqsave(&port->lock, flags); | |
273 | ||
274 | ier = siu_read(port, UART_IER); | |
275 | ier &= ~UART_IER_RLSI; | |
276 | siu_write(port, UART_IER, ier); | |
277 | ||
278 | port->read_status_mask &= ~UART_LSR_DR; | |
279 | ||
280 | spin_unlock_irqrestore(&port->lock, flags); | |
281 | } | |
282 | ||
283 | static void siu_enable_ms(struct uart_port *port) | |
284 | { | |
285 | unsigned long flags; | |
286 | uint8_t ier; | |
287 | ||
288 | spin_lock_irqsave(&port->lock, flags); | |
289 | ||
290 | ier = siu_read(port, UART_IER); | |
291 | ier |= UART_IER_MSI; | |
292 | siu_write(port, UART_IER, ier); | |
293 | ||
294 | spin_unlock_irqrestore(&port->lock, flags); | |
295 | } | |
296 | ||
297 | static void siu_break_ctl(struct uart_port *port, int ctl) | |
298 | { | |
299 | unsigned long flags; | |
300 | uint8_t lcr; | |
301 | ||
302 | spin_lock_irqsave(&port->lock, flags); | |
303 | ||
304 | lcr = siu_read(port, UART_LCR); | |
305 | if (ctl == -1) | |
306 | lcr |= UART_LCR_SBC; | |
307 | else | |
308 | lcr &= ~UART_LCR_SBC; | |
309 | siu_write(port, UART_LCR, lcr); | |
310 | ||
311 | spin_unlock_irqrestore(&port->lock, flags); | |
312 | } | |
313 | ||
7d12e780 | 314 | static inline void receive_chars(struct uart_port *port, uint8_t *status) |
1da177e4 | 315 | { |
1da177e4 LT |
316 | uint8_t lsr, ch; |
317 | char flag; | |
318 | int max_count = RX_MAX_COUNT; | |
319 | ||
1da177e4 LT |
320 | lsr = *status; |
321 | ||
322 | do { | |
1da177e4 LT |
323 | ch = siu_read(port, UART_RX); |
324 | port->icount.rx++; | |
325 | flag = TTY_NORMAL; | |
326 | ||
327 | #ifdef CONFIG_SERIAL_VR41XX_CONSOLE | |
328 | lsr |= lsr_break_flag[port->line]; | |
329 | lsr_break_flag[port->line] = 0; | |
330 | #endif | |
331 | if (unlikely(lsr & (UART_LSR_BI | UART_LSR_FE | | |
332 | UART_LSR_PE | UART_LSR_OE))) { | |
333 | if (lsr & UART_LSR_BI) { | |
334 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
335 | port->icount.brk++; | |
336 | ||
337 | if (uart_handle_break(port)) | |
338 | goto ignore_char; | |
339 | } | |
340 | ||
341 | if (lsr & UART_LSR_FE) | |
342 | port->icount.frame++; | |
343 | if (lsr & UART_LSR_PE) | |
344 | port->icount.parity++; | |
345 | if (lsr & UART_LSR_OE) | |
346 | port->icount.overrun++; | |
347 | ||
348 | lsr &= port->read_status_mask; | |
349 | if (lsr & UART_LSR_BI) | |
350 | flag = TTY_BREAK; | |
351 | if (lsr & UART_LSR_FE) | |
352 | flag = TTY_FRAME; | |
353 | if (lsr & UART_LSR_PE) | |
354 | flag = TTY_PARITY; | |
355 | } | |
356 | ||
7d12e780 | 357 | if (uart_handle_sysrq_char(port, ch)) |
1da177e4 | 358 | goto ignore_char; |
05ab3014 RK |
359 | |
360 | uart_insert_char(port, lsr, UART_LSR_OE, ch, flag); | |
1da177e4 LT |
361 | |
362 | ignore_char: | |
363 | lsr = siu_read(port, UART_LSR); | |
364 | } while ((lsr & UART_LSR_DR) && (max_count-- > 0)); | |
365 | ||
2e124b4a | 366 | tty_flip_buffer_push(&port->state->port); |
1da177e4 LT |
367 | |
368 | *status = lsr; | |
369 | } | |
370 | ||
371 | static inline void check_modem_status(struct uart_port *port) | |
372 | { | |
373 | uint8_t msr; | |
374 | ||
375 | msr = siu_read(port, UART_MSR); | |
376 | if ((msr & UART_MSR_ANY_DELTA) == 0) | |
377 | return; | |
378 | if (msr & UART_MSR_DDCD) | |
379 | uart_handle_dcd_change(port, msr & UART_MSR_DCD); | |
380 | if (msr & UART_MSR_TERI) | |
381 | port->icount.rng++; | |
382 | if (msr & UART_MSR_DDSR) | |
383 | port->icount.dsr++; | |
384 | if (msr & UART_MSR_DCTS) | |
385 | uart_handle_cts_change(port, msr & UART_MSR_CTS); | |
386 | ||
bdc04e31 | 387 | wake_up_interruptible(&port->state->port.delta_msr_wait); |
1da177e4 LT |
388 | } |
389 | ||
390 | static inline void transmit_chars(struct uart_port *port) | |
391 | { | |
392 | struct circ_buf *xmit; | |
393 | int max_count = TX_MAX_COUNT; | |
394 | ||
ebd2c8f6 | 395 | xmit = &port->state->xmit; |
1da177e4 LT |
396 | |
397 | if (port->x_char) { | |
398 | siu_write(port, UART_TX, port->x_char); | |
399 | port->icount.tx++; | |
400 | port->x_char = 0; | |
401 | return; | |
402 | } | |
403 | ||
404 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 405 | siu_stop_tx(port); |
1da177e4 LT |
406 | return; |
407 | } | |
408 | ||
409 | do { | |
410 | siu_write(port, UART_TX, xmit->buf[xmit->tail]); | |
411 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
412 | port->icount.tx++; | |
413 | if (uart_circ_empty(xmit)) | |
414 | break; | |
415 | } while (max_count-- > 0); | |
416 | ||
417 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
418 | uart_write_wakeup(port); | |
419 | ||
420 | if (uart_circ_empty(xmit)) | |
b129a8cc | 421 | siu_stop_tx(port); |
1da177e4 LT |
422 | } |
423 | ||
7d12e780 | 424 | static irqreturn_t siu_interrupt(int irq, void *dev_id) |
1da177e4 LT |
425 | { |
426 | struct uart_port *port; | |
427 | uint8_t iir, lsr; | |
428 | ||
1da177e4 LT |
429 | port = (struct uart_port *)dev_id; |
430 | ||
431 | iir = siu_read(port, UART_IIR); | |
432 | if (iir & UART_IIR_NO_INT) | |
433 | return IRQ_NONE; | |
434 | ||
435 | lsr = siu_read(port, UART_LSR); | |
436 | if (lsr & UART_LSR_DR) | |
7d12e780 | 437 | receive_chars(port, &lsr); |
1da177e4 LT |
438 | |
439 | check_modem_status(port); | |
440 | ||
441 | if (lsr & UART_LSR_THRE) | |
442 | transmit_chars(port); | |
443 | ||
444 | return IRQ_HANDLED; | |
445 | } | |
446 | ||
447 | static int siu_startup(struct uart_port *port) | |
448 | { | |
449 | int retval; | |
450 | ||
eae936e2 YY |
451 | if (port->membase == NULL) |
452 | return -ENODEV; | |
453 | ||
1da177e4 LT |
454 | siu_clear_fifo(port); |
455 | ||
456 | (void)siu_read(port, UART_LSR); | |
457 | (void)siu_read(port, UART_RX); | |
458 | (void)siu_read(port, UART_IIR); | |
459 | (void)siu_read(port, UART_MSR); | |
460 | ||
461 | if (siu_read(port, UART_LSR) == 0xff) | |
462 | return -ENODEV; | |
463 | ||
464 | retval = request_irq(port->irq, siu_interrupt, 0, siu_type_name(port), port); | |
465 | if (retval) | |
466 | return retval; | |
467 | ||
468 | if (port->type == PORT_VR41XX_DSIU) | |
469 | vr41xx_enable_dsiuint(DSIUINT_ALL); | |
470 | ||
471 | siu_write(port, UART_LCR, UART_LCR_WLEN8); | |
472 | ||
473 | spin_lock_irq(&port->lock); | |
474 | siu_set_mctrl(port, port->mctrl); | |
475 | spin_unlock_irq(&port->lock); | |
476 | ||
477 | siu_write(port, UART_IER, UART_IER_RLSI | UART_IER_RDI); | |
478 | ||
479 | (void)siu_read(port, UART_LSR); | |
480 | (void)siu_read(port, UART_RX); | |
481 | (void)siu_read(port, UART_IIR); | |
482 | (void)siu_read(port, UART_MSR); | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
487 | static void siu_shutdown(struct uart_port *port) | |
488 | { | |
489 | unsigned long flags; | |
490 | uint8_t lcr; | |
491 | ||
1da177e4 LT |
492 | siu_write(port, UART_IER, 0); |
493 | ||
494 | spin_lock_irqsave(&port->lock, flags); | |
495 | ||
496 | port->mctrl &= ~TIOCM_OUT2; | |
497 | siu_set_mctrl(port, port->mctrl); | |
498 | ||
499 | spin_unlock_irqrestore(&port->lock, flags); | |
500 | ||
501 | lcr = siu_read(port, UART_LCR); | |
502 | lcr &= ~UART_LCR_SBC; | |
503 | siu_write(port, UART_LCR, lcr); | |
504 | ||
505 | siu_clear_fifo(port); | |
506 | ||
507 | (void)siu_read(port, UART_RX); | |
508 | ||
509 | if (port->type == PORT_VR41XX_DSIU) | |
510 | vr41xx_disable_dsiuint(DSIUINT_ALL); | |
511 | ||
512 | free_irq(port->irq, port); | |
513 | } | |
514 | ||
606d099c AC |
515 | static void siu_set_termios(struct uart_port *port, struct ktermios *new, |
516 | struct ktermios *old) | |
1da177e4 LT |
517 | { |
518 | tcflag_t c_cflag, c_iflag; | |
519 | uint8_t lcr, fcr, ier; | |
520 | unsigned int baud, quot; | |
521 | unsigned long flags; | |
522 | ||
523 | c_cflag = new->c_cflag; | |
524 | switch (c_cflag & CSIZE) { | |
525 | case CS5: | |
526 | lcr = UART_LCR_WLEN5; | |
527 | break; | |
528 | case CS6: | |
529 | lcr = UART_LCR_WLEN6; | |
530 | break; | |
531 | case CS7: | |
532 | lcr = UART_LCR_WLEN7; | |
533 | break; | |
534 | default: | |
535 | lcr = UART_LCR_WLEN8; | |
536 | break; | |
537 | } | |
538 | ||
539 | if (c_cflag & CSTOPB) | |
540 | lcr |= UART_LCR_STOP; | |
541 | if (c_cflag & PARENB) | |
542 | lcr |= UART_LCR_PARITY; | |
543 | if ((c_cflag & PARODD) != PARODD) | |
544 | lcr |= UART_LCR_EPAR; | |
545 | if (c_cflag & CMSPAR) | |
546 | lcr |= UART_LCR_SPAR; | |
547 | ||
548 | baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16); | |
549 | quot = uart_get_divisor(port, baud); | |
550 | ||
551 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10; | |
552 | ||
553 | spin_lock_irqsave(&port->lock, flags); | |
554 | ||
555 | uart_update_timeout(port, c_cflag, baud); | |
556 | ||
557 | c_iflag = new->c_iflag; | |
558 | ||
559 | port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR; | |
560 | if (c_iflag & INPCK) | |
561 | port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
562 | if (c_iflag & (BRKINT | PARMRK)) | |
563 | port->read_status_mask |= UART_LSR_BI; | |
564 | ||
565 | port->ignore_status_mask = 0; | |
566 | if (c_iflag & IGNPAR) | |
567 | port->ignore_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
568 | if (c_iflag & IGNBRK) { | |
569 | port->ignore_status_mask |= UART_LSR_BI; | |
570 | if (c_iflag & IGNPAR) | |
571 | port->ignore_status_mask |= UART_LSR_OE; | |
572 | } | |
573 | ||
574 | if ((c_cflag & CREAD) == 0) | |
575 | port->ignore_status_mask |= UART_LSR_DR; | |
576 | ||
577 | ier = siu_read(port, UART_IER); | |
578 | ier &= ~UART_IER_MSI; | |
579 | if (UART_ENABLE_MS(port, c_cflag)) | |
580 | ier |= UART_IER_MSI; | |
581 | siu_write(port, UART_IER, ier); | |
582 | ||
583 | siu_write(port, UART_LCR, lcr | UART_LCR_DLAB); | |
584 | ||
585 | siu_write(port, UART_DLL, (uint8_t)quot); | |
586 | siu_write(port, UART_DLM, (uint8_t)(quot >> 8)); | |
587 | ||
588 | siu_write(port, UART_LCR, lcr); | |
589 | ||
590 | siu_write(port, UART_FCR, fcr); | |
591 | ||
592 | siu_set_mctrl(port, port->mctrl); | |
593 | ||
594 | spin_unlock_irqrestore(&port->lock, flags); | |
595 | } | |
596 | ||
597 | static void siu_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) | |
598 | { | |
599 | switch (state) { | |
600 | case 0: | |
601 | switch (port->type) { | |
602 | case PORT_VR41XX_SIU: | |
603 | vr41xx_supply_clock(SIU_CLOCK); | |
604 | break; | |
605 | case PORT_VR41XX_DSIU: | |
606 | vr41xx_supply_clock(DSIU_CLOCK); | |
607 | break; | |
608 | } | |
609 | break; | |
610 | case 3: | |
611 | switch (port->type) { | |
612 | case PORT_VR41XX_SIU: | |
613 | vr41xx_mask_clock(SIU_CLOCK); | |
614 | break; | |
615 | case PORT_VR41XX_DSIU: | |
616 | vr41xx_mask_clock(DSIU_CLOCK); | |
617 | break; | |
618 | } | |
619 | break; | |
620 | } | |
621 | } | |
622 | ||
623 | static const char *siu_type(struct uart_port *port) | |
624 | { | |
625 | return siu_type_name(port); | |
626 | } | |
627 | ||
628 | static void siu_release_port(struct uart_port *port) | |
629 | { | |
630 | unsigned long size; | |
631 | ||
632 | if (port->flags & UPF_IOREMAP) { | |
633 | iounmap(port->membase); | |
634 | port->membase = NULL; | |
635 | } | |
636 | ||
637 | size = siu_port_size(port); | |
638 | release_mem_region(port->mapbase, size); | |
639 | } | |
640 | ||
641 | static int siu_request_port(struct uart_port *port) | |
642 | { | |
643 | unsigned long size; | |
644 | struct resource *res; | |
645 | ||
646 | size = siu_port_size(port); | |
647 | res = request_mem_region(port->mapbase, size, siu_type_name(port)); | |
648 | if (res == NULL) | |
649 | return -EBUSY; | |
650 | ||
651 | if (port->flags & UPF_IOREMAP) { | |
652 | port->membase = ioremap(port->mapbase, size); | |
653 | if (port->membase == NULL) { | |
654 | release_resource(res); | |
655 | return -ENOMEM; | |
656 | } | |
657 | } | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
662 | static void siu_config_port(struct uart_port *port, int flags) | |
663 | { | |
664 | if (flags & UART_CONFIG_TYPE) { | |
665 | port->type = siu_check_type(port); | |
666 | (void)siu_request_port(port); | |
667 | } | |
668 | } | |
669 | ||
670 | static int siu_verify_port(struct uart_port *port, struct serial_struct *serial) | |
671 | { | |
672 | if (port->type != PORT_VR41XX_SIU && port->type != PORT_VR41XX_DSIU) | |
673 | return -EINVAL; | |
674 | if (port->irq != serial->irq) | |
675 | return -EINVAL; | |
676 | if (port->iotype != serial->io_type) | |
677 | return -EINVAL; | |
678 | if (port->mapbase != (unsigned long)serial->iomem_base) | |
679 | return -EINVAL; | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
684 | static struct uart_ops siu_uart_ops = { | |
685 | .tx_empty = siu_tx_empty, | |
686 | .set_mctrl = siu_set_mctrl, | |
687 | .get_mctrl = siu_get_mctrl, | |
688 | .stop_tx = siu_stop_tx, | |
689 | .start_tx = siu_start_tx, | |
690 | .stop_rx = siu_stop_rx, | |
691 | .enable_ms = siu_enable_ms, | |
692 | .break_ctl = siu_break_ctl, | |
693 | .startup = siu_startup, | |
694 | .shutdown = siu_shutdown, | |
695 | .set_termios = siu_set_termios, | |
696 | .pm = siu_pm, | |
697 | .type = siu_type, | |
698 | .release_port = siu_release_port, | |
699 | .request_port = siu_request_port, | |
700 | .config_port = siu_config_port, | |
701 | .verify_port = siu_verify_port, | |
702 | }; | |
703 | ||
89164940 | 704 | static int siu_init_ports(struct platform_device *pdev) |
1da177e4 | 705 | { |
1da177e4 | 706 | struct uart_port *port; |
89164940 | 707 | struct resource *res; |
574de559 | 708 | int *type = dev_get_platdata(&pdev->dev); |
89164940 | 709 | int i; |
1da177e4 | 710 | |
89164940 | 711 | if (!type) |
1da177e4 | 712 | return 0; |
1da177e4 LT |
713 | |
714 | port = siu_uart_ports; | |
89164940 YY |
715 | for (i = 0; i < SIU_PORTS_MAX; i++) { |
716 | port->type = type[i]; | |
717 | if (port->type == PORT_UNKNOWN) | |
718 | continue; | |
719 | port->irq = platform_get_irq(pdev, i); | |
1da177e4 LT |
720 | port->uartclk = SIU_BAUD_BASE * 16; |
721 | port->fifosize = 16; | |
722 | port->regshift = 0; | |
723 | port->iotype = UPIO_MEM; | |
724 | port->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; | |
1da177e4 | 725 | port->line = i; |
89164940 YY |
726 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); |
727 | port->mapbase = res->start; | |
1da177e4 LT |
728 | port++; |
729 | } | |
730 | ||
89164940 | 731 | return i; |
1da177e4 LT |
732 | } |
733 | ||
734 | #ifdef CONFIG_SERIAL_VR41XX_CONSOLE | |
735 | ||
1da177e4 LT |
736 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
737 | ||
738 | static void wait_for_xmitr(struct uart_port *port) | |
739 | { | |
740 | int timeout = 10000; | |
741 | uint8_t lsr, msr; | |
742 | ||
743 | do { | |
744 | lsr = siu_read(port, UART_LSR); | |
745 | if (lsr & UART_LSR_BI) | |
746 | lsr_break_flag[port->line] = UART_LSR_BI; | |
747 | ||
748 | if ((lsr & BOTH_EMPTY) == BOTH_EMPTY) | |
749 | break; | |
750 | } while (timeout-- > 0); | |
751 | ||
752 | if (port->flags & UPF_CONS_FLOW) { | |
753 | timeout = 1000000; | |
754 | ||
755 | do { | |
756 | msr = siu_read(port, UART_MSR); | |
757 | if ((msr & UART_MSR_CTS) != 0) | |
758 | break; | |
759 | } while (timeout-- > 0); | |
760 | } | |
761 | } | |
762 | ||
d358788f RK |
763 | static void siu_console_putchar(struct uart_port *port, int ch) |
764 | { | |
765 | wait_for_xmitr(port); | |
766 | siu_write(port, UART_TX, ch); | |
767 | } | |
768 | ||
1da177e4 LT |
769 | static void siu_console_write(struct console *con, const char *s, unsigned count) |
770 | { | |
771 | struct uart_port *port; | |
772 | uint8_t ier; | |
1da177e4 LT |
773 | |
774 | port = &siu_uart_ports[con->index]; | |
775 | ||
776 | ier = siu_read(port, UART_IER); | |
777 | siu_write(port, UART_IER, 0); | |
778 | ||
d358788f | 779 | uart_console_write(port, s, count, siu_console_putchar); |
1da177e4 LT |
780 | |
781 | wait_for_xmitr(port); | |
782 | siu_write(port, UART_IER, ier); | |
783 | } | |
784 | ||
a24ac9fb | 785 | static int __init siu_console_setup(struct console *con, char *options) |
1da177e4 LT |
786 | { |
787 | struct uart_port *port; | |
788 | int baud = 9600; | |
789 | int parity = 'n'; | |
790 | int bits = 8; | |
791 | int flow = 'n'; | |
792 | ||
793 | if (con->index >= SIU_PORTS_MAX) | |
794 | con->index = 0; | |
795 | ||
796 | port = &siu_uart_ports[con->index]; | |
797 | if (port->membase == NULL) { | |
798 | if (port->mapbase == 0) | |
799 | return -ENODEV; | |
eae936e2 | 800 | port->membase = ioremap(port->mapbase, siu_port_size(port)); |
1da177e4 LT |
801 | } |
802 | ||
a95d3209 YY |
803 | if (port->type == PORT_VR41XX_SIU) |
804 | vr41xx_select_siu_interface(SIU_INTERFACE_RS232C); | |
1da177e4 LT |
805 | |
806 | if (options != NULL) | |
807 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
808 | ||
809 | return uart_set_options(port, con, baud, parity, bits, flow); | |
810 | } | |
811 | ||
812 | static struct uart_driver siu_uart_driver; | |
813 | ||
814 | static struct console siu_console = { | |
815 | .name = "ttyVR", | |
816 | .write = siu_console_write, | |
817 | .device = uart_console_device, | |
818 | .setup = siu_console_setup, | |
819 | .flags = CON_PRINTBUFFER, | |
820 | .index = -1, | |
821 | .data = &siu_uart_driver, | |
822 | }; | |
823 | ||
9671f099 | 824 | static int siu_console_init(void) |
1da177e4 LT |
825 | { |
826 | struct uart_port *port; | |
89164940 | 827 | int i; |
1da177e4 | 828 | |
89164940 | 829 | for (i = 0; i < SIU_PORTS_MAX; i++) { |
1da177e4 | 830 | port = &siu_uart_ports[i]; |
eae936e2 | 831 | port->ops = &siu_uart_ops; |
1da177e4 LT |
832 | } |
833 | ||
834 | register_console(&siu_console); | |
835 | ||
836 | return 0; | |
837 | } | |
838 | ||
839 | console_initcall(siu_console_init); | |
840 | ||
baac5895 YY |
841 | void __init vr41xx_siu_early_setup(struct uart_port *port) |
842 | { | |
843 | if (port->type == PORT_UNKNOWN) | |
844 | return; | |
845 | ||
846 | siu_uart_ports[port->line].line = port->line; | |
847 | siu_uart_ports[port->line].type = port->type; | |
848 | siu_uart_ports[port->line].uartclk = SIU_BAUD_BASE * 16; | |
849 | siu_uart_ports[port->line].mapbase = port->mapbase; | |
850 | siu_uart_ports[port->line].mapbase = port->mapbase; | |
851 | siu_uart_ports[port->line].ops = &siu_uart_ops; | |
852 | } | |
853 | ||
1da177e4 LT |
854 | #define SERIAL_VR41XX_CONSOLE &siu_console |
855 | #else | |
856 | #define SERIAL_VR41XX_CONSOLE NULL | |
857 | #endif | |
858 | ||
859 | static struct uart_driver siu_uart_driver = { | |
860 | .owner = THIS_MODULE, | |
861 | .driver_name = "SIU", | |
862 | .dev_name = "ttyVR", | |
1da177e4 LT |
863 | .major = SIU_MAJOR, |
864 | .minor = SIU_MINOR_BASE, | |
865 | .cons = SERIAL_VR41XX_CONSOLE, | |
866 | }; | |
867 | ||
9671f099 | 868 | static int siu_probe(struct platform_device *dev) |
1da177e4 LT |
869 | { |
870 | struct uart_port *port; | |
871 | int num, i, retval; | |
872 | ||
89164940 | 873 | num = siu_init_ports(dev); |
1da177e4 LT |
874 | if (num <= 0) |
875 | return -ENODEV; | |
876 | ||
877 | siu_uart_driver.nr = num; | |
878 | retval = uart_register_driver(&siu_uart_driver); | |
879 | if (retval) | |
880 | return retval; | |
881 | ||
882 | for (i = 0; i < num; i++) { | |
883 | port = &siu_uart_ports[i]; | |
884 | port->ops = &siu_uart_ops; | |
3ae5eaec | 885 | port->dev = &dev->dev; |
1da177e4 LT |
886 | |
887 | retval = uart_add_one_port(&siu_uart_driver, port); | |
eae936e2 YY |
888 | if (retval < 0) { |
889 | port->dev = NULL; | |
1da177e4 | 890 | break; |
eae936e2 | 891 | } |
1da177e4 LT |
892 | } |
893 | ||
894 | if (i == 0 && retval < 0) { | |
895 | uart_unregister_driver(&siu_uart_driver); | |
896 | return retval; | |
897 | } | |
898 | ||
899 | return 0; | |
900 | } | |
901 | ||
ae8d8a14 | 902 | static int siu_remove(struct platform_device *dev) |
1da177e4 LT |
903 | { |
904 | struct uart_port *port; | |
905 | int i; | |
906 | ||
907 | for (i = 0; i < siu_uart_driver.nr; i++) { | |
908 | port = &siu_uart_ports[i]; | |
3ae5eaec | 909 | if (port->dev == &dev->dev) { |
1da177e4 LT |
910 | uart_remove_one_port(&siu_uart_driver, port); |
911 | port->dev = NULL; | |
912 | } | |
913 | } | |
914 | ||
915 | uart_unregister_driver(&siu_uart_driver); | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
3ae5eaec | 920 | static int siu_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 LT |
921 | { |
922 | struct uart_port *port; | |
923 | int i; | |
924 | ||
1da177e4 LT |
925 | for (i = 0; i < siu_uart_driver.nr; i++) { |
926 | port = &siu_uart_ports[i]; | |
927 | if ((port->type == PORT_VR41XX_SIU || | |
3ae5eaec | 928 | port->type == PORT_VR41XX_DSIU) && port->dev == &dev->dev) |
1da177e4 LT |
929 | uart_suspend_port(&siu_uart_driver, port); |
930 | ||
931 | } | |
932 | ||
933 | return 0; | |
934 | } | |
935 | ||
3ae5eaec | 936 | static int siu_resume(struct platform_device *dev) |
1da177e4 LT |
937 | { |
938 | struct uart_port *port; | |
939 | int i; | |
940 | ||
1da177e4 LT |
941 | for (i = 0; i < siu_uart_driver.nr; i++) { |
942 | port = &siu_uart_ports[i]; | |
943 | if ((port->type == PORT_VR41XX_SIU || | |
3ae5eaec | 944 | port->type == PORT_VR41XX_DSIU) && port->dev == &dev->dev) |
1da177e4 LT |
945 | uart_resume_port(&siu_uart_driver, port); |
946 | } | |
947 | ||
948 | return 0; | |
949 | } | |
950 | ||
3ae5eaec | 951 | static struct platform_driver siu_device_driver = { |
1da177e4 | 952 | .probe = siu_probe, |
2d47b716 | 953 | .remove = siu_remove, |
1da177e4 LT |
954 | .suspend = siu_suspend, |
955 | .resume = siu_resume, | |
3ae5eaec RK |
956 | .driver = { |
957 | .name = "SIU", | |
d39b6cfe | 958 | .owner = THIS_MODULE, |
3ae5eaec | 959 | }, |
1da177e4 LT |
960 | }; |
961 | ||
c8381c15 | 962 | module_platform_driver(siu_device_driver); |
e169c139 KS |
963 | |
964 | MODULE_LICENSE("GPL"); | |
965 | MODULE_ALIAS("platform:SIU"); |