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1da177e4 | 1 | /* |
7f3edb94 | 2 | * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $ |
1da177e4 LT |
3 | * |
4 | * Device driver for Microgate SyncLink Multiport | |
5 | * high speed multiprotocol serial adapter. | |
6 | * | |
7 | * written by Paul Fulghum for Microgate Corporation | |
8 | * paulkf@microgate.com | |
9 | * | |
10 | * Microgate and SyncLink are trademarks of Microgate Corporation | |
11 | * | |
12 | * Derived from serial.c written by Theodore Ts'o and Linus Torvalds | |
13 | * This code is released under the GNU General Public License (GPL) | |
14 | * | |
15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | |
17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
18 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, | |
19 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
20 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
21 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
22 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
23 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
24 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | |
25 | * OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
28 | #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq)) | |
29 | #if defined(__i386__) | |
30 | # define BREAKPOINT() asm(" int $3"); | |
31 | #else | |
32 | # define BREAKPOINT() { } | |
33 | #endif | |
34 | ||
35 | #define MAX_DEVICES 12 | |
36 | ||
1da177e4 LT |
37 | #include <linux/module.h> |
38 | #include <linux/errno.h> | |
39 | #include <linux/signal.h> | |
40 | #include <linux/sched.h> | |
41 | #include <linux/timer.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/pci.h> | |
44 | #include <linux/tty.h> | |
45 | #include <linux/tty_flip.h> | |
46 | #include <linux/serial.h> | |
47 | #include <linux/major.h> | |
48 | #include <linux/string.h> | |
49 | #include <linux/fcntl.h> | |
50 | #include <linux/ptrace.h> | |
51 | #include <linux/ioport.h> | |
52 | #include <linux/mm.h> | |
e6c8dd8a | 53 | #include <linux/seq_file.h> |
1da177e4 LT |
54 | #include <linux/slab.h> |
55 | #include <linux/netdevice.h> | |
56 | #include <linux/vmalloc.h> | |
57 | #include <linux/init.h> | |
1da177e4 LT |
58 | #include <linux/delay.h> |
59 | #include <linux/ioctl.h> | |
60 | ||
1da177e4 LT |
61 | #include <asm/io.h> |
62 | #include <asm/irq.h> | |
63 | #include <asm/dma.h> | |
64 | #include <linux/bitops.h> | |
65 | #include <asm/types.h> | |
66 | #include <linux/termios.h> | |
67 | #include <linux/workqueue.h> | |
68 | #include <linux/hdlc.h> | |
3dd1247f | 69 | #include <linux/synclink.h> |
1da177e4 | 70 | |
af69c7f9 PF |
71 | #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE)) |
72 | #define SYNCLINK_GENERIC_HDLC 1 | |
73 | #else | |
74 | #define SYNCLINK_GENERIC_HDLC 0 | |
1da177e4 LT |
75 | #endif |
76 | ||
77 | #define GET_USER(error,value,addr) error = get_user(value,addr) | |
78 | #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 | |
79 | #define PUT_USER(error,value,addr) error = put_user(value,addr) | |
80 | #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 | |
81 | ||
82 | #include <asm/uaccess.h> | |
83 | ||
1da177e4 LT |
84 | static MGSL_PARAMS default_params = { |
85 | MGSL_MODE_HDLC, /* unsigned long mode */ | |
86 | 0, /* unsigned char loopback; */ | |
87 | HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */ | |
88 | HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */ | |
89 | 0, /* unsigned long clock_speed; */ | |
90 | 0xff, /* unsigned char addr_filter; */ | |
91 | HDLC_CRC_16_CCITT, /* unsigned short crc_type; */ | |
92 | HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */ | |
93 | HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */ | |
94 | 9600, /* unsigned long data_rate; */ | |
95 | 8, /* unsigned char data_bits; */ | |
96 | 1, /* unsigned char stop_bits; */ | |
97 | ASYNC_PARITY_NONE /* unsigned char parity; */ | |
98 | }; | |
99 | ||
100 | /* size in bytes of DMA data buffers */ | |
101 | #define SCABUFSIZE 1024 | |
102 | #define SCA_MEM_SIZE 0x40000 | |
103 | #define SCA_BASE_SIZE 512 | |
104 | #define SCA_REG_SIZE 16 | |
105 | #define SCA_MAX_PORTS 4 | |
106 | #define SCAMAXDESC 128 | |
107 | ||
108 | #define BUFFERLISTSIZE 4096 | |
109 | ||
110 | /* SCA-I style DMA buffer descriptor */ | |
111 | typedef struct _SCADESC | |
112 | { | |
113 | u16 next; /* lower l6 bits of next descriptor addr */ | |
114 | u16 buf_ptr; /* lower 16 bits of buffer addr */ | |
115 | u8 buf_base; /* upper 8 bits of buffer addr */ | |
116 | u8 pad1; | |
117 | u16 length; /* length of buffer */ | |
118 | u8 status; /* status of buffer */ | |
119 | u8 pad2; | |
120 | } SCADESC, *PSCADESC; | |
121 | ||
122 | typedef struct _SCADESC_EX | |
123 | { | |
124 | /* device driver bookkeeping section */ | |
125 | char *virt_addr; /* virtual address of data buffer */ | |
126 | u16 phys_entry; /* lower 16-bits of physical address of this descriptor */ | |
127 | } SCADESC_EX, *PSCADESC_EX; | |
128 | ||
129 | /* The queue of BH actions to be performed */ | |
130 | ||
131 | #define BH_RECEIVE 1 | |
132 | #define BH_TRANSMIT 2 | |
133 | #define BH_STATUS 4 | |
134 | ||
135 | #define IO_PIN_SHUTDOWN_LIMIT 100 | |
136 | ||
1da177e4 LT |
137 | struct _input_signal_events { |
138 | int ri_up; | |
139 | int ri_down; | |
140 | int dsr_up; | |
141 | int dsr_down; | |
142 | int dcd_up; | |
143 | int dcd_down; | |
144 | int cts_up; | |
145 | int cts_down; | |
146 | }; | |
147 | ||
148 | /* | |
149 | * Device instance data structure | |
150 | */ | |
151 | typedef struct _synclinkmp_info { | |
152 | void *if_ptr; /* General purpose pointer (used by SPPP) */ | |
153 | int magic; | |
8fb06c77 | 154 | struct tty_port port; |
1da177e4 LT |
155 | int line; |
156 | unsigned short close_delay; | |
157 | unsigned short closing_wait; /* time to wait before closing */ | |
158 | ||
159 | struct mgsl_icount icount; | |
160 | ||
1da177e4 LT |
161 | int timeout; |
162 | int x_char; /* xon/xoff character */ | |
1da177e4 LT |
163 | u16 read_status_mask1; /* break detection (SR1 indications) */ |
164 | u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */ | |
165 | unsigned char ignore_status_mask1; /* break detection (SR1 indications) */ | |
166 | unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */ | |
167 | unsigned char *tx_buf; | |
168 | int tx_put; | |
169 | int tx_get; | |
170 | int tx_count; | |
171 | ||
1da177e4 LT |
172 | wait_queue_head_t status_event_wait_q; |
173 | wait_queue_head_t event_wait_q; | |
174 | struct timer_list tx_timer; /* HDLC transmit timeout timer */ | |
175 | struct _synclinkmp_info *next_device; /* device list link */ | |
176 | struct timer_list status_timer; /* input signal status check timer */ | |
177 | ||
178 | spinlock_t lock; /* spinlock for synchronizing with ISR */ | |
179 | struct work_struct task; /* task structure for scheduling bh */ | |
180 | ||
181 | u32 max_frame_size; /* as set by device config */ | |
182 | ||
183 | u32 pending_bh; | |
184 | ||
0fab6de0 | 185 | bool bh_running; /* Protection from multiple */ |
1da177e4 | 186 | int isr_overflow; |
0fab6de0 | 187 | bool bh_requested; |
1da177e4 LT |
188 | |
189 | int dcd_chkcount; /* check counts to prevent */ | |
190 | int cts_chkcount; /* too many IRQs if a signal */ | |
191 | int dsr_chkcount; /* is floating */ | |
192 | int ri_chkcount; | |
193 | ||
194 | char *buffer_list; /* virtual address of Rx & Tx buffer lists */ | |
195 | unsigned long buffer_list_phys; | |
196 | ||
197 | unsigned int rx_buf_count; /* count of total allocated Rx buffers */ | |
198 | SCADESC *rx_buf_list; /* list of receive buffer entries */ | |
199 | SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */ | |
200 | unsigned int current_rx_buf; | |
201 | ||
202 | unsigned int tx_buf_count; /* count of total allocated Tx buffers */ | |
203 | SCADESC *tx_buf_list; /* list of transmit buffer entries */ | |
204 | SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */ | |
205 | unsigned int last_tx_buf; | |
206 | ||
207 | unsigned char *tmp_rx_buf; | |
208 | unsigned int tmp_rx_buf_count; | |
209 | ||
0fab6de0 JP |
210 | bool rx_enabled; |
211 | bool rx_overflow; | |
1da177e4 | 212 | |
0fab6de0 JP |
213 | bool tx_enabled; |
214 | bool tx_active; | |
1da177e4 LT |
215 | u32 idle_mode; |
216 | ||
217 | unsigned char ie0_value; | |
218 | unsigned char ie1_value; | |
219 | unsigned char ie2_value; | |
220 | unsigned char ctrlreg_value; | |
221 | unsigned char old_signals; | |
222 | ||
223 | char device_name[25]; /* device instance name */ | |
224 | ||
225 | int port_count; | |
226 | int adapter_num; | |
227 | int port_num; | |
228 | ||
229 | struct _synclinkmp_info *port_array[SCA_MAX_PORTS]; | |
230 | ||
231 | unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */ | |
232 | ||
233 | unsigned int irq_level; /* interrupt level */ | |
234 | unsigned long irq_flags; | |
0fab6de0 | 235 | bool irq_requested; /* true if IRQ requested */ |
1da177e4 LT |
236 | |
237 | MGSL_PARAMS params; /* communications parameters */ | |
238 | ||
239 | unsigned char serial_signals; /* current serial signal states */ | |
240 | ||
0fab6de0 | 241 | bool irq_occurred; /* for diagnostics use */ |
1da177e4 LT |
242 | unsigned int init_error; /* Initialization startup error */ |
243 | ||
244 | u32 last_mem_alloc; | |
245 | unsigned char* memory_base; /* shared memory address (PCI only) */ | |
246 | u32 phys_memory_base; | |
247 | int shared_mem_requested; | |
248 | ||
249 | unsigned char* sca_base; /* HD64570 SCA Memory address */ | |
250 | u32 phys_sca_base; | |
251 | u32 sca_offset; | |
0fab6de0 | 252 | bool sca_base_requested; |
1da177e4 LT |
253 | |
254 | unsigned char* lcr_base; /* local config registers (PCI only) */ | |
255 | u32 phys_lcr_base; | |
256 | u32 lcr_offset; | |
257 | int lcr_mem_requested; | |
258 | ||
259 | unsigned char* statctrl_base; /* status/control register memory */ | |
260 | u32 phys_statctrl_base; | |
261 | u32 statctrl_offset; | |
0fab6de0 | 262 | bool sca_statctrl_requested; |
1da177e4 LT |
263 | |
264 | u32 misc_ctrl_value; | |
a6b68a69 | 265 | char *flag_buf; |
0fab6de0 | 266 | bool drop_rts_on_tx_done; |
1da177e4 LT |
267 | |
268 | struct _input_signal_events input_signal_events; | |
269 | ||
270 | /* SPPP/Cisco HDLC device parts */ | |
271 | int netcount; | |
1da177e4 LT |
272 | spinlock_t netlock; |
273 | ||
af69c7f9 | 274 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
275 | struct net_device *netdev; |
276 | #endif | |
277 | ||
278 | } SLMP_INFO; | |
279 | ||
280 | #define MGSL_MAGIC 0x5401 | |
281 | ||
282 | /* | |
283 | * define serial signal status change macros | |
284 | */ | |
285 | #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */ | |
286 | #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */ | |
287 | #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */ | |
288 | #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */ | |
289 | ||
290 | /* Common Register macros */ | |
291 | #define LPR 0x00 | |
292 | #define PABR0 0x02 | |
293 | #define PABR1 0x03 | |
294 | #define WCRL 0x04 | |
295 | #define WCRM 0x05 | |
296 | #define WCRH 0x06 | |
297 | #define DPCR 0x08 | |
298 | #define DMER 0x09 | |
299 | #define ISR0 0x10 | |
300 | #define ISR1 0x11 | |
301 | #define ISR2 0x12 | |
302 | #define IER0 0x14 | |
303 | #define IER1 0x15 | |
304 | #define IER2 0x16 | |
305 | #define ITCR 0x18 | |
306 | #define INTVR 0x1a | |
307 | #define IMVR 0x1c | |
308 | ||
309 | /* MSCI Register macros */ | |
310 | #define TRB 0x20 | |
311 | #define TRBL 0x20 | |
312 | #define TRBH 0x21 | |
313 | #define SR0 0x22 | |
314 | #define SR1 0x23 | |
315 | #define SR2 0x24 | |
316 | #define SR3 0x25 | |
317 | #define FST 0x26 | |
318 | #define IE0 0x28 | |
319 | #define IE1 0x29 | |
320 | #define IE2 0x2a | |
321 | #define FIE 0x2b | |
322 | #define CMD 0x2c | |
323 | #define MD0 0x2e | |
324 | #define MD1 0x2f | |
325 | #define MD2 0x30 | |
326 | #define CTL 0x31 | |
327 | #define SA0 0x32 | |
328 | #define SA1 0x33 | |
329 | #define IDL 0x34 | |
330 | #define TMC 0x35 | |
331 | #define RXS 0x36 | |
332 | #define TXS 0x37 | |
333 | #define TRC0 0x38 | |
334 | #define TRC1 0x39 | |
335 | #define RRC 0x3a | |
336 | #define CST0 0x3c | |
337 | #define CST1 0x3d | |
338 | ||
339 | /* Timer Register Macros */ | |
340 | #define TCNT 0x60 | |
341 | #define TCNTL 0x60 | |
342 | #define TCNTH 0x61 | |
343 | #define TCONR 0x62 | |
344 | #define TCONRL 0x62 | |
345 | #define TCONRH 0x63 | |
346 | #define TMCS 0x64 | |
347 | #define TEPR 0x65 | |
348 | ||
349 | /* DMA Controller Register macros */ | |
350 | #define DARL 0x80 | |
351 | #define DARH 0x81 | |
352 | #define DARB 0x82 | |
353 | #define BAR 0x80 | |
354 | #define BARL 0x80 | |
355 | #define BARH 0x81 | |
356 | #define BARB 0x82 | |
357 | #define SAR 0x84 | |
358 | #define SARL 0x84 | |
359 | #define SARH 0x85 | |
360 | #define SARB 0x86 | |
361 | #define CPB 0x86 | |
362 | #define CDA 0x88 | |
363 | #define CDAL 0x88 | |
364 | #define CDAH 0x89 | |
365 | #define EDA 0x8a | |
366 | #define EDAL 0x8a | |
367 | #define EDAH 0x8b | |
368 | #define BFL 0x8c | |
369 | #define BFLL 0x8c | |
370 | #define BFLH 0x8d | |
371 | #define BCR 0x8e | |
372 | #define BCRL 0x8e | |
373 | #define BCRH 0x8f | |
374 | #define DSR 0x90 | |
375 | #define DMR 0x91 | |
376 | #define FCT 0x93 | |
377 | #define DIR 0x94 | |
378 | #define DCMD 0x95 | |
379 | ||
380 | /* combine with timer or DMA register address */ | |
381 | #define TIMER0 0x00 | |
382 | #define TIMER1 0x08 | |
383 | #define TIMER2 0x10 | |
384 | #define TIMER3 0x18 | |
385 | #define RXDMA 0x00 | |
386 | #define TXDMA 0x20 | |
387 | ||
388 | /* SCA Command Codes */ | |
389 | #define NOOP 0x00 | |
390 | #define TXRESET 0x01 | |
391 | #define TXENABLE 0x02 | |
392 | #define TXDISABLE 0x03 | |
393 | #define TXCRCINIT 0x04 | |
394 | #define TXCRCEXCL 0x05 | |
395 | #define TXEOM 0x06 | |
396 | #define TXABORT 0x07 | |
397 | #define MPON 0x08 | |
398 | #define TXBUFCLR 0x09 | |
399 | #define RXRESET 0x11 | |
400 | #define RXENABLE 0x12 | |
401 | #define RXDISABLE 0x13 | |
402 | #define RXCRCINIT 0x14 | |
403 | #define RXREJECT 0x15 | |
404 | #define SEARCHMP 0x16 | |
405 | #define RXCRCEXCL 0x17 | |
406 | #define RXCRCCALC 0x18 | |
407 | #define CHRESET 0x21 | |
408 | #define HUNT 0x31 | |
409 | ||
410 | /* DMA command codes */ | |
411 | #define SWABORT 0x01 | |
412 | #define FEICLEAR 0x02 | |
413 | ||
414 | /* IE0 */ | |
415 | #define TXINTE BIT7 | |
416 | #define RXINTE BIT6 | |
417 | #define TXRDYE BIT1 | |
418 | #define RXRDYE BIT0 | |
419 | ||
420 | /* IE1 & SR1 */ | |
421 | #define UDRN BIT7 | |
422 | #define IDLE BIT6 | |
423 | #define SYNCD BIT4 | |
424 | #define FLGD BIT4 | |
425 | #define CCTS BIT3 | |
426 | #define CDCD BIT2 | |
427 | #define BRKD BIT1 | |
428 | #define ABTD BIT1 | |
429 | #define GAPD BIT1 | |
430 | #define BRKE BIT0 | |
431 | #define IDLD BIT0 | |
432 | ||
433 | /* IE2 & SR2 */ | |
434 | #define EOM BIT7 | |
435 | #define PMP BIT6 | |
436 | #define SHRT BIT6 | |
437 | #define PE BIT5 | |
438 | #define ABT BIT5 | |
439 | #define FRME BIT4 | |
440 | #define RBIT BIT4 | |
441 | #define OVRN BIT3 | |
442 | #define CRCE BIT2 | |
443 | ||
444 | ||
445 | /* | |
446 | * Global linked list of SyncLink devices | |
447 | */ | |
448 | static SLMP_INFO *synclinkmp_device_list = NULL; | |
449 | static int synclinkmp_adapter_count = -1; | |
450 | static int synclinkmp_device_count = 0; | |
451 | ||
452 | /* | |
453 | * Set this param to non-zero to load eax with the | |
454 | * .text section address and breakpoint on module load. | |
455 | * This is useful for use with gdb and add-symbol-file command. | |
456 | */ | |
90ab5ee9 | 457 | static bool break_on_load = 0; |
1da177e4 LT |
458 | |
459 | /* | |
460 | * Driver major number, defaults to zero to get auto | |
461 | * assigned major number. May be forced as module parameter. | |
462 | */ | |
8fb06c77 | 463 | static int ttymajor = 0; |
1da177e4 LT |
464 | |
465 | /* | |
466 | * Array of user specified options for ISA adapters. | |
467 | */ | |
468 | static int debug_level = 0; | |
469 | static int maxframe[MAX_DEVICES] = {0,}; | |
1da177e4 LT |
470 | |
471 | module_param(break_on_load, bool, 0); | |
472 | module_param(ttymajor, int, 0); | |
473 | module_param(debug_level, int, 0); | |
474 | module_param_array(maxframe, int, NULL, 0); | |
1da177e4 LT |
475 | |
476 | static char *driver_name = "SyncLink MultiPort driver"; | |
7f3edb94 | 477 | static char *driver_version = "$Revision: 4.38 $"; |
1da177e4 LT |
478 | |
479 | static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent); | |
480 | static void synclinkmp_remove_one(struct pci_dev *dev); | |
481 | ||
482 | static struct pci_device_id synclinkmp_pci_tbl[] = { | |
483 | { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, }, | |
484 | { 0, }, /* terminate list */ | |
485 | }; | |
486 | MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl); | |
487 | ||
488 | MODULE_LICENSE("GPL"); | |
489 | ||
490 | static struct pci_driver synclinkmp_pci_driver = { | |
491 | .name = "synclinkmp", | |
492 | .id_table = synclinkmp_pci_tbl, | |
493 | .probe = synclinkmp_init_one, | |
91116cba | 494 | .remove = synclinkmp_remove_one, |
1da177e4 LT |
495 | }; |
496 | ||
497 | ||
498 | static struct tty_driver *serial_driver; | |
499 | ||
500 | /* number of characters left in xmit buffer before we ask for more */ | |
501 | #define WAKEUP_CHARS 256 | |
502 | ||
503 | ||
504 | /* tty callbacks */ | |
505 | ||
506 | static int open(struct tty_struct *tty, struct file * filp); | |
507 | static void close(struct tty_struct *tty, struct file * filp); | |
508 | static void hangup(struct tty_struct *tty); | |
606d099c | 509 | static void set_termios(struct tty_struct *tty, struct ktermios *old_termios); |
1da177e4 LT |
510 | |
511 | static int write(struct tty_struct *tty, const unsigned char *buf, int count); | |
55da7789 | 512 | static int put_char(struct tty_struct *tty, unsigned char ch); |
1da177e4 LT |
513 | static void send_xchar(struct tty_struct *tty, char ch); |
514 | static void wait_until_sent(struct tty_struct *tty, int timeout); | |
515 | static int write_room(struct tty_struct *tty); | |
516 | static void flush_chars(struct tty_struct *tty); | |
517 | static void flush_buffer(struct tty_struct *tty); | |
518 | static void tx_hold(struct tty_struct *tty); | |
519 | static void tx_release(struct tty_struct *tty); | |
520 | ||
6caa76b7 | 521 | static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg); |
1da177e4 LT |
522 | static int chars_in_buffer(struct tty_struct *tty); |
523 | static void throttle(struct tty_struct * tty); | |
524 | static void unthrottle(struct tty_struct * tty); | |
9e98966c | 525 | static int set_break(struct tty_struct *tty, int break_state); |
1da177e4 | 526 | |
af69c7f9 | 527 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
528 | #define dev_to_port(D) (dev_to_hdlc(D)->priv) |
529 | static void hdlcdev_tx_done(SLMP_INFO *info); | |
530 | static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size); | |
531 | static int hdlcdev_init(SLMP_INFO *info); | |
532 | static void hdlcdev_exit(SLMP_INFO *info); | |
533 | #endif | |
534 | ||
535 | /* ioctl handlers */ | |
536 | ||
537 | static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount); | |
538 | static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params); | |
539 | static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params); | |
540 | static int get_txidle(SLMP_INFO *info, int __user *idle_mode); | |
541 | static int set_txidle(SLMP_INFO *info, int idle_mode); | |
542 | static int tx_enable(SLMP_INFO *info, int enable); | |
543 | static int tx_abort(SLMP_INFO *info); | |
544 | static int rx_enable(SLMP_INFO *info, int enable); | |
1da177e4 LT |
545 | static int modem_input_wait(SLMP_INFO *info,int arg); |
546 | static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr); | |
60b33c13 | 547 | static int tiocmget(struct tty_struct *tty); |
20b9d177 AC |
548 | static int tiocmset(struct tty_struct *tty, |
549 | unsigned int set, unsigned int clear); | |
9e98966c | 550 | static int set_break(struct tty_struct *tty, int break_state); |
1da177e4 LT |
551 | |
552 | static void add_device(SLMP_INFO *info); | |
553 | static void device_init(int adapter_num, struct pci_dev *pdev); | |
554 | static int claim_resources(SLMP_INFO *info); | |
555 | static void release_resources(SLMP_INFO *info); | |
556 | ||
557 | static int startup(SLMP_INFO *info); | |
558 | static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info); | |
31f35939 | 559 | static int carrier_raised(struct tty_port *port); |
1da177e4 LT |
560 | static void shutdown(SLMP_INFO *info); |
561 | static void program_hw(SLMP_INFO *info); | |
562 | static void change_params(SLMP_INFO *info); | |
563 | ||
0fab6de0 JP |
564 | static bool init_adapter(SLMP_INFO *info); |
565 | static bool register_test(SLMP_INFO *info); | |
566 | static bool irq_test(SLMP_INFO *info); | |
567 | static bool loopback_test(SLMP_INFO *info); | |
1da177e4 | 568 | static int adapter_test(SLMP_INFO *info); |
0fab6de0 | 569 | static bool memory_test(SLMP_INFO *info); |
1da177e4 LT |
570 | |
571 | static void reset_adapter(SLMP_INFO *info); | |
572 | static void reset_port(SLMP_INFO *info); | |
573 | static void async_mode(SLMP_INFO *info); | |
574 | static void hdlc_mode(SLMP_INFO *info); | |
575 | ||
576 | static void rx_stop(SLMP_INFO *info); | |
577 | static void rx_start(SLMP_INFO *info); | |
578 | static void rx_reset_buffers(SLMP_INFO *info); | |
579 | static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last); | |
0fab6de0 | 580 | static bool rx_get_frame(SLMP_INFO *info); |
1da177e4 LT |
581 | |
582 | static void tx_start(SLMP_INFO *info); | |
583 | static void tx_stop(SLMP_INFO *info); | |
584 | static void tx_load_fifo(SLMP_INFO *info); | |
585 | static void tx_set_idle(SLMP_INFO *info); | |
586 | static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count); | |
587 | ||
588 | static void get_signals(SLMP_INFO *info); | |
589 | static void set_signals(SLMP_INFO *info); | |
590 | static void enable_loopback(SLMP_INFO *info, int enable); | |
591 | static void set_rate(SLMP_INFO *info, u32 data_rate); | |
592 | ||
593 | static int bh_action(SLMP_INFO *info); | |
c4028958 | 594 | static void bh_handler(struct work_struct *work); |
1da177e4 LT |
595 | static void bh_receive(SLMP_INFO *info); |
596 | static void bh_transmit(SLMP_INFO *info); | |
597 | static void bh_status(SLMP_INFO *info); | |
598 | static void isr_timer(SLMP_INFO *info); | |
599 | static void isr_rxint(SLMP_INFO *info); | |
600 | static void isr_rxrdy(SLMP_INFO *info); | |
601 | static void isr_txint(SLMP_INFO *info); | |
602 | static void isr_txrdy(SLMP_INFO *info); | |
603 | static void isr_rxdmaok(SLMP_INFO *info); | |
604 | static void isr_rxdmaerror(SLMP_INFO *info); | |
605 | static void isr_txdmaok(SLMP_INFO *info); | |
606 | static void isr_txdmaerror(SLMP_INFO *info); | |
607 | static void isr_io_pin(SLMP_INFO *info, u16 status); | |
608 | ||
609 | static int alloc_dma_bufs(SLMP_INFO *info); | |
610 | static void free_dma_bufs(SLMP_INFO *info); | |
611 | static int alloc_buf_list(SLMP_INFO *info); | |
612 | static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count); | |
613 | static int alloc_tmp_rx_buf(SLMP_INFO *info); | |
614 | static void free_tmp_rx_buf(SLMP_INFO *info); | |
615 | ||
616 | static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count); | |
617 | static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit); | |
618 | static void tx_timeout(unsigned long context); | |
619 | static void status_timeout(unsigned long context); | |
620 | ||
621 | static unsigned char read_reg(SLMP_INFO *info, unsigned char addr); | |
622 | static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val); | |
623 | static u16 read_reg16(SLMP_INFO *info, unsigned char addr); | |
624 | static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val); | |
625 | static unsigned char read_status_reg(SLMP_INFO * info); | |
626 | static void write_control_reg(SLMP_INFO * info); | |
627 | ||
628 | ||
629 | static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes | |
630 | static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes | |
631 | static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes | |
632 | ||
633 | static u32 misc_ctrl_value = 0x007e4040; | |
761a444d | 634 | static u32 lcr1_brdr_value = 0x00800028; |
1da177e4 LT |
635 | |
636 | static u32 read_ahead_count = 8; | |
637 | ||
638 | /* DPCR, DMA Priority Control | |
639 | * | |
640 | * 07..05 Not used, must be 0 | |
641 | * 04 BRC, bus release condition: 0=all transfers complete | |
642 | * 1=release after 1 xfer on all channels | |
643 | * 03 CCC, channel change condition: 0=every cycle | |
644 | * 1=after each channel completes all xfers | |
645 | * 02..00 PR<2..0>, priority 100=round robin | |
646 | * | |
647 | * 00000100 = 0x00 | |
648 | */ | |
649 | static unsigned char dma_priority = 0x04; | |
650 | ||
651 | // Number of bytes that can be written to shared RAM | |
652 | // in a single write operation | |
653 | static u32 sca_pci_load_interval = 64; | |
654 | ||
655 | /* | |
656 | * 1st function defined in .text section. Calling this function in | |
657 | * init_module() followed by a breakpoint allows a remote debugger | |
658 | * (gdb) to get the .text address for the add-symbol-file command. | |
659 | * This allows remote debugging of dynamically loadable modules. | |
660 | */ | |
661 | static void* synclinkmp_get_text_ptr(void); | |
662 | static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;} | |
663 | ||
664 | static inline int sanity_check(SLMP_INFO *info, | |
665 | char *name, const char *routine) | |
666 | { | |
667 | #ifdef SANITY_CHECK | |
668 | static const char *badmagic = | |
669 | "Warning: bad magic number for synclinkmp_struct (%s) in %s\n"; | |
670 | static const char *badinfo = | |
671 | "Warning: null synclinkmp_struct for (%s) in %s\n"; | |
672 | ||
673 | if (!info) { | |
674 | printk(badinfo, name, routine); | |
675 | return 1; | |
676 | } | |
677 | if (info->magic != MGSL_MAGIC) { | |
678 | printk(badmagic, name, routine); | |
679 | return 1; | |
680 | } | |
681 | #else | |
682 | if (!info) | |
683 | return 1; | |
684 | #endif | |
685 | return 0; | |
686 | } | |
687 | ||
688 | /** | |
689 | * line discipline callback wrappers | |
690 | * | |
691 | * The wrappers maintain line discipline references | |
692 | * while calling into the line discipline. | |
693 | * | |
694 | * ldisc_receive_buf - pass receive data to line discipline | |
695 | */ | |
696 | ||
697 | static void ldisc_receive_buf(struct tty_struct *tty, | |
698 | const __u8 *data, char *flags, int count) | |
699 | { | |
700 | struct tty_ldisc *ld; | |
701 | if (!tty) | |
702 | return; | |
703 | ld = tty_ldisc_ref(tty); | |
704 | if (ld) { | |
a352def2 AC |
705 | if (ld->ops->receive_buf) |
706 | ld->ops->receive_buf(tty, data, flags, count); | |
1da177e4 LT |
707 | tty_ldisc_deref(ld); |
708 | } | |
709 | } | |
710 | ||
711 | /* tty callbacks */ | |
712 | ||
ee3b48da | 713 | static int install(struct tty_driver *driver, struct tty_struct *tty) |
1da177e4 LT |
714 | { |
715 | SLMP_INFO *info; | |
ee3b48da | 716 | int line = tty->index; |
1da177e4 | 717 | |
410235fd | 718 | if (line >= synclinkmp_device_count) { |
1da177e4 LT |
719 | printk("%s(%d): open with invalid line #%d.\n", |
720 | __FILE__,__LINE__,line); | |
721 | return -ENODEV; | |
722 | } | |
723 | ||
724 | info = synclinkmp_device_list; | |
ee3b48da | 725 | while (info && info->line != line) |
1da177e4 LT |
726 | info = info->next_device; |
727 | if (sanity_check(info, tty->name, "open")) | |
728 | return -ENODEV; | |
ee3b48da | 729 | if (info->init_error) { |
1da177e4 | 730 | printk("%s(%d):%s device is not allocated, init error=%d\n", |
ee3b48da JS |
731 | __FILE__, __LINE__, info->device_name, |
732 | info->init_error); | |
1da177e4 LT |
733 | return -ENODEV; |
734 | } | |
735 | ||
736 | tty->driver_data = info; | |
ee3b48da JS |
737 | |
738 | return tty_port_install(&info->port, driver, tty); | |
739 | } | |
740 | ||
741 | /* Called when a port is opened. Init and enable port. | |
742 | */ | |
743 | static int open(struct tty_struct *tty, struct file *filp) | |
744 | { | |
745 | SLMP_INFO *info = tty->driver_data; | |
746 | unsigned long flags; | |
747 | int retval; | |
748 | ||
8fb06c77 | 749 | info->port.tty = tty; |
1da177e4 LT |
750 | |
751 | if (debug_level >= DEBUG_LEVEL_INFO) | |
752 | printk("%s(%d):%s open(), old ref count = %d\n", | |
8fb06c77 | 753 | __FILE__,__LINE__,tty->driver->name, info->port.count); |
1da177e4 | 754 | |
d6c53c0e | 755 | info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; |
1da177e4 LT |
756 | |
757 | spin_lock_irqsave(&info->netlock, flags); | |
758 | if (info->netcount) { | |
759 | retval = -EBUSY; | |
760 | spin_unlock_irqrestore(&info->netlock, flags); | |
761 | goto cleanup; | |
762 | } | |
8fb06c77 | 763 | info->port.count++; |
1da177e4 LT |
764 | spin_unlock_irqrestore(&info->netlock, flags); |
765 | ||
8fb06c77 | 766 | if (info->port.count == 1) { |
1da177e4 LT |
767 | /* 1st open on this device, init hardware */ |
768 | retval = startup(info); | |
769 | if (retval < 0) | |
770 | goto cleanup; | |
771 | } | |
772 | ||
773 | retval = block_til_ready(tty, filp, info); | |
774 | if (retval) { | |
775 | if (debug_level >= DEBUG_LEVEL_INFO) | |
776 | printk("%s(%d):%s block_til_ready() returned %d\n", | |
777 | __FILE__,__LINE__, info->device_name, retval); | |
778 | goto cleanup; | |
779 | } | |
780 | ||
781 | if (debug_level >= DEBUG_LEVEL_INFO) | |
782 | printk("%s(%d):%s open() success\n", | |
783 | __FILE__,__LINE__, info->device_name); | |
784 | retval = 0; | |
785 | ||
786 | cleanup: | |
787 | if (retval) { | |
788 | if (tty->count == 1) | |
8fb06c77 AC |
789 | info->port.tty = NULL; /* tty layer will release tty struct */ |
790 | if(info->port.count) | |
791 | info->port.count--; | |
1da177e4 LT |
792 | } |
793 | ||
794 | return retval; | |
795 | } | |
796 | ||
797 | /* Called when port is closed. Wait for remaining data to be | |
798 | * sent. Disable port and free resources. | |
799 | */ | |
800 | static void close(struct tty_struct *tty, struct file *filp) | |
801 | { | |
c9f19e96 | 802 | SLMP_INFO * info = tty->driver_data; |
1da177e4 LT |
803 | |
804 | if (sanity_check(info, tty->name, "close")) | |
805 | return; | |
806 | ||
807 | if (debug_level >= DEBUG_LEVEL_INFO) | |
808 | printk("%s(%d):%s close() entry, count=%d\n", | |
8fb06c77 | 809 | __FILE__,__LINE__, info->device_name, info->port.count); |
1da177e4 | 810 | |
a6614999 | 811 | if (tty_port_close_start(&info->port, tty, filp) == 0) |
1da177e4 | 812 | goto cleanup; |
a360fae6 AC |
813 | |
814 | mutex_lock(&info->port.mutex); | |
8fb06c77 | 815 | if (info->port.flags & ASYNC_INITIALIZED) |
1da177e4 LT |
816 | wait_until_sent(tty, info->timeout); |
817 | ||
978e595f | 818 | flush_buffer(tty); |
1da177e4 | 819 | tty_ldisc_flush(tty); |
1da177e4 | 820 | shutdown(info); |
a360fae6 | 821 | mutex_unlock(&info->port.mutex); |
1da177e4 | 822 | |
a6614999 | 823 | tty_port_close_end(&info->port, tty); |
8fb06c77 | 824 | info->port.tty = NULL; |
1da177e4 LT |
825 | cleanup: |
826 | if (debug_level >= DEBUG_LEVEL_INFO) | |
827 | printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__, | |
8fb06c77 | 828 | tty->driver->name, info->port.count); |
1da177e4 LT |
829 | } |
830 | ||
831 | /* Called by tty_hangup() when a hangup is signaled. | |
832 | * This is the same as closing all open descriptors for the port. | |
833 | */ | |
834 | static void hangup(struct tty_struct *tty) | |
835 | { | |
c9f19e96 | 836 | SLMP_INFO *info = tty->driver_data; |
a360fae6 | 837 | unsigned long flags; |
1da177e4 LT |
838 | |
839 | if (debug_level >= DEBUG_LEVEL_INFO) | |
840 | printk("%s(%d):%s hangup()\n", | |
841 | __FILE__,__LINE__, info->device_name ); | |
842 | ||
843 | if (sanity_check(info, tty->name, "hangup")) | |
844 | return; | |
845 | ||
a360fae6 | 846 | mutex_lock(&info->port.mutex); |
1da177e4 LT |
847 | flush_buffer(tty); |
848 | shutdown(info); | |
849 | ||
a360fae6 | 850 | spin_lock_irqsave(&info->port.lock, flags); |
8fb06c77 AC |
851 | info->port.count = 0; |
852 | info->port.flags &= ~ASYNC_NORMAL_ACTIVE; | |
853 | info->port.tty = NULL; | |
a360fae6 AC |
854 | spin_unlock_irqrestore(&info->port.lock, flags); |
855 | mutex_unlock(&info->port.mutex); | |
1da177e4 | 856 | |
8fb06c77 | 857 | wake_up_interruptible(&info->port.open_wait); |
1da177e4 LT |
858 | } |
859 | ||
860 | /* Set new termios settings | |
861 | */ | |
606d099c | 862 | static void set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
1da177e4 | 863 | { |
c9f19e96 | 864 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
865 | unsigned long flags; |
866 | ||
867 | if (debug_level >= DEBUG_LEVEL_INFO) | |
868 | printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__, | |
869 | tty->driver->name ); | |
870 | ||
1da177e4 LT |
871 | change_params(info); |
872 | ||
873 | /* Handle transition to B0 status */ | |
874 | if (old_termios->c_cflag & CBAUD && | |
adc8d746 | 875 | !(tty->termios.c_cflag & CBAUD)) { |
9fe8074b | 876 | info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); |
1da177e4 LT |
877 | spin_lock_irqsave(&info->lock,flags); |
878 | set_signals(info); | |
879 | spin_unlock_irqrestore(&info->lock,flags); | |
880 | } | |
881 | ||
882 | /* Handle transition away from B0 status */ | |
883 | if (!(old_termios->c_cflag & CBAUD) && | |
adc8d746 | 884 | tty->termios.c_cflag & CBAUD) { |
1da177e4 | 885 | info->serial_signals |= SerialSignal_DTR; |
adc8d746 | 886 | if (!(tty->termios.c_cflag & CRTSCTS) || |
1da177e4 LT |
887 | !test_bit(TTY_THROTTLED, &tty->flags)) { |
888 | info->serial_signals |= SerialSignal_RTS; | |
889 | } | |
890 | spin_lock_irqsave(&info->lock,flags); | |
891 | set_signals(info); | |
892 | spin_unlock_irqrestore(&info->lock,flags); | |
893 | } | |
894 | ||
895 | /* Handle turning off CRTSCTS */ | |
896 | if (old_termios->c_cflag & CRTSCTS && | |
adc8d746 | 897 | !(tty->termios.c_cflag & CRTSCTS)) { |
1da177e4 LT |
898 | tty->hw_stopped = 0; |
899 | tx_release(tty); | |
900 | } | |
901 | } | |
902 | ||
903 | /* Send a block of data | |
904 | * | |
905 | * Arguments: | |
906 | * | |
907 | * tty pointer to tty information structure | |
908 | * buf pointer to buffer containing send data | |
909 | * count size of send data in bytes | |
910 | * | |
911 | * Return Value: number of characters written | |
912 | */ | |
913 | static int write(struct tty_struct *tty, | |
914 | const unsigned char *buf, int count) | |
915 | { | |
916 | int c, ret = 0; | |
c9f19e96 | 917 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
918 | unsigned long flags; |
919 | ||
920 | if (debug_level >= DEBUG_LEVEL_INFO) | |
921 | printk("%s(%d):%s write() count=%d\n", | |
922 | __FILE__,__LINE__,info->device_name,count); | |
923 | ||
924 | if (sanity_check(info, tty->name, "write")) | |
925 | goto cleanup; | |
926 | ||
326f28e9 | 927 | if (!info->tx_buf) |
1da177e4 LT |
928 | goto cleanup; |
929 | ||
930 | if (info->params.mode == MGSL_MODE_HDLC) { | |
931 | if (count > info->max_frame_size) { | |
932 | ret = -EIO; | |
933 | goto cleanup; | |
934 | } | |
935 | if (info->tx_active) | |
936 | goto cleanup; | |
937 | if (info->tx_count) { | |
938 | /* send accumulated data from send_char() calls */ | |
939 | /* as frame and wait before accepting more data. */ | |
940 | tx_load_dma_buffer(info, info->tx_buf, info->tx_count); | |
941 | goto start; | |
942 | } | |
943 | ret = info->tx_count = count; | |
944 | tx_load_dma_buffer(info, buf, count); | |
945 | goto start; | |
946 | } | |
947 | ||
948 | for (;;) { | |
949 | c = min_t(int, count, | |
950 | min(info->max_frame_size - info->tx_count - 1, | |
951 | info->max_frame_size - info->tx_put)); | |
952 | if (c <= 0) | |
953 | break; | |
954 | ||
955 | memcpy(info->tx_buf + info->tx_put, buf, c); | |
956 | ||
957 | spin_lock_irqsave(&info->lock,flags); | |
958 | info->tx_put += c; | |
959 | if (info->tx_put >= info->max_frame_size) | |
960 | info->tx_put -= info->max_frame_size; | |
961 | info->tx_count += c; | |
962 | spin_unlock_irqrestore(&info->lock,flags); | |
963 | ||
964 | buf += c; | |
965 | count -= c; | |
966 | ret += c; | |
967 | } | |
968 | ||
969 | if (info->params.mode == MGSL_MODE_HDLC) { | |
970 | if (count) { | |
971 | ret = info->tx_count = 0; | |
972 | goto cleanup; | |
973 | } | |
974 | tx_load_dma_buffer(info, info->tx_buf, info->tx_count); | |
975 | } | |
976 | start: | |
977 | if (info->tx_count && !tty->stopped && !tty->hw_stopped) { | |
978 | spin_lock_irqsave(&info->lock,flags); | |
979 | if (!info->tx_active) | |
980 | tx_start(info); | |
981 | spin_unlock_irqrestore(&info->lock,flags); | |
982 | } | |
983 | ||
984 | cleanup: | |
985 | if (debug_level >= DEBUG_LEVEL_INFO) | |
986 | printk( "%s(%d):%s write() returning=%d\n", | |
987 | __FILE__,__LINE__,info->device_name,ret); | |
988 | return ret; | |
989 | } | |
990 | ||
991 | /* Add a character to the transmit buffer. | |
992 | */ | |
55da7789 | 993 | static int put_char(struct tty_struct *tty, unsigned char ch) |
1da177e4 | 994 | { |
c9f19e96 | 995 | SLMP_INFO *info = tty->driver_data; |
1da177e4 | 996 | unsigned long flags; |
55da7789 | 997 | int ret = 0; |
1da177e4 LT |
998 | |
999 | if ( debug_level >= DEBUG_LEVEL_INFO ) { | |
1000 | printk( "%s(%d):%s put_char(%d)\n", | |
1001 | __FILE__,__LINE__,info->device_name,ch); | |
1002 | } | |
1003 | ||
1004 | if (sanity_check(info, tty->name, "put_char")) | |
55da7789 | 1005 | return 0; |
1da177e4 | 1006 | |
326f28e9 | 1007 | if (!info->tx_buf) |
55da7789 | 1008 | return 0; |
1da177e4 LT |
1009 | |
1010 | spin_lock_irqsave(&info->lock,flags); | |
1011 | ||
1012 | if ( (info->params.mode != MGSL_MODE_HDLC) || | |
1013 | !info->tx_active ) { | |
1014 | ||
1015 | if (info->tx_count < info->max_frame_size - 1) { | |
1016 | info->tx_buf[info->tx_put++] = ch; | |
1017 | if (info->tx_put >= info->max_frame_size) | |
1018 | info->tx_put -= info->max_frame_size; | |
1019 | info->tx_count++; | |
55da7789 | 1020 | ret = 1; |
1da177e4 LT |
1021 | } |
1022 | } | |
1023 | ||
1024 | spin_unlock_irqrestore(&info->lock,flags); | |
55da7789 | 1025 | return ret; |
1da177e4 LT |
1026 | } |
1027 | ||
1028 | /* Send a high-priority XON/XOFF character | |
1029 | */ | |
1030 | static void send_xchar(struct tty_struct *tty, char ch) | |
1031 | { | |
c9f19e96 | 1032 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
1033 | unsigned long flags; |
1034 | ||
1035 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1036 | printk("%s(%d):%s send_xchar(%d)\n", | |
1037 | __FILE__,__LINE__, info->device_name, ch ); | |
1038 | ||
1039 | if (sanity_check(info, tty->name, "send_xchar")) | |
1040 | return; | |
1041 | ||
1042 | info->x_char = ch; | |
1043 | if (ch) { | |
1044 | /* Make sure transmit interrupts are on */ | |
1045 | spin_lock_irqsave(&info->lock,flags); | |
1046 | if (!info->tx_enabled) | |
1047 | tx_start(info); | |
1048 | spin_unlock_irqrestore(&info->lock,flags); | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | /* Wait until the transmitter is empty. | |
1053 | */ | |
1054 | static void wait_until_sent(struct tty_struct *tty, int timeout) | |
1055 | { | |
c9f19e96 | 1056 | SLMP_INFO * info = tty->driver_data; |
1da177e4 LT |
1057 | unsigned long orig_jiffies, char_time; |
1058 | ||
1059 | if (!info ) | |
1060 | return; | |
1061 | ||
1062 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1063 | printk("%s(%d):%s wait_until_sent() entry\n", | |
1064 | __FILE__,__LINE__, info->device_name ); | |
1065 | ||
1066 | if (sanity_check(info, tty->name, "wait_until_sent")) | |
1067 | return; | |
1068 | ||
f602501d | 1069 | if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags)) |
1da177e4 LT |
1070 | goto exit; |
1071 | ||
1072 | orig_jiffies = jiffies; | |
1073 | ||
1074 | /* Set check interval to 1/5 of estimated time to | |
1075 | * send a character, and make it at least 1. The check | |
1076 | * interval should also be less than the timeout. | |
1077 | * Note: use tight timings here to satisfy the NIST-PCTS. | |
1078 | */ | |
1079 | ||
1080 | if ( info->params.data_rate ) { | |
1081 | char_time = info->timeout/(32 * 5); | |
1082 | if (!char_time) | |
1083 | char_time++; | |
1084 | } else | |
1085 | char_time = 1; | |
1086 | ||
1087 | if (timeout) | |
1088 | char_time = min_t(unsigned long, char_time, timeout); | |
1089 | ||
1090 | if ( info->params.mode == MGSL_MODE_HDLC ) { | |
1091 | while (info->tx_active) { | |
1092 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
1093 | if (signal_pending(current)) | |
1094 | break; | |
1095 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
1096 | break; | |
1097 | } | |
1098 | } else { | |
f602501d AC |
1099 | /* |
1100 | * TODO: determine if there is something similar to USC16C32 | |
1101 | * TXSTATUS_ALL_SENT status | |
1102 | */ | |
1da177e4 LT |
1103 | while ( info->tx_active && info->tx_enabled) { |
1104 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
1105 | if (signal_pending(current)) | |
1106 | break; | |
1107 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
1108 | break; | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | exit: | |
1113 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1114 | printk("%s(%d):%s wait_until_sent() exit\n", | |
1115 | __FILE__,__LINE__, info->device_name ); | |
1116 | } | |
1117 | ||
1118 | /* Return the count of free bytes in transmit buffer | |
1119 | */ | |
1120 | static int write_room(struct tty_struct *tty) | |
1121 | { | |
c9f19e96 | 1122 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
1123 | int ret; |
1124 | ||
1125 | if (sanity_check(info, tty->name, "write_room")) | |
1126 | return 0; | |
1127 | ||
1128 | if (info->params.mode == MGSL_MODE_HDLC) { | |
1129 | ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE; | |
1130 | } else { | |
1131 | ret = info->max_frame_size - info->tx_count - 1; | |
1132 | if (ret < 0) | |
1133 | ret = 0; | |
1134 | } | |
1135 | ||
1136 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1137 | printk("%s(%d):%s write_room()=%d\n", | |
1138 | __FILE__, __LINE__, info->device_name, ret); | |
1139 | ||
1140 | return ret; | |
1141 | } | |
1142 | ||
1143 | /* enable transmitter and send remaining buffered characters | |
1144 | */ | |
1145 | static void flush_chars(struct tty_struct *tty) | |
1146 | { | |
c9f19e96 | 1147 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
1148 | unsigned long flags; |
1149 | ||
1150 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
1151 | printk( "%s(%d):%s flush_chars() entry tx_count=%d\n", | |
1152 | __FILE__,__LINE__,info->device_name,info->tx_count); | |
1153 | ||
1154 | if (sanity_check(info, tty->name, "flush_chars")) | |
1155 | return; | |
1156 | ||
1157 | if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped || | |
1158 | !info->tx_buf) | |
1159 | return; | |
1160 | ||
1161 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
1162 | printk( "%s(%d):%s flush_chars() entry, starting transmitter\n", | |
1163 | __FILE__,__LINE__,info->device_name ); | |
1164 | ||
1165 | spin_lock_irqsave(&info->lock,flags); | |
1166 | ||
1167 | if (!info->tx_active) { | |
1168 | if ( (info->params.mode == MGSL_MODE_HDLC) && | |
1169 | info->tx_count ) { | |
1170 | /* operating in synchronous (frame oriented) mode */ | |
1171 | /* copy data from circular tx_buf to */ | |
1172 | /* transmit DMA buffer. */ | |
1173 | tx_load_dma_buffer(info, | |
1174 | info->tx_buf,info->tx_count); | |
1175 | } | |
1176 | tx_start(info); | |
1177 | } | |
1178 | ||
1179 | spin_unlock_irqrestore(&info->lock,flags); | |
1180 | } | |
1181 | ||
1182 | /* Discard all data in the send buffer | |
1183 | */ | |
1184 | static void flush_buffer(struct tty_struct *tty) | |
1185 | { | |
c9f19e96 | 1186 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
1187 | unsigned long flags; |
1188 | ||
1189 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1190 | printk("%s(%d):%s flush_buffer() entry\n", | |
1191 | __FILE__,__LINE__, info->device_name ); | |
1192 | ||
1193 | if (sanity_check(info, tty->name, "flush_buffer")) | |
1194 | return; | |
1195 | ||
1196 | spin_lock_irqsave(&info->lock,flags); | |
1197 | info->tx_count = info->tx_put = info->tx_get = 0; | |
1198 | del_timer(&info->tx_timer); | |
1199 | spin_unlock_irqrestore(&info->lock,flags); | |
1200 | ||
1da177e4 LT |
1201 | tty_wakeup(tty); |
1202 | } | |
1203 | ||
1204 | /* throttle (stop) transmitter | |
1205 | */ | |
1206 | static void tx_hold(struct tty_struct *tty) | |
1207 | { | |
c9f19e96 | 1208 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
1209 | unsigned long flags; |
1210 | ||
1211 | if (sanity_check(info, tty->name, "tx_hold")) | |
1212 | return; | |
1213 | ||
1214 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
1215 | printk("%s(%d):%s tx_hold()\n", | |
1216 | __FILE__,__LINE__,info->device_name); | |
1217 | ||
1218 | spin_lock_irqsave(&info->lock,flags); | |
1219 | if (info->tx_enabled) | |
1220 | tx_stop(info); | |
1221 | spin_unlock_irqrestore(&info->lock,flags); | |
1222 | } | |
1223 | ||
1224 | /* release (start) transmitter | |
1225 | */ | |
1226 | static void tx_release(struct tty_struct *tty) | |
1227 | { | |
c9f19e96 | 1228 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
1229 | unsigned long flags; |
1230 | ||
1231 | if (sanity_check(info, tty->name, "tx_release")) | |
1232 | return; | |
1233 | ||
1234 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
1235 | printk("%s(%d):%s tx_release()\n", | |
1236 | __FILE__,__LINE__,info->device_name); | |
1237 | ||
1238 | spin_lock_irqsave(&info->lock,flags); | |
1239 | if (!info->tx_enabled) | |
1240 | tx_start(info); | |
1241 | spin_unlock_irqrestore(&info->lock,flags); | |
1242 | } | |
1243 | ||
1244 | /* Service an IOCTL request | |
1245 | * | |
1246 | * Arguments: | |
1247 | * | |
1248 | * tty pointer to tty instance data | |
1da177e4 LT |
1249 | * cmd IOCTL command code |
1250 | * arg command argument/context | |
1251 | * | |
1252 | * Return Value: 0 if success, otherwise error code | |
1253 | */ | |
6caa76b7 | 1254 | static int ioctl(struct tty_struct *tty, |
1da177e4 LT |
1255 | unsigned int cmd, unsigned long arg) |
1256 | { | |
c9f19e96 | 1257 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
1258 | void __user *argp = (void __user *)arg; |
1259 | ||
1260 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1261 | printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__, | |
1262 | info->device_name, cmd ); | |
1263 | ||
1264 | if (sanity_check(info, tty->name, "ioctl")) | |
1265 | return -ENODEV; | |
1266 | ||
1267 | if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && | |
0587102c | 1268 | (cmd != TIOCMIWAIT)) { |
1da177e4 LT |
1269 | if (tty->flags & (1 << TTY_IO_ERROR)) |
1270 | return -EIO; | |
1271 | } | |
1272 | ||
1273 | switch (cmd) { | |
1274 | case MGSL_IOCGPARAMS: | |
1275 | return get_params(info, argp); | |
1276 | case MGSL_IOCSPARAMS: | |
1277 | return set_params(info, argp); | |
1278 | case MGSL_IOCGTXIDLE: | |
1279 | return get_txidle(info, argp); | |
1280 | case MGSL_IOCSTXIDLE: | |
1281 | return set_txidle(info, (int)arg); | |
1282 | case MGSL_IOCTXENABLE: | |
1283 | return tx_enable(info, (int)arg); | |
1284 | case MGSL_IOCRXENABLE: | |
1285 | return rx_enable(info, (int)arg); | |
1286 | case MGSL_IOCTXABORT: | |
1287 | return tx_abort(info); | |
1288 | case MGSL_IOCGSTATS: | |
1289 | return get_stats(info, argp); | |
1290 | case MGSL_IOCWAITEVENT: | |
1291 | return wait_mgsl_event(info, argp); | |
1292 | case MGSL_IOCLOOPTXDONE: | |
1293 | return 0; // TODO: Not supported, need to document | |
1294 | /* Wait for modem input (DCD,RI,DSR,CTS) change | |
1295 | * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS) | |
1296 | */ | |
1297 | case TIOCMIWAIT: | |
1298 | return modem_input_wait(info,(int)arg); | |
1299 | ||
1300 | /* | |
1301 | * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) | |
1302 | * Return: write counters to the user passed counter struct | |
1303 | * NB: both 1->0 and 0->1 transitions are counted except for | |
1304 | * RI where only 0->1 is counted. | |
1305 | */ | |
1da177e4 LT |
1306 | default: |
1307 | return -ENOIOCTLCMD; | |
1308 | } | |
1309 | return 0; | |
1310 | } | |
1311 | ||
0587102c AC |
1312 | static int get_icount(struct tty_struct *tty, |
1313 | struct serial_icounter_struct *icount) | |
1314 | { | |
1315 | SLMP_INFO *info = tty->driver_data; | |
1316 | struct mgsl_icount cnow; /* kernel counter temps */ | |
1317 | unsigned long flags; | |
1318 | ||
1319 | spin_lock_irqsave(&info->lock,flags); | |
1320 | cnow = info->icount; | |
1321 | spin_unlock_irqrestore(&info->lock,flags); | |
1322 | ||
1323 | icount->cts = cnow.cts; | |
1324 | icount->dsr = cnow.dsr; | |
1325 | icount->rng = cnow.rng; | |
1326 | icount->dcd = cnow.dcd; | |
1327 | icount->rx = cnow.rx; | |
1328 | icount->tx = cnow.tx; | |
1329 | icount->frame = cnow.frame; | |
1330 | icount->overrun = cnow.overrun; | |
1331 | icount->parity = cnow.parity; | |
1332 | icount->brk = cnow.brk; | |
1333 | icount->buf_overrun = cnow.buf_overrun; | |
1334 | ||
1335 | return 0; | |
1336 | } | |
1337 | ||
1da177e4 LT |
1338 | /* |
1339 | * /proc fs routines.... | |
1340 | */ | |
1341 | ||
e6c8dd8a | 1342 | static inline void line_info(struct seq_file *m, SLMP_INFO *info) |
1da177e4 LT |
1343 | { |
1344 | char stat_buf[30]; | |
1da177e4 LT |
1345 | unsigned long flags; |
1346 | ||
e6c8dd8a | 1347 | seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n" |
1da177e4 LT |
1348 | "\tIRQ=%d MaxFrameSize=%u\n", |
1349 | info->device_name, | |
1350 | info->phys_sca_base, | |
1351 | info->phys_memory_base, | |
1352 | info->phys_statctrl_base, | |
1353 | info->phys_lcr_base, | |
1354 | info->irq_level, | |
1355 | info->max_frame_size ); | |
1356 | ||
1357 | /* output current serial signal states */ | |
1358 | spin_lock_irqsave(&info->lock,flags); | |
1359 | get_signals(info); | |
1360 | spin_unlock_irqrestore(&info->lock,flags); | |
1361 | ||
1362 | stat_buf[0] = 0; | |
1363 | stat_buf[1] = 0; | |
1364 | if (info->serial_signals & SerialSignal_RTS) | |
1365 | strcat(stat_buf, "|RTS"); | |
1366 | if (info->serial_signals & SerialSignal_CTS) | |
1367 | strcat(stat_buf, "|CTS"); | |
1368 | if (info->serial_signals & SerialSignal_DTR) | |
1369 | strcat(stat_buf, "|DTR"); | |
1370 | if (info->serial_signals & SerialSignal_DSR) | |
1371 | strcat(stat_buf, "|DSR"); | |
1372 | if (info->serial_signals & SerialSignal_DCD) | |
1373 | strcat(stat_buf, "|CD"); | |
1374 | if (info->serial_signals & SerialSignal_RI) | |
1375 | strcat(stat_buf, "|RI"); | |
1376 | ||
1377 | if (info->params.mode == MGSL_MODE_HDLC) { | |
e6c8dd8a | 1378 | seq_printf(m, "\tHDLC txok:%d rxok:%d", |
1da177e4 LT |
1379 | info->icount.txok, info->icount.rxok); |
1380 | if (info->icount.txunder) | |
e6c8dd8a | 1381 | seq_printf(m, " txunder:%d", info->icount.txunder); |
1da177e4 | 1382 | if (info->icount.txabort) |
e6c8dd8a | 1383 | seq_printf(m, " txabort:%d", info->icount.txabort); |
1da177e4 | 1384 | if (info->icount.rxshort) |
e6c8dd8a | 1385 | seq_printf(m, " rxshort:%d", info->icount.rxshort); |
1da177e4 | 1386 | if (info->icount.rxlong) |
e6c8dd8a | 1387 | seq_printf(m, " rxlong:%d", info->icount.rxlong); |
1da177e4 | 1388 | if (info->icount.rxover) |
e6c8dd8a | 1389 | seq_printf(m, " rxover:%d", info->icount.rxover); |
1da177e4 | 1390 | if (info->icount.rxcrc) |
e6c8dd8a | 1391 | seq_printf(m, " rxlong:%d", info->icount.rxcrc); |
1da177e4 | 1392 | } else { |
e6c8dd8a | 1393 | seq_printf(m, "\tASYNC tx:%d rx:%d", |
1da177e4 LT |
1394 | info->icount.tx, info->icount.rx); |
1395 | if (info->icount.frame) | |
e6c8dd8a | 1396 | seq_printf(m, " fe:%d", info->icount.frame); |
1da177e4 | 1397 | if (info->icount.parity) |
e6c8dd8a | 1398 | seq_printf(m, " pe:%d", info->icount.parity); |
1da177e4 | 1399 | if (info->icount.brk) |
e6c8dd8a | 1400 | seq_printf(m, " brk:%d", info->icount.brk); |
1da177e4 | 1401 | if (info->icount.overrun) |
e6c8dd8a | 1402 | seq_printf(m, " oe:%d", info->icount.overrun); |
1da177e4 LT |
1403 | } |
1404 | ||
1405 | /* Append serial signal status to end */ | |
e6c8dd8a | 1406 | seq_printf(m, " %s\n", stat_buf+1); |
1da177e4 | 1407 | |
e6c8dd8a | 1408 | seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", |
1da177e4 LT |
1409 | info->tx_active,info->bh_requested,info->bh_running, |
1410 | info->pending_bh); | |
1da177e4 LT |
1411 | } |
1412 | ||
1413 | /* Called to print information about devices | |
1414 | */ | |
e6c8dd8a | 1415 | static int synclinkmp_proc_show(struct seq_file *m, void *v) |
1da177e4 | 1416 | { |
1da177e4 LT |
1417 | SLMP_INFO *info; |
1418 | ||
e6c8dd8a | 1419 | seq_printf(m, "synclinkmp driver:%s\n", driver_version); |
1da177e4 LT |
1420 | |
1421 | info = synclinkmp_device_list; | |
1422 | while( info ) { | |
e6c8dd8a | 1423 | line_info(m, info); |
1da177e4 LT |
1424 | info = info->next_device; |
1425 | } | |
e6c8dd8a AD |
1426 | return 0; |
1427 | } | |
1da177e4 | 1428 | |
e6c8dd8a AD |
1429 | static int synclinkmp_proc_open(struct inode *inode, struct file *file) |
1430 | { | |
1431 | return single_open(file, synclinkmp_proc_show, NULL); | |
1da177e4 LT |
1432 | } |
1433 | ||
e6c8dd8a AD |
1434 | static const struct file_operations synclinkmp_proc_fops = { |
1435 | .owner = THIS_MODULE, | |
1436 | .open = synclinkmp_proc_open, | |
1437 | .read = seq_read, | |
1438 | .llseek = seq_lseek, | |
1439 | .release = single_release, | |
1440 | }; | |
1441 | ||
1da177e4 LT |
1442 | /* Return the count of bytes in transmit buffer |
1443 | */ | |
1444 | static int chars_in_buffer(struct tty_struct *tty) | |
1445 | { | |
c9f19e96 | 1446 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
1447 | |
1448 | if (sanity_check(info, tty->name, "chars_in_buffer")) | |
1449 | return 0; | |
1450 | ||
1451 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1452 | printk("%s(%d):%s chars_in_buffer()=%d\n", | |
1453 | __FILE__, __LINE__, info->device_name, info->tx_count); | |
1454 | ||
1455 | return info->tx_count; | |
1456 | } | |
1457 | ||
1458 | /* Signal remote device to throttle send data (our receive data) | |
1459 | */ | |
1460 | static void throttle(struct tty_struct * tty) | |
1461 | { | |
c9f19e96 | 1462 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
1463 | unsigned long flags; |
1464 | ||
1465 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1466 | printk("%s(%d):%s throttle() entry\n", | |
1467 | __FILE__,__LINE__, info->device_name ); | |
1468 | ||
1469 | if (sanity_check(info, tty->name, "throttle")) | |
1470 | return; | |
1471 | ||
1472 | if (I_IXOFF(tty)) | |
1473 | send_xchar(tty, STOP_CHAR(tty)); | |
1474 | ||
adc8d746 | 1475 | if (tty->termios.c_cflag & CRTSCTS) { |
1da177e4 LT |
1476 | spin_lock_irqsave(&info->lock,flags); |
1477 | info->serial_signals &= ~SerialSignal_RTS; | |
1478 | set_signals(info); | |
1479 | spin_unlock_irqrestore(&info->lock,flags); | |
1480 | } | |
1481 | } | |
1482 | ||
1483 | /* Signal remote device to stop throttling send data (our receive data) | |
1484 | */ | |
1485 | static void unthrottle(struct tty_struct * tty) | |
1486 | { | |
c9f19e96 | 1487 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
1488 | unsigned long flags; |
1489 | ||
1490 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1491 | printk("%s(%d):%s unthrottle() entry\n", | |
1492 | __FILE__,__LINE__, info->device_name ); | |
1493 | ||
1494 | if (sanity_check(info, tty->name, "unthrottle")) | |
1495 | return; | |
1496 | ||
1497 | if (I_IXOFF(tty)) { | |
1498 | if (info->x_char) | |
1499 | info->x_char = 0; | |
1500 | else | |
1501 | send_xchar(tty, START_CHAR(tty)); | |
1502 | } | |
1503 | ||
adc8d746 | 1504 | if (tty->termios.c_cflag & CRTSCTS) { |
1da177e4 LT |
1505 | spin_lock_irqsave(&info->lock,flags); |
1506 | info->serial_signals |= SerialSignal_RTS; | |
1507 | set_signals(info); | |
1508 | spin_unlock_irqrestore(&info->lock,flags); | |
1509 | } | |
1510 | } | |
1511 | ||
1512 | /* set or clear transmit break condition | |
1513 | * break_state -1=set break condition, 0=clear | |
1514 | */ | |
9e98966c | 1515 | static int set_break(struct tty_struct *tty, int break_state) |
1da177e4 LT |
1516 | { |
1517 | unsigned char RegValue; | |
c9f19e96 | 1518 | SLMP_INFO * info = tty->driver_data; |
1da177e4 LT |
1519 | unsigned long flags; |
1520 | ||
1521 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1522 | printk("%s(%d):%s set_break(%d)\n", | |
1523 | __FILE__,__LINE__, info->device_name, break_state); | |
1524 | ||
1525 | if (sanity_check(info, tty->name, "set_break")) | |
9e98966c | 1526 | return -EINVAL; |
1da177e4 LT |
1527 | |
1528 | spin_lock_irqsave(&info->lock,flags); | |
1529 | RegValue = read_reg(info, CTL); | |
1530 | if (break_state == -1) | |
1531 | RegValue |= BIT3; | |
1532 | else | |
1533 | RegValue &= ~BIT3; | |
1534 | write_reg(info, CTL, RegValue); | |
1535 | spin_unlock_irqrestore(&info->lock,flags); | |
9e98966c | 1536 | return 0; |
1da177e4 LT |
1537 | } |
1538 | ||
af69c7f9 | 1539 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
1540 | |
1541 | /** | |
1542 | * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) | |
1543 | * set encoding and frame check sequence (FCS) options | |
1544 | * | |
1545 | * dev pointer to network device structure | |
1546 | * encoding serial encoding setting | |
1547 | * parity FCS setting | |
1548 | * | |
1549 | * returns 0 if success, otherwise error code | |
1550 | */ | |
1551 | static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, | |
1552 | unsigned short parity) | |
1553 | { | |
1554 | SLMP_INFO *info = dev_to_port(dev); | |
1555 | unsigned char new_encoding; | |
1556 | unsigned short new_crctype; | |
1557 | ||
1558 | /* return error if TTY interface open */ | |
8fb06c77 | 1559 | if (info->port.count) |
1da177e4 LT |
1560 | return -EBUSY; |
1561 | ||
1562 | switch (encoding) | |
1563 | { | |
1564 | case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; | |
1565 | case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; | |
1566 | case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; | |
1567 | case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; | |
1568 | case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; | |
1569 | default: return -EINVAL; | |
1570 | } | |
1571 | ||
1572 | switch (parity) | |
1573 | { | |
1574 | case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; | |
1575 | case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; | |
1576 | case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; | |
1577 | default: return -EINVAL; | |
1578 | } | |
1579 | ||
1580 | info->params.encoding = new_encoding; | |
53b3531b | 1581 | info->params.crc_type = new_crctype; |
1da177e4 LT |
1582 | |
1583 | /* if network interface up, reprogram hardware */ | |
1584 | if (info->netcount) | |
1585 | program_hw(info); | |
1586 | ||
1587 | return 0; | |
1588 | } | |
1589 | ||
1590 | /** | |
1591 | * called by generic HDLC layer to send frame | |
1592 | * | |
1593 | * skb socket buffer containing HDLC frame | |
1594 | * dev pointer to network device structure | |
1da177e4 | 1595 | */ |
4c5d502d SH |
1596 | static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, |
1597 | struct net_device *dev) | |
1da177e4 LT |
1598 | { |
1599 | SLMP_INFO *info = dev_to_port(dev); | |
1da177e4 LT |
1600 | unsigned long flags; |
1601 | ||
1602 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1603 | printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name); | |
1604 | ||
1605 | /* stop sending until this frame completes */ | |
1606 | netif_stop_queue(dev); | |
1607 | ||
1608 | /* copy data to device buffers */ | |
1609 | info->tx_count = skb->len; | |
1610 | tx_load_dma_buffer(info, skb->data, skb->len); | |
1611 | ||
1612 | /* update network statistics */ | |
198191c4 KH |
1613 | dev->stats.tx_packets++; |
1614 | dev->stats.tx_bytes += skb->len; | |
1da177e4 LT |
1615 | |
1616 | /* done with socket buffer, so free it */ | |
1617 | dev_kfree_skb(skb); | |
1618 | ||
1619 | /* save start time for transmit timeout detection */ | |
1620 | dev->trans_start = jiffies; | |
1621 | ||
1622 | /* start hardware transmitter if necessary */ | |
1623 | spin_lock_irqsave(&info->lock,flags); | |
1624 | if (!info->tx_active) | |
1625 | tx_start(info); | |
1626 | spin_unlock_irqrestore(&info->lock,flags); | |
1627 | ||
4c5d502d | 1628 | return NETDEV_TX_OK; |
1da177e4 LT |
1629 | } |
1630 | ||
1631 | /** | |
1632 | * called by network layer when interface enabled | |
1633 | * claim resources and initialize hardware | |
1634 | * | |
1635 | * dev pointer to network device structure | |
1636 | * | |
1637 | * returns 0 if success, otherwise error code | |
1638 | */ | |
1639 | static int hdlcdev_open(struct net_device *dev) | |
1640 | { | |
1641 | SLMP_INFO *info = dev_to_port(dev); | |
1642 | int rc; | |
1643 | unsigned long flags; | |
1644 | ||
1645 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1646 | printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name); | |
1647 | ||
1648 | /* generic HDLC layer open processing */ | |
485e148d GKH |
1649 | rc = hdlc_open(dev); |
1650 | if (rc) | |
1da177e4 LT |
1651 | return rc; |
1652 | ||
1653 | /* arbitrate between network and tty opens */ | |
1654 | spin_lock_irqsave(&info->netlock, flags); | |
8fb06c77 | 1655 | if (info->port.count != 0 || info->netcount != 0) { |
1da177e4 LT |
1656 | printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name); |
1657 | spin_unlock_irqrestore(&info->netlock, flags); | |
1658 | return -EBUSY; | |
1659 | } | |
1660 | info->netcount=1; | |
1661 | spin_unlock_irqrestore(&info->netlock, flags); | |
1662 | ||
1663 | /* claim resources and init adapter */ | |
1664 | if ((rc = startup(info)) != 0) { | |
1665 | spin_lock_irqsave(&info->netlock, flags); | |
1666 | info->netcount=0; | |
1667 | spin_unlock_irqrestore(&info->netlock, flags); | |
1668 | return rc; | |
1669 | } | |
1670 | ||
9fe8074b JP |
1671 | /* assert RTS and DTR, apply hardware settings */ |
1672 | info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; | |
1da177e4 LT |
1673 | program_hw(info); |
1674 | ||
1675 | /* enable network layer transmit */ | |
1676 | dev->trans_start = jiffies; | |
1677 | netif_start_queue(dev); | |
1678 | ||
1679 | /* inform generic HDLC layer of current DCD status */ | |
1680 | spin_lock_irqsave(&info->lock, flags); | |
1681 | get_signals(info); | |
1682 | spin_unlock_irqrestore(&info->lock, flags); | |
fbeff3c1 KH |
1683 | if (info->serial_signals & SerialSignal_DCD) |
1684 | netif_carrier_on(dev); | |
1685 | else | |
1686 | netif_carrier_off(dev); | |
1da177e4 LT |
1687 | return 0; |
1688 | } | |
1689 | ||
1690 | /** | |
1691 | * called by network layer when interface is disabled | |
1692 | * shutdown hardware and release resources | |
1693 | * | |
1694 | * dev pointer to network device structure | |
1695 | * | |
1696 | * returns 0 if success, otherwise error code | |
1697 | */ | |
1698 | static int hdlcdev_close(struct net_device *dev) | |
1699 | { | |
1700 | SLMP_INFO *info = dev_to_port(dev); | |
1701 | unsigned long flags; | |
1702 | ||
1703 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1704 | printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name); | |
1705 | ||
1706 | netif_stop_queue(dev); | |
1707 | ||
1708 | /* shutdown adapter and release resources */ | |
1709 | shutdown(info); | |
1710 | ||
1711 | hdlc_close(dev); | |
1712 | ||
1713 | spin_lock_irqsave(&info->netlock, flags); | |
1714 | info->netcount=0; | |
1715 | spin_unlock_irqrestore(&info->netlock, flags); | |
1716 | ||
1717 | return 0; | |
1718 | } | |
1719 | ||
1720 | /** | |
1721 | * called by network layer to process IOCTL call to network device | |
1722 | * | |
1723 | * dev pointer to network device structure | |
1724 | * ifr pointer to network interface request structure | |
1725 | * cmd IOCTL command code | |
1726 | * | |
1727 | * returns 0 if success, otherwise error code | |
1728 | */ | |
1729 | static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1730 | { | |
1731 | const size_t size = sizeof(sync_serial_settings); | |
1732 | sync_serial_settings new_line; | |
1733 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | |
1734 | SLMP_INFO *info = dev_to_port(dev); | |
1735 | unsigned int flags; | |
1736 | ||
1737 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1738 | printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name); | |
1739 | ||
1740 | /* return error if TTY interface open */ | |
8fb06c77 | 1741 | if (info->port.count) |
1da177e4 LT |
1742 | return -EBUSY; |
1743 | ||
1744 | if (cmd != SIOCWANDEV) | |
1745 | return hdlc_ioctl(dev, ifr, cmd); | |
1746 | ||
1747 | switch(ifr->ifr_settings.type) { | |
1748 | case IF_GET_IFACE: /* return current sync_serial_settings */ | |
1749 | ||
1750 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; | |
1751 | if (ifr->ifr_settings.size < size) { | |
1752 | ifr->ifr_settings.size = size; /* data size wanted */ | |
1753 | return -ENOBUFS; | |
1754 | } | |
1755 | ||
1756 | flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1757 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1758 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1759 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1760 | ||
b19a47e0 | 1761 | memset(&new_line, 0, sizeof(new_line)); |
1da177e4 LT |
1762 | switch (flags){ |
1763 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; | |
1764 | case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; | |
1765 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; | |
1766 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; | |
1767 | default: new_line.clock_type = CLOCK_DEFAULT; | |
1768 | } | |
1769 | ||
1770 | new_line.clock_rate = info->params.clock_speed; | |
1771 | new_line.loopback = info->params.loopback ? 1:0; | |
1772 | ||
1773 | if (copy_to_user(line, &new_line, size)) | |
1774 | return -EFAULT; | |
1775 | return 0; | |
1776 | ||
1777 | case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ | |
1778 | ||
1779 | if(!capable(CAP_NET_ADMIN)) | |
1780 | return -EPERM; | |
1781 | if (copy_from_user(&new_line, line, size)) | |
1782 | return -EFAULT; | |
1783 | ||
1784 | switch (new_line.clock_type) | |
1785 | { | |
1786 | case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; | |
1787 | case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; | |
1788 | case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; | |
1789 | case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; | |
1790 | case CLOCK_DEFAULT: flags = info->params.flags & | |
1791 | (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1792 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1793 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1794 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; | |
1795 | default: return -EINVAL; | |
1796 | } | |
1797 | ||
1798 | if (new_line.loopback != 0 && new_line.loopback != 1) | |
1799 | return -EINVAL; | |
1800 | ||
1801 | info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
1802 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
1803 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
1804 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
1805 | info->params.flags |= flags; | |
1806 | ||
1807 | info->params.loopback = new_line.loopback; | |
1808 | ||
1809 | if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) | |
1810 | info->params.clock_speed = new_line.clock_rate; | |
1811 | else | |
1812 | info->params.clock_speed = 0; | |
1813 | ||
1814 | /* if network interface up, reprogram hardware */ | |
1815 | if (info->netcount) | |
1816 | program_hw(info); | |
1817 | return 0; | |
1818 | ||
1819 | default: | |
1820 | return hdlc_ioctl(dev, ifr, cmd); | |
1821 | } | |
1822 | } | |
1823 | ||
1824 | /** | |
1825 | * called by network layer when transmit timeout is detected | |
1826 | * | |
1827 | * dev pointer to network device structure | |
1828 | */ | |
1829 | static void hdlcdev_tx_timeout(struct net_device *dev) | |
1830 | { | |
1831 | SLMP_INFO *info = dev_to_port(dev); | |
1da177e4 LT |
1832 | unsigned long flags; |
1833 | ||
1834 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1835 | printk("hdlcdev_tx_timeout(%s)\n",dev->name); | |
1836 | ||
198191c4 KH |
1837 | dev->stats.tx_errors++; |
1838 | dev->stats.tx_aborted_errors++; | |
1da177e4 LT |
1839 | |
1840 | spin_lock_irqsave(&info->lock,flags); | |
1841 | tx_stop(info); | |
1842 | spin_unlock_irqrestore(&info->lock,flags); | |
1843 | ||
1844 | netif_wake_queue(dev); | |
1845 | } | |
1846 | ||
1847 | /** | |
1848 | * called by device driver when transmit completes | |
1849 | * reenable network layer transmit if stopped | |
1850 | * | |
1851 | * info pointer to device instance information | |
1852 | */ | |
1853 | static void hdlcdev_tx_done(SLMP_INFO *info) | |
1854 | { | |
1855 | if (netif_queue_stopped(info->netdev)) | |
1856 | netif_wake_queue(info->netdev); | |
1857 | } | |
1858 | ||
1859 | /** | |
1860 | * called by device driver when frame received | |
1861 | * pass frame to network layer | |
1862 | * | |
1863 | * info pointer to device instance information | |
1864 | * buf pointer to buffer contianing frame data | |
1865 | * size count of data bytes in buf | |
1866 | */ | |
1867 | static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size) | |
1868 | { | |
1869 | struct sk_buff *skb = dev_alloc_skb(size); | |
1870 | struct net_device *dev = info->netdev; | |
1da177e4 LT |
1871 | |
1872 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1873 | printk("hdlcdev_rx(%s)\n",dev->name); | |
1874 | ||
1875 | if (skb == NULL) { | |
198191c4 KH |
1876 | printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", |
1877 | dev->name); | |
1878 | dev->stats.rx_dropped++; | |
1da177e4 LT |
1879 | return; |
1880 | } | |
1881 | ||
198191c4 | 1882 | memcpy(skb_put(skb, size), buf, size); |
1da177e4 | 1883 | |
198191c4 | 1884 | skb->protocol = hdlc_type_trans(skb, dev); |
1da177e4 | 1885 | |
198191c4 KH |
1886 | dev->stats.rx_packets++; |
1887 | dev->stats.rx_bytes += size; | |
1da177e4 LT |
1888 | |
1889 | netif_rx(skb); | |
1da177e4 LT |
1890 | } |
1891 | ||
991990a1 KH |
1892 | static const struct net_device_ops hdlcdev_ops = { |
1893 | .ndo_open = hdlcdev_open, | |
1894 | .ndo_stop = hdlcdev_close, | |
1895 | .ndo_change_mtu = hdlc_change_mtu, | |
1896 | .ndo_start_xmit = hdlc_start_xmit, | |
1897 | .ndo_do_ioctl = hdlcdev_ioctl, | |
1898 | .ndo_tx_timeout = hdlcdev_tx_timeout, | |
1899 | }; | |
1900 | ||
1da177e4 LT |
1901 | /** |
1902 | * called by device driver when adding device instance | |
1903 | * do generic HDLC initialization | |
1904 | * | |
1905 | * info pointer to device instance information | |
1906 | * | |
1907 | * returns 0 if success, otherwise error code | |
1908 | */ | |
1909 | static int hdlcdev_init(SLMP_INFO *info) | |
1910 | { | |
1911 | int rc; | |
1912 | struct net_device *dev; | |
1913 | hdlc_device *hdlc; | |
1914 | ||
1915 | /* allocate and initialize network and HDLC layer objects */ | |
1916 | ||
485e148d GKH |
1917 | dev = alloc_hdlcdev(info); |
1918 | if (!dev) { | |
1da177e4 LT |
1919 | printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__); |
1920 | return -ENOMEM; | |
1921 | } | |
1922 | ||
1923 | /* for network layer reporting purposes only */ | |
1924 | dev->mem_start = info->phys_sca_base; | |
1925 | dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1; | |
1926 | dev->irq = info->irq_level; | |
1927 | ||
1928 | /* network layer callbacks and settings */ | |
991990a1 KH |
1929 | dev->netdev_ops = &hdlcdev_ops; |
1930 | dev->watchdog_timeo = 10 * HZ; | |
1da177e4 LT |
1931 | dev->tx_queue_len = 50; |
1932 | ||
1933 | /* generic HDLC layer callbacks and settings */ | |
1934 | hdlc = dev_to_hdlc(dev); | |
1935 | hdlc->attach = hdlcdev_attach; | |
1936 | hdlc->xmit = hdlcdev_xmit; | |
1937 | ||
1938 | /* register objects with HDLC layer */ | |
485e148d GKH |
1939 | rc = register_hdlc_device(dev); |
1940 | if (rc) { | |
1da177e4 LT |
1941 | printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); |
1942 | free_netdev(dev); | |
1943 | return rc; | |
1944 | } | |
1945 | ||
1946 | info->netdev = dev; | |
1947 | return 0; | |
1948 | } | |
1949 | ||
1950 | /** | |
1951 | * called by device driver when removing device instance | |
1952 | * do generic HDLC cleanup | |
1953 | * | |
1954 | * info pointer to device instance information | |
1955 | */ | |
1956 | static void hdlcdev_exit(SLMP_INFO *info) | |
1957 | { | |
1958 | unregister_hdlc_device(info->netdev); | |
1959 | free_netdev(info->netdev); | |
1960 | info->netdev = NULL; | |
1961 | } | |
1962 | ||
1963 | #endif /* CONFIG_HDLC */ | |
1964 | ||
1965 | ||
1966 | /* Return next bottom half action to perform. | |
1967 | * Return Value: BH action code or 0 if nothing to do. | |
1968 | */ | |
ce9f9f73 | 1969 | static int bh_action(SLMP_INFO *info) |
1da177e4 LT |
1970 | { |
1971 | unsigned long flags; | |
1972 | int rc = 0; | |
1973 | ||
1974 | spin_lock_irqsave(&info->lock,flags); | |
1975 | ||
1976 | if (info->pending_bh & BH_RECEIVE) { | |
1977 | info->pending_bh &= ~BH_RECEIVE; | |
1978 | rc = BH_RECEIVE; | |
1979 | } else if (info->pending_bh & BH_TRANSMIT) { | |
1980 | info->pending_bh &= ~BH_TRANSMIT; | |
1981 | rc = BH_TRANSMIT; | |
1982 | } else if (info->pending_bh & BH_STATUS) { | |
1983 | info->pending_bh &= ~BH_STATUS; | |
1984 | rc = BH_STATUS; | |
1985 | } | |
1986 | ||
1987 | if (!rc) { | |
1988 | /* Mark BH routine as complete */ | |
0fab6de0 JP |
1989 | info->bh_running = false; |
1990 | info->bh_requested = false; | |
1da177e4 LT |
1991 | } |
1992 | ||
1993 | spin_unlock_irqrestore(&info->lock,flags); | |
1994 | ||
1995 | return rc; | |
1996 | } | |
1997 | ||
1998 | /* Perform bottom half processing of work items queued by ISR. | |
1999 | */ | |
ce9f9f73 | 2000 | static void bh_handler(struct work_struct *work) |
1da177e4 | 2001 | { |
c4028958 | 2002 | SLMP_INFO *info = container_of(work, SLMP_INFO, task); |
1da177e4 LT |
2003 | int action; |
2004 | ||
1da177e4 LT |
2005 | if ( debug_level >= DEBUG_LEVEL_BH ) |
2006 | printk( "%s(%d):%s bh_handler() entry\n", | |
2007 | __FILE__,__LINE__,info->device_name); | |
2008 | ||
0fab6de0 | 2009 | info->bh_running = true; |
1da177e4 LT |
2010 | |
2011 | while((action = bh_action(info)) != 0) { | |
2012 | ||
2013 | /* Process work item */ | |
2014 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
2015 | printk( "%s(%d):%s bh_handler() work item action=%d\n", | |
2016 | __FILE__,__LINE__,info->device_name, action); | |
2017 | ||
2018 | switch (action) { | |
2019 | ||
2020 | case BH_RECEIVE: | |
2021 | bh_receive(info); | |
2022 | break; | |
2023 | case BH_TRANSMIT: | |
2024 | bh_transmit(info); | |
2025 | break; | |
2026 | case BH_STATUS: | |
2027 | bh_status(info); | |
2028 | break; | |
2029 | default: | |
2030 | /* unknown work item ID */ | |
2031 | printk("%s(%d):%s Unknown work item ID=%08X!\n", | |
2032 | __FILE__,__LINE__,info->device_name,action); | |
2033 | break; | |
2034 | } | |
2035 | } | |
2036 | ||
2037 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
2038 | printk( "%s(%d):%s bh_handler() exit\n", | |
2039 | __FILE__,__LINE__,info->device_name); | |
2040 | } | |
2041 | ||
ce9f9f73 | 2042 | static void bh_receive(SLMP_INFO *info) |
1da177e4 LT |
2043 | { |
2044 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
2045 | printk( "%s(%d):%s bh_receive()\n", | |
2046 | __FILE__,__LINE__,info->device_name); | |
2047 | ||
2048 | while( rx_get_frame(info) ); | |
2049 | } | |
2050 | ||
ce9f9f73 | 2051 | static void bh_transmit(SLMP_INFO *info) |
1da177e4 | 2052 | { |
8fb06c77 | 2053 | struct tty_struct *tty = info->port.tty; |
1da177e4 LT |
2054 | |
2055 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
2056 | printk( "%s(%d):%s bh_transmit() entry\n", | |
2057 | __FILE__,__LINE__,info->device_name); | |
2058 | ||
b963a844 | 2059 | if (tty) |
1da177e4 | 2060 | tty_wakeup(tty); |
1da177e4 LT |
2061 | } |
2062 | ||
ce9f9f73 | 2063 | static void bh_status(SLMP_INFO *info) |
1da177e4 LT |
2064 | { |
2065 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
2066 | printk( "%s(%d):%s bh_status() entry\n", | |
2067 | __FILE__,__LINE__,info->device_name); | |
2068 | ||
2069 | info->ri_chkcount = 0; | |
2070 | info->dsr_chkcount = 0; | |
2071 | info->dcd_chkcount = 0; | |
2072 | info->cts_chkcount = 0; | |
2073 | } | |
2074 | ||
ce9f9f73 | 2075 | static void isr_timer(SLMP_INFO * info) |
1da177e4 LT |
2076 | { |
2077 | unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0; | |
2078 | ||
2079 | /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */ | |
2080 | write_reg(info, IER2, 0); | |
2081 | ||
2082 | /* TMCS, Timer Control/Status Register | |
2083 | * | |
2084 | * 07 CMF, Compare match flag (read only) 1=match | |
2085 | * 06 ECMI, CMF Interrupt Enable: 0=disabled | |
2086 | * 05 Reserved, must be 0 | |
2087 | * 04 TME, Timer Enable | |
2088 | * 03..00 Reserved, must be 0 | |
2089 | * | |
2090 | * 0000 0000 | |
2091 | */ | |
2092 | write_reg(info, (unsigned char)(timer + TMCS), 0); | |
2093 | ||
0fab6de0 | 2094 | info->irq_occurred = true; |
1da177e4 LT |
2095 | |
2096 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2097 | printk("%s(%d):%s isr_timer()\n", | |
2098 | __FILE__,__LINE__,info->device_name); | |
2099 | } | |
2100 | ||
ce9f9f73 | 2101 | static void isr_rxint(SLMP_INFO * info) |
1da177e4 | 2102 | { |
8fb06c77 | 2103 | struct tty_struct *tty = info->port.tty; |
1da177e4 LT |
2104 | struct mgsl_icount *icount = &info->icount; |
2105 | unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD); | |
2106 | unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN; | |
2107 | ||
2108 | /* clear status bits */ | |
2109 | if (status) | |
2110 | write_reg(info, SR1, status); | |
2111 | ||
2112 | if (status2) | |
2113 | write_reg(info, SR2, status2); | |
2114 | ||
2115 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2116 | printk("%s(%d):%s isr_rxint status=%02X %02x\n", | |
2117 | __FILE__,__LINE__,info->device_name,status,status2); | |
2118 | ||
2119 | if (info->params.mode == MGSL_MODE_ASYNC) { | |
2120 | if (status & BRKD) { | |
2121 | icount->brk++; | |
2122 | ||
2123 | /* process break detection if tty control | |
2124 | * is not set to ignore it | |
2125 | */ | |
92a19f9c JS |
2126 | if (!(status & info->ignore_status_mask1)) { |
2127 | if (info->read_status_mask1 & BRKD) { | |
2128 | tty_insert_flip_char(&info->port, 0, TTY_BREAK); | |
2129 | if (tty && (info->port.flags & ASYNC_SAK)) | |
2130 | do_SAK(tty); | |
1da177e4 LT |
2131 | } |
2132 | } | |
2133 | } | |
2134 | } | |
2135 | else { | |
2136 | if (status & (FLGD|IDLD)) { | |
2137 | if (status & FLGD) | |
2138 | info->icount.exithunt++; | |
2139 | else if (status & IDLD) | |
2140 | info->icount.rxidle++; | |
2141 | wake_up_interruptible(&info->event_wait_q); | |
2142 | } | |
2143 | } | |
2144 | ||
2145 | if (status & CDCD) { | |
2146 | /* simulate a common modem status change interrupt | |
2147 | * for our handler | |
2148 | */ | |
2149 | get_signals( info ); | |
2150 | isr_io_pin(info, | |
2151 | MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD)); | |
2152 | } | |
2153 | } | |
2154 | ||
2155 | /* | |
2156 | * handle async rx data interrupts | |
2157 | */ | |
ce9f9f73 | 2158 | static void isr_rxrdy(SLMP_INFO * info) |
1da177e4 LT |
2159 | { |
2160 | u16 status; | |
2161 | unsigned char DataByte; | |
1da177e4 LT |
2162 | struct mgsl_icount *icount = &info->icount; |
2163 | ||
2164 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2165 | printk("%s(%d):%s isr_rxrdy\n", | |
2166 | __FILE__,__LINE__,info->device_name); | |
2167 | ||
2168 | while((status = read_reg(info,CST0)) & BIT0) | |
2169 | { | |
33f0f88f | 2170 | int flag = 0; |
0fab6de0 | 2171 | bool over = false; |
1da177e4 LT |
2172 | DataByte = read_reg(info,TRB); |
2173 | ||
1da177e4 LT |
2174 | icount->rx++; |
2175 | ||
2176 | if ( status & (PE + FRME + OVRN) ) { | |
2177 | printk("%s(%d):%s rxerr=%04X\n", | |
2178 | __FILE__,__LINE__,info->device_name,status); | |
2179 | ||
2180 | /* update error statistics */ | |
2181 | if (status & PE) | |
2182 | icount->parity++; | |
2183 | else if (status & FRME) | |
2184 | icount->frame++; | |
2185 | else if (status & OVRN) | |
2186 | icount->overrun++; | |
2187 | ||
2188 | /* discard char if tty control flags say so */ | |
2189 | if (status & info->ignore_status_mask2) | |
2190 | continue; | |
2191 | ||
2192 | status &= info->read_status_mask2; | |
2193 | ||
92a19f9c JS |
2194 | if (status & PE) |
2195 | flag = TTY_PARITY; | |
2196 | else if (status & FRME) | |
2197 | flag = TTY_FRAME; | |
2198 | if (status & OVRN) { | |
2199 | /* Overrun is special, since it's | |
2200 | * reported immediately, and doesn't | |
2201 | * affect the current character | |
2202 | */ | |
2203 | over = true; | |
1da177e4 LT |
2204 | } |
2205 | } /* end of if (error) */ | |
2206 | ||
92a19f9c JS |
2207 | tty_insert_flip_char(&info->port, DataByte, flag); |
2208 | if (over) | |
2209 | tty_insert_flip_char(&info->port, 0, TTY_OVERRUN); | |
1da177e4 LT |
2210 | } |
2211 | ||
2212 | if ( debug_level >= DEBUG_LEVEL_ISR ) { | |
1da177e4 LT |
2213 | printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n", |
2214 | __FILE__,__LINE__,info->device_name, | |
2215 | icount->rx,icount->brk,icount->parity, | |
2216 | icount->frame,icount->overrun); | |
2217 | } | |
2218 | ||
2e124b4a | 2219 | tty_flip_buffer_push(&info->port); |
1da177e4 LT |
2220 | } |
2221 | ||
2222 | static void isr_txeom(SLMP_INFO * info, unsigned char status) | |
2223 | { | |
2224 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2225 | printk("%s(%d):%s isr_txeom status=%02x\n", | |
2226 | __FILE__,__LINE__,info->device_name,status); | |
2227 | ||
2228 | write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ | |
2229 | write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ | |
2230 | write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ | |
2231 | ||
2232 | if (status & UDRN) { | |
2233 | write_reg(info, CMD, TXRESET); | |
2234 | write_reg(info, CMD, TXENABLE); | |
2235 | } else | |
2236 | write_reg(info, CMD, TXBUFCLR); | |
2237 | ||
2238 | /* disable and clear tx interrupts */ | |
2239 | info->ie0_value &= ~TXRDYE; | |
2240 | info->ie1_value &= ~(IDLE + UDRN); | |
2241 | write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value)); | |
2242 | write_reg(info, SR1, (unsigned char)(UDRN + IDLE)); | |
2243 | ||
2244 | if ( info->tx_active ) { | |
2245 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
2246 | if (status & UDRN) | |
2247 | info->icount.txunder++; | |
2248 | else if (status & IDLE) | |
2249 | info->icount.txok++; | |
2250 | } | |
2251 | ||
0fab6de0 | 2252 | info->tx_active = false; |
1da177e4 LT |
2253 | info->tx_count = info->tx_put = info->tx_get = 0; |
2254 | ||
2255 | del_timer(&info->tx_timer); | |
2256 | ||
2257 | if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) { | |
2258 | info->serial_signals &= ~SerialSignal_RTS; | |
0fab6de0 | 2259 | info->drop_rts_on_tx_done = false; |
1da177e4 LT |
2260 | set_signals(info); |
2261 | } | |
2262 | ||
af69c7f9 | 2263 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
2264 | if (info->netcount) |
2265 | hdlcdev_tx_done(info); | |
2266 | else | |
2267 | #endif | |
2268 | { | |
8fb06c77 | 2269 | if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { |
1da177e4 LT |
2270 | tx_stop(info); |
2271 | return; | |
2272 | } | |
2273 | info->pending_bh |= BH_TRANSMIT; | |
2274 | } | |
2275 | } | |
2276 | } | |
2277 | ||
2278 | ||
2279 | /* | |
2280 | * handle tx status interrupts | |
2281 | */ | |
ce9f9f73 | 2282 | static void isr_txint(SLMP_INFO * info) |
1da177e4 LT |
2283 | { |
2284 | unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS); | |
2285 | ||
2286 | /* clear status bits */ | |
2287 | write_reg(info, SR1, status); | |
2288 | ||
2289 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2290 | printk("%s(%d):%s isr_txint status=%02x\n", | |
2291 | __FILE__,__LINE__,info->device_name,status); | |
2292 | ||
2293 | if (status & (UDRN + IDLE)) | |
2294 | isr_txeom(info, status); | |
2295 | ||
2296 | if (status & CCTS) { | |
2297 | /* simulate a common modem status change interrupt | |
2298 | * for our handler | |
2299 | */ | |
2300 | get_signals( info ); | |
2301 | isr_io_pin(info, | |
2302 | MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS)); | |
2303 | ||
2304 | } | |
2305 | } | |
2306 | ||
2307 | /* | |
2308 | * handle async tx data interrupts | |
2309 | */ | |
ce9f9f73 | 2310 | static void isr_txrdy(SLMP_INFO * info) |
1da177e4 LT |
2311 | { |
2312 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2313 | printk("%s(%d):%s isr_txrdy() tx_count=%d\n", | |
2314 | __FILE__,__LINE__,info->device_name,info->tx_count); | |
2315 | ||
2316 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
2317 | /* disable TXRDY IRQ, enable IDLE IRQ */ | |
2318 | info->ie0_value &= ~TXRDYE; | |
2319 | info->ie1_value |= IDLE; | |
2320 | write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value)); | |
2321 | return; | |
2322 | } | |
2323 | ||
8fb06c77 | 2324 | if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) { |
1da177e4 LT |
2325 | tx_stop(info); |
2326 | return; | |
2327 | } | |
2328 | ||
2329 | if ( info->tx_count ) | |
2330 | tx_load_fifo( info ); | |
2331 | else { | |
0fab6de0 | 2332 | info->tx_active = false; |
1da177e4 LT |
2333 | info->ie0_value &= ~TXRDYE; |
2334 | write_reg(info, IE0, info->ie0_value); | |
2335 | } | |
2336 | ||
2337 | if (info->tx_count < WAKEUP_CHARS) | |
2338 | info->pending_bh |= BH_TRANSMIT; | |
2339 | } | |
2340 | ||
ce9f9f73 | 2341 | static void isr_rxdmaok(SLMP_INFO * info) |
1da177e4 LT |
2342 | { |
2343 | /* BIT7 = EOT (end of transfer) | |
2344 | * BIT6 = EOM (end of message/frame) | |
2345 | */ | |
2346 | unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0; | |
2347 | ||
2348 | /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ | |
2349 | write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); | |
2350 | ||
2351 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2352 | printk("%s(%d):%s isr_rxdmaok(), status=%02x\n", | |
2353 | __FILE__,__LINE__,info->device_name,status); | |
2354 | ||
2355 | info->pending_bh |= BH_RECEIVE; | |
2356 | } | |
2357 | ||
ce9f9f73 | 2358 | static void isr_rxdmaerror(SLMP_INFO * info) |
1da177e4 LT |
2359 | { |
2360 | /* BIT5 = BOF (buffer overflow) | |
2361 | * BIT4 = COF (counter overflow) | |
2362 | */ | |
2363 | unsigned char status = read_reg(info,RXDMA + DSR) & 0x30; | |
2364 | ||
2365 | /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ | |
2366 | write_reg(info, RXDMA + DSR, (unsigned char)(status | 1)); | |
2367 | ||
2368 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2369 | printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n", | |
2370 | __FILE__,__LINE__,info->device_name,status); | |
2371 | ||
0fab6de0 | 2372 | info->rx_overflow = true; |
1da177e4 LT |
2373 | info->pending_bh |= BH_RECEIVE; |
2374 | } | |
2375 | ||
ce9f9f73 | 2376 | static void isr_txdmaok(SLMP_INFO * info) |
1da177e4 LT |
2377 | { |
2378 | unsigned char status_reg1 = read_reg(info, SR1); | |
2379 | ||
2380 | write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */ | |
2381 | write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */ | |
2382 | write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ | |
2383 | ||
2384 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2385 | printk("%s(%d):%s isr_txdmaok(), status=%02x\n", | |
2386 | __FILE__,__LINE__,info->device_name,status_reg1); | |
2387 | ||
2388 | /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */ | |
2389 | write_reg16(info, TRC0, 0); | |
2390 | info->ie0_value |= TXRDYE; | |
2391 | write_reg(info, IE0, info->ie0_value); | |
2392 | } | |
2393 | ||
ce9f9f73 | 2394 | static void isr_txdmaerror(SLMP_INFO * info) |
1da177e4 LT |
2395 | { |
2396 | /* BIT5 = BOF (buffer overflow) | |
2397 | * BIT4 = COF (counter overflow) | |
2398 | */ | |
2399 | unsigned char status = read_reg(info,TXDMA + DSR) & 0x30; | |
2400 | ||
2401 | /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */ | |
2402 | write_reg(info, TXDMA + DSR, (unsigned char)(status | 1)); | |
2403 | ||
2404 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2405 | printk("%s(%d):%s isr_txdmaerror(), status=%02x\n", | |
2406 | __FILE__,__LINE__,info->device_name,status); | |
2407 | } | |
2408 | ||
2409 | /* handle input serial signal changes | |
2410 | */ | |
ce9f9f73 | 2411 | static void isr_io_pin( SLMP_INFO *info, u16 status ) |
1da177e4 LT |
2412 | { |
2413 | struct mgsl_icount *icount; | |
2414 | ||
2415 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2416 | printk("%s(%d):isr_io_pin status=%04X\n", | |
2417 | __FILE__,__LINE__,status); | |
2418 | ||
2419 | if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED | | |
2420 | MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) { | |
2421 | icount = &info->icount; | |
2422 | /* update input line counters */ | |
2423 | if (status & MISCSTATUS_RI_LATCHED) { | |
2424 | icount->rng++; | |
2425 | if ( status & SerialSignal_RI ) | |
2426 | info->input_signal_events.ri_up++; | |
2427 | else | |
2428 | info->input_signal_events.ri_down++; | |
2429 | } | |
2430 | if (status & MISCSTATUS_DSR_LATCHED) { | |
2431 | icount->dsr++; | |
2432 | if ( status & SerialSignal_DSR ) | |
2433 | info->input_signal_events.dsr_up++; | |
2434 | else | |
2435 | info->input_signal_events.dsr_down++; | |
2436 | } | |
2437 | if (status & MISCSTATUS_DCD_LATCHED) { | |
2438 | if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) { | |
2439 | info->ie1_value &= ~CDCD; | |
2440 | write_reg(info, IE1, info->ie1_value); | |
2441 | } | |
2442 | icount->dcd++; | |
2443 | if (status & SerialSignal_DCD) { | |
2444 | info->input_signal_events.dcd_up++; | |
2445 | } else | |
2446 | info->input_signal_events.dcd_down++; | |
af69c7f9 | 2447 | #if SYNCLINK_GENERIC_HDLC |
fbeff3c1 KH |
2448 | if (info->netcount) { |
2449 | if (status & SerialSignal_DCD) | |
2450 | netif_carrier_on(info->netdev); | |
2451 | else | |
2452 | netif_carrier_off(info->netdev); | |
2453 | } | |
1da177e4 LT |
2454 | #endif |
2455 | } | |
2456 | if (status & MISCSTATUS_CTS_LATCHED) | |
2457 | { | |
2458 | if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) { | |
2459 | info->ie1_value &= ~CCTS; | |
2460 | write_reg(info, IE1, info->ie1_value); | |
2461 | } | |
2462 | icount->cts++; | |
2463 | if ( status & SerialSignal_CTS ) | |
2464 | info->input_signal_events.cts_up++; | |
2465 | else | |
2466 | info->input_signal_events.cts_down++; | |
2467 | } | |
2468 | wake_up_interruptible(&info->status_event_wait_q); | |
2469 | wake_up_interruptible(&info->event_wait_q); | |
2470 | ||
8fb06c77 | 2471 | if ( (info->port.flags & ASYNC_CHECK_CD) && |
1da177e4 LT |
2472 | (status & MISCSTATUS_DCD_LATCHED) ) { |
2473 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2474 | printk("%s CD now %s...", info->device_name, | |
2475 | (status & SerialSignal_DCD) ? "on" : "off"); | |
2476 | if (status & SerialSignal_DCD) | |
8fb06c77 | 2477 | wake_up_interruptible(&info->port.open_wait); |
1da177e4 LT |
2478 | else { |
2479 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2480 | printk("doing serial hangup..."); | |
8fb06c77 AC |
2481 | if (info->port.tty) |
2482 | tty_hangup(info->port.tty); | |
1da177e4 LT |
2483 | } |
2484 | } | |
2485 | ||
f21ec3d2 | 2486 | if (tty_port_cts_enabled(&info->port) && |
1da177e4 | 2487 | (status & MISCSTATUS_CTS_LATCHED) ) { |
8fb06c77 AC |
2488 | if ( info->port.tty ) { |
2489 | if (info->port.tty->hw_stopped) { | |
1da177e4 LT |
2490 | if (status & SerialSignal_CTS) { |
2491 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2492 | printk("CTS tx start..."); | |
8fb06c77 | 2493 | info->port.tty->hw_stopped = 0; |
1da177e4 LT |
2494 | tx_start(info); |
2495 | info->pending_bh |= BH_TRANSMIT; | |
2496 | return; | |
2497 | } | |
2498 | } else { | |
2499 | if (!(status & SerialSignal_CTS)) { | |
2500 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2501 | printk("CTS tx stop..."); | |
8fb06c77 | 2502 | info->port.tty->hw_stopped = 1; |
1da177e4 LT |
2503 | tx_stop(info); |
2504 | } | |
2505 | } | |
2506 | } | |
2507 | } | |
2508 | } | |
2509 | ||
2510 | info->pending_bh |= BH_STATUS; | |
2511 | } | |
2512 | ||
2513 | /* Interrupt service routine entry point. | |
2514 | * | |
2515 | * Arguments: | |
2516 | * irq interrupt number that caused interrupt | |
2517 | * dev_id device ID supplied during interrupt registration | |
2518 | * regs interrupted processor context | |
2519 | */ | |
a6f97b29 | 2520 | static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id) |
1da177e4 | 2521 | { |
a6f97b29 | 2522 | SLMP_INFO *info = dev_id; |
1da177e4 LT |
2523 | unsigned char status, status0, status1=0; |
2524 | unsigned char dmastatus, dmastatus0, dmastatus1=0; | |
2525 | unsigned char timerstatus0, timerstatus1=0; | |
2526 | unsigned char shift; | |
2527 | unsigned int i; | |
2528 | unsigned short tmp; | |
2529 | ||
2530 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
a6f97b29 JG |
2531 | printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n", |
2532 | __FILE__, __LINE__, info->irq_level); | |
1da177e4 LT |
2533 | |
2534 | spin_lock(&info->lock); | |
2535 | ||
2536 | for(;;) { | |
2537 | ||
2538 | /* get status for SCA0 (ports 0-1) */ | |
2539 | tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */ | |
2540 | status0 = (unsigned char)tmp; | |
2541 | dmastatus0 = (unsigned char)(tmp>>8); | |
2542 | timerstatus0 = read_reg(info, ISR2); | |
2543 | ||
2544 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
a6f97b29 JG |
2545 | printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n", |
2546 | __FILE__, __LINE__, info->device_name, | |
2547 | status0, dmastatus0, timerstatus0); | |
1da177e4 LT |
2548 | |
2549 | if (info->port_count == 4) { | |
2550 | /* get status for SCA1 (ports 2-3) */ | |
2551 | tmp = read_reg16(info->port_array[2], ISR0); | |
2552 | status1 = (unsigned char)tmp; | |
2553 | dmastatus1 = (unsigned char)(tmp>>8); | |
2554 | timerstatus1 = read_reg(info->port_array[2], ISR2); | |
2555 | ||
2556 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2557 | printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n", | |
2558 | __FILE__,__LINE__,info->device_name, | |
2559 | status1,dmastatus1,timerstatus1); | |
2560 | } | |
2561 | ||
2562 | if (!status0 && !dmastatus0 && !timerstatus0 && | |
2563 | !status1 && !dmastatus1 && !timerstatus1) | |
2564 | break; | |
2565 | ||
2566 | for(i=0; i < info->port_count ; i++) { | |
2567 | if (info->port_array[i] == NULL) | |
2568 | continue; | |
2569 | if (i < 2) { | |
2570 | status = status0; | |
2571 | dmastatus = dmastatus0; | |
2572 | } else { | |
2573 | status = status1; | |
2574 | dmastatus = dmastatus1; | |
2575 | } | |
2576 | ||
2577 | shift = i & 1 ? 4 :0; | |
2578 | ||
2579 | if (status & BIT0 << shift) | |
2580 | isr_rxrdy(info->port_array[i]); | |
2581 | if (status & BIT1 << shift) | |
2582 | isr_txrdy(info->port_array[i]); | |
2583 | if (status & BIT2 << shift) | |
2584 | isr_rxint(info->port_array[i]); | |
2585 | if (status & BIT3 << shift) | |
2586 | isr_txint(info->port_array[i]); | |
2587 | ||
2588 | if (dmastatus & BIT0 << shift) | |
2589 | isr_rxdmaerror(info->port_array[i]); | |
2590 | if (dmastatus & BIT1 << shift) | |
2591 | isr_rxdmaok(info->port_array[i]); | |
2592 | if (dmastatus & BIT2 << shift) | |
2593 | isr_txdmaerror(info->port_array[i]); | |
2594 | if (dmastatus & BIT3 << shift) | |
2595 | isr_txdmaok(info->port_array[i]); | |
2596 | } | |
2597 | ||
2598 | if (timerstatus0 & (BIT5 | BIT4)) | |
2599 | isr_timer(info->port_array[0]); | |
2600 | if (timerstatus0 & (BIT7 | BIT6)) | |
2601 | isr_timer(info->port_array[1]); | |
2602 | if (timerstatus1 & (BIT5 | BIT4)) | |
2603 | isr_timer(info->port_array[2]); | |
2604 | if (timerstatus1 & (BIT7 | BIT6)) | |
2605 | isr_timer(info->port_array[3]); | |
2606 | } | |
2607 | ||
2608 | for(i=0; i < info->port_count ; i++) { | |
2609 | SLMP_INFO * port = info->port_array[i]; | |
2610 | ||
2611 | /* Request bottom half processing if there's something | |
2612 | * for it to do and the bh is not already running. | |
2613 | * | |
2614 | * Note: startup adapter diags require interrupts. | |
2615 | * do not request bottom half processing if the | |
2616 | * device is not open in a normal mode. | |
2617 | */ | |
8fb06c77 | 2618 | if ( port && (port->port.count || port->netcount) && |
1da177e4 LT |
2619 | port->pending_bh && !port->bh_running && |
2620 | !port->bh_requested ) { | |
2621 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
2622 | printk("%s(%d):%s queueing bh task.\n", | |
2623 | __FILE__,__LINE__,port->device_name); | |
2624 | schedule_work(&port->task); | |
0fab6de0 | 2625 | port->bh_requested = true; |
1da177e4 LT |
2626 | } |
2627 | } | |
2628 | ||
2629 | spin_unlock(&info->lock); | |
2630 | ||
2631 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
a6f97b29 JG |
2632 | printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n", |
2633 | __FILE__, __LINE__, info->irq_level); | |
1da177e4 LT |
2634 | return IRQ_HANDLED; |
2635 | } | |
2636 | ||
2637 | /* Initialize and start device. | |
2638 | */ | |
2639 | static int startup(SLMP_INFO * info) | |
2640 | { | |
2641 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2642 | printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name); | |
2643 | ||
8fb06c77 | 2644 | if (info->port.flags & ASYNC_INITIALIZED) |
1da177e4 LT |
2645 | return 0; |
2646 | ||
2647 | if (!info->tx_buf) { | |
5cbded58 | 2648 | info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); |
1da177e4 LT |
2649 | if (!info->tx_buf) { |
2650 | printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n", | |
2651 | __FILE__,__LINE__,info->device_name); | |
2652 | return -ENOMEM; | |
2653 | } | |
2654 | } | |
2655 | ||
2656 | info->pending_bh = 0; | |
2657 | ||
166692e4 PF |
2658 | memset(&info->icount, 0, sizeof(info->icount)); |
2659 | ||
1da177e4 LT |
2660 | /* program hardware for current parameters */ |
2661 | reset_port(info); | |
2662 | ||
2663 | change_params(info); | |
2664 | ||
40565f19 | 2665 | mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10)); |
1da177e4 | 2666 | |
8fb06c77 AC |
2667 | if (info->port.tty) |
2668 | clear_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
1da177e4 | 2669 | |
8fb06c77 | 2670 | info->port.flags |= ASYNC_INITIALIZED; |
1da177e4 LT |
2671 | |
2672 | return 0; | |
2673 | } | |
2674 | ||
2675 | /* Called by close() and hangup() to shutdown hardware | |
2676 | */ | |
2677 | static void shutdown(SLMP_INFO * info) | |
2678 | { | |
2679 | unsigned long flags; | |
2680 | ||
8fb06c77 | 2681 | if (!(info->port.flags & ASYNC_INITIALIZED)) |
1da177e4 LT |
2682 | return; |
2683 | ||
2684 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2685 | printk("%s(%d):%s synclinkmp_shutdown()\n", | |
2686 | __FILE__,__LINE__, info->device_name ); | |
2687 | ||
2688 | /* clear status wait queue because status changes */ | |
2689 | /* can't happen after shutting down the hardware */ | |
2690 | wake_up_interruptible(&info->status_event_wait_q); | |
2691 | wake_up_interruptible(&info->event_wait_q); | |
2692 | ||
2693 | del_timer(&info->tx_timer); | |
2694 | del_timer(&info->status_timer); | |
2695 | ||
735d5661 JJ |
2696 | kfree(info->tx_buf); |
2697 | info->tx_buf = NULL; | |
1da177e4 LT |
2698 | |
2699 | spin_lock_irqsave(&info->lock,flags); | |
2700 | ||
2701 | reset_port(info); | |
2702 | ||
adc8d746 | 2703 | if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) { |
9fe8074b | 2704 | info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); |
1da177e4 LT |
2705 | set_signals(info); |
2706 | } | |
2707 | ||
2708 | spin_unlock_irqrestore(&info->lock,flags); | |
2709 | ||
8fb06c77 AC |
2710 | if (info->port.tty) |
2711 | set_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
1da177e4 | 2712 | |
8fb06c77 | 2713 | info->port.flags &= ~ASYNC_INITIALIZED; |
1da177e4 LT |
2714 | } |
2715 | ||
2716 | static void program_hw(SLMP_INFO *info) | |
2717 | { | |
2718 | unsigned long flags; | |
2719 | ||
2720 | spin_lock_irqsave(&info->lock,flags); | |
2721 | ||
2722 | rx_stop(info); | |
2723 | tx_stop(info); | |
2724 | ||
2725 | info->tx_count = info->tx_put = info->tx_get = 0; | |
2726 | ||
2727 | if (info->params.mode == MGSL_MODE_HDLC || info->netcount) | |
2728 | hdlc_mode(info); | |
2729 | else | |
2730 | async_mode(info); | |
2731 | ||
2732 | set_signals(info); | |
2733 | ||
2734 | info->dcd_chkcount = 0; | |
2735 | info->cts_chkcount = 0; | |
2736 | info->ri_chkcount = 0; | |
2737 | info->dsr_chkcount = 0; | |
2738 | ||
2739 | info->ie1_value |= (CDCD|CCTS); | |
2740 | write_reg(info, IE1, info->ie1_value); | |
2741 | ||
2742 | get_signals(info); | |
2743 | ||
adc8d746 | 2744 | if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) ) |
1da177e4 LT |
2745 | rx_start(info); |
2746 | ||
2747 | spin_unlock_irqrestore(&info->lock,flags); | |
2748 | } | |
2749 | ||
2750 | /* Reconfigure adapter based on new parameters | |
2751 | */ | |
2752 | static void change_params(SLMP_INFO *info) | |
2753 | { | |
2754 | unsigned cflag; | |
2755 | int bits_per_char; | |
2756 | ||
adc8d746 | 2757 | if (!info->port.tty) |
1da177e4 LT |
2758 | return; |
2759 | ||
2760 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2761 | printk("%s(%d):%s change_params()\n", | |
2762 | __FILE__,__LINE__, info->device_name ); | |
2763 | ||
adc8d746 | 2764 | cflag = info->port.tty->termios.c_cflag; |
1da177e4 | 2765 | |
9fe8074b JP |
2766 | /* if B0 rate (hangup) specified then negate RTS and DTR */ |
2767 | /* otherwise assert RTS and DTR */ | |
1da177e4 | 2768 | if (cflag & CBAUD) |
9fe8074b | 2769 | info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; |
1da177e4 | 2770 | else |
9fe8074b | 2771 | info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); |
1da177e4 LT |
2772 | |
2773 | /* byte size and parity */ | |
2774 | ||
2775 | switch (cflag & CSIZE) { | |
2776 | case CS5: info->params.data_bits = 5; break; | |
2777 | case CS6: info->params.data_bits = 6; break; | |
2778 | case CS7: info->params.data_bits = 7; break; | |
2779 | case CS8: info->params.data_bits = 8; break; | |
2780 | /* Never happens, but GCC is too dumb to figure it out */ | |
2781 | default: info->params.data_bits = 7; break; | |
2782 | } | |
2783 | ||
2784 | if (cflag & CSTOPB) | |
2785 | info->params.stop_bits = 2; | |
2786 | else | |
2787 | info->params.stop_bits = 1; | |
2788 | ||
2789 | info->params.parity = ASYNC_PARITY_NONE; | |
2790 | if (cflag & PARENB) { | |
2791 | if (cflag & PARODD) | |
2792 | info->params.parity = ASYNC_PARITY_ODD; | |
2793 | else | |
2794 | info->params.parity = ASYNC_PARITY_EVEN; | |
2795 | #ifdef CMSPAR | |
2796 | if (cflag & CMSPAR) | |
2797 | info->params.parity = ASYNC_PARITY_SPACE; | |
2798 | #endif | |
2799 | } | |
2800 | ||
2801 | /* calculate number of jiffies to transmit a full | |
2802 | * FIFO (32 bytes) at specified data rate | |
2803 | */ | |
2804 | bits_per_char = info->params.data_bits + | |
2805 | info->params.stop_bits + 1; | |
2806 | ||
2807 | /* if port data rate is set to 460800 or less then | |
2808 | * allow tty settings to override, otherwise keep the | |
2809 | * current data rate. | |
2810 | */ | |
2811 | if (info->params.data_rate <= 460800) { | |
8fb06c77 | 2812 | info->params.data_rate = tty_get_baud_rate(info->port.tty); |
1da177e4 LT |
2813 | } |
2814 | ||
2815 | if ( info->params.data_rate ) { | |
2816 | info->timeout = (32*HZ*bits_per_char) / | |
2817 | info->params.data_rate; | |
2818 | } | |
2819 | info->timeout += HZ/50; /* Add .02 seconds of slop */ | |
2820 | ||
2821 | if (cflag & CRTSCTS) | |
8fb06c77 | 2822 | info->port.flags |= ASYNC_CTS_FLOW; |
1da177e4 | 2823 | else |
8fb06c77 | 2824 | info->port.flags &= ~ASYNC_CTS_FLOW; |
1da177e4 LT |
2825 | |
2826 | if (cflag & CLOCAL) | |
8fb06c77 | 2827 | info->port.flags &= ~ASYNC_CHECK_CD; |
1da177e4 | 2828 | else |
8fb06c77 | 2829 | info->port.flags |= ASYNC_CHECK_CD; |
1da177e4 LT |
2830 | |
2831 | /* process tty input control flags */ | |
2832 | ||
2833 | info->read_status_mask2 = OVRN; | |
8fb06c77 | 2834 | if (I_INPCK(info->port.tty)) |
1da177e4 | 2835 | info->read_status_mask2 |= PE | FRME; |
8fb06c77 | 2836 | if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) |
1da177e4 | 2837 | info->read_status_mask1 |= BRKD; |
8fb06c77 | 2838 | if (I_IGNPAR(info->port.tty)) |
1da177e4 | 2839 | info->ignore_status_mask2 |= PE | FRME; |
8fb06c77 | 2840 | if (I_IGNBRK(info->port.tty)) { |
1da177e4 LT |
2841 | info->ignore_status_mask1 |= BRKD; |
2842 | /* If ignoring parity and break indicators, ignore | |
2843 | * overruns too. (For real raw support). | |
2844 | */ | |
8fb06c77 | 2845 | if (I_IGNPAR(info->port.tty)) |
1da177e4 LT |
2846 | info->ignore_status_mask2 |= OVRN; |
2847 | } | |
2848 | ||
2849 | program_hw(info); | |
2850 | } | |
2851 | ||
2852 | static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount) | |
2853 | { | |
2854 | int err; | |
2855 | ||
2856 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2857 | printk("%s(%d):%s get_params()\n", | |
2858 | __FILE__,__LINE__, info->device_name); | |
2859 | ||
166692e4 PF |
2860 | if (!user_icount) { |
2861 | memset(&info->icount, 0, sizeof(info->icount)); | |
2862 | } else { | |
f602501d | 2863 | mutex_lock(&info->port.mutex); |
166692e4 | 2864 | COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount)); |
f602501d | 2865 | mutex_unlock(&info->port.mutex); |
166692e4 PF |
2866 | if (err) |
2867 | return -EFAULT; | |
1da177e4 LT |
2868 | } |
2869 | ||
2870 | return 0; | |
2871 | } | |
2872 | ||
2873 | static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params) | |
2874 | { | |
2875 | int err; | |
2876 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2877 | printk("%s(%d):%s get_params()\n", | |
2878 | __FILE__,__LINE__, info->device_name); | |
2879 | ||
f602501d | 2880 | mutex_lock(&info->port.mutex); |
1da177e4 | 2881 | COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS)); |
f602501d | 2882 | mutex_unlock(&info->port.mutex); |
1da177e4 LT |
2883 | if (err) { |
2884 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2885 | printk( "%s(%d):%s get_params() user buffer copy failed\n", | |
2886 | __FILE__,__LINE__,info->device_name); | |
2887 | return -EFAULT; | |
2888 | } | |
2889 | ||
2890 | return 0; | |
2891 | } | |
2892 | ||
2893 | static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params) | |
2894 | { | |
2895 | unsigned long flags; | |
2896 | MGSL_PARAMS tmp_params; | |
2897 | int err; | |
2898 | ||
2899 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2900 | printk("%s(%d):%s set_params\n", | |
2901 | __FILE__,__LINE__,info->device_name ); | |
2902 | COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS)); | |
2903 | if (err) { | |
2904 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2905 | printk( "%s(%d):%s set_params() user buffer copy failed\n", | |
2906 | __FILE__,__LINE__,info->device_name); | |
2907 | return -EFAULT; | |
2908 | } | |
2909 | ||
f602501d | 2910 | mutex_lock(&info->port.mutex); |
1da177e4 LT |
2911 | spin_lock_irqsave(&info->lock,flags); |
2912 | memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS)); | |
2913 | spin_unlock_irqrestore(&info->lock,flags); | |
2914 | ||
2915 | change_params(info); | |
f602501d | 2916 | mutex_unlock(&info->port.mutex); |
1da177e4 LT |
2917 | |
2918 | return 0; | |
2919 | } | |
2920 | ||
2921 | static int get_txidle(SLMP_INFO * info, int __user *idle_mode) | |
2922 | { | |
2923 | int err; | |
2924 | ||
2925 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2926 | printk("%s(%d):%s get_txidle()=%d\n", | |
2927 | __FILE__,__LINE__, info->device_name, info->idle_mode); | |
2928 | ||
2929 | COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int)); | |
2930 | if (err) { | |
2931 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2932 | printk( "%s(%d):%s get_txidle() user buffer copy failed\n", | |
2933 | __FILE__,__LINE__,info->device_name); | |
2934 | return -EFAULT; | |
2935 | } | |
2936 | ||
2937 | return 0; | |
2938 | } | |
2939 | ||
2940 | static int set_txidle(SLMP_INFO * info, int idle_mode) | |
2941 | { | |
2942 | unsigned long flags; | |
2943 | ||
2944 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2945 | printk("%s(%d):%s set_txidle(%d)\n", | |
2946 | __FILE__,__LINE__,info->device_name, idle_mode ); | |
2947 | ||
2948 | spin_lock_irqsave(&info->lock,flags); | |
2949 | info->idle_mode = idle_mode; | |
2950 | tx_set_idle( info ); | |
2951 | spin_unlock_irqrestore(&info->lock,flags); | |
2952 | return 0; | |
2953 | } | |
2954 | ||
2955 | static int tx_enable(SLMP_INFO * info, int enable) | |
2956 | { | |
2957 | unsigned long flags; | |
2958 | ||
2959 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2960 | printk("%s(%d):%s tx_enable(%d)\n", | |
2961 | __FILE__,__LINE__,info->device_name, enable); | |
2962 | ||
2963 | spin_lock_irqsave(&info->lock,flags); | |
2964 | if ( enable ) { | |
2965 | if ( !info->tx_enabled ) { | |
2966 | tx_start(info); | |
2967 | } | |
2968 | } else { | |
2969 | if ( info->tx_enabled ) | |
2970 | tx_stop(info); | |
2971 | } | |
2972 | spin_unlock_irqrestore(&info->lock,flags); | |
2973 | return 0; | |
2974 | } | |
2975 | ||
2976 | /* abort send HDLC frame | |
2977 | */ | |
2978 | static int tx_abort(SLMP_INFO * info) | |
2979 | { | |
2980 | unsigned long flags; | |
2981 | ||
2982 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2983 | printk("%s(%d):%s tx_abort()\n", | |
2984 | __FILE__,__LINE__,info->device_name); | |
2985 | ||
2986 | spin_lock_irqsave(&info->lock,flags); | |
2987 | if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) { | |
2988 | info->ie1_value &= ~UDRN; | |
2989 | info->ie1_value |= IDLE; | |
2990 | write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ | |
2991 | write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ | |
2992 | ||
2993 | write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ | |
2994 | write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ | |
2995 | ||
2996 | write_reg(info, CMD, TXABORT); | |
2997 | } | |
2998 | spin_unlock_irqrestore(&info->lock,flags); | |
2999 | return 0; | |
3000 | } | |
3001 | ||
3002 | static int rx_enable(SLMP_INFO * info, int enable) | |
3003 | { | |
3004 | unsigned long flags; | |
3005 | ||
3006 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3007 | printk("%s(%d):%s rx_enable(%d)\n", | |
3008 | __FILE__,__LINE__,info->device_name,enable); | |
3009 | ||
3010 | spin_lock_irqsave(&info->lock,flags); | |
3011 | if ( enable ) { | |
3012 | if ( !info->rx_enabled ) | |
3013 | rx_start(info); | |
3014 | } else { | |
3015 | if ( info->rx_enabled ) | |
3016 | rx_stop(info); | |
3017 | } | |
3018 | spin_unlock_irqrestore(&info->lock,flags); | |
3019 | return 0; | |
3020 | } | |
3021 | ||
1da177e4 LT |
3022 | /* wait for specified event to occur |
3023 | */ | |
3024 | static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr) | |
3025 | { | |
3026 | unsigned long flags; | |
3027 | int s; | |
3028 | int rc=0; | |
3029 | struct mgsl_icount cprev, cnow; | |
3030 | int events; | |
3031 | int mask; | |
3032 | struct _input_signal_events oldsigs, newsigs; | |
3033 | DECLARE_WAITQUEUE(wait, current); | |
3034 | ||
3035 | COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int)); | |
3036 | if (rc) { | |
3037 | return -EFAULT; | |
3038 | } | |
3039 | ||
3040 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3041 | printk("%s(%d):%s wait_mgsl_event(%d)\n", | |
3042 | __FILE__,__LINE__,info->device_name,mask); | |
3043 | ||
3044 | spin_lock_irqsave(&info->lock,flags); | |
3045 | ||
3046 | /* return immediately if state matches requested events */ | |
3047 | get_signals(info); | |
7f3edb94 | 3048 | s = info->serial_signals; |
1da177e4 LT |
3049 | |
3050 | events = mask & | |
3051 | ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + | |
3052 | ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + | |
3053 | ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + | |
3054 | ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); | |
3055 | if (events) { | |
3056 | spin_unlock_irqrestore(&info->lock,flags); | |
3057 | goto exit; | |
3058 | } | |
3059 | ||
3060 | /* save current irq counts */ | |
3061 | cprev = info->icount; | |
3062 | oldsigs = info->input_signal_events; | |
3063 | ||
3064 | /* enable hunt and idle irqs if needed */ | |
3065 | if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) { | |
3066 | unsigned char oldval = info->ie1_value; | |
3067 | unsigned char newval = oldval + | |
3068 | (mask & MgslEvent_ExitHuntMode ? FLGD:0) + | |
3069 | (mask & MgslEvent_IdleReceived ? IDLD:0); | |
3070 | if ( oldval != newval ) { | |
3071 | info->ie1_value = newval; | |
3072 | write_reg(info, IE1, info->ie1_value); | |
3073 | } | |
3074 | } | |
3075 | ||
3076 | set_current_state(TASK_INTERRUPTIBLE); | |
3077 | add_wait_queue(&info->event_wait_q, &wait); | |
3078 | ||
3079 | spin_unlock_irqrestore(&info->lock,flags); | |
3080 | ||
3081 | for(;;) { | |
3082 | schedule(); | |
3083 | if (signal_pending(current)) { | |
3084 | rc = -ERESTARTSYS; | |
3085 | break; | |
3086 | } | |
3087 | ||
3088 | /* get current irq counts */ | |
3089 | spin_lock_irqsave(&info->lock,flags); | |
3090 | cnow = info->icount; | |
3091 | newsigs = info->input_signal_events; | |
3092 | set_current_state(TASK_INTERRUPTIBLE); | |
3093 | spin_unlock_irqrestore(&info->lock,flags); | |
3094 | ||
3095 | /* if no change, wait aborted for some reason */ | |
3096 | if (newsigs.dsr_up == oldsigs.dsr_up && | |
3097 | newsigs.dsr_down == oldsigs.dsr_down && | |
3098 | newsigs.dcd_up == oldsigs.dcd_up && | |
3099 | newsigs.dcd_down == oldsigs.dcd_down && | |
3100 | newsigs.cts_up == oldsigs.cts_up && | |
3101 | newsigs.cts_down == oldsigs.cts_down && | |
3102 | newsigs.ri_up == oldsigs.ri_up && | |
3103 | newsigs.ri_down == oldsigs.ri_down && | |
3104 | cnow.exithunt == cprev.exithunt && | |
3105 | cnow.rxidle == cprev.rxidle) { | |
3106 | rc = -EIO; | |
3107 | break; | |
3108 | } | |
3109 | ||
3110 | events = mask & | |
3111 | ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + | |
3112 | (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + | |
3113 | (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + | |
3114 | (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + | |
3115 | (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + | |
3116 | (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + | |
3117 | (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + | |
3118 | (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + | |
3119 | (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + | |
3120 | (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); | |
3121 | if (events) | |
3122 | break; | |
3123 | ||
3124 | cprev = cnow; | |
3125 | oldsigs = newsigs; | |
3126 | } | |
3127 | ||
3128 | remove_wait_queue(&info->event_wait_q, &wait); | |
3129 | set_current_state(TASK_RUNNING); | |
3130 | ||
3131 | ||
3132 | if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { | |
3133 | spin_lock_irqsave(&info->lock,flags); | |
3134 | if (!waitqueue_active(&info->event_wait_q)) { | |
3135 | /* disable enable exit hunt mode/idle rcvd IRQs */ | |
3136 | info->ie1_value &= ~(FLGD|IDLD); | |
3137 | write_reg(info, IE1, info->ie1_value); | |
3138 | } | |
3139 | spin_unlock_irqrestore(&info->lock,flags); | |
3140 | } | |
3141 | exit: | |
3142 | if ( rc == 0 ) | |
3143 | PUT_USER(rc, events, mask_ptr); | |
3144 | ||
3145 | return rc; | |
3146 | } | |
3147 | ||
3148 | static int modem_input_wait(SLMP_INFO *info,int arg) | |
3149 | { | |
3150 | unsigned long flags; | |
3151 | int rc; | |
3152 | struct mgsl_icount cprev, cnow; | |
3153 | DECLARE_WAITQUEUE(wait, current); | |
3154 | ||
3155 | /* save current irq counts */ | |
3156 | spin_lock_irqsave(&info->lock,flags); | |
3157 | cprev = info->icount; | |
3158 | add_wait_queue(&info->status_event_wait_q, &wait); | |
3159 | set_current_state(TASK_INTERRUPTIBLE); | |
3160 | spin_unlock_irqrestore(&info->lock,flags); | |
3161 | ||
3162 | for(;;) { | |
3163 | schedule(); | |
3164 | if (signal_pending(current)) { | |
3165 | rc = -ERESTARTSYS; | |
3166 | break; | |
3167 | } | |
3168 | ||
3169 | /* get new irq counts */ | |
3170 | spin_lock_irqsave(&info->lock,flags); | |
3171 | cnow = info->icount; | |
3172 | set_current_state(TASK_INTERRUPTIBLE); | |
3173 | spin_unlock_irqrestore(&info->lock,flags); | |
3174 | ||
3175 | /* if no change, wait aborted for some reason */ | |
3176 | if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && | |
3177 | cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { | |
3178 | rc = -EIO; | |
3179 | break; | |
3180 | } | |
3181 | ||
3182 | /* check for change in caller specified modem input */ | |
3183 | if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || | |
3184 | (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || | |
3185 | (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || | |
3186 | (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { | |
3187 | rc = 0; | |
3188 | break; | |
3189 | } | |
3190 | ||
3191 | cprev = cnow; | |
3192 | } | |
3193 | remove_wait_queue(&info->status_event_wait_q, &wait); | |
3194 | set_current_state(TASK_RUNNING); | |
3195 | return rc; | |
3196 | } | |
3197 | ||
3198 | /* return the state of the serial control and status signals | |
3199 | */ | |
60b33c13 | 3200 | static int tiocmget(struct tty_struct *tty) |
1da177e4 | 3201 | { |
c9f19e96 | 3202 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
3203 | unsigned int result; |
3204 | unsigned long flags; | |
3205 | ||
3206 | spin_lock_irqsave(&info->lock,flags); | |
3207 | get_signals(info); | |
3208 | spin_unlock_irqrestore(&info->lock,flags); | |
3209 | ||
9fe8074b JP |
3210 | result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) | |
3211 | ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) | | |
3212 | ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) | | |
3213 | ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) | | |
3214 | ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) | | |
3215 | ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0); | |
1da177e4 LT |
3216 | |
3217 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3218 | printk("%s(%d):%s tiocmget() value=%08X\n", | |
3219 | __FILE__,__LINE__, info->device_name, result ); | |
3220 | return result; | |
3221 | } | |
3222 | ||
3223 | /* set modem control signals (DTR/RTS) | |
3224 | */ | |
20b9d177 AC |
3225 | static int tiocmset(struct tty_struct *tty, |
3226 | unsigned int set, unsigned int clear) | |
1da177e4 | 3227 | { |
c9f19e96 | 3228 | SLMP_INFO *info = tty->driver_data; |
1da177e4 LT |
3229 | unsigned long flags; |
3230 | ||
3231 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3232 | printk("%s(%d):%s tiocmset(%x,%x)\n", | |
3233 | __FILE__,__LINE__,info->device_name, set, clear); | |
3234 | ||
3235 | if (set & TIOCM_RTS) | |
3236 | info->serial_signals |= SerialSignal_RTS; | |
3237 | if (set & TIOCM_DTR) | |
3238 | info->serial_signals |= SerialSignal_DTR; | |
3239 | if (clear & TIOCM_RTS) | |
3240 | info->serial_signals &= ~SerialSignal_RTS; | |
3241 | if (clear & TIOCM_DTR) | |
3242 | info->serial_signals &= ~SerialSignal_DTR; | |
3243 | ||
3244 | spin_lock_irqsave(&info->lock,flags); | |
3245 | set_signals(info); | |
3246 | spin_unlock_irqrestore(&info->lock,flags); | |
3247 | ||
3248 | return 0; | |
3249 | } | |
3250 | ||
31f35939 AC |
3251 | static int carrier_raised(struct tty_port *port) |
3252 | { | |
3253 | SLMP_INFO *info = container_of(port, SLMP_INFO, port); | |
3254 | unsigned long flags; | |
1da177e4 | 3255 | |
31f35939 AC |
3256 | spin_lock_irqsave(&info->lock,flags); |
3257 | get_signals(info); | |
3258 | spin_unlock_irqrestore(&info->lock,flags); | |
3259 | ||
3260 | return (info->serial_signals & SerialSignal_DCD) ? 1 : 0; | |
3261 | } | |
1da177e4 | 3262 | |
fcc8ac18 | 3263 | static void dtr_rts(struct tty_port *port, int on) |
3e61696b AC |
3264 | { |
3265 | SLMP_INFO *info = container_of(port, SLMP_INFO, port); | |
3266 | unsigned long flags; | |
3267 | ||
3268 | spin_lock_irqsave(&info->lock,flags); | |
fcc8ac18 | 3269 | if (on) |
9fe8074b | 3270 | info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; |
fcc8ac18 | 3271 | else |
9fe8074b | 3272 | info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); |
3e61696b AC |
3273 | set_signals(info); |
3274 | spin_unlock_irqrestore(&info->lock,flags); | |
3275 | } | |
3276 | ||
1da177e4 LT |
3277 | /* Block the current process until the specified port is ready to open. |
3278 | */ | |
3279 | static int block_til_ready(struct tty_struct *tty, struct file *filp, | |
3280 | SLMP_INFO *info) | |
3281 | { | |
3282 | DECLARE_WAITQUEUE(wait, current); | |
3283 | int retval; | |
0fab6de0 | 3284 | bool do_clocal = false; |
1da177e4 | 3285 | unsigned long flags; |
31f35939 AC |
3286 | int cd; |
3287 | struct tty_port *port = &info->port; | |
1da177e4 LT |
3288 | |
3289 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3290 | printk("%s(%d):%s block_til_ready()\n", | |
3291 | __FILE__,__LINE__, tty->driver->name ); | |
3292 | ||
3293 | if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ | |
3294 | /* nonblock mode is set or port is not enabled */ | |
3295 | /* just verify that callout device is not active */ | |
31f35939 | 3296 | port->flags |= ASYNC_NORMAL_ACTIVE; |
1da177e4 LT |
3297 | return 0; |
3298 | } | |
3299 | ||
adc8d746 | 3300 | if (tty->termios.c_cflag & CLOCAL) |
0fab6de0 | 3301 | do_clocal = true; |
1da177e4 LT |
3302 | |
3303 | /* Wait for carrier detect and the line to become | |
3304 | * free (i.e., not in use by the callout). While we are in | |
31f35939 | 3305 | * this loop, port->count is dropped by one, so that |
1da177e4 LT |
3306 | * close() knows when to free things. We restore it upon |
3307 | * exit, either normal or abnormal. | |
3308 | */ | |
3309 | ||
3310 | retval = 0; | |
31f35939 | 3311 | add_wait_queue(&port->open_wait, &wait); |
1da177e4 LT |
3312 | |
3313 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3314 | printk("%s(%d):%s block_til_ready() before block, count=%d\n", | |
31f35939 | 3315 | __FILE__,__LINE__, tty->driver->name, port->count ); |
1da177e4 LT |
3316 | |
3317 | spin_lock_irqsave(&info->lock, flags); | |
e359a4e3 | 3318 | port->count--; |
1da177e4 | 3319 | spin_unlock_irqrestore(&info->lock, flags); |
31f35939 | 3320 | port->blocked_open++; |
1da177e4 LT |
3321 | |
3322 | while (1) { | |
53a72d57 | 3323 | if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags)) |
3e61696b | 3324 | tty_port_raise_dtr_rts(port); |
1da177e4 LT |
3325 | |
3326 | set_current_state(TASK_INTERRUPTIBLE); | |
3327 | ||
31f35939 AC |
3328 | if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){ |
3329 | retval = (port->flags & ASYNC_HUP_NOTIFY) ? | |
1da177e4 LT |
3330 | -EAGAIN : -ERESTARTSYS; |
3331 | break; | |
3332 | } | |
3333 | ||
31f35939 | 3334 | cd = tty_port_carrier_raised(port); |
fef062cb PH |
3335 | if (do_clocal || cd) |
3336 | break; | |
1da177e4 LT |
3337 | |
3338 | if (signal_pending(current)) { | |
3339 | retval = -ERESTARTSYS; | |
3340 | break; | |
3341 | } | |
3342 | ||
3343 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3344 | printk("%s(%d):%s block_til_ready() count=%d\n", | |
31f35939 | 3345 | __FILE__,__LINE__, tty->driver->name, port->count ); |
1da177e4 | 3346 | |
89c8d91e | 3347 | tty_unlock(tty); |
1da177e4 | 3348 | schedule(); |
89c8d91e | 3349 | tty_lock(tty); |
1da177e4 LT |
3350 | } |
3351 | ||
3352 | set_current_state(TASK_RUNNING); | |
31f35939 | 3353 | remove_wait_queue(&port->open_wait, &wait); |
e359a4e3 | 3354 | if (!tty_hung_up_p(filp)) |
31f35939 AC |
3355 | port->count++; |
3356 | port->blocked_open--; | |
1da177e4 LT |
3357 | |
3358 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3359 | printk("%s(%d):%s block_til_ready() after, count=%d\n", | |
31f35939 | 3360 | __FILE__,__LINE__, tty->driver->name, port->count ); |
1da177e4 LT |
3361 | |
3362 | if (!retval) | |
31f35939 | 3363 | port->flags |= ASYNC_NORMAL_ACTIVE; |
1da177e4 LT |
3364 | |
3365 | return retval; | |
3366 | } | |
3367 | ||
ce9f9f73 | 3368 | static int alloc_dma_bufs(SLMP_INFO *info) |
1da177e4 LT |
3369 | { |
3370 | unsigned short BuffersPerFrame; | |
3371 | unsigned short BufferCount; | |
3372 | ||
3373 | // Force allocation to start at 64K boundary for each port. | |
3374 | // This is necessary because *all* buffer descriptors for a port | |
3375 | // *must* be in the same 64K block. All descriptors on a port | |
3376 | // share a common 'base' address (upper 8 bits of 24 bits) programmed | |
3377 | // into the CBP register. | |
3378 | info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num; | |
3379 | ||
3380 | /* Calculate the number of DMA buffers necessary to hold the */ | |
3381 | /* largest allowable frame size. Note: If the max frame size is */ | |
3382 | /* not an even multiple of the DMA buffer size then we need to */ | |
3383 | /* round the buffer count per frame up one. */ | |
3384 | ||
3385 | BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE); | |
3386 | if ( info->max_frame_size % SCABUFSIZE ) | |
3387 | BuffersPerFrame++; | |
3388 | ||
3389 | /* calculate total number of data buffers (SCABUFSIZE) possible | |
3390 | * in one ports memory (SCA_MEM_SIZE/4) after allocating memory | |
3391 | * for the descriptor list (BUFFERLISTSIZE). | |
3392 | */ | |
3393 | BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE; | |
3394 | ||
3395 | /* limit number of buffers to maximum amount of descriptors */ | |
3396 | if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC)) | |
3397 | BufferCount = BUFFERLISTSIZE/sizeof(SCADESC); | |
3398 | ||
3399 | /* use enough buffers to transmit one max size frame */ | |
3400 | info->tx_buf_count = BuffersPerFrame + 1; | |
3401 | ||
3402 | /* never use more than half the available buffers for transmit */ | |
3403 | if (info->tx_buf_count > (BufferCount/2)) | |
3404 | info->tx_buf_count = BufferCount/2; | |
3405 | ||
3406 | if (info->tx_buf_count > SCAMAXDESC) | |
3407 | info->tx_buf_count = SCAMAXDESC; | |
3408 | ||
3409 | /* use remaining buffers for receive */ | |
3410 | info->rx_buf_count = BufferCount - info->tx_buf_count; | |
3411 | ||
3412 | if (info->rx_buf_count > SCAMAXDESC) | |
3413 | info->rx_buf_count = SCAMAXDESC; | |
3414 | ||
3415 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
3416 | printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n", | |
3417 | __FILE__,__LINE__, info->device_name, | |
3418 | info->tx_buf_count,info->rx_buf_count); | |
3419 | ||
3420 | if ( alloc_buf_list( info ) < 0 || | |
3421 | alloc_frame_bufs(info, | |
3422 | info->rx_buf_list, | |
3423 | info->rx_buf_list_ex, | |
3424 | info->rx_buf_count) < 0 || | |
3425 | alloc_frame_bufs(info, | |
3426 | info->tx_buf_list, | |
3427 | info->tx_buf_list_ex, | |
3428 | info->tx_buf_count) < 0 || | |
3429 | alloc_tmp_rx_buf(info) < 0 ) { | |
3430 | printk("%s(%d):%s Can't allocate DMA buffer memory\n", | |
3431 | __FILE__,__LINE__, info->device_name); | |
3432 | return -ENOMEM; | |
3433 | } | |
3434 | ||
3435 | rx_reset_buffers( info ); | |
3436 | ||
3437 | return 0; | |
3438 | } | |
3439 | ||
3440 | /* Allocate DMA buffers for the transmit and receive descriptor lists. | |
3441 | */ | |
ce9f9f73 | 3442 | static int alloc_buf_list(SLMP_INFO *info) |
1da177e4 LT |
3443 | { |
3444 | unsigned int i; | |
3445 | ||
3446 | /* build list in adapter shared memory */ | |
3447 | info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc; | |
3448 | info->buffer_list_phys = info->port_array[0]->last_mem_alloc; | |
3449 | info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE; | |
3450 | ||
3451 | memset(info->buffer_list, 0, BUFFERLISTSIZE); | |
3452 | ||
3453 | /* Save virtual address pointers to the receive and */ | |
3454 | /* transmit buffer lists. (Receive 1st). These pointers will */ | |
3455 | /* be used by the processor to access the lists. */ | |
3456 | info->rx_buf_list = (SCADESC *)info->buffer_list; | |
3457 | ||
3458 | info->tx_buf_list = (SCADESC *)info->buffer_list; | |
3459 | info->tx_buf_list += info->rx_buf_count; | |
3460 | ||
3461 | /* Build links for circular buffer entry lists (tx and rx) | |
3462 | * | |
3463 | * Note: links are physical addresses read by the SCA device | |
3464 | * to determine the next buffer entry to use. | |
3465 | */ | |
3466 | ||
3467 | for ( i = 0; i < info->rx_buf_count; i++ ) { | |
3468 | /* calculate and store physical address of this buffer entry */ | |
3469 | info->rx_buf_list_ex[i].phys_entry = | |
2652c216 | 3470 | info->buffer_list_phys + (i * SCABUFSIZE); |
1da177e4 LT |
3471 | |
3472 | /* calculate and store physical address of */ | |
3473 | /* next entry in cirular list of entries */ | |
3474 | info->rx_buf_list[i].next = info->buffer_list_phys; | |
3475 | if ( i < info->rx_buf_count - 1 ) | |
3476 | info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC); | |
3477 | ||
3478 | info->rx_buf_list[i].length = SCABUFSIZE; | |
3479 | } | |
3480 | ||
3481 | for ( i = 0; i < info->tx_buf_count; i++ ) { | |
3482 | /* calculate and store physical address of this buffer entry */ | |
3483 | info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys + | |
3484 | ((info->rx_buf_count + i) * sizeof(SCADESC)); | |
3485 | ||
3486 | /* calculate and store physical address of */ | |
3487 | /* next entry in cirular list of entries */ | |
3488 | ||
3489 | info->tx_buf_list[i].next = info->buffer_list_phys + | |
3490 | info->rx_buf_count * sizeof(SCADESC); | |
3491 | ||
3492 | if ( i < info->tx_buf_count - 1 ) | |
3493 | info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC); | |
3494 | } | |
3495 | ||
3496 | return 0; | |
3497 | } | |
3498 | ||
3499 | /* Allocate the frame DMA buffers used by the specified buffer list. | |
3500 | */ | |
ce9f9f73 | 3501 | static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count) |
1da177e4 LT |
3502 | { |
3503 | int i; | |
3504 | unsigned long phys_addr; | |
3505 | ||
3506 | for ( i = 0; i < count; i++ ) { | |
3507 | buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc; | |
3508 | phys_addr = info->port_array[0]->last_mem_alloc; | |
3509 | info->port_array[0]->last_mem_alloc += SCABUFSIZE; | |
3510 | ||
3511 | buf_list[i].buf_ptr = (unsigned short)phys_addr; | |
3512 | buf_list[i].buf_base = (unsigned char)(phys_addr >> 16); | |
3513 | } | |
3514 | ||
3515 | return 0; | |
3516 | } | |
3517 | ||
ce9f9f73 | 3518 | static void free_dma_bufs(SLMP_INFO *info) |
1da177e4 LT |
3519 | { |
3520 | info->buffer_list = NULL; | |
3521 | info->rx_buf_list = NULL; | |
3522 | info->tx_buf_list = NULL; | |
3523 | } | |
3524 | ||
3525 | /* allocate buffer large enough to hold max_frame_size. | |
3526 | * This buffer is used to pass an assembled frame to the line discipline. | |
3527 | */ | |
ce9f9f73 | 3528 | static int alloc_tmp_rx_buf(SLMP_INFO *info) |
1da177e4 LT |
3529 | { |
3530 | info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL); | |
3531 | if (info->tmp_rx_buf == NULL) | |
3532 | return -ENOMEM; | |
a6b68a69 PF |
3533 | /* unused flag buffer to satisfy receive_buf calling interface */ |
3534 | info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL); | |
3535 | if (!info->flag_buf) { | |
3536 | kfree(info->tmp_rx_buf); | |
3537 | info->tmp_rx_buf = NULL; | |
3538 | return -ENOMEM; | |
3539 | } | |
1da177e4 LT |
3540 | return 0; |
3541 | } | |
3542 | ||
ce9f9f73 | 3543 | static void free_tmp_rx_buf(SLMP_INFO *info) |
1da177e4 | 3544 | { |
735d5661 | 3545 | kfree(info->tmp_rx_buf); |
1da177e4 | 3546 | info->tmp_rx_buf = NULL; |
a6b68a69 PF |
3547 | kfree(info->flag_buf); |
3548 | info->flag_buf = NULL; | |
1da177e4 LT |
3549 | } |
3550 | ||
ce9f9f73 | 3551 | static int claim_resources(SLMP_INFO *info) |
1da177e4 LT |
3552 | { |
3553 | if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) { | |
3554 | printk( "%s(%d):%s mem addr conflict, Addr=%08X\n", | |
3555 | __FILE__,__LINE__,info->device_name, info->phys_memory_base); | |
3556 | info->init_error = DiagStatus_AddressConflict; | |
3557 | goto errout; | |
3558 | } | |
3559 | else | |
0fab6de0 | 3560 | info->shared_mem_requested = true; |
1da177e4 LT |
3561 | |
3562 | if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) { | |
3563 | printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n", | |
3564 | __FILE__,__LINE__,info->device_name, info->phys_lcr_base); | |
3565 | info->init_error = DiagStatus_AddressConflict; | |
3566 | goto errout; | |
3567 | } | |
3568 | else | |
0fab6de0 | 3569 | info->lcr_mem_requested = true; |
1da177e4 LT |
3570 | |
3571 | if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) { | |
3572 | printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n", | |
3573 | __FILE__,__LINE__,info->device_name, info->phys_sca_base); | |
3574 | info->init_error = DiagStatus_AddressConflict; | |
3575 | goto errout; | |
3576 | } | |
3577 | else | |
0fab6de0 | 3578 | info->sca_base_requested = true; |
1da177e4 LT |
3579 | |
3580 | if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) { | |
3581 | printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n", | |
3582 | __FILE__,__LINE__,info->device_name, info->phys_statctrl_base); | |
3583 | info->init_error = DiagStatus_AddressConflict; | |
3584 | goto errout; | |
3585 | } | |
3586 | else | |
0fab6de0 | 3587 | info->sca_statctrl_requested = true; |
1da177e4 | 3588 | |
24cb2335 AC |
3589 | info->memory_base = ioremap_nocache(info->phys_memory_base, |
3590 | SCA_MEM_SIZE); | |
1da177e4 | 3591 | if (!info->memory_base) { |
25985edc | 3592 | printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n", |
1da177e4 LT |
3593 | __FILE__,__LINE__,info->device_name, info->phys_memory_base ); |
3594 | info->init_error = DiagStatus_CantAssignPciResources; | |
3595 | goto errout; | |
3596 | } | |
3597 | ||
24cb2335 | 3598 | info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE); |
1da177e4 | 3599 | if (!info->lcr_base) { |
25985edc | 3600 | printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n", |
1da177e4 LT |
3601 | __FILE__,__LINE__,info->device_name, info->phys_lcr_base ); |
3602 | info->init_error = DiagStatus_CantAssignPciResources; | |
3603 | goto errout; | |
3604 | } | |
3605 | info->lcr_base += info->lcr_offset; | |
3606 | ||
24cb2335 | 3607 | info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE); |
1da177e4 | 3608 | if (!info->sca_base) { |
25985edc | 3609 | printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n", |
1da177e4 LT |
3610 | __FILE__,__LINE__,info->device_name, info->phys_sca_base ); |
3611 | info->init_error = DiagStatus_CantAssignPciResources; | |
3612 | goto errout; | |
3613 | } | |
3614 | info->sca_base += info->sca_offset; | |
3615 | ||
24cb2335 AC |
3616 | info->statctrl_base = ioremap_nocache(info->phys_statctrl_base, |
3617 | PAGE_SIZE); | |
1da177e4 | 3618 | if (!info->statctrl_base) { |
25985edc | 3619 | printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n", |
1da177e4 LT |
3620 | __FILE__,__LINE__,info->device_name, info->phys_statctrl_base ); |
3621 | info->init_error = DiagStatus_CantAssignPciResources; | |
3622 | goto errout; | |
3623 | } | |
3624 | info->statctrl_base += info->statctrl_offset; | |
3625 | ||
3626 | if ( !memory_test(info) ) { | |
3627 | printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n", | |
3628 | __FILE__,__LINE__,info->device_name, info->phys_memory_base ); | |
3629 | info->init_error = DiagStatus_MemoryError; | |
3630 | goto errout; | |
3631 | } | |
3632 | ||
3633 | return 0; | |
3634 | ||
3635 | errout: | |
3636 | release_resources( info ); | |
3637 | return -ENODEV; | |
3638 | } | |
3639 | ||
ce9f9f73 | 3640 | static void release_resources(SLMP_INFO *info) |
1da177e4 LT |
3641 | { |
3642 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
3643 | printk( "%s(%d):%s release_resources() entry\n", | |
3644 | __FILE__,__LINE__,info->device_name ); | |
3645 | ||
3646 | if ( info->irq_requested ) { | |
3647 | free_irq(info->irq_level, info); | |
0fab6de0 | 3648 | info->irq_requested = false; |
1da177e4 LT |
3649 | } |
3650 | ||
3651 | if ( info->shared_mem_requested ) { | |
3652 | release_mem_region(info->phys_memory_base,SCA_MEM_SIZE); | |
0fab6de0 | 3653 | info->shared_mem_requested = false; |
1da177e4 LT |
3654 | } |
3655 | if ( info->lcr_mem_requested ) { | |
3656 | release_mem_region(info->phys_lcr_base + info->lcr_offset,128); | |
0fab6de0 | 3657 | info->lcr_mem_requested = false; |
1da177e4 LT |
3658 | } |
3659 | if ( info->sca_base_requested ) { | |
3660 | release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE); | |
0fab6de0 | 3661 | info->sca_base_requested = false; |
1da177e4 LT |
3662 | } |
3663 | if ( info->sca_statctrl_requested ) { | |
3664 | release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE); | |
0fab6de0 | 3665 | info->sca_statctrl_requested = false; |
1da177e4 LT |
3666 | } |
3667 | ||
3668 | if (info->memory_base){ | |
3669 | iounmap(info->memory_base); | |
3670 | info->memory_base = NULL; | |
3671 | } | |
3672 | ||
3673 | if (info->sca_base) { | |
3674 | iounmap(info->sca_base - info->sca_offset); | |
3675 | info->sca_base=NULL; | |
3676 | } | |
3677 | ||
3678 | if (info->statctrl_base) { | |
3679 | iounmap(info->statctrl_base - info->statctrl_offset); | |
3680 | info->statctrl_base=NULL; | |
3681 | } | |
3682 | ||
3683 | if (info->lcr_base){ | |
3684 | iounmap(info->lcr_base - info->lcr_offset); | |
3685 | info->lcr_base = NULL; | |
3686 | } | |
3687 | ||
3688 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
3689 | printk( "%s(%d):%s release_resources() exit\n", | |
3690 | __FILE__,__LINE__,info->device_name ); | |
3691 | } | |
3692 | ||
3693 | /* Add the specified device instance data structure to the | |
3694 | * global linked list of devices and increment the device count. | |
3695 | */ | |
ce9f9f73 | 3696 | static void add_device(SLMP_INFO *info) |
1da177e4 LT |
3697 | { |
3698 | info->next_device = NULL; | |
3699 | info->line = synclinkmp_device_count; | |
3700 | sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num); | |
3701 | ||
3702 | if (info->line < MAX_DEVICES) { | |
3703 | if (maxframe[info->line]) | |
3704 | info->max_frame_size = maxframe[info->line]; | |
1da177e4 LT |
3705 | } |
3706 | ||
3707 | synclinkmp_device_count++; | |
3708 | ||
3709 | if ( !synclinkmp_device_list ) | |
3710 | synclinkmp_device_list = info; | |
3711 | else { | |
3712 | SLMP_INFO *current_dev = synclinkmp_device_list; | |
3713 | while( current_dev->next_device ) | |
3714 | current_dev = current_dev->next_device; | |
3715 | current_dev->next_device = info; | |
3716 | } | |
3717 | ||
3718 | if ( info->max_frame_size < 4096 ) | |
3719 | info->max_frame_size = 4096; | |
3720 | else if ( info->max_frame_size > 65535 ) | |
3721 | info->max_frame_size = 65535; | |
3722 | ||
3723 | printk( "SyncLink MultiPort %s: " | |
3724 | "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n", | |
3725 | info->device_name, | |
3726 | info->phys_sca_base, | |
3727 | info->phys_memory_base, | |
3728 | info->phys_statctrl_base, | |
3729 | info->phys_lcr_base, | |
3730 | info->irq_level, | |
3731 | info->max_frame_size ); | |
3732 | ||
af69c7f9 | 3733 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
3734 | hdlcdev_init(info); |
3735 | #endif | |
3736 | } | |
3737 | ||
31f35939 AC |
3738 | static const struct tty_port_operations port_ops = { |
3739 | .carrier_raised = carrier_raised, | |
fcc8ac18 | 3740 | .dtr_rts = dtr_rts, |
31f35939 AC |
3741 | }; |
3742 | ||
1da177e4 LT |
3743 | /* Allocate and initialize a device instance structure |
3744 | * | |
3745 | * Return Value: pointer to SLMP_INFO if success, otherwise NULL | |
3746 | */ | |
3747 | static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev) | |
3748 | { | |
3749 | SLMP_INFO *info; | |
3750 | ||
dd00cc48 | 3751 | info = kzalloc(sizeof(SLMP_INFO), |
1da177e4 LT |
3752 | GFP_KERNEL); |
3753 | ||
3754 | if (!info) { | |
3755 | printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n", | |
3756 | __FILE__,__LINE__, adapter_num, port_num); | |
3757 | } else { | |
44b7d1b3 | 3758 | tty_port_init(&info->port); |
31f35939 | 3759 | info->port.ops = &port_ops; |
1da177e4 | 3760 | info->magic = MGSL_MAGIC; |
c4028958 | 3761 | INIT_WORK(&info->task, bh_handler); |
1da177e4 | 3762 | info->max_frame_size = 4096; |
44b7d1b3 AC |
3763 | info->port.close_delay = 5*HZ/10; |
3764 | info->port.closing_wait = 30*HZ; | |
1da177e4 LT |
3765 | init_waitqueue_head(&info->status_event_wait_q); |
3766 | init_waitqueue_head(&info->event_wait_q); | |
3767 | spin_lock_init(&info->netlock); | |
3768 | memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); | |
3769 | info->idle_mode = HDLC_TXIDLE_FLAGS; | |
3770 | info->adapter_num = adapter_num; | |
3771 | info->port_num = port_num; | |
3772 | ||
3773 | /* Copy configuration info to device instance data */ | |
3774 | info->irq_level = pdev->irq; | |
3775 | info->phys_lcr_base = pci_resource_start(pdev,0); | |
3776 | info->phys_sca_base = pci_resource_start(pdev,2); | |
3777 | info->phys_memory_base = pci_resource_start(pdev,3); | |
3778 | info->phys_statctrl_base = pci_resource_start(pdev,4); | |
3779 | ||
3780 | /* Because veremap only works on page boundaries we must map | |
3781 | * a larger area than is actually implemented for the LCR | |
3782 | * memory range. We map a full page starting at the page boundary. | |
3783 | */ | |
3784 | info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1); | |
3785 | info->phys_lcr_base &= ~(PAGE_SIZE-1); | |
3786 | ||
3787 | info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1); | |
3788 | info->phys_sca_base &= ~(PAGE_SIZE-1); | |
3789 | ||
3790 | info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1); | |
3791 | info->phys_statctrl_base &= ~(PAGE_SIZE-1); | |
3792 | ||
3793 | info->bus_type = MGSL_BUS_TYPE_PCI; | |
0f2ed4c6 | 3794 | info->irq_flags = IRQF_SHARED; |
1da177e4 | 3795 | |
40565f19 JS |
3796 | setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info); |
3797 | setup_timer(&info->status_timer, status_timeout, | |
3798 | (unsigned long)info); | |
1da177e4 LT |
3799 | |
3800 | /* Store the PCI9050 misc control register value because a flaw | |
3801 | * in the PCI9050 prevents LCR registers from being read if | |
3802 | * BIOS assigns an LCR base address with bit 7 set. | |
3803 | * | |
3804 | * Only the misc control register is accessed for which only | |
3805 | * write access is needed, so set an initial value and change | |
3806 | * bits to the device instance data as we write the value | |
3807 | * to the actual misc control register. | |
3808 | */ | |
3809 | info->misc_ctrl_value = 0x087e4546; | |
3810 | ||
3811 | /* initial port state is unknown - if startup errors | |
3812 | * occur, init_error will be set to indicate the | |
3813 | * problem. Once the port is fully initialized, | |
3814 | * this value will be set to 0 to indicate the | |
3815 | * port is available. | |
3816 | */ | |
3817 | info->init_error = -1; | |
3818 | } | |
3819 | ||
3820 | return info; | |
3821 | } | |
3822 | ||
ce9f9f73 | 3823 | static void device_init(int adapter_num, struct pci_dev *pdev) |
1da177e4 LT |
3824 | { |
3825 | SLMP_INFO *port_array[SCA_MAX_PORTS]; | |
3826 | int port; | |
3827 | ||
3828 | /* allocate device instances for up to SCA_MAX_PORTS devices */ | |
3829 | for ( port = 0; port < SCA_MAX_PORTS; ++port ) { | |
3830 | port_array[port] = alloc_dev(adapter_num,port,pdev); | |
3831 | if( port_array[port] == NULL ) { | |
191c5f10 JS |
3832 | for (--port; port >= 0; --port) { |
3833 | tty_port_destroy(&port_array[port]->port); | |
1da177e4 | 3834 | kfree(port_array[port]); |
191c5f10 | 3835 | } |
1da177e4 LT |
3836 | return; |
3837 | } | |
3838 | } | |
3839 | ||
3840 | /* give copy of port_array to all ports and add to device list */ | |
3841 | for ( port = 0; port < SCA_MAX_PORTS; ++port ) { | |
3842 | memcpy(port_array[port]->port_array,port_array,sizeof(port_array)); | |
3843 | add_device( port_array[port] ); | |
3844 | spin_lock_init(&port_array[port]->lock); | |
3845 | } | |
3846 | ||
3847 | /* Allocate and claim adapter resources */ | |
3848 | if ( !claim_resources(port_array[0]) ) { | |
3849 | ||
3850 | alloc_dma_bufs(port_array[0]); | |
3851 | ||
3852 | /* copy resource information from first port to others */ | |
3853 | for ( port = 1; port < SCA_MAX_PORTS; ++port ) { | |
3854 | port_array[port]->lock = port_array[0]->lock; | |
3855 | port_array[port]->irq_level = port_array[0]->irq_level; | |
3856 | port_array[port]->memory_base = port_array[0]->memory_base; | |
3857 | port_array[port]->sca_base = port_array[0]->sca_base; | |
3858 | port_array[port]->statctrl_base = port_array[0]->statctrl_base; | |
3859 | port_array[port]->lcr_base = port_array[0]->lcr_base; | |
3860 | alloc_dma_bufs(port_array[port]); | |
3861 | } | |
3862 | ||
3863 | if ( request_irq(port_array[0]->irq_level, | |
3864 | synclinkmp_interrupt, | |
3865 | port_array[0]->irq_flags, | |
3866 | port_array[0]->device_name, | |
3867 | port_array[0]) < 0 ) { | |
25985edc | 3868 | printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n", |
1da177e4 LT |
3869 | __FILE__,__LINE__, |
3870 | port_array[0]->device_name, | |
3871 | port_array[0]->irq_level ); | |
3872 | } | |
3873 | else { | |
0fab6de0 | 3874 | port_array[0]->irq_requested = true; |
1da177e4 LT |
3875 | adapter_test(port_array[0]); |
3876 | } | |
3877 | } | |
3878 | } | |
3879 | ||
b68e31d0 | 3880 | static const struct tty_operations ops = { |
ee3b48da | 3881 | .install = install, |
1da177e4 LT |
3882 | .open = open, |
3883 | .close = close, | |
3884 | .write = write, | |
3885 | .put_char = put_char, | |
3886 | .flush_chars = flush_chars, | |
3887 | .write_room = write_room, | |
3888 | .chars_in_buffer = chars_in_buffer, | |
3889 | .flush_buffer = flush_buffer, | |
3890 | .ioctl = ioctl, | |
3891 | .throttle = throttle, | |
3892 | .unthrottle = unthrottle, | |
3893 | .send_xchar = send_xchar, | |
3894 | .break_ctl = set_break, | |
3895 | .wait_until_sent = wait_until_sent, | |
1da177e4 LT |
3896 | .set_termios = set_termios, |
3897 | .stop = tx_hold, | |
3898 | .start = tx_release, | |
3899 | .hangup = hangup, | |
3900 | .tiocmget = tiocmget, | |
3901 | .tiocmset = tiocmset, | |
0587102c | 3902 | .get_icount = get_icount, |
e6c8dd8a | 3903 | .proc_fops = &synclinkmp_proc_fops, |
1da177e4 LT |
3904 | }; |
3905 | ||
31f35939 | 3906 | |
1da177e4 LT |
3907 | static void synclinkmp_cleanup(void) |
3908 | { | |
3909 | int rc; | |
3910 | SLMP_INFO *info; | |
3911 | SLMP_INFO *tmp; | |
3912 | ||
3913 | printk("Unloading %s %s\n", driver_name, driver_version); | |
3914 | ||
3915 | if (serial_driver) { | |
485e148d GKH |
3916 | rc = tty_unregister_driver(serial_driver); |
3917 | if (rc) | |
1da177e4 LT |
3918 | printk("%s(%d) failed to unregister tty driver err=%d\n", |
3919 | __FILE__,__LINE__,rc); | |
3920 | put_tty_driver(serial_driver); | |
3921 | } | |
3922 | ||
3923 | /* reset devices */ | |
3924 | info = synclinkmp_device_list; | |
3925 | while(info) { | |
3926 | reset_port(info); | |
3927 | info = info->next_device; | |
3928 | } | |
3929 | ||
3930 | /* release devices */ | |
3931 | info = synclinkmp_device_list; | |
3932 | while(info) { | |
af69c7f9 | 3933 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
3934 | hdlcdev_exit(info); |
3935 | #endif | |
3936 | free_dma_bufs(info); | |
3937 | free_tmp_rx_buf(info); | |
3938 | if ( info->port_num == 0 ) { | |
3939 | if (info->sca_base) | |
3940 | write_reg(info, LPR, 1); /* set low power mode */ | |
3941 | release_resources(info); | |
3942 | } | |
3943 | tmp = info; | |
3944 | info = info->next_device; | |
191c5f10 | 3945 | tty_port_destroy(&tmp->port); |
1da177e4 LT |
3946 | kfree(tmp); |
3947 | } | |
3948 | ||
3949 | pci_unregister_driver(&synclinkmp_pci_driver); | |
3950 | } | |
3951 | ||
3952 | /* Driver initialization entry point. | |
3953 | */ | |
3954 | ||
3955 | static int __init synclinkmp_init(void) | |
3956 | { | |
3957 | int rc; | |
3958 | ||
3959 | if (break_on_load) { | |
3960 | synclinkmp_get_text_ptr(); | |
3961 | BREAKPOINT(); | |
3962 | } | |
3963 | ||
3964 | printk("%s %s\n", driver_name, driver_version); | |
3965 | ||
3966 | if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) { | |
3967 | printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc); | |
3968 | return rc; | |
3969 | } | |
3970 | ||
3971 | serial_driver = alloc_tty_driver(128); | |
3972 | if (!serial_driver) { | |
3973 | rc = -ENOMEM; | |
3974 | goto error; | |
3975 | } | |
3976 | ||
3977 | /* Initialize the tty_driver structure */ | |
3978 | ||
1da177e4 LT |
3979 | serial_driver->driver_name = "synclinkmp"; |
3980 | serial_driver->name = "ttySLM"; | |
3981 | serial_driver->major = ttymajor; | |
3982 | serial_driver->minor_start = 64; | |
3983 | serial_driver->type = TTY_DRIVER_TYPE_SERIAL; | |
3984 | serial_driver->subtype = SERIAL_TYPE_NORMAL; | |
3985 | serial_driver->init_termios = tty_std_termios; | |
3986 | serial_driver->init_termios.c_cflag = | |
3987 | B9600 | CS8 | CREAD | HUPCL | CLOCAL; | |
606d099c AC |
3988 | serial_driver->init_termios.c_ispeed = 9600; |
3989 | serial_driver->init_termios.c_ospeed = 9600; | |
1da177e4 LT |
3990 | serial_driver->flags = TTY_DRIVER_REAL_RAW; |
3991 | tty_set_operations(serial_driver, &ops); | |
3992 | if ((rc = tty_register_driver(serial_driver)) < 0) { | |
3993 | printk("%s(%d):Couldn't register serial driver\n", | |
3994 | __FILE__,__LINE__); | |
3995 | put_tty_driver(serial_driver); | |
3996 | serial_driver = NULL; | |
3997 | goto error; | |
3998 | } | |
3999 | ||
4000 | printk("%s %s, tty major#%d\n", | |
4001 | driver_name, driver_version, | |
4002 | serial_driver->major); | |
4003 | ||
4004 | return 0; | |
4005 | ||
4006 | error: | |
4007 | synclinkmp_cleanup(); | |
4008 | return rc; | |
4009 | } | |
4010 | ||
4011 | static void __exit synclinkmp_exit(void) | |
4012 | { | |
4013 | synclinkmp_cleanup(); | |
4014 | } | |
4015 | ||
4016 | module_init(synclinkmp_init); | |
4017 | module_exit(synclinkmp_exit); | |
4018 | ||
4019 | /* Set the port for internal loopback mode. | |
4020 | * The TxCLK and RxCLK signals are generated from the BRG and | |
4021 | * the TxD is looped back to the RxD internally. | |
4022 | */ | |
ce9f9f73 | 4023 | static void enable_loopback(SLMP_INFO *info, int enable) |
1da177e4 LT |
4024 | { |
4025 | if (enable) { | |
4026 | /* MD2 (Mode Register 2) | |
4027 | * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback | |
4028 | */ | |
4029 | write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); | |
4030 | ||
4031 | /* degate external TxC clock source */ | |
4032 | info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); | |
4033 | write_control_reg(info); | |
4034 | ||
4035 | /* RXS/TXS (Rx/Tx clock source) | |
4036 | * 07 Reserved, must be 0 | |
4037 | * 06..04 Clock Source, 100=BRG | |
4038 | * 03..00 Clock Divisor, 0000=1 | |
4039 | */ | |
4040 | write_reg(info, RXS, 0x40); | |
4041 | write_reg(info, TXS, 0x40); | |
4042 | ||
4043 | } else { | |
4044 | /* MD2 (Mode Register 2) | |
4045 | * 01..00 CNCT<1..0> Channel connection, 0=normal | |
4046 | */ | |
4047 | write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); | |
4048 | ||
4049 | /* RXS/TXS (Rx/Tx clock source) | |
4050 | * 07 Reserved, must be 0 | |
4051 | * 06..04 Clock Source, 000=RxC/TxC Pin | |
4052 | * 03..00 Clock Divisor, 0000=1 | |
4053 | */ | |
4054 | write_reg(info, RXS, 0x00); | |
4055 | write_reg(info, TXS, 0x00); | |
4056 | } | |
4057 | ||
4058 | /* set LinkSpeed if available, otherwise default to 2Mbps */ | |
4059 | if (info->params.clock_speed) | |
4060 | set_rate(info, info->params.clock_speed); | |
4061 | else | |
4062 | set_rate(info, 3686400); | |
4063 | } | |
4064 | ||
4065 | /* Set the baud rate register to the desired speed | |
4066 | * | |
4067 | * data_rate data rate of clock in bits per second | |
4068 | * A data rate of 0 disables the AUX clock. | |
4069 | */ | |
ce9f9f73 | 4070 | static void set_rate( SLMP_INFO *info, u32 data_rate ) |
1da177e4 LT |
4071 | { |
4072 | u32 TMCValue; | |
4073 | unsigned char BRValue; | |
4074 | u32 Divisor=0; | |
4075 | ||
4076 | /* fBRG = fCLK/(TMC * 2^BR) | |
4077 | */ | |
4078 | if (data_rate != 0) { | |
4079 | Divisor = 14745600/data_rate; | |
4080 | if (!Divisor) | |
4081 | Divisor = 1; | |
4082 | ||
4083 | TMCValue = Divisor; | |
4084 | ||
4085 | BRValue = 0; | |
4086 | if (TMCValue != 1 && TMCValue != 2) { | |
4087 | /* BRValue of 0 provides 50/50 duty cycle *only* when | |
4088 | * TMCValue is 1 or 2. BRValue of 1 to 9 always provides | |
4089 | * 50/50 duty cycle. | |
4090 | */ | |
4091 | BRValue = 1; | |
4092 | TMCValue >>= 1; | |
4093 | } | |
4094 | ||
4095 | /* while TMCValue is too big for TMC register, divide | |
4096 | * by 2 and increment BR exponent. | |
4097 | */ | |
4098 | for(; TMCValue > 256 && BRValue < 10; BRValue++) | |
4099 | TMCValue >>= 1; | |
4100 | ||
4101 | write_reg(info, TXS, | |
4102 | (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue)); | |
4103 | write_reg(info, RXS, | |
4104 | (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue)); | |
4105 | write_reg(info, TMC, (unsigned char)TMCValue); | |
4106 | } | |
4107 | else { | |
4108 | write_reg(info, TXS,0); | |
4109 | write_reg(info, RXS,0); | |
4110 | write_reg(info, TMC, 0); | |
4111 | } | |
4112 | } | |
4113 | ||
4114 | /* Disable receiver | |
4115 | */ | |
ce9f9f73 | 4116 | static void rx_stop(SLMP_INFO *info) |
1da177e4 LT |
4117 | { |
4118 | if (debug_level >= DEBUG_LEVEL_ISR) | |
4119 | printk("%s(%d):%s rx_stop()\n", | |
4120 | __FILE__,__LINE__, info->device_name ); | |
4121 | ||
4122 | write_reg(info, CMD, RXRESET); | |
4123 | ||
4124 | info->ie0_value &= ~RXRDYE; | |
4125 | write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */ | |
4126 | ||
4127 | write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ | |
4128 | write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ | |
4129 | write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */ | |
4130 | ||
0fab6de0 JP |
4131 | info->rx_enabled = false; |
4132 | info->rx_overflow = false; | |
1da177e4 LT |
4133 | } |
4134 | ||
4135 | /* enable the receiver | |
4136 | */ | |
ce9f9f73 | 4137 | static void rx_start(SLMP_INFO *info) |
1da177e4 LT |
4138 | { |
4139 | int i; | |
4140 | ||
4141 | if (debug_level >= DEBUG_LEVEL_ISR) | |
4142 | printk("%s(%d):%s rx_start()\n", | |
4143 | __FILE__,__LINE__, info->device_name ); | |
4144 | ||
4145 | write_reg(info, CMD, RXRESET); | |
4146 | ||
4147 | if ( info->params.mode == MGSL_MODE_HDLC ) { | |
4148 | /* HDLC, disabe IRQ on rxdata */ | |
4149 | info->ie0_value &= ~RXRDYE; | |
4150 | write_reg(info, IE0, info->ie0_value); | |
4151 | ||
4152 | /* Reset all Rx DMA buffers and program rx dma */ | |
4153 | write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */ | |
4154 | write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */ | |
4155 | ||
4156 | for (i = 0; i < info->rx_buf_count; i++) { | |
4157 | info->rx_buf_list[i].status = 0xff; | |
4158 | ||
4159 | // throttle to 4 shared memory writes at a time to prevent | |
4160 | // hogging local bus (keep latency time for DMA requests low). | |
4161 | if (!(i % 4)) | |
4162 | read_status_reg(info); | |
4163 | } | |
4164 | info->current_rx_buf = 0; | |
4165 | ||
4166 | /* set current/1st descriptor address */ | |
4167 | write_reg16(info, RXDMA + CDA, | |
4168 | info->rx_buf_list_ex[0].phys_entry); | |
4169 | ||
4170 | /* set new last rx descriptor address */ | |
4171 | write_reg16(info, RXDMA + EDA, | |
4172 | info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry); | |
4173 | ||
4174 | /* set buffer length (shared by all rx dma data buffers) */ | |
4175 | write_reg16(info, RXDMA + BFL, SCABUFSIZE); | |
4176 | ||
4177 | write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */ | |
4178 | write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */ | |
4179 | } else { | |
4180 | /* async, enable IRQ on rxdata */ | |
4181 | info->ie0_value |= RXRDYE; | |
4182 | write_reg(info, IE0, info->ie0_value); | |
4183 | } | |
4184 | ||
4185 | write_reg(info, CMD, RXENABLE); | |
4186 | ||
0fab6de0 JP |
4187 | info->rx_overflow = false; |
4188 | info->rx_enabled = true; | |
1da177e4 LT |
4189 | } |
4190 | ||
4191 | /* Enable the transmitter and send a transmit frame if | |
4192 | * one is loaded in the DMA buffers. | |
4193 | */ | |
ce9f9f73 | 4194 | static void tx_start(SLMP_INFO *info) |
1da177e4 LT |
4195 | { |
4196 | if (debug_level >= DEBUG_LEVEL_ISR) | |
4197 | printk("%s(%d):%s tx_start() tx_count=%d\n", | |
4198 | __FILE__,__LINE__, info->device_name,info->tx_count ); | |
4199 | ||
4200 | if (!info->tx_enabled ) { | |
4201 | write_reg(info, CMD, TXRESET); | |
4202 | write_reg(info, CMD, TXENABLE); | |
0fab6de0 | 4203 | info->tx_enabled = true; |
1da177e4 LT |
4204 | } |
4205 | ||
4206 | if ( info->tx_count ) { | |
4207 | ||
4208 | /* If auto RTS enabled and RTS is inactive, then assert */ | |
4209 | /* RTS and set a flag indicating that the driver should */ | |
4210 | /* negate RTS when the transmission completes. */ | |
4211 | ||
0fab6de0 | 4212 | info->drop_rts_on_tx_done = false; |
1da177e4 LT |
4213 | |
4214 | if (info->params.mode != MGSL_MODE_ASYNC) { | |
4215 | ||
4216 | if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) { | |
4217 | get_signals( info ); | |
4218 | if ( !(info->serial_signals & SerialSignal_RTS) ) { | |
4219 | info->serial_signals |= SerialSignal_RTS; | |
4220 | set_signals( info ); | |
0fab6de0 | 4221 | info->drop_rts_on_tx_done = true; |
1da177e4 LT |
4222 | } |
4223 | } | |
4224 | ||
4225 | write_reg16(info, TRC0, | |
4226 | (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level)); | |
4227 | ||
4228 | write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ | |
4229 | write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ | |
4230 | ||
4231 | /* set TX CDA (current descriptor address) */ | |
4232 | write_reg16(info, TXDMA + CDA, | |
4233 | info->tx_buf_list_ex[0].phys_entry); | |
4234 | ||
4235 | /* set TX EDA (last descriptor address) */ | |
4236 | write_reg16(info, TXDMA + EDA, | |
4237 | info->tx_buf_list_ex[info->last_tx_buf].phys_entry); | |
4238 | ||
4239 | /* enable underrun IRQ */ | |
4240 | info->ie1_value &= ~IDLE; | |
4241 | info->ie1_value |= UDRN; | |
4242 | write_reg(info, IE1, info->ie1_value); | |
4243 | write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); | |
4244 | ||
4245 | write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */ | |
4246 | write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */ | |
4247 | ||
40565f19 JS |
4248 | mod_timer(&info->tx_timer, jiffies + |
4249 | msecs_to_jiffies(5000)); | |
1da177e4 LT |
4250 | } |
4251 | else { | |
4252 | tx_load_fifo(info); | |
4253 | /* async, enable IRQ on txdata */ | |
4254 | info->ie0_value |= TXRDYE; | |
4255 | write_reg(info, IE0, info->ie0_value); | |
4256 | } | |
4257 | ||
0fab6de0 | 4258 | info->tx_active = true; |
1da177e4 LT |
4259 | } |
4260 | } | |
4261 | ||
4262 | /* stop the transmitter and DMA | |
4263 | */ | |
ce9f9f73 | 4264 | static void tx_stop( SLMP_INFO *info ) |
1da177e4 LT |
4265 | { |
4266 | if (debug_level >= DEBUG_LEVEL_ISR) | |
4267 | printk("%s(%d):%s tx_stop()\n", | |
4268 | __FILE__,__LINE__, info->device_name ); | |
4269 | ||
4270 | del_timer(&info->tx_timer); | |
4271 | ||
4272 | write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */ | |
4273 | write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */ | |
4274 | ||
4275 | write_reg(info, CMD, TXRESET); | |
4276 | ||
4277 | info->ie1_value &= ~(UDRN + IDLE); | |
4278 | write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */ | |
4279 | write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */ | |
4280 | ||
4281 | info->ie0_value &= ~TXRDYE; | |
4282 | write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */ | |
4283 | ||
0fab6de0 JP |
4284 | info->tx_enabled = false; |
4285 | info->tx_active = false; | |
1da177e4 LT |
4286 | } |
4287 | ||
4288 | /* Fill the transmit FIFO until the FIFO is full or | |
4289 | * there is no more data to load. | |
4290 | */ | |
ce9f9f73 | 4291 | static void tx_load_fifo(SLMP_INFO *info) |
1da177e4 LT |
4292 | { |
4293 | u8 TwoBytes[2]; | |
4294 | ||
4295 | /* do nothing is now tx data available and no XON/XOFF pending */ | |
4296 | ||
4297 | if ( !info->tx_count && !info->x_char ) | |
4298 | return; | |
4299 | ||
4300 | /* load the Transmit FIFO until FIFOs full or all data sent */ | |
4301 | ||
4302 | while( info->tx_count && (read_reg(info,SR0) & BIT1) ) { | |
4303 | ||
4304 | /* there is more space in the transmit FIFO and */ | |
4305 | /* there is more data in transmit buffer */ | |
4306 | ||
4307 | if ( (info->tx_count > 1) && !info->x_char ) { | |
4308 | /* write 16-bits */ | |
4309 | TwoBytes[0] = info->tx_buf[info->tx_get++]; | |
4310 | if (info->tx_get >= info->max_frame_size) | |
4311 | info->tx_get -= info->max_frame_size; | |
4312 | TwoBytes[1] = info->tx_buf[info->tx_get++]; | |
4313 | if (info->tx_get >= info->max_frame_size) | |
4314 | info->tx_get -= info->max_frame_size; | |
4315 | ||
4316 | write_reg16(info, TRB, *((u16 *)TwoBytes)); | |
4317 | ||
4318 | info->tx_count -= 2; | |
4319 | info->icount.tx += 2; | |
4320 | } else { | |
4321 | /* only 1 byte left to transmit or 1 FIFO slot left */ | |
4322 | ||
4323 | if (info->x_char) { | |
4324 | /* transmit pending high priority char */ | |
4325 | write_reg(info, TRB, info->x_char); | |
4326 | info->x_char = 0; | |
4327 | } else { | |
4328 | write_reg(info, TRB, info->tx_buf[info->tx_get++]); | |
4329 | if (info->tx_get >= info->max_frame_size) | |
4330 | info->tx_get -= info->max_frame_size; | |
4331 | info->tx_count--; | |
4332 | } | |
4333 | info->icount.tx++; | |
4334 | } | |
4335 | } | |
4336 | } | |
4337 | ||
4338 | /* Reset a port to a known state | |
4339 | */ | |
ce9f9f73 | 4340 | static void reset_port(SLMP_INFO *info) |
1da177e4 LT |
4341 | { |
4342 | if (info->sca_base) { | |
4343 | ||
4344 | tx_stop(info); | |
4345 | rx_stop(info); | |
4346 | ||
9fe8074b | 4347 | info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); |
1da177e4 LT |
4348 | set_signals(info); |
4349 | ||
4350 | /* disable all port interrupts */ | |
4351 | info->ie0_value = 0; | |
4352 | info->ie1_value = 0; | |
4353 | info->ie2_value = 0; | |
4354 | write_reg(info, IE0, info->ie0_value); | |
4355 | write_reg(info, IE1, info->ie1_value); | |
4356 | write_reg(info, IE2, info->ie2_value); | |
4357 | ||
4358 | write_reg(info, CMD, CHRESET); | |
4359 | } | |
4360 | } | |
4361 | ||
4362 | /* Reset all the ports to a known state. | |
4363 | */ | |
ce9f9f73 | 4364 | static void reset_adapter(SLMP_INFO *info) |
1da177e4 LT |
4365 | { |
4366 | int i; | |
4367 | ||
4368 | for ( i=0; i < SCA_MAX_PORTS; ++i) { | |
4369 | if (info->port_array[i]) | |
4370 | reset_port(info->port_array[i]); | |
4371 | } | |
4372 | } | |
4373 | ||
4374 | /* Program port for asynchronous communications. | |
4375 | */ | |
ce9f9f73 | 4376 | static void async_mode(SLMP_INFO *info) |
1da177e4 LT |
4377 | { |
4378 | ||
4379 | unsigned char RegValue; | |
4380 | ||
4381 | tx_stop(info); | |
4382 | rx_stop(info); | |
4383 | ||
4384 | /* MD0, Mode Register 0 | |
4385 | * | |
4386 | * 07..05 PRCTL<2..0>, Protocol Mode, 000=async | |
4387 | * 04 AUTO, Auto-enable (RTS/CTS/DCD) | |
4388 | * 03 Reserved, must be 0 | |
4389 | * 02 CRCCC, CRC Calculation, 0=disabled | |
4390 | * 01..00 STOP<1..0> Stop bits (00=1,10=2) | |
4391 | * | |
4392 | * 0000 0000 | |
4393 | */ | |
4394 | RegValue = 0x00; | |
4395 | if (info->params.stop_bits != 1) | |
4396 | RegValue |= BIT1; | |
4397 | write_reg(info, MD0, RegValue); | |
4398 | ||
4399 | /* MD1, Mode Register 1 | |
4400 | * | |
4401 | * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64 | |
4402 | * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5 | |
4403 | * 03..02 RXCHR<1..0>, rx char size | |
4404 | * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd | |
4405 | * | |
4406 | * 0100 0000 | |
4407 | */ | |
4408 | RegValue = 0x40; | |
4409 | switch (info->params.data_bits) { | |
4410 | case 7: RegValue |= BIT4 + BIT2; break; | |
4411 | case 6: RegValue |= BIT5 + BIT3; break; | |
4412 | case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; | |
4413 | } | |
4414 | if (info->params.parity != ASYNC_PARITY_NONE) { | |
4415 | RegValue |= BIT1; | |
4416 | if (info->params.parity == ASYNC_PARITY_ODD) | |
4417 | RegValue |= BIT0; | |
4418 | } | |
4419 | write_reg(info, MD1, RegValue); | |
4420 | ||
4421 | /* MD2, Mode Register 2 | |
4422 | * | |
4423 | * 07..02 Reserved, must be 0 | |
6e8dcee3 | 4424 | * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback |
1da177e4 LT |
4425 | * |
4426 | * 0000 0000 | |
4427 | */ | |
4428 | RegValue = 0x00; | |
6e8dcee3 PF |
4429 | if (info->params.loopback) |
4430 | RegValue |= (BIT1 + BIT0); | |
1da177e4 LT |
4431 | write_reg(info, MD2, RegValue); |
4432 | ||
4433 | /* RXS, Receive clock source | |
4434 | * | |
4435 | * 07 Reserved, must be 0 | |
4436 | * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL | |
4437 | * 03..00 RXBR<3..0>, rate divisor, 0000=1 | |
4438 | */ | |
4439 | RegValue=BIT6; | |
4440 | write_reg(info, RXS, RegValue); | |
4441 | ||
4442 | /* TXS, Transmit clock source | |
4443 | * | |
4444 | * 07 Reserved, must be 0 | |
4445 | * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock | |
4446 | * 03..00 RXBR<3..0>, rate divisor, 0000=1 | |
4447 | */ | |
4448 | RegValue=BIT6; | |
4449 | write_reg(info, TXS, RegValue); | |
4450 | ||
4451 | /* Control Register | |
4452 | * | |
4453 | * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out | |
4454 | */ | |
4455 | info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); | |
4456 | write_control_reg(info); | |
4457 | ||
4458 | tx_set_idle(info); | |
4459 | ||
4460 | /* RRC Receive Ready Control 0 | |
4461 | * | |
4462 | * 07..05 Reserved, must be 0 | |
4463 | * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte | |
4464 | */ | |
4465 | write_reg(info, RRC, 0x00); | |
4466 | ||
4467 | /* TRC0 Transmit Ready Control 0 | |
4468 | * | |
4469 | * 07..05 Reserved, must be 0 | |
4470 | * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes | |
4471 | */ | |
4472 | write_reg(info, TRC0, 0x10); | |
4473 | ||
4474 | /* TRC1 Transmit Ready Control 1 | |
4475 | * | |
4476 | * 07..05 Reserved, must be 0 | |
4477 | * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1) | |
4478 | */ | |
4479 | write_reg(info, TRC1, 0x1e); | |
4480 | ||
4481 | /* CTL, MSCI control register | |
4482 | * | |
4483 | * 07..06 Reserved, set to 0 | |
4484 | * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC) | |
4485 | * 04 IDLC, idle control, 0=mark 1=idle register | |
4486 | * 03 BRK, break, 0=off 1 =on (async) | |
4487 | * 02 SYNCLD, sync char load enable (BSC) 1=enabled | |
4488 | * 01 GOP, go active on poll (LOOP mode) 1=enabled | |
4489 | * 00 RTS, RTS output control, 0=active 1=inactive | |
4490 | * | |
4491 | * 0001 0001 | |
4492 | */ | |
4493 | RegValue = 0x10; | |
4494 | if (!(info->serial_signals & SerialSignal_RTS)) | |
4495 | RegValue |= 0x01; | |
4496 | write_reg(info, CTL, RegValue); | |
4497 | ||
4498 | /* enable status interrupts */ | |
4499 | info->ie0_value |= TXINTE + RXINTE; | |
4500 | write_reg(info, IE0, info->ie0_value); | |
4501 | ||
4502 | /* enable break detect interrupt */ | |
4503 | info->ie1_value = BRKD; | |
4504 | write_reg(info, IE1, info->ie1_value); | |
4505 | ||
4506 | /* enable rx overrun interrupt */ | |
4507 | info->ie2_value = OVRN; | |
4508 | write_reg(info, IE2, info->ie2_value); | |
4509 | ||
4510 | set_rate( info, info->params.data_rate * 16 ); | |
1da177e4 LT |
4511 | } |
4512 | ||
4513 | /* Program the SCA for HDLC communications. | |
4514 | */ | |
ce9f9f73 | 4515 | static void hdlc_mode(SLMP_INFO *info) |
1da177e4 LT |
4516 | { |
4517 | unsigned char RegValue; | |
4518 | u32 DpllDivisor; | |
4519 | ||
4520 | // Can't use DPLL because SCA outputs recovered clock on RxC when | |
4521 | // DPLL mode selected. This causes output contention with RxC receiver. | |
4522 | // Use of DPLL would require external hardware to disable RxC receiver | |
4523 | // when DPLL mode selected. | |
4524 | info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL); | |
4525 | ||
4526 | /* disable DMA interrupts */ | |
4527 | write_reg(info, TXDMA + DIR, 0); | |
4528 | write_reg(info, RXDMA + DIR, 0); | |
4529 | ||
4530 | /* MD0, Mode Register 0 | |
4531 | * | |
4532 | * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC | |
4533 | * 04 AUTO, Auto-enable (RTS/CTS/DCD) | |
4534 | * 03 Reserved, must be 0 | |
4535 | * 02 CRCCC, CRC Calculation, 1=enabled | |
4536 | * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16 | |
4537 | * 00 CRC0, CRC initial value, 1 = all 1s | |
4538 | * | |
4539 | * 1000 0001 | |
4540 | */ | |
4541 | RegValue = 0x81; | |
4542 | if (info->params.flags & HDLC_FLAG_AUTO_CTS) | |
4543 | RegValue |= BIT4; | |
4544 | if (info->params.flags & HDLC_FLAG_AUTO_DCD) | |
4545 | RegValue |= BIT4; | |
4546 | if (info->params.crc_type == HDLC_CRC_16_CCITT) | |
4547 | RegValue |= BIT2 + BIT1; | |
4548 | write_reg(info, MD0, RegValue); | |
4549 | ||
4550 | /* MD1, Mode Register 1 | |
4551 | * | |
4552 | * 07..06 ADDRS<1..0>, Address detect, 00=no addr check | |
4553 | * 05..04 TXCHR<1..0>, tx char size, 00=8 bits | |
4554 | * 03..02 RXCHR<1..0>, rx char size, 00=8 bits | |
4555 | * 01..00 PMPM<1..0>, Parity mode, 00=no parity | |
4556 | * | |
4557 | * 0000 0000 | |
4558 | */ | |
4559 | RegValue = 0x00; | |
4560 | write_reg(info, MD1, RegValue); | |
4561 | ||
4562 | /* MD2, Mode Register 2 | |
4563 | * | |
4564 | * 07 NRZFM, 0=NRZ, 1=FM | |
4565 | * 06..05 CODE<1..0> Encoding, 00=NRZ | |
4566 | * 04..03 DRATE<1..0> DPLL Divisor, 00=8 | |
4567 | * 02 Reserved, must be 0 | |
4568 | * 01..00 CNCT<1..0> Channel connection, 0=normal | |
4569 | * | |
4570 | * 0000 0000 | |
4571 | */ | |
4572 | RegValue = 0x00; | |
4573 | switch(info->params.encoding) { | |
4574 | case HDLC_ENCODING_NRZI: RegValue |= BIT5; break; | |
4575 | case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */ | |
4576 | case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ | |
4577 | case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */ | |
4578 | #if 0 | |
4579 | case HDLC_ENCODING_NRZB: /* not supported */ | |
4580 | case HDLC_ENCODING_NRZI_MARK: /* not supported */ | |
4581 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */ | |
4582 | #endif | |
4583 | } | |
4584 | if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) { | |
4585 | DpllDivisor = 16; | |
4586 | RegValue |= BIT3; | |
4587 | } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) { | |
4588 | DpllDivisor = 8; | |
4589 | } else { | |
4590 | DpllDivisor = 32; | |
4591 | RegValue |= BIT4; | |
4592 | } | |
4593 | write_reg(info, MD2, RegValue); | |
4594 | ||
4595 | ||
4596 | /* RXS, Receive clock source | |
4597 | * | |
4598 | * 07 Reserved, must be 0 | |
4599 | * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL | |
4600 | * 03..00 RXBR<3..0>, rate divisor, 0000=1 | |
4601 | */ | |
4602 | RegValue=0; | |
4603 | if (info->params.flags & HDLC_FLAG_RXC_BRG) | |
4604 | RegValue |= BIT6; | |
4605 | if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
4606 | RegValue |= BIT6 + BIT5; | |
4607 | write_reg(info, RXS, RegValue); | |
4608 | ||
4609 | /* TXS, Transmit clock source | |
4610 | * | |
4611 | * 07 Reserved, must be 0 | |
4612 | * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock | |
4613 | * 03..00 RXBR<3..0>, rate divisor, 0000=1 | |
4614 | */ | |
4615 | RegValue=0; | |
4616 | if (info->params.flags & HDLC_FLAG_TXC_BRG) | |
4617 | RegValue |= BIT6; | |
4618 | if (info->params.flags & HDLC_FLAG_TXC_DPLL) | |
4619 | RegValue |= BIT6 + BIT5; | |
4620 | write_reg(info, TXS, RegValue); | |
4621 | ||
4622 | if (info->params.flags & HDLC_FLAG_RXC_DPLL) | |
4623 | set_rate(info, info->params.clock_speed * DpllDivisor); | |
4624 | else | |
4625 | set_rate(info, info->params.clock_speed); | |
4626 | ||
4627 | /* GPDATA (General Purpose I/O Data Register) | |
4628 | * | |
4629 | * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out | |
4630 | */ | |
4631 | if (info->params.flags & HDLC_FLAG_TXC_BRG) | |
4632 | info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); | |
4633 | else | |
4634 | info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2)); | |
4635 | write_control_reg(info); | |
4636 | ||
4637 | /* RRC Receive Ready Control 0 | |
4638 | * | |
4639 | * 07..05 Reserved, must be 0 | |
4640 | * 04..00 RRC<4..0> Rx FIFO trigger active | |
4641 | */ | |
4642 | write_reg(info, RRC, rx_active_fifo_level); | |
4643 | ||
4644 | /* TRC0 Transmit Ready Control 0 | |
4645 | * | |
4646 | * 07..05 Reserved, must be 0 | |
4647 | * 04..00 TRC<4..0> Tx FIFO trigger active | |
4648 | */ | |
4649 | write_reg(info, TRC0, tx_active_fifo_level); | |
4650 | ||
4651 | /* TRC1 Transmit Ready Control 1 | |
4652 | * | |
4653 | * 07..05 Reserved, must be 0 | |
4654 | * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full) | |
4655 | */ | |
4656 | write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1)); | |
4657 | ||
4658 | /* DMR, DMA Mode Register | |
4659 | * | |
4660 | * 07..05 Reserved, must be 0 | |
4661 | * 04 TMOD, Transfer Mode: 1=chained-block | |
4662 | * 03 Reserved, must be 0 | |
4663 | * 02 NF, Number of Frames: 1=multi-frame | |
4664 | * 01 CNTE, Frame End IRQ Counter enable: 0=disabled | |
4665 | * 00 Reserved, must be 0 | |
4666 | * | |
4667 | * 0001 0100 | |
4668 | */ | |
4669 | write_reg(info, TXDMA + DMR, 0x14); | |
4670 | write_reg(info, RXDMA + DMR, 0x14); | |
4671 | ||
4672 | /* Set chain pointer base (upper 8 bits of 24 bit addr) */ | |
4673 | write_reg(info, RXDMA + CPB, | |
4674 | (unsigned char)(info->buffer_list_phys >> 16)); | |
4675 | ||
4676 | /* Set chain pointer base (upper 8 bits of 24 bit addr) */ | |
4677 | write_reg(info, TXDMA + CPB, | |
4678 | (unsigned char)(info->buffer_list_phys >> 16)); | |
4679 | ||
4680 | /* enable status interrupts. other code enables/disables | |
4681 | * the individual sources for these two interrupt classes. | |
4682 | */ | |
4683 | info->ie0_value |= TXINTE + RXINTE; | |
4684 | write_reg(info, IE0, info->ie0_value); | |
4685 | ||
4686 | /* CTL, MSCI control register | |
4687 | * | |
4688 | * 07..06 Reserved, set to 0 | |
4689 | * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC) | |
4690 | * 04 IDLC, idle control, 0=mark 1=idle register | |
4691 | * 03 BRK, break, 0=off 1 =on (async) | |
4692 | * 02 SYNCLD, sync char load enable (BSC) 1=enabled | |
4693 | * 01 GOP, go active on poll (LOOP mode) 1=enabled | |
4694 | * 00 RTS, RTS output control, 0=active 1=inactive | |
4695 | * | |
4696 | * 0001 0001 | |
4697 | */ | |
4698 | RegValue = 0x10; | |
4699 | if (!(info->serial_signals & SerialSignal_RTS)) | |
4700 | RegValue |= 0x01; | |
4701 | write_reg(info, CTL, RegValue); | |
4702 | ||
4703 | /* preamble not supported ! */ | |
4704 | ||
4705 | tx_set_idle(info); | |
4706 | tx_stop(info); | |
4707 | rx_stop(info); | |
4708 | ||
4709 | set_rate(info, info->params.clock_speed); | |
4710 | ||
4711 | if (info->params.loopback) | |
4712 | enable_loopback(info,1); | |
4713 | } | |
4714 | ||
4715 | /* Set the transmit HDLC idle mode | |
4716 | */ | |
ce9f9f73 | 4717 | static void tx_set_idle(SLMP_INFO *info) |
1da177e4 LT |
4718 | { |
4719 | unsigned char RegValue = 0xff; | |
4720 | ||
4721 | /* Map API idle mode to SCA register bits */ | |
4722 | switch(info->idle_mode) { | |
4723 | case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break; | |
4724 | case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break; | |
4725 | case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break; | |
4726 | case HDLC_TXIDLE_ONES: RegValue = 0xff; break; | |
4727 | case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break; | |
4728 | case HDLC_TXIDLE_SPACE: RegValue = 0x00; break; | |
4729 | case HDLC_TXIDLE_MARK: RegValue = 0xff; break; | |
4730 | } | |
4731 | ||
4732 | write_reg(info, IDL, RegValue); | |
4733 | } | |
4734 | ||
4735 | /* Query the adapter for the state of the V24 status (input) signals. | |
4736 | */ | |
ce9f9f73 | 4737 | static void get_signals(SLMP_INFO *info) |
1da177e4 LT |
4738 | { |
4739 | u16 status = read_reg(info, SR3); | |
4740 | u16 gpstatus = read_status_reg(info); | |
4741 | u16 testbit; | |
4742 | ||
9fe8074b JP |
4743 | /* clear all serial signals except RTS and DTR */ |
4744 | info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR; | |
1da177e4 LT |
4745 | |
4746 | /* set serial signal bits to reflect MISR */ | |
4747 | ||
4748 | if (!(status & BIT3)) | |
4749 | info->serial_signals |= SerialSignal_CTS; | |
4750 | ||
4751 | if ( !(status & BIT2)) | |
4752 | info->serial_signals |= SerialSignal_DCD; | |
4753 | ||
4754 | testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7> | |
4755 | if (!(gpstatus & testbit)) | |
4756 | info->serial_signals |= SerialSignal_RI; | |
4757 | ||
4758 | testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6> | |
4759 | if (!(gpstatus & testbit)) | |
4760 | info->serial_signals |= SerialSignal_DSR; | |
4761 | } | |
4762 | ||
9fe8074b | 4763 | /* Set the state of RTS and DTR based on contents of |
1da177e4 LT |
4764 | * serial_signals member of device context. |
4765 | */ | |
ce9f9f73 | 4766 | static void set_signals(SLMP_INFO *info) |
1da177e4 LT |
4767 | { |
4768 | unsigned char RegValue; | |
4769 | u16 EnableBit; | |
4770 | ||
4771 | RegValue = read_reg(info, CTL); | |
4772 | if (info->serial_signals & SerialSignal_RTS) | |
4773 | RegValue &= ~BIT0; | |
4774 | else | |
4775 | RegValue |= BIT0; | |
4776 | write_reg(info, CTL, RegValue); | |
4777 | ||
4778 | // Port 0..3 DTR is ctrl reg <1,3,5,7> | |
4779 | EnableBit = BIT1 << (info->port_num*2); | |
4780 | if (info->serial_signals & SerialSignal_DTR) | |
4781 | info->port_array[0]->ctrlreg_value &= ~EnableBit; | |
4782 | else | |
4783 | info->port_array[0]->ctrlreg_value |= EnableBit; | |
4784 | write_control_reg(info); | |
4785 | } | |
4786 | ||
4787 | /*******************/ | |
4788 | /* DMA Buffer Code */ | |
4789 | /*******************/ | |
4790 | ||
4791 | /* Set the count for all receive buffers to SCABUFSIZE | |
4792 | * and set the current buffer to the first buffer. This effectively | |
4793 | * makes all buffers free and discards any data in buffers. | |
4794 | */ | |
ce9f9f73 | 4795 | static void rx_reset_buffers(SLMP_INFO *info) |
1da177e4 LT |
4796 | { |
4797 | rx_free_frame_buffers(info, 0, info->rx_buf_count - 1); | |
4798 | } | |
4799 | ||
4800 | /* Free the buffers used by a received frame | |
4801 | * | |
4802 | * info pointer to device instance data | |
4803 | * first index of 1st receive buffer of frame | |
4804 | * last index of last receive buffer of frame | |
4805 | */ | |
ce9f9f73 | 4806 | static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last) |
1da177e4 | 4807 | { |
0fab6de0 | 4808 | bool done = false; |
1da177e4 LT |
4809 | |
4810 | while(!done) { | |
4811 | /* reset current buffer for reuse */ | |
4812 | info->rx_buf_list[first].status = 0xff; | |
4813 | ||
4814 | if (first == last) { | |
0fab6de0 | 4815 | done = true; |
1da177e4 LT |
4816 | /* set new last rx descriptor address */ |
4817 | write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry); | |
4818 | } | |
4819 | ||
4820 | first++; | |
4821 | if (first == info->rx_buf_count) | |
4822 | first = 0; | |
4823 | } | |
4824 | ||
4825 | /* set current buffer to next buffer after last buffer of frame */ | |
4826 | info->current_rx_buf = first; | |
4827 | } | |
4828 | ||
4829 | /* Return a received frame from the receive DMA buffers. | |
4830 | * Only frames received without errors are returned. | |
4831 | * | |
0fab6de0 | 4832 | * Return Value: true if frame returned, otherwise false |
1da177e4 | 4833 | */ |
ce9f9f73 | 4834 | static bool rx_get_frame(SLMP_INFO *info) |
1da177e4 LT |
4835 | { |
4836 | unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */ | |
4837 | unsigned short status; | |
4838 | unsigned int framesize = 0; | |
0fab6de0 | 4839 | bool ReturnCode = false; |
1da177e4 | 4840 | unsigned long flags; |
8fb06c77 | 4841 | struct tty_struct *tty = info->port.tty; |
1da177e4 LT |
4842 | unsigned char addr_field = 0xff; |
4843 | SCADESC *desc; | |
4844 | SCADESC_EX *desc_ex; | |
4845 | ||
4846 | CheckAgain: | |
4847 | /* assume no frame returned, set zero length */ | |
4848 | framesize = 0; | |
4849 | addr_field = 0xff; | |
4850 | ||
4851 | /* | |
4852 | * current_rx_buf points to the 1st buffer of the next available | |
4853 | * receive frame. To find the last buffer of the frame look for | |
4854 | * a non-zero status field in the buffer entries. (The status | |
4855 | * field is set by the 16C32 after completing a receive frame. | |
4856 | */ | |
4857 | StartIndex = EndIndex = info->current_rx_buf; | |
4858 | ||
4859 | for ( ;; ) { | |
4860 | desc = &info->rx_buf_list[EndIndex]; | |
4861 | desc_ex = &info->rx_buf_list_ex[EndIndex]; | |
4862 | ||
4863 | if (desc->status == 0xff) | |
4864 | goto Cleanup; /* current desc still in use, no frames available */ | |
4865 | ||
4866 | if (framesize == 0 && info->params.addr_filter != 0xff) | |
4867 | addr_field = desc_ex->virt_addr[0]; | |
4868 | ||
4869 | framesize += desc->length; | |
4870 | ||
4871 | /* Status != 0 means last buffer of frame */ | |
4872 | if (desc->status) | |
4873 | break; | |
4874 | ||
4875 | EndIndex++; | |
4876 | if (EndIndex == info->rx_buf_count) | |
4877 | EndIndex = 0; | |
4878 | ||
4879 | if (EndIndex == info->current_rx_buf) { | |
4880 | /* all buffers have been 'used' but none mark */ | |
4881 | /* the end of a frame. Reset buffers and receiver. */ | |
4882 | if ( info->rx_enabled ){ | |
4883 | spin_lock_irqsave(&info->lock,flags); | |
4884 | rx_start(info); | |
4885 | spin_unlock_irqrestore(&info->lock,flags); | |
4886 | } | |
4887 | goto Cleanup; | |
4888 | } | |
4889 | ||
4890 | } | |
4891 | ||
4892 | /* check status of receive frame */ | |
4893 | ||
4894 | /* frame status is byte stored after frame data | |
4895 | * | |
4896 | * 7 EOM (end of msg), 1 = last buffer of frame | |
4897 | * 6 Short Frame, 1 = short frame | |
4898 | * 5 Abort, 1 = frame aborted | |
4899 | * 4 Residue, 1 = last byte is partial | |
4900 | * 3 Overrun, 1 = overrun occurred during frame reception | |
4901 | * 2 CRC, 1 = CRC error detected | |
4902 | * | |
4903 | */ | |
4904 | status = desc->status; | |
4905 | ||
4906 | /* ignore CRC bit if not using CRC (bit is undefined) */ | |
4907 | /* Note:CRC is not save to data buffer */ | |
4908 | if (info->params.crc_type == HDLC_CRC_NONE) | |
4909 | status &= ~BIT2; | |
4910 | ||
4911 | if (framesize == 0 || | |
4912 | (addr_field != 0xff && addr_field != info->params.addr_filter)) { | |
4913 | /* discard 0 byte frames, this seems to occur sometime | |
4914 | * when remote is idling flags. | |
4915 | */ | |
4916 | rx_free_frame_buffers(info, StartIndex, EndIndex); | |
4917 | goto CheckAgain; | |
4918 | } | |
4919 | ||
4920 | if (framesize < 2) | |
4921 | status |= BIT6; | |
4922 | ||
4923 | if (status & (BIT6+BIT5+BIT3+BIT2)) { | |
4924 | /* received frame has errors, | |
4925 | * update counts and mark frame size as 0 | |
4926 | */ | |
4927 | if (status & BIT6) | |
4928 | info->icount.rxshort++; | |
4929 | else if (status & BIT5) | |
4930 | info->icount.rxabort++; | |
4931 | else if (status & BIT3) | |
4932 | info->icount.rxover++; | |
4933 | else | |
4934 | info->icount.rxcrc++; | |
4935 | ||
4936 | framesize = 0; | |
af69c7f9 | 4937 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 | 4938 | { |
198191c4 KH |
4939 | info->netdev->stats.rx_errors++; |
4940 | info->netdev->stats.rx_frame_errors++; | |
1da177e4 LT |
4941 | } |
4942 | #endif | |
4943 | } | |
4944 | ||
4945 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
4946 | printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n", | |
4947 | __FILE__,__LINE__,info->device_name,status,framesize); | |
4948 | ||
4949 | if ( debug_level >= DEBUG_LEVEL_DATA ) | |
4950 | trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr, | |
53d785cc | 4951 | min_t(unsigned int, framesize, SCABUFSIZE), 0); |
1da177e4 LT |
4952 | |
4953 | if (framesize) { | |
4954 | if (framesize > info->max_frame_size) | |
4955 | info->icount.rxlong++; | |
4956 | else { | |
4957 | /* copy dma buffer(s) to contiguous intermediate buffer */ | |
4958 | int copy_count = framesize; | |
4959 | int index = StartIndex; | |
4960 | unsigned char *ptmp = info->tmp_rx_buf; | |
4961 | info->tmp_rx_buf_count = framesize; | |
4962 | ||
4963 | info->icount.rxok++; | |
4964 | ||
4965 | while(copy_count) { | |
4966 | int partial_count = min(copy_count,SCABUFSIZE); | |
4967 | memcpy( ptmp, | |
4968 | info->rx_buf_list_ex[index].virt_addr, | |
4969 | partial_count ); | |
4970 | ptmp += partial_count; | |
4971 | copy_count -= partial_count; | |
4972 | ||
4973 | if ( ++index == info->rx_buf_count ) | |
4974 | index = 0; | |
4975 | } | |
4976 | ||
af69c7f9 | 4977 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
4978 | if (info->netcount) |
4979 | hdlcdev_rx(info,info->tmp_rx_buf,framesize); | |
4980 | else | |
4981 | #endif | |
4982 | ldisc_receive_buf(tty,info->tmp_rx_buf, | |
4983 | info->flag_buf, framesize); | |
4984 | } | |
4985 | } | |
4986 | /* Free the buffers used by this frame. */ | |
4987 | rx_free_frame_buffers( info, StartIndex, EndIndex ); | |
4988 | ||
0fab6de0 | 4989 | ReturnCode = true; |
1da177e4 LT |
4990 | |
4991 | Cleanup: | |
4992 | if ( info->rx_enabled && info->rx_overflow ) { | |
4993 | /* Receiver is enabled, but needs to restarted due to | |
4994 | * rx buffer overflow. If buffers are empty, restart receiver. | |
4995 | */ | |
4996 | if (info->rx_buf_list[EndIndex].status == 0xff) { | |
4997 | spin_lock_irqsave(&info->lock,flags); | |
4998 | rx_start(info); | |
4999 | spin_unlock_irqrestore(&info->lock,flags); | |
5000 | } | |
5001 | } | |
5002 | ||
5003 | return ReturnCode; | |
5004 | } | |
5005 | ||
5006 | /* load the transmit DMA buffer with data | |
5007 | */ | |
ce9f9f73 | 5008 | static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count) |
1da177e4 LT |
5009 | { |
5010 | unsigned short copy_count; | |
5011 | unsigned int i = 0; | |
5012 | SCADESC *desc; | |
5013 | SCADESC_EX *desc_ex; | |
5014 | ||
5015 | if ( debug_level >= DEBUG_LEVEL_DATA ) | |
53d785cc | 5016 | trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1); |
1da177e4 LT |
5017 | |
5018 | /* Copy source buffer to one or more DMA buffers, starting with | |
5019 | * the first transmit dma buffer. | |
5020 | */ | |
5021 | for(i=0;;) | |
5022 | { | |
53d785cc | 5023 | copy_count = min_t(unsigned int, count, SCABUFSIZE); |
1da177e4 LT |
5024 | |
5025 | desc = &info->tx_buf_list[i]; | |
5026 | desc_ex = &info->tx_buf_list_ex[i]; | |
5027 | ||
5028 | load_pci_memory(info, desc_ex->virt_addr,buf,copy_count); | |
5029 | ||
5030 | desc->length = copy_count; | |
5031 | desc->status = 0; | |
5032 | ||
5033 | buf += copy_count; | |
5034 | count -= copy_count; | |
5035 | ||
5036 | if (!count) | |
5037 | break; | |
5038 | ||
5039 | i++; | |
5040 | if (i >= info->tx_buf_count) | |
5041 | i = 0; | |
5042 | } | |
5043 | ||
5044 | info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */ | |
5045 | info->last_tx_buf = ++i; | |
5046 | } | |
5047 | ||
ce9f9f73 | 5048 | static bool register_test(SLMP_INFO *info) |
1da177e4 LT |
5049 | { |
5050 | static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96}; | |
fe971071 | 5051 | static unsigned int count = ARRAY_SIZE(testval); |
1da177e4 | 5052 | unsigned int i; |
0fab6de0 | 5053 | bool rc = true; |
1da177e4 LT |
5054 | unsigned long flags; |
5055 | ||
5056 | spin_lock_irqsave(&info->lock,flags); | |
5057 | reset_port(info); | |
5058 | ||
5059 | /* assume failure */ | |
5060 | info->init_error = DiagStatus_AddressFailure; | |
5061 | ||
5062 | /* Write bit patterns to various registers but do it out of */ | |
5063 | /* sync, then read back and verify values. */ | |
5064 | ||
5065 | for (i = 0 ; i < count ; i++) { | |
5066 | write_reg(info, TMC, testval[i]); | |
5067 | write_reg(info, IDL, testval[(i+1)%count]); | |
5068 | write_reg(info, SA0, testval[(i+2)%count]); | |
5069 | write_reg(info, SA1, testval[(i+3)%count]); | |
5070 | ||
5071 | if ( (read_reg(info, TMC) != testval[i]) || | |
5072 | (read_reg(info, IDL) != testval[(i+1)%count]) || | |
5073 | (read_reg(info, SA0) != testval[(i+2)%count]) || | |
5074 | (read_reg(info, SA1) != testval[(i+3)%count]) ) | |
5075 | { | |
0fab6de0 | 5076 | rc = false; |
1da177e4 LT |
5077 | break; |
5078 | } | |
5079 | } | |
5080 | ||
5081 | reset_port(info); | |
5082 | spin_unlock_irqrestore(&info->lock,flags); | |
5083 | ||
5084 | return rc; | |
5085 | } | |
5086 | ||
ce9f9f73 | 5087 | static bool irq_test(SLMP_INFO *info) |
1da177e4 LT |
5088 | { |
5089 | unsigned long timeout; | |
5090 | unsigned long flags; | |
5091 | ||
5092 | unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0; | |
5093 | ||
5094 | spin_lock_irqsave(&info->lock,flags); | |
5095 | reset_port(info); | |
5096 | ||
5097 | /* assume failure */ | |
5098 | info->init_error = DiagStatus_IrqFailure; | |
0fab6de0 | 5099 | info->irq_occurred = false; |
1da177e4 LT |
5100 | |
5101 | /* setup timer0 on SCA0 to interrupt */ | |
5102 | ||
5103 | /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */ | |
5104 | write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4)); | |
5105 | ||
5106 | write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */ | |
5107 | write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */ | |
5108 | ||
5109 | ||
5110 | /* TMCS, Timer Control/Status Register | |
5111 | * | |
5112 | * 07 CMF, Compare match flag (read only) 1=match | |
5113 | * 06 ECMI, CMF Interrupt Enable: 1=enabled | |
5114 | * 05 Reserved, must be 0 | |
5115 | * 04 TME, Timer Enable | |
5116 | * 03..00 Reserved, must be 0 | |
5117 | * | |
5118 | * 0101 0000 | |
5119 | */ | |
5120 | write_reg(info, (unsigned char)(timer + TMCS), 0x50); | |
5121 | ||
5122 | spin_unlock_irqrestore(&info->lock,flags); | |
5123 | ||
5124 | timeout=100; | |
5125 | while( timeout-- && !info->irq_occurred ) { | |
5126 | msleep_interruptible(10); | |
5127 | } | |
5128 | ||
5129 | spin_lock_irqsave(&info->lock,flags); | |
5130 | reset_port(info); | |
5131 | spin_unlock_irqrestore(&info->lock,flags); | |
5132 | ||
5133 | return info->irq_occurred; | |
5134 | } | |
5135 | ||
5136 | /* initialize individual SCA device (2 ports) | |
5137 | */ | |
0fab6de0 | 5138 | static bool sca_init(SLMP_INFO *info) |
1da177e4 LT |
5139 | { |
5140 | /* set wait controller to single mem partition (low), no wait states */ | |
5141 | write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */ | |
5142 | write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */ | |
5143 | write_reg(info, WCRL, 0); /* wait controller low range */ | |
5144 | write_reg(info, WCRM, 0); /* wait controller mid range */ | |
5145 | write_reg(info, WCRH, 0); /* wait controller high range */ | |
5146 | ||
5147 | /* DPCR, DMA Priority Control | |
5148 | * | |
5149 | * 07..05 Not used, must be 0 | |
5150 | * 04 BRC, bus release condition: 0=all transfers complete | |
5151 | * 03 CCC, channel change condition: 0=every cycle | |
5152 | * 02..00 PR<2..0>, priority 100=round robin | |
5153 | * | |
5154 | * 00000100 = 0x04 | |
5155 | */ | |
5156 | write_reg(info, DPCR, dma_priority); | |
5157 | ||
5158 | /* DMA Master Enable, BIT7: 1=enable all channels */ | |
5159 | write_reg(info, DMER, 0x80); | |
5160 | ||
5161 | /* enable all interrupt classes */ | |
5162 | write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */ | |
5163 | write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */ | |
5164 | write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */ | |
5165 | ||
5166 | /* ITCR, interrupt control register | |
5167 | * 07 IPC, interrupt priority, 0=MSCI->DMA | |
5168 | * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle | |
5169 | * 04 VOS, Vector Output, 0=unmodified vector | |
5170 | * 03..00 Reserved, must be 0 | |
5171 | */ | |
5172 | write_reg(info, ITCR, 0); | |
5173 | ||
0fab6de0 | 5174 | return true; |
1da177e4 LT |
5175 | } |
5176 | ||
5177 | /* initialize adapter hardware | |
5178 | */ | |
ce9f9f73 | 5179 | static bool init_adapter(SLMP_INFO *info) |
1da177e4 LT |
5180 | { |
5181 | int i; | |
5182 | ||
5183 | /* Set BIT30 of Local Control Reg 0x50 to reset SCA */ | |
5184 | volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50); | |
5185 | u32 readval; | |
5186 | ||
5187 | info->misc_ctrl_value |= BIT30; | |
5188 | *MiscCtrl = info->misc_ctrl_value; | |
5189 | ||
5190 | /* | |
5191 | * Force at least 170ns delay before clearing | |
5192 | * reset bit. Each read from LCR takes at least | |
5193 | * 30ns so 10 times for 300ns to be safe. | |
5194 | */ | |
5195 | for(i=0;i<10;i++) | |
5196 | readval = *MiscCtrl; | |
5197 | ||
5198 | info->misc_ctrl_value &= ~BIT30; | |
5199 | *MiscCtrl = info->misc_ctrl_value; | |
5200 | ||
5201 | /* init control reg (all DTRs off, all clksel=input) */ | |
5202 | info->ctrlreg_value = 0xaa; | |
5203 | write_control_reg(info); | |
5204 | ||
5205 | { | |
5206 | volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c); | |
5207 | lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3); | |
5208 | ||
5209 | switch(read_ahead_count) | |
5210 | { | |
5211 | case 16: | |
5212 | lcr1_brdr_value |= BIT5 + BIT4 + BIT3; | |
5213 | break; | |
5214 | case 8: | |
5215 | lcr1_brdr_value |= BIT5 + BIT4; | |
5216 | break; | |
5217 | case 4: | |
5218 | lcr1_brdr_value |= BIT5 + BIT3; | |
5219 | break; | |
5220 | case 0: | |
5221 | lcr1_brdr_value |= BIT5; | |
5222 | break; | |
5223 | } | |
5224 | ||
5225 | *LCR1BRDR = lcr1_brdr_value; | |
5226 | *MiscCtrl = misc_ctrl_value; | |
5227 | } | |
5228 | ||
5229 | sca_init(info->port_array[0]); | |
5230 | sca_init(info->port_array[2]); | |
5231 | ||
0fab6de0 | 5232 | return true; |
1da177e4 LT |
5233 | } |
5234 | ||
5235 | /* Loopback an HDLC frame to test the hardware | |
5236 | * interrupt and DMA functions. | |
5237 | */ | |
ce9f9f73 | 5238 | static bool loopback_test(SLMP_INFO *info) |
1da177e4 LT |
5239 | { |
5240 | #define TESTFRAMESIZE 20 | |
5241 | ||
5242 | unsigned long timeout; | |
5243 | u16 count = TESTFRAMESIZE; | |
5244 | unsigned char buf[TESTFRAMESIZE]; | |
0fab6de0 | 5245 | bool rc = false; |
1da177e4 LT |
5246 | unsigned long flags; |
5247 | ||
8fb06c77 | 5248 | struct tty_struct *oldtty = info->port.tty; |
1da177e4 LT |
5249 | u32 speed = info->params.clock_speed; |
5250 | ||
5251 | info->params.clock_speed = 3686400; | |
8fb06c77 | 5252 | info->port.tty = NULL; |
1da177e4 LT |
5253 | |
5254 | /* assume failure */ | |
5255 | info->init_error = DiagStatus_DmaFailure; | |
5256 | ||
5257 | /* build and send transmit frame */ | |
5258 | for (count = 0; count < TESTFRAMESIZE;++count) | |
5259 | buf[count] = (unsigned char)count; | |
5260 | ||
5261 | memset(info->tmp_rx_buf,0,TESTFRAMESIZE); | |
5262 | ||
5263 | /* program hardware for HDLC and enabled receiver */ | |
5264 | spin_lock_irqsave(&info->lock,flags); | |
5265 | hdlc_mode(info); | |
5266 | enable_loopback(info,1); | |
5267 | rx_start(info); | |
5268 | info->tx_count = count; | |
5269 | tx_load_dma_buffer(info,buf,count); | |
5270 | tx_start(info); | |
5271 | spin_unlock_irqrestore(&info->lock,flags); | |
5272 | ||
5273 | /* wait for receive complete */ | |
5274 | /* Set a timeout for waiting for interrupt. */ | |
5275 | for ( timeout = 100; timeout; --timeout ) { | |
5276 | msleep_interruptible(10); | |
5277 | ||
5278 | if (rx_get_frame(info)) { | |
0fab6de0 | 5279 | rc = true; |
1da177e4 LT |
5280 | break; |
5281 | } | |
5282 | } | |
5283 | ||
5284 | /* verify received frame length and contents */ | |
0fab6de0 JP |
5285 | if (rc && |
5286 | ( info->tmp_rx_buf_count != count || | |
5287 | memcmp(buf, info->tmp_rx_buf,count))) { | |
5288 | rc = false; | |
1da177e4 LT |
5289 | } |
5290 | ||
5291 | spin_lock_irqsave(&info->lock,flags); | |
5292 | reset_adapter(info); | |
5293 | spin_unlock_irqrestore(&info->lock,flags); | |
5294 | ||
5295 | info->params.clock_speed = speed; | |
8fb06c77 | 5296 | info->port.tty = oldtty; |
1da177e4 LT |
5297 | |
5298 | return rc; | |
5299 | } | |
5300 | ||
5301 | /* Perform diagnostics on hardware | |
5302 | */ | |
ce9f9f73 | 5303 | static int adapter_test( SLMP_INFO *info ) |
1da177e4 LT |
5304 | { |
5305 | unsigned long flags; | |
5306 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
5307 | printk( "%s(%d):Testing device %s\n", | |
5308 | __FILE__,__LINE__,info->device_name ); | |
5309 | ||
5310 | spin_lock_irqsave(&info->lock,flags); | |
5311 | init_adapter(info); | |
5312 | spin_unlock_irqrestore(&info->lock,flags); | |
5313 | ||
5314 | info->port_array[0]->port_count = 0; | |
5315 | ||
5316 | if ( register_test(info->port_array[0]) && | |
5317 | register_test(info->port_array[1])) { | |
5318 | ||
5319 | info->port_array[0]->port_count = 2; | |
5320 | ||
5321 | if ( register_test(info->port_array[2]) && | |
5322 | register_test(info->port_array[3]) ) | |
5323 | info->port_array[0]->port_count += 2; | |
5324 | } | |
5325 | else { | |
5326 | printk( "%s(%d):Register test failure for device %s Addr=%08lX\n", | |
5327 | __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base)); | |
5328 | return -ENODEV; | |
5329 | } | |
5330 | ||
5331 | if ( !irq_test(info->port_array[0]) || | |
5332 | !irq_test(info->port_array[1]) || | |
5333 | (info->port_count == 4 && !irq_test(info->port_array[2])) || | |
5334 | (info->port_count == 4 && !irq_test(info->port_array[3]))) { | |
5335 | printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n", | |
5336 | __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) ); | |
5337 | return -ENODEV; | |
5338 | } | |
5339 | ||
5340 | if (!loopback_test(info->port_array[0]) || | |
5341 | !loopback_test(info->port_array[1]) || | |
5342 | (info->port_count == 4 && !loopback_test(info->port_array[2])) || | |
5343 | (info->port_count == 4 && !loopback_test(info->port_array[3]))) { | |
5344 | printk( "%s(%d):DMA test failure for device %s\n", | |
5345 | __FILE__,__LINE__,info->device_name); | |
5346 | return -ENODEV; | |
5347 | } | |
5348 | ||
5349 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
5350 | printk( "%s(%d):device %s passed diagnostics\n", | |
5351 | __FILE__,__LINE__,info->device_name ); | |
5352 | ||
5353 | info->port_array[0]->init_error = 0; | |
5354 | info->port_array[1]->init_error = 0; | |
5355 | if ( info->port_count > 2 ) { | |
5356 | info->port_array[2]->init_error = 0; | |
5357 | info->port_array[3]->init_error = 0; | |
5358 | } | |
5359 | ||
5360 | return 0; | |
5361 | } | |
5362 | ||
5363 | /* Test the shared memory on a PCI adapter. | |
5364 | */ | |
ce9f9f73 | 5365 | static bool memory_test(SLMP_INFO *info) |
1da177e4 LT |
5366 | { |
5367 | static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa, | |
5368 | 0x66666666, 0x99999999, 0xffffffff, 0x12345678 }; | |
fe971071 | 5369 | unsigned long count = ARRAY_SIZE(testval); |
1da177e4 LT |
5370 | unsigned long i; |
5371 | unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long); | |
5372 | unsigned long * addr = (unsigned long *)info->memory_base; | |
5373 | ||
5374 | /* Test data lines with test pattern at one location. */ | |
5375 | ||
5376 | for ( i = 0 ; i < count ; i++ ) { | |
5377 | *addr = testval[i]; | |
5378 | if ( *addr != testval[i] ) | |
0fab6de0 | 5379 | return false; |
1da177e4 LT |
5380 | } |
5381 | ||
5382 | /* Test address lines with incrementing pattern over */ | |
5383 | /* entire address range. */ | |
5384 | ||
5385 | for ( i = 0 ; i < limit ; i++ ) { | |
5386 | *addr = i * 4; | |
5387 | addr++; | |
5388 | } | |
5389 | ||
5390 | addr = (unsigned long *)info->memory_base; | |
5391 | ||
5392 | for ( i = 0 ; i < limit ; i++ ) { | |
5393 | if ( *addr != i * 4 ) | |
0fab6de0 | 5394 | return false; |
1da177e4 LT |
5395 | addr++; |
5396 | } | |
5397 | ||
5398 | memset( info->memory_base, 0, SCA_MEM_SIZE ); | |
0fab6de0 | 5399 | return true; |
1da177e4 LT |
5400 | } |
5401 | ||
5402 | /* Load data into PCI adapter shared memory. | |
5403 | * | |
5404 | * The PCI9050 releases control of the local bus | |
5405 | * after completing the current read or write operation. | |
5406 | * | |
5407 | * While the PCI9050 write FIFO not empty, the | |
5408 | * PCI9050 treats all of the writes as a single transaction | |
5409 | * and does not release the bus. This causes DMA latency problems | |
5410 | * at high speeds when copying large data blocks to the shared memory. | |
5411 | * | |
5412 | * This function breaks a write into multiple transations by | |
5413 | * interleaving a read which flushes the write FIFO and 'completes' | |
5414 | * the write transation. This allows any pending DMA request to gain control | |
5415 | * of the local bus in a timely fasion. | |
5416 | */ | |
ce9f9f73 | 5417 | static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count) |
1da177e4 LT |
5418 | { |
5419 | /* A load interval of 16 allows for 4 32-bit writes at */ | |
5420 | /* 136ns each for a maximum latency of 542ns on the local bus.*/ | |
5421 | ||
5422 | unsigned short interval = count / sca_pci_load_interval; | |
5423 | unsigned short i; | |
5424 | ||
5425 | for ( i = 0 ; i < interval ; i++ ) | |
5426 | { | |
5427 | memcpy(dest, src, sca_pci_load_interval); | |
5428 | read_status_reg(info); | |
5429 | dest += sca_pci_load_interval; | |
5430 | src += sca_pci_load_interval; | |
5431 | } | |
5432 | ||
5433 | memcpy(dest, src, count % sca_pci_load_interval); | |
5434 | } | |
5435 | ||
ce9f9f73 | 5436 | static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit) |
1da177e4 LT |
5437 | { |
5438 | int i; | |
5439 | int linecount; | |
5440 | if (xmit) | |
5441 | printk("%s tx data:\n",info->device_name); | |
5442 | else | |
5443 | printk("%s rx data:\n",info->device_name); | |
5444 | ||
5445 | while(count) { | |
5446 | if (count > 16) | |
5447 | linecount = 16; | |
5448 | else | |
5449 | linecount = count; | |
5450 | ||
5451 | for(i=0;i<linecount;i++) | |
5452 | printk("%02X ",(unsigned char)data[i]); | |
5453 | for(;i<17;i++) | |
5454 | printk(" "); | |
5455 | for(i=0;i<linecount;i++) { | |
5456 | if (data[i]>=040 && data[i]<=0176) | |
5457 | printk("%c",data[i]); | |
5458 | else | |
5459 | printk("."); | |
5460 | } | |
5461 | printk("\n"); | |
5462 | ||
5463 | data += linecount; | |
5464 | count -= linecount; | |
5465 | } | |
5466 | } /* end of trace_block() */ | |
5467 | ||
5468 | /* called when HDLC frame times out | |
5469 | * update stats and do tx completion processing | |
5470 | */ | |
ce9f9f73 | 5471 | static void tx_timeout(unsigned long context) |
1da177e4 LT |
5472 | { |
5473 | SLMP_INFO *info = (SLMP_INFO*)context; | |
5474 | unsigned long flags; | |
5475 | ||
5476 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
5477 | printk( "%s(%d):%s tx_timeout()\n", | |
5478 | __FILE__,__LINE__,info->device_name); | |
5479 | if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) { | |
5480 | info->icount.txtimeout++; | |
5481 | } | |
5482 | spin_lock_irqsave(&info->lock,flags); | |
0fab6de0 | 5483 | info->tx_active = false; |
1da177e4 LT |
5484 | info->tx_count = info->tx_put = info->tx_get = 0; |
5485 | ||
5486 | spin_unlock_irqrestore(&info->lock,flags); | |
5487 | ||
af69c7f9 | 5488 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
5489 | if (info->netcount) |
5490 | hdlcdev_tx_done(info); | |
5491 | else | |
5492 | #endif | |
5493 | bh_transmit(info); | |
5494 | } | |
5495 | ||
5496 | /* called to periodically check the DSR/RI modem signal input status | |
5497 | */ | |
ce9f9f73 | 5498 | static void status_timeout(unsigned long context) |
1da177e4 LT |
5499 | { |
5500 | u16 status = 0; | |
5501 | SLMP_INFO *info = (SLMP_INFO*)context; | |
5502 | unsigned long flags; | |
5503 | unsigned char delta; | |
5504 | ||
5505 | ||
5506 | spin_lock_irqsave(&info->lock,flags); | |
5507 | get_signals(info); | |
5508 | spin_unlock_irqrestore(&info->lock,flags); | |
5509 | ||
5510 | /* check for DSR/RI state change */ | |
5511 | ||
5512 | delta = info->old_signals ^ info->serial_signals; | |
5513 | info->old_signals = info->serial_signals; | |
5514 | ||
5515 | if (delta & SerialSignal_DSR) | |
5516 | status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR); | |
5517 | ||
5518 | if (delta & SerialSignal_RI) | |
5519 | status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI); | |
5520 | ||
5521 | if (delta & SerialSignal_DCD) | |
5522 | status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD); | |
5523 | ||
5524 | if (delta & SerialSignal_CTS) | |
5525 | status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS); | |
5526 | ||
5527 | if (status) | |
5528 | isr_io_pin(info,status); | |
5529 | ||
40565f19 | 5530 | mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10)); |
1da177e4 LT |
5531 | } |
5532 | ||
5533 | ||
5534 | /* Register Access Routines - | |
5535 | * All registers are memory mapped | |
5536 | */ | |
5537 | #define CALC_REGADDR() \ | |
5538 | unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \ | |
5539 | if (info->port_num > 1) \ | |
5540 | RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \ | |
5541 | if ( info->port_num & 1) { \ | |
5542 | if (Addr > 0x7f) \ | |
5543 | RegAddr += 0x40; /* DMA access */ \ | |
5544 | else if (Addr > 0x1f && Addr < 0x60) \ | |
5545 | RegAddr += 0x20; /* MSCI access */ \ | |
5546 | } | |
5547 | ||
5548 | ||
ce9f9f73 | 5549 | static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr) |
1da177e4 LT |
5550 | { |
5551 | CALC_REGADDR(); | |
5552 | return *RegAddr; | |
5553 | } | |
ce9f9f73 | 5554 | static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value) |
1da177e4 LT |
5555 | { |
5556 | CALC_REGADDR(); | |
5557 | *RegAddr = Value; | |
5558 | } | |
5559 | ||
ce9f9f73 | 5560 | static u16 read_reg16(SLMP_INFO * info, unsigned char Addr) |
1da177e4 LT |
5561 | { |
5562 | CALC_REGADDR(); | |
5563 | return *((u16 *)RegAddr); | |
5564 | } | |
5565 | ||
ce9f9f73 | 5566 | static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value) |
1da177e4 LT |
5567 | { |
5568 | CALC_REGADDR(); | |
5569 | *((u16 *)RegAddr) = Value; | |
5570 | } | |
5571 | ||
ce9f9f73 | 5572 | static unsigned char read_status_reg(SLMP_INFO * info) |
1da177e4 LT |
5573 | { |
5574 | unsigned char *RegAddr = (unsigned char *)info->statctrl_base; | |
5575 | return *RegAddr; | |
5576 | } | |
5577 | ||
ce9f9f73 | 5578 | static void write_control_reg(SLMP_INFO * info) |
1da177e4 LT |
5579 | { |
5580 | unsigned char *RegAddr = (unsigned char *)info->statctrl_base; | |
5581 | *RegAddr = info->port_array[0]->ctrlreg_value; | |
5582 | } | |
5583 | ||
5584 | ||
9671f099 | 5585 | static int synclinkmp_init_one (struct pci_dev *dev, |
1da177e4 LT |
5586 | const struct pci_device_id *ent) |
5587 | { | |
5588 | if (pci_enable_device(dev)) { | |
5589 | printk("error enabling pci device %p\n", dev); | |
5590 | return -EIO; | |
5591 | } | |
5592 | device_init( ++synclinkmp_adapter_count, dev ); | |
5593 | return 0; | |
5594 | } | |
5595 | ||
ae8d8a14 | 5596 | static void synclinkmp_remove_one (struct pci_dev *dev) |
1da177e4 LT |
5597 | { |
5598 | } |